tm TE CH T15M256B SRAM 32K X 8 LOW POWER CMOS STATIC RAM FEATURES GENERAL DESCRIPTION • High speed access time: 45/50/70/85/100ns The T15M256B is a low power CMOS static RAM. organized as 32,768 x 8 bits that operates on a single 5-volt power supply. Low operating and standby current . Data retention is guaranteed at a power supply voltage as low as 1.5V. This device is packaged in a standard 28-pin DIP(600mil), SOJ, SOP, TSOP-I forward and reverse type. • Low power supply current : - Operating :37mA(max) - Standby : 10uA • Power supply : 5V (± 10%) • Fully static operation – No clock or refreshing required • All inputs and outputs directly LVTTL compatible BLOCK DIAGRAM • Common I/O capability • Data retention voltage : 1.5V (min) • Available packages : 28-pin DIP(600mil),SOJ, SOP/lead-free, TSOP-I (8x13.4mm forward type and reverse type). • Operating temperature : - Vcc → Vss → A0 → 0 ~ +70 °C -40 ~ +85 °C . . . DECODER CORE ARRAY A14 → PART NUMBER EXAMPLES PART NO. PACKAGE CODE T15M256B-70N N=DIP T15M256B-70J J=SOJ T15M256B-70D D=SOP T15M256B-85P P= TSOP-I(Forward) T15M256B-85R R= TSOP-I(Reverse) T15M256B-70DG D=SOP/lead-free T15M256B-70NI N=DIP T15M256B-70JI J=SOJ T15M256B-70DI D=SOP T15M256B-85PI P= TSOP-I(Forward) T15M256B-85RI R= TSOP-I(Reverse) Operating Temperature CS → OE → CONTROL WE → ← I / O1 DATA I/O . . ← I / O8 0 ~ +70 °C -40 ~ +85 °C TM Technology Inc. reserves the right to change products or specifications without notice. P. 1 Publication Date: OCT. 2003 Revision:C tm TE CH T15M256B PIN CONFIGURATION A 14 1 28 V cc A14 1 28 Vcc A 12 2 27 WE A12 2 27 WE A7 3 26 A 13 A7 3 26 A13 A6 4 25 A8 A6 4 25 A8 A5 5 24 A9 A4 6 23 A 11 A5 A4 5 6 24 23 A9 A11 A3 7 22 OE A3 7 22 OE A2 8 21 A 10 A2 8 A1 9 20 CS A1 D IP & SO J SOP 21 A10 9 20 CS A0 10 19 I/O 8 A0 10 19 I/O8 I/O 1 11 18 I/O 7 I/O1 11 18 I/O7 I/O 2 12 17 I/O 6 I/O2 12 17 I/O6 I/O 3 13 16 I/O 5 I/O3 13 16 I/O5 V ss 14 15 I/O 4 Vss 14 15 I/O4 OE A11 A9 A8 A13 WE VCC A14 A12 A7 A6 A5 A4 A3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 TSOP-I Forward 28 27 26 25 24 23 22 21 20 19 18 17 16 15 A10 CS I/O8 I/O7 I/O6 I/O5 I/O4 VSS I/O3 I/O2 I/O1 A0 A1 A2 A3 A4 A5 A6 A7 A12 A14 VCC WE A13 A8 A9 A11 OE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 TSOP-I Reverse 28 27 26 25 24 23 22 21 20 19 18 17 16 15 A2 A1 A0 I/O1 I/O2 I/O3 VSS I/O4 I/O5 I/O6 I/O7 I/O8 CS A10 PIN DESCRIPTION SYMBOL A0 - A14 I/O1 - I/O8 CS WE OE Vcc Vss DESCRIPTION Address Inputs Data Inputs/Outputs Chip Select Inputs Write Enable Output Enable Power Supply Ground TM Technology Inc. reserves the right to change products or specifications without notice. P. 2 Publication Date: OCT. 2003 Revision:C tm TE CH T15M256B DC CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS PARAMETER Supply Voltage to Vss Potential Inputs to Vss Potential Power Dissipation Storage Temperature RATING -0.5 to + 7V -0.5 to Vcc +0.5 0.7 -60 to +150 UNIT V V W °C RECOMMENDED OPERATING CONDITIONS PARAMETER Supply Voltage Input Voltage, low Input Voltage, high Ambient Temperature SYM Vcc MIN 4.5 -0.3 2.2 0/-40 VIL VIH TA TYP 5 - MAX 5.5 0.8 Vcc+0.3 +70/+85 UNIT V V V °C TRUTH TABLE CS H L L OE X H L WE X H H MODE Not Selected Output Disable Read I/O1- I/O8 High-Z High-Z Data Out Power Standby Active L X L Write Data In Active Active OPERATING CHARACTERISTICS (Vcc = 5V / ± 10%, Vss = 0V, Ta = 0 ~ +70 °C /-40 to 85°C) PARAMETER Input Leakage Current SYM. I LI Output Leakage Current I LO Output Low Voltage Output High Voltage VOL VOH TEST CONDITIONS Vin=Vss to Vcc VI/O=Vss to Vcc , CS = VIH or OE = VIH or WE = VIL I OL = + 2.1mA I OH = - 1.0mA CS = VIL , I/O=0mA Operating Power Supply Current Standby Power Supply Current Icc Cycle = MIN. Duty = 100% -45 -50 -70 -85 -100 MIN. TYP. MAX. UNIT 1 uA - - 1 uA 2.4 - - 0.4 37 35 30 25 V V mA mA mA mA - - 20 mA I SB CS = VIH , Cycle=min, Duty=100% - - 0.3 mA I SB1 CS ≥ Vcc -0.2V - - 10 uA TM Technology Inc. reserves the right to change products or specifications without notice. P. 3 Publication Date: OCT. 2003 Revision:C tm TE CH T15M256B CAPACITANCE (Vcc = 5V / ± 10%, Ta = 25°C, f = 1 MHz) PARAMETER Input Capacitance Input/ Output Capacitance SYMBOL CONDITION VIN = 0V VOUT = 0V C IN C I/O MAX. 6 8 UNIT pF pF Note: These parameters are sampled but not 100% tested. AC TEST CONDITIONS PARAMETER CONDITIONS Input Pulse Levels Input Rise and Fall Times Input and Output Timing Reference Level Output Load 0V to 3V 3 ns 1.5V See Fig. 1,2 AC TEST LOADS AND WAVEFORM 5V R1 - 1928 ohm 5V R1- 1928 ohm OUTPUT OUTPUT 30pF Including Jig and Scope R2 1020 ohm 5pF Including Jig and Scope R2 1020 ohm (For T C L Z , T O LZ , T C H Z , T O H Z , T W H Z , T O W ) Fig 2 Fig 1 TM Technology Inc. reserves the right to change products or specifications without notice. P. 4 Publication Date: OCT. 2003 Revision:C tm TE CH T15M256B AC CHARACTERISTICS ( Vcc = 5V / ± 10%, Vss = 0V, Ta =0 ~ +70 °C/ -40 to 85°C) (1) READ CYCLE PARAMETER SYM. -45ns -50ns -70ns -85ns -100ns UNIT MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX Read Cycle Time tRC 45 - 50 - 70 - 85 - 100 - ns Address Access Time tAA - 45 - 50 - 70 - 85 - 100 ns Chip Select Access Time tACS - 45 - 50 - 70 - 85 - 100 ns Output Enable to Output Valid tAOE - 22 - 25 - 35 - 40 - 50 ns Chip Selection to Output in Low Z tCLZ* 7 - 7 - 10 - 10 - 10 - ns Output Enable to Output in Low Z tOLZ* 5 - 5 - 5 - 5 - 5 - ns Chip Deselection to Output in High tCHZ* Z Output Disable to Output in High Z tOHZ* - 15 - 20 - 25 - 30 - 30 ns - 15 - 20 - 25 - 30 - 30 ns 10 - 10 - 10 - 10 - 10 - ns Output Hold from Address Change tOH * These parameters is measured with 5pF test load. (2)WRITE CYCLE PARAMETER SYM. -45ns -50ns -70ns -85ns -100ns UNIT MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX Write Cycle Time tWC 45 - 50 - 70 - 85 - 100 - ns Chip Selection to End of Write tCW 35 - 40 - 60 - 70 - 80 - ns Address Valid to End of Write tAW 35 - 40 - 60 - 70 - 80 - ns Address Setup Time tAS 0 - 0 - 0 - 0 - 0 - ns Write Pulse Width tWP 25 - 30 - 50 - 60 - 70 - ns Write Recovery Time tWR 0 - 0 - 0 - 0 - 0 - ns Data Valid to End of Write tDW 22 - 25 - 30 - 35 - 40 - ns Data Hold from End of Write tDH 0 - 0 - 0 - 0 - 0 - ns Write to Output in High Z tWHZ* tOW - 15 - 20 - 25 - 30 - 30 ns 5 - 5 - 5 - 5 - 5 - ns Output Active from End of Write * These parameters is measured with 30pF test load. TM Technology Inc. reserves the right to change products or specifications without notice. P. 5 Publication Date: OCT. 2003 Revision:C tm TE CH T15M256B DATA RETENTION CHARACTERISTICS Item Symbol Test Condition Vcc for data retention VDR CS ≥ Vcc -0.2V Data retention current IDR Vcc =5.0, CS ≥ Vcc -0.2V Data retention set-up time tCDR tR Recovery time See data retention waveform Min Typ max unit 1.5 - - V 10 uA 0 - - 5 - - ms DATA RETENTION WAVE FORM Data Retention M ode V CC V cc_typ t CS V D R > 1.5V Vcc_TYP t CD R R CS >VCC-0.2V V IH TM Technology Inc. reserves the right to change products or specifications without notice. V IH P. 6 Publication Date: OCT. 2003 Revision:C tm TE CH T15M256B TIMING WAVEFORMS READ CYCLE 1 (Address Controlled) tR C A d d re s s tA A tO H tO H D O U T READ CYCLE 2 (Chip Select Controlled) CS tA C S tC H Z tC L Z D O U T READ CYCLE 3 (Output Enable Controlled) tR C A d d re s s tA A O E tO H tA O E tO L Z CS tA C S tC L Z tO H Z tC H Z D O U T DON' T CARE UNDEF INED TM Technology Inc. reserves the right to change products or specifications without notice. P. 7 Publication Date: OCT. 2003 Revision:C tm TE CH WRITE CYCLE 1 T15M256B ( OE CLOCK) tW C Ad d r es s t WR OE tC W CS t t AW WP WE t AS tO H Z (1,4) DOUT t DW t DH DIN WRITE CYCLE 2 ( OE = V IL Fixed) tW C A d d re s s tC W tW R CS tA W tW P W E tO H tA S tW H Z tO W (1 ,4 ) (2 ) (3 ) D O U T tD W tD H D IN DON'T CARE UNDEF INED TM Technology Inc. reserves the right to change products or specifications without notice. P. 8 Publication Date: OCT. 2003 Revision:C tm TE CH T15M256B Notes: 1. During this period, I/O pins are in the output state, so input signals of opposite phase to the outputs should not be applied. 2. The data output from D OUT are the same as the data written to D IN during the write cycle. 3. D OUT provides the read data for the next address. 4. Transition is measured ± 500 mV from steady state with C L = 5pF. guaranteed but not 100% tested. This parameter is 5. If OE is low during a WE controlled write cycle, the write pulse width must be the larger of tWP or (tWHZ + tDW) to allow the I/O drivers to turn off and data to be placed on the bus for the required tDW. If OE is high during a WE controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified tWP. TM Technology Inc. reserves the right to change products or specifications without notice. P. 9 Publication Date: OCT. 2003 Revision:C tm TE CH T15M256B PACKAGE DIMENSIONS 28-LEAD DIP SRAM (600 mil) A A1 D B2 B B3 B1 C2 C C1 Dimension in inches min. typ. max Dimension in mm min. typ. max. A 1.440 1.450 1.460 36.58 36.83 37.08 A1 0.546 0.550 0.554 13.87 13.97 14.07 B - 0.210 - - 5.33 - B1 0.100 - - 2.54 - - B2 0.140 0.150 0.160 3.56 3.81 4.06 B3 0.015 - - 0.38 - - C - 0.100 - - 2.54 - C1 0.016 0.018 0.020 0.41 0.46 0.51 C2 - 0.060 - - 1.52 - D 0.600 0.612 0.624 15.24 15.54 15.85 D1 0.630 0.650 0.670 16.0 16.51 17.0 Symbol TM Technology Inc. reserves the right to change products or specifications without notice. P. 10 D1 Publication Date: OCT. 2003 Revision:C tm TE CH T15M256B PACKAGE DIMENSIONS 28-LEAD SOJ SRAM (300 mil) SYMBOL A B C D E F G H I J K L M N O P Q y DIMENSIONS IN INCHES 0.710±0.002 0.300±0.005 0.060±0.002 0.050±0.001 0.063±0.001 0.015±0.002 0.030±0.002 0.050±0.002 0.018±0.002 0.028±0.002 0.337±0.002 0.010±0.001 0.026±0.002 0.268±0.003 0.300±0.002 0.053±0.001 0.140±0.004 0.004(MAX) TM Technology Inc. reserves the right to change products or specifications without notice. DIMENSIONS IN MM 18.03±0.05 7.62±0.13 1.52±0.05 1.27±0.03 1.63±0.03 0.38±0.05 0.76±0.05 1.27±0.05 0.46±0.05 0.71±0.05 8.56±0.05 0.25±0.03 0.66±0.05 6.81±0.08 7.62±0.05 1.35±0.03 3.56±0.10 0.10(MAX) P. 11 Publication Date: OCT. 2003 Revision:C tm TE CH T15M256B PACKAGE DIMENSIONS 28-LEAD SOP e1 28 15 E HE Detail F 1 b L 14 e1 D C A2 S e y A LE A1 See Detail F Seating Plane Symbol A A1 A2 b C D E e HE L LE S y θ Dimension in inches Dimension in mm min. typ. max min. typ. max. 0.112 2.845 0.004 0.102 0.093 0.098 0.103 2.362 2.489 2.616 0.014 0.016 0.020 0.335 0.406 0.508 0.008 0.010 0.014 0.203 0.254 0.356 0.713 0.733 18.110 18.618 0.326 0.331 0.336 8.280 8.407 8.534 0.044 0.050 0.056 1.118 1.270 1.422 0.453 0.465 0.477 11.506 11.811 12.116 0.028 0.036 0.044 0.711 0.914 1.117 0.059 0.067 0.075 1.499 1.702 1.905 39 1.0 0.004 0.102 0° 10° 0° 10° TM Technology Inc. reserves the right to change products or specifications without notice. P. 12 Notes : 1. Dimensions D max. & S include mold flash or tie bar burrs. 2. Dimension b does not include dambar protrusion / intrusion. 3. Dimensions D & E include mold mismatch and determined at the mold parting line. 4. controlling dimension : inches 5. general appearance spec should be based on final visual inspection spec. Publication Date: OCT. 2003 Revision:C tm TE CH T15M256B PACKAGE DIMENSIONS 28-LEAD TSOP-I FORWARD AND REVERSE (8X13.4mm) D C 1 28 b E e 14 15 A2 "A" A A1 Seating plane Db y 0.010 Gauge plane Seating plane L Detail "A" SYMBOL A A1 A2 b c Db E e D L L1 y θ DIMENSIONS IN INCHES 0.047(max.) 0.004±0.002 0.039±0.002 0.008(typ.) 0.006(typ.) 0.465±0.004 0.315±0.004 0.022(typ.) 0.528±0.008 0.020±0.004 0.0315±0.004 0.004(max.) 0°°~5°° TM Technology Inc. reserves the right to change products or specifications without notice. P. 13 L1 DIMENSIONS IN MM 1.20(max.) 0.10±0.05 1.00±0.05 0.20(typ.) 0.15(typ.) 11.80±0.10 8.00±0.10 0.55(typ.) 13.40±0.20 0.50±0.10 0.80±0.10 0.10(max.) 0°°~5°° Publication Date: OCT. 2003 Revision:C