NIMD6302R2 HDPlus Dual N−Channel Self−protected Field Effect Transistors with 1:200 Current Mirror FET HDPlus devices are an advanced HDTMOS™ series of power MOSFET which utilize ON’s latest MOSFET technology process to achieve the lowest possible on−resistance per silicon area while incorporating smart features. They are capable of withstanding high energy in the avalanche and commutation modes. The avalanche energy is specified to eliminate guesswork in designs where inductive loads are switched and offer additional safety margin against unexpected voltage transients. This HDPlus device features an integrated Gate−to−Source clamp for ESD protection. Also, this device features a mirror FET for current monitoring. • ±3.5% Current Mirror Accuracy in Linear Region • ±15% Current Mirror Accuracy in Low Current Saturation Region • IDSS Specified at Elevated Temperature • Avalanche Energy Specified • Current Sense FET • ESD Protected on the Main and the Mirror FET http://onsemi.com 5.0 AMPERES 30 VOLTS RDS(on) = 50 mW ISOLATED DUAL PACKAGING Drain1 Gate1 Mirror Main FET Mirror1 Source1 Drain2 Main FET Mirror Gate2 Mirror2 Source2 ABSOLUTE MAXIMUM RATINGS Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated in this specification is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. SOIC−8 CASE 751 STYLE 19 MAIN MOSFET MAXIMUM RATINGS (TJ = 25°C unless otherwise noted) Rating Value Unit Drain−to−Source Voltage VDSS 30 Vdc Drain−to−Gate Voltage (RGS = 1.0 MW) VDGR 30 Vdc VGS "16 Vdc Gate−to−Source Voltage Drain Current − Continuous @ TA = 25°C − Continuous @ TA = 100°C (Note 3) − Pulsed (tpv10 ms) Total Power Dissipation @ TA = 25°C (Note 1) Total Power Dissipation @ TA = 25°C (Note 2) Thermal Resistance Junction−to−Ambient (Note 1) Junction−to−Ambient (Note 2) Single Pulse Drain−to−Source Avalanche Energy (Note 3) (VDD = 25 Vdc, VGS = 10 Vdc, VDS = 20 Vdc, IL = 15 Apk, L = 10 mH, RG = 25 W) ID ID IDM 6.5 4.4 33 Adc Adc Apk PD PD 1.3 1.67 W RqJA RqJA 96 75 EAS 250 °C/W mJ MARKING DIAGRAM Source 1 Gate 1 Source 2 Gate 2 1 8 2 7 3 4 N6302 AYWW Symbol 6 5 Mirror 1 Drain 1 Mirror 2 Drain 2 (Top View) N6302 A Y WW = Specific Device Code = Assembly Location = Year = Work Week ORDERING INFORMATION Device NIMD6302R2 Package SOIC−8 Shipping 2500/Tape & Reel 1. Mounted onto min pad board. 2. Mounted onto 1″ pad board. 3. Switching characteristics are independent of operating junction temperatures. © Semiconductor Components Industries, LLC, 2006 March, 2006 − Rev. 4 1 Publication Order Number: NIMD6302R2/D NIMD6302R2 MAIN MOSFET ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted) Characteristic Symbol Min Typ Max Unit 30 20 35 23 − 30 Vdc mV/°C − − − 0.065 0.2 11 10 100 100 mAdc − − 11 12 18 100 mAdc nAdc 1.0 1.1 − 1.33 1.17 3.8 2.0 − 4.6 Vdc − − − 35 57 69 50 65 90 mW gFS 14.5 19.8 25 Mhos Ciss − 301 600 pF Coss − 265 350 Crss − 82 200 td(on) − 9.2 9.6 tr − 56.5 75.3 td(off) − 35.9 40 tf − 36.3 40.6 td(on) − 6.3 7.0 tr − 2.7 3.1 td(off) − 66.5 70.5 tf − 36.5 39.4 QT − 3.91 4.5 Q1 − 1.0 1.25 Q2 − 1.59 1.95 Q3 − 1.48 1.64 QT − 8.03 13.6 Q1 − 1.06 1.36 Q2 − 1.75 2.82 Q3 − 1.54 1.75 OFF CHARACTERISTICS Drain−to−Source Breakdown Voltage (VGS = 0 Vdc, ID = 250 mAdc) Temperature Coefficient (Positive) V(BR)DSS Zero Gate Voltage Drain Current (VDS = 30 Vdc, VGS = 0 Vdc) (VDS = 30 Vdc, VGS = 0 Vdc, TJ = 125°C) (VDS = 30 Vdc, VGS = 0 Vdc, TJ = 175°C) IDSS Gate−Body Leakage Current (VGS = 12 Vdc, VDS = 0 Vdc) (VGS = 3.0 Vdc, VDS = 0 Vdc) IGSS ON CHARACTERISTICS Gate Threshold Voltage (VDS = VGS, ID = 250 mAdc) (VDS = VGS, ID = 250 mAdc, TJ = 75°C) Threshold Temperature Coefficient (Negative) VGS(th) Static Drain−to−Source On−Resistance (Note 4) (VGS = 10 Vdc, ID = 3.0 Adc, TJ @ 25°C) (VGS = 10 Vdc, ID = 3.0 Adc, TJ @ 125°C) (VGS = 10 Vdc, ID = 3.0 Adc, TJ @ 175°C) RDS(on) Forward Transconductance (Note 4) (VDS = 6.0 Vdc, ID = 15 Adc) mV/°C DYNAMIC CHARACTERISTICS (Note 5) Input Capacitance Output Capacitance (VDS = 6.0 Vdc, VGS = 0 Vdc, f = 1.0 MHz) Transfer Capacitance SWITCHING CHARACTERISTICS (Note 5) Turn−On Delay Time Rise Time Turn−Off Delay Time (VDD = 6.0 Vdc, ID = 2.0 Adc, VGS = 4.5 Vdc, RG = 2.5 W) Fall Time Turn−On Delay Time Rise Time Turn−Off Delay Time (VDD = 6.0 Vdc, ID = 2.0 Adc, VGS = 10 Vdc, RG = 2.5 W) Fall Time Gate Charge (VDS = 6.0 Vdc, ID = 2.0 Adc, VGS = 4.5 Vdc) Gate Charge (VDS = 6.0 Vdc, ID = 2.0 Adc, VGS = 10 Vdc) 4. Pulse Test: Pulse Width = 300 ms, Duty Cycle = 2%. 5. Switching characteristics are independent of operating junction temperatures. http://onsemi.com 2 ns ns nC nC NIMD6302R2 MAIN MOSFET ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted) (Continued) Characteristic Symbol Min Typ Max Unit VSD − − − 0.79 0.65 0.58 0.86 0.72 0.64 Vdc trr − 30.8 41 ns ta − 14.6 18 tb − 15.2 20.2 QRR − 0.020 0.03 mC IRAT 170 167 200 196 230 225 − IDRAT 170 200 230 − IRAT 166 165 172 171 178 177 − IDRAT 166 172 184 − IRAT 150 155 155 161 160 166 − IDRAT 150 155 166 − IRAT 141 148 146 153 155 157 − IDRAT 141 146 157 − SOURCE−DRAIN DIODE CHARACTERISTICS Forward On−Voltage (Notes 6 & 7) (IS = 3.0 Adc, VGS = 0 Vdc) (IS = 3.0 Adc, VGS = 0 Vdc, TJ = 125°C) (IS = 3.0 Adc, VGS = 0 Vdc, TJ = 175°C) Reverse Recovery Time (Note 7) (IS = 3.0 Adc, VGS = 0 Vdc, dIS/dt = 100 A/ms) Reverse Recovery Stored Charge (Note 7) MIRROR MOSFET CHARACTERISTICS (TJ = 25°C unless otherwise noted) Main/Mirror MOSFET Current Ratio Operating in the Saturation Region Main/Mirror Current Ratio Variation versus Temperature Operating in the Saturation Region Main/Mirror MOSFET Current Ratio Operating in the Linear Region Main/Mirror Current Ratio Variation versus Temperature Operating in the Linear Region Main/Mirror MOSFET Current Ratio Operating in the Linear Region Main/Mirror Current Ratio Variation versus Temperature Operating in the Linear Region Main/Mirror MOSFET Current Ratio Operating in the Linear Region Main/Mirror Current Ratio Variation versus Temperature Operating in the Linear Region (VDS = 6.0 Vdc, IDmain = 5.0 mA) (VDS = 6.0 Vdc, IDmain = 5.0 mA, TA = 125°C) (VDS = 6.0 Vdc, IDmain = 5.0 mA, TA = 25 to 125°C) (VGS = 3.0 Vdc, IDmain = 1.0 A) (VGS = 3.0 Vdc, IDmain = 1.0 A, TA = 175°C) (VGS = 3.0 Vdc, IDmain = 1.0 A, TA = −40 to +175°C) (VGS = 5.0 Vdc, IDmain = 1.0 A) (VGS = 5.0 Vdc, IDmain = 1.0 A, TA = 175°C) (VGS = 5.0 Vdc, IDmain = 1.0 A, TA = −40 to +175°C) (VGS = 10 Vdc, IDmain = 1.0 A) (VGS = 10 Vdc, IDmain = 1.0 A, TA = 175°C) (VGS = 10 Vdc, IDmain = 1.0 A, TA = −40 to +175°C) MAIN AND SENSE MOSFET ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted) Electro−Static Discharge (ESD) Capability Charge Device Model (CDM) Capability Main FET Sense FET − − 1800 1800 − − − − V Main/Sense FET − 2000 − − V 6. Pulse Test: Pulse Width = 300 ms, Duty Cycle = 2%. 7. Switching characteristics are independent of operating junction temperatures. http://onsemi.com 3 NIMD6302R2 TYPICAL ELECTRICAL CHARACTERISTICS ID, DRAIN CURRENT (AMPS) 6 9V 5 8V 4 7V 7 4V VGS = 10 V 5V 6V 3V 3 2 1 0 2V 0 VDS ≥ 10 V TJ = 25°C ID, DRAIN CURRENT (AMPS) 7 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) 6 5 4 3 TJ = 25°C 2 TJ = 100°C 1 TJ = − 55°C 0 1 1 2 3 4 5 6 VGS, GATE−TO−SOURCE VOLTAGE (VOLTS) Figure 2. Transfer Characteristics RDS(on), DRAIN−TO−SOURCE RESISTANCE (W) RDS(on), DRAIN−TO−SOURCE RESISTANCE (W) Figure 1. On−Region Characteristics 0.07 VGS = 10 V 0.06 TJ = 100°C 0.05 0.04 TJ = 25°C 0.03 TJ = −55°C 0.02 0.01 0 1 2 3 4 5 ID, DRAIN CURRENT (AMPS) 6 0.07 TJ = 25°C 0.06 VGS = 4.5 V 0.05 0.04 VGS = 10 V 0.03 0.02 0.01 0 1 RDS(on), DRAIN−TO−SOURCE RESISTANCE (NORMALIZED) 2 3 4 5 ID, DRAIN CURRENT (AMPS) 6 7 Figure 4. On−Resistance versus Drain Current and Gate Voltage Figure 3. On−Resistance versus Drain Current and Temperature 1000 1.5 VGS = 0 V VGS = 10 V ID = 3 A IDSS, LEAKAGE (nA) 1.25 TJ = 125°C 100 1 0.75 0.5 −50 7 −25 0 25 50 75 TJ = 100°C 10 0 100 0 5 10 15 20 25 TJ, JUNCTION TEMPERATURE (°C) VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) Figure 5. On−Resistance Variation with Temperature Figure 6. Drain−To−Source Leakage Current versus Voltage http://onsemi.com 4 30 NIMD6302R2 POWER MOSFET SWITCHING Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (Dt) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because drain−gate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the off−state condition when calculating td(on) and is read at a voltage corresponding to the on−state when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses. During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG − VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turn−on and turn−off delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG − VGSP)] td(off) = RG Ciss In (VGG/VGSP) 800 VGS = 0 V VDS = 0 V TJ = 25°C C, CAPACITANCE (pF) Ciss 600 400 Crss Ciss 200 Coss 0 −10 Crss −5 0 VGS 5 10 15 20 25 VDS GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS) Figure 7. Capacitance Variation http://onsemi.com 5 12 VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) 35 QT 10 VDD = 30 V ID = 5 A VGS = 10 V 30 VDS 25 8 VGS 20 6 15 4 Q1 ID = 3 A TJ = 25°C 0 1 2 3 100 tf td(off) tr 10 td(on) 10 Q2 2 0 1000 t, TIME (ns) VGS, GATE−TO−SOURCE VOLTAGE (VOLTS) NIMD6302R2 4 5 5 0 6 QG, TOTAL GATE CHARGE (nC) 1 1 10 100 RG, GATE RESISTANCE (W) Figure 8. Gate−To−Source and Drain−To−Source Voltage versus Total Charge Figure 9. Resistive Switching Time Variation versus Gate Resistance DRAIN−TO−SOURCE DIODE CHARACTERISTICS The switching characteristics of a MOSFET body diode are very important in systems using it as a freewheeling or commutating diode. Of particular interest are the reverse recovery characteristics which play a major role in determining switching losses, radiated noise, EMI and RFI. System switching losses are largely due to the nature of the body diode itself. The body diode is a minority carrier device, therefore it has a finite reverse recovery time, trr, due to the storage of minority carrier charge, QRR, as shown in the typical reverse recovery wave form of Figure 14. It is this stored charge that, when cleared from the diode, passes through a potential and defines an energy loss. Obviously, repeatedly forcing the diode through reverse recovery further increases switching losses. Therefore, one would like a diode with short trr and low QRR specifications to minimize these losses. The abruptness of diode reverse recovery effects the amount of radiated noise, voltage spikes, and current ringing. The mechanisms at work are finite irremovable circuit parasitic inductances and capacitances acted upon by high di/dts. The diode’s negative di/dt during ta is directly controlled by the device clearing the stored charge. However, the positive di/dt during tb is an uncontrollable diode characteristic and is usually the culprit that induces current ringing. Therefore, when comparing diodes, the ratio of tb/ta serves as a good indicator of recovery abruptness and thus gives a comparative estimate of probable noise generated. A ratio of 1 is considered ideal and values less than 0.5 are considered snappy. Compared to ON Semiconductor standard cell density low voltage MOSFETs, high cell density MOSFET diodes are faster (shorter trr), have less stored charge and a softer reverse recovery characteristic. The softness advantage of the high cell density diode means they can be forced through reverse recovery at a higher di/dt than a standard cell MOSFET diode without increasing the current ringing or the noise generated. In addition, power dissipation incurred from switching the diode will be less due to the shorter recovery time and lower switching losses. http://onsemi.com 6 NIMD6302R2 IS, SOURCE CURRENT (AMPS) 3.5 3 VGS = 0 V TJ = 25°C 2.5 2 1.5 1 0.5 0 4.00E−01 6.00E−01 8.00E−01 1.00E+00 VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS) Figure 10. Diode Forward Voltage versus Current SAFE OPERATING AREA total power averaged over a complete switching cycle must not exceed (TJ(MAX) − TC)/(RqJC). A power MOSFET designated E−FET can be safely used in switching circuits with unclamped inductive loads. For reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and must be adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases non−linearly with an increase of peak current in avalanche and peak junction temperature. ID, DRAIN CURRENT (AMPS) 100 Mounted on 2″ sq. FR4 board (1″ sq. 2 oz. Cu 0.06″ thick single sided) with one die operating, 10s max. 10 10 ms 1 0.1 0.01 0.1 VGS = 10 V SINGLE PULSE TC = 25°C 100 ms 1 ms 10 ms RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 1 dc 10 100 EAS, SINGLE PULSE DRAIN−TO−SOURCE AVALANCHE ENERGY (mJ) The Forward Biased Safe Operating Area curves define the maximum simultaneous drain−to−source voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25°C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, “Transient Thermal Resistance − General Data and Its Use.” Switching between the off−state and the on−state may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded, and that the transition time (tr, tf) does not exceed 10 ms. In addition the 300 ID = 15 A 250 200 150 100 50 0 25 VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) 50 75 100 125 150 TJ, STARTING JUNCTION TEMPERATURE (°C) Figure 11. Maximum Rated Forward Biased Safe Operating Area Figure 12. Maximum Avalanche Energy versus Starting Junction Temperature http://onsemi.com 7 NIMD6302R2 TYPICAL ELECTRICAL CHARACTERISTICS RqJA(t), EFFECTIVE TRANSIENT THERMAL RESPONSE 1 D = 0.5 0.2 0.1 0.1 0.05 0.02 0.01 0.01 1.0E−03 Normalized to RqJA at Steady State (1″ pad) SINGLE PULSE 1.0E−02 1.0E−01 1.0E+00 1.0E+01 t, TIME (s) Figure 13. FET Thermal Response di/dt IS trr ta tb TIME 0.25 IS tp IS Figure 14. Diode Reverse Recovery Waveform http://onsemi.com 8 1.0E+02 1.0E+03 NIMD6302R2 PACKAGE DIMENSIONS SOIC−8 CASE 751−07 ISSUE AH −X− NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. 751−01 THRU 751−06 ARE OBSOLETE. NEW STANDARD IS 751−07. A 8 5 S B 1 0.25 (0.010) M Y M 4 K −Y− G C N DIM A B C D G H J K M N S X 45 _ SEATING PLANE −Z− 0.10 (0.004) H M D 0.25 (0.010) M Z Y S X J S STYLE 19: PIN 1. 2. 3. 4. 5. 6. 7. 8. SOLDERING FOOTPRINT* 1.52 0.060 7.0 0.275 MILLIMETERS MIN MAX 4.80 5.00 3.80 4.00 1.35 1.75 0.33 0.51 1.27 BSC 0.10 0.25 0.19 0.25 0.40 1.27 0_ 8_ 0.25 0.50 5.80 6.20 INCHES MIN MAX 0.189 0.197 0.150 0.157 0.053 0.069 0.013 0.020 0.050 BSC 0.004 0.010 0.007 0.010 0.016 0.050 0 _ 8 _ 0.010 0.020 0.228 0.244 SOURCE 1 GATE 1 SOURCE 2 GATE 2 DRAIN 2 MIRROR 2 DRAIN 1 MIRROR 1 4.0 0.155 0.6 0.024 1.270 0.050 SCALE 6:1 mm Ǔ ǒinches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. HDTMOS is a registered trademarks of Semiconductor Components Industries, LLC (SCILLC). ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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