19-2709; Rev 1; 5/03 KIT ATION EVALU E L B A IL AVA Multirate Clock and Data Recovery with Limiting Amplifier Features The MAX3872 is a compact, multirate clock and data recovery with limiting amplifier for OC-3, OC-12, OC-24, OC-48, OC-48 with FEC SONET/SDH and Gigabit Ethernet (1.25Gbps/2.5Gbps) applications. Without using an external reference clock, the fully integrated phaselocked loop (PLL) recovers a synchronous clock signal from the serial NRZ data input. The input data is then retimed by the recovered clock, providing a clean data output. An additional serial input (SLBI±) is available for system loopback diagnostic testing. Alternatively, this input can be connected to a reference clock to maintain a valid clock output in the absence of data transitions. The device also includes a loss-of-lock (LOL) output. The MAX3872 contains a vertical threshold control to compensate for optical noise due to EDFAs in DWDM transmission systems. The recovered data and clock outputs are CML with on-chip 50Ω back termination on each line. Its jitter performance exceeds all SONET/SDH specifications. The MAX3872 operates from a single +3.3V supply and typically consumes 580mW. It is available in a 5mm x 5mm 32-pin thin QFN with exposed-pad package and operates over a -40°C to +85°C temperature range. ♦ Multirate Data Input: 2.667Gbps (FEC), 2.488Gbps, 1.244Gbps, 622.08Mbps, 155.52Mbps, 1.25Gbps/2.5Gbps (Ethernet) ♦ Reference Clock Not Required for Data Acquisition Applications Ordering Information ♦ Exceeds ANSI, ITU, and Bellcore SONET/SDH Jitter Specifications ♦ 2.7mUIRMS Jitter Generation ♦ 10mVP-P Input Sensitivity Without Threshold Adjust ♦ 0.65UIP-P High-Frequency Jitter Tolerance ♦ ±170mV Input Threshold Adjust Range ♦ Clock Holdover Capability Using FrequencySelectable Reference Clock ♦ Serial Loopback Input Available for System Diagnostic Testing ♦ Loss-of-Lock (LOL) Indicator SONET/SDH Receivers and Regenerators PART Add/Drop Multiplexers TEMP RANGE MAX3872EGJ Digital Cross-Connects PIN-PACKAGE -40°C to +85°C 32 QFN PKG CODE G3255-1 SONET/SDH Test Equipment DWDM Transmission Systems Access Networks Pin Configuration appears at end of data sheet. Typical Application Circuit +3.3V +3.3V CAZ 0.1µF CFIL 0.82µF VCC FILTER +3.3V FIL VCC_VCO CAZ- OUT+ SDI+ MAX3745* OUT- SDI- IN CAZ+ FREFSET VCC SDO+ SDO- SLBI+ GND +3.3V MAX3872 SLBI- SCLKO+ SCLKO- +3.3V CML CML VCTRL VREF *FUTURE PRODUCT SYSTEM LOOPBACK DATA SIS LREF LOL RS1 RS2 RATESET GND +3.3V ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 MAX3872 General Description MAX3872 Multirate Clock and Data Recovery with Limiting Amplifier ABSOLUTE MAXIMUM RATINGS Supply Voltage, VCC..............................................-0.5V to +5.0V Input Voltage Levels (SDI+, SDI-, SLBI+, SLBI-) ..........(VCC - 1.0V) to (VCC + 0.5V) Input Current Levels (SDI+, SDI-, SLBI+, SLBI-)............................................±20mA CML Output Current (SDO+, SDO-, SCLKO+, SCLKO-) ...............................±22mA Voltage at LOL, LREF, SIS, FIL, RATESET, FREFSET, RS1, RS2, VCTRL, VREF, CAZ+, CAZ-......................-0.5V to (VCC + 0.5V) Continuous Power Dissipation (TA = +85°C) 32-Pin QFN (derate 21.3mW/°C above +85°C) .........1384mW Operating Junction Temperature Range ...........-55°C to +150°C Storage Temperature Range .............................-55°C to +150°C Processing Temperature (die) .........................................+400°C Lead Temperature (soldering, 10s) .................................+300°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC ELECTRICAL CHARACTERISTICS (VCC = +3.0V to +3.6V, TA = -40°C to +85°C. Typical values at VCC = +3.3V, TA = +25°C, unless otherwise noted.) (Note 1) PARAMETER Supply Current SYMBOL ICC CONDITIONS MIN (Note 2) TYP MAX UNITS 175 215 mA INPUT SPECIFICATIONS (SDI±, SLBI±) Single-Ended Input Voltage Range VIS Input Common-Mode Voltage Input Termination to VCC Figure 1 VCC - 0.8 VCC + 0.4 V Figure 1 VCC - 0.4 VCC V 57.5 Ω 50 600 mVP-P RIN 42.5 50 THRESHOLD-SETTING SPECIFICATIONS (SDI±) Differential Input Voltage Range (SDI±) Threshold Adjustment Range Threshold Control Voltage Threshold adjust enabled VTH VCTRL Figure 2 -170 +170 mV Figure 2 (Note 3) 0.3 2.1 V Figure 2 -18 +18 mV 15mV ≤ |VTH| ≤ 80mV -6 +6 80mV < |VTH| ≤ 170mV -12 +12 ±5 Threshold Control Linearity Threshold Setting Accuracy Threshold Setting Stability % mV Maximum Input Current ICTRL -10 +10 µA Reference Voltage Output VREF 2.14 2.2 2.24 V 600 800 1000 mVP-P 85 100 115 Ω CML OUTPUT SPECIFICATIONS (SDO±, SCLKO±) CML Differential Output Swing CML Differential Output Impedance CML Output Common-Mode Voltage 2 (Note 4) RO (Note 4) VCC - 0.2 _______________________________________________________________________________________ V Multirate Clock and Data Recovery with Limiting Amplifier MAX3872 DC ELECTRICAL CHARACTERISTICS (continued) (VCC = +3.0V to +3.6V, TA = -40°C to +85°C. Typical values at VCC = +3.3V, TA = +25°C, unless otherwise noted.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS LVTTL INPUT/OUTPUT SPECIFICATIONS (LOL, LREF, RATESET, RS1, RS2, FREFSET) LVTTL Input High Voltage VIH LVTTL Input Low Voltage VIL 2.0 LVTTL Input Current -10 LVTTL Output High Voltage VOH IOH = +20µA LVTTL Output Low Voltage VOL IOL = -1mA Note 1: Note 2: Note 3: Note 4: V 0.8 V +10 µA 0.4 V 2.4 V At -40°C, DC characteristics are guaranteed by design and characterization. CML outputs open. Voltage applied to VCTRL pin is from +0.3V to +2.1V when input threshold is adjusted from +170mV to -170mV. RL = 50Ω to VCC. AC ELECTRICAL CHARACTERISTICS (VCC = +3.0V to +3.6V, TA = -40°C to +85°C. Typical values are at VCC = +3.3V and TA = +25°C, unless otherwise noted.) (Note 5) PARAMETER SYMBOL CONDITIONS MIN Serial Input Data Rate Differential Input Voltage (SDI±) Jitter Peaking MAX UNITS Table 2 VID Differential Input Voltage (SLBI±) Jitter Transfer Bandwidth TYP JBW JP Sinusoidal Jitter Tolerance OC-48 Sinusoidal Jitter Tolerance OC-12 Sinusoidal Jitter Tolerance OC-3 Sinusoidal Jitter Tolerance with Threshold Adjust Enabled OC-48 (Note 7) Threshold adjust disabled, Figure 1 (Note 6) 10 1600 mVP-P BER ≤ 10-10 50 800 mVP-P OC-3 80 OC-12 370 500 OC-48 1500 2000 f ≤ JBW f = 100kHz 3.1 8.0 f = 1MHz 0.62 0.93 f = 10MHz 0.44 0.65 f = 25kHz 2.9 8.3 f = 250kHz 0. 59 1.03 f = 2.5MHz 0.42 0.63 f = 6.5kHz 2.9 7.8 f = 65kHz 0.59 1.05 f = 650kHz 0.42 0.64 130 0.1 f = 100kHz 7.1 f = 1MHz 0.82 f = 10MHz 0.54 Jitter Generation JGEN (Note 8) 2.7 Differential Input Return Loss (SDI±, SLBI±) -20log | S11 | 100kHz to 2.5GHz 16 2.5GHz to 4.0GHz 15 kHz dB UIP-P UIP-P UIP-P UIP-P 4.0 mUIRMS dB _______________________________________________________________________________________ 3 MAX3872 Multirate Clock and Data Recovery with Limiting Amplifier AC ELECTRICAL CHARACTERISTICS (continued) (VCC = +3.0V to +3.6V, TA = -40°C to +85°C. Typical values are at VCC = +3.3V and TA = +25°C, unless otherwise noted.) (Note 5) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 110 ps RC = 100Ω differential 600 800 1000 mVP-P (Note 9) -50 +50 ps CML OUTPUT SPECIFICATIONS (SDO±, SCLKO±) Output Edge Speed tr, tf CML Output Differential Swing Clock-to-Q Delay tCLK-Q 20% to 80% PLL ACQUISITION/LOCK SPECIFICATIONS Tolerated Consecutive Identical Digits BER ≤ 10-10 Acquisition Time Figure 4 (Note 10) LOL Assert Time Figure 4 Low-Frequency Cutoff for DC-Offset Cancellation CAZ = 0.1µF 2000 bits 5.5 2.3 ms 100.0 4 µs kHz CLOCK HOLDOVER SPECIFICATIONS Reference Clock Frequency Table 3 Maximum VCO Frequency Drift (Note 11) 400 ppm AC characteristics are guaranteed by design and characterization. Jitter tolerance is guaranteed (BER ≤ 10-10) within this input voltage range. Input threshold adjust is disabled with VCTRL connected to VCC. Note 7: Measured at OC-48 data rate using a 100mVP-P differential swing with a 20mVDC offset and an edge speed of 145ps (4thorder Bessel filter with f3dB = 1.8GHz). Note 8: Measured with 10mVP-P differential input, 223 - 1 PRBS pattern at OC-48 with bandwidth from 12kHz to 20MHz. Note 9: Relative to the falling edge of the SCLKO+ (Figure 3). Note 10: Measured using a 0.82µF loop-filter capacitor initialized to +3.6V. Note 11: Measured at OC-48 data rate under LOL condition with the CDR clock output set by the external reference clock. Note 5: Note 6: Timing Diagrams VTH (mV) VCC + 0.4V 800mV 5mV THRESHOLD-SETTING STABILITY (OVERTEMPERATURE AND POWER SUPPLY) +170 +152 VCC VCC - 0.4V +188 (a) AC-COUPLED SINGLE-ENDED INPUT 1.3 5mV VCTRL (V) VCC 0.3 1.1 800mV VCC - 0.4V -152 -170 VCC - 0.8V -188 (b) DC-COUPLED SINGLE-ENDED INPUT Figure 1. Definition of Input Voltage Swing 4 2.10 THRESHOLDSETTING ACCURACY (PART-TO-PART VARIATION OVER PROCESS) Figure 2. Relationship Between Control Voltage and Threshold Voltage _______________________________________________________________________________________ Multirate Clock and Data Recovery with Limiting Amplifier DATA tCLK DATA INPUT DATA SCLKO+ tCLK-Q ACQUISITION TIME LOL ASSERT TIME SDO LOL OUTPUT Figure 3. Definition of Clock-to-Q Delay Figure 4. LOL Assert Time and PLL Acquisition Time Measurement Typical Operating Characteristics (VCC = +3.3V, TA = +25°C, unless otherwise noted.) MAX3872toc02 RECOVERED CLOCK AND DATA (2.67Gbps, 223 - 1 PATTERN, VIN = 10mVP-P) MAX3872toc01 RECOVERED CLOCK AND DATA (2.488Gbps, 223 - 1 PATTERN, VIN = 10mVP-P) 200mV/ div 200mV/ div 100ps/div OC-48 PRBS = 223 - 1 3.5 JITTER GENERATION (psRMS) MAX3872toc04 4.0 MAX3872toc05 JITTER GENERATION vs. POWER-SUPPLY WHITE NOISE RECOVERED CLOCK JITTER (622.08Mbps) MAX3872toc03 RECOVERED CLOCK JITTER (2.488Gbps) 100ps/div 3.0 2.5 2.0 1.5 1.0 0.5 0.0 10ps/div TOTAL WIDEBAND RMS JITTER = 1.60ps PEAK-TO-PEAK JITTER = 12.20ps 10ps/div TOTAL WIDEBAND RMS JITTER = 2.17ps PEAK-TO-PEAK JITTER = 15.80ps 0 5 10 15 20 25 30 WHITE-NOISE AMPLITUDE (mVRMS) _______________________________________________________________________________________ 5 MAX3872 Timing Diagrams (continued) Typical Operating Characteristics (continued) (VCC = +3.3V, TA = +25°C, unless otherwise noted.) 1 BELLCORE MASK 0.5 0.4 JITTER FREQUENCY = 10MHz 0.3 0.2 WITH ADDITIONAL 0.15UI DETERMINISTIC JITTER 1M 1 10M 10 JITTER TOLERANCE vs. THRESHOLD ADJUST 0.5 0.3 0.2 0.1 VIN = 100mVP-P 2.488Gbps 223 - 1 PATTERN 0.3 0.2 INPUT DATA FILTERED BY A 1870MHz 4TH-ORDER BESSEL FILTER 0.1 30 40 50 60 70 80 INPUT THRESHOLD (% AMPLITUDE) -1.5 10-5 10-6 10-7 10-8 10-9 CFIL = 0.82µF PRBS = 223 - 1 2.488Gbps 1k 90 10k 10-10 10-11 100k 1M 0 10M 5 2.9 2.8 FREQUENCY (GHz) S11 (dB) -15 -20 2.7 2.6 2.5 2.4 2.3 2.2 2.1 -40 100 4 3.0 MAX3872toc13 MAX3872toc12 -5 -35 75 3 PULLIN RANGE (RATESET = 0) DIFFERENTIAL S11 vs. FREQUENCY 0 -30 0 25 50 TEMPERATURE (°C) 2 INPUT VOLTAGE (mVP-P) -25 -25 1 FREQUENCY (Hz) -10 -50 0.30 OC-48 PRBS = 223 - 1 10-3 -2.0 SUPPLY CURRENT vs. TEMPERATURE 200 195 190 185 180 175 170 165 160 155 150 145 140 0.10 0.15 0.20 0.25 DETERMINISTIC JITTER (UIP-P) 10-2 MAX3872toc10 -1.0 -3.0 20 0.05 10-4 BELLCORE MASK -0.5 -2.5 0 10 0 BIT-ERROR RATIO vs. INPUT AMPLITUDE 0 JITTER TRANSFER (dB) 0.6 0.4 10,000 0.5 MAX3872toc09 JITTER FREQUENCY = 10MHz 0.5 fJITTER = 10MHz 0.4 JITTER TRANSFER 0.7 SINUSOIDAL JITTER TOLERANCE (UIP-P) 0.6 0 100 1000 INPUT AMPLITUDE (mVP-P) JITTER FREQUENCY (Hz) 6 0.7 MAX3872toc14 100k fJITTER = 1MHz 0.8 0 10k 223 - 1 PATTERN 2.488Gbps VIN = 10mVP-P 0.9 MAX3872toc08 JITTER FREQUENCY = 1MHz 0.6 0.1 0.1 1.0 MAX3872toc07 0.7 SINUSOIDAL JITTER TOLERANCE (UIP-P) 10 JITTER TOLERANCE vs. INPUT DETERMINISTIC JITTER BIT-ERROR RATIO INPUT JITTER (UIP-P) WITH ADDITIONAL 0.15UI DETERMINISTIC JITTER 0.8 JITTER TOLERANCE (UIP-P) MAX3872 TOC06 100 JITTER TOLERANCE vs. INPUT AMPLITUDE (2.488Gbps, 223 - 1 PATTERN) MAX3872toc11 JITTER TOLERANCE (2.488Gbps, 223 - 1 PATTERN, VIN = 10mVP-P) SUPPLY CURRENT (mA) MAX3872 Multirate Clock and Data Recovery with Limiting Amplifier 2.0 0 0.5 1.0 1.5 2.0 2.5 3.0 FREQUENCY (GHz) 3.5 4.0 -50 -25 0 25 50 AMBIENT TEMPERATURE (°C) _______________________________________________________________________________________ 75 100 Multirate Clock and Data Recovery with Limiting Amplifier PIN NAME FUNCTION 1, 4, 27 VCC 2 SDI+ Positive Serial Data Input, CML 3 SDI- Negative Serial Data Input, CML 5 SLBI+ Positive System Loopback Input or Reference Clock Input, CML 6 SLBI- Negative System Loopback Input or Reference Clock Input, CML 7 SIS 8 LREF Lock to Reference Clock Input, LVTTL. Set high for PLL lock to serial data, set low for PLL lock to reference clock. 9 LOL Loss-of-Lock Output, LVTTL. Active low. 10, 11, 16, 25, 32 GND Supply Ground 12 FIL 13, 18 VCC_VCO 14 RS1 15 RS2 17 RATESET 19 SCLKO- 20 SCLKO+ 21, 24 VCC_OUT 22 SDO- +3.3V Supply Voltage Signal Selection Input, LVTTL. Set low for normal operation, set high for system loopback. PLL Loop Filter Capacitor Input. Connect a 0.82µF capacitor between FIL and VCC_VCO. +3.3V Supply Voltage for the VCO Multirate Select Input 1, LVTTL (Table 2) Multirate Select Input 2, LVTTL (Table 2) VCO Frequency Select Input, LVTTL (Table 2) Negative Serial Clock Output, CML Positive Serial Clock Output, CML +3.3V Supply Voltage for the CML Outputs Negative Serial Data Output, CML 23 SDO+ 26 FREFSET Positive Serial Data Output, CML 28 CAZ+ Positive Capacitor Input for DC-Offset Cancellation Loop. Connect a 0.1µF capacitor between CAZ+ and CAZ-. 29 CAZ- Negative Capacitor Input for DC-Offset Cancellation Loop. Connect a 0.1µF capacitor between CAZ+ and CAZ-. 30 VREF +2.2V Bandgap Reference Voltage Output. Optionally used for threshold adjustment. 31 VCTRL Analog Control Input for Threshold Adjustment. Connect to VCC to disable threshold adjust. EP Exposed Pad Reference Clock Frequency Select Input, LVTTL (Tables 2 and 3) Ground. The exposed pad must be soldered to the circuit board ground for proper thermal and electrical performance. _______________________________________________________________________________________ 7 MAX3872 Pin Description MAX3872 Multirate Clock and Data Recovery with Limiting Amplifier Detailed Description The MAX3872 consists of a fully integrated phaselocked loop (PLL), limiting amplifier with threshold adjust, DC-offset cancellation loop, data retiming block, and CML output buffers (Figure 5). The PLL consists of a phase/frequency detector, a loop filter, and a voltagecontrolled oscillator (VCO) with programmable dividers. This device is designed to deliver the best combination of jitter performance and power dissipation by using a fully differential signal architecture and low-noise design techniques. SDI Input Amplifier The SDI inputs of the MAX3872 accept serial NRZ data with a differential input amplitude from 10mVP-P up to1600mVP-P. The input sensitivity is 10mVP-P, at which the jitter tolerance is met for a BER of 10-10 with threshold adjust disabled. The input sensitivity can be as low as 4mV P-P and still maintain a BER of 10 -10 . The MAX3872 inputs are designed to directly interface with a transimpedance amplifier such as the MAX3745. For applications in which vertical threshold adjustment is needed, the MAX3872 can be connected to the output of an AGC amplifier such as the MAX3861. When using the threshold adjust, the input voltage range is 50mVP-P to 600mVP-P. See the Design Procedure section for decision threshold adjust. CAZ+ VCTRL THRESHOLD ADJUST SDI+ AMP SDI- LOL CAZ- SLBI Input Amplifier The SLBI input amplifier accepts either NRZ loopback data or a reference clock signal. This amplifier can accept a differential input amplitude from 50mVP-P to 800mVP-P. Phase Detector The phase detector incorporated in the MAX3872 produces a voltage proportional to the phase difference between the incoming data and the internal clock. Because of its feedback nature, the PLL drives the error voltage to zero, aligning the recovered clock to the center of the incoming data eye for retiming. Frequency Detector The digital frequency detector (FD) acquires frequency lock without the use of an external reference clock. The frequency difference between the received data and the VCO clock is derived by sampling the in-phase and quadrature VCO outputs on both edges of the data input signal. Depending on the polarity of the frequency difference, the FD drives the VCO until the frequency difference is reduced to zero. Once frequency acquisition is complete, the FD returns to a neutral state. False locking is completely eliminated by this digital frequency detector. FIL VREF RATESET BANDGAP REFERENCE MAX3872 DC-OFFSET CANCELLATION LOOP SDO+ 0 D Q CML SDO- 1 PHASE AND FREQUENCY DETECTOR SLBI+ AMP SLBI- LOOP FILTER SCLKO+ ÷ BY N VCO CML SCLKO- SIS LREF LOGIC FREFSET RS1 RS2 Figure 5. Functional Diagram 8 _______________________________________________________________________________________ Multirate Clock and Data Recovery with Limiting Amplifier Modes of Operation The MAX3872 has three operational modes controlled by the LREF and SIS inputs. The three operational modes are normal, system loopback, and clock holdover. Normal operation mode requires a serial data stream at the SDI± input, system loopback mode requires a serial data stream at the SLBI± input, and clock holdover mode requires a reference clock signal at the SLBI± inputs. See Table 1 for the required LREF and SIS settings. Once an operational mode is chosen, the remaining logic inputs (RATESET, RS1, RS2, and FREFSET) program the input data rate or reference clock frequency. VCOs with Programmable Dividers The loop filter output controls the two on-chip VCOs. The VCOs provide low phase noise and are trimmed to the frequency of 2.488GHz and 2.667GHz. The RATESET pin is used to select the appropriate VCO. The VCO output is connected to programmable dividers controlled by inputs RS1 and RS2. See Tables 2 and 3 for the proper settings. LOL Monitor The LOL output indicates a PLL lock failure, either because of excessive jitter present at the data input or because of loss of input data. The LOL output is asserted low when the PLL loses lock. Normal and System Loopback Settings Three pins (RS1, RS2, and RATESET) are available for setting the SDI± and SLBI± input to receive the appropriate data rate. The FREFSET pin can be set to a zero or 1 while in normal or system loopback mode (Table 2). Clock Frequencies in Holdover Mode Set the incoming reference clock frequency and outgoing serial clock frequency by setting RS1, RS2, RATESET, and FREFSET appropriately (Table 3). DC-Offset Cancellation Loop A DC-offset cancellation loop is implemented to remove the DC offset of the limiting amplifier. To minimize the low-frequency pattern-dependent jitter associated with this DC-cancellation loop, the low-frequency cutoff is 10kHz (typ) with CAZ = 0.1µF, connected from CAZ+ to CAZ-. The DC-offset cancellation loop operates only when threshold adjust is disabled. Table 1. Operational Modes LREF MODE SIS Normal 1 0 System loopback 1 1 Clock holdover 0 1 or 0 Design Procedure Decision Threshold Adjust In applications in which the noise density is not balanced between logical zeros and ones (i.e., optical amplification using EDFA amplifiers), lower bit-error ratios (BERs) can be achieved by adjusting the input threshold. Varying the voltage at VCTRL from +0.3V to +2.1V achieves a vertical decision threshold adjustment of +170mV to -170mV, respectively (Figure 2). Use the provided bandgap reference voltage output (VREF) with a voltage-divider circuit or the output of a DAC to set the voltage at VCTRL. VREF can be used to generate the voltage for VCTRL (Figure 10). If threshold adjust is not required, disable it by connecting VCTRL directly to VCC and leave VREF floating. Table 2. Data Rate Settings INPUT DATA RATE (bps) RS1 RS2 RATESET FREFSET 2.667G 0 0 1 1 or 0 2.488G/2.5G 0 0 0 1 or 0 1.25G/1.244G 1 1 0 1 or 0 666.51M 0 1 1 1 or 0 622.08M 0 1 0 1 or 0 166.63M 1 0 1 1 or 0 155.52M 1 0 0 1 or 0 _______________________________________________________________________________________ 9 MAX3872 Loop Filter The phase detector and frequency detector outputs are summed into the loop filter. An external capacitor (CFIL) connected from FIL to VCC_VCO is required to set the PLL damping ratio. Note that the PLL jitter bandwidth does not change as the external capacitor changes, but the jitter peaking, acquisition time, and loop stability are affected. See the Design Procedure section for guidelines on selecting this capacitor. Table 3. Holdover Frequency Settings REFERENCE CLOCK FREQUENCY (MHz) SCLKO FREQUENCY RS1 RS2 RATESET FREFSET 666.51 2.667GHz 0 0 1 0 666.51 666.51MHz 0 1 1 0 666.51 166.63MHz 1 0 1 0 622.08/625 1.244/1.25GHz 1 1 0 0 622.08/625 2.488GHz/2.5GHz 0 0 0 0 622.08 622.08MHz 0 1 0 0 622.08 155.52MHz 1 0 0 0 166.63 2.67GHz 0 0 1 1 166.63 666.51MHz 0 1 1 1 166.63 166.63MHz 1 0 1 1 155.52/156.25 1.244/1.25GHz 1 1 0 1 155.52/156.25 2.488GHz/2.5GHz 0 0 0 1 155.52 622.08MHz 0 1 0 1 155.52 155.52MHz 1 0 0 1 fZ = Excessive reduction of CFIL might cause PLL instability. CFIL must be a low-TC, high-quality capacitor of type X7R or better. HO(j2πf) (dB) DATA RATE: 2.488Gbps OPEN-LOOP GAIN Setting the Loop Filter The MAX3872 is designed for regenerator and receiver applications. Its fully integrated PLL is a classic 2nd-order feedback system, with a jitter transfer bandwidth (JBW) below 2.0MHz. The external capacitor (CFIL) connected from FIL to VCC_VCO sets the PLL loop damping. Note that the PLL jitter transfer bandwidth does not change as CFIL changes, but the jitter peaking, acquisition time, and loop stability are affected. Figures 6 and 7 show the open-loop and closed-loop transfer functions. The PLL zero frequency, fZ, is a function of external capacitor CFIL, and can be approximated according to: CFIL = 0.01µF fZ = 24.5kHz CFIL = 0.82µF fZ = 299Hz 1 2π(650Ω)CFIL f (kHz) For an overdamped system (fZ / JBW < 0.25), the jitter peaking (JP) of a 2nd-order system can be approximated by: f JP = 20 log1 + Z JBW where JBW is the jitter transfer bandwidth for a given data rate. The recommended value of CFIL = 0.82µF is to guarantee a maximum jitter peaking of less than 0.1dB for all data rates. Decreasing CFIL from the recommended value decreases acquisition time, with the tradeoff of increased peaking. For data rates greater than OC-3, CFIL can be less than 0.82µF and still meet the jitter-peaking specification. 10 1 1000 100 10 Figure 6. Open-Loop Transfer Function CFIL = 0.01µF H(j2πf) (dB) CLOSED-LOOP GAIN MAX3872 Multirate Clock and Data Recovery with Limiting Amplifier 0 -3 CFIL = 0.82µF DATA RATE: 2.488Gbps f (kHz) 1 10 100 1000 Figure 7. Closed-Loop Transfer Function ______________________________________________________________________________________ Multirate Clock and Data Recovery with Limiting Amplifier MAX3872 Input Terminations The SDI± and SLBI± inputs of the MAX3872 are currentmode logic (CML) compatible. The inputs all provide internal 50Ω termination to reduce the required number of external components. AC-coupling is recommended. See Figure 8 for the input structure. For additional information on logic interfacing, refer to Maxim Application Note HFAN 1.0: Introduction to LVDS, PECL, and CML. MAX3872 VCC 50Ω 50Ω Output Terminations The MAX3872 uses CML for its high-speed digital outputs (SDO± and SCLKO±). The configuration of the output circuit includes internal 50Ω back terminations to VCC. See Figure 9 for the output structure. CML outputs can be terminated by 50Ω to VCC, or by 100Ω differential impedance. For additional information on logic interfacing, refer to Maxim Application Note HFAN 1.0: Introduction to LVDS, PECL, and CML. SDO+ SDO- Figure 9. CML Output Model Applications Information VCC Clock Holdover Capability 50Ω SDI+ SDI- 50Ω Clock holdover is required in some applications in which a valid clock must be provided to the upstream device in the absence of data transitions. To provide this function, an external reference clock signal must be applied to the SLBI± inputs and the proper control signals set (see the Modes of Operation section). To enter holdover mode automatically when there are no transitions applied to the SDI± inputs, LOL or the system LOS can be directly connected to LREF. System Loopback MAX3872 The MAX3872 is designed to allow system loopback testing. When the device is set for system loopback mode, the serial output data of a transmitter may be directly connected to the SLBI inputs to run system diagnostics. See Table 1 for selecting system loopback operation mode. While in system loopback mode, LREF should not be connected to LOL. Figure 8. CML Input Model ______________________________________________________________________________________ 11 Pin Configuration MAX3861 AGC AMPLIFIER CAZ- CAZ+ VCC FREFSET GND 29 28 27 26 25 CAZ+ VCC FREFSET SDI+ TIA OUTPUT (2.488Gbps) VREF TOP VIEW 30 FIL VCC_VCO CAZ- +3.3V VCTRL +3.3V 31 +3.3V GND 0.1µF 0.82µF 32 +3.3V SDI- SDO+ VCC 1 24 VCC_OUT SDI+ 2 23 SDO+ SDI- 3 22 SDO- VCC 4 21 VCC_OUT 20 SCLKO+ CML SLBI+ R1 SDOSCLKO+ VCTRL SCLKO- CML VREF SIS LREF LOL RS1 RS2 RATESET GND MAX3872 SLBI+ 5 SLBI- 6 19 SCLKO- SIS 7 18 VCC_VCO LREF 8 17 RATESET 12 13 14 15 16 FIL VCC_VCO RS1 RS2 GND Consecutive Identical Digits (CIDs) 11 Figure 10. Interfacing with the MAX3861 AGC Using Threshold Adjust GND TTL 10 R1 + R2 ≥ 50kΩ GND R2 9 155.52MHz REFERENCE CLOCK MAX3872 SLBI- LOL MAX3872 Multirate Clock and Data Recovery with Limiting Amplifier The MAX3872 has a low phase and frequency drift in the absence of data transitions. As a result, long runs of consecutive zeros and ones can be tolerated while maintaining a BER better than 10-10. The CID tolerance is tested using a 213 - 1 PRBS with long runs of ones and zeros inserted in the pattern. A CID tolerance of 2000 bits is typical. Exposed Pad (EP) Package The EP 32-pin QFN incorporates features that provide a very-low thermal-resistance path for heat removal from the IC. The pad is electrical ground on the MAX3872 and should be soldered to the circuit board for proper thermal and electrical performance. 5mm x 5mm 32 QFN Chip Information TRANSISTOR COUNT: 5142 PROCESS: SiGe BiPOLAR SUBSTRATE: SOI Layout Considerations For best performance, use good high-frequency layout techniques. Filter voltage supplies, keep ground connections short, and use multiple vias where possible. Use controlled-impedance transmission lines to interface with the MAX3872 high-speed inputs and outputs. Power-supply decoupling should be placed as close to VCC as possible. To reduce feedthrough, isolate the input signals from the output signals. If a bare die is used, mount the back of die to ground (GND) potential. 12 ______________________________________________________________________________________ Multirate Clock and Data Recovery with Limiting Amplifier 32L QFN.EPS Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 13 © 2003 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products. MAX3872 Package Information (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)