ETC ALC250

ALC250
TWO CHANNEL AC’97 2.3 AUDIO CODEC
with EQUALIZER
DATA SHEET
Rev. 1.01
06 August 2003
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ALC250 Data Sheet
COPYRIGHT
©2003 Realtek Semiconductor Corp. All rights reserved. No part of this document may be reproduced,
transmitted, transcribed, stored in a retrieval system, or translated into any language in any form or by any
means without the written permission of Realtek Semiconductor Corp.
DISCLAIMER
Realtek provides this document “as is”, without warranty of any kind, neither expressed nor implied,
including, but not limited to, the particular purpose. Realtek may make improvements and/or changes in
this document or in the product described in this document at any time. This document could include
technical inaccuracies or typographical errors.
TRADEMARKS
Realtek is a trademark of Realtek Semiconductor Corporation. Other names mentioned in this document
are trademarks/registered trademarks of their respective owners.
CONFIDENTIALITY
This document is confidential and should not be provided to a third-party without the permission of Realtek
Semiconductor Corporation.
USING THIS DOCUMENT
This document is intended for the software engineer’s reference and provides detailed programming
information.
Though every effort has been made to ensure that this document is current and accurate, more information
may have become available subsequent to the production of this guide. In that event, please contact your
Realtek representative for additional information that may help in the development process.
REVISION HISTORY
Revision
1.00
1.01
Release Date
2003/07/31
2003/08/06
Two Channel AC’97 2.3 Audio Codec
Summary
First release.
Change cover page.
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ALC250 Data Sheet
Table of Contents
1. Features................................................................................................................................................................................... 1
2. General Description ............................................................................................................................................................... 1
3. Block Diagram........................................................................................................................................................................ 2
3.1 Analog Mixer .................................................................................................................................................................... 2
3.2 Digital Data Path ............................................................................................................................................................... 3
4. Pin Assignments ..................................................................................................................................................................... 4
5. Pin Description ....................................................................................................................................................................... 5
5.1 Digital I/O Pins ................................................................................................................................................................. 5
5.2 Analog I/O Pins................................................................................................................................................................. 5
5.3 Filter/Reference/NC .......................................................................................................................................................... 6
5.4 Power/Ground ................................................................................................................................................................... 6
6. Registers.................................................................................................................................................................................. 7
6.1 Mixer Registers ................................................................................................................................................................. 7
6.1.2 MX02 Master Volume............................................................................................................................................... 8
6.1.3 MX04 Headphone....................................................................................................................................................... 8
6.1.4 MX06 MONO_OUT Volume ................................................................................................................................... 9
6.1.5 MX0A PC BEEP Volume ......................................................................................................................................... 9
6.1.6 MX0C PHONE Volume............................................................................................................................................ 9
6.1.7 MX0E MIC Volume................................................................................................................................................ 10
6.1.8 MX10 LINE_IN Volume ........................................................................................................................................ 10
6.1.9 MX12 CD Volume .................................................................................................................................................. 10
6.1.10 MX16 AUX Volume ............................................................................................................................................. 11
6.1.11 MX18 PCM_OUT Volume ................................................................................................................................... 11
6.1.12 MX1A Record Select ............................................................................................................................................ 11
6.1.13 MX1C Record Gain for Stereo ADC .................................................................................................................... 12
6.1.14 MX1E Record Gain for MIC ADC ....................................................................................................................... 12
6.1.15 MX20 General Purpose Register........................................................................................................................... 12
6.1.16 MX22 3D Control ................................................................................................................................................. 13
6.1.17 MX24 Audio interrupt and Paging ........................................................................................................................ 13
6.1.18 MX26 Powerdown Control/Status ........................................................................................................................ 14
6.1.19 MX28 Extended Audio ID .................................................................................................................................... 15
6.1.20 MX2A Extended Audio Status and Control............................................................................................................. 15
6.1.21 MX2C PCM DAC Rate......................................................................................................................................... 16
6.1.22 MX32 PCM ADC Rate ......................................................................................................................................... 16
6.1.23 MX3A S/PDIF Out Channel Status/Control ............................................................................................................ 16
6.2 Vendor Defined Registers (Page ID-00h) ....................................................................................................................... 18
6.2.1 MX60 S/PDIF Input Channel Status [15:0] ............................................................................................................ 18
6.2.2 MX62 S/PDIF Input Channel Status [29:15] .......................................................................................................... 18
6.2.3 MX64 EQualizer Control Index Port....................................................................................................................... 18
6.2.4 MX64 EQualizer Control Data Port ........................................................................................................................ 18
6.2.5 MX6A Data Flow Control....................................................................................................................................... 19
6.3 Discovery Descriptor (Page ID-01h) .............................................................................................................................. 20
6.3.1 MX62 PCI Sub System ID ...................................................................................................................................... 20
6.3.2 MX64 PCI Sub Vendor ID ...................................................................................................................................... 20
6.3.3 MX66 Sense Function Select .................................................................................................................................. 20
6.3.4 MX68 Sense Function Information ......................................................................................................................... 20
6.3.5 MX6A Sense Detail................................................................................................................................................. 21
6.4 Extension Registers......................................................................................................................................................... 22
6.4.1 MX76 GPIO & Interrupt Setup ............................................................................................................................... 22
6.4.2 MX78 GPIO & Interrupt Status .............................................................................................................................. 22
6.4.3 MX7A Miscellaneous Control................................................................................................................................. 23
6.4.4 MX7C Vendor ID1.................................................................................................................................................. 23
6.4.5 MX7E Vendor ID2 .................................................................................................................................................. 23
6.5 EQualizer Control Registers ........................................................................................................................................... 24
7. Electrical Characteristics .................................................................................................................................................... 28
Two Channel AC’97 2.3 Audio Codec
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ALC250 Data Sheet
7.1 DC Characteristics .......................................................................................................................................................... 28
7.1.1 Absolute Maximum Ratings .................................................................................................................................... 28
7.1.2 Threshold Hold Voltage .......................................................................................................................................... 28
7.1.3 Digital Filter Characteristics.................................................................................................................................... 28
7.1.4 S/PDIF output Characteristics ................................................................................................................................. 28
7.2 AC Timing Characteristics.............................................................................................................................................. 29
7.2.1 Cold Reset ............................................................................................................................................................... 29
7.2.2 Warm Reset ............................................................................................................................................................. 29
7.2.3 AC-Link Clocks....................................................................................................................................................... 29
7.2.4 Data Output and Input Timing................................................................................................................................. 30
7.2.5 Signal Rise and Fall Timing .................................................................................................................................... 30
7.2.6 AC-Link Low Power Mode Timing ........................................................................................................................ 31
7.2.7 ATE Test Mode ....................................................................................................................................................... 31
7.2.8 AC-Link IO Pin Capacitance and Loading.............................................................................................................. 31
7.2.9 SPDIF Output .......................................................................................................................................................... 32
8. Analog Performance Characteristics ................................................................................................................................. 33
9. Design Suggestions ............................................................................................................................................................... 35
9.1 Clocking .......................................................................................................................................................................... 35
Low................................................................................................................................................................................... 35
0 (Primary)........................................................................................................................................................................ 35
9.2 AC-Link .......................................................................................................................................................................... 35
9.3 Reset................................................................................................................................................................................ 35
9.4 CD Input.......................................................................................................................................................................... 36
9.5 Odd Addressed Register Access ..................................................................................................................................... 36
9.6 Power-down Mode.......................................................................................................................................................... 36
9.7 Test Mode ....................................................................................................................................................................... 36
9.7.1 ATE In Circuit Test Mode....................................................................................................................................... 36
9.7.2 Vendor Specific Test Mode..................................................................................................................................... 36
9.8 DC Voltage Volume Control .......................................................................................................................................... 37
9.9 POWER OFF CD Function............................................................................................................................................. 38
10. Application Circuit ............................................................................................................................................................ 39
11. Mechanical Dimensions ..................................................................................................................................................... 41
11. Mechanical Dimensions ..................................................................................................................................................... 41
Two Channel AC’97 2.3 Audio Codec
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ALC250 Data Sheet
1. Features
Multiple CODEC extension capability
External Amplifier Power Down (EAPD)
capability
Power management and enhanced power saving
features
Stereo MIC record for AEC/BF application
DC Voltage volume control
Auxiliary power to support Power Off CD
Adjustable VREFOUT control
EQ operation can be controlled by 2 pins of
serial bus
2 Universal Audio Jack (UAJ)® for front panel
Support 32K/44.1K/48K/96KHz of S/PDIF output
Support 32K/44.1K/48KHz of S/PDIF input
Power support: Digital: 3.3V; Analog: 3.3V/5V
Standard 48-Pin LQFP Package
EAX™ 1.0&2.0 compatible
Direct Sound 3D™ compatible
A3D™ compatible
I3DL2 compatible
HRTF 3D Positional Audio
Sensaura™ 3D Enhancement (optional)
10 Bands of Software Equalizer
Voice Cancellation and Key Shifting in Kara
OK mode
AVRack® Media Player
Configuration Panel to improve Experience of
User
Built- in 7 Bands of Digital Hardware Equalizer
for Optimizing Speaker Response
Single chip with high S/N ratio (>100 dB)
Meets performance requirements for audio on
PC99/2001 systems
Meets Microsoft WHQL/WLP 2.0 audio
requirements
20-bit DAC and 18-bit ADC resolution
Compliant with AC’97 2.3 specifications
-LINE/HP-OUT, MIC-IN and LINE-IN sensing
-14.318MHz- 24.576MHz PLL saves crystal
-12.288MHz BITCLK input can be consumed
-Integrated PCBEEP generator to save buzzer
-Interrupt capability
-Page registers and Analog Plug&Play
Support of S/PDIF out is fully compliant with
AC’97 rev2.3 specifications
Three analog line-level stereo inputs with 5-bit
volume control: LINE_IN, CD, AUX
High quality differential CD input
Two analog line-level mono input: PCBEEP,
PHONE-IN
Supports double sampling rate (96KHz) of DVD
audio playback
Two software selectable MIC inputs
+6/12/20/30dB boost preamplifier for MIC input
Stereo output with 6-bit volume control
Mono output with 5-bit volume control
Headphone output with 50mW/20Ω amplifier
3D Stereo Enhancement
2. General Description
The ALC250 is a 20-bit DAC and 18-bit ADC full duplex AC'97 2.3 compatible stereo audio CODEC designed for PC multimedia
systems, including host/soft audio and AMR/CNR based designs. The ALC250 incorporates proprietary converter technology to
achieve a high SNR, greater than 100 dB, sensing logics for device reporting and Universal Audio Jack® to improve user interface.
The ALC250 AC'97 CODEC supports multiple CODEC extensions with independent variable sampling rates and built-in 3D
effects. The ALC250 CODEC provides two pairs of stereo outputs with independent volume controls, a mono output, and multiple
stereo and mono inputs, along with flexible mixing, gain and mute functions to provide a complete integrated audio solution for
PCs. The circuitry of the ALC250 CODEC operates from a +3.3V digital power and +5V analog power supply with EAPD
(External Amplifier Power Down) control for use in notebook and PC applications. The ALC250 integrates a 50mW/20Ω headset
audio amplifier into the CODEC, saving BOM costs. The ALC250 also supports the SPDIF out function, which is compliant to
AC'97 2.3, which can offer easy connection of PCs to consumer electronic products, such as AC3 decoder/speaker and mini disk
devices. The ALC250 CODEC supports host/soft audio from Intel ICHx chipsets as well as audio controller based
VIA/SIS/ALI/AMD/nVIDIA/ ATI chipset. Bundled Windows series drivers (WinXP/ME/2000/98/NT), EAX/ Direct Sound 3D/
I3DL2/ A3D compatible sound effect utilities (supporting Karaoke, 26-kind of environment sound emulation, 10-band of software
equalizer), HRTF 3D positional audio and Sensaura™ 3D (optional) provide an excellent entertainment package and game
experience for PC users. Integrated 14.318M 24.576MHz PLL generate required clock to eliminate the need for external crystal.
Besides, ALC250 also built in seven bands of digital hardware equalizer cascades one lowpass filter, five bandpass filters and one
highpass filter. It is for optimizing frequency response of speaker on mobil PCs.
.
Two Channel AC’97 2.3 Audio Codec
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Two Channel AC’97 2.3 Audio Codec
AUX-IN
CD-IN
LINE-IN
MIC2
PHONE
MIC1
mono analog
stereo analog
1
0*
MX6A.7
MX20.8
0*
Boost
1
Boost
0*
MX6A.6
1
Boost
2
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* : default setting
PC-BEEP
DAC output
MX16
MX12
MX10
MX0E
MX0C
MX0A
MX18
Record
Gain
MX1E
MX6A.8
MX1A
MX1C
Record
Gain
1*
0
left channel
right channel
M
U
X
MX6A.14
stereo mix
mono mix
phone
mic-L
mic-R
line
CD
aux
3D
MX22
1
0*
Mono
Volume
MX06
MX02
Master
Volume
ADC
MONO-OUT
LINE-OUT
HP-OUT
ALC250
RESET#
Yes
No
AMP
MIC&EQ ADC
MX04
HeadPhone
Volume
ALC250 Data Sheet
3. Block Diagram
3.1 Analog Mixer
Figure. Analog Mixer Diagram
Rev1.01
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ALC250 Data Sheet
3.2 Digital Data Path
SPDIF
Input
20-bit SPDIF In
20-bit SPDIF Out
1
0
0
1
SPDIF
Output
Digital Process Engine
ACLINK
0
20-bit PCM
Digital
EQ
DVOL
1
DVOL
1
0
Digital
3D
DAC
1 0
Left
1
0
1 0
Right
Digital Stereo
Digital Mono
Analog Stereo
Analog Mono
Original
ADC
Line-In
Mixer
Block
EQ&MIC
ADC
Left
CD-In
MIC-In
...
Analog outputs
DVOL : Digital Volume Control
Figure. Digial Data Path Diagram
Two Channel AC’97 2.3 Audio Codec
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ALC250 Data Sheet
LINE-OUT-R
LINE-OUT-L
VAUX
VREFOUT2
DCVOL
NC
AFILT2
AFILT1
VREFOUT
VREF
AVSS1
AVDD1
4. Pin Assignments
36 35 34 33 32 31 30 29 28 27 26 25
37
38
39
40
41
42
43
44
45
46
47
48
ALC250
1 2 3 4 5 6 7 8 9 10 11 12
24
23
22
21
20
19
18
17
16
15
14
13
LINE-IN-R
LINE-IN-L
MIC2
MIC1
CD-R
CD-GND
CD-L
JD1
JD2
AUX-R
AUX-L
PHONE
DVDD1
XTL-IN
XTL-OUT
DVSS1
SDATA-OUT
BIT-CLK
DVSS2
SDATA-IN
DVDD2
SYNC
RESET#
PC-BEEP
MONO-OUT/VREFOUT3
AVDD2
HP-OUT-L
NC
HP-OUT-R
AVSS2
SCK
SDA
NC
XTLSEL
SPDIFI/EAPD
SPDIFO
Two Channel AC’97 2.3 Audio Codec
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ALC250 Data Sheet
5. Pin Description
In order to reduce pin count, and therefore size and cost, some pins have multiple functions. In those cases, the functions are
separated with a “/” symbol. Refer to the Pin Assignment diagram for a graphical representation.
5.1 Digital I/O Pins
Name
RESET#
XTL-IN
Type Pin No
Description
I
11
AC'97 H/W reset
I
2
Crystal input pad
XTL-OUT
O
3
Crystal output pad
SYNC
BIT-CLK
SDATA-OUT
I
O
I
10
6
5
SDATA-IN
O
8
SCK
SDA
XELSEL
I
IO
I
43
44
46
SPDIFI/EAPD
I/O
47
SPDIFO
O
48
Sample Sync (48KHz)
12.288MHz bit clock output
Serial TDM input from
AC’97 controller
Serial TDM AC’97 Codec
output
Serial bit clock input
Serial data input/output
Pulled low to use external
14.318MHz clock source
S/PDIF input / External
Amplifier power down
control
S/PDIF output
Characteristic Definition
Schmitt trigger input
Crystal: 24.576M/14.318M crystal input
External: 24.576M/14.318M external clock input
Crystal: 24.576M/14.318M crystal output
External: 24.576M/14.318M clock output
Schmitt trigger input
CMOS output
CMOS input , Vt=1.65V
CMOS output
Schmitt trigger input, VIL=1.0V, VIH=2.0V
Schmitt trigger input, VIL=1.0V, VIH=2.0V
CMOS input, Vt=0.35Vdd, internally pulled high by a 50K
resistor.
CMOS input / output
Digital output has 12 [email protected] driving capability.
Total: 12 Pins
5.2 Analog I/O Pins
Name
PC-BEEP
PHONE
AUX-L
AUX-R
JD2
JD1
CD-L
CD-GND
CD-R
MIC1
MIC2
LINE-IN-L
LINE-IN-R
LINE-OUT-L
LINE-OUT-R
HP-OUT-L
Type Pin No
I
12
I
13
IO
14
IO
15
I
16
I
17
I
18
I
19
I
20
I
21
I
22
I
23
I
24
O
35
O
36
IO
39
HP-OUT-R
IO
41
MONO-OUT/
VREFOUT3
O
37
Description
PC speaker input
Speakerphone input
AUX Left channel
AUX Right channel
Jack Detect pin-2
Jack Detect pin-1
CD audio Left channel
CD audio analog GND
CD audio Right channel
First MIC input
Second MIC input
Line input Left channel
Line input Right channel
Line-Out Left channel
Line-Out Right channel
Headphone Out Left
channel
Headphone Out Left
channel
Mono output /
Third reference voltage
Characteristic Definition
Analog input (1.6Vrms)
Analog input (1.6Vrms)
Analog input/output
Analog input/output
Internally pulled high to AVDD by a 50K resistor
Internally pulled high to AVDD by a 50K resistor
Analog input (1.6Vrms)
Analog input
Analog input (1.6Vrms)
Analog input (1.6Vrms)
Analog input (1.6Vrms)
Analog input (1.6Vrms)
Analog input (1.6Vrms)
Analog output w/o amplifier
Analog output w/o amplifier
ALC250: Analog output with amplifier / Analog input
ALC250: Analog output with amplifier / Analog input
Analog output / Voltage output (2.5V/4.0V)
Total: 18 Pins
Two Channel AC’97 2.3 Audio Codec
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ALC250 Data Sheet
5.3 Filter/Reference/NC
Name
VREF
VREFOUT
AFILT1
AFILT2
NC
DC VOL
Type Pin No
27
O
28
29
30
31
I
32
VREFOUT2
VREFOUT3
VAUX
O
O
I
33
37
34
NC
NC
-
40
45
Description
Reference voltage
Ref. voltage out
ADC anti-aliasing filter
ADC anti-aliasing filter
Not Connection
DC
Voltage
Volume
Control
Secondary Ref. voltage out
Third Ref. voltage out
Auxiliary Power to keep CD
and amplifier turned on.
Not Connection
Not Connection
Characteristic Definition
1uf capacitor to analog ground
Analog DC voltage output (2.5V / 4.0V)
1000pf capacitor to analog ground.
1000pf capacitor to analog ground.
Analog Input (AGND~AVDD)
Analog DC voltage output (2.5V / 4.0V)
Analog DC voltage output (2.5V / 4.0V)
+5V analog stand-by power
Total: 11 Pins
5.4 Power/Ground
Name
AVDD1
AVDD2
AVSS1
AVSS2
DVDD1
DVDD2
DVSS1
DVSS2
Type Pin No
I
25
I
38
I
26
I
42
I
1
I
9
I
4
I
7
Description
Analog VDD (5.0V or 3.3V)
Analog VDD (5.0V or 3.3V)
Analog GND
Analog GND
Digital VDD (3.3V)
Digital VDD (3.3V)
Digital GND
Digital GND
Characteristic Definition
Total: 8 Pins
Two Channel AC’97 2.3 Audio Codec
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ALC250 Data Sheet
6. Registers
6.1 Mixer Registers
Access to registers with an odd number will return a 0. Reading unimplemented registers will also return a 0. X=Reserved bit.
REG.
(HEX)
00h
02h
NAME
Reset
Master
Volume
04h Headphone
volume
06h
Mono-Out
Volume
0Ah
PC_BEEP
Volume
0Ch
PHONE
Volume
0Eh MIC Volume
10h
Line-In
Volume
12h CD Volume
16h Aux Volume
18h
PCM Out
Volume
1Ah
Record
Select
1Ch
ADC
Record Gain
1Eh
MIC ADC
Record Gain
20h
General
Purpose
22h 3D Control
24h Audio Int. &
Paging
26h Power Down
Ctrl/Status
28h
Extended
Audio ID
2Ah
Extended
Audio Status
2Ch PCM front
Out Sample
Rate
32h PCM Input
Sample Rate
34h
MIC Input
Sample Rate
3Ah S/PDIF Ctl
60h/
6Eh
76h
78h
7Ch
7Eh
D15 D14 D13 D12 D11 D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0 DEFAU
LT
X SE4 SE3 SE2 SE1 SE0 ID9 ID8 ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0 0190h
Mute X ML5 ML4 ML3 ML2 ML1 ML0 RM* X MR5 MR4 MR3 MR2 MR1 MR0 8000h
Mute
X
HPL HPL HPL HPL HPL HPL RM*
5
4
3
2
1
0
X
X
X
X
X
X
X
Mute
X
Mute
X
X
F7
F6
F5
F4
F3
F2
F1
Mute
X
X
X
X
X
X
X
X
X
X
PH4 PH3 PH2 PH1 PH0 8008h
Mute
X
X
X
X
X
X
MI4 MI3 MI2 MI1 MI0 8008h
Mute
X
X
BGO BGO X BC
1
0
NL4 NL3 NL2 NL1 NL0 RM* X
X
NR4 NR3 NR2 NR1 NR0 8808h
Mute
Mute
Mute
X
X
X
X
X
X
CL4 CL3 CL2 CL1 CL0 RM*
AL4 AL3 AL2 AL1 AL0 RM*
PL4 PL3 PL2 PL1 PL0 RM*
X
X
X
X
X
X
CR4 CR3 CR2 CR1 CR0 8808h
AR4 AR3 AR2 AR1 AR0 8808h
PR4 PR3 PR2 PR1 PR0 8808h
X
X
X
X
X
X
X
X
Mute
X
X
X
X
X
X
Mute
X
X
X
X
X
X
POP
X
3D
X
X
X
X
X
I4
X
I3
X
I2
X
I1
LRG
3
LM
RG3
DRS
S1
X
I0
RRS
2
RRG RRG
3
2
RM RM
RG3 RG2
X
X
X
X
X
X
X
X
X DP2 DP1 DP0 0000h
PG3 PG2 PG1 PG0 0000h
LRS
2
LRG
2
LM
RG2
DRS
S0
X
X
LRS
1
LRG
1
LM
RG1
MIX
X
X
X
X
LRS X
0
LRG X
0
LM X
RG0
MS LBK
X
X
X
X
HPR HPR HPR HPR HPR HPR 8000h
5
4
3
2
1
0
X MM MM MM MM MM 8000h
4
3
2
1
0
F0 PB3 PB2 PB1 PB0 X 8000h
X
RRS
1
RRG
1
RM
RG1
X
RRS
0
RRG
0
RM
RG0
X
EAP PR6 PR5 PR4 PR3 PR2 PR1 PR0 X
X
X
X REF ANL DAC ADC
D
ID1 ID0 X
X REV REV AM X
X
X
X
X
X SPD DRA VRA
1
0
AP
IF
X
X
X
X
X SPC X
X
X
X SPS SPS X SPD DRA VRA
V
A1 A0
IF
FSR FSR FSR FSR FSR FSR FSR FSR FSR FSR FSR FSR FSR FSR FSR FSR
15 14 13
12
11 10
9
8
7
6
5
4
3
2
1
0
ISR
15
MSR
15
V
Vendor
0
Define
GPIO Setup 0
GPIO Status 0
Vendor ID1 F7
Vendor ID2 T7
ISR
14
MSR
14
DRS
ISR
12
MSR
12
SPS
R0
0
ISR
11
MSR
11
L
0
ISR
13
MSR
13
SPS
R1
0
0
0
F6
T6
0
0
F5
T5
0
0
F4
T4
0
0
F3
T3
Two Channel AC’97 2.3 Audio Codec
0
0000h
8000h
8000h
0400h
000Fh
0A07h
0000h
BB80h
ISR ISR ISR ISR ISR ISR ISR ISR ISR ISR ISR BB80h
10
9
8
7
6
5
4
3
2
1
0
MSR MSR MSR MSR MSR MSR MSR MSR MSR MSR MSR BB80h
10
9
8
7
6
5
4
3
2
1
0
CC6 CC5 CC4 CC3 CC2 CC1 CC0 PRE COP /AU PRO 2000h
Y DIO
0
0
0
0
0
0
0
0
0
0
0 0000h
0
0
F2
T2
0
0
F1
T1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
F0 S7 S6 S5 S4 S3 S2 S1 S0
T0 DEV DEV DEV DEV DEV DEV DEV DEV
7
6
5
4
3
2
1
0
7
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0000h
0000h
414Ch
4750h
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ALC250 Data Sheet
6.1.1 MX00 Reset
Default: 0190h
Writing any value to this register will start a register reset, and causes all of the registers to revert to their default values, then the
written data is ignored. Reading this register returns the ID code of the specific part.
Bit
Type
Function
15
Reserved
14:10
R
Return 00000b
9
R
Read as 0 (No support for 20-bit ADC)
8
R
Read as 1 (Support for 18-bit ADC)
7
R
Read as 1 (Support for 20-bit DAC)
6
R
Read as 0 (No support for 18-bit DAC)
5
R
Read as 0 (No support for Loudness)
4
R
Read as 1 (Headphone output support)
3
R
Read as 0 (No simulated stereo; for analog 3D block use)
2
R
Read as 0 (No Bass & Treble Control)
1
R
Reserved, Read as 0
0
R
Read as 0 (No dedicated MIC PCM input)
6.1.2 MX02 Master Volume
Default: 8000h
These registers control the overall volume level of the output functions. Each step on the left and right channels correspond to
1.5dB in increase/decrease in volume.
Bit
Type
Function
15
R/W Mute Control 0: Normal 1: Mute (-∞ dB)
14
Reserved
13:8
R/W Master Left Volume (MLV[5:0]) in 1.5 dB steps
7:6
Reserved
5:0
R/W Master Right Volume (MRV[5:0]) in 1.5 dB steps
For MRV/MLV: 00h
0 dB attenuation
3Fh
94.5 dB attenuation
6.1.3 MX04 Headphone
Default: 8000h
Register 04h controls the headphone (ALC250) output volume. Each step in bits 5:0 and 13:8 correspond to 1.5dB in
increase/decrease in volume, allowing 63 levels of volume, from 000000 to 111111.
Bit
Type
Function
15
R/W Mute Control 0: Normal 1: Mute (-∞ dB)
14
Reserved
13:8
R/W Headphone/True Line Output Left Volume (HPL[5:0]) in 1.5 dB steps
7:6
Reserved
5:0
R/W Headphone/True Line Output Right Volume (HPR[5:0]) in 1.5 dB steps
For HPR/HPL: 00h
0 dB attenuation
3Fh
94.5 dB attenuation
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ALC250 Data Sheet
6.1.4 MX06 MONO_OUT Volume
Default: 8000h
Register 06h controls the mono volume output. Mono output is the same data sent on all output channels. Each step in bits 4:0
correspond to 1.5dB in increase/decrease in volume, allowing 32 levels of volume from 00000 to 11111.
Bit
Type
Function
15
R/W Mute Control 0: Normal 1: Mute (-∞ dB)
14:5
Reserved
4:0
R/W Mono Master Volume (MMV[4:0]) in 1.5 dB steps
For MMV:
00h
0 dB attenuation
1Fh
46.5 dB attenuation
6.1.5 MX0A PC BEEP Volume
Default: 8000h
This register controls the input volume for the PC beep signal. Each step in bits 4:1 correspond to a 3dB increase/decrease in
volume. 16 levels of volume are available, from 0000 to 1111.
The purpose of this register is to allow the PC Beep signals to pass through the ALC250, eliminating the need for an external system
speaker/buzzer. The PC BEEP pin is directly routed (internally hardwired) to the LINE-OUTL & R pins. If the PC speaker/buzzer is
eliminated, it is recommended to connect the external speakers at all times so the POST codes can be heard during reset.
Bit
Type
Function
15
R/W Mute Control 0: Normal 1: Mute (-∞ dB)
14:13
Reserved
12:5
R/W Internal PCBEEP Frequency, F[7:0]
The internal PCBEEP frequency is the result of dividing the 48KHz clock by 4 times the number specified
in F[7:0].
The lowest tone is 48KHz/(255*4)=47Hz.
The highest tone is 48KHz/(1*4)=12KHz.
A value of 00h in F[7:0] disables internal PCBEEP generator and allows external PCBEEP input.
4:1
R/W PC Beep Volume (PBV[3:0]) in 3 dB steps
0
Reserved
For PBV:
00h
0 dB attenuation
0Fh
45 dB attenuation
6.1.6 MX0C PHONE Volume
Default: 8008h
Register 0Ch controls the telephone input volume for software modem applications. Because software modem applications may
not have a speaker, the CODEC can offer a speaker-out service. Each step in bits 4:0 correspond to 1.5dB in increase/decrease
in volume, allowing 32 levels of volume, from 00000 to 11111.
Bit
Type
Function
15
R/W Mute Control 0: Normal 1: Mute (-∞ dB)
14:5
Reserved
4:0
R/W Phone Volume (PV[4:0]) in 1.5 dB steps
For PV:
00h
+12 dB Gain
08h
0dB gain
1Fh
-34.5dB Gain
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ALC250 Data Sheet
6.1.7 MX0E MIC Volume
Default: 8008h
Register 0Eh controls the microphone input volume. Each step in bits 4:0 correspond to 1.5dB in increase/decrease in volume,
allowing 32 levels of volume, from 00000 to 11111. Bit 6 enables/disables a boost in volume to a magnification based on bits 9:8.
Bit
Type
Function
15
R/W Mute Control 0: Normal 1: Mute (-∞ dB)
14:10
Reserved
9:8
R/W Boost Gain Option (BGO)
00: 20 dB 01: 6 dB 10: 12 dB 11: 29.5 dB (V=30*Vmic-in)
7
Reserved
6
R/W Boost Control (BC)
0: Disable 1: Enable Boost
5
Reserved
4:0
R/W Mic Volume (MV[4:0]) in 1.5 dB steps
For MV:
00h
+12 dB Gain
08h
0dB gain
1Fh
-34.5dB Gain
If 29.5dB boost gain is selected, input resistor can be reduced to save area of feedback resistor.
6.1.8 MX10 LINE_IN Volume
Default: 8808h
Register 10h controls the LINE_IN input volume. Each step in bits 4:0 correspond to 1.5dB in increase/decrease in volume for
the right channel, allowing 32 levels of volume, from 00000 to 11111. Each step in bits 12:8 correspond to 1.5dB in
increase/decrease in volume for the left channel, allowing 32 levels of volume, from 00000 to 11111.
Bit
Type
Function
15
R/W Mute Control 0: Normal 1: Mute (-∞ dB)
14:13
Reserved
12:8
R/W Line-In Left Volume (NLV[4:0]) in 1.5 dB steps
7:5
Reserved
4:0
R/W Line-In Right Volume (NRV[4:0]) in 1.5 dB steps
For NLV/NRV:
00h
+12 dB Gain
08h
0dB gain
1Fh
-34.5dB Gain
6.1.9 MX12 CD Volume
Default: 8808h
Register 12h controls the CD input volume. Each step in bits 4:0 correspond to 1.5dB in increase/decrease in volume for the
right channel, allowing 32 levels of volume, from 00000 to 11111. Each step in bits 12:8 correspond to 1.5dB in
increase/decrease in volume for the left channel, allowing 32 levels of volume, from 00000 to 11111.
Bit
Type
Function
15
R/W Mute Control 0: Normal 1: Mute (-∞ dB)
14:13
Reserved
12:8
R/W CD Left Volume (CLV[4:0]) in 1.5 dB steps
7:5
Reserved
4:0
R/W CD Right Volume (CRV[4:0]) in 1.5 dB steps
For CLV/CRV:
00h
+12 dB Gain
08h
0dB gain
1Fh
-34.5dB Gain
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ALC250 Data Sheet
6.1.10 MX16 AUX Volume
Default: 8808h
Register 16h controls the auxiliary input volume. Each step in bits 4:0 correspond to 1.5dB in increase/decrease in volume for
the right channel, allowing 32 levels of volume, from 00000 to 11111. Each step in bits 12:8 correspond to 1.5dB in
increase/decrease in volume for the left channel, allowing 32 levels of volume, from 00000 to 11111.
Bit
Type
Function
15
R/W Mute Control 0: Normal 1: Mute (-∞ dB)
14:13
Reserved
12:8
R/W AUX Left Volume (ALV[4:0]) in 1.5 dB steps
7:5
Reserved
4:0
R/W AUX Right Volume (ARV[4:0]) in 1.5 dB steps
For ALV/ARV:
00h
+12 dB Gain
08h
0dB gain
1Fh
-34.5dB Gain
6.1.11 MX18 PCM_OUT Volume
Default: 8808h
Register 18h controls the PCM_OUT output volume. Each step in bits 4:0 correspond to 1.5dB in increase/decrease in volume
for the right channel, allowing 32 levels of volume, from 00000 to 11111. Each step in bits 12:8 correspond to 1.5dB in
increase/decrease in volume for the left channel, allowing 32 levels of volume, from 00000 to 11111.
Bit
Type
Function
15
R/W Mute Control 0: Normal 1: Mute (-∞ dB)
14:13
Reserved
12:8
R/W PCM Volume (PLV[4:0]) in 1.5 dB steps
7:5
Reserved
4:0
R/W PCM Right Volume (PRV[4:0]) in 1.5 dB steps
For PLV/PRV:
00h
+12 dB Gain
08h
0dB gain
1Fh
-34.5dB Gain
6.1.12 MX1A Record Select
Default: 0000h
Register 1Ah controls the record input volume. Each step in bits 2:0 correspond to 1.5dB in increase/decrease in volume for the
right channel, allowing 7 levels of volume, from 000 to 111. Each step in bits 10:8 correspond to 1.5dB in increase/decrease in
volume for the left channel, allowing 7 levels of volume, from 000 to 111.
Bit
Type
Function
15:11
Reserved
10:8
R/W Left Record Source Select (LRS[2:0])
7:3
Reserved
2:0
R/W Right Record Source Select (RRS[2:0])
For LRS
0
MIC
1
CD LEFT
2
Muted
3
AUX LEFT
4
LINE LEFT
5
STEREO MIXER OUTPUT LEFT
6
MONO MIXER OUTPUT
7
PHONE
For RRS
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ALC250 Data Sheet
0
1
2
3
4
5
6
7
MIC
CD RIGHT
Muted
AUX RIGHT
LINE RIGHT
STEREO MIXER OUTPUT RIGHT
MONO MIXER OUTPUT
PHONE
6.1.13 MX1C Record Gain for Stereo ADC
Default: 8000h
Register 1Ch controls the record gain. Each step in bits 3:0 correspond to 1.5dB in increase/decrease in gain for the right
channel, allowing 16 levels of gain, from 0000 to 1111. Each step in bits 11:8 correspond to 1.5dB in increase/decrease in gain
for the left channel, allowing 16 levels of gain, from 0000 to 1111.
Bit
Type
Function
15
R/W Mute Control 0: Normal 1: Mute (-∞ dB)
14:12
Reserved
11:8
R/W Left Record Gain Select (LRG[3:0]) in 1.5 dB steps
7:4
Reserved
3:0
R/W Right Record Gain Select (RRG[3:0]) in 1.5 dB steps
For LRG/RRG:
0Fh
+22.5dB
00h
0 dB (No Gain)
6.1.14 MX1E Record Gain for MIC ADC
Default: 8000h
Register 1Eh controls the record gain. Each step in bits 3:0 correspond to 1.5dB in increase/decrease in gain for the right
channel, allowing 16 levels of gain, from 0000 to 1111. Each step in bits 11:8 correspond to 1.5dB in increase/decrease in gain
for the left channel, allowing 16 levels of gain, from 0000 to 1111.
Bit
Type
Function
15
R/W Mute Control 0: Normal 1: Mute (-∞ dB)
14:12
Reserved
11:8
R/W Left Record Gain Select (LMRG[3:0]) in 1.5 dB steps
7:4
Reserved
3:0
R/W Right Record Gain Select (RMRG[3:0]) in 1.5 dB steps
For LRG/RRG:
0Fh
+22.5dB
00h
0 dB (No Gain)
6.1.15 MX20 General Purpose Register
Default: 0000h
This register is used to control several functions. Bit 13 enables or disables 3D control. Bit 9 allows selection of mono output.
Bit 8 controls the MIC selector. Bit 7 enables loopback of the AD output to the DA input without involving the AC-Link,
allowing for full system performance measurements.
Bit
15:14
13
12:9
8
7
6:0
Type
R/W
R/W
R/W
Function
Reserved, Read as 0
3D Control 1: On 0: Off
Reserved, Read as 0
MIC Select 0: MIC 1 1: MIC 2
AD to DA Loop-back Control 0: Disable
Reserved
Two Channel AC’97 2.3 Audio Codec
1: Enable
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ALC250 Data Sheet
6.1.16 MX22 3D Control
Default: 0000h
This register is used to control the 3D stereo enhancement function built into the AC’97 component. The register bits, DP2-DP0
are used to control the separation ratios in the analog 3D and digital 3D for both LINE_OUT and HP_OUT.
The 3D stereo function provides for a deeper and wider sound experience. Note that the 3D bit in the MX20.[13] must be set to
1 to enable this function.
Bit
Type
15:3
Reserved, Read as 0
2:0
R/W Depth Control (DP[2:0])
3D effect control
DP[2:0]
Function
DP[2:0]
000
0% (off)
100
001
12.5%
101
010
25%
110
011
37.5
111
Function
Function
50%
67.5%
75%
100%
6.1.17 MX24 Audio interrupt and Paging
Default: 0000h
Bit
15
Type
14
R
13
R
12
R/W
11
R/W
10:4
3:0
NA
R/W
Function
Interrupt Status, I4
0: Interrupt is clear.
1: Interrupt was generated
Interrupt event and status are clear by writing a 1 to this bit. The status will change regardless of interrupt
enable (I0).
Interrupt Cause, I3
I3=0: GPIO, SPDIF-IN and Jack-Detect interrupt status in MX78 are not changed.
1: GPIO, SPDIF-IN and Jack-Detect interrupt status in MX78 are changed.
I3= (MX78.14|MX78.13|MX78.12|MX78.6|MX78.5|MX78.4)
This bit reflects the cause of the first interrupt event generated. Software should read it after interrupt
status (I4) has been confirmed as interrupting. I3 will be zero when I4 is cleared.
Interrupt Cause, I2
I2=0: Sense value in page ID-01h MX6A.[12:8] has not changed.
1: Sense cycle completed or new sense value in page ID-01h MX6A.[12:8] is available.
This bit reflects the cause of the first interrupt event generated. Software should read it after interrupt
status (I4) has been confirmed as interrupting. I2 will be zero when I4 is cleared.
Sense Cycle, I1
0: Sense cycle not in progress
1: Sense cycle start
Writing a ‘1’ to this bit causes a sense cycle start. If a sense cycle is in progress, writing a ‘0’ to this bit will
abort the sense cycle.
Whether the data in the sense result register (page ID-01h MX6A) is valid or not is determined by the IV
bit in MX6A, Page ID-1h.
Interrupt Enable, I0
0: Interrupt is masked, interrupt status (I4) will not be shown in bit 0 in Slot 12 in SDATA-IN.
1: Interrupt is un-masked, interrupt status (I4) will be shown in bit 0 in Slot 12 in SDATA-IN.
Reserved, read as 0
Page Selector, PG[3:0]
0000b: Vendor Specific
0001b: Page ID 01 (AC’97 2.3 Discovery Descriptor Definition)
Others: Reserved.
This register is used to select a descriptor of 16 word pages between registers MX60 to MX6F. Value of 0
is used to select vendor specific space to maintain compatibility with AC’97 2.2 vendor specific register.
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ALC250 Data Sheet
Once PG[3:0] is not 0000b and 0001b, ALC250 will return zero data for ACLINK mixer read command.
6.1.18 MX26 Powerdown Control/Status
Default: 000Fh
This read/write register is used to program powerdown states and monitor subsystem readiness. The lower half of this register is
read only status; a “1” indicating that the subsection is “ready.” Ready is defined as the subsection’s ability to perform in its nominal
state.
When the AC-Link “CODEC Ready” indicator bit (SDATA_IN slot 0, bit 15) is a 1, it indicates that the AC-Link and AC’97
control and status registers are in a fully operational state. The AC’97 controller must further probe this powerdown control
/status register to determine exactly which subsections, if any are ready.
Bit
Type
Function
15
R/W PR7 External Amplifier Power Down (EAPD) 0: Normal 1: Power down
14
R/W PR6 0: Normal 1: Power down Headphone Out (HP-OUT, pin-39/41)
13
R/W PR5 0: Normal 1: Disable internal clock
12
R/W PR4 0: Normal 1: Power down AC-Link
11
R/W PR3 0: Normal 1: Power down Mixer (Vref off)
10
R/W PR2 0: Normal 1: Power down Mixer (Vref still on)
9
R/W PR1 0: Normal 1: Power down PCM DAC
8
R/W PR0 0: Normal 1: Power down PCM ADC and input MUX
7:4
Reserved, Read as 0
3
R
Vref Status 1: Vref is up to normal level 0: Not yet ready
2
R
Analog Mixer Status 1: Ready 0: Not yet ready
1
R
DAC Status 1: Ready 0: Not yet ready
0
R
ADC Status 1: Ready 0: Not yet ready
True table for power down mode :
ADC
DAC
Mixer
Verf
ACLINK Int CLK HP-OUT EAPD
PR0=1
PD
PR1=1
PD
PR2=1
PD
PD
PR3=1
PD
PD
PD
PD
PD
PR4=1
PD
PD
PD
PR5=1
PD
PD
PD
PR6=1
PD
PR7=1
PD
PD: Power down
Blank: Don’t care
If Mixer is power down (PR2=1 or PR3=1), the LINE-OUT (pin-35/36) is shut down and its output is floated.
If Headphone-Out is power down (PR6=1), the HP-OUT (pin-39/41) is shut down and its output is floated.
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ALC250 Data Sheet
6.1.19 MX28 Extended Audio ID
Default: 0605h
The Extended Audio ID register is a read only register used to communicate information to the digital controller on two functions.
ALC250 is designed as the primary CODEC with ID is ‘00’.
Bit
Type
Function
15:14
R
ID[1:0], read as ‘00’.
13:12
Reserved, Read as 0
11:10
R
REV[1:0]=10 to indicate that the ALC250 is AC’97 rev2.3 compliant
9
R
AMAP read as 1 (DAC mapping based on ID)
8:6
Reserved, Read as 0
5:4
R/W DAC Slot Assignment DSA[1:0] (Default value depends on ID[1:0])
DSA[1:0] Controls the DAC slot assignment, as described in AC’97 rev2.2.
3
Reserved, Read as 0
2
R
SPDIF Read as 1 (S/PDIF is supported)
1
R
DRA Read as 1
0
R
VRA Read as 1 (Variable Rate Audio is supported)
The ALC250 maps DAC slot according to the following table: (default maps to AC’97 spec. rev2.3)
DSA[1:0]
0,0
0,1
1,0
1,1
Left DAC slot #
3
7
6
10
Right DAC slot #
Comment
4
Default when ID[1:0]=00
8
Default when ID[1:0]=01,10
9
Default when ID[1:0]=11
11
-
6.1.20 MX2A Extended Audio Status and Control
Default: 0000h
This register contains two active bits for powerdown and status of the surrounding DACs. Bits 0, 1 & 2 are read/write bits which
are used to enable or disable VRA, DRA and SPDIF respectively. Bits 4 & 5 are read/write bits used to determine the AC-LINK
slot assignment of the S/PDIF. Bit 10 is a read only bit which tells the controller if the S/PDIF configuration is valid.
Bit
Type
Function
15
R/W Validity Configuration of S/PDIF Output (VCFG)
Combines with MX3A.15 to decide validity control in S/PDIF output signal.
14:11
NA
Reserved
10
R
S/PDIF Configuration Valid (SPCV)
0: Current S/PDIF configuration {SPSA,SPSR,DAC/slot rate} is not valid.
1: Current S/PDIF configuration {SPSA,SPSR,DAC/slot rate} is valid.
9:6
Reserved
5:4
R/W SPSA[1:0], S/PDIF Slot Assignment when DRS=0
00: S/PDIF source data assigned to AC-LINK slot3/4
01: S/PDIF source data assigned to AC-LINK slot7/8 (Default when ID=00)
10: S/PDIF source data assigned to AC-LINK slot6/9 (Default when ID=01,10)
11: S/PDIF source data assigned to AC-LINK slot10/11 (Default when ID=11)
SPSA[1:0], S/PDIF-Out Slot Assignment when DRS=1(for 96K S/PDIF-Out)
01: S/PDIF-Out source is from AC-LINK slot3/4 + slot7/8.
3
Reserved
2
R/W SPDIF 1: Enable 0: Disable (SPDIFO is in high impedance)
1
R/W DRA
1: Enable 0: Disable
0
R/W VRA
1: Enable 0: Disable
If VRA = 0, ALC250 ADC/DAC operate at fixed 48KHz sampling rate. Otherwise, it operates with variable
sampling rate defined in MX2C and MX32. VRA also control write operation of MX2Cand MX32.
DRA can be written when (ID=00)&(DSA=00), otherwise it is always 0.
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ALC250 Data Sheet
If DRA = 1, DAC operates at a fixed 96KHz sampling rate. The PCM(n) and PCM(n+1) data is captured in the
same frame. In this mode, MX2C is fixed at BB80h, MX32 and ADC is still controlled by VRA.
SPCV is a read only bit that indicates whether the current S/PDIF-Out configuration is supported or not. If the
configuration is supported, SPCV is set as 1 by H/W. So driver can check this bit to determine the status of the
S/PDIF transmitter system. SPCV is always operating, independent of the SPDIF enable bit (MX2A.2). The
S/PDIF output is active if MX2A.2 is set in spite of SPCV. Once S/PDIF output is enabled but SPCV is invalid
(SPCV=0), channel status is still output, but the output data bits will be all zero.
6.1.21 MX2C PCM DAC Rate
Default: BB80h
The ALC250 allows adjustment of the output sample rate. This register is used to adjust the sample rate. By changing the values,
sampling rates from 8000 to 48000 can be chosen.
Bit
Type
Function
15:0
R/W Output Sampling Rate FOSR[15:0]
The ALC250 supports the following sampling rates, as required in the PC99/PC2001 design guide.
Sampling rate
FOSR[15:0]
8000
1F40h
11025
2B11h
12000
2EE0
16000
3E80h
22050
5622h
24000
5DC0
32000
7D00h
44100
AC44h
48000
BB80h
Note that If the value written is not support, the closest value is returned.
When MX2A.0=0 (VRA is disable), this register will return BB80h when read.
6.1.22 MX32 PCM ADC Rate
Default: BB80h
The ALC250 allows adjustment of the input sample rate. This register is used to adjust the sample rate. By changing the values,
sampling rates from 8000 to 48000 can be chosen.
Bit
Type
Function
15:0
R/W Output Sampling Rate FISR[15:0]
The ALC250 supports the following sampling rates, as required in the PC99/PC2001 design guide.
Sampling rate
FISR[15:0]
8000
1F40h
11025
2B11h
12000
2EE0
16000
3E80h
22050
5622h
24000
5DC0
32000
7D00h
44100
AC44h
48000
BB80h
Note that If the value written is not support, the closest value is returned.
When MX2A.0=0 (VRA is disable), this register will return BB80h when read.
6.1.23 MX3A S/PDIF Out Channel Status/Control
Default: 2000h
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Bit
15
14
13:12
11
10:4
3
2
1
0
Type
R/W
Function
Validity Control (control V bit in Sub-Frame)
0: The V bit (valid flag) in sub-frame depends on whether the S/PDIF data is under-run or over-run.
1: The V bit in sub-frame is always send as 1 to indicate the invalid data is not
suitable for receiver.
R
DRS (Double Rate S/PDIF)
0: 32K, 44.1K, 48K S/PDIF-Out
1: 96K S/PDIF-Out
This bit only can be set when SPSR is 10b.
R/W S/PDIF Sample Rate SPSR[1:0]
00: Sample rate set to 44.1KHz, Fs[0:3]=0000
01: Reserved
10: Sample rate set to 48.0KHz, Fs[0:3]=0100 (default)
11: Sample rate set to 32.0KHz, Fs[0:3]=1100
R/W Generation Level (LEVEL)
R/W Category Code (CC[6:0])
R/W Preemphasis (PRE)
0: None
1: Filter preemphasis is 50/15 usec
R/W Copyright (COPY)
0: Not asserted
1: Asserted
R/W Non-Audio Data type (/AUDIO)
0: PCM data
1: AC3 or other digital non-audio data
R
Professional or Consumer format (PRO)
0: Consumer format
1: Professional format
The ALC250 supports consumer channel status format, so this bit is always 0.
The consumer channel status block (bit0~bit31):
0
1
2
3
4
5
6
7
PRO=0 /AUDIO COPY
PRE
0
0
0
0
8
9
10
11
12
13
14
15
CC0
CC1
CC2
CC3
CC4
CC5
CC6
LEVEL
16
17
18
19
20
21
22
23
0
0
0
0
0
0
0
0
24
25
26
27
28
29
30
31
Fs0
Fs1
Fs2
Fs3
0
0
0
0
The “V” bit in the sub-frame is determined by Validity control (MX3A.15) and VCFG (MX2A.15):
Validity
VCFG
Operation
0
0
If S/PDIF FIFO is under-run, the “V” bit in the sub-frame is set to
indicate that the S/PDIF data is invalid.
0
1
If S/PDIF FIFO is under-run, the “V” bit in the sub-frame is always
0, and pads the data with “0”s.
1
0
The “V” bit is always 1, and data bits (bit 8 ~ bit 27) should be
forced to 0.
1
1
The “V” bit in sub-frame is always “0”, and the S/PDIF output data
should be forced to zero.
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ALC250 Data Sheet
6.2 Vendor Defined Registers (Page ID-00h)
These registers are available to Realtek and Realtek customers for specialized functions.
6.2.1 MX60 S/PDIF Input Channel Status [15:0]
Default: 0000h
The data in MX60 are captured from channel status [15:0] of S/PDIF-IN signal.
Bit
Type
Function
15
R
LEVEL (Generation Level)
14:8
R
CC[6:0] (Category Code)
7:6
R
Mode[1:0]
5:3
R
PRE[2:0] (Pre-Emphasis)
2
R
COPY (Copyright)
0: asserted
1: Not asserted
1
R
/AUDIO (Non-Audio Data type)
0: PCM data
1: AC3 or other digital non-audio data
0
R
PRO (Professional or Consumer format)
0: consumer format
1: professional format
6.2.2 MX62 S/PDIF Input Channel Status [29:15]
Default: 0000h
The data in MX62 are captured from channel status [29:16] of S/PDIF-IN signal.
Bit
Type
Function
15
R
“V” bit in sub-frame of SPDIFI
0: Data X and Y are valid
1: At least one of data X and Y is invalid
This bit is real-time updated, and it is meaning when S/PDIF-IN is locked
14
R
S/PDIF-IN Input Signal Locked by hardware
0: Unlocked
1: Locked
13:12
R
Ca[1:0] ( Clock Accuracy)
11:8
R
Fs[3:0]. (Sample Frequency in channel status)
0000: 44.1KHz
0010: 48 KHz
0011: 32 KHz
Others: Reserved
7:4
R
Cn[3:0] (Channel Number)
3:0
R
Sn[3:0] (Source Number)
6.2.3 MX64 EQualizer Control Index Port
Default: 0000h
Bit
15:6
3:0
Type
NA
R/W
Function
Reserved
EQ Control Registers Index
6.2.4 MX64 EQualizer Control Data Port
Default: 0000h
Bit
15:0
Type
R/W
Function
EQ Control Registers Data
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Data written into this mixer will set the EQ register MX64 points to. Read this mixer will get the register content
MX60 points to.
6.2.5 MX6A Data Flow Control
Default: 0308h
Bit
15
Type
R/W
14
R/W
13:12
R/W
11
R/W
10
R/W
9
R/W
8
R/W
7
R/W
6
R/W
5:4
3:2
NA
R/W
1
R/W
0
R/W
Function
SDATA-IN Slot 6 Source
0: EQ&MIC ADC Left Channel
1: Original ADC Left Channel
Direct DAC Mode
0: Analog output is from summation of DAC and analog inputs.
1: Analog output is from DAC.
S/PDIF Out Source
00: S/PDIF data is from ACLINK controller
01: Reserved.
10: Directly bypass S/PDIF-In signal to S/PDIF-Out.
11: Reserved.
Recorded PCM Data to ACLINK
0: Recorded PCM data to host is from original ADC
1: Recorded PCM data to host is from S/PDIF-IN
DAC Source
0: DAC data is from ACLINK controller.
1: DAC data is from DPE.
DPE (Digital Process Engine) ADC Source
0: EQ&MIC ADC.
1: Original ADC.
EQ&MIC ADC Record Select
0: From mixed signal of MIC, LINE-In, CD-In, AUX-In and VIDEO-In.
1: Left channel is from MIC, right channel is from sum of others.
Data to DPE is composed of right channel and its duplicated one.
MIC2 Source
0: MIC2
1: (MIC1+MIC2)/2.
ADC MIC Source
0: Mono duplicated. (Default) 1: Stereo.
Reserved
Function Selection for pin-47 and pin-16.
MX6A.[3:2]
Pin-47
Pin-16
Note
00
EAPD
(Out) S/PDIF-In (In)
01
EAPD
(Out) JD2
(In)
10
S/PDIF-In (In) JD2
(In) (Default)
11
JD2
(In) S/PDIF-In (In) Compatible with ALC202
S/PDIF-In Enable
0: Disable
1: Enable
S/PDIF-In Monitoring Control
0: Disable, SPDIFI data is not added into PCM data to DAC. (Default)
1: Enable, SPDIFI data will be added into PCM data to DAC after SPDIFI is locked.
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6.3 Discovery Descriptor (Page ID-01h)
These registers are defined in Ac’97 2.3 for sensing and analog plug&play functions.
6.3.1 MX62 PCI Sub System ID
Default: FFFFh
Bit
15:0
Type
R/W
Function
PCI Sub System Vendor ID
This register can be written once only after power on. BIOS can set its own sub-system ID.
The default value FFFFh means this register is implemented and data is not set by BIOS.
6.3.2 MX64 PCI Sub Vendor ID
Default: FFFFh
Bit
15:0
Type
R/W
Function
PCI Vendor ID
This register can be written once only after power on. BIOS can set its own sub-vendor ID.
The default value FFFFh means this register is implemented and data is not set by BIOS.
6.3.3 MX66 Sense Function Select
Default: 0000h
Bit
15:5
4:1
Type
0
R/W
R/W
Function
Reserved
Function Code bits, FC[3:0]
These bits specify the type of audio function described in page ID-01h MX66, MX68 and MX6A.
0h: LINE OUT
1h: HP OUT
5h: MIC1 In
6h: MIC2 In
7h: LINE In
Others: Not supported
Tip or Ring Selection, T/R
This bit sets which jack conductor the sense value is measured from. It is combined with FC[3:0].
0: Tip (Left channel)
1: Ring (Right channel)
6.3.4 MX68 Sense Function Information
Default: 02F1h
Bit
15:11
Type
R/W
10
R/W
9:5
R/W
4
R/W
Function
Gain bits, G[4:0]
These bits are updated by BIOS to tell driver the gain supported by external amplifier. 1 LSB = 1.5dBV
00000b: 0dBV, 00001b: +1.5dBV,… 01111b:+24dBV
10000b: 0dBV, 10001b: -1.5dBV,… 11111b: -24dBV
Inversion bit, INV
0: No inversion reported
1: Inverted.
Buffer delays, DL[4:0]
Delay measurement for the signal from inputs to outputs channels in 20.83 usec (1/48000 second) units.
Information Valid bit, IV
0: After a sense cycle is completed indicates that no information is provided on the sensing method
1: After a sense cycle is completed indicates that information is provided on the sensing method
Clearing this bit by writing “1”, writing “0” to this bit has no effect.
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3:1
0
NA
R
Reserved
Function Information Present, FIP
This bit is set to a ‘1’ indicates that the G[4:0], INV, DL[4:0] and ST[2:0] bits are supported and are
Read/Write capable.
6.3.5 MX6A Sense Detail
Default: 0000h
Bit
15:13
Type
R/W
12:8
R
7:0
R
Function
Connection/Jack Location bits, ST[2:0]
000b: Rear I/O Panel (Default)
001b: Front Panel
010b: Motherboard
011b: Dock/External
100b ~ 110b: Reserved
111b: Unused I/O.
These bits should be written by BIOS to let driver know where those I/O FC[3:0] specify are located.
Sense bits, S[4:0] (Default value depends on sensed result after Cold Reset)
For output devices:
02h: Not specificed or unknown 05h: Powered speaker
06h: Earphone or passive speaker
Other: Not supported
For input deices:
12h: Not specified or unknown
13h: Mono Microphone 15h: Stereo Line-In
Other: Not supported
This field reports the type of output/input peripheral plugged in the jack after sensing.
Always read as 0.
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6.4 Extension Registers
6.4.1 MX76 GPIO & Interrupt Setup
Default: 0000h
Bit
15
Type
R/W
14
R/W
13
R/W
12
R/W
11:7
6
R/W
5:0
Function
GPIO Statue Indication in SDATA_IN
0:The status of JD and its valid tag is not indicated in SDATA_IN.
1: The status of JD and its valid tag is indicated in SDATA_IN
SPDIFI Valid Interrupt Enable
0:Disable
1: Enable
SPDIFI Lock Interrupt Enable
0:Disable
1: Enable
JD2 (Jack-Detect 2) interrupt Enable
0: Disable
1: Enable.
A low to high transaction will trigger the JD2 interrupt in bit0 of SDATA_IN’s slot-12.
Reserved
JD1 (Jack-Detect 1) interrupt Enable
0: Disable
1: Enable.
A low to high transaction will trigger the JD interrupt in bit0 of SDATA_IN’s slot-12.
Reserved
6.4.2 MX78 GPIO & Interrupt Status
Default: 0000h
Bit
15
14
Type
NA
R/W
13
R/W
12
R/W
11:7
6
NA
R/W
5:3
2
NA
R
0
NA
Function
Reserved
S/PDINF-In Valid Interrupt Status (SPDIFIN_VIS).
0: No SPDIFI Valid Interrupt.
1: SPDIFI Valid interrupt.
Write 1 to clear this status bit and its interrupt.
S/PDINF-In Lock Interrupt Status (SPDIFIN_LIS).
0: No SPDIFI Lock interrupt.
1: SPDIFI LOCK interrupt.
Write 1 to clear this status bit and its interrupt.
JD2 Interrupt Status (JD2_IS)
0: No JD2 interrupt.
1: JD2 interrupt.
Write 1 to clear this status bit.
Reserved
JD1 Interrupt Status (JD1_IS)
0: No JD1 interrupt.
1: JD1 interrupt.
Write 1 to clear this status bit.
Reserved
Jack-Detect Event (JDEVT)
0: No Jack-Detect event occurs.
1: Jack-Detect event occurs.
JDEVT = JDS1 | JDS2
Software can check this bit and MX7A.1 to know the status of JDx.
When MX7A.5=0, MX7A.1=JDS1.
When MX7A.5=1, MX7A.1=JDS2.
Reserved
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6.4.3 MX7A Miscellaneous Control
Default: 0000h
Bit
15:11
10
Type
NA
R/W
9
R/W
8
R/W
7:6
5
NA
R/W
4
R/W
3
R/W
2
R/W
1
R
0
R/W
Function
Reserved
Pin-37 Function Selection (MONO-OUT or Vrefout3)
0: Vrefout3
1: MONO-OUT
Vrefout Off Control
0: Vrefout is normal on (output of buffered Vref).
1: Vrefout is off. (In High-Z).
Vrefout / Vrefout2 / Vrefout3 Level Control
0: 2.5V 1: 4.0V
Reserved
Source of Jack-Detect status for MX7A.1
0: MX7A.1 indicates the status of Jack-Detect 1
1: MX7A.1 indicates the status of Jack-Detect 2
HP-OUT Control
0: Normal
1: HP-OUT is muted by H/W when MX7A.1=1
MONO-OUT Control
0: Normal
1: MONO-OUT is muted by H/W when MX7A.1=1
SPDIF Output Gating
0: SPDIF output is not gated with MX7A.1
1: SPDIF output is gated with MX7A.1.
Status of Jack-Detect 1 or 2 (JDSx)
0: JDSx is pull low
1: JDSx is floating or pull high
LINE-OUT Output Control
0: Normal
1: LINE-OUT output is muted by H/W when MX7A.1=1
6.4.4 MX7C Vendor ID1
The two registers (MX7C Vendor ID1 and MX7E Vendor ID2) contain four 8-bit ID codes. The first three codes have been
assigned by Microsoft for Plug and Play definitions. The fourth code is a Realtek assigned code identifying the ALC250. The
MX7C Vendor ID1 register contains the value 414Ch, which is the first and second characters of the Microsoft ID code. The
MX7C Vendor ID2 register contains the value 4750h, which is the third of the Microsoft ID code
Default: 414Ch
Bit
15:0
Type
R
Function
Vendor ID “AL”
6.4.5 MX7E Vendor ID2
Default: 4750h
Bit
15:8
7:0
Type
R
R
Function
Vendor ID - “G”
Device ID – 50h for ALC250
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6.5 EQualizer Control Registers
6.5.1 Index-00h EQ Band-0 Coefficient (Low Pass Filter, LP0: a1)
Default: 0000h
Bit
15:0
Type
R/W
Function
16-bit 2’s complement coefficient. Range= -2 ~ 1.99
6.5.2 Index-02h EQ Band-0 Gain (Low Pass Filter, LP0: Ho)
Default: 0000h
Bit
15:0
Type
R/W
Function
16-bit 2’s complement coefficient. Range= -8 ~ 7.99. (Gain=-20dB ~ +20dB)
6.5.3 Index-03h EQ Band-1 Coefficient (Band Pass Filter, BP1: a1)
Default: 0000h
Bit
15:0
Type
R/W
Function
16-bit 2’s complement coefficient. Range= -2 ~ 1.99
6.5.4 Index-04h EQ Band-1 Coefficient (Band Pass Filter, BP1: a2)
Default: 0000h
Bit
15:0
Type
R/W
Function
16-bit 2’s complement coefficient. Range= -2 ~ 1.99
6.5.5 Index-05h EQ Band-1 Gain (Band Pass Filter, BP1: Ho)
Default: 0000h
Bit
15:0
Type
R/W
Function
16-bit 2’s complement coefficient. Range= -8 ~ 7.99. (Gain=-20dB ~ +20dB)
6.5.6 Index-06h EQ Band-2 Coefficient (Band Pass Filter, BP1: a1)
Default: 0000h
Bit
15:0
Type
R/W
Function
16-bit 2’s complement coefficient. Range= -2 ~ 1.99
6.5.7 Index-07h EQ Band-2 Coefficient (Band Pass Filter, BP1: a2)
Default: 0000h
Bit
15:0
Type
R/W
Function
16-bit 2’s complement coefficient. Range= -2 ~ 1.99
6.5.8 Index-08h EQ Band-2 Gain (Band Pass Filter, BP2: Ho)
Default: 0000h
Bit
15:0
Type
R/W
Function
16-bit 2’s complement coefficient. Range= -8 ~ 7.99. (Gain=-20dB ~ +20dB)
6.5.9 Index-09h EQ Band-3 Coefficient (Band Pass Filter, BP3: a1)
Default: 0000h
Bit
Type
Two Channel AC’97 2.3 Audio Codec
Function
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15:0
R/W
16-bit 2’s complement coefficient. Range= -2 ~ 1.99
6.5.10 Index-0Ah EQ Band-3 Coefficient (Band Pass Filter, BP3: a2)
Default: 0000h
Bit
15:0
Type
R/W
Function
16-bit 2’s complement coefficient. Range= -2 ~ 1.99
6.5.11 Index-0Bh EQ Band-3 Gain (Band Pass Filter, BP3: Ho)
Default: 0000h
Bit
15:0
Type
R/W
Function
16-bit 2’s complement coefficient. Range= -8 ~ 7.99. (Gain=-20dB ~ +20dB)
6.5.12 Index-0Ch EQ Band-4 Coefficient (Band Pass Filter, BP4: a1)
Default: 0000h
Bit
15:0
Type
R/W
Function
16-bit 2’s complement coefficient. Range= -2 ~ 1.99
6.5.13 Index-0Dh EQ Band-4 Coefficient (Band Pass Filter, BP4: a2)
Default: 0000h
Bit
15:0
Type
R/W
Function
16-bit 2’s complement coefficient. Range= -2 ~ 1.99
6.5.14 Index-0Eh EQ Band-4 Gain (Band Pass Filter, BP4: Ho)
Default: 0000h
Bit
15:0
Type
R/W
Function
16-bit 2’s complement coefficient. Range= -8 ~ 7.99. (Gain=-20dB ~ +20dB)
6.5.15 Index-0Fh EQ Band-5 Coefficient (Band Pass Filter, BP5: a1)
Default: 0000h
Bit
15:0
Type
R/W
Function
16-bit 2’s complement coefficient. Range= -2 ~ 1.99
6.5.16 Index-10h EQ Band-5 Coefficient (Band Pass Filter, BP5: a2)
Default: 0000h
Bit
15:0
Type
R/W
Function
16-bit 2’s complement coefficient. Range= -2 ~ 1.99
6.5.17 Index-11h EQ Band-5 Gain (Band Pass Filter, BP5: Ho)
Default: 0000h
Bit
15:0
Type
R/W
Function
16-bit 2’s complement coefficient. Range= -8 ~ 7.99. (Gain=-20dB ~ +20dB)
6.5.18 Index-12h EQ Band-6 Coefficient (High Pass Filter, HP6: a1)
Default: 0000h
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Bit
15:0
Type
R/W
Function
16-bit 2’s complement coefficient. Range= -2 ~ 1.99
6.5.19 Index-13h EQ Band-6 Coefficient (High Pass Filter, HP6: a2)
Default: 0000h
Bit
15:1
0
Type
NA
R/W
Function
Reserved
0: 20dB/decade slope
1: 40dB/decade slope (2 cascaded HP6)
6.5.20 Index-20h EQ Control & Status Register
Default: 0000h
Bit
15
Type
R/W
Function
Digital Process Engine Output Control
0: Bypass digital EQ (Default)
1: Digital EQ output.
14
R/W EQ Band-6 Control. 0: Disable
1: Enable.
13
R/W EQ Band-5 Control. 0: Disable
1: Enable.
12
R/W EQ Band-4 Control. 0: Disable
1: Enable.
11
R/W EQ Band-3 Control. 0: Disable
1: Enable.
10
R/W EQ Band-2 Control. 0: Disable
1: Enable.
9
R/W EQ Band-1 Control. 0: Disable
1: Enable.
8
R/W EQ Band-0 Control. 0: Disable
1: Enable.
7
R/W Bypass Digital EQ Control by JDx
0:Normal, bypass EQ control is decided by EQ Control&Status register Index-20h.15 (Default)
1: Bypass digital EQ by H/W when MX7A.1=1
The EQ function is planned to compensate frequency response for mini speaker, it should be bypassed
when headphone jack is plugged to be output device.
6
R
EQ Band-6 Status. 0: Normal
1: Overflow.
This bit is set if overflow had ever occurred. Write 1 to clear it.
5
R
EQ Band-5 Status. 0: Normal
1: Overflow.
This bit is set if overflow had ever occurred. Write 1 to clear it.
4
R
EQ Band-4 Status. 0: Normal
1: Overflow.
This bit is set if overflow had ever occurred. Write 1 to clear it.
3
R
EQ Band-3 Status. 0: Normal
1: Overflow.
This bit is set if overflow had ever occurred. Write 1 to clear it.
2
R
EQ Band-2 Status. 0: Normal
1: Overflow.
This bit is set if overflow had ever occurred. Write 1 to clear it.
1
R
EQ Band-1 Status. 0: Normal
1: Overflow.
This bit is set if overflow had ever occurred. Write 1 to clear it.
0
R
EQ Band-0 Status. 0: Normal
1: Overflow.
This bit is set if overflow had ever occurred. Write 1 to clear it.
Write to EQ coefficient-{a1,a1,Ho} will be ignored when specific control bit is enabled, it means modify individual EQ
coefficients is forbidden when EQ is working.
6.5.21 Index-21h EQ PCM Digital Volume Control
Default: 007Fh
Bit
15
14:7
Type
R/W
Function
Mute Control.
0: Turn on
1: Mute, force data to zero. (-∞ dB)
Reserved
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6:0
R/W
7-bit Volume Ratio, EQVR[7:0]
The multiplier ratio is EQVR[7:0]/128. (1/128 ~ 1)
If 7-bit volume ratio is 7Fh, it means the multiplier is 1 (0dB).
6.5.22 Index-22h EQ MIC ADC Digital Volume Control
Default: 007Fh
Bit
15
Type
R/W
Function
Mute Control.
0: Turn on
1: Mute, force data to zero. (-∞ dB)
14:7
Reserved
6:0
R/W 7-bit Volume Ratio, EQMICVR[7:0]
The multiplier ratio is EQMICVR[7:0]/128. (1/128 ~ 1)
If 7-bit volume ratio is 7Fh, it means the multiplier is 1 (0dB).
Two Channel AC’97 2.3 Audio Codec
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ALC250 Data Sheet
7. Electrical Characteristics
7.1 DC Characteristics
7.1.1 Absolute Maximum Ratings
Parameter
Power Supplies
Symbol
Minimum
Typical
Maximum
Units
Digital
Analog
Operating Ambient Temperature
Storage Temperature
DVDD
AVDD
Ta
Ts
3.0
3.0
0
3.3
5.0
-
3.6
5.5
+70
+125
V
V
o
C
o
C
7.1.2 Threshold Hold Voltage
Dvdd= 3.3V±5%, Tambient=250C, with 50pF external load.
Parameter
Symbol
Input voltage range
Vin
Low level input voltage
VIL
(AC-LINK, XTAL-IN/OUT)
Low level input voltage
VIL
(SCK,SDA)
Low level input voltage
VIL
(JD1, JD2)
High level input voltage
VIH
(AC-LINK, XTAL-IN/OUT)
High level input voltage
VIH
(SCK, SDA)
High level input voltage
VIH
(JD1, JD2)
High level output voltage
VOH
Low level output voltage
VOL
Input leakage current
Output leakage current
(Hi-Z)
Output buffer drive current
Internal pull up resistance
-
Minimum
-0.30
-
Typical
-
Maximum
Dvdd+0.30
0.50*Dvdd
Units
V
V
-
-
1.0
V
-
-
2.0
V
0.5*DVdd
-
-
V
2.0
-
-
V
-
V
2.0
0.9DVdd
-10
-10
-
0.1DVdd
10
10
V
V
µA
µA
30k
5
50k
100k
mA
Ω
Maximum
20.0
Units
KHz
KHz
dB
dB
20.0
KHz
KHz
dB
dB
7.1.3 Digital Filter Characteristics
Filter
ADC Lowpass Filter
DAC Lowpass Filter
Symbol
Passband
Stopband
Stopband Rejection
Passband
Frequency Response
Passband
Stopband
Stopband Rejection
Passband
Frequency Response
Minimum
10
28.8
Typical
-76.0
+- 0.20
10
28.8
-78.5
+- 0.20
7.1.4 S/PDIF output Characteristics
Dvdd= 3.3V, Tambient=250C, with 75Ω external load.
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ALC250 Data Sheet
Parameter
High level output voltage
Low level output voltage
Symbol
VOH
VOL
Minimum
3.0
-
Typical
3.3
0
Maximum
0.5
Units
V
V
Typical
-
Maximum
-
Units
µs
ns
Typical
-
Maximum
-
Units
µs
ns
Maximum
750
45
45
-
Units
MHz
ns
ps
ns
ns
KHz
µs
µs
µs
7.2 AC Timing Characteristics
7.2.1 Cold Reset
Parameter
RESET# active low pulse width
RESET# inactive to BIT_CLK
Startup delay
Symbol
Trst_low
Trst2clk
Minimum
1.0
162.8
Cold reset timing diagram
7.2.2 Warm Reset
Parameter
SYNC active high pulse width
SYNC inactive to BIT_CLK
Startup delay
Symbol
Tsync_high
Tsync2clk
Minimum
1.0
162.8
Warm reset timing diagram
7.2.3 AC-Link Clocks
Parameter
Symbol
BIT_CLK frequency
BIT_CLK period
Tclk_period
BIT_CLK output jitter
BIT_CLK high pulse width (note 2)
Tclk_high
BIT_CLK low pulse width (note 2)
Tclk_low
SYNC frequency
SYNC period
Tsync_period
SYNC high pulse width
Tsync_high
SYNC low pulse width
Tsync_low
Note 1: Worse case duty cycle restricted to 45/55.
Two Channel AC’97 2.3 Audio Codec
Minimum
36
36
-
Typical
12.288
81.4
40.7
40.7
48.0
20.8
1.3
19.5
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ALC250 Data Sheet
BIT_CLK and SYNC timing diagram
7.2.4 Data Output and Input Timing
Parameter
Symbol
Minimum
Typical
Maximum
Output Valid Delay from rising
tco
15
edge of BIT_CLK
Note 1: Timing is for SDATA and SYNC outputs with respect to BIT_CLK at the device driving the output.
Note 2: 50pF external load
Units
ns
Parameter
Symbol
Minimum
Typical
Maximum
Input Setup to falling edge of
tsetup
10
BIT_CLK
Input Hold from falling edge of
thold
10
BIT_CLK
Note: Timing is for SDATA and SYNC outputs with respect to BIT_CLK at the device driving the output.
Units
ns
Parameter
Symbol
Minimum
Typical
Maximum
BIT_CLK combined rise or fall
7
plus flight time
SDATA combined rise or fall plus
7
flight time
Note: Combined rise or fall plus flight times are provided for worst case scenario modeling purposes.
Units
ns
ns
ns
Data Output and Input timing diagram
7.2.5 Signal Rise and Fall Timing
Parameter
Symbol
BIT_CLK rise time
Triseclk
BIT_CLK fall time
Tfallclk
SYNC rise time
Trisesync
SYNC fall time
Tfallsync
SDATA_IN rise time
Trisedin
SDATA_IN fall time
Tfalldin
SDATA_OUT rise time
Trisedout
SDATA_OUT fall time
Tfalldout
Note 1: 75pF external load (50 pF in AC’97 rev2.1)
Note 2: rise is from 10% to 90% of Vdd (Vol to Voh)
Note 3: fall is from 90% to 10% of Vdd (Voh to Vol)
Two Channel AC’97 2.3 Audio Codec
Minimum
-
Typical
-
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Maximum
6
6
6
6
6
6
6
6
Units
ns
ns
ns
ns
ns
ns
ns
ns
Rev1.01
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ALC250 Data Sheet
Signal Rise and Fall timing diagram
7.2.6 AC-Link Low Power Mode Timing
Parameter
End of slot 2 to BIT_CLK,
SDATA_IN low
Symbol
Ts2_pdown
Minimum
-
Typical
-
Maximum
1.0
Units
µs
AC-Link low power mode timing diagram
7.2.7 ATE Test Mode
To meet AC’97 rev2.3 specifications, EAPD, SPDIFO, BIT_CLK and SDATA_IN should be floating in test mode.
Parameter
Symbol
Minimum
Typical
Maximum
Units
Setup to trailing edge of RESET#
Tsetup2rst
15.0
ns
(also applies to SYNC)
Rising edge of RESET# to Hi-Z
Toff
25.0
ns
delay
ATE test mode timing diagram
7.2.8 AC-Link IO Pin Capacitance and Loading
Output Pin
BIT_CLK (must support ≥ 2
CODECs)
Two Channel AC’97 2.3 Audio Codec
1 CODEC
55pF
2 CODEC
62.5pF
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3 CODEC
75pF
4 CODEC
85pF
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ALC250 Data Sheet
SDATA_IN
47.5pF
55pF
60pF
62.5pF
Minimum
0
45
Typical
Maximum
10
55
Units
%
%
7.2.9 SPDIF Output
SPDIF_OUT
Rise time/fall time
Duty cycle
T(h)
T(l)
90%
50%
10%
T(r)
Notes:
T(f)
Rise time = 100 * T(r)/ (T(l)+ T(h))%
Fall time = 100 * T(f)/ (T(l)+ T(h))%
Duty cycle = 100 * T(h)/ (T(l)+ T(h))%
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ALC250 Data Sheet
8. Analog Performance Characteristics
Standard test conditions: Tambient=250C, Dvdd=3.3V ±5%,Avdd=5.0V±5%
1KHz input sine wave; Sampling frequency=48KHz; 0dB=1Vrms
10KΩ/50pF load; Test bench Characterization BW: 10Hz~22KHz
0dB attenuation; tone and 3D disabled
Parameter
Minimum
Typical
Maximum
Full scale input voltage: Line inputs (Mixers)
1.6
Line inputs (A/D)
1.0
Mic input (0 dB)
1.6
Mic input (20 dB boost)
0.16
Full scale output voltage
LINE-OUT
1.25
HP-OUT
1.25
Analog to Analog S/N:
CD to LINE-OUT
100
Other to LINE-OUT
100
Analog frequency response
10
22,000
S/N (A-weighted):
D/A
100
A/D
92
Total Harmonic Distortion:
D/A
-92
A/D
-86
D/A & A/D frequency response
20
20,000
Transition Band
20,000
28,800
Stop Band
28,800
∞
Stop Band Rejection
-75
Out-of-Band Rejection
-70
Group delay
1
Power Supply Rejection
-40
MIC Boost Gain
6
20
30
Master Volume (LINE- / HP-OUT): 64 step
Step Size
1.5
Attenuation Control Range
0
-94.5
Master Volume (MONO-OUT): 32 step
Step Size
1.5
Attenuation Control Range
0
-46.5
PC Beep Volume 16 steps:
Step Size
3.0
Attenuation Control Range
0
-45
Analog Mixer Volume 32 steps:
Step Size
1.5
Gain Control Range
-34.5
+12
Record Gain 16 steps:
Step Size
1.5
Gain Control Range
0
+22.5
DC Volume Control: 32 step
Gain Control Range
0
-43
0 dB DC voltage
0.1
Mute DC voltage
4.7
Input impedance (gain = 0dB, mixer = off)
LINE-IN, CD-IN, AUX-IN, MIC1 / MIC2
64
PCBEEP, PHONE
16
cont…
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Units
Vrms
Vrms
Vrms
dB
Hz
dB
dB
Hz
Hz
Hz
dB
dB
ms
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
V
V
KΩ
KΩ
Rev1.01
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ALC250 Data Sheet
Output Impedance
LINE-OUT
HP-OUT
MONO-OUT
Amplifier Maximum Output Power
@20Ω load
Power Supply Current
VA=5.0V
VA=3.3V
VD=3.3V
Power Down Current
VA=5.0V / 3.3V
VD=3.3V
Vrefout/Vrefout2/Vrefout3
Vrefout Drive Current
Two Channel AC’97 2.3 Audio Codec
-
200
5
500
-
Ω
Ω
Ω
-
-
50
mW
-
50
36
26
-
mA
mA
mA
-
2.50
5
1000
700
4.0
-
uA
uA
V
mA
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ALC250 Data Sheet
9. Design Suggestions
9.1 Clocking
The clock source is decided by XTLSEL latched from pin-46 after power-on reset. The clock source of different
configuration is listed below:
Configuration
Operation & ID0
Pin-46(XTLSEL)
ID0
BIT-CLK Clock source
NC
0 (Primary) Output
Crystal or ext. 24.576MHz is attached
12.288MHz at XTL-IN
Low
0 (Primary) Output
Crystal or ext. 14.318MHz is attached
12.288MHz at XTL-IN
NC
0 (Primary) Input
12.288M input at BIT-CLK
*Low: Pulled low by a 0 ohm resistor. NC: Not connect or pulled high.
*Pin-46is internally pulled high by a weak resistor.
According to AC’97 ver 2.3, the primary mode while RESET# is asserted, if a clock is present at BIT-CLK pin for at least 5
cycles before RESET# is de-asserted, ALC250 is a consumer of BITCLK. ALC250 should use external 12.288MHz BITCLK
as its clock source.
9.2 AC-Link
When the ALC250 receives serial data from the AC97 controller, it samples SDATA_OUT on the falling edge of BIT_CLK.
When the ALC250 sends serial data to the AC97 controller, it starts to drive SDATA_IN on the rising edge of BIT_CLK.
The ALC250 will return any uninstalled bits or registers with 0 for read operations. The ALC250 also stuffs the unimplemented
slot or bit with 0 in SDATA_IN. Note that AC-LINK is MSB-justified.
Refer to “Audio CODEC ’97 Component Specification Revision 2.3.” for details.
0
Slot#
1
2
3
4
5
6
7
8
9
10
11
12
SYNC
SDATA-OUT
SDATA-IN
TAG CMD DATA PCM PCMR
L
TAG
SPDIF SPDIF
L
R
ADD DATA PCM PCMR
R
L
Default ALC250 Slot Arrangement – CODEC ID = 00 (ALC250 supports only primary mode)
9.3 Reset
There are 3 types of reset operations: Cold, Warm and Register.
Reset Type
Cold
Register
Warm
Trigger condition
Assert RESET# for a specified period
CODEC response
Reset all hardware logic and all registers to its default
value.
Write register indexed 00h
Reset all registers to its default value.
Driven SYNC high for specified period without Reactivates AC-LINK, no change to register values.
BIT_CLK
The AC97 controller should drive SYNC and SDATA_OUT low during the period of RESET# assertion to guarantee that the
ALC250 has reset successfully.
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ALC250 Data Sheet
9.4 CD Input
It is important to pay attention to differential CD input. Below is an example of differential CD input.
Example of differential CD input
9.5 Odd Addressed Register Access
The ALC250 will return “0000h” when odd-addressed and unimplemented registers are read.
9.6 Power-down Mode
It is important to pay special attention to the power down control register (index 26h), especially PR4 (powerdown AC-link).
9.7 Test Mode
To provide compatibility with AC’97 rev2.2, the ALC250 will float its digital output pins in both ATE and Vendor-Specific test
modes. Please refer to AC’97 rev2.2 section 9.2 for a detailed description of the test modes.
9.7.1 ATE In Circuit Test Mode
SDATA_OUT is sampled high at the trailing edge of RESET#. In this mode, the ALC250 will drive BIT_CLK, SDATA_IN,
EAPD and SPDIFO to high impedance.
9.7.2 Vendor Specific Test Mode
The Vendor Specific Test mode is no longer supported.
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ALC250 Data Sheet
9.8 DC Voltage Volume Control
The ALC250 has a 32-step internal volume control that is controlled by the DC voltage applied the ‘DC Vol’ pin (pin-32). The
volume control input range is from GND to AVDD, to attenuate the master volume (real MX02), headphone volume (real
MX04) and mono-out volume (real MX06). A higher DC voltage means more attenuation related to output volume. The table
below shows the relation between input DC voltage and the 5-bit volume code.
Input DC
Volume
Note
Input DC
Volume
Note
Voltage
Code
Voltage
Code
95%=< DC
1F
47%< DC <= 50%
F
DCMute=1
92%< DC <= 95%
1E
DCMute=0
44%< DC <= 47%
E
89%< DC <= 92%
1D
41%< DC <= 44%
D
86%< DC <= 89%
1C
38%< DC <= 41%
C
83%< DC <= 86%
1B
35%< DC <= 38%
B
80%< DC <= 83%
1A
32%< DC <= 35%
A
77%< DC <= 80%
19
29%< DC <= 32%
9
74%< DC <= 77%
18
26%< DC <= 29%
8
71%< DC <= 74%
17
23%< DC <= 26%
7
68%< DC <= 71%
16
20%< DC <= 23%
6
65%< DC <= 68%
15
17%< DC <= 20%
5
62%< DC <= 65%
14
14%< DC <= 17%
4
59%< DC <= 62%
13
11%< DC <= 14%
3
56%< DC <= 59%
12
8%< DC <= 11%
2
53%< DC <= 56%
11
5%< DC <= 8%
1
50%< DC <= 53%
10
DC <= 5%
0
DCMute=0
Input DC Voltage is ratio of AVDD (+5VA).
❷This 5-bit volume code adds extra attenuation for master volume and headphone volume, the absolute maximum volume is
determined by MX02, MX04 and MX06.
Once the sum of MX value and volume code exceeds 3Fh, the real MX value is 3Fh.
Example 1: (Normal case)
MX02=0002h, MX04=0300h, MX06=0001h, Volume Code=2h,
then Master Volume=0204h, Headphone Volume=0502h, Mono-Out=0003h
Example 2: (The sum exceeds 3Fh for MX02/MX04, 1Fh for MX06)
MX02=2F2Fh, MX04=2E2Eh, MX06=0002h, Volume Code=1Eh,
then Master Volume=3F3Fh, real Headphone Volume=3D3Dh, Mono-Out=001Fh
Example 3: (Volume code is 1Fh, DCMute=1, real MXs should be muted)
MX02=0000h, MX04=2020h, MX06=0010h, Volume Code=1Fh,
then Master Volume=9F1Fh, Headphone Volume=BF3Fh, Mono-Out=801Fh
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ALC250 Data Sheet
9.9 POWER OFF CD Function
The ‘POWER OFF CD’ function describes a state which, after the system has been shut down and a +5V analog power is
supplied at VAUX(pin-34), the ALC250 will turn on the CD-IN op and output amplifier. It is possible to design a system which
will save op-amp circuitry and bypass CD output directly to the speaker.
The figure below indicates the system application circuitry to support the ‘POWER OFF CD’ function. The operation mode is
defined by +3.3VCC and +5Vaux.
+3.3VCC
No (0)
No (0)
Yes (1)
Yes (1)
+5Vaux
No (0)
Yes (1)
No (0)
Yes (1)
Operation Mode
Shut Down
Power Off CD
Normal (+5Vaudio must be on)
Normal (+5Vaudio must be on)
+5VA
+5Vstandby
D1
+3.3VDD
1N5817M/CYL
D2
+
10u
1u
0
VDD
VDD
25
38
RESET#
BITCLK
SYNC
SDOUT
SDIN
VREF
VREFOUT
AFILT1
AFILT2
ALC250
PC-BEEP
PHONE
AUX-L
AUX-R
JD2
JD1
CD-L
CD-R
MIC1
MIC2
LINE-L
LINE-R
4
7
GND
GND
1u
NC
DCVOL
VREFOUT2
VAUX
GPIO0
GPIO1
NC
XTLSEL
SPDIFI/EAPD
SPDIFO
HPOUT-L
NC
HPOUT-R
35
36
37
27
28
29
30
31
32
33
34
43
44
45
46
47
48
39
40
41
AGND
AGND
1u
0
U3
LINEOUT-L
LINEOUT-R
MONO-OUT/VREFOUT3
CD-GND
0
1
2
3
4
12
13
14
15
16
17
18
20
21
22
23
24
0.1u
26
42
11
6
10
5
8
XTL-IN
XTL-OUT
19
2
3
1N5817M/CYL
10u
AVDD
AVDD
+
1
9
0.1u
POWER OFF CD Circuitry
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ALC250 Data Sheet
10. Application Circuit
DC Volume Control (ALC202/203/250)
+5VA
C31
R67
VAR 10K
C67
R70
[email protected]/250
R71
[email protected]
[email protected]
[email protected]
[email protected]/250
C1
+
+3.3VDD
U1
+5VA
6.8k~8.2k
10u
3
1000P
+5VAUX
R4
[email protected]
46
47
Pown Down Ext. AMP
N.C
25
26
AVSS1
28
30
27
VREF
VREFOUT
AVDD1
CD-GND
ALC250/203/202
2
GPIO0/SCK
CD-L
18
GPIO1/SDA
JD1
17
ID0#/JD0
JD2
16
AUX-R
15
C37
AUX-L
14
C39
PHONE
13
XTLSEL
SPDIFI/EAPD
SPDIFO
MIC1-IN
R1
J4
0
R2
4
3
2
1
0
R3
0
R34
R35
C41
1u
[email protected]/250
[email protected]/250
R7
CD-IN Header
[email protected]
[email protected]
AUX-R
AUX-L
0
Audio-From-Modem
R12B1 10K
C12A1
1u
Signal-From-PCSPK
IN
VCC
GND
29
1u
SPDIF-OUT
4
AFILT1
C30
AVSS2
1
N.C
19
1u
DVDD1
TOTX178
5
48
Optical
Transmitter
U3
1u
C28
+
EQualizer Control by uP (ALC250 only)
C27
PC-BEEP
45
20
RESET#
43
44
CD-R
MIC2-IN
12
[email protected]
HP-OUT-R
11
[email protected]
R66
1u
SYNC
R65
SDA
1u
C25
DVDD2
SDA
SCK
C24
21
10
SCK
22
9
42
LINE-IN-L
MIC1
SDATA-IN
41
100u
LINE-IN-R
MIC2
DVSS2
C26
HP-OUT-R
1u
1u
NC
8
R64
[email protected]
+
R63
[email protected]
C21
C22
HP-OUT-L
7
40
U6
23
BIT-CLK
39
100u
C15
LINE-IN-L
SDATA-OUT
+
C23
HP-OUT-L
+3.3VDD
C8
10u
10u
1u
AVDD2
+
FERB
0.1u
24
6
38
+
C16
IN
C11
10u
10u
OUT
C7
LINE-IN-R
MONO-O
5
0.1u
[email protected]/250 37
DVSS1
R69
VREFOUT3
AFILT2
For UAJ (ALC203/250)
XTL-OUT
C20
4
10u
+
3
C19
32
+5VA
R54
4.7K
31
1u
NC
C12
DCVOL
LINE-OUT-R
34
LINE-OUT-R to Ext.AMP
+5VA
C14
1000P
33
1u
VAUX
C5
VREFOUT2
LINE-OUT-L to Ext.AMP
LINE-OUT-L
36
Vol-Up
Vol-Down
+
C6
C10
[email protected]/250/202
35
[email protected]
R41
LINE-OUT-L
R56
VREFOUT2
For Power Off CD
LINE-OUT-R
Vol-Mute
[email protected]
XTL-IN
GPIO0
R55
2
GPIO1
[email protected]/250
+
R53
4.7K
R68
L3
1
GND
VREFOUT
For UAJ (ALC203/250)
+12V
LM7805CT/200mA
+
GPIO Volume Contro (ALC203 only)
3
1
2
+3.3VDD
C44
C43
10u
C32
0.1u
C42
+
0.1u
0.1u
C38
R5
1
S/PDIF OUTPUT
100P
100P
2
R9
22
100
R8
SPDIF-OUT
C40
(Coaxial)
+3.3VDD
R12A1
1K
R33
[email protected]
+5VDD
J6
C12B1
0.01u
R10
22
Y1
AC97-RESET#
EXT 14.318MHz
[email protected]
R6
220
AC97-SYNC
AC97-SDIN
AC97-BCLK
AC97-SDOUT
24.576MHz
C45
C46
22P
22P
EQualizer Control by uP (ALC250 only)
C50
22P
Crystal Saving:
R8,R4=0; Y1,C45,C46=X (EXT-14.288MHz clock)
R8,R4=X; Y1=24.576M, C45,C46=22p (24.576MHz crystal)
DGND
AGND
Tied at one point only under
the codec or near the codec
Filter Connection Schematic
Two Channel AC’97 2.3 Audio Codec
39
Tel: +49(0)234-9351135 · Fax: +49(0)234-9351137 E-MAIL: [email protected]
Rev1.01
http://www.cornelius-consult.de
JD1
JD2
ALC250 Data Sheet
Standard Jack Connection (ALC250/203/202)
VREFOUT
R13
[email protected]/250, Stereo MIC
MIC2-IN
R12
[email protected]/250, Mono MIC
[email protected]/250,Stereo MIC
[email protected]/250, Stereo MIC
R15
MIC1-IN
R17
FERB
L8
1
2
3
4
5
Internal MIC-IN
0
L9
FERB
C52
C53
J2
Microphone Input
100P 100P
Jack Detect to bypass EQ while headphone is plugged in (ALC250 only)
JD1
C72
R56
[email protected]
[email protected]
HP-OUT-R
HP-OUT-L
L13
FERB
L15
FERB
J1
1
2
3
4
5
R59
R60
C60
C61
22K
22K
100P
100P
Headphone Out
Jack Connection - Standard Connection
Universal Audio Jack(UAJ): (ALC250/203)
R50
JD2
+
D5
VREFOUT2
10K
C71
3.3u
1N4148
AUX-R
L18
1
2
3
4
5
FERB
Internal MIC-IN
AUX-L
L19
R51
FERB
C58
C59
100P
100P
J2
UAJ2
22K
R32
10K
JD1
+
VREFOUT3-UAJ1
C66
3.3u
D4
1N4148
FERB
HP-OUT-R
L16
HP-OUT-L
L17
J1
FERB
R31
22K
C62
C63
100P
100P
1
2
3
4
5
UAJ1
Jack Connection -(Universal Audio Jack, UAJ)
Two Channel AC’97 2.3 Audio Codec
40
Tel: +49(0)234-9351135 · Fax: +49(0)234-9351137 E-MAIL: [email protected]
Rev1.01
http://www.cornelius-consult.de
ALC250 Data Sheet
11. Mechanical Dimensions
L
L1
SYMBOL
A
A1
A2
c
D
D1
D2
E
E1
E2
b
e
TH
L
L1
MILLIMETER
MIN. TYPICAL MAX.
1.60
0.05
0.15
1.35
1.40
1.45
0.09
0.20
9.00 BSC
7.00 BSC
5.50
9.00 BSC
7.00BSC
5.50
0.17
0.20
0.27
0.50 BSC
0o
3.5o
7o
0.45
0.60
0.75
1.00
INCH
MIN. TYPICAL
0.002
0.053
0.004
0.055
TITLE: LQFP-48 (7.0x7.0x1.6mm)
PACKAGE OUTLINE DRAWING, FOOTPRINT 2.0mm
LEADFRAME MATERIAL
APPROVE
DOC. NO.
VERSION 02
CHECK
DWG NO. PKGC-065
DATE
REALTEK SEMICONDUCTOR CORP.
MAX
0.063
0.006
0.057
0.008
0.354 BSC
0.276 BSC
0.217
0.354 BSC
0.276 BSC
0.217
0.007 0.008
0.011
0.016 BSC
0o
3.5o
7o
0.018 0.0236 0.030
0.0393
Two Channel AC’97 2.3 Audio Codec
41
Tel: +49(0)234-9351135 · Fax: +49(0)234-9351137 E-MAIL: [email protected]
Rev1.01
http://www.cornelius-consult.de
ALC250 Data Sheet
Realtek Semiconductor Corp.
Headquarters
1F, No. 2, Industry East Road IX, Science-based
Industrial Park, Hsinchu, 300, Taiwan, R.O.C.
Tel : 886-3-5780211 Fax : 886-3-5776047
WWW: www.realtek.com.tw
Two Channel AC’97 2.3 Audio Codec
42
Tel: +49(0)234-9351135 · Fax: +49(0)234-9351137 E-MAIL: [email protected]
Rev1.01
http://www.cornelius-consult.de