TI SN74CB3T3306

SN74CB3T3306
www.ti.com
SCDS119B – JANUARY 2003 – REVISED AUGUST 2012
DUAL FET BUS SWITCH 2.5-V/3.3-V LOW-VOLTAGE BUS SWITCH
WITH 5-V TOLERANT LEVEL SHIFTER
Check for Samples: SN74CB3T3306
FEATURES
•
•
1
•
•
•
•
•
•
•
•
Output Voltage Translation Tracks VCC
Supports Mixed-Mode Signal Operation
on All Data I/O Ports
– 5-V Input Down to 3.3-V Output Level
Shift With 3.3-V VCC
– 5-V/3.3-V Input Down to 2.5-V Output
Level Shift With 2.5-V VCC
5-V Tolerant I/Os With Device Powered Up
or Powered Down
Bidirectional Data Flow With Near-Zero
Propagation Delay
Low ON-State Resistance (ron)
Characteristics (ron = 5 Ω Typ)
Low Input/Output Capacitance Minimizes
Loading (Cio(OFF) = 4.5 pF Typ)
Data and Control Inputs Provide
Undershoot Clamp Diodes
Low Power Consumption
(ICC = 20 μA Max)
•
•
•
•
•
•
VCC Operating Range From 2.3 V to 3.6 V
Data I/Os Support 0- to 5-V Signaling Levels
(0.8 V, 1.2 V, 1.5 V, 1.8 V, 2.5 V, 3.3 V, 5 V)
Control Inputs Can Be Driven by TTL or
5-V/3.3-V CMOS Outputs
Ioff Supports Partial-Power-Down Mode
Operation
Latch-Up Performance Exceeds 250 mA Per
JESD 17
ESD Performance Tested Per JESD 22
– 2000-V Human-Body Model
(A114-B, Class II)
– 1000-V Charged-Device Model (C101)
Supports Digital Applications: Level
Translation, USB Interface, Bus Isolation
Ideal for Low-Power Portable Equipment
DCT OR DCU PACKAGE
(TOP VIEW)
1OE
1A
1B
GND
1
8
2
7
3
6
4
5
VCC
2OE
2B
2A
DESCRIPTION/ORDERING INFORMATION
The SN74CB3T3306 is a high-speed TTL-compatible FET bus switch with low ON-state resistance (ron), allowing
for minimal propagation delay. The device fully supports mixed-mode signal operation on all data I/O ports by
providing voltage translation that tracks VCC. The SN74CB3T3306 supports systems using 5-V TTL, 3.3-V
LVTTL, and 2.5-V CMOS switching standards, as well as user-defined switching levels (see Figure 1).
The SN74CB3T3306 is organized as two 1-bit bus switches with separate ouput-enable (1OE, 2OE) inputs. It
can be used as two 1-bit bus switches or as one 2-bit bus switch. When OE is low, the associated 1-bit bus
switch is ON, and the A port is connected to the B port, allowing bidirectional data flow between ports. When OE
is high, the associated 1-bit bus switch is OFF, and a high-impedance state exists between the A and B ports.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2003–2012, Texas Instruments Incorporated
SN74CB3T3306
SCDS119B – JANUARY 2003 – REVISED AUGUST 2012
www.ti.com
ORDERING INFORMATION
TA
–40°C to 85°C
(1)
(2)
PACKAGE (1)
TOP-SIDE MARKING (2)
ORDERABLE PART NUMBER
SSOP – DCT
Tape and reel
SN74CB3T3306DCTR
WA6_ _ _
VSSOP – DCU
Tape and reel
SN74CB3T3306DCUR
WA6_
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
DCT: The actual top-side marking has three additional characters that designate the year, month, and assembly/test site.
DCU: The actual top-side marking has one additional character that designates the assembly/test site.
DESCRIPTION/ORDERING INFORMATION (CONTINUED)
This device is fully specified for partial-power-down applications using Ioff. The Ioff feature ensures that damaging
current will not backflow through the device when it is powered down. The device has isolation during power off.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Figure 1. Typical DC Voltage-Translation Characteristics
Table 1. FUNCTION TABLE
(EACH BUS SWITCH)
INPUT
OE
INPUT/OUTPUT
A
FUNCTION
L
B
A port = B port
H
Z
Disconnect
LOGIC DIAGRAM (POSITIVE LOGIC)
2
1A
1OE
3
1B
SW
1
5
2A
6
SW
2B
7
2OE
2
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SCDS119B – JANUARY 2003 – REVISED AUGUST 2012
SIMPLIFIED SCHEMATIC, EACH FET SWITCH (SW)
B
A
VG(1)
Control
Circuit
EN(2)
(1) Gate voltage (VG) is approximately equal to VCC + VT when the switch is ON
and VI > VCC + VT.
(2) EN is the internal enable signal applied to the switch.
Absolute Maximum Ratings (1)
over operating free-air temperature range (unless otherwise noted)
(2)
MIN
MAX
UNIT
VCC
Supply voltage range
VIN
Control input voltage range (2)
–0.5
7
V
(3)
–0.5
7
VI/O
Switch I/O voltage range (2)
V
(3) (4)
–0.5
7
V
IIK
Control input clamp current
VIN < 0
–50
mA
II/OK
I/O port clamp current
VI/O < 0
–50
mA
II/O
ON-state switch current (5)
±128
mA
±100
mA
Continuous current through VCC or GND
θJA
Package thermal impedance (6)
Tstg
Storage temperature range
(1)
(2)
(3)
(4)
(5)
(6)
DCT package
220
DCU package
227
–65
150
°C/W
°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltages are with respect to ground, unless otherwise specified.
The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
VI and VO are used to denote specific conditions for VI/O.
II and IO are used to denote specific conditions for II/O.
The package thermal impedance is calculated in accordance with JESD 51-7.
Recommended Operating Conditions (1)
VCC
Supply voltage
VIH
High-level control input voltage
VIL
Low-level control input voltage
VI/O
Data input/output voltage
TA
Operating free-air temperature
(1)
MIN
MAX
UNIT
2.3
3.6
VCC = 2.3 V to 2.7 V
1.7
5.5
V
VCC = 2.7 V to 3.6 V
2
5.5
VCC = 2.3 V to 2.7 V
0
0.7
VCC = 2.7 V to 3.6 V
0
0.8
0
5.5
V
–40
85
°C
V
V
All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
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SCDS119B – JANUARY 2003 – REVISED AUGUST 2012
www.ti.com
Electrical Characteristics (1)
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VIK
VCC = 3 V, II = –18 mA
VOH
See Figure 3 and Figure 4
IIN
Control inputs
VCC = 3.6 V, VIN = 3.6 V to 5.5 V or GND
VCC = 3.6 V, Switch ON,
VIN = VCC or GND
II
TYP (2) MAX
MIN
IOZ
(3)
VCC = 0, VO = 0 to 5.5 V, VI = 0
ICC
VCC = 3.6 V, II/O = 0,
Switch ON or OFF, VIN = VCC or GND
ΔICC
(4)
Cin
Control inputs
VCC = 3 V to 3.6 V, One input at VCC – 0.6 V,
Other inputs at VCC or GND
Control inputs
VCC = 3.3 V, VIN = VCC or GND
V
±10
μA
±20
VI = 0.7 V to VCC – 0.7 V
–40
±10
μA
10
μA
VI = VCC or GND
20
VI = 5.5 V
20
pF
4.5
pF
Cio(ON)
VCC = 3.3 V, Switch ON,
VIN = VCC or GND
VI/O = 5.5 V or 3.3 V
VI/O = GND
15
VCC = 2.3 V, TYP at VCC = 2.5 V,
VI = 0
IO = 24 mA
5
8
IO = 16 mA
5
8
IO = 64 mA
5
7
IO = 32 mA
5
7
VCC = 3 V, VI = 0
(1)
(2)
(3)
(4)
(5)
μA
3
Cio(OFF)
(5)
μA
300
VCC = 3.3 V, VI/O = 5.5 V, 3.3 V, or GND, Switch OFF,
VIN = VCC or GND
ron
μA
±5
VCC = 3.6 V, VO = 0 to 5.5 V, VI = 0, Switch OFF, VIN = VCC or GND
Ioff
–1.2
VI = VCC – 0.7 V to 5.5 V
VI = 0 to 0.7 V
UNIT
4
pF
Ω
VIN and IIN refer to control inputs. VI, VO, II, and IO refer to data pins.
All typical values are at VCC = 3.3 V (unless otherwise noted), TA = 25°C.
For I/O ports, the parameter IOZ includes the input leakage current.
This is the increase in supply current for each input that is at the specified TTL voltage level, rather than VCC or GND.
Measured by the voltage drop between A and B terminals at the indicated current through the switch. ON-state resistance is determined
by the lower of the voltages of the two (A or B) terminals.
Switching Characteristics
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 2)
4
VCC = 3.3 V
± 0.3 V
TO
(OUTPUT)
A or B
B or A
ten
OE
A or B
1
8.5
tdis
OE
A or B
1
9
tpd
(1)
VCC = 2.5 V
± 0.2 V
FROM
(INPUT)
PARAMETER
(1)
MIN
MAX
MIN
0.15
UNIT
MAX
0.25
ns
1
6.5
ns
1
9
ns
The propagation delay is the calculated RC time constant of the typical ON-state resistance of the switch and the specified load
capacitance, when driven by an ideal voltage source (zero output impedance).
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SCDS119B – JANUARY 2003 – REVISED AUGUST 2012
PARAMETER MEASUREMENT INFORMATION
VCC
Input Generator
VIN
50 Ω
50 Ω
VG1
TEST CIRCUIT
DUT
2 × VCC
Input Generator
VI
S1
RL
VO
50 Ω
50 Ω
VG2
RL
CL
(see Note A)
TEST
VCC
S1
RL
VI
CL
tpd(s)
2.5 V ± 0.2 V
3.3 V ± 0.3 V
Open
Open
500 Ω
500 Ω
3.6 V or GND
5.5 V or GND
30 pF
50 pF
tPLZ/tPZL
2.5 V ± 0.2 V
3.3 V ± 0.3 V
2 × VCC
2 × VCC
500 Ω
500 Ω
GND
GND
30 pF
50 pF
0.15 V
0.3 V
tPHZ/tPZH
2.5 V ± 0.2 V
3.3 V ± 0.3 V
Open
Open
500 Ω
500 Ω
3.6 V
5.5 V
30 pF
50 pF
0.15 V
0.3 V
V∆
VCC
Output
Control
(VIN)
VCC/2
VCC
VCC/2
VCC/2
0V
tPLH
VOH
Output
VCC/2
tPLZ
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
VCC
VCC/2
VCC/2
VOL
tPHZ
Output
Waveform 2
S1 at Open
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES (tpd(s))
VOL + V∆
VOL
tPZH
tPHL
VCC/2
0V
tPZL
Output
Control
(VIN)
Open
GND
VOH
VCC/2
VOH − V∆
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd(s). The tpd propagation delay is the calculated RC time constant of the typical ON-state resistance
of the switch and the specified load capacitance, when driven by an ideal voltage source (zero output impedance).
H. All parameters and waveforms are not applicable to all devices.
Figure 2. Test Circuit and Voltage Waveforms
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SCDS119B – JANUARY 2003 – REVISED AUGUST 2012
www.ti.com
TYPICAL CHARACTERISTICS
OUTPUT VOLTAGE
vs
INPUT VOLTAGE
OUTPUT VOLTAGE
vs
INPUT VOLTAGE
4.0
VCC = 2.3 V
IO = 1 µA
TA = 25°C
3.0
V - Output Voltage - V
O
V - Output Voltage - V
O
4.0
2.0
1.0
VCC = 3 V
IO = 1 µA
TA = 25°C
3.0
2.0
1.0
0.0
0.0
0.0
1.0
2.0
3.0
4.0
5.0
6.0
0.0
VI - Input Voltage - V
1.0
2.0
3.0
4.0
5.0
6.0
VI - Input Voltage - V
Figure 3. Data Output Voltage vs Data Input Voltage
6
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SN74CB3T3306
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SCDS119B – JANUARY 2003 – REVISED AUGUST 2012
TYPICAL CHARACTERISTICS
OUTPUT VOLTAGE HIGH
vs
SUPPLY VOLTAGE
OUTPUT VOLTAGE HIGH
vs
SUPPLY VOLTAGE
3.5
4.0
VCC = 2.3 V ~ 3.6 V
VI = 5.5 V
TA = 85°C
100 µA
8 mA
16 mA
24 mA
3.0
2.5
2.0
1.5
2.3
VOH - Output Voltage High - V
VOH - Output Voltage High - V
4.0
VCC = 2.3 V to 3.6 V
VI = 5.5 V
TA = 25°C
3.5
100 µA
8 mA
16 mA
24 mA
3.0
2.5
2.0
1.5
2.5
2.7
2.9
3.1
3.3
3.5
3.7
2.3
2.5
2.7
2.9
3.1
3.3
3.5
3.7
VCC - Supply Voltage - V
VCC - Supply Voltage - V
OUTPUT VOLTAGE HIGH
vs
SUPPLY VOLTAGE
V
- Output Voltage High - V
OH
4.0
VCC = 2.3 V to 3.6 V
VI = 5.5 V
TA = -40°C
3.5
100 µA
8 mA
16 mA
24 mA
3.0
2.5
2.0
1.5
2.3
2.5
2.7
2.9
3.1
3.3
3.5
3.7
VCC - Supply Voltage - V
Figure 4. VOH Values
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SN74CB3T3306
SCDS119B – JANUARY 2003 – REVISED AUGUST 2012
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REVISION HISTORY
Changes from Revision A (June 2005) to Revision B
•
8
Page
Updated graphic note and picture in figure 1. ...................................................................................................................... 2
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PACKAGE MATERIALS INFORMATION
www.ti.com
16-Aug-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
SN74CB3T3306DCUR
Package Package Pins
Type Drawing
US8
DCU
8
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
3000
180.0
8.4
Pack Materials-Page 1
2.25
B0
(mm)
K0
(mm)
P1
(mm)
3.35
1.05
4.0
W
Pin1
(mm) Quadrant
8.0
Q3
PACKAGE MATERIALS INFORMATION
www.ti.com
16-Aug-2012
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
SN74CB3T3306DCUR
US8
DCU
8
3000
202.0
201.0
28.0
Pack Materials-Page 2
MECHANICAL DATA
MPDS049B – MAY 1999 – REVISED OCTOBER 2002
DCT (R-PDSO-G8)
PLASTIC SMALL-OUTLINE PACKAGE
0,30
0,15
0,65
8
0,13 M
5
0,15 NOM
ÇÇÇÇÇ
ÇÇÇÇÇ
ÇÇÇÇÇ
ÇÇÇÇÇ
2,90
2,70
4,25
3,75
Gage Plane
PIN 1
INDEX AREA
1
0,25
4
0° – 8°
3,15
2,75
0,60
0,20
1,30 MAX
Seating Plane
0,10
0,10
0,00
NOTES: A.
B.
C.
D.
4188781/C 09/02
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion
Falls within JEDEC MO-187 variation DA.
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