HI-3000H, HI-3001H 1Mbps Avionics CAN Transceiver with High Operating Temperature December 2012 GENERAL DESCRIPTION PIN CONFIGURATIONS (Top Views) TXD - 1 The HI-3000H is a 1 Mbps Controller Area Network (CAN) transceiver optimized for use in high temperature avionics applications. The device is capable of operating at extended temperature ranges of -55°C to 175°C for plastic packages and -55°C to 200°C for the ceramic CERDIP-8 package. It interfaces between a CAN protocol controller and the physical wires of the bus in a CAN network. Differential output amplitude and current drive capability are specifically enhanced to meet the needs of long cable runs typical of avionics applications. GND - 2 VDD - 3 Superior common-mode receiver performance makes the device especially suitable for applications where ground reference voltages may vary from point to point over long distances along the CAN bus. In addition, the HI-3000H provides a SPLIT pin to give an output reference voltage of VDD/2 which can be used for stabilizing the recessive bus level when the split termination technique is used to terminate the bus. A TXD dominant time-out feature protects the bus from being driven into a permanent dominant state (so-called “babbling idiot”) if pin TXD becomes permanently low due to application failure. The device also has short circuit protection to +/-58V on CANH, CANL and SPLIT pins and ESD protection to +/- 6kV on all pins. The HI-3001H is identical to the HI-3000H except the SPLIT pin is substituted with a VIO supply voltage pin. This allows the HI-3001H to interface directly with controllers with 3.3V supply voltages. ( DS 3000H Rev. New) HI-3000PSHF HI-3000CRH 7 - CANH 6 - CANL RXD - 4 5 - SPLIT TXD - 1 8 - STB GND - 2 VDD - 3 RXD - 4 The HI-3000H supports two modes of operation: Normal Mode and Standby Mode. The Standby Mode is a very low-current mode which continues to monitor bus activity and allows an external controller to manage wake-up. 8 - STB HI-3001PSHF HI-3001CRH 7 - CANH 6 - CANL 5 - VIO 8-Pin Plastic SOIC package (Narrow Body) & 8-Pin Ceramic CERDIP FEATURES · Extended Temperature Ranges -55°C to 175°C (plastic · · · · · · · · · SOIC-8 package) and -55°C to 200°C (ceramic CERDIP8 package) Compatible with ARINC 825 and ISO 11898-5 standards. Signaling rates up to 1Mbit/s. Internal VDD/2 voltage source available to stabilize the recessive bus level if split termination is used (HI-3000H SPLIT pin). VIO input on HI-3001H allows for direct interfacing with 3.3V controllers. Detection of permanent dominant on TXD pin (babbling idiot protection). High impedance allows connection of up to 120 nodes. Input levels compatible with 3.3V or 5V controllers. CANH, CANL and SPLIT pins short-circuit proof to +/58V. Will not disturb the bus if unpowered. HOLT INTEGRATED CIRCUITS www.holtic.com 12/12 HI-3000H, HI-3001H PIN DESCRIPTIONS SIGNAL FUNCTION TXD GND VDD RXD CANL CANH STB INPUT POWER POWER OUTPUT BUS I/O BUS I/O INPUT SPLIT (HI-3000H) VIO (HI-3001H) INPUT INPUT DESCRIPTION 100kOhm internal pull-up. Transmit Data Input. Chip 0V supply Positive supply, 5V +/-5%. Bypass with 0.1uF ceramic capacitor. Receive Data Output. CAN Bus Line Low. CAN Bus Line High. 100kOhm internal pull-up. Standby Mode selection input. Drive STB low or connect to GND for Normal operation. Drive STB high to select low-current Standby Mode. Supplies a VDD/2 output to provide recessive bus level stabilization when a split termination is used to terminate the bus. Connect to a 3.3V supply to allow compatibility of all digital I/O (RXD, TXD, STB) with a 3.3V controller input. BLOCK DIAGRAM VDD V Split SPLIT (HI-3000H) CANH TXD Dominant Detect TXD STB Driver Standby Control VIO (HI-3001H) RXD CANL MUX Main Receiver GND Low power Standby Rx Figure 1. HI-3000H Functional Block Diagram HOLT INTEGRATED CIRCUITS 2 HI-3000H, HI-3001H FUNCTIONAL DESCRIPTION OPERATING MODES The HI-3000H provides two modes of operation which are selectable via the STB pin. Table 1 summarizes the modes. due to an unpowered node with high leakage from the bus lines to ground), the split circuit will force the recessive voltage to VDD/2. INTERNAL PROTECTION FEATURES Table 1 - Operating Modes MODE Normal Standby Short-circuit protection STB pin Short-circuit protection is provided on the CANH, CANL and SPLIT pins. These pins are protected from ESD to over 6KV (HBM) and from shorts between -58V and +58V continuous, as specified in ISO 11898-5. The short circuit current is limited to less than 200mA typical. LOW HIGH TXD permanent dominant time-out Normal Mode Normal mode is selected by setting the STB pin to a LOW logic level (GND). In this mode, the transceiver transmits and receives data in the usual way from the CANH and CANL bus lines. The differential receiver converts the analog bus data to digital data which is output on the RXD pin (Note: the RXD output on HI-3001H is compatible with 3.3V controllers if the VIO pin is connected to a 3.3V supply). Standby Mode A timer circuit prevents the bus lines being driven into a permanent dominant state, which would result in a situation blocking all bus traffic. This could happen in the case of the TXD pin becoming permanently low due to a hardware or application failure. The timer is triggered by a negative edge on the TXD pin (start of dominant state). If the TXD pin is not set high (recessive state) after a typical time of 2ms, the transmitter outputs will be disabled, driving the bus lines into the recessive state. The timer is reset by a positive edge on the TXD pin. Note that the minimum TXD dominant time-out time, tdom = 300μs, defines the minimum possible bit rate of 40kbit/s (the CAN protocol specifies a maximum of 11 successive dominant bits − 5 successive dominant bits immediately followed by an error frame). Standby Mode is selected by setting the STB pin to a HIGH logic level. In this mode, the transmitter is switched off and a low power differential receiver monitors the bus lines for activity. A dominant signal of more than 3ms will be reflected on the RXD pin as a logic LOW, where it may be detected by the host as a wake-up request. The device will not leave standby mode until the host forces the STB pin to a logic low. Fail-safe features SPLIT Circuit Pins TXD and STB will become floating if power is lost. This will prevent reverse currents via these pins. Pin TXD has a pull up in order to force a recessive level if pin TXD is left open. The SPLIT pin provides a stable VDD/2 DC voltage. This pin can be used to stabilize the recessive common mode voltage by connecting the SPLIT pin to the center tap of the split termination (see figure 7). In the case of a recessive bus voltage dropping below the ideal value of VDD/2 (e.g. HOLT INTEGRATED CIRCUITS 3 HI-3000H, HI-3001H TIMING DIAGRAMS Timing Delays HIGH TXD LOW CANH CANL Dominant 0.9V VDIFF(BUS) = VCANH - VCANL 0.5V Recessive HIGH RXD 50% 50% LOW tdr(TXD) tdf(TXD) tdr(RXD) tdf(RXD) tProp1 tProp2 TXD dominant time-out feature transmitter enabled tdom(TXD) tRdom recessive TXD dominant HIGH LOW transmitter disabled CANH CANL HOLT INTEGRATED CIRCUITS 4 HI-3000H, HI-3001H ABSOLUTE MAXIMUM RATINGS (Voltages referenced to GND = 0V) Supply Voltage, VDD, VIO : .....................................................................7V Current at Input pins ......................................................-100mA to +100mA DC Voltages at TXD, RXD and STB ..............................-0.5V to VDD +0.5V DC Voltages at CANH, CANL and SPLIT: ...............................-58V to +58V Internal Power Dissipation: ..............................................................900mW Electrostatic Discharge (ESD)1, All pins ..........................................+/- 6kV Operating Temperature Range: (Plastic)...........................-55°C to +175°C (Ceramic) ........................-55°C to +200°C Storage Temperature Range: -65°C to +150°C Soldering Temperature: (Ceramic)......................60 sec. at +300°C (Plastic - leads).............10 sec. at +280°C (Plastic - body) .....................+260°C Max. NOTES: 1. Human Body Model (HBM). Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC ELECTRICAL CHARACTERISTICS VDD = 5V±5%, Operating temperature range (unless otherwise noted). Positive currents flow into the IC. LIMITS PARAMETER SYMBOL CONDITIONS VDD Supply Current IDD Recessive: VTXD = VDD Dominant: VTXD = 0 V Standby Mode: VTXD = VDD VIO Supply Current IIO MIN UNIT TYP MAX 6 50 15 10 70 50 100 mA mA μA μA VDD + 0.5 20%VDD V V 0 − 50 +5 − 150 μA μA 0.1 10%VDD V V SUPPLY CURRENT DIGITAL INPUTS (Pins TXD, STB) HIGH-level input voltage (see Note 1) LOW-level input voltage (TXD pin) VIH VIL 80%VDD − 0.5 HIGH-level input current LOW-level input current IIH IIL VTXD = VDD or VIO VTXD = 0 V −5 VOH VOL IOH = 1mA IOL = 1mA 90%VDD 0 VSPLIT ISTB − 100 μA < ISPLIT < 100 μA 0.45VDD -5 0.5VDD 0.55VDD +5 V μA CANH dominant output voltage CANL dominant output voltage VO(CANH) VO(CANL) VTXD = 0 V VTXD = 0 V (See Fig. 2) 3 0.5 3.6 1.4 4.25 1.75 V V Recessive output voltage VCANH(r), VCANL(r) VTXD = VDD, RL = 0 (See Fig. 2) 2 0.5VDD 3 V VSTB VTXD = VDD, RL = 0 (See Fig. 2) -0.1 0.1 V Dominant differential output voltage Recessive differential output voltage VDIFF(d)(o) VDIFF(r)(o) VTXD = 0 V, 45 Ω < RL < 65 Ω VTXD = VDD, no load (See Fig. 2) 1.5 − 50 1.8 0 3 50 V mV Matching of dominant output voltage, VDD − VO(CANH) − VO(CANL) VOM (See Fig. 4) − 100 -40 150 mV VOC(ss) VSTB = 0V, RL = 60 Ω (See Fig. 5) 2 0.5VDD 3 V DIGITAL OUTPUTS HIGH-level output voltage (RXD Pin) (see Note 1) LOW-level output voltage (RXD Pin) Output voltage (SPLIT Pin) Standby leakage current (SPLIT Pin) DRIVER Bus output voltage in standby Steady state common mode output voltage NOTE: 1. When VIO is connected (HI-3001H), limits are referenced wrt VIO rather than VDD. HOLT INTEGRATED CIRCUITS 5 HI-3000H, HI-3001H DC ELECTRICAL CHARACTERISTICS (cont.) VDD = 5V±5%, Operating temperature range. Positive currents flow into the IC. LIMITS PARAMETER SYMBOL CONDITIONS IOS(ss) VCANH = +58V, VCANL open VCANH = -58V, VCANL openV VCANL = +58V, VCANH open VCANL = -58V, VCANH open (See Fig. 6) -20 -200 100 -20 Differential receiver threshold voltage Differential hysteresis voltage Differential hysteresis voltage in Standby mode VTh(Rx)(diff) VHys(Rx)(diff) VHys(Stb)(diff) − 12 V < VCANH, VCANL < + 12 V − 12 V < VCANH, VCANL < + 12 V − 12 V < VCANH, VCANL < + 12 V 500 50 500 Input leakage current, unpowered node ICANH, ICANL VDD = VIO 0 V VCANH = VCANL = 5V − 200 VTXD = VDD − 12 V < VCANH, VCANL < + 12 V 25 VTXD = VDD − 12 V < VCANH, VCANL < + 12 V 15 VCANH = VCANL −3 Short-circuit steady-state output current MIN TYP MAX UNIT 20 100 200 20 mA mA mA mA 900 200 1150 mV mV mV + 200 μA 50 100 kΩ 30 45 kΩ +3 % RECEIVER Differential input resistance RIN(DIFF) Common mode input resistance RIN(CM) Deviation between common mode input resistance between CANH and CANL RIN(CM)(m) 700 120 AC ELECTRICAL CHARACTERISTICS VDD = 5V±5%, Operating temperature range. Positive currents flow into the IC. LIMITS PARAMETER SYMBOL Bit time Bit rate Common mode input capacitance Differential input capacitance3 CONDITIONS tBit fBit 3 CIN(CM) CDIFF(CM) Delay TXD to bus active Delay TXD to bus inactive Delay bus active to RXD Delay bus inactive to RXD tdr(TXD) tdf(TXD) tdf(RXD) tdr(RXD) Propagation delay TXD to RXD (recessive to dominant) Propagation delay TXD to RXD (dominant to recessive) tProp1 tProp2 TXD permanent dominant time-out TXD permanent dominant timer reset time tdom tRdom Dominant time required on bus for wake up from standby MIN TYP 1 40 VTXD = VDD, 1Mbit/s data rate VTXD = VDD, 1Mbit/s data rate twake NOTES: 1. All currents into the device pins are positive; all currents out of the device pins are negative. 2. All typicals are given for VDD = 5V, TA = 25°C. 3. Guaranteed by design but not tested. HOLT INTEGRATED CIRCUITS 6 25 1000 20 10 See Timing Diagrans VTXD = 0 V Rising edge on TXD while in permanent dominant state MAX 0.3 0.5 UNIT μs kHz pF pF 40 40 30 70 90 90 70 150 ns ns ns ns 70 110 160 240 ns ns 2 6 ms 1 μs 5 μs 3 HI-3000H, HI-3001H Application and Test Information Transceiver TXD VDIFF(d)(o) RL VO(CANH) VO(CANL) STB Dominant Recessive ~3.5V: VO(CANH) ~2.5V ~1.5V: VO(CANL) Figure 2. CAN Bus Driver Circuit Transceiver 300 W +/- 1% CANH 0V VDIFF(d)(o) TXD RL +_ CANL STB -12V <= VTEST <= +12V 300 W +/- 1% Figure 3. CAN Bus Driver (Dominant) Test Circuit Transceiver TXD VDIFF(d)(o) RL VO(CANH) V1 VO(CANL) STB Figure 4. Driver Output Symmetry Test. HOLT INTEGRATED CIRCUITS 7 VOM = VDD - VO(CANH) + VO(CANL) HI-3000H, HI-3001H Application and Test Information Transceiver TXD V1 VDIFF(d)(o) RL VO(CANH) VO(CANL) VOC(ss) = VO(CANH) + VO(CANL) STB 2 Figure 5. Common Mode Output Voltage Test. Transceiver CANH TXD +_ V1 -58V or +58V CANL Figure 6. CAN Bus Driver Short-Circuit Test. (Note: V1 is a pulse from 0V to VDD with duty cycle of 99% such that permanent dominant time-out is avoided). HOLT INTEGRATED CIRCUITS 8 HI-3000H, HI-3001H Application and Test Information 5V Regulator VDD TXD RXD TXD RXD VDD 3 1 7 CANH 4 RL/2 HI-3000H 5 Controller SPLIT (optional) CAN BUS VBAT RL/2 STB 8 GND 2 GND 6 CANL 5V 3.3V Regulator VDD VIO VDD TXD RXD TXD RXD 1 5 3 7 4 RL HI-3001H Controller STB GND CANH 8 2 GND Figure 7. Typical Application Connections HOLT INTEGRATED CIRCUITS 9 6 CANL CAN BUS VBAT HI-3000H, HI-3001H ORDERING INFORMATION HI - 300x PS H x PART NUMBER F PART NUMBER PS PART NUMBER LEAD FINISH 100% Matte Tin (Pb-free, RoHS compliant) PACKAGE DESCRIPTION o o 8 PIN PLASTIC NARROW BODY SOIC (8HN): -55 C to +175 C. DESCRIPTION 3000 SPLIT pin option 3001 VIO pin option HI - 300x CR H PART NUMBER CR PART CR NUMBER PACKAGE DESCRIPTION o o 8 PIN CERDIP (8D) not available Pb-free: -55 C to +200 C. DESCRIPTION 3000 SPLIT pin option 3001 VIO pin option HOLT INTEGRATED CIRCUITS 10 HI-3000H, HI-3001H REVISION HISTORY P/N Rev Date DS3000H New 12/05/12 Description of Change Initial Release HOLT INTEGRATED CIRCUITS 11 PACKAGE DIMENSIONS inches (millimeters) 8-PIN PLASTIC SMALL OUTLINE (SOIC) - NB (Narrow Body) Package Type: 8HN .193 BSC (4.90) .007 ± .003 (.175 ± .075) .236 BSC (6.00) PIN 1 .154 ± .004 (3.90 ± .09) See Detail A .016 ± .004 (.410 ± .10) 1.25 min. 0° to 8° BSC = “Basic Spacing between Centers” is theoretical true position dimension and has no tolerance. (JEDEC Standard 95) .050 BSC (1.27) .007 ± .003 (.175 ± .075) .033 ± .017 (.835 ± .435) Detail A inches (millimeters) 8-PIN CERDIP Package Type: 8D .380 ±.004 (9.652 ±.102) .005 min (.127 min) .248 ±.003 (6.299 ±.076) .039 ±.006 (.991 ±.154) .100 BSC (2.54) .015 min (.381min) .200 max (5.080 max) .314 ±.003 (7.976 ±.076) Base Plane .010 ±.006 (.254 ±.152) Seating Plane .163 ±.037 (4.140 ±.940) .056 ±.006 (1.422 ±.152) .018 ±.006 (.457 ±.152) BSC = “Basic Spacing between Centers” is theoretical true position dimension and has no tolerance. (JEDEC Standard 95) HOLT INTEGRATED CIRCUITS 12 .350 ±.030 (8.890 ±.762)