NANDFLASHCTRL NAND Flash Memory Controller Core Implements a flexible controller for NAND flash memory devices from 2 to 128 Gb (single device). A smaller controller for up to 2 Gb devices is also available. The full-featured core efficiently manages the read/write interactions between a master host system and Single- or Multi-Level Cell (SLC or MLC) NAND flash memory devices. The core includes an optional direct memory access (DMA) manager, uses a comprehensive command set for easy NAND Flash memory access, automatically remaps corrupted memory blocks to improve reliability, can protect memory areas against writes with a block lock mode, has built-in power-saving features, and can boot software directly from Flash memory. The controller works with any suitable memory device with 2- or 4-kB page sizes supporting the Open NAND Flash Interface Working Group (ONFI) 1.0 standard. The NAND Flash Controller employs a standard OCP 2.0 socket interface to facilitate easy adaption into all types of design structures depending on the designer needs. OCP is being widely adopted due to its ease of integration and flexibility. A wrapper supporting AMBA 2 AHB master and slave is available and other structures are available by request. The Controller offers two error code correction (ECC) mechanisms from the relatively simple single-bit Hamming Code, to more sophisticated high-speed BCH (Bose, RayChaudhuri and Hocquenghem) ECC. BCH targets applications with high-density memory as well as direct boot from the NAND flash device. This third-generation product builds on silicon-proven previous versions of the controller. Developed for reuse in ASICs and FPGAs, the core is fully synchronous with positive-edge clocking, has no internal three-state buses, and uses a synchronous reset so scan insertion is straightforward. The included verification package features bus models for the AHB master and NAND flash devices to help designers verify the functioning of the core. Block Diagram Supports Single- and Multi-Level Cell (SLC and MLC) flash devices from 2 Gb to 32Gb for SLC and 128 Gb for MLC The maximum memory space supported is 128 Gbits * 128 devices for a total of 2TB Supports 2 kB and 4 kB page sizes for fast memory operations Configurable number of banks has a maximum of 128 Command interface conforms to ONFI Standard 1.0 for compatibility with major manufacturers (e.g., Samsung, Micron, STMicroelectronics, etc.) Configurable number of memory banks and devices per bank − Define number of chip select, ready/busy, and write protect signals − Allows different memory for each bank Enables booting from flash, with configurable boot sequence OCP 2.0 socket interface for easy integration with any system bus Optional AMBA™ system interface wrapper supports AHB specification 2.0 − 32-/16-/8-bits data transfers with 32-bit bus giving the advantage of higher throughput − burst transfers support − responses (OK, RETRY & SPLIT) Custom development of system bus wrappers Adapts to a variety of system and memory types, with configurable: − timing parameters − 4/5 address cycles − 8/32 I/O memory support − ECC calculation turn on/off − Write/Erase Protection area − Interrupt enable/disable Two options for ECC: − Simple Hamming-Code me- chanism (for SLC devices) − Sophisticated BCH multiple- bit mechanism (for MLC devices) March 2009 Features (Continued) • Built-in optional Direct Memory Access (DMA) manager to speed data transfer and off-load the host • Bad Block management supports Automatic Write/Read Page (with data correction)Advanced memory access modes - Cache read/write - Two-plane access • Power Save Mode for low-power applications that uses a gated clock for ECC • Easily adjustable parameters - Endian Type (Big or Little) - Easy to model timing and insure efficient operation with a variety of memory types • Custom NAND Flash Controller Driver available; allows designer to develop system software without detailed NAND flash controller knowledge Applications The core is suitable for controlling embedded storage (e.g. in mobile devices, network routers, and point-of-sale systems) and solid state device (SSD) mass storage for USB flash drives, digital cameras, laptops, and more. NAND Flash Controller Software Driver • Written in “C” • Contains functions which support common memory functions • Contains functions which support custom memory features of Micron, Samsung and ST devices • DMA support module configures DMA and transmits data • Configurable to reduce resource requirements • Hardware mapping of memory blocks • See associated datasheet Functional Description The NANDFLASH-CTRL core is partitioned into modules and comes with external elements as shown in the block diagram and described below. AHB WRAPPERS SL & MS This example connects internal blocks to the external AHB bus using the core’s OCP socket standard with the optional AMBA system interface wrapper. BIU FSM The main component responsible for handling memory devices, it comprises a set of SFRs that define the parameters of transfer to/from Flash memory. It monitors an instruction register and takes action as defined by any new instruction. Sends busy message to the BIU during instruction execution, and then sets a status flag indicating successful execution or not. After reset, it either goes IDLE or executes a “Boot sequence”, loading a CPU start-up page from the Flash memory to the BUFFER. DMA Speeds up data transfer between a device on the AHB bus and the memory, and decreases AHB bus burden. BUFFER An internal memory used by the FSM during the automatic Page Read/Write process. It helps optimize bus traffic time and supports burst read and write operations and can be used to boot the system from the memory. ARBITER Grants access to the BUFFER for other controller subcomponents. CLK SYNCH Synchronizes clock signals hclk (system) and fclk (controller, turned off in Power Save Mode). ECC Detects and corrects errors in the page data area. Error handling is automatic when transfer is realized using the BUFFER. The user can choose a simple ECC block that can correct a single error in the data area (suitable for SLC memories), or a more advanced ECC block that can correct multiple errors in the data area (for MLC memories). Implementation Results NANDFLASH-CTRL reference designs have been evaluated in a variety of technologies. The following are sample Actel results for the core implemented with Hamming ECC and 2KB page size. Actel Device Igloo AGL600V5-STD ProASICPLUS APA600-STD ProASIC3 A3P600-2 Fusion AFS600-2 Cells Sequ (R) Comb (C) RAM Blocks I/Os Fmax (MHz) 2077 8033 8 146 29 1184 5726 16 146 31 2088 7996 8 146 47 2119 8010 8 146 47 Opens a window in the address space where the BUFFER and all SFRs are visible, providing access to these elements. Works as glue logic between the system interface and internal controller bus, coordinating their interaction. Contains a register for turning on/off Power Save Mode, and is the only component not switched off in that Mode. CAST, Inc. Page 2 Example Application Support The core as delivered is warranted against defects for 90 days from purchase. Thirty days of phone and email technical support are included, starting with the first interaction. Additional maintenance and support options are available. Verification For this USB thumb drive, the core is implemented with an internal BUFFER and tri-state buffers. Data goes through a USB controller with an AHB interface (CUSB_AHB), and a C68000-AHB processor manages everything. Small SLC Devices The core is available in a smaller version to support the following SLC devices: Toshiba TC58DVG02A1FT00, TC58DVM82A1FT00, TC58DVM92A1FT00, TC58512FT Samsung K9F1208D0A, K9F1208U0A, K9F1216D0A, K9F1216U0A, K9F5608U0B, K9F5616U0B Extensive verification has been performed, using code coverage tests, simulation with multiple tools, and implementation and testing in an FPGA demonstration system. Verification has been performed with many different devices from Micron, Samsung and STM. Deliverables The core includes everything required for successful implementation: • Post-synthesis EDIF netlist • An example design that uses the core and illustrates how to build and connect memory and tri-state buffers • Sophisticated HDL Test Bench that instantiates the example design and related elements • Interface wrappers when ordered • Simulation script, vectors, expected results, and comparison utility • Place and route script • Comprehensive user documentation, including detailed specifications and a system integration guide CAST, Inc. 11 Stonewall Court Woodcliff Lake, NJ 07677 USA tel 201-391-8300 fax 201-391-8694 Copyright © CAST, Inc. 2009, All Rights Reserved. Contents subject to change without notice. Trademarks are the property of their respective owners.