HD74AC283/HD74ACT283 4-bit Binary Full Adder with Fast Carry REJ03D0267–0200Z (Previous ADE-205-388 (Z)) Rev.2.00 Jul.16.2004 Description The HD74AC283/HD74ACT283 high-speed 4-bit binary full adder with internal carry lookahead accepts two 4-bit binary works (A0 – A3, B0 – B3) and a Carry input (C0). It generates the binary Sum outputs (S0 – S3) and the Carry output (C4) from the most significant bit. The HD74AC283/HD74ACT283 will operate with either active High or active Low operands (positive or negative logic). Features • Outputs Source/Sink 24 mA • HD74ACT283 has TTL-Cmpatible Inputs • Ordering Information: Ex. HD74AC283 Part Name HD74AC283AP Package Type Package Code Package Abbreviation Taping Abbreviation (Quantity) DIP-16 pin DP-16E, -16FV P — FP-16DAV FP EL (2,000 pcs/reel) HD74AC283ARPEL SOP-16 pin (JEDEC) FP-16DNV RP EL (2,500 pcs/reel) HD74AC283TELL T ELL(2,000 pcs/reel) HD74AC283AFPEL SOP-16 pin (JEITA) TSSOP-16 pin TTP-16DAV Notes: 1. Please consult the sales office for the above package availability. 2. The packages with lead-free pins are distinguished from the conventional products by adding V at the end of the package code. Pin Arrangement S1 1 16 VCC B1 2 15 B2 A1 3 14 A2 S0 4 13 S2 A0 5 12 A3 B0 6 11 B3 C0 7 10 S3 GND 8 9 C4 (Top view) Rev.2.00, Jul.16.2004, page 1 of 9 HD74AC283/HD74ACT283 Logic Symbol A0 B0 A1 B1 A2 B2 A3 B3 C0 C4 S0 S1 S2 S3 Pin Names A0 – A3 B0 – B3 C0 S0 – S3 C4 A Operand Inputs B Operand Inputs Carry Input Sum Outputs Carry Output Functional Description The HD74AC283/HD74ACT283 adds two 4-bit binary words (A plus B) plus the incoming Carry (C0). The binary sum appears on the Sum (S0 – S3) and outgoing carry (C4) outputs. The binary weight of the various inputs and outputs is indicated by the subscript numbers, representing powers of two. 20 (A0 + B0 + C0) + 21 (A1 + B1) + 22 (A2 + B2) + 23 (A3 + B3) = S0 + 2S1 + 4S2 + 8S3 + 16C4 Where (+) = plus Interchanging inputs of equal weight does not affect the operation. Thus C0, A0, B0 can be arbitrarily assigned to pins 5, 6 and 7 for DIPS. Due to the symmetry of the binary add function, the HD74AC283/HD74ACT283 can be used either with all inputs and outputs active High (positive logic) or with all inputs and outputs active Low (negative logic). See Figure a. Note that if C0 is not used it must be tied Low for active High logic or tied High for active Low logic. Due to pin limitations, the intermediate carries of the HD74AC283/HD74ACT283 are not brought out for use as inputs or outputs. However, other means can be used to effectively insert a carry into, or bring a carry out from, an intermediate stage. Figure b shows how to make a 3-bit adder. Tying the operand inputs of the fourth adder (A3, B3) Low makes S3 dependent only on, and equal to, the carry from the third adder. Using somewhat the same principle Figure c shows a way of dividing the HD74AC283/HD74ACT283 into a 2-bit and a 1-bit adder. The third stage adder (A2, B2, S2) is used merely as a means of getting a carry (C10) signal into the fourth stage (via A2 and B2) and bringing out the carry from the second stage on S2. Note that as long as A2 and B2 are the same, whether High or Low, they do not influence S2. Similarly, when A2 and B2 are the same the carry into the third stage does not influence the carry out of the third stage. Figure d shows a method of implementing a 5-input encoder, where the inputs are equally weighted. The outputs S0, S1 and S2 present a binary number equal to the number of inputs I1 – I5 that are true. Figure e shows one method of implementing a 5-input majority gate. When three or more of the inputs I1 – I5 are true, the output M5 is true. Fig. a Active HIGH varsus Active LOW Interpretation C0 A0 A1 A2 A3 B0 B1 B2 B3 S0 S1 S2 S3 C4 Logic levels Active HIGH L 0 L 0 H 1 L 0 H 1 H 1 L 0 L 0 H 1 H 1 H 1 L 0 L 0 H 1 Active LOW 1 1 0 1 0 0 1 1 0 0 0 1 1 0 Active HIGH: 0 + 10 + 9 = 3 + 16 Active LOW: 1 + 5 + 6 = 12 + 0 Rev.2.00, Jul.16.2004, page 2 of 9 HD74AC283/HD74ACT283 L A0 B0 A1 B1 A2 B2 A3 B3 C0 C4 S0 S1 S2 S3 C3 Fig. b 3-bit Adder C10 C0 A0 B0 A1 B1 A10 B10 A0 B0 A1 B1 A2 B2 A3 B3 C0 C4 S0 S1 S2 S3 S0 S1 C2 S10 Fig. c 2-bit and 1-bit adders I3 I1 I2 L I4 I5 A0 B0 A1 B1 A2 B2 A3 B3 C0 C4 S0 S1 S2 20 21 22 S3 Fig. d 5-Input Encoder Rev.2.00, Jul.16.2004, page 3 of 9 C11 HD74AC283/HD74ACT283 I3 I1 I2 I4 I5 A0 B0 A1 B1 A2 B2 A3 B3 C0 C4 S0 S1 S2 S3 M5 Fig. e 5-Input Majority Gate Logic Diagram C0 A0 S0 B0 A1 S1 B1 A2 S2 B2 A3 S3 B3 C4 Please note that this diagram is provided only for the understanding of logic operations and shoudl not be used to estimate propagation delays. Rev.2.00, Jul.16.2004, page 4 of 9 HD74AC283/HD74ACT283 Absolute Maximum Ratings Item Symbol Ratings Unit Condition Supply voltage DC input diode current VCC IIK –0.5 to 7 –20 V mA VI 20 –0.5 to Vcc+0.5 mA V VI = Vcc+0.5V DC input voltage DC output diode current IOK –50 50 mA mA VO = –0.5V VO = Vcc+0.5V DC output voltage DC output source or sink current VO IO –0.5 to Vcc+0.5 ±50 V mA DC VCC or ground current per output pin Storage temperature ICC, IGND Tstg ±50 –65 to +150 mA °C VI = –0.5V Recommended Operating Conditions: HD74AC283 Item Symbol Ratings Unit Supply voltage Input and output voltage VCC VI, VO 2 to 6 0 to VCC V V Operating temperature Input rise and fall time (except Schmitt inputs) VIN 30% to 70% VCC Ta tr, tf –40 to +85 8 °C ns/V Condition VCC = 3.0V VCC = 4.5 V VCC = 5.5 V DC Characteristics: HD74AC283 Item Input Voltage Symbol Unit Condition min. 2.1 typ. 1.5 max. — min. 2.1 max. — 4.5 5.5 3.15 3.85 2.25 2.75 — — 3.15 3.85 — — 3.0 4.5 — — 1.50 2.25 0.9 1.35 — — 0.9 1.35 5.5 3.0 — 2.9 2.75 2.99 1.65 — — 2.9 1.65 — 4.5 5.5 4.4 5.4 4.49 5.49 — — 4.4 5.4 — — 3.0 4.5 2.58 3.94 — — — — 2.48 3.80 — — 5.5 3.0 4.94 — — 0.002 — 0.1 4.80 — — 0.1 4.5 5.5 — — 0.001 0.001 0.1 0.1 — — 0.1 0.1 3.0 4.5 — — — — 0.32 0.32 — — 0.37 0.37 IIN 5.5 5.5 — — — — 0.32 ±0.1 — — 0.37 ±1.0 µA VIN = VCC or GND IOLD IOHD 5.5 5.5 — — — — — — 86 –75 — — mA mA VOLD = 1.1 V VOHD = 3.85 V — 80 µA VIN = VCC or ground VOH VOL Input leakage current Dynamic output current* Ta = –40 to +85°°C 3.0 VIH VIL Output voltage Ta = 25°°C Vcc (V) Quiescent supply 5.5 — — 8.0 ICC current *Maximum test duration 2.0 ms, one output loaded at a time. Rev.2.00, Jul.16.2004, page 5 of 9 V VOUT = 0.1 V or VCC –0.1 V VOUT = 0.1 V or VCC –0.1 V V VIN = VIL or VIH IOUT = –50 µA VIN = VIL or VIH IOH = –12 mA IOH = –24 mA IOH = –24 mA VIN = VIL or VIH IOUT = 50 µA VIN = VIL or VIH IOL = 12 mA IOL = 24 mA IOL = 24 mA HD74AC283/HD74ACT283 Recommended Operating Conditions: HD74ACT283 Item Symbol Ratings Unit Supply voltage Input and output voltage VCC VI, VO 2 to 6 0 to VCC V V Operating temperature Input rise and fall time (except Schmitt inputs) VIN 0.8 to 2.0 V Ta tr, tf –40 to +85 8 °C ns/V Condition VCC = 4.5V VCC = 5.5V DC Characteristics: HD74ACT283 Item Input voltage Output voltage Symbol Ta = 25°°C VCC (V) Ta = –40 to +85°°C VIH 4.5 min. 2.0 VIL 5.5 4.5 2.0 — 1.5 1.5 — 0.8 2.0 — — 0.8 VOH 5.5 4.5 — 4.4 1.5 4.49 0.8 — — 4.4 0.8 — 5.5 4.5 5.4 3.94 5.49 — — — 5.4 3.80 — — 5.5 4.5 4.94 — — 0.001 — 0.1 4.80 — — 0.1 5.5 4.5 — — 0.001 — 0.1 0.32 — — 0.1 0.37 VOL typ. 1.5 max. — min. 2.0 max. — Unit V Condition VOUT = 0.1 V or Vcc–0.1 V VOUT = 0.1 V or Vcc–0.1 V V VIN = VIL or VIH IOUT = –50 µA VIN = VIL IOH = –24 mA IOH = –24 mA VIN = VIL or VIH IOUT = 50 µA VIN = VIL IOL = 24 mA Input current IIN 5.5 5.5 — — — — 0.32 ±0.1 — — 0.37 ±1.0 µA VIN = VCC or GND ICC/input current Dynamic output current* ICCT IOLD 5.5 5.5 — — 0.6 — — — — 86 1.5 — mA mA VIN = VCC–2.1 V VOLD = 1.1 V IOHD ICC 5.5 5.5 — — — — — 8.0 –75 — — 80 mA µA VOHD = 3.85 V VIN = VCC or ground Quiescent supply current *Maximum test duration 2.0 ms, one output loaded at a time. Rev.2.00, Jul.16.2004, page 6 of 9 IOL = 24 mA HD74AC283/HD74ACT283 AC Characteristics: HD74AC283 Ta = +25°C CL = 50 pF Item Propagation delay C0 to Sn Propagation delay C0 to Sn Propagation delay Ta = –40°C to +85°C CL = 50 pF tPLH VCC (V)*1 Min 3.3 1.0 Typ 11.5 Max 15.0 1.0 Max 16.5 ns tPHL 5.0 3.3 1.0 1.0 9.5 10.5 11.5 14.0 1.0 1.0 12.5 15.5 ns 1.0 1.0 8.5 14.0 10.5 17.0 1.0 1.0 11.5 18.5 ns Symbol Min Unit tPLH 5.0 3.3 An or Bn to Sn Propagation delay tPHL 5.0 3.3 1.0 1.0 11.5 13.5 13.5 16.5 1.0 1.0 14.5 18.0 ns An or Bn to Sn Propagation delay tPLH 5.0 3.3 1.0 1.0 11.0 9.5 13.0 12.5 1.0 1.0 14.0 15.5 ns C0 to C4 Propagation delay tPHL 5.0 3.3 1.0 1.0 7.5 10.0 9.5 13.0 1.0 1.0 10.5 14.0 ns tPLH 5.0 3.3 1.0 1.0 8.0 11.5 10.0 14.5 1.0 1.0 11.0 16.0 ns tPHL 5.0 3.3 1.0 1.0 9.5 12.0 11.5 15.0 1.0 1.0 12.5 16.5 ns 5.0 1.0 10.0 12.0 1.0 13.0 C0 to C4 Propagation delay An or Bn to C4 Propagation delay An or Bn to C4 Note: 1. Voltage Range 3.3 is 3.3 V ± 0.3 V Voltage Range 5.0 is 5.0 V ± 0.5 V AC Characteristics: HD74ACT283 Ta = +25°C CL = 50 pF Item Symbol VCC (V)*1 Propagation delay tPLH 5.0 C0 to Sn Propagation delay tPHL 5.0 C0 to Sn Propagation delay tPLH 5.0 An or Bn to Sn Propagation delay tPHL 5.0 An or Bn to Sn Propagation delay tPLH 5.0 C0 to C4 Propagation delay tPHL 5.0 C0 to C4 Propagation delay tPLH 5.0 An or Bn to C4 Propagation delay tPHL 5.0 An or Bn to C4 Note: 1. Voltage Range 5.0 is 5.0 V ± 0.5 V Ta = –40°C to +85°C CL = 50 pF Min 1.0 Typ 11.5 Max 13.5 1.0 Min Max 14.5 ns Unit 1.0 10.0 12.0 1.0 13.0 ns 1.0 13.0 15.0 1.0 16.5 ns 1.0 12.0 14.0 1.0 15.5 ns 1.0 9.0 11.0 1.0 12.0 ns 1.0 10.0 12.0 1.0 13.0 ns 1.0 11.0 13.0 1.0 14.0 ns 1.0 11.5 13.5 1.0 14.5 ns Capacitance Item Input capacitance CIN 4.5 pF VCC = 5.5 V Power dissipation capacitance CPD 60.0 pF VCC = 5.0 V Rev.2.00, Jul.16.2004, page 7 of 9 Symbol Typ Unit Condition HD74AC283/HD74ACT283 Package Dimensions As of January, 2003 Unit: mm 19.2 20.32 Max 9 6.3 7.4 Max 16 1 8 0.48 ± 0.1 2.54 ± 0.25 2.54 Min 5.06 Max 0.51 Min 1.3 0.89 7.62 + 0.1 0.25 – 0.05 0˚ – 15˚ Package Code JEDEC JEITA Mass (reference value) DP-16E Conforms Conforms 1.05 g Unit: mm 19.2 20.32 Max 9 6.3 7.4 Max 16 1 8 *0.48 ± 0.08 2.54 Min 5.06 Max 2.54 ± 0.25 1.3 0.51 Min 0.89 7.62 *0.25 ± 0.06 0˚ – 15˚ *NI/Pd/AU Plating Rev.2.00, Jul.16.2004, page 8 of 9 Package Code JEDEC JEITA Mass (reference value) DP-16FV Conforms Conforms 1.05 g HD74AC283/HD74ACT283 As of January, 2003 Unit: mm 10.06 10.5 Max 9 1 8 1.27 *0.40 ± 0.06 0.20 7.80 +– 0.30 1.15 0 ˚ – 8˚ 0.10 ± 0.10 0.80 Max *0.20 ± 0.05 2.20 Max 5.5 16 0.70 ± 0.20 0.15 0.12 M Package Code JEDEC JEITA Mass (reference value) *Ni/Pd/Au plating FP-16DAV — Conforms 0.24 g As of January, 2003 Unit: mm 9.9 10.3 Max 9 1 8 0.635 Max *0.40 ± 0.06 0.15 *0.20 ± 0.05 1.27 0.11 0.14 +– 0.04 1.75 Max 3.95 16 0.10 6.10 +– 0.30 1.08 0˚ – 8˚ + 0.67 0.60 – 0.20 0.25 M *Ni/Pd/Au plating Rev.2.00, Jul.16.2004, page 9 of 9 Package Code JEDEC JEITA Mass (reference value) FP-16DNV Conforms Conforms 0.15 g Sales Strategic Planning Div. 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