EM78F651N

EM78F651N
8-Bit
Microcontroller
Product
Specification
DOC. VERSION 1.6
ELAN MICROELECTRONICS CORP.
September 2013
Trademark Acknowledgments:
IBM is a registered trademark and PS/2 is a trademark of IBM.
Windows is a trademark of Microsoft Corporation.
ELAN and ELAN logo
are trademarks of ELAN Microelectronics Corporation.
Copyright © 2006~2013 by ELAN Microelectronics Corporation
All Rights Reserved
Printed in Taiwan
The contents of this specification are subject to change without further notice. ELAN Microelectronics assumes no
responsibility concerning the accuracy, adequacy, or completeness of this specification. ELAN Microelectronics
makes no commitment to update, or to keep current the information and material contained in this specification.
Such information and material may change to conform to each confirmed order.
In no event shall ELAN Microelectronics be made responsible for any claims attributed to errors, omissions, or
other inaccuracies in the information or material contained in this specification. ELAN Microelectronics shall
not be liable for direct, indirect, special incidental, or consequential damages arising from the use of such
information or material.
The software (if any) described in this specification is furnished under a license or nondisclosure agreement, and
may be used or copied only in accordance with the terms of such agreement.
ELAN Microelectronics products are not intended for use in life support appliances, devices, or systems. Use of
ELAN Microelectronics product in such applications is not supported and is prohibited.
NO PART OF THIS SPECIFICATION MAY BE REPRODUCED OR TRANSMITTED IN ANY FORM OR BY
ANY MEANS WITHOUT THE EXPRESSED WRITTEN PERMISSION OF ELAN MICROELECTRONICS.
ELAN MICROELECTRONICS CORPORATION
Headquarters:
Hong Kong:
USA:
No. 12, Innovation Road 1
Hsinchu Science Park
Hsinchu, TAIWAN 308
Tel: +886 3 563-9977
Fax: +886 3 563-9966
webmaster@emc.com.tw
http://www.emc.com.tw
Elan (HK) Microelectronics
Corporation, Ltd.
Flat A, 19F., World Tech Centre
95 How Ming Street, Kwun Tong
Kowloon, HONG KONG
Tel: +852 2723-3376
Fax: +852 2723-7780
Elan Information
Technology Group (U.S.A.)
PO Box 601
Cupertino, CA 95015
U.S.A.
Tel: +1 408 366-8225
Fax: +1 408 366-8225
Korea:
Shenzhen:
Shanghai:
Elan Korea Electronics
Company, Ltd.
Elan Microelectronics
Shenzhen, Ltd.
Elan Microelectronics
Shanghai, Ltd.
301 Dong-A Building
632 Kojan-Dong, Namdong-ku
Incheon City, KOREA
Tel: +82 32 814-7730
Fax: +82 32 813-7730
8A Floor, Microprofit Building
Gaoxin South Road 6
Shenzhen Hi-tech Industrial Park
South Area, Shenzhen
CHINA 518057
Tel: +86 755 2601-0565
Fax: +86 755 2601-0500
elan-sz@elanic.com.cn
6F, Ke Yuan Building
No. 5 Bibo Road
Zhangjiang Hi-Tech Park
Shanghai, CHINA 201203
Tel: +86 21 5080-3866
Fax: +86 21 5080-0273
elan-sh@elanic.com.cn
Contents
Contents
1
General Description ...................................................................................... 1
2
Features ......................................................................................................... 1
3
Pin Assignment.............................................................................................. 2
4
Pin Description .............................................................................................. 3
4.1
EM78F651NSS10 .............................................................................................. 3
4.2
EM78F651ND14/SO14 ...................................................................................... 3
4.3
EM78F651ND16/SO16 ...................................................................................... 4
4.4
EM78F651ND18/SO18 ...................................................................................... 4
4.5
EM78F651ND20/SS20/SO20............................................................................. 5
5
Block Diagram ............................................................................................... 6
6
Function Description..................................................................................... 7
6.1
Operational Registers......................................................................................... 7
6.1.1
6.1.2
6.1.3
6.1.4
6.1.5
6.1.6
6.1.7
6.1.8
6.1.9
6.1.10
6.1.11
6.1.12
6.1.13
6.1.14
6.2
R0 (Indirect Addressing Register) .......................................................................7
R1 (Timer Clock/Counter) ...................................................................................7
R2 (Program Counter) and Stack........................................................................7
R3 (Status Register) ..........................................................................................10
R4 (RAM Select Register).................................................................................10
R5 ~ R7 (Port 5 ~ Port 7) ..................................................................................10
R8 ~ R9 .............................................................................................................10
RA (Wake- up Control Register)........................................................................11
RB (EEPROM Control Register) .......................................................................11
RC (128 Bytes EEPROM Address) ...................................................................12
RD (128 Bytes EEPROM Data) ........................................................................12
RE (LVD Control Register) ................................................................................12
RF (Interrupt Status Register) ...........................................................................13
R10 ~ R3F .........................................................................................................13
Special Function Registers............................................................................... 14
6.2.1
6.2.2
6.2.3
6.2.4
6.2.5
6.2.6
6.2.7
6.2.8
A (Accumulator).................................................................................................14
CONT (Control Register)...................................................................................14
IOC5 ~ IOC7 (I/O Port Control Register) ..........................................................15
IOCA (WDT Control Register) ...........................................................................15
IOCB (Pull-down Control Register) ...................................................................16
IOCC (Open-drain Control Register).................................................................16
IOCD (Pull-high Control Register).....................................................................17
IOCF (Interrupt Mask Register).........................................................................17
6.3
TCC/WDT and Prescaler.................................................................................. 18
6.4
I/O Ports ........................................................................................................... 19
Product Specification (V1.6) 09.09.2013
• iii
Contents
6.5
Reset and Wake-up.......................................................................................... 22
6.5.1
6.5.2
Reset .................................................................................................................22
Status of RST, T, and P of the Status Register..................................................28
6.6
Interrupt ............................................................................................................ 30
6.7
LVD (Low Voltage Detector) ............................................................................. 32
6.8
Data EEPROM ................................................................................................. 34
6.8.1
6.8.2
6.9
Data EEPROM Control Register .......................................................................34
6.8.1.1 RB (EEPROM Control Register) ........................................................34
6.8.1.2 RC (128 Bytes EEPROM Address) ....................................................35
6.8.1.3 RD (128 Bytes EEPROM Data) .........................................................35
Programming Step / Example Demonstration...................................................35
6.8.2.1 Programming Step..............................................................................35
6.8.2.2 Example Demonstration Programs ....................................................36
Oscillator .......................................................................................................... 37
6.9.1
6.9.2
6.9.3
6.9.4
Oscillator Modes................................................................................................37
Crystal Oscillator/Ceramic Resonators (Crystal)...............................................37
External RC Oscillator Mode.............................................................................39
Internal RC Oscillator Mode ..............................................................................40
6.10 Code Option Register....................................................................................... 42
6.10.1 Code Option Register (Word 0).........................................................................42
6.10.2 Code Option Register (Word 1).........................................................................44
6.10.3 Customer ID Register (Word 2).........................................................................45
6.11 Power-on Considerations ................................................................................. 46
6.12 External Power-on Reset Circuit ...................................................................... 46
6.13 Residue-Voltage Protection.............................................................................. 47
6.14 Instruction Set .................................................................................................. 48
7
Timing Diagrams ......................................................................................... 51
8
Absolute Maximum Ratings........................................................................ 52
9
DC Electrical Characteristics...................................................................... 52
10 AC Electrical Characteristics...................................................................... 56
iv •
Product Specification (V1.6) 09.09.2013
Contents
APPENDIX
A
Package Type............................................................................................... 57
B
Package Information ................................................................................... 58
B.1 EM78F651NSS10 ............................................................................................ 58
B.2 EM78F651ND14............................................................................................... 59
B.3 EM78F651NSO14 ............................................................................................ 60
B.4 EM78F651ND16............................................................................................... 61
B.5 EM78F651NSO16 ............................................................................................ 62
B.6 EM78F651ND18............................................................................................... 63
B.7 EM78F651NSO18 ............................................................................................ 64
B.8 EM78F651ND20............................................................................................... 65
B.9 EM78F651NSS20 ............................................................................................ 66
C
ICE 652N Output Pin Assignment (JP 3).................................................... 68
D
EM78F651N Program Pin ............................................................................ 68
E
Quality Assurance and Reliability .............................................................. 69
E.1 Address Trap Detect......................................................................................... 69
F
Comparison between R-Package and U-Package .................................... 70
EM78F651N-R Package Version ............................................................................. 70
EM78F651N-U Package Version ............................................................................. 70
Product Specification (V1.6) 09.09.2013
•v
Contents
Specification Revision History
Doc. Version
1.0
1.1
Revision Description
Date
Initial version
2006/09/20
1. Modified the General Description, Pin Assignment and
Features sections.
2. Added green product information.
2006/10/20
3. Modified the Functional Block Diagram.
1. Added Quality Assurance and Reliability.
2. Modified the DC Electrical Characteristics.
1.2
3. Adjusted the Internal RC Oscillator Mode from 16 MHz
to 12 MHz.
2007/10/22
4. Added package type EM78F651NSS10J/S.
1.3
Modified the package type name.
2007/12/20
1.4
Modified the DC Electrical Characteristics.
2008/06/18
1.5
Added package type EM78F651NSO20J/S.
2008/12/01
1. Modified the package type description.
1.6
vi •
2. Modified the table entries of the Summary of Registers
Initialized Values.
2013/09/09
Product Specification (V1.6) 09.09.2013
EM78F651N
8-Bit Microcontroller
1
General Description
The EM78F651N is an 8-bit microprocessor designed and developed with low-power, high-speed CMOS
technology and high noise immunity. It has an on-chip 1K×13-bit Electrical Flash Memory and 128×8-bit in
system programmable EEPROM. It provides three protection bits to prevent intrusion of user’s Flash memory
code. Twelve Code option bits are also available to meet user’s requirements.
With its enhanced Flash-ROM feature, the EM78F651N provides a convenient way of developing and verifying
user’s programs. Moreover, this Flash-ROM device offers the advantages of easy and effective program
updates, using development and programming tools. User can avail of the ELAN Writer to easily program his
development code.
2
Features
„
CPU configuration
•
•
•
•
•
•
•
•
„
I/O port configuration
•
•
•
•
•
•
•
„
•
Operating voltage:
2.4V~5.5V at -40°C ~85°C (Industrial)
Operating voltage: 2.2V~5.5V at 0°C
~70°C (Commercial)
Three available interrupts:
•
TCC overflow interrupt
•
Input-port status changed interrupt (wake-up
from sleep mode
•
External interrupt
„ Fast set-up time requires only 2ms in high Crystal
and 32 CLKS in IRC mode from wake up to
operating mode
„ Peripheral configuration
•
8-bit real time clock/counter (TCC) with selective
signal sources, trigger edges, and overflow
interrupt
•
Power down (Sleep) mode
*Vdd power monitor and supports low voltage
detector interrupt flag
•
Four programmable Level Voltage Detector
(LVD)
•
Three security registers to prevent intrusion of
Flash memory codes
•
One configuration register to accommodate
user’s requirements
•
2-/4-/8-/16 clocks per instruction cycle selected
by code option
•
High EFT immunity
„
„
•
•
Crystal mode:
DC ~ 16 MHz @ 5V
DC ~ 8 MHz @ 3V
DC ~ 4 MHz @ 2.2V
ERC mode:
DC ~ 16 MHz @ 5V
DC ~ 8 MHz @ 3V
DC ~ 4 MHz @ 2.2V
IRC mode:
DC ~ 12 MHz @ 4.5V~5.5V
DC ~ 4 MHz @ 2.2V~5.5V
All the four main frequencies can be trimmed
by programming with five calibrated bits in the
ICE652N Simulator. Flash is auto trimmed by
ELAN FWriter.
Product Specification (V1.6) 09.09.2013
(This specification is subject to change without further notice)
Single instruction cycle commands
Four Crystal range in Oscillator Mode
Crystal Range
16 MHz ~ 6 MHz
6 MHz ~ 1 MHz
1 MHz ~ 100kHz
32.768kHz
Operating frequency range (base on two
clocks):
•
„
Two bidirectional I/O ports
Wake-up port : P6
High sink port : P6
Eight Programmable pull-down I/O pins
Eight programmable pull-high I/O pins
Eight programmable open-drain I/O pins
External interrupt : P60
Operating voltage range:
•
„
1K×13 bits on-chip ROM
80×8 bits on chip registers (SRAM)
128 bytes in-system programmable
EEPROM
*Endurance: 100,000 write/erase cycles
More than 10 years data retention
5-level stacks for subroutine nesting
Less than 2 mA at 5V/4MHz
Typically 20 µA, at 3V/32kHz
Typically 2 µA, during sleep mode
„
„
„
Oscillator Mode
HXT
XT
LXT1
LXT2
Programmable free running watchdog timer
Package type:
•
10-pin SSOP 150mil : EM78F651NSS10J/S
•
14-pin DIP 300mil
: EM78F651ND14J/S
•
14-pin SOP 150mil
: EM78F651NSO14J/S
•
16-pin DIP 300mil
: EM78F651ND16J/S
•
16-pin SOP 300mil
: EM78F651NSO16J/S
•
18-pin DIP 300 mil
: EM78F651ND18J/S
•
18-pin SOP 300mil
: EM78F651NSO18J/S
•
20-pin DIP 300mil
: EM78F651ND20J/S
•
20-pin SOP 300mil
: EM78F651NSO20J/S
•
20-pin SSOP 209mil : EM78F651NSS20J/S
Note: These are Green products which do not contain
hazardous substances.
•1
EM78F651N
8-Bit Microcontroller
3
Pin Assignment
Figure 3-1 EM78F651NSS10
Figure 3-2 EM78F651ND14/SO14
Figure 3-3 EM78F651ND16/SO16
Figure 3-4 EM78F651ND18/SO18
Figure 3-5 EM78F651ND20/SO20/SS20
2•
Product Specification (V1.6) 09.09.2013
(This specification is subject to change without further notice)
EM78F651N
8-Bit Microcontroller
4
Pin Description
4.1 EM78F651NSS10
Symbol
Pin No.
Type
P50~P51
P54~P55
10, 1
8, 9
I/O
Bidirectional 4-bit input/output pins.
P60, P66
P67
4~6
I/O
Bidirectional 3-bit input/output pins. These can be pulledhigh or can be open drain by software programming.
P60 can be pulled down by software.
9
I
OSCI
Function
Crystal type: Crystal input terminal or external clock input
pin.
ERC type: RC oscillator input pin
Crystal type: Output terminal for crystal oscillator or
external clock input pin.
RC type: Instruction clock output.
External clock signal input.
OSCO
8
I/O
/INT
4
I
External interrupt pin triggered by a falling edge.
/RESET
2
I
Input pin with Schmitt Trigger. If this pin remains at logic
low, the controller will also remain in reset condition.
VDD
7
−
Power supply
VSS
3
−
Ground
4.2 EM78F651ND14/SO14
Symbol
Pin No.
Type
13, 14
I/O
Bidirectional 2-bit input/output pins.
4~11
I/O
Bidirectional 8-bit input/output pins. These can be pulledhigh or can be open drain by software programming.
P60~63 can also be pulled down by software.
P77
1
I/O
P77 is an open drain I/O pin.
OSCI
14
I
P54~P55
P60~P67
Function
Crystal type: Crystal input terminal or external clock input
pin.
ERC type: RC oscillator input pin
Crystal type: Output terminal for crystal oscillator or
external clock input pin.
RC type: Instruction clock output.
External clock signal input.
OSCO
13
I/O
TCC
1
I
Real time clock/counter (with Schmitt Trigger input pin)
must be tied to VDD or VSS if not in use.
/INT
4
I
External interrupt pin triggered by a falling edge.
/RESET
2
I
Input pin with Schmitt Trigger. If this pin remains at logic
low, the controller will also remain in reset condition.
VDD
12
−
Power supply
VSS
3
−
Ground
Product Specification (V1.6) 09.09.2013
(This specification is subject to change without further notice)
•3
EM78F651N
8-Bit Microcontroller
4.3 EM78F651ND16/SO16
Symbol
Pin No.
Type
Function
P50, P53
P54~P55
16, 1
14, 15
I/O
P60~P67
5~12
I/O
P77
2
I/O
OSCI
15
I
OSCO
14
I/O
TCC
2
I
/INT
5
I
External interrupt pin triggered by a falling edge.
/RESET
3
I
Input pin with Schmitt Trigger. If this pin remains at logic
low, the controller will also remain in reset condition.
VDD
13
-
Power supply
VSS
4
-
Ground
Bidirectional 4-bit input/output pins.
50, P53 can be pulled-down by software.
Bidirectional 8-bit input/output pins. These can be pulledhigh or can be open drain by software programming.
P60~63 can be pulled down by software.
P77 is an open drain I/O pin.
Crystal type: Crystal input terminal or external clock input
pin.
ERC type: RC oscillator input pin
Crystal type: Output terminal for crystal oscillator or
external clock input pin.
RC type: Instruction clock output.
External clock signal input.
The real time clock/counter (with Schmitt Trigger input pin)
must be tied to VDD or VSS if not in use.
4.4 EM78F651ND18/SO18
Symbol
Pin No.
Type
P50~P53
P54~P55
17, 18, 1
2, 15, 16
I/O
P60~P67
6~13
I/O
3
I/O
P77
4•
Function
P50~P53 are bidirectional 6-bit input/output pins and can
be pulled-down by software.
Bidirectional 8-bit input/output pins. These can be pulledhigh or can be open drain by software programming.
P60~63 can also be pulled down by software.
P77 is an open drain I/O pin.
Crystal type: Crystal input terminal or external clock input
pin.
ERC type: RC oscillator input pin
Crystal type: Output terminal for crystal oscillator or
external clock input pin.
RC type: Instruction clock output.
External clock signal input.
Real time clock/counter (with Schmitt Trigger input pin)
must be tied to VDD or VSS if not in use.
OSCI
16
I
OSCO
15
I/O
TCC
3
I
/INT
6
I
External interrupt pin triggered by a falling edge.
/RESET
4
I
Input pin with Schmitt Trigger. If this pin remains at logic
low, the controller will also remain in reset condition.
VDD
14
-
Power supply
VSS
5
-
Ground
Product Specification (V1.6) 09.09.2013
(This specification is subject to change without further notice)
EM78F651N
8-Bit Microcontroller
4.5 EM78F651ND20/SO20/SS20
Symbol
Pin No.
Type
Function
P50~P57
18, 19, 2,
3, 16, 17,
1, 20
I/O
P50~P57 are bidirectional 8-it input/output pins.
P50 and P51 can also be defined as the R-option pins.
P50~P53 can be pulled-down by software.
P60~P67
7~14
I/O
Bidirectional 8-bit input/output pins. These can be pulledhigh or can be open drain by software programming.
P60~63 can be pulled down by software.
P77
4
I/O
P77 is an open drain I/O pin.
OSCI
17
I
Crystal type: Crystal input terminal or external clock input
pin.
ERC type: RC oscillator input pin
Crystal type: Output terminal for crystal oscillator or
external clock input pin.
RC type: Instruction clock output.
External clock signal input.
OSCO
16
I/O
TCC
4
I
The real time clock/counter (with Schmitt Trigger input pin)
must be tied to VDD or VSS if not in use.
/INT
7
I
External interrupt pin triggered by a falling edge.
/RESET
5
I
Input pin with Schmitt Trigger. If this pin remains at logic
low, the controller will also remain in reset condition.
VDD
15
-
Power supply
VSS
5
-
Ground
Product Specification (V1.6) 09.09.2013
(This specification is subject to change without further notice)
•5
EM78F651N
8-Bit Microcontroller
5
Block Diagram
Flash
ROM
PC
Instruction
Register
5-levelstack
(13 bi t)
Crystal
Int.
RC
Ext.
RC
Oscillation
Generator
WDT
Reset
Instruction
Decoder
P7
TCC
TCC
P77
Mux
ALU
P6
P60
P61
P62
P63
P64
P65
P66
P67
R4
RAM
ACC
R3
(Status Reg.)
LVD
Interrupt
Control
Register
LVR
P5
P50
P51
P52
P53
P54
P55
P56
P57
Interrupt
Circuit
EEPROM
Ext INT
Figure 5 Functional Block Diagram
6•
Product Specification (V1.6) 09.09.2013
(This specification is subject to change without further notice)
EM78F651N
8-Bit Microcontroller
6
Function Description
6.1 Operational Registers
6.1.1 R0 (Indirect Addressing Register)
R0 is not a physically implemented register. It is used as an indirect addressing
pointer. Any instruction using R0 as a pointer actually accesses data pointed by the
RAM Select Register (R4).
6.1.2 R1 (Timer Clock/Counter)
R1 is incremented by an external signal edge, which is defined by TE bit (CONT-4)
through the TCC pin, or by the instruction cycle clock. It is writable and readable as
any other registers. It is defined by resetting PSTE (CONT-3).
The prescaler is assigned to TCC, if the PSTE bit (CONT-3) is reset. The contents of
the prescaler counter are cleared only when the TCC register is written with a value.
6.1.3 R2 (Program Counter) and Stack
Depending on the device type, R2 and hardware stack are 10-bit wide. The structure
is depicted in Figure 6-1.
The configuration structure generates 1024×13 bits on-chip Flash ROM addresses to
the relative programming instruction codes. One program page is 1024 words long.
R2 is set as all "0"s when under a reset condition.
"JMP" instruction allows direct loading of the lower 10 program counter bits. Thus,
"JMP" allows PC to go to any location within a page.
"CALL" instruction loads the lower 10 bits of the PC and PC+1 are pushed onto the
stack. Thus, the subroutine entry address can be located anywhere within a page.
Product Specification (V1.6) 09.09.2013
(This specification is subject to change without further notice)
•7
EM78F651N
8-Bit Microcontroller
"RET" ("RETL k", "RETI") instruction loads the program counter with the contents of
the top-level stack.
"ADD R2, A" allows a relative address to be added to the current PC, and the ninth
and above bits of the PC will increase progressively.
"MOV R2, A" allows to load an address from the "A" register to the lower 8 bits of the
PC, and the ninth and tenth bits of the PC will not be changed.
Any instruction except “ADD R2, A” that is written to R2 (e.g. "MOV R2, A", "BC R2, 6",
etc.) will cause the ninth bit and the tenth bit (A8~A9) of the PC to remain unchanged.
All instructions are single instruction cycle (fclk/2 or fclk/4) except for the instruction
that would change the contents of R2. Such instruction will need one more
instruction cycle.
PC (A9 ~ A0)
Reset Vector
External INT pin interrupt vector
TCC overflow
LVD interrupt vector
Stack Level 1
Stack Level 2
006H
009H
00CH
On-chip Program
Memory
Stack Level 3
Stack Level 5
User Memory Space
Port 6 pin status change interrupt vector
000H
003H
3FFH
Figure 6-1 Program Counter Organization
8•
Product Specification (V1.6) 09.09.2013
(This specification is subject to change without further notice)
EM78F651N
8-Bit Microcontroller
Address
R PAGE Registers
IOC PAGE Registers
00
R0
(IAR)
Reserve
01
R1
(TCC)
02
R2
(PC)
Reserve
03
R3
(Status)
Reserve
04
R4
(RSR)
Reserve
05
R5
(Port 5)
IOC5
(I/O Port Control Register)
06
R6
(Port 6)
IOC6
(I/O Port Control Register)
07
R7
(Port 7)
IOC7
(I/O Port Control Register)
CONT
(Control Register)
08
Reserve
Reserve
09
Reserve
Reserve
0A
RA
(WUCR)
IOCA
(WDT Control Register)
0B
RB
(EECON)
IOCB
(Pull-down Register)
0C
RC
(EEADR)
IOCC
(Open-drain Control)
0D
RD
(EEDATA)
IOCD
(Pull-high Control Register)
0E
RE
(LVD Control)
0F
RF
(Interrupt Status)
Reserve
IOCF
(Interrupt Mask Register)
10
General Registers
1F
20
Bank 0
Bank 1
3F
Figure 6-2 Data Memory Configuration
Product Specification (V1.6) 09.09.2013
(This specification is subject to change without further notice)
•9
EM78F651N
8-Bit Microcontroller
6.1.4 R3 (Status Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
GP2
GP1
GP0
T
P
Z
DC
C
Bits 7 ~ 5 (GP2 ~ 0): General-purpose read/write bits
Bit 4 (T): Time-out bit
Set to “1” with the "SLEP" and "WDTC" commands, or during power up and
reset to ”0” by WDT time-out.
Bit 3 (P): Power down bit
Set to “1” during power on or by a "WDTC" command and reset to ”0” by a
"SLEP" command.
Bit 2 (Z): Zero flag
Set to "1" if the result of an arithmetic or logic operation is zero.
Bit 1 (DC): Auxiliary carry flag
Bit 0 (C): Carry flag
6.1.5 R4 (RAM Select Register)
Bit 7:
Not used (read only). Bit 7 is always set to “1” at all time.
Bit 6
Used to select Bank 0 or Bank 1.
Bits 5~0 are used to select registers (Address: 00~3F) in indirect addressing
mode.
Z flag of R3 is set to “1” when R4 content is equal to “3F.” When R4=R4+1, R4
content will select as R0.
See the data memory configuration in Figure 6-2.
6.1.6 R5 ~ R7 (Port 5 ~ Port 7)
R5 and R6 are I/O registers.
Only Bits 0, 1, 4 and 5 of R5 are available (EM78F651N-10Pin)
Only Bits 4 and 5 of R5 are available (EM78F651N-14Pin)
Only Bits 0, 3, 4 and 5 of R5 are available (EM78F651N-16Pin)
Only the lower 6 bits of R5 are available (EM78F651N-18Pin, EM78F651N-20Pin)
Only Bit 7 of R7 is available
6.1.7 R8 ~ R9
These are reserved registers
10 •
Product Specification (V1.6) 09.09.2013
(This specification is subject to change without further notice)
EM78F651N
8-Bit Microcontroller
6.1.8 RA (Wake- up Control Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
EM78F651N
-
ICWE
-
-
-
-
-
-
ICE652
-
ICWE
-
C4
C3
C2
C1
C0
Bit 7:
Not used. Set to “0” all the time
Bit 6 (ICWE): Port 6 input status change wake-up enable bit
0 : Disable Port 6 input status change wake-up
1 : Enable Port 6 input status change wake-up
Bit 5: Not used. Set to “0” all the time.
Bits 4~0 (C4~C0): IRC calibration bits in IRC oscillator mode.
6.1.9 RB (EEPROM Control Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RD
WR
EEWE
EEDF
EEPC
-
-
-
Bit 7: Read control register
0 : Does not execute EEPROM read
1 : Read EEPROM contents, (RD can be set by software, it is cleared by
hardware after Read instruction is completed).
Bit 6 Write control register
0 : Write cycle to the EEPROM is complete.
1 : Initiate a write cycle, (WR can be set by software, WR is cleared by
hardware after Write cycle is completed)
Bit 5 EEPROM Write Enable bit
0 : Prohibit write to the EEPROM
1 : Allows EEPROM write cycles
Bit 4 EEPROM Detective Flag
0 : Write cycle is completed
1 : Write cycle is unfinished
Bit 3 EEPROM power-down control bit
0 : Switch off the EEPROM
1 : EEPROM is operating
Bits 2 ~ 0: Not used, set to “0” at all time
Product Specification (V1.6) 09.09.2013
(This specification is subject to change without further notice)
• 11
EM78F651N
8-Bit Microcontroller
6.1.10 RC (128 Bytes EEPROM Address)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
EE_A6
EE_A5
EE_A4
EE_A3
EE_A2
EE_A1
EE_A0
Bit 7
Not used, fixed at “0”
Bits 6 ~ 0
128 bytes EEPROM address
6.1.11 RD (128 Bytes EEPROM Data)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
EE_D7
EE_D6
EE_D5
EE_D4
EE_D3
EE_D2
EE_D1
EE_D0
Bits 7 ~ 0
128 bytes EEPROM data
6.1.12 RE (LVD Control Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
-
-
-
LVDEN
/LVD
LVD1
LVD0
Bits 7 ~ 4:
Not used, set to “0” at all time
Bit 3 (LVDEN): Low Voltage Detect Enable Bit
0 : LVD disable
1 : LVD enable
Bit 2 (/LVD): Low Voltage Detector. This is a read only bit. When the VDD pin
voltage is lower than the LVD voltage interrupt level (selected by LVD1
and LVD0), this bit will be cleared.
0 : low voltage is detected
1 : low voltage is not detected or LVD function is disabled
Bit 1~Bit 0 (LVD1~LVD0): Low Voltage Detect level select bits
12 •
LVD1
LVD0
LVD Voltage Interrupt Level
0
0
2.3
0
1
3.3
1
0
4.0
1
1
4.5
Product Specification (V1.6) 09.09.2013
(This specification is subject to change without further notice)
EM78F651N
8-Bit Microcontroller
6.1.13 RF (Interrupt Status Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
LVDIF
-
-
-
-
EXIF
ICIF
TCIF
Note: “ 1 ” means with interrupt request
“ 0 ” means no interrupt occurs
Bit 7 (LVDIF): Low voltage Detector Interrupt Flag
When LVD1, LVD0 = “0, 0”, Vdd > 2.3V, LVDIF is “0”, Vdd ≤ 2.3V, set LVDIF to “1”.
LVDIF reset to “0” by software.
When LVD1, LVD0 = “0, 1”, Vdd > 3.3V, LVDIF is “0”, Vdd ≤ 3.3V, set LVDIF to “1”.
LVDIF reset to “0” by software.
When LVD1, LVD0 = “1, 0”, Vdd > 4.0V, LVDIF is “0”, Vdd ≤ 4.0V, set LVDIF to “1”.
LVDIF reset to “0” by software.
When LVD1, LVD0 = “1, 1”, Vdd > 4.5V, LVDIF is “0”, Vdd ≤ 4.5V, set LVDIF to “1”.
LVDIF reset to “0” by software.
Bits 6 ~ 3
Not used. Set all to”0”.
Bit 2 (EXIF) External Interrupt Flag. Set by a falling edge on the /INT pin, reset by
software.
Bit 1 (ICIF) Port 6 Input Status Change Interrupt Flag. Set when Port 6 input
changes, reset by software.
Bit 0 (TCIF) TCC overflow interrupt flag. Set when TCC overflows, reset by software.
RF can be cleared by instruction but cannot be set.
IOCF is the interrupt mask register.
Note that the result of reading RF is the "logic AND" of RF and IOCF.
6.1.14 R10 ~ R3F
All of these are 8-bit general-purpose registers.
Product Specification (V1.6) 09.09.2013
(This specification is subject to change without further notice)
• 13
EM78F651N
8-Bit Microcontroller
6.2 Special Function Registers
6.2.1 A (Accumulator)
Internal data transfer operation, or instruction operand holding usually involves the
temporary storage function of the Accumulator, which is not an addressable register.
6.2.2 CONT (Control Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTE
/INT
TS
TE
PSTE
PST2
PST1
PST0
Bit 7 (INTE): INT signal edge
0 : interrupt occurs at a rising edge of the INT pin
1 : interrupt occurs at a falling edge of the INT pin
Bit 6 (/INT): Interrupt Enable flag
0 : masked by DISI or hardware interrupt
1 : enabled by ENI/RETI instructions
Bit 5 (TS): TCC signal source
0 : internal instruction cycle clock
1 : transition on TCC pin
Bit 4 (TE): TCC signal edge
0 : increment if a transition from low to high takes place on the TCC pin
1 : increment if a transition from high to low takes place on the TCC pin
Bit 3 (PSTE): Prescaler enable bit for TCC
0 : prescaler disable bit, TCC rate is 1:1
1 : prescaler enable bit, TCC rate is set as Bit 2~Bit 0
Bit 0 (PST0) ~ Bit 2 (PST2): TCC prescaler bits
PST2
PST1
PST0
TCC Rate
0
0
0
1:2
0
0
1
1:4
0
1
0
1:8
0
1
1
1:16
1
0
0
1:32
1
0
1
1:64
1
1
0
1:128
1
1
1
1:256
The CONT register is both readable and writable.
14 •
Product Specification (V1.6) 09.09.2013
(This specification is subject to change without further notice)
EM78F651N
8-Bit Microcontroller
6.2.3 IOC5 ~ IOC7 (I/O Port Control Register)
A value of "1" sets the relative I/O pin into high impedance, while "0" defines the
relative I/O pin as output.
Only Bits 0, 1, 4 and 5 of R5 are available (EM78F651N-10Pin)
Only Bits 4 and 5 of R5 are available (EM78F651N-14 Pin)
Only Bits 0, 3, 4 and 5 of IOC5 can be defined (EM78F651N-16 Pin)
Only the lower 6 bits of IOC5 can be defined (EM78F651N-18 Pin)
Only Bit 0 of IOC7 is available, when P77 is set as output, a pull-high resistor must be
tied to Vdd, since this is an internal open-drain circuit.
IOC5 and IOC7 registers are both readable and writable.
6.2.4 IOCA (WDT Control Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
WDTE
EIS
-
-
PSWE
PSW2
PSW1
PSW0
Bit 7 (WDTE) Control bit used to enable the Watchdog timer
0 : Disable WDT
1 : Enable WDT
WDTE is both readable and writable.
Bit 6 (EIS):
Control bit used to define the function of P60 (/INT) pin
0 : P60, bidirectional I/O pin
1 : /INT, external interrupt pin. In this case, the I/O control bit of P60
(Bit 0 of IOC6) must be set to "1".
When EIS is "0", the path of /INT is masked. When EIS is "1", the
status of /INT pin can also be read by way of reading Port 6 (R6).
Refer to Figure 6-5 (a).
EIS is both readable and writable.
Bits 5~4:
Not used, set to “0” at all time
Bit 3 (PSWE): Prescaler enable bit for WDT
0 : prescaler disable bit, WDT rate is 1:1
1 : prescaler enable bit, WDT rate is set as Bit 0~Bit 2
Bit 2 ~ Bit 0 (PSW2 ~ PSW0): WDT prescaler bits
PSW2
0
0
0
0
1
1
1
1
PSW1
0
0
1
1
0
0
1
1
PSW0
0
1
0
1
0
1
0
1
Product Specification (V1.6) 09.09.2013
(This specification is subject to change without further notice)
WDT Rate
1:2
1:4
1:8
1:16
1:32
1:64
1:128
1:256
• 15
EM78F651N
8-Bit Microcontroller
6.2.5 IOCB (Pull-down Control Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
/PD7
/PD6
/PD5
/PD4
/PD3
/PD2
/PD1
/PD0
Bit 7 (/PD7): Control bit used to enable the of P63 pull-down pin
0 : Enable internal pull-down
1 : Disable internal pull-down
Bit 6 (/PD6): Control bit used to enable the P62 pull-down pin
Bit 5 (/PD5): Control bit used to enable the P61 pull-down pin
Bit 4 (/PD4): Control bit used to enable the P60 pull-down pin
Bit 3 (/PD3): Control bit used to enable the P53 pull-down pin
Bit 2 (/PD2): Control bit used to enable the P52 pull-down pin
Bit 1 (/PD1): Control bit used to enable the P51 pull-down pin
Bit 0 (/PD0): Control bit used to enable the P50 pull-down pin
The IOCB Register is both readable and writable.
6.2.6 IOCC (Open-drain Control Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
OD7
OD6
OD5
OD4
OD3
OD2
OD1
OD0
Bit 7 (OD7): Control bit used to enable open-drain output of the P67 pin
0 : Disable open-drain output
1 : Enable open-drain output
Bit 6 (OD6): Control bit used to enable the P66 open-drain output pin
Bit 5 (OD5): Control bit used to enable the P65 open-drain output pin
Bit 4 (OD4): Control bit used to enable the P64 open-drain output pin
Bit 3 (OD3): Control bit used to enable the P63 open-drain output pin
Bit 2 (OD2): Control bit used to enable the P62 open-drain output pin
Bit 1 (OD1): Control bit used to enable the P61 open-drain output pin
Bit 0 (OD0): Control bit used to enable the P60 open-drain output pin
The IOCC Register is both readable and writable.
16 •
Product Specification (V1.6) 09.09.2013
(This specification is subject to change without further notice)
EM78F651N
8-Bit Microcontroller
6.2.7 IOCD (Pull-high Control Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
/PH7
/PH6
/PH5
/PH4
/PH3
/PH2
/PH1
/PH0
Bit 7 (/PH7): Control bit used to enable the P67 pull-high pin
0 : Enable internal pull-high
1 : Disable internal pull-high
Bit 6 (/PH6): Control bit used to enable the P66 pull-high pin
Bit 5 (/PH5): Control bit used to enable the P65 pull-high pin
Bit 4 (/PH4): Control bit used to enable the P64 pull-high pin
Bit 3 (/PH3): Control bit used to enable the P63 pull-high pin
Bit 2 (/PH2): Control bit used to enable the P62 pull-high pin
Bit 1 (/PH1): Control bit used to enable the P61 pull-high pin
Bit 0 (/PH0): Control bit used to enable the P60 pull-high pin
The IOCD Register is both readable and writable.
6.2.8 IOCF (Interrupt Mask Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
LVDIE
-
-
-
-
EXIE
ICIE
TCIE
Bit 7 (LVDIE): LVDIF interrupt enable bit
0 : Disable LVDIF interrupt
1 : Enable LVDIF interrupt
Bits 6~3:
Not used, set to “0” at all time
Bit 2 (EXIE): EXIF interrupt enable bit
0 : Disable EXIF interrupt
1 : Enable EXIF interrupt
Bit 1 (ICIE): ICIF interrupt enable bit
0 : Disable ICIF interrupt
1 : Enable ICIF interrupt
Bit 0 (TCIE): TCIF interrupt enable bit
0 : Disable TCIF interrupt
1 : Enable TCIF interrupt
Product Specification (V1.6) 09.09.2013
(This specification is subject to change without further notice)
• 17
EM78F651N
8-Bit Microcontroller
Individual interrupt is enabled by setting its associated control bit in the IOCF to "1".
Global interrupt is enabled by the ENI instruction and is disabled by the DISI instruction.
Refer to Figure 6-8.
The IOCF register is both readable and writable.
6.3 TCC/WDT and Prescaler
There are two 8-bit counters available as prescalers for the TCC and WDT respectively.
The PST0~PST2 bits of the CONT register are used to determine the ratio of the TCC
prescaler. Likewise, the PSW0~PSW2 bits of the IOCE0 register are used to
determine the WDT prescaler. The prescaler counter will be cleared by the
instructions each time they are written into TCC. The WDT and prescaler will be
cleared by the “WDTC” and “SLEP” instructions. Figure 6-3 depicts the circuit
diagram of TCC/WDT.
R1 (TCC) is an 8-bit timer/counter. The TCC clock source can be an internal clock or
external signal input (edge selectable from the TCC pin). If TCC signal source is from
the internal clock, TCC will be incremented by 1 at every instruction cycle (without
prescaler). As illustrated in Figure 6-3, selection of CLK=Fosc/2, CLK=Fosc/4,
CLK=Fosc/8 or CLK=Fosc/16 depends on the Code Option bit <CLKS1, CLKS0>.
If the TCC signal source is from an external clock input, TCC will be incremented by 1
at every falling edge or rising edge of the TCC pin. TCC pin input time length (kept in
High or low level) must be greater than 1CLK. The TCC will stop running when sleep
mode occurs.
The Watchdog Timer is a free running on-chip RC oscillator. The WDT will keep on
running even after the oscillator driver has been turned off (i.e. in sleep mode).
During normal operation or sleep mode, a WDT time-out (if enabled) will cause the
device to reset. The WDT can be enabled or disabled at any time during normal
mode by software programming. Refer to WDTE bit of IOCE0 register. With no
prescaler, the WDT time-out period is approximately 18 ms1 (one oscillator start-up
timer period).
It is recommended to use Port 6 Input Status Change Interrupt if user wants to
use the Interrupt function.
1
18 •
Note: VDD=5V, WDT time-out period = 16.5ms ± 8%
VDD=3V, WDT time-out period = 18ms ± 8%.
Product Specification (V1.6) 09.09.2013
(This specification is subject to change without further notice)
EM78F651N
8-Bit Microcontroller
Figure 6-3 Block Diagram of TCC and WDT
6.4 I/O Ports
The I/O registers, Port 5, Port 6 and Port 7, are bidirectional tri-state I/O ports. Port 6
can be pulled high internally by software. In addition, Port 6 can also have opendrain output by software. Input status change interrupt (or wake-up) function on Port 6
P50 ~ P53 and P60 ~ P63 pins can be pulled down by software. Each I/O pin can be
defined as "input" or "output" pin by the I/O control register (IOC5 ~ IOC7). When
Port 70 is set as output, the internal circuit becomes open-drain, so it must be tied to
pull-high to work normally.
The I/O registers and I/O control registers are both readable and writable. The I/O
interface circuits for Port 5, Port 6 and Port 7 are shown in the following Figures 6-4,
6-5 (a), 6-5 (b), and Figure 6-6.
Product Specification (V1.6) 09.09.2013
(This specification is subject to change without further notice)
• 19
EM78F651N
8-Bit Microcontroller
PCRD
Q
_
Q
PORT
Q
_
Q
P
R
C
L
D
P
R
C
L
PCWR
CLK
IOD
D
PDWR
CLK
PDRD
0
1
M
U
X
Note: Pull-down is not shown in the figure.
Figure 6-4 Port 5 and Port 7.0 I/O Port and I/O Control Register Circuit
PCRD
P
Q R D
_ CLK
Q C
L
P60 /INT
Q
_
Q
PORT
Bit 2 of IOCF
0
P Q
R
CLK _
C Q
L
D
1
P
R D
CLK
C
L
PCWR
IOD
PDWR
M
U
X
PDRD
T10
P
R Q
CLK _
C Q
L
D
INT
Note: Pull-high (down) and Open-drain are not shown in the figure.
Figure 6-5 (a) P60 (/INT) I/O Port and I/O Control Register Circuit
20 •
Product Specification (V1.6) 09.09.2013
(This specification is subject to change without further notice)
EM78F651N
8-Bit Microcontroller
PCRD
P
Q R D
_ CLK
Q C
L
P61~P67
PORT
PCWR
IOD
P D
Q R
_ CLK
Q C
L
0
1
PDWR
M
U
X
TIN
PDRD
P
R
CLK
C
L
D
Q
_
Q
Note: Pull-high (down) and Open-drain are not shown in the figure.
Figure 6-5 (b) P61~P67 I/O Port and I/O Control Register Circuit
IOCE.1
D
P
R
Q
Interrupt
CLK
_
C Q
L
RE.1
ENI Instruction
P
D R Q
T10
T11
CLK
_
C Q
L
P
Q R
D
CLK
_
Q C
L
T17
DISI Instruction
/SLEP
Interrupt
(Wake-up from SLEEP)
Next Instruction
(Wake-up from SLEEP)
Figure 6-5 (c) Block Diagram of I/O Port 6 with Input Change Interrupt/Wake-up
Product Specification (V1.6) 09.09.2013
(This specification is subject to change without further notice)
• 21
EM78F651N
8-Bit Microcontroller
Table 6 Usage of Port 6 Input Change Wake-up/Interrupt Function
Usage of Port 6 Input Status Change Wake-up/Interrupt
(I) Wake-up from Port 6 Input Status
Change
(II) Port 6 Input Status Change Interrupt
(a) Before Sleep
1. Read I/O Port 6 (MOV R6,R6)
1. Disable WDT2 (use this very
carefully)
2. Execute "ENI"
2. Read I/O Port 6 (MOV R6,R6)
3. Enable interrupt (Set IOCF.1)
3 a. Enable interrupt (Set IOCF.1), after
wake-up if “ENI”, switch to Interrupt
Vector (006H), if “DISI”, excute the
next instruction
4. If Port 6 change (interrupt) →
Interrupt Vector (006H)
3 b. Disable interrupt (Set IOCF.1),
always execute the next instruction
4. Enable wake-up enable bit
(Set RA.6)
5 a. Execute "SLEP" instruction
b. After Wake-up
1. IF "ENI" → Interrupt Vector (006H)
2. IF "DISI" → Next instruction
6.5 Reset and Wake-up
6.5.1 Reset
A reset is initiated by one of the following events:
(1) Power-on reset
(2) /RESET pin input "low"
(3) WDT time-out (if enabled)
The device is kept in a reset condition for a period of approx. 18ms3 (one oscillator
start-up timer period) after the reset is detected. And if the /Reset pin goes “low” or
WDT time-out is active, a reset is generated, in RC mode the reset time is 34 clocks,
High crystal mode reset time is 2 ms and 32 clocks. In low crystal mode, the reset
time is 500 ms.
2
Note: Software disables WDT (watchdog timer) but hardware must be enabled before applying
Port 6 Change Wake-up function. (Code Option Register and Bit 11 (ENWDTB-) set to “1”).
3
Vdd = 5V, set up time period = 16.8ms ± 8%
Vdd = 3V, set up time period = 18ms ± 8%
22 •
Product Specification (V1.6) 09.09.2013
(This specification is subject to change without further notice)
EM78F651N
8-Bit Microcontroller
Once a reset occurs, the following functions are performed. Refer to Figure 6-7.
„
The oscillator is running, or will be started.
„
The Program Counter (R2) is set to all "0".
„
All I/O port pins are configured as input mode (high-impedance state).
„
The Watchdog timer and prescaler are cleared.
„
When power is switched on, the upper three bits of R3 are cleared.
„
The bits of the RB, RC, RD, RD, RE registers are set to their previous status.
„
The bits of the CONT register are set to all "1" except for Bit 6 (INT flag).
„
The bits of the IOCA register are set to all "1".
„
The bits of the IOCB register are set to all "1".
„
The IOCC register is cleared.
„
The bits of the IOCD register are set to all "1".
„
Bit 7 of the IOCE register is set to "1", and Bits 4 and 6 are cleared.
„
Bits 0~2 of RF and Bits 0~2 of IOCF register are cleared.
Sleep (power down) mode is asserted by executing the “SLEP” instruction. While
entering sleep mode, WDT (if enabled) is cleared but keeps on running. After a wakeup in RC mode, the wake-up time is 34 clocks. High crystal mode wake-up time is 2 ms
and 32 clocks. In low crystal mode, the wake-up time is 500 ms. The controller can be
awakened by:
(1) External reset input on /RESET pin
(2) WDT time-out (if enabled), or
(3) Port 6 input status changes (if enabled)
The first two cases will cause the EM78F651N to reset. The T and P flags of R3 can
be used to determine the source of the reset (wake-up). The third case must set the
RA Bit 6 to 1 bit to determine the wake-up source to wake-up the EM78F651N.
Before SLEP instruction, enable the IOCF.1, the third case is considered the
continuation of program execution and the global interrupt ("ENI" or "DISI" being
executed) determines whether or not the controller branches to the interrupt vector
following a wake-up. If ENI is executed before SLEP, the instruction will begin to
execute from Address 006H after wake-up. If DISI is executed before SLEP, the
operation will restart from the succeeding instruction right next to SLEP after wakeup. In IOCF.1 disable before SLEP instruction, after wake-up the EM78F651N will
restart and execute the next instruction sequentially.
Product Specification (V1.6) 09.09.2013
(This specification is subject to change without further notice)
• 23
EM78F651N
8-Bit Microcontroller
Case 2, can be enabled before entering Sleep mode and Case 3 must be disabled.
That is,
[a] If Port 6 Input Status Change Interrupt and External interrupt(/INT) are enabled
before SLEP, WDT must be disabled by software. However, the WDT bit in the
option register remains enabled. Hence, the EM78F651N can be awakened only
by Case 1 or Case 3.
[b] If WDT is enabled before SLEP, Port 6 Input Status Change wake-up and
External interrupt (/INT) must be disabled. Hence, the EM78F651N can be
awakened only by Case 1 or Case 2. Refer to the section on Interrupt.
If Port 6 Input Status Change Interrupt is used to wake-up the EM78F651N, (Case [a]
above), the following instructions must be executed before SLEP:
MOV A, @xx000110b ; Select internal TCC clock
CONTW
CLR R1
; Clear TCC and prescaler
WDTC
; Clear WDT and prescaler
MOV A, @0xxx1110b ; Select WDT prescaler & disable WDT
IOW RA
MOV R6, R6
; Read Port 6
MOV A, @00000x1xb ; Enable Port 6 input change interrupt
IOW RF
ENI (or DISI)
; Enable (or disable) global interrupt
BS RA,ICWE
; Enable Port 6 input change wake up bit
SLEP
; Sleep
NOP
One problem user should be aware of, is that after waking up from Sleep mode, the
WDT would be automatically enabled. The WDT operation (being enabled or
disabled) should be handled appropriately by software after waking up from Sleep
mode.
24 •
Product Specification (V1.6) 09.09.2013
(This specification is subject to change without further notice)
EM78F651N
8-Bit Microcontroller
Table 7 Summary of Registers Initialized Values
Address
N/A
N/A
N/A
N/A
0x00
0x01
0x02
Name
IOC5
IOC6
IOC7
CONT
R0
(IAR)
R1
(TCC)
R2
(PC)
Reset Type
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit Name
C57
C56
C55
C54
C53
C52
C51
C50
Power-on
1
1
1
1
1
1
1
1
/RESET and WDT
1
1
1
1
1
1
1
1
Wake-up from Pin
Change
P
P
P
P
P
P
P
P
Bit Name
C67
C66
C65
C64
C63
C62
C61
C60
Power-on
1
1
1
1
1
1
1
1
/RESET and WDT
1
1
1
1
1
1
1
1
Wake-up from Pin
Change
P
P
P
P
P
P
P
P
Bit Name
C77
-
-
-
-
-
-
-
Power-on
1
U
U
U
U
U
U
U
/RESET and WDT
1
P
P
P
P
P
P
P
Wake-up from Pin
Change
P
P
P
P
P
P
P
P
Bit Name
INTE
/INT
TS
TE
PSTE
PST2
PST1
PST0
Power-on
1
0
1
1
1
1
1
1
/RESET and WDT
1
0
1
1
1
1
1
1
Wake-up from Pin
Change
P
P
P
P
P
P
P
P
Bit Name
-
-
-
-
-
-
-
-
Power-on
U
U
U
U
U
U
U
U
/RESET and WDT
P
P
P
P
P
P
P
P
Wake-up from Pin
Change
P
P
P
P
P
P
P
P
Bit Name
-
-
-
-
-
-
-
-
Power-on
0
0
0
0
0
0
0
0
/RESET and WDT
0
0
0
0
0
0
0
0
Wake-up from Pin
Change
P
P
P
P
P
P
P
P
Bit Name
-
-
-
-
-
-
-
-
Power-on
0
0
0
0
0
0
0
0
/RESET and WDT
0
0
0
0
0
0
0
0
Wake-up from Pin
Change
*0/P
*0/P
*0/P
*0/P
*1/P
*0/P
*0/P
*0/P
Product Specification (V1.6) 09.09.2013
(This specification is subject to change without further notice)
• 25
EM78F651N
8-Bit Microcontroller
Address
0x03
0x04
0x05
0x06
0x07
0x7~0x9
0XA
26 •
Name
R3
(SR)
R4
(RSR)
P5
P6
P7
R7~R9
RA
(WCR)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit Name
GP2
GP1
GP0
T
P
Z
DC
C
Power-on
0
0
0
1
1
U
U
U
/RESET and WDT
0
0
0
t
t
P
P
P
Wake-up from Pin
Change
P
P
P
t
t
P
P
P
Bit Name
-
-
-
-
-
-
-
-
Power-on
0
0
U
U
U
U
U
U
/RESET and WDT
0
0
P
P
P
P
P
P
Wake-up from Pin
Change
0
0
P
P
P
P
P
P
Bit Name
P57
P56
P55
P54
P53
P52
P51
P50
Power-on
U
U
U
U
U
U
U
U
/RESET and WDT
P
P
P
P
P
P
P
P
Wake-up from Pin
Change
P
P
P
P
P
P
P
P
Bit Name
P67
P66
P65
P64
P63
P62
P61
P60
Power-on
U
U
U
U
U
U
U
U
/RESET and WDT
P
P
P
P
P
P
P
P
Wake-up from Pin
Change
P
P
P
P
P
P
P
P
Bit Name
P77
×
×
×
×
×
×
×
Power-on
U
0
0
0
0
0
0
0
/RESET and WDT
P
0
0
0
0
0
0
0
Wake-up from Pin
Change
P
0
0
0
0
0
0
0
Bit Name
-
-
-
-
-
-
-
-
Power-on
1
1
1
1
1
1
1
1
/RESET and WDT
P
P
P
P
P
P
P
P
Wake-up from Pin
Change
P
P
P
P
P
P
P
P
Bit Name
-
ICWE
-
-
-
-
-
-
Power-on
0
0
0
0
0
0
0
0
/RESET and WDT
0
P
0
0
0
0
0
0
Wake-up from Pin
Change
0
P
0
0
0
0
0
0
Reset Type
Product Specification (V1.6) 09.09.2013
(This specification is subject to change without further notice)
EM78F651N
8-Bit Microcontroller
Address
0XB
0XC
Name
RB
(ECR)
RC
Reset Type
Bit 7
Bit 6
Bit Name
RD
WR
Power-on
0
0
0
0
/RESET and WDT
P
P
P
Wake-up from Pin
Change
P
P
P
Bit Name
-
Power-on
0
0
0
0
0
0
0
0
/RESET and WDT
0
P
P
P
P
P
P
P
Wake-up from Pin
Change
0
P
P
P
P
P
P
P
Bit Name
0XD
0XE
0x0F
0x0A
0x0B
RD
RE
(LVDCR)
RF
(ISR)
IOCA
(WDTCR)
IOCB
(PDCR)
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
-
-
0
0
0
0
P
P
0
0
0
P
P
0
0
0
EEWE EEDF EEPC
EE_A6 EE_A5 EE_A4 EE_A3 EE_A2 EE_A1 EE_A0
EE_D7 EE_D6 EE_D5 EE_D4 EE_D3 EE_D2 EE_D1 EE_D0
Power-on
0
0
0
0
0
0
0
0
/RESET and WDT
P
P
P
P
P
P
P
P
Wake-up from Pin
Change
P
P
P
P
P
P
P
P
Bit Name
-
-
-
-
LVDEN
/LVD
LVD1
LVD0
Power-on
0
0
0
0
0
1
0
0
/RESET and WDT
0
0
0
0
0
1
0
0
Wake-up from Pin
Change
0
0
0
0
P
P
P
P
Bit Name
LVDIF
×
×
×
×
EXIF
ICIF
TCIF
Power-on
0
0
0
0
0
0
0
0
/RESET and WDT
0
U
U
U
U
0
0
0
Wake-up from Pin
Change
P
U
U
U
U
P
P
P
Bit Name
WDTE
EIS
×
×
Power-on
1
0
U
0
1
1
1
1
/RESET and WDT
1
0
U
0
1
1
1
1
Wake-up from Pin
Change
1
P
U
P
P
P
P
P
Bit Name
/PD7
/PD6
/PD5
/PD4
/PD3
/PD2
/PD1
/PD0
Power-on
1
1
1
1
1
1
1
1
/RESET and WDT
1
1
1
1
1
1
1
1
Wake-up from Pin
Change
P
P
P
P
P
P
P
P
Product Specification (V1.6) 09.09.2013
(This specification is subject to change without further notice)
PSWE PSW2 PSW1 PSW0
• 27
EM78F651N
8-Bit Microcontroller
Address
0x0C
0x0D
0x0F
Name
IOCC
(ODCR)
IOCD
(PHCR)
IOCF
(IMR)
0x10~0x2F R10~R2F
Reset Type
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit Name
OD7
OD6
OD5
OD4
OD3
OD2
OD1
OD0
Power-on
0
0
0
0
0
0
0
0
/RESET and WDT
0
0
0
0
0
0
0
0
Wake-up from Pin
Change
P
P
P
P
P
P
P
P
Bit Name
/PH7
/PH6
/PH5
/PH4
/PH3
/PH2
/PH1
/PH0
Power-on
1
1
1
1
1
1
1
1
/RESET and WDT
1
1
1
1
1
1
1
1
Wake-up from Pin
Change
P
P
P
P
P
P
P
P
Bit Name
LVDIE
×
×
×
×
EXIE
ICIE
TCIE
Power-on
0
0
0
0
0
0
0
0
/RESET and WDT
0
0
0
0
0
0
0
0
Wake-up from Pin
Change
P
U
U
U
U
P
P
P
Bit Name
-
-
-
-
-
-
-
-
Power-on
U
U
U
U
U
U
U
U
/RESET and WDT
P
P
P
P
P
P
P
P
Wake-up from Pin
Change
P
P
P
P
P
P
P
P
Legend: “×” = not used
“P” = previous value before reset
“u” = unknown or don’t care
“t” = check Table 8
*To jump Address 0x08, or to execute the instruction next to the “SLEP” instruction.
6.5.2 Status of RST, T, and P of the Status Register
A reset condition is initiated by the following events:
1. Power-on condition
2. High-low-high pulse on /RESET pin
3. Watchdog timer time-out
The values of T and P, listed in Table 8 are used to check how the processor wakes
up. Table 9 shows the events that may affect the status of T and P.
28 •
Product Specification (V1.6) 09.09.2013
(This specification is subject to change without further notice)
EM78F651N
8-Bit Microcontroller
Table 8 Values of RST, T and P after Reset
Reset Type
T
P
1
1
*P
*P
/RESET wake-up during Sleep mode
1
0
WDT during Operating mode
0
*P
WDT wake-up during Sleep mode
0
0
Wake-up on pin change during Sleep mode
1
0
Power on
/RESET during Operating mode
* P: Previous status before reset
Table 9 Status of T and P Being Affected by Events
Event
T
P
Power on
1
1
WDTC instruction
1
1
WDT time-out
0
*P
SLEP instruction
1
0
Wake-up on pin change during Sleep mode
1
0
* P: Previous value before reset
VDD
D
CLK
Oscillator
Q
CLK
CLR
Power-on
Reset
Voltage
Detector
WDTE
WDT
WDT Timeout
Setup Time
RESET
/RESET
Figure 6-6 Block Diagram of Controller Reset
Product Specification (V1.6) 09.09.2013
(This specification is subject to change without further notice)
• 29
EM78F651N
8-Bit Microcontroller
6.6 Interrupt
The EM78F651N has three falling-edge interrupts listed below:
(1) TCC overflow interrupt
(2) Port 6 Input Status Change Interrupt
(3) External interrupt [(P60, /INT) pin]
(4) LVD (Low Voltage Detector) Interrupt
RF is the interrupt status register that records the interrupt requests in the relative
flags/bits. IOCF is the interrupt mask register. The global interrupt is enabled by the
ENI instruction and is disabled by the DISI instruction. When one of the enabled
interrupts occurs, the next instruction will be fetched from address in the priority as
shown in Table 10. Once in the interrupt service routine, the source of an interrupt
can be determined by polling the flag bits in RF. The interrupt flag bit must be
cleared by instructions before leaving the interrupt service routine and before
interrupts are enabled to avoid recursive interrupts.
When an interrupt is generated by the LVD (Low Voltage Detector), in the Code
Option, enable LVD interrupt is selected, the next instruction will be fetched from
Address 00CH.
When an interrupt is generated by the Timer clock/counter (if enabled), the next
instruction will be fetched from Address 009 (TCC).
Before the Port 6 Input Status Change Interrupt is enabled, reading Port 6 (e.g. "MOV
R6, R6") is necessary. Each Port 6 pin will have this feature if its status changes.
The Port 6 Input Status Change Interrupt will wake up the EM78F651N from sleep
mode if it is enabled prior to going into Sleep mode by executing SLEP instruction.
When wake-up occurs, the controller will continue to execute program in-line if the
global interrupt is disabled. If the global interrupt is enabled, it will branch out to the
Interrupt Vector 006H.
External interrupt equipped with digital noise rejection circuit (input pulse less than 8
system clock time is eliminated as noise), but in Low crystal oscillator (LXT)
mode the noise rejection circuit will be disabled. When an interrupt (Falling edge)
is generated by the External interrupt (when enabled), the next instruction will be
fetched from Address 003H.
The flag (except ICIF bit) in the Interrupt Status Register (RF) is set regardless of the
status of its mask bit or the execution of ENI. Note that the outcome of RF will be the
logic AND of RF and IOCF (refer to Figure 6-8). The RETI instruction ends the
interrupt routine and enables the global interrupt (the execution of ENI).
Before the interrupt subroutine is executed, the contents of ACC and the R3 and R4
register will be saved by hardware. If another interrupt occurred, the ACC, R3 and
R4 will be replaced by the new interrupt. After the interrupt service routine is finished,
ACC, R3 and R4 will be pushed back.
30 •
Product Specification (V1.6) 09.09.2013
(This specification is subject to change without further notice)
EM78F651N
8-Bit Microcontroller
VCC
P
R
D
/IRQn
CLK
RF
C
L
Q
IRQn
INT
_
Q
RFRD
IRQm
ENI/DISI
Q
IOCF
_
Q
P
R
C
L
IOD
D
CLK
IOCFWR
/RESET
IOCFRD
RFWR
Figure 6-7 Interrupt Input Circuit
Interrupt
Sources
ACC
R3
ENI/DISI
Interrupt
occurs
RETI
R4
STACKACC
STACKR3
STACKR4
Figure 6-8 Interrupt Back-up Diagram
Table 10 Interrupt Vector
Interrupt Vector
Interrupt Status
Priority
003H
External interrupt
1
006H
Port 6 pin change
2
009H
TCC overflow interrupt
3
00CH
LVD interrupt
4
Note: Priority is in descending order, i.e. 1 is the highest priority, 4 is the lowest priority
Product Specification (V1.6) 09.09.2013
(This specification is subject to change without further notice)
• 31
EM78F651N
8-Bit Microcontroller
6.7 LVD (Low Voltage Detector)
During power source unstable situations, such as external power noise interference
or EMS test condition, it will cause the power to vibrate fiercely. At the time Vdd is
unsettled, it is probably below the working voltage. When the system supply voltage,
Vdd, is below the working voltage, the IC kernel must automatically keep all register
status.
LVD property is set at Register RE, Bit 1, 0. The detailed operation mode is as
follows:
Bits 1~ 0 (LVD1~LVD0): Low Voltage Detect level control Bits.
LVD1
LVD0
LVD Voltage Interrupt Level
0
0
2.3V
0
1
3.3V
1
0
4.0V
1
1
4.5V
The LVD status and interrupt flag is referred to as RF.
Register
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RF
LVDIF
-
-
-
-
EXIF
ICIF
TCIF
Bit 7 (LVDIF): Low Voltage Detector Interrupt Flag.
When LVD1, LVD0 = “0, 0”, Vdd > 2.3V, LVDIF is “0”, Vdd ≤ 2.3V, set LVDIF to “1”.
LVDIF is reset to “0” by software.
When LVD1, LVD0 = “0, 1”, Vdd > 3.3V, LVDIF is “0”, Vdd ≤ 3.3V, set LVDIF to “1”.
LVDIF is reset to “0” by software.
When LVD1, LVD0 = “1, 0”, Vdd > 4.0V, LVDIF is “0”, Vdd ≤ 4.0V, set LVDIF to “1”.
LVDIF is reset to “0” by software.
When LVD1, LVD0 = “1, 1”, Vdd > 4.5V, LVDIF is “0”, Vdd ≤ 4.5V, set LVDIF to “1”.
LVDIF is reset to “0” by software.
The following steps are needed to setup the LVD function:
Set the LVDEN of Register RE to “1”, then use Bit 1, 0 (LVD1, LVD0) of Register RE
to set LVD interrupt level
Wait for LVD interrupt to occur.
32 •
Product Specification (V1.6) 09.09.2013
(This specification is subject to change without further notice)
EM78F651N
8-Bit Microcontroller
Clear the LVD interrupt flag
The internal LVD module uses internal circuit to fit. When the LVDEN is set to enable
the LVD module, the current consumption will increase to about 10 µA.
During sleep mode, the LVD module continues to operate. If the device voltage
drops slowly and crosses the detect point, the LVDIF bit will be set and the device will
not wake-up from Sleep mode. Until the other wake-up sources wakes up the device,
the LVD interrupt flag is still set at its prior status.
When the system resets, the LVD flag will be cleared.
Figure 6-9 shows the LVD module to detect the external voltage situation.
When Vdd drops not below VLVD, LVDIF remain at “0”.
When Vdd drops to below VLVD, LVDIF is set to “1”. If global ENI enable, LVDIF will
be set to “1”, the next instruction will branch to the interrupt vector. The LVD interrupt
flag is cleared to “0” by software.
When Vdd drops below VRESET and is less than 80 µs, the system will all maintain the
register status and system halt but oscillation is active. When Vdd drops below
VRESET and is more than 80 µs, a system reset will occur, and for the following
waveform situation, refer to Section 6.5.1 Reset Description.
LVDXIF cleared by software
Vdd
VLVD
VRESET
LVDXIF
Internal Reset
<50,40,30 us
>50,40,30 us
Vdd < Vreset not longer than 80us, system keep on going
18ms
System occur reset
Figure 6-9 LVD Waveform diagram
Product Specification (V1.6) 09.09.2013
(This specification is subject to change without further notice)
• 33
EM78F651N
8-Bit Microcontroller
6.8 Data EEPROM
The Data EEPROM is readable and writable during normal operation over the whole
Vdd range. The operation for Data EEPROM is base on a single byte. A write
operation makes an erase-then-write cycle to take place on the allocated byte.
The Data EEPROM memory provides high erase and write cycles. A byte write
automatically erases the location and writes the new value.
6.8.1 Data EEPROM Control Register
6.8.1.1 RB (EEPROM Control Register)
The EECR (EEPROM Control Register) is the control register for configuring and
initiating the control register status.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RD
WR
EEWE
EEDF
EEPC
-
-
-
Bit 7 (RD) Read control register
0 : Does not execute EEPROM read
1 : Read EEPROM content, (RD can be set by software, RD is cleared by
hardware after Read instruction is completed)
Bit 6 (WR) Write control register
0 : Write cycle to the EEPROM is completed.
1 : Initiate a write cycle, (WR can be set by software, WR is cleared by
hardware after Write cycle is completed)
Bit 5 (EEWE)
EEPROM Write Enable bit
0 : Prohibit write to the EEPROM
1 : Allows EEPROM write cycles
Bit 4 (EEDF)
EEPROM Detect Flag
0 : Write cycle is completed
1 : Write cycle is unfinished
Bit 3 (EEPC) EEPROM power-down control bit
0 : Switch off the EEPROM
1 : EEPROM is operating
Bits 2 ~ 0: Not used, set to “0” at all time
34 •
Product Specification (V1.6) 09.09.2013
(This specification is subject to change without further notice)
EM78F651N
8-Bit Microcontroller
6.8.1.2 RC (128 Bytes EEPROM Address)
When accessing the EEPROM data memory, the RC (128 bytes EEPROM address
register) holds the address to be accessed. According the operation, the RD (128
bytes EEPROM Data register) holds the data to written, or the data read, at the
address in RC.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
EE_A6
EE_A6
EE_A4
EE_A3
EE_A2
EE_A1
EE_A0
Bit 7
Not used, fixed at “0”.
Bits 6 ~ 0
128 bytes EEPROM address
6.8.1.3 RD (128 Bytes EEPROM Data)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
EE_D7
EE_D6
EE_D5
EE_D4
EE_D3
EE_D2
EE_D1
EE_D0
Bits 7 ~ 0
128 bytes EEPROM data
6.8.2 Programming Step / Example Demonstration
6.8.2.1 Programming Step
Follow these steps to write or read data from the EEPROM:
(1) Set the RC.EEPC bit to 1 to enable EEPROM power.
(2) Write the address to RC (128 bytes EEPROM address).
a.1. Set the RC.EEWE bit to 1, if the write function is employed.
a.2. Write the 8-bit data value to be programmed in the RD (128 bytes EEPROM
data)
a.3. Set the RC.WR bit to 1, then execute the write function
b.
(3) a.
b.
Set the RC.READ bit to 1, after which, execute the read function
Wait for the RC.EEDF or RC.WR to be cleared
Wait for the RC.EEDF to be cleared
(4) For the next conversion, go to Step 2 as required.
(5) If user wants to save power and to make sure the EEPROM data is not used,
clear the RC.EEPC.
Product Specification (V1.6) 09.09.2013
(This specification is subject to change without further notice)
• 35
EM78F651N
8-Bit Microcontroller
6.8.2.2 Example Demonstration Programs
;To define the control register
;Write data to EEPROM
RC == 0x0C
RB == 0x0B
RD == 0x0D
Read == 0x07
WR == 0x06
EEWE == 0x05
EEDF == 0x04
EEPC == 0x03
BS RB, EEPC
; Set the EEPROM power on
MOV A,@0x0A
MOV RC,A
; Assign the address from EEPROM
BS RB, EEWE
; Enable the EEPROM write function
MOV A,@0x55
MOV RD,A
; Set the data for EEPROM
BS RB,WR
; Write value to EEPROM
JBC RB,EEDF
; To check the EEPROM bit completed or not
JMP $-1
;To define the control register
;Read data from EEPROM
RC == 0x0C
RD == 0x0D
Read == 0x07
WR == 0x06
EEWE == 0x05
EEDF == 0x04
EEPC == 0x03
BS RB, EEPC
; Set the EEPROM power on
MOV A,@0x0A
MOV RC,A
; Assign the address from EEPROM
BS RB, Read
; Set EEPROM read function
JBC RB,EEDF
; To check the EEPROM bit completed or not
JMP $-1
MOV A,RD
36 •
Product Specification (V1.6) 09.09.2013
(This specification is subject to change without further notice)
EM78F651N
8-Bit Microcontroller
6.9 Oscillator
6.9.1 Oscillator Modes
The device can be operated in four different oscillator modes, such as Internal RC
oscillator mode (IRC), External RC oscillator mode (ERC), High Crystal oscillator
mode (HXT), and Low Crystal oscillator mode (LXT). User can select one of such
modes by programming OSC2, OCS1 and OSC0 in the Code Option register.
Table11 depicts how these four modes are defined.
The up-limited operation frequency of the crystal/resonator on the different VDD is
listed in Table 11.
Table 11 Oscillator Modes defined by OSC2 ~ OSC0
Mode
OSC2
OSC1
OSC0
XT (Crystal oscillator mode)
0
0
0
HXT (High Crystal oscillator mode)
0
0
1
LXT1 (Low Crystal 1 oscillator mode)
0
1
0
LXT2 (Low Crystal 2 oscillator mode)
0
1
1
IRC mode, OSCO (P54) act as I/O pin
1
0
0
IRC mode, OSCO (P54) act as RCOUT pin
1
0
1
ERC mode, OSCO (P54) act as I/O pin
1
1
0
ERC mode, OSCO (P54) act as RCOUT pin
1
1
1
NOTE
1. Frequency range of HXT mode is 16 MHz ~ 6 MHz.
2. Frequency range of XT mode is 6 MHz ~ 1 MHz.
3. Frequency range of LXT1 mode is 1MHz ~ 100kHz.
4. Frequency range of XT mode is 32kHz.
Table 12 Summary of Maximum Operating Speeds
Conditions
Two cycles with two clocks
VDD
Max Fxt. (MHz)
2.5V
4.0
3.0V
8.0
5.0V
16.0
6.9.2 Crystal Oscillator/Ceramic Resonators (Crystal)
The EM78F651N can be driven by an external clock signal through the OSCI pin as
shown in Figure 6-10 below.
OSCI
Ext. Clock
OSCO
Figure 6-10 Circuit for External Clock Input
Product Specification (V1.6) 09.09.2013
(This specification is subject to change without further notice)
• 37
EM78F651N
8-Bit Microcontroller
In most applications, the OSCI pin and the OSCO pin can be connected with a crystal
or ceramic resonator to generate oscillation. Figure 6-11 depicts such a circuit. The
same thing applies whether it is in the HXT mode or in the LXT mode. Table 13
provides the recommended values of C1 and C2. Since each resonator has its own
attribute, user should refer to its specification for appropriate values of C1 and C2. A
serial resistor RS, may be necessary for AT strip cut crystal or low frequency mode.
C1
OSCI
Crystal
OSCO
C2
RS
Figure 6-11 Circuit for Crystal/Resonator
Table 13 Capacitor Selection Guide for Crystal Oscillator or Ceramic Resonator
Oscillator Type
Frequency Mode
Frequency
100kHz
200kHz
LXT1
(100K~1MHz)
455kHz
Ceramic Resonators
HXT2
(1M~6 MHz)
LXT2 (32.768kHz)
LXT1
(100K~1 MHz)
Crystal Oscillator
XT
(1~6 MHz)
HXT
(6~20 MHz)
38 •
C1 (pF)
C2 (pF)
45pF
45pF
20pF
100~150pF
20pF
100~150pF
1.0 MHz
20pF
20pF
1.0 MHz
25pF
25pF
2.0 MHz
20pF
20pF
4.0 MHz
20pF
20pF
32.768kHz
40pF
40pF
100kHz
45pF
45pF
200kHz
20pF
20pF
455kHz
100~150pF
100~150pF
1.0 MHz
20pF
20pF
455kHz
100~150pF
100~150pF
1.0 MHz
20pF
20pF
2.0 MHz
20pF
20pF
4.0 MHz
20pF
20pF
6.0 MHz
20pF
20pF
6.0 MHz
25pF
25pF
8.0 MHz
20pF
20pF
10.0 MHz
20pF
20pF
12.0 MHz
20pF
20pF
16.0 MHz
15pF
15pF
20.0 MHz
10pF
10pF
Product Specification (V1.6) 09.09.2013
(This specification is subject to change without further notice)
EM78F651N
8-Bit Microcontroller
330
330
C
OSCI
7404
7404
7404
Crystal
Figure 6-12 Circuit for Crystal/Resonator-Series Mode
4.7K
10K
Vdd
OSCI
7404
7404
10K
Crystal
C1
C2
Figure 6-13 Circuit for Crystal/Resonator-Parallel Mode
6.9.3 External RC Oscillator Mode
For some applications that do not need a very precise timing calculation, the RC
oscillator (Figure 6-14) offers a cost-effective oscillator configuration. Nevertheless, it
should be noted that the frequency of the RC oscillator is influenced by the supply
voltage, the values of the resistor (Rext), the capacitor (Cext), and even by the
operation temperature. Moreover, the frequency also changes slightly from one chip
to another due to manufacturing process variation.
In order to maintain a stable system frequency, the values of the Cext should not be
less than 20pF, and that the value of Rext should not be greater than 1 MΩ. If they
cannot be kept in this range, the frequency is easily affected by noise, humidity, and
leakage.
The smaller the Rext in the RC oscillator, the faster its frequency will be. On the
contrary, for very low Rext values, for instance, 1 KΩ, the oscillator becomes unstable
since the NMOS cannot discharge correctly the current of the capacitance.
Based on the above reasons, it must be kept in mind that all of the supply voltage, the
operation temperature, the components of the RC oscillator, the package types, and
the PCB layout, will affect the system frequency.
Product Specification (V1.6) 09.09.2013
(This specification is subject to change without further notice)
• 39
EM78F651N
8-Bit Microcontroller
Vcc
Rext
OSCI
Cext
Figure 6-14 Circuit for External RC Oscillator Mode
Table 14 RC Oscillator Frequencies
Cext
20 pF
100 pF
300 pF
Rext
Average Fosc 5V, 25°C
Average Fosc 3V, 25°C
3.3k
3.3 MHz
3 MHz
5.1k
2.27 MHz
2.1 MHz
10k
1.1 MHz
1.05 MHz
100k
145kHz
145kHz
3.3k
1.02 MHz
0.98 MHz
5.1k
724kHz
694kHz
10k
360kHz
360kHz
100k
45kHz
47kHz
3.3k
400kHz
380kHz
5.1k
280kHz
270kHz
10k
143kHz
140kHz
100k
14kHz
14kHz
Note: 1: Measured based on DIP packages.
2
: The values are for design reference only.
6.9.4 Internal RC Oscillator Mode
EM78F651N offers a versatile internal RC mode with default frequency value of 4 MHz.
The Internal RC oscillator mode has other frequencies (12 MHz, 3.58 MHz and
455kHz) that can be set by Code Option (Word 1), RCM1 and RCM0. All these four
main frequencies can be calibrated by programming the Code Option (Word 1) bits,
C4~C0. Table 15 describes a typical instance of the calibration.
Table 15 Internal RC Drift Rate (Ta=25°C, VDD=5 V± 5%, VSS=0V)
Drift Rate
40 •
Internal RC
Temperature
(-40°C~85°C)
Voltage
(2.2V~5.5V)
Process
Total
4 MHz
± 3%
± 5%
± 3%
± 11%
12 MHz
± 3%
± 5%
± 4%
± 12%
3.58 MHz
± 3%
± 5%
± 4%
± 12%
455kHz
± 3%
± 5%
± 4%
± 12%
Product Specification (V1.6) 09.09.2013
(This specification is subject to change without further notice)
EM78F651N
8-Bit Microcontroller
Table 16 Calibration Selections for Internal RC Mode
C4
C3
C2
C1
C0
*Cycle Time (ns)
*Frequency (MHz)
1
1
1
1
1
399
2.506
1
1
1
1
0
385
2.6
1
1
1
0
1
371
2.693
1
1
1
0
0
358
2.786
1
1
0
1
1
347
2.879
1
1
0
1
0
336
2.973
1
1
0
0
1
326
3.066
1
1
0
0
0
316
3.159
0
1
1
1
1
307
3.253
0
1
1
1
0
298
3.346
0
1
1
0
1
290
3.439
0
1
1
0
0
283
3.533
0
1
0
1
1
275
3.626
0
1
0
1
0
268
3.719
0
1
0
0
1
262
3.813
0
1
0
0
0
256
3.906
0
0
0
0
0
250
4.00
0
0
0
0
1
244
4.093
0
0
0
1
0
238
4.186
0
0
0
1
1
233
4.279
0
0
1
0
0
228
4.373
0
0
1
0
1
223
4.466
0
0
1
1
0
219
4.559
0
0
1
1
1
214
4.653
1
0
0
0
0
210
4.746
1
0
0
0
1
206
4.839
1
0
0
1
0
202
4.933
1
0
0
1
1
198
5.026
1
0
1
0
0
195
5.119
1
0
1
0
1
191
5.213
1
0
1
1
0
188
5.306
1
0
1
1
1
185
5.4
* 1. These are theoretical values and for reference only. Actual values may vary depending on
the process.
2. Similar way of calculation is also applicable for low frequency mode.
Product Specification (V1.6) 09.09.2013
(This specification is subject to change without further notice)
• 41
EM78F651N
8-Bit Microcontroller
6.10 Code Option Register
The EM78F651N has a Code option word that is not part of the normal program
memory. The option bits cannot be accessed during normal program execution.
Code Option Register and Customer ID Register arrangement distribution:
Word 0
Word 1
Word 2
Bit 12~Bit 0
Bit 12~Bit 0
Bit 12~Bit 0
6.10.1 Code Option Register (Word 0)
Word 0
Bit
Bit 12 Bit 11
Bit 10
Bit 9
Mne
NRM NRHL
monic
NRE
CYES CLKS1 CLKS0
8/fc
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
ENWDTB OSC2 OSC1 OSC0
Bit 1
Bit 0
Protect
1
MOD2
Disable 1cycle
High
High
Enable
High
High
High
Enable
0
MOD1 32/fc Enable 2cycles
Low
Low
Disable
Low
Low
Low
Disable
Bit 12 (NRM): Noise rejection mode
1 : Noise reject Mode 2. For multi-time, using scan circuit, such as key
scan and LED output
0 : Noise reject Mode 1. For General input or output use. (Default)
Bit 11 (NRHL): Noise rejection high/low pulse define bit. INT pin is falling edge
trigger.
1 : Pulses equal to 8/fc [s] is regarded as signal
0 : Pulses equal to 32/fc [s] is regarded as signal (default)
NOTE
The noise rejection function is turned off in the LXT2 and sleep mode.
Bit 10 (NRE): Noise rejection enable (depending on the EM78F651N). The INT pin is
falling edge triggered.
1 : Disable noise rejection
0 : Enable noise rejection (default) but in Low Crystal oscillator (LXT)
mode, the noise rejection circuit is always disabled.
Bit 9 (CYES): Instruction cycle selection bit
1 : One instruction cycle
0 : Two instruction cycles (default, for ICE only)
42 •
Product Specification (V1.6) 09.09.2013
(This specification is subject to change without further notice)
EM78F651N
8-Bit Microcontroller
Bits 8~7 (CLKS1 and CLKS0): Instruction period option bit
Instruction Period
CLKS1
CLKS0
4 clocks
0
0
2 clocks
0
1
8 clocks
1
0
16 clocks
1
1
Refer to the section on Instruction Set.
Bit 6 (ENWDTB): Watchdog timer enable bit
1 : Enable
0 : Disable
Bits 5~3 (OSC2 ~ OSC0): Oscillator Mode Selection bits
Oscillator Modes defined by OSC2 ~ OSC0
Mode
OSC2
OSC1
OSC0
XT (Crystal oscillator mode)
0
0
0
HXT (High Crystal oscillator mode)
0
0
1
LXT1 (Low Crystal 1 oscillator mode)
0
1
0
LXT2 (Low Crystal 2 oscillator mode)
0
1
1
IRC mode, OSCO (P54) act as I/O pin
1
0
0
IRC mode, OSCO (P54) act as RCOUT pin
1
0
1
ERC mode, OSCO (P54) act as I/O pin
1
1
0
ERC mode, OSCO (P54) act as RCOUT pin
1
1
1
Note: 1. Frequency range of HXT mode is 16 MHz ~ 6 MHz.
2. Frequency range of XT mode is 6 MHz ~ 1 MHz.
3. Frequency range of LXT1 mode is 1 MHz ~ 100kHz.
4. Frequency range of LXT2 mode is 32kHz.
Bits 2 ~ 0 (Protect):
Protect Bit
Protect are protect bits, protect type are as follows:
0 : Disable
1 : Enable
Product Specification (V1.6) 09.09.2013
(This specification is subject to change without further notice)
• 43
EM78F651N
8-Bit Microcontroller
6.10.2 Code Option Register (Word 1)
Word 1
Bit
Bit 12 Bit 11 Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Mnem
onic
–
TCEN
–
–
C4
C3
C2
C1
C0
1
–
TCC
–
–
High
High
High
High
High
High
High
High
High
0
–
P77
–
–
Low
Low
Low
Low
Low
Low
Low
Low
Low
Bit 12:
RCM1 RCM0 LVR1 LVR0
Not used, set to “1” at all time
Bit 11 (TCEN): TCC enable bit
0 : P77/TCC is set as P77
1 : P77/TCC is set as TCC
Bit 10:
Not used, set to “0” at all time.
Bit 9:
Not used, set to “1” at all time
Bits 8, 7, 6, 5 and Bit 4 (C4, C3, C2, C1, C0): Internal RC mode calibration bits.
Calibration Selection for Internal RC Mode
44 •
C4
C3
C2
C1
C0
*Cycle Time (ns)
*Frequency (MHz)
1
1
1
1
1
399
2.506
1
1
1
1
0
385
2.6
1
1
1
0
1
371
2.693
1
1
1
0
0
358
2.786
1
1
0
1
1
347
2.879
1
1
0
1
0
336
2.973
1
1
0
0
1
326
3.066
1
1
0
0
0
316
3.159
0
1
1
1
1
307
3.253
0
1
1
1
0
298
3.346
0
1
1
0
1
290
3.439
0
1
1
0
0
283
3.533
0
1
0
1
1
275
3.626
0
1
0
1
0
268
3.719
0
1
0
0
1
262
3.813
0
1
0
0
0
256
3.906
0
0
0
0
0
250
4.00
0
0
0
0
1
244
4.093
0
0
0
1
0
238
4.186
0
0
0
1
1
233
4.279
0
0
1
0
0
228
4.373
0
0
1
0
1
223
4.466
Product Specification (V1.6) 09.09.2013
(This specification is subject to change without further notice)
EM78F651N
8-Bit Microcontroller
C4
C3
C2
C1
C0
*Cycle Time (ns)
*Frequency (MHz)
0
0
1
1
0
219
4.559
0
0
1
1
1
214
4.653
1
0
0
0
0
210
4.746
1
0
0
0
1
206
4.839
1
0
0
1
0
202
4.933
1
0
0
1
1
198
5.026
1
0
1
0
0
195
5.119
1
0
1
0
1
191
5.213
1
0
1
1
0
188
5.306
1
0
1
1
1
185
5.4
Note: 1. These are theoretical values taken on an instance of a high frequency mode, and
which are shown here for reference only. Actual values may vary depending on the
process.
2. Similar way of calculation is also applicable for low frequency mode.
Bit 3 and Bit 2 (RCM1, RCM0): RC mode selection bits
RCM 1
RCM 0
*Frequency (MHz)
0
0
4
0
1
12
1
0
3.58
1
1
455kHz
Bits 1~0 (LVR1 ~ LVR0): Low Voltage Reset Enable bits
LVR1
LVR0
Reset Level
Release Level
0
0
NA
NA
0
1
2.6V
2.8V
1
0
3.3V
3.45V
1
1
3.8V
3.9V
LVR1, LVR0=“0, 0”
LVR disable, power- on reset point of EM78F651N is 2.0V.
LVR1, LVR0=“0, 1”
If Vdd < 2.6V, the EM78F651N will be reset.
LVR1, LVR0=“1, 0”
If Vdd < 3.3V, the EM78F651N will be reset.
LVR1, LVR0=“1, 1”
If Vdd < 3.8V, the EM78F651N will be reset.
6.10.3 Customer ID Register (Word 2)
Bit 12~Bit 0
XXXXXXXXXXXXX
Bits 12~0: Customer’s ID code
Product Specification (V1.6) 09.09.2013
(This specification is subject to change without further notice)
• 45
EM78F651N
8-Bit Microcontroller
6.11 Power-on Considerations
Any microcontroller is not guaranteed to start to operate properly before the power
supply has stabilized. The EM78F651N has an on-chip Power-on Voltage Detector
(POVD) with a detecting level of 2.0V. It will work well if Vdd can rise quickly enough
(50 ms or less). In many critical applications, however, extra devices are still required
to assist in solving power-up problems.
6.12 External Power-on Reset Circuit
The circuit shown in Figure 6-15 implements an external RC that produces a reset
pulse. The pulse width (time constant) should be kept long enough for Vdd to reach
minimum operation voltage. This circuit is used when the power supply has slow rise
time. Because the current leakage from the /RESET pin is ± 5 µA, it is recommended
that R should not be greater than 40K. In this way, the /RESET pin voltage is held
below 0.2V. The diode (D) acts as a short circuit at the moment of power down.
The capacitor C will discharge rapidly and fully. The current-limited resistor Rin, will
prevent high current or ESD (electrostatic discharge) from flowing to Pin /RESET.
Vdd
R
/RESET
D
Rin
C
Figure 6-15 External Power-up Reset Circuit
46 •
Product Specification (V1.6) 09.09.2013
(This specification is subject to change without further notice)
EM78F651N
8-Bit Microcontroller
6.13 Residue-Voltage Protection
When battery is replaced, device power (Vdd) is taken off but residue-voltage
remains. The residue-voltage may trip below Vdd minimum, but not to zero. This
condition may cause a poor power-on reset. Figure 6-16 and Figure 6-17 show how
to build a residue-voltage protection circuit.
Vdd
Vdd
33K
Q1
10K
/RESET
40K
1N4684
Figure 6-16 Residue Voltage Protection Circuit 1
Vdd
Vdd
R1
Q1
/RESET
40K
R2
Figure 6-17 Residue Voltage Protection Circuit 2
Product Specification (V1.6) 09.09.2013
(This specification is subject to change without further notice)
• 47
EM78F651N
8-Bit Microcontroller
6.14 Instruction Set
Each instruction in the instruction set is a 13-bit word divided into an OP code and
one or more operands. Normally, all instructions are executed within one single
instruction cycle (one instruction consists of two oscillator periods), unless the
program counter is changed by instruction "MOV R2,A", "ADD R2,A", or by
instructions of arithmetic or logic operation on R2 (e.g. "SUB R2,A", "BS(C) R2,6",
"CLR R2", etc.). In this case, the execution takes two instruction cycles.
If for some reasons, the specification of the instruction cycle is not suitable for certain
applications, try to modify the instruction as follows:
(A) Change one instruction cycle to consist of four oscillator periods.
(B) "JMP", "CALL", "RET", "RETL", "RETI", or the conditional skip ("JBS", "JBC", "JZ",
"JZA", "DJZ", "DJZA") commands which were tested to be true, are executed
within two instruction cycles. The instructions that are written to the program
counter also take two instruction cycles.
Case (A) is selected by the Code Option bit, called CLK. One instruction cycle
consists of two oscillator clocks if CLK is low, and four oscillator clocks if CLK is
high.
Note that once the four oscillator periods within one instruction cycle is selected
as in Case (A), the TCC internal clock source should be CLK=Fosc/4, instead of
Fosc/2 as indicated in Figure 6-3.
In addition, the instruction set has the following features:
(1) Every bit of any register can be set, cleared, or tested directly.
(2) The I/O register can be regarded as general register. That is, the same instruction
can operate on the I/O register.
Convention:
R = Register designator that specifies which one of the registers (including operation and
general purpose registers) is to be utilized by the instruction.
b = Bit field designator that selects the value for the bit located in the register R and which
affects the operation.
k = 8 or 10-bit constant or literal value
48 •
Product Specification (V1.6) 09.09.2013
(This specification is subject to change without further notice)
EM78F651N
8-Bit Microcontroller
Binary Instruction
Hex
Mnemonic
Operation
0 0000 0000 0000
0000
NOP
No Operation
0 0000 0000 0001
0001
DAA
Decimal Adjust A
0 0000 0000 0010
0002
CONTW
0 0000 0000 0011
0003
0 0000 0000 0100
Status Affected
None
C
A → CONT
None
SLEP
0 → WDT, Stop oscillator
T, P
0004
WDTC
0 → WDT
T, P
0 0000 0000 rrrr
000r
IOW R
A → IOCR
None 1
0 0000 0001 0000
0010
ENI
Enable Interrupt
None
0 0000 0001 0001
0011
DISI
Disable Interrupt
None
0 0000 0001 0010
0012
RET
[Top of Stack] → PC
None
0 0000 0001 0011
0013
RETI
[Top of Stack] → PC,
Enable Interrupt
None
0 0000 0001 0100
0014
CONTR
CONT → A
None
0 0000 0001 rrrr
001r
IOR R
IOCR → A
None 1
0 0000 01rr rrrr
00rr
MOV R,A
A→R
None
0 0000 1000 0000
0080
CLRA
0→A
Z
0 0000 11rr rrrr
00rr
CLR R
0→R
Z
0 0001 00rr rrrr
01rr
SUB A,R
R-A → A
Z, C, DC
0 0001 01rr rrrr
01rr
SUB R,A
R-A → R
Z, C, DC
0 0001 10rr rrrr
01rr
DECA R
R-1 → A
Z
0 0001 11rr rrrr
01rr
DEC R
R-1 → R
Z
0 0010 00rr rrrr
02rr
OR A,R
A∨R→A
Z
0 0010 01rr rrrr
02rr
OR R,A
A∨R→R
Z
0 0010 10rr rrrr
02rr
AND A,R
A&R→A
Z
0 0010 11rr rrrr
02rr
AND R,A
A&R→R
Z
0 0011 00rr rrrr
03rr
XOR A,R
A⊕R→A
Z
0 0011 01rr rrrr
03rr
XOR R,A
A⊕R→R
Z
0 0011 10rr rrrr
03rr
ADD A,R
A+R→A
Z, C, DC
0 0011 11rr rrrr
03rr
ADD R,A
A+R→R
Z, C, DC
0 0100 00rr rrrr
04rr
MOV A,R
R→A
Z
0 0100 01rr rrrr
04rr
MOV R,R
R→R
Z
0 0100 10rr rrrr
04rr
COMA R
/R → A
Z
0 0100 11rr rrrr
04rr
COM R
/R → R
Z
0 0101 00rr rrrr
05rr
INCA R
R+1 → A
Z
0 0101 01rr rrrr
05rr
INC R
R+1 → R
Z
0 0101 10rr rrrr
05rr
DJZA R
R-1 → A, skip if zero
None
0 0101 11rr rrrr
05rr
DJZ R
R-1 → R, skip if zero
None
Product Specification (V1.6) 09.09.2013
(This specification is subject to change without further notice)
• 49
EM78F651N
8-Bit Microcontroller
Binary Instruction
Hex
Mnemonic
Operation
Status Affected
0 0110 00rr rrrr
06rr
RRCA R
R(n) → A(n-1),
R(0) → C, C → A(7)
C
0 0110 01rr rrrr
06rr
RRC R
R(n) → R(n-1),
R(0) → C, C → R(7)
C
0 0110 10rr rrrr
06rr
RLCA R
R(n) → A(n+1),
R(7) → C, C → A(0)
C
0 0110 11rr rrrr
06rr
RLC R
R(n) → R(n+1),
R(7) → C, C → R(0)
C
0 0111 00rr rrrr
07rr
SWAPA R
R(0-3) → A(4-7),
R(4-7) → A(0-3)
None
0 0111 01rr rrrr
07rr
SWAP R
R(0-3) ↔ R(4-7)
None
0 0111 10rr rrrr
07rr
JZA R
R+1 → A, skip if zero
None
0 0111 11rr rrrr
07rr
JZ R
R+1 → R, skip if zero
None
0 100b bbrr rrrr
0xxx
BC R,b
0 → R(b)
None 2
0 101b bbrr rrrr
0xxx
BS R,b
1 → R(b)
None 3
0 110b bbrr rrrr
0xxx
JBC R,b
if R(b)=0, skip
None
0 111b bbrr rrrr
0xxx
JBS R,b
if R(b)=1, skip
None
1 00kk kkkk kkkk
1kkk
CALL k
PC+1 → [SP],
(Page, k) → PC
None
1 01kk kkkk kkkk
1kkk
JMP k
(Page, k) → PC
None
1 1000 kkkk kkkk
18kk
MOV A,k
k→A
None
1 1001 kkkk kkkk
19kk
OR A,k
A∨k→A
Z
1 1010 kkkk kkkk
1Akk
AND A,k
A&k→A
Z
1 1011 kkkk kkkk
1Bkk
XOR A,k
A⊕k→A
Z
1 1100 kkkk kkkk
1Ckk
RETL k
k → A,
[Top of Stack] → PC
1 1101 kkkk kkkk
1Dkk
SUB A,k
k-A → A
Z, C, DC
1 1111 kkkk kkkk
1Fkk
ADD A,k
k+A → A
Z, C, DC
1 1110 1001 000k
1E9k
BANK k
K->R3(6)
None
None
Note: 1 This instruction is applicable to IOC5~IOC6, IOCB ~ IOCF only.
50 •
2
This instruction is not recommended for RF operation.
3
This instruction cannot operate under RF.
Product Specification (V1.6) 09.09.2013
(This specification is subject to change without further notice)
EM78F651N
8-Bit Microcontroller
7
Timing Diagrams
AC Test Input/Output Waveform
Note: AC Testing: Input is driven at 0.9Vdd for Logic "1", and 0.1Vdd for Logic “0”
Timing measurements are made at 0.75Vdd for Logic “1”, and 0.25Vdd for Logic “0”
Figure 7-1 AC Test Timing Diagram
Reset Timing (CLK="0")
Figure 7-2 Reset Timing Diagram
TCC Input Timing (CLKS="0")
Figure 7-3 TCC Input Timing Diagram
Product Specification (V1.6) 09.09.2013
(This specification is subject to change without further notice)
• 51
EM78F651N
8-Bit Microcontroller
8
Absolute Maximum Ratings
Items
Rating
Temperature under bias
-40°C
to
85°C
Storage temperature
-65°C
to
150°C
Working voltage
2.2
to
5.5V
Working frequency
DC
to
16 MHz*
Input voltage
Vss-0.3V
to
Vdd+0.5V
Output voltage
Vss-0.3V
to
Vdd+0.5V
*Note: These parameters are theoretical values and have not been tested.
9
DC Electrical Characteristics
Ta=25°C, VDD=5.0V±5%, VSS=0V
Symbol
Parameter
Crystal: VDD to 3V
Fxt
IIL
52 •
Crystal: VDD to 5V
Condition
Two cycles with two clocks
Min.
Typ.
Max.
Unit
DC
−
8
MHz
DC
−
16
MHz
F±30%
kHz
F
F±30%
Hz
−
−
±1
µA
ERC: VDD to 5V
R: 5.1KΩ, C: 100 pF
F±30% 830
IRC: VDD to 5V
4 MHz, 1 MHz, 455kHz, 8 MHz F±30%
Input Leakage Current
for input pins
VIN = VDD, VSS
VIHRC
Input High Threshold Voltage
OSCI in RC mode
(Schmitt Trigger)
−
3.5
−
V
IERC1
Sink current
VI from low to high, VI=5V
21
22
23
mA
VILRC
Input Low Threshold Voltage
(Schmitt Trigger)
OSCI in RC mode
−
1.5
−
V
IERC2
Sink current
VI from high to low, VI=2V
16
17
18
mA
VIH1
Input High Voltage
Ports 5, 6
0.4Vdd
−
Vdd+0.3V
V
VIL1
Input Low Voltage
Ports 5, 6
-0.3V
−
0.4Vdd
V
VIH2
Input High Voltage
(Schmitt Trigger)
Port 7
0.75Vdd
−
Vdd+0.3V
V
VIL2
Input Low Voltage
(Schmitt Trigger)
Port 7
-0.3V
−
0.25Vdd
V
VIHT1
Input High Threshold Voltage
/RESET
(Schmitt Trigger)
0.75Vdd
−
Vdd+0.3V
V
VILT1
Input Low Threshold Voltage
(Schmitt Trigger)
-0.3V
−
0.25Vdd
V
VIHT2
Input High Threshold Voltage INT
0.4Vdd
−
Vdd+0.3V
V
VILT2
Input Low Threshold Voltage
-0.3V
−
0.4Vdd
V
VIHT3
Input High Threshold Voltage
TCC
(Schmitt Trigger)
0.75Vdd
−
Vdd+0.3V
V
VILT3
Input Low Threshold Voltage
(Schmitt Trigger)
TCC
-0.3V
−
0.25Vdd
V
VIHX1
Clock Input High Voltage
OSCI in crystal mode
−
3.0
−
V
/RESET
INT
Product Specification (V1.6) 09.09.2013
(This specification is subject to change without further notice)
EM78F651N
8-Bit Microcontroller
Symbol
Parameter
Condition
Min. Typ.
Max.
Unit
VILX1
Clock Input Low Voltage
OSCI in crystal mode
−
1.8
−
V
IOH1
Output High Voltage
(Ports 5, 6)
VOH = VDD-0.5V
(IOH =3.7mA)
−
-3.5
−
mA
IOL1
Output Low Voltage
(Ports 5, 7)
VOL = GND+0.5V
−
10
−
mA
IOL2
Output Low Voltage
(Port 6)
VOL = GND+0.5V
−
18
−
mA
IPH
Pull-high current
Pull-high active,
Input pin at VSS
-50
-75
-240
µA
IPL
Pull-low current
Pull-low active,
Input pin at Vdd
25
40
120
µA
ISB1
Power down current
All input and I/O pins at VDD,
Output pin floating,
WDT disabled
−
−
2.0
µA
ISB2
Power down current
All input and I/O pins at VDD,
Output pin floating,
WDT enabled
−
−
8
µA
ICC1
Operating supply current
at two clocks
/RESET= 'High', Fosc=32kHz
(Crystal type, CLKS="0"),
Output pin floating,
WDT disabled, HLP=1
−
−
35
µA
ICC2
Operating supply current
at two clocks
/RESET= 'High', Fosc=32kHz
(Crystal type, CLKS="0"),
Output pin floating,
WDT enabled, HLP=1
−
−
39
µA
ICC3
Operating supply current
at two clocks
/RESET= 'High', Fosc=455kHz
(Crystal type, CLKS="0"),
Output pin floating,
WDT enabled, HLP=0
−
−
270
µA
ICC4
Operating supply current
at two clocks
/RESET= 'High', Fosc=455kHz
(IRC type, CLKS="0"),
Output pin floating,
WDT enabled, HLP=0
−
−
640
µA
ICC5
Operating supply current
at two clocks
/RESET= 'High', Fosc=4 MHz
(Crystal type, CLKS="0"),
Output pin floating,
WDT enabled
−
−
1.5
mA
ICC6
Operating supply current
at two clocks
/RESET= 'High', Fosc=10 MHz
(Crystal type, CLKS="0"),
Output pin floating,
WDT enabled
−
−
3
mA
Note: These parameters are theoretical values and have not been tested.
*Data in the Minimum, Typical, Maximum (“Min.”, “Typ.”, ”Max.”) columns are based on
characterization results at 25°C. The data have not been tested and are for design reference only.
Product Specification (V1.6) 09.09.2013
(This specification is subject to change without further notice)
• 53
EM78F651N
8-Bit Microcontroller
Internal RC Electrical Characteristics (Ta=25°C, VDD=5 V, VSS=0V)
Internal RC
Drift Rate
Temperature
Voltage
Min.
Typ.
Max.
4 MHz
25°C
5V
3.88 MHz
4 MHz
4.12 MHz
12 MHz
25°C
5V
11.52 MHz
12 MHz
12.48 MHz
3.58 MHz
25°C
5V
3.43 MHz
3.58 MHz
3.72 MHz
455kHz
25°C
5V
436.8kHz
455kHz
473.2kHz
Internal RC Electrical Characteristics (Ta=-40 ~85°C, VDD=2.2~5.5 V, VSS=0V)
Drift Rate
Internal RC
Temperature
Voltage
Min.
Typ.
Max.
4 MHz
-40°C ~85°C
2.2V~5.5V
3.55 MHz
4 MHz
4.45 MHz
12 MHz
-40°C ~85°C
2.2V~5.5V
10.5 MHz
12 MHz
13.5 MHz
3.58 MHz
-40°C ~85°C
2.2V~5.5V
3.15 MHz
3.58 MHz
4 MHz
455kHz
-40°C ~85°C
2.2V~5.5V
400kHz
455kHz
510kHz
LVD (Low Voltage Detector) Electrical Characteristics
Symbol
Parameter
Condition
Min.*
Typ. Max.**
Unit
LVD1
LVD1 Voltage interrupt level
(Schmitt Trigger)
Vdd=5V
2.3+0.1
−
2.4+0.1
V
LVD2
LVD2 Voltage interrupt level
(Schmitt Trigger)
Vdd=5V
3.3+0.1
−
3.4+0.1
V
LVD3
LVD3 Voltage interrupt level
(Schmitt Trigger)
Vdd=5V
4.0+0.1
−
4.1+0.1
V
LVD4
LVD4 Voltage interrupt level
(Schmitt Trigger)
Vdd=5V
4.5+0.1
−
4.6+0.1
V
Note: * VDD Voltage from High to Low.
** VDD Voltage from Low to High.
54 •
Product Specification (V1.6) 09.09.2013
(This specification is subject to change without further notice)
EM78F651N
8-Bit Microcontroller
LVR (Low Voltage Reset) Electrical Characteristics
Symbol
Parameter
Condition
Min.*
Typ.
Max.**
Unit
LVR1
LVR1 Voltage reset level
(Schmitt trigger)
Vdd=5V
−
−
−
V
LVR2
LVR2 Voltage reset level
(Schmitt trigger)
Vdd=5V
2.6+0.15
−
2.8+0.15
V
LVR3
LVR3 Voltage reset level
(Schmitt trigger)
Vdd=5V
3.3+0.15
−
3.45+0.15
V
LVR4
LVR4 Voltage reset level
(Schmitt trigger)
Vdd=5V
3.8+0.15
−
3.9+0.15
V
Note:
* VDD Voltage from High to Low
** VDD Voltage from Low to High
Data EEPROM Electrical Characteristics
Symbol
Tprog
Parameter
Condition
Erase/Write cycle time
Treten
Data Retention
Tendu
Endurance time
Vdd = 2.2~ 5.5V
Temperature = -40°C ~ 85°C
Min. Typ. Max.
−
Unit
6
−
ms
−
10
−
Years
−
100K
−
Cycles
Program Flash memory Electrical Characteristics
Symbol
Parameter
Tprog
Erase/Write cycle time
Treten
Tendu
Data Retention
Endurance time
Product Specification (V1.6) 09.09.2013
(This specification is subject to change without further notice)
Condition
Min. Typ. Max.
−
Vdd = 5.0V
Temperature = -40°C ~ 85°C
−
−
Unit
4
−
ms
10
−
Years
100K
−
Cycles
• 55
EM78F651N
8-Bit Microcontroller
10 AC Electrical Characteristics
EM78F651N, 0 ≤ Ta ≤ 70°C, VDD=5V, VSS=0V
-40 ≤ Ta ≤ 85°C, VDD=5V, VSS=0V
Symbol
Dclk
Tins
Parameter
Conditions
Min.
Typ.
Max.
Unit
Input CLK duty cycle
−
45
50
55
%
Instruction cycle time
Crystal type
100
−
DC
ns
RC type
500
−
DC
ns
(CLKS="0")
Ttcc
TCC input period
−
(Tins+20)/N*
−
−
ns
Tdrh
Device reset hold time
−
11.8
16.8
21.8
ms
Trst
/RESET pulse width
Ta = 25°C
2000
−
−
ns
Twdt
Watchdog timer period
Ta = 25°C
11.8
16.8
21.8
ms
Tset
Input pin setup time
−
−
0
−
ns
Thold
Input pin hold time
−
−
20
−
ns
Tdelay
Output pin delay time
Cload=20pF
−
50
−
ns
Note: These parameters are theoretical values and have not been tested.
*Data in the Minimum, Typical, Maximum ("Min.", "Typ.", "Max.") columns are based on
characterization results at 25°C. The data have not been tested and are for design
reference only.
*N = selected prescaler ratio
56 •
Product Specification (V1.6) 09.09.2013
(This specification is subject to change without further notice)
EM78F651N
8-Bit Microcontroller
APPENDIX
A Package Type
Flash MCU
Package Type
Pin Count
Package Size
EM78F651ND14J/S
DIP
14
300 mil
EM78F651NSO14J/S
SOP
14
150 mil
EM78F651ND16J/S
DIP
16
300 mil
EM78F651NSO16J/S
SOP
16
150 mil
EM78F651ND18J/S
DIP
18
300 mil
EM78F651NSO18J/S
SOP
18
300 mil
EM78F651NSS20J/S
SSOP
20
209 mil
EM78F651NSO20J/S
SOP
20
300 mil
EM78F651ND20J/S
DIP
20
300 mil
SSOP
10
150 mil
EM78F651NSS10J/S
These are Green products which do not contain hazardous substances and comply
with the third edition of Sony SS-00259 standard.
Pb content is less than 100ppm and complies with Sony specifications.
Part No.
EM78F651NS/J
Electroplate type
Pure Tin
Ingredient (%)
Sn: 100%
Melting point (°C)
232°C
Electrical resistivity
(µΩ cm)
11.4
Hardness (hv)
8~10
Elongation (%)
>50%
Product Specification (V1.6) 09.09.2013
(This specification is subject to change without further notice)
• 57
EM78F651N
8-Bit Microcontroller
B Package Information
B.1
EM78F651NSS10
Figure B-1 EM78F651N 10-pin SSOP Package Type
58 •
Product Specification (V1.6) 09.09.2013
(This specification is subject to change without further notice)
EM78F651N
8-Bit Microcontroller
B.2 EM78F651ND14
θ
Min
Normal
Max
0.203
0.254
0.356
0.356
1.143
0.457 0.559
1.524 1.778
3.302 3.556
2.540(TYP)
Figure B-2 EM78F651N 14-pin DIP Package Type
Product Specification (V1.6) 09.09.2013
(This specification is subject to change without further notice)
• 59
EM78F651N
8-Bit Microcontroller
B.3 EM78F651NSO14
E
Symbol
A
A1
b
c
E
H
D
L
e
H
Min
Normal
Max
1.27(TYP)
e
b
c
D
A2
A
Edtion: A
Unit : mm
Scale: Free
Material:
Sheet:1 of 1
Figure B-3 EM78F651N 14-pin SOP Package Type
60 •
Product Specification (V1.6) 09.09.2013
(This specification is subject to change without further notice)
EM78F651N
8-Bit Microcontroller
B.4 EM78F651ND16
Figure B-4 EM78F651N 16-pin DIP Package Type
Product Specification (V1.6) 09.09.2013
(This specification is subject to change without further notice)
• 61
EM78F651N
8-Bit Microcontroller
B.5 EM78F651NSO16
Figure B-5 EM78F651N 16-pin SOP Package Type
62 •
Product Specification (V1.6) 09.09.2013
(This specification is subject to change without further notice)
EM78F651N
8-Bit Microcontroller
B.6 EM78F651ND18
eB
Symbol Min Normal Max
A
A1
A2
0.203 0.254 0.356
c
D
E1
E
eB
0.356 0.457 0.559
B
B1 1.143 1.524 1.778
3.302 3.556
L
2.540(TYP)
e
Edtion: A
Unit : mm
Scale: Free
Material:
Sheet:1 of 1
Figure B-6 EM78F651N 18-pin DIP Package Type
Product Specification (V1.6) 09.09.2013
(This specification is subject to change without further notice)
• 63
EM78F651N
8-Bit Microcontroller
B.7 EM78F651NSO18
Symbol
A
A1
b
c
E
H
D
L
e
b
Min
Normal
Max
0.406(TYP)
1.27(TYP)
e
c
Edtion: A
Unit : mm
Scale: Free
Material:
Sheet:1 of 1
Figure B-7 EM78F651N 18-pin SOP Package Type
64 •
Product Specification (V1.6) 09.09.2013
(This specification is subject to change without further notice)
EM78F651N
8-Bit Microcontroller
B.8 EM78F651ND20
E
Symbol Min Normal Max
A
A1
A2
c
0.203 0.254 0.356
D
E1
E
eB
B
0.356 0.457 0.559
B1
1.143 1.524 1.778
L
3.302 3.556
e
2.540(TYP)
TITLE:
PDIP-20L 300MIL PACKAGE
OUTLINE DIMENSION
File :
D20
Edtion: A
Unit : mm
Scale: Free
Material:
Sheet:1 of 1
Figure B-8 EM78F651N 20-pin DIP Package Type
Product Specification (V1.6) 09.09.2013
(This specification is subject to change without further notice)
• 65
EM78F651N
8-Bit Microcontroller
B.9 EM78F651NS020
Symbol
A
A1
b
c
E
H
D
L
e
b
Min
Normal
Max
0.406(TYP)
1.27(TYP)
e
c
TITLE:
SOP-20L(300MIL) PACKAGE
OUTLINE DIMENSION
File :
Edtion: A
SO20
Unit : mm
Scale: Free
Material:
Sheet:1 of 1
Figure B-9 EM78F651N 20-pin SOP Package Type
66 •
Product Specification (V1.6) 09.09.2013
(This specification is subject to change without further notice)
EM78F651N
8-Bit Microcontroller
b
Symbol Min
Normal
Max
A
A1
A2
b
0.090
c
E
E1
D
L
1.250(REF )
L1
0.650(TYP)
e
E
E1
B.10 EM78F651NSS20
e
A2
c
L1
Edtion: A
Unit : mm
Scale: Free
Material:
Sheet:1 of 1
Figure B-10 EM78F651N 20-pin SSOP Package Type
Product Specification (V1.6) 09.09.2013
(This specification is subject to change without further notice)
• 67
EM78F651N
8-Bit Microcontroller
P67
P65
P66
P64
P63
6
8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60
1
3
5
7
P55/OSCI
P62
P53
4
P50
P61
P52
2
P51
GND
P60/INT
P56
/RESET
P77/TCC
C ICE 652N Output Pin Assignment (JP 3)
P77
VCC
9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59
P54/OSCO
P57
JP 3
D EM78F651N Program Pin
In the following IC diagram, “Pin # number” means the Pin to be connected to the Socket
in FWTR.
EM78F651ND 20
FWTR Socket
1
P56
1
20
P57
P52
2
19
P51
P53
3
18
P50
P77/TCC
4
17
P55/OSCI
#15
/RESET
5
16
P54/OSCO
#16
VSS
6
15
VDD
#25
P60/INT
7
14
P67
#28
8
13
P66
#29
P62
9
12
P65
P63
10
11
P64
P61
68 •
40
#26
#15
#16
29
28
#29
#28
15
16
25
#26
#25
20
21
Product Specification (V1.6) 09.09.2013
(This specification is subject to change without further notice)
EM78F651N
8-Bit Microcontroller
E
Quality Assurance and Reliability
Test Category
Test Conditions
Solder temperature=245±5°C, for 5 seconds up to the
stopper using a rosin-type flux
Solderability
Remarks
–
Step 1: TCT, 65°C (15mins)~150°C (15 min), 10 cycles
Step 2: Bake at 125°C, TD (endurance)=24 hrs
Step 3: Soak at 30°C/60% TD (endurance)=192 hrs
Pre-condition
Step 4: IR flow 3 cycles
(Pkg thickness ≥ 2.5mm or
3
Pkg volume ≥ 350mm ----225±5°C)
For SMD IC (such as
SOP, QFP, SOJ, etc)
(Pkg thickness ≤ 2.5mm or
3
Pkg volume ≤ 350mm ----240±5°C)
Temperature cycle test
-65°C (15mins)~150°C (15mins), 200 cycles
–
Pressure cooker test
TA =121°C, RH=100%, pressure=2 atm,
TD (endurance)= 96 hrs
–
High temperature /
High humidity test
TA=85°C , RH=85% TD (endurance) = 168 , 500 hrs
–
High-temperature
storage life
TA=150°C, TD (endurance) = 500, 1000 hrs
–
High-temperature
operating life
TA=125°C, VCC = Max. operating voltage,
TD (endurance) = 168, 500, 1000 hrs
–
Latch-up
TA=25°C, VCC = Max. operating voltage, 150mA/20V
–
ESD (HBM)
TA=25°C, ≥ ± 3KV
IP_ND,OP_ND,IO_ND
IP_NS,OP_NS,IO_NS
IP_PD,OP_PD,IO_PD,
ESD (MM)
TA=25°C, ≥
IP_PS,OP_PS,IO_PS,
± 300V
VDD-VSS(+),VDD_VSS
(-) mode
E.1 Address Trap Detect
An address trap detect is one of the MCU embedded fail-safe functions that detects
MCU malfunction caused by noise or the like. Whenever the MCU attempts to fetch
an instruction from a certain section of ROM, an internal recovery circuit is auto
started. If a noise-caused address error is detected, the MCU will repeat execution of
the program until the noise is eliminated. The MCU will then continue to execute the
next program.
Product Specification (V1.6) 09.09.2013
(This specification is subject to change without further notice)
• 69
EM78F651N
8-Bit Microcontroller
F
Comparison between R-Package and U-Package
This series of microcontrollers comprise of the R-package version and the U-package
version. In the U-package version, P5 and P6 VIH/L of the same level voltages have
been modified to favorably meet users’ requirements. The following table is provided
for quick comparison between the two package versions and for user convenience in
the choice of the most suitable product for their application.
Item
P5, P6 VIH/L
EM78F651N-R
EM78F651N
0810R
EM78F651N-R Package Version
70 •
EM78F651N-U
VIH : 0.75Vdd – Vdd+0.3V
VIL : -0.3V – 0.25Vdd
VIH : 0.4Vdd – Vdd+0.3V
VIL : -0.3V – 0.4Vdd
EM78F651N
0810U
EM78F651N-U Package Version
Product Specification (V1.6) 09.09.2013
(This specification is subject to change without further notice)