PI3VDP612-A 4-Lane DisplayPort™ Rev 1.1a Compliant Switch with Triple Control Logic for Fast Switching Features Description ÎÎ4-lane, 1:2 mux/demux that will support 2.7Gbps or Pericom Semiconductor’s PI3VDP612-A mux/demux is targeted for next generation digital video signals. This device can be used to connect a DisplayPort™ Source to two Independent DisplayPort Sinks or to connect two DisplayPort sources to a single DP display. 1.62Gbps DP rev 1.1a signals ÎÎ1-channel 1:2 mux/demux for DP_HPD signal ÎÎ1-differential channel 1:2 mux/demux for DP_Aux signal ÎÎInsertion Loss for high speed channels @ 2.7 Gbps: -1.5dB The newly released DisplayPort spec requires a data rate of 2.7 Gbps with AC coupled I/Os. Pericom's solution has been specifically designed around this standard and will support such signals. ÎÎ-3dB Bandwidth for high speed channels of 3.25 Ghz ÎÎLow Bit-to-Bit Skew , 7ps max (between '+' and '-' bits) ÎÎLow Crosstalk for high speed channels: [email protected] Gbps ÎÎLow Off Isolation for high speed channels: [email protected] Gbps ÎÎVDD Operating Range: 3.3V ±10% Application ÎÎESD Tolerance: +/-8kV contact on Ports A and B per Routing of DisplayPort signals with low signal attenuation between source and sink. IEC61000-4-2 Specification ÎÎLow channel-to-channel skew, 35ps max ÎÎPackaging (Pb-free & Green): àà -56 TQFN (ZFE) àà -42 TQFN (ZHE) 11-0103 1 GND VDD D0+ A D0- A D1+A D1-A VDD GND 55 54 53 52 51 50 49 42 8 41 9 40 GND 10 39 34 16 33 17 32 18 31 19 30 20 29 28 35 15 GND 36 14 27 37 13 V DD 38 26 11 12 AUX+B AUX_SEL Logic Control 43 7 25 SEL2 SEL1 44 6 AUX-B AUX+ B AUX- B HPD B CAB_DETB/LEDB 45 5 24 AUX+ A AUX- A HPD A CAB_DETA/LEDA 46 4 HPD_B AUX+ AUXHPD CAB_DET/LED 3 23 D2+B D2-B D3+B D3-B 47 CAB_DET/LEDB D0+B D0-B D1+B D1-B 48 2 22 D2+A D2-A D3+A D3-A 1 21 D2+ D2D3+ D3- AUX_SEL D0+ D0D1+ D1VDD D2+ D2D3+ D3GND AUX+ AUXHPD CAB_DET/LED GND VDD SEL1 SEL2 GND VDD D0+A D0-A D1+A D1-A GND D0+ D0 D1+ D1 - 56 Pin Description - 56-Pin Block Diagram GND D2+A D2-A D3+A D3-A D0+B D0-B D1+B D1-B D2+B D2-B D3+B D3-B GND VDD AUX+A AUX-A HPD_A CAB_DET/LEDA GND PS9056A 07/12/11 PI3VDP612-A 4-Lane DisplayPort™ Rev 1.1a Compliant Switch with Triple Control Logic for Fast Switching 11-0103 39 D1- A VDD 40 41 D0-A D1+ A 1 38 2 37 3 36 4 35 5 34 6 33 7 32 GND 8 31 28 12 27 13 26 14 25 15 24 16 23 17 22 D3+A D3-A D0+B D0-B D1+B D1-B D2+B D2-B D3+B D3-B VDD AUX+A AUX-A HPD_ A CAB_DETA/LED_A AUX+B AUX-B 2 D2+A D2-A 21 11 20 29 19 10 HPD_B 30 18 9 CAB_DETB/LED_B D0+A AUX_SEL D0+ D0D1+ D1D2+ D2D3+ D3AUX+ AUXHPD CAB_DET/LED VDD SEL1 SEL2 42 Pin Description - 42-Pin PS9056A 07/12/11 PI3VDP612-A 4-Lane DisplayPort™ Rev 1.1a Compliant Switch with Triple Control Logic for Fast Switching Pin Description 42-Package 56-Package Pin # Pin # Pin Name Signal Type Description ESD Logic control for AUX signals: 2 1 AUX_SEL Input if LOW then AUX from COM port will connect to AUX from port A. If HIGH, then AUX from COM port will connect to AUX from port B. 3 2 D0+ I/O Positive Lane0 signal for common port +/-7kV 4 3 D0- I/O Negative Lane0 signal for common port +/-7kV 5 4 D1+ I/O Positive Lane1 signal for common port +/-7kV 6 5 D1- I/O Negative Lane1 signal for common port +/-7kV 15, 26, 39 6, 17, 22, 27, 34, 50, 55 VDD Power 3.3V Power Supply 7 7 D2+ I/O Positive Lane2 signal for common port +/-7kV 8 8 D2- I/O Negative Lane2 signal for common port +/-7kV 9 9 D3+ I/O Positive Lane3 signal for common port +/-7kV 10 10 D3- I/O Negative Lane3 signal for common port +/-7kV *GND plate 11, 16, 20, 21, 28, 29, 35, GND 48, 49, 56 Ground Ground 11 12 AUX+ I/O Positive AUX signal for common port +/-8kV 12 13 AUX- I/O Negative AUX signal for common port +/-8kV 13 14 HPD I/O HPD for common port +/-8kV 14 15 CAB_DET/LED I/O Common port pin for cable detect signal or LED common port +/-8kV 16 18 SEL1 Input Port Selection Control. If LOW, then port A is active. If HIGH, then port B is active 17 19 SEL2 Input Port Selection Control for HPD path and CAB_ DET/LED path only: If LOW, then port A is active. If HIGH, then port B is active. 20 GND Power Ground 21 GND Power Ground 22 V DD Power 3.3V Power Supply 18 23 CAB_DETB/ LEDB I/O Port B pin13 from dual mode DP connector or LED from port B +/-8kV 19 24 HPD_B I/O HPD for port B +/-8kV 20 25 AUX-B I/O Negative AUX signal for Port B +/-8kV 21 26 AUX+B I/O Positive AUX signal for Port B +/-8kV (Continued) 11-0103 3 PS9056A 07/12/11 PI3VDP612-A 4-Lane DisplayPort™ Rev 1.1a Compliant Switch with Triple Control Logic for Fast Switching Pin Description 42-Package 56-Package Pin # Pin # Pin Name Signal Type Description ESD 22 30 CAB_DETA/ LEDA I/O Port A cable detect from dual mode DP connector or LED from port A +/-8kV 23 31 HPD_A I/O HPD for port A +/-8kV 24 32 AUX-A I/O Negative AUX signal for Port A +/-8kV 25 33 AUX+A I/O Positive AUX signal for Port A +/-8kV 27 36 D3-B I/O Negative Lane3 signal for Port B +/-8kV 28 37 D3+B I/O Positive Lane3 signal for Port B +/-8kV 29 38 D2-B I/O Negative Lane2 signal for Port B +/-8kV 30 39 D2+B I/O Positive Lane2 signal for Port B +/-8kV 31 40 D1-B I/O Negative Lane1 signal for Port B +/-8kV 32 41 D1+B I/O Positive Lane1 signal for Port B +/-8kV 33 42 D0-B I/O Negative Lane0 signal for Port B +/-8kV 34 43 D0+B I/O Positive Lane0 signal for Port B +/-8kV 35 44 D3-A I/O Negative Lane3 signal for Port A +/-8kV 36 45 D3+A I/O Positive Lane3 signal for Port A +/-8kV 37 46 D2-A I/O Negative Lane2 signal for Port A +/-8kV 38 47 D2+A I/O Positive Lane2 signal for Port A +/-8kV 40 51 D1-A I/O Negative Lane1 signal for Port A +/-8kV 41 52 D1+A I/O Positive Lane1 signal for Port A +/-8kV 42 53 D0-A I/O Negative Lane0 signal for Port A +/-8kV 1 54 D0+A I/O Positive Lane0 signal for Port A +/-8kV Truth Table (SEL control) Function SEL 1/SEL2/AUX_SEL Port A is active L Port B is active H Notes: SEL1 is only for DP lanes SEL2 is only for HPD/CAB_DET signals AUX_SEL is only for AUX path 11-0103 4 PS9056A 07/12/11 PI3VDP612-A 4-Lane DisplayPort™ Rev 1.1a Compliant Switch with Triple Control Logic for Fast Switching Maximum Ratings (Above which useful life may be impaired. For user guidelines, not tested.) Storage Temperature .....................................................–65°C to +150°C Supply Voltage to Ground Potential ................................–0.5V to +3.6V DC Input Voltage ............................................................... –0.7V to 3.6V DC Output Current ....................................................................... 120mA Power Dissipation ............................................................................ 0.5W Note: Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. DC Electrical Characteristics for Switching over Operating Range (TA = –40°C to +85°C, VDD = 3.3V ±10%) Parameter Description Test Conditions(1) Min Typ(1) VIH Input HIGH Voltage Guaranteed HIGH level 1.6 VIL Input LOW Voltage Guaranteed LOW level VIK Clamp Diode Voltage VDD = Max., IIN = –18mA IIH Input HIGH Current VDD = Max., VIN = VDD ±5 IIL Input LOW Current VDD = Max., VIN = GND ±5 IOFF I/O leakage when part is off VDD = 0V, VINPUT = 0V to 3.6V 50 RON On resistance between input to output VDD = 3.0V, -0.6V<VINPUT<0.6V 7 Ohm VDD = 3.0V, 1.0V<VINPUT<1.5V 10 Ohm Max Units 70 µA –0.7 Max Units 0.75 V –1.2 µA Power Supply Characteristics (TA = 0°C to +70°C) Parameter Description Test Conditions(1) ICC Quiescent Power Supply Current VDD = Max., VIN = GND or VDD Min Typ(1) Dynamic Electrical Characteristics over Operating Range (TA = -40º to +85ºC, VDD = 3.3V ±10%, GND=0V) Parameter Description Test Conditions XTALK Crosstalk on High Speed Channels See Fig. 1 for Measurement Setup Typ.(2) f= 1.35 GHz -33dB f = 100 MHz -48dB f= 1.35 GHz -33dB f = 100 MHz -56dB Units dB OIRR OFF Isolation on High Speed Channels See Fig. 2 for Measurement Setup, ILOSS Differential Insertion Loss on High Speed Channels @2.7Gbps (see figure 3) -1.5 dB BW_Dx± Bandwidth -3dB for Main high speed path (Dx±) See figure 3 3.25 GHz BW_AUX/HPD -3dB BW for AUX and HPD signals See figure 3 1.5 GHz Notes: 1. For Max. or Min. conditions, use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at V DD = 3.3V, Ta = 25°C ambient and maximum loading. 11-0103 5 PS9056A 07/12/11 PI3VDP612-A 4-Lane DisplayPort™ Rev 1.1a Compliant Switch with Triple Control Logic for Fast Switching BALANCED PORT1 BALANCED PORT2 + + 50 – – 50 + + 50 – – 50 DUT Fig 1. Crosstalk Setup BALANCED PORT1 + + 50 – – 50 + BALANCED PORT2 – DUT Fig 2. Off-isolation setup BALANCED PORT1 + + – – BALANCED PORT2 DUT Fig 3. Differential Insertion Loss 11-0103 6 PS9056A 07/12/11 PI3VDP612-A 4-Lane DisplayPort™ Rev 1.1a Compliant Switch with Triple Control Logic for Fast Switching Fig 4. Crosstalk Fig 4. Xtalk 11-0103 7 PS9056A 07/12/11 PI3VDP612-A 4-Lane DisplayPort™ Rev 1.1a Compliant Switch with Triple Control Logic for Fast Switching Fig 5. Off Isolation 11-0103 8 PS9056A 07/12/11 PI3VDP612-A 4-Lane DisplayPort™ Rev 1.1a Compliant Switch with Triple Control Logic for Fast Switching Fig 6. Insertion Loss 11-0103 9 PS9056A 07/12/11 PI3VDP612-A 4-Lane DisplayPort™ Rev 1.1a Compliant Switch with Triple Control Logic for Fast Switching (OHMS) 20.0 RON 2.00/div 0.00 0.00 VIN (V) 200.m /div 3.00 Fig 7. Ron Curve for High Speed Signal Path Only (Dx±) 11-0103 10 PS9056A 07/12/11 PI3VDP612-A 4-Lane DisplayPort™ Rev 1.1a Compliant Switch with Triple Control Logic for Fast Switching Switching Characteristics (TA= -40º to +85ºC, VDD = 3.3V±10%) Parameter Description Min. Max. Units tPZH, tPZL Line Enable Time 0.5 15.0 tPHZ , tPLZ Line Disable Time 0.5 15.0 Tpd Propagation delay (input pin to output pin) 200 ps tb-b Bit-to-bit skew within the same differential pair 7 ps tch-ch Channel-to-channel skew 50 ps ns Test Circuit for Electrical Characteristics(1-5) 6.0V VDD 200-ohm Pulse Generator VIN VOUT D.U.T 4pF CL RT 200-ohm Notes: 1. CL = Load capacitance: includes jig and probe capacitance. 2. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator 3. Output 1 is for an output with internal conditions such that the output is low except when disabled by the output control. output 2 is for an output with internal conditions such that the output is high except when disabled by the output control. 4. All input impulses are supplied by generators having the following characteristics: PRR ≤ MHz, ZO = 50Ω, tR ≤ 2.5ns, tF ≤ 2.5ns. 5. The outputs are measured one at a time with one transition per measurement. Switching Waveforms SEL VDD/2 VDD/2 VDD 0V Output 1 tPZL tPLZ VDD/2 VOH VOL + 0.3V tPHZ tPZH VOH – 0.3V VDD/2 VOL VOH VOL Output 2 Voltage Waveforms Enable and Disable Times Switch Positions Test Switch tPLZ , tPZL (output on B-side) 6.0V tPHZ , tPZH (output on B-side) GND Prop Delay Open 11-0103 11 PS9056A 07/12/11 PI3VDP612-A 4-Lane DisplayPort™ Rev 1.1a Compliant Switch with Triple Control Logic for Fast Switching Test Circuit for Dynamic Electrical Characteristics Agilent N5230A 300kHz-20GHz PNA-L Network Analyzer PI3VDP12412 HP11667A Application Section - Pre-Emphasis Waveforms Input Pre-emphasis = 9.5dB; Red waveform is input of PI3VDP612-A & Black is output of PI3VDP612-A 11-0103 12 PS9056A 07/12/11 PI3VDP612-A 4-Lane DisplayPort™ Rev 1.1a Compliant Switch with Triple Control Logic for Fast Switching Input Pre-emphasis = 6dB; Red waveform is input of PI3VDP612-A and Black is output of PI3VDP612-A 11-0103 13 PS9056A 07/12/11 PI3VDP612-A 4-Lane DisplayPort™ Rev 1.1a Compliant Switch with Triple Control Logic for Fast Switching Input Pre-emphasis = 3.5dB; Red waveform is input of PI3VDP612-A & Black is output of PI3VDP612-A 11-0103 14 PS9056A 07/12/11 PI3VDP612-A 4-Lane DisplayPort™ Rev 1.1a Compliant Switch with Triple Control Logic for Fast Switching Packaging Mechanical: 56-Contact TQFN (ZF) 1 DATE: 05/15/08 DESCRIPTION: 56-contact, Thin Fine Pitch Quad Flat No-lead (TQFN) PACKAGE CODE: ZF56 DOCUMENT CONTROL #: PD-2024 REVISION: C 08-0208 Note: • For latest package info, please check: http://www.pericom.com/products/packaging/mechanicals.php 11-0103 15 PS9056A 07/12/11 PI3VDP612-A 4-Lane DisplayPort™ Rev 1.1a Compliant Switch with Triple Control Logic for Fast Switching Packaging Mechanical: 42-Pin TQFN (ZH) 1 DATE: 02/17/09 Notes: 1. All dimensions are in millimeters, angles in degrees. 2. Coplanarity applies to the exposed thermal pad as well as the terminals. 3. Refer JEDEC MO-220 4. Recommended Land Pattern is for reference only. 5. Thermal Pad Soldering Area DESCRIPTION: 42-contact Thin Fine Pitch Quad Flat No-Lead (TQFN) PACKAGE CODE: ZH (ZH42) REVISION: C DOCUMENT CONTROL #: PD-2035 09-0116 Note: • For latest package info, please check: http://www.pericom.com/products/packaging/mechanicals.php Ordering Information Ordering Code Package Code Package Description PI3VDP612-AZFE ZF Pb-free & Green, 56-contact TQFN PI3VDP612-AZHE ZH Pb-free & Green, 42-contact TQFN Notes: • Thermal characteristics can be found on the company web site at www.pericom.com/packaging/ • "E" denotes Pb-free and Green • Adding an "X" at the end of the ordering code denotes tape and reel packaging Pericom Semiconductor Corporation • 1-800-435-2336 • www.pericom.com 11-0103 DisplayPort is a trademark of VESA www.vesa.org 16 PS9056A 07/12/11