Datasheet

PI3WVR12612
HDMI 2.0, DisplayPort 1.2 Video Switch
Features
Description
ÎÎ4-lane, 1:2 mux/demux that will support RBR, HBR1, or
Pericom Semiconductor’s PI3WVR12612 is a multi-standard
video switch with wide voltage range capability. It supports
DisplayPort 1.2, HDMI 2.0, and emerging and proprietary standards.
HBR2
ÎÎData rate: 3.4 Gbps to 6.0 Gbps for high data channels
PI3WVR12612 can pass high-speed signals up to 1.2 V peakto-peak differential with a common-mode voltage from 0 to
3.4V. The wide voltage range allows DC-coupled multi-standard
operation. Eliminating AC coupling capacitors saves board space
and improves signal integrity for dense PCB designs.
ÎÎ1-channel 1:2 mux/demux for HPD signal
ÎÎDifferential switch matrix for DP AUX and HDMI DDC
ÎÎsupports 720 Mbps high-speed DP AUX
ÎÎ-1.8 dB Insertion Loss for Dx channels @ 2.7 GHz
ÎÎ-3 dB Bandwidth for Dx channels:
4.1 GHz
ÎÎReturn loss for Dx channels @ 2.7GHz:
The high speed channels can also pass 0V-3.3V CMOS signals up
to 1MHz.
-14 dB
In addition to four high-speed lanes, PI3WVR12612 also switches AUX, DDC, and HPD signals.
ÎÎLow Crosstalk for high speed channels: -28 dB@5.4 Gbps
ÎÎLow Off Isolation for high speed channels:
-22dB@5.4 Gbps
ÎÎLow channel-to-channel skew, 35ps max
ÎÎLow Bit-to-Bit Skew, 5ps typ (between '+' and '-' bits)
Application
ÎÎVDD Operating Range: 3.3V +/-10%
Routing of DisplayPort and HDMI signals with low signal attenuation between source and sink.
ÎÎESD Tolerance: 2kV HBM
ÎÎPackaging (Pb-free & Green):
-50-ball TFBGA (NEE)
-52-pin TQFN (ZL52)
Block Diagram
D0+
D0+A
D0D1+
D0-A
D1+A
AUX+B
SCL_A
D1-
D1-A
SCL_B
D2+
D2+A
D2D3+
D0-A
D3+A
D3-
D3-A
AUX+
AUX+A
SCL
AUX-
D0+B
AUX-A
AUX-B
SDA_A
D0-B
D1+B
SDA_B
D1-B
SDA
D2+B
D2-B
D3+B
HPD
D3-B
HPDA
HPDB
Logic
Control
DDC_AUX_SEL
GPU_SEL
OE
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PI3W VR12612
HDMI 2.0, DisplayPort 1.2 Video Switch
1
2
A
GPU
GPU_SEL
VDD
B
D0-
D0+
_SEL
C
3
GND
4
5
6
D0-A
D1-A
D2-A
D0+A
D1+A
D2+A
Pin Assignment (52-Pin TQFN, ZL52)
7
OE
8
9
D3+A
D3-A
D0+B
D0-B
DDC_
AUX_
SEL
GND
D
D1-
D1+
D1+B
D1-B
E
D2-
D2+
D2+B
D2-B
F
D3-
D3+
D3+B
D3-B
GND
GND
G
H
AUX-
AUX+
HPD_B
GND
SCL_B
AUX+B
GND
SCL_A
AUX+A
J
HPD
HPD_A
SCL
Vdd
SDA_B
AUX-B
SDA
SDA_A
AUX-A
D0-A
D0+A
D1-A
D1+A
GND
Pin Assignment (50-Ball TFBGA, NEE)
VDD
GND
GPU_SEL
D0D0+
DDC_AUX_SEL
D1D1+
D2D2+
D3D3+
GND
VDD
AUXAUX+
HPD_B
HPD_A
HPD
SCL
SDA
Truth Table
Switch Function
OE
GPU_
SEL
DDC_
AUX_
SEL
D0D3 AUX
HPD
DDC
High
Low
Low
A
AUX A
HPD A
Hi-Z
High
High
Low
B
AUX B
HPD B
Hi-Z
High
Low
High
A
DDC A HPD A
Hi-Z
High
High
High
B
DDC B
HPD B
Hi-Z
High
Low
Medium
A
AUX A
HPD A
DDC A
High
High
Medium
B
AUX B
HPD B
DDC B
Low
x
x
Hi-Z
Hi-Z
Hi-Z
Hi-Z
52 51 50 49 48
22 23 24 25 26
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
OE
D2-A
D2+A
D3-A
D3+A
VDD
D0-B
D0+B
D1-B
D1+B
GND
D2-B
D2+B
D3-B
D3+B
SDA_A
SCL_A
GND
AUX-A
AUX+A
GND
SDA_B
SCL_B
AUX-B
AUX+B
VDD
Control
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
ÎÎMedium level = 1/2 VDD = 1.65V
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PI3W VR12612
HDMI 2.0, DisplayPort 1.2 Video Switch
Pin Description
pin#
pin Name
Signal Type
Description
A1
GPU_SEL
I
switch logic control
B1
D0-
I/O
negative differential signal 0 for COM port
B2
D0+
I/O
positive differential signal 0 for COM port
D1
D1-
I/O
negative differential signal 1 for COM port
D2
D1+
I/O
positive differential signal 1 for COM port
E1
D2-
I/O
negative differential signal 2 for COM port
E2
D2+
I/O
positive differential signal 2 for COM port
F1
D3-
I/O
negative differential signal 3 for COM port
F2
D3+
I/O
positive differential signal 3 for COM port
B3
GND
Ground
Ground
H1
AUX-
I/O
negative differential signal for AUX COM port
H2
AUX+
I/O
posititve differential signal for AUX COM port
J1
HPD
I/O
HPD for COM port
J2
HPD_A
I/O
HPD for port A
H3
HPD_B
I/O
HPD for port B
C8
GND
Ground
Ground
J4
VDD
Pwr
3.3V +/-10% power supply
G2
GND
Ground
Ground
H6
AUX+B
I/O
positive differential signal for AUX, port B
J6
AUX-B
I/O
negative differential signal for AUX, port B
H9
AUX+A
I/O
positive differential signal for AUX, port A
J9
AUX-A
I/O
negative differential signal for AUX, port A
G8
GND
Ground
Ground
F8
D3+B
I/O
positive differential signal 3 for portB
F9
D3-B
I/O
negative differential signal 3 for portB
E8
D2+B
I/O
positive differential signal 2 for portB
E9
D2-B
I/O
negative differential signal 2 for portB
D8
D1+B
I/O
positive differential signal 1 for portB
D9
D1-B
I/O
negative differential signal 1 for portB
B8
D0+B
I/O
positive differential signal 0 for portB
B9
D0-B
I/O
negative differential signal 0 for portB
(Continued)
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PI3W VR12612
HDMI 2.0, DisplayPort 1.2 Video Switch
pin#
pin Name
Signal Type
Description
A8
D3+A
I/O
positive differential signal 3 for port A
A9
D3-A
I/O
negative differential signal 3 for port A
H4
GND
Ground
B6
D2+A
I/O
positive differential signal 2 for port A
A6
D2-A
I/O
negative differential signal 2 for port A
B5
D1+A
I/O
positive differential signal 1 for port A
A5
D1-A
I/O
negative differential signal 1 for port A
B4
D0+A
I/O
positive differential signal 0 for port A
A4
D0-A
I/O
negative differential signal 0 for port A
A2
VDD
Pwr
Power
C2
DDC_
AUX_SEL
I
switch logic control
H5
SCL_B
I/O
DDC_clock channel for port B
H7
GND
Ground
H8
SCL_A
I/O
DDC_clock channel for port A
J5
SDA_B
I/O
DDC_data channel for port B
J8
SDA_A
I/O
DDC_data channel for port A
J3
SCL
I/O
DDC_clock channel for COM port
J7
SDA
I/O
DDC_data channel for COM port
B7
OE
I
Output enable. if OE is high, IC is enabled. If OE is low, then IC is power down and
all I/Os are hi-z
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PI3W VR12612
HDMI 2.0, DisplayPort 1.2 Video Switch
Maximum Ratings
(Above which useful life may be impaired. For user guidelines, not tested.)
Storage Temperature ........................................................... –65°C to +150°C
Supply Voltage to Ground Potential ....................................–0.5V to +4.2V
DC Input Voltage .......................................................................–0.5V to VDD
High Speed Data Channel........................................................ –0.5V to 3.8V
HPD_x, SDA_x, SCL_x............................................................. -0.5V to 5.5V
DC Output Current ..............................................................................120mA
Power Dissipation .................................................................................... 0.5W
Note: Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to
the device. This is a stress rating only and functional
operation of the device at these or any other conditions above
those indicated in the operational sections of this specification
is not implied. Exposure to absolute maximum rating condi-
tions for extended periods may affect reliability.
DC Electrical Characteristics for Switching over Operating Range (TA = –40°C to +105°C, VDD =
3.3V ±10%)
Parameter Description
Test Conditions(1)
VIH
Input HIGH Voltage (OE, GPU_SEL)
Guaranteed HIGH level
VIL
Input LOW Voltage (OE, GPU_SEL)
Guaranteed LOW level
VIH
Input HIGH Voltage (DDC_AUX_SEL)
Guaranteed HIGH level
2.65
VIM
Input Mid-Level Voltage (DDC_AUX_
SEL)
Guaranteed MID level
VDD/2300mV
VIL
Input LOW Voltage (DDC_AUX_SEL)
Guaranteed LOW level
-0.5
VIK
Clamp Diode Voltage (HS Channel)
VDD = Max., IIN = –18mA
–1.6V
–1.8
VIK
Clamp Diode Voltage (Aux, Cntrl )
VDD = Max., IIN = –18mA
–0.7
–1.5
IIH
Input HIGH Current (All Control Pins)
VDD = Max., VIN = VDD
±5
IIL
Input LOW Current (All Control Pins)
VDD = Max., VIN = GND
±5
IOFF_SB
I/O leakage when part is off for sideband
signals only (DDC, AUX, HPD)
VDD = 0V, VINPUT = 0V to
3.6V
20
RON_HS
On resistance between input to output for
high speed signals
VINPUT,cm = 0V to 3.4V,
VINPUT,diff < 1.2Vp-p,diff,
VDD = 3.0V, IINPUT = 20mA
11
Ohm
RON_AUX
On resistance between input to output for
side-band signals (AUX)
VDD = 3.0V, Vinput = 0 to 3.3V,
IINPUT = 20mA
7
Ohm
RON_DDC
On resistance between input to output for
DDC channel
VDD = 3.0V, Vinput = 0V,
IINPUT = 20mA
12
Ohm
RON_HPD
On resistance between input to output for
HPD channel
VDD = 3.0V, Vinput = 0 to 3.0V,
IINPUT = 20mA
7
Ohm
VAUX_SS
Signal Swing Tolerance in Aux path
VDD = 3.0V
VHPD_I
Input voltage on HPD path
VHPD_O
Output voltage tolerance on HPD path
VSDA_X
Input Voltage on SDA path
VPASS
(SDA_X)
Switch output voltage tolerance input
VSCL_X
Input Voltage on SCL path
VPASS
(SCL_X)
Switch output voltage tolerance input
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Min
Typ(2)
Max
1.5
0.75
VDD
VDD/2
VDD/2+
300mV
3.3
2.2
V
5.5
V
3.6
V
V
2.5
5
15-0039
Vin = 5.25V, Ii = 100uA, VDD
= 3.3V
5
1.8
2.2
µA
5.5
5
1.8
V
0.6
–0.5
HPD input from 3.3V to 5.25V
Vin = 5.25V, Ii = 100uA, VDD
= 3.3V
Units
V
V
2.5
V
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PI3W VR12612
HDMI 2.0, DisplayPort 1.2 Video Switch
Power Supply Characteristics (TA = –40°C to +105°C)
Parameter
Description
Test Conditions(1)
Typ(2)
IDD
Power Supply Current
VDD = 3.3V, VIN = GND or VDD
1
3
mA
IDD,Off
Power Supply Current, Disabled
VDD = 3.3V, VIN = GND or VDD,
VOE < VIL
1
50
µA
Min
Max
Units
1. For Max. or Min. conditions, use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at V DD = 3.3V, Ta = 25°C ambient and maximum loading.
Dynamic Electrical Characteristics over Operating Range (TA = -40º to +105ºC, VDD = 3.3V ±10%)
Test Conditions1
Parameter Description
Min
Typ2
MAX
See Fig. 1 for Measurement Setup
f= 2.7 GHz
-28
-25
f = 1.35 GHz
-32
-28
See Fig. 2 for Measurement Setup,
f= 2.7 GHz
-22
-20
f = 1.35 GHz
-30
-27
Units
XTALK
Crosstalk on High Speed Channels
OIRR
OFF Isolation on High Speed
Channels
ILOSS
Differential Insertion Loss on
High Speed Channels
@5.4Gbps (see figure 3)
R loss
Differential Return Loss on high
speed channels
@ 2.7GHz (5.4Gbps)
BW_Dx±
Bandwidth -3dB for Main high
speed path (Dx±)
See figure 3
3.7
4.1
GHz
BW_AUX/
HPD
-3dB BW for AUX, DDC, and
HPD signals
See figure 3
1.35
1.5
GHz
-2.0
dB
dB
-1.8
-14
-12.5
dB
1. For Max. or Min. conditions, use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at V DD = 3.3V, Ta = 25°C ambient and maximum loading.
Switching Characteristics (TA= -40º to +105ºC, VDD = 3.3V±10%)
Parameter
Description
Min.
Typ.
Tpd
Propagation delay (input pin to output pin) on Dx± channels
80
tb-b
Bit-to-bit skew within the same differential pair of Dx± channels
5
tch-ch
Tsw a-b
Max.
Units
ps
7
ps
Channel-to-channel skew of Dx± channels
35
ps
time it takes to switch from port A to port B
0.1
us
Tsw b-a
time it takes to switch from port B to port A
0.1
us
Tstartup
Vdd valid to channel enable
10
us
Twakeup
Enabling output by changing OE from low to High
10
us
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PI3W VR12612
HDMI 2.0, DisplayPort 1.2 Video Switch
BALANCED
PORT1
BALANCED
PORT2
+
50
–
–
50
+
50
–
–
50
+
+
50
+
–
–
50
–
BALANCED
PORT1
BALANCED
PORT2
DUT
DUT
Fig 1. Crosstalk Setup
BALANCED
PORT1
+
+
Fig 2. Off-isolation setup
+
+
–
–
BALANCED
PORT2
DUT
Fig 3. Differential Insertion Loss
Test Circuit for Dynamic Electrical Characteristics
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PI3W VR12612
HDMI 2.0, DisplayPort 1.2 Video Switch
Fig 4. Crosstalk
Fig 5. Off Isolation
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PI3W VR12612
HDMI 2.0, DisplayPort 1.2 Video Switch
Fig 6. Insertion Loss
Fig 7. TDR Channel D0, VDD= 3.0V, 25C
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PI3W VR12612
HDMI 2.0, DisplayPort 1.2 Video Switch
Fig 8. Differential output Eye at Input signal is a 27-1 PRBS, Vdd=3.0V, 25C,
Input swing is 800mV differential
Fig 9. Differential output Eye at Input signal is a 27-1 PRBS, Vdd=3.0V, 25C,
Input swing is 800mV differential
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PI3W VR12612
HDMI 2.0, DisplayPort 1.2 Video Switch
Test Circuit for Electrical Characteristics(1-5)
VDD
0V/3V
PA
3V/0V
PB
D.U.T
COM
4pF
CL
SEL
200-ohm
Pulse
Generator
Notes:
1. CL = Load capacitance: includes jig and probe capacitance.
2. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator
3. All input impulses are supplied by generators having the following characteristics: PRR ≤ MHz, ZO = 50Ω, t R ≤ 2.5ns, t F ≤ 2.5ns.
4. The outputs are measured one at a time with one transition per measurement.
Switching Waveforms
SEL
50%
50%
VDD
0V
Tsw b-a
Output 1
Tsw a-b
VOH
50%
50%
VOL
VOH
VOL
Output 2
Voltage Waveforms Enable and Disable Times
Test Condition
Output 1 Test Conditon
Output 2 Test Conditon
PA = Low
PA = High
PB = High
PB = Low
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PI3W VR12612
HDMI 2.0, DisplayPort 1.2 Video Switch
Packaging Mechanical: 50-Ball TFBGA (NE50)
DATE: 10/26/12
DESCRIPTION: 50-Pin, Thin Fine Pitch Ball Grid Array TFBGA
Notes:
1. Controlling dimensions in millimeters
2. Ref: JEDEC MO-195C
PACKAGE CODE: NE50
DOCUMENT CONTROL #: PD-2101
REVISION: --
12-0332
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PI3W VR12612
HDMI 2.0, DisplayPort 1.2 Video Switch
Packaging Mechanical: 52-Pin TQFN (ZL52)
14-0122
Note:
For latest package info, please check: http://www.pericom.com/products/packaging/mechanicals.php
Ordering Information
Ordering Code
Package Code
Package Description
PI3WVR12612NEE
NE
50-Pin, Thin Fine Pitch Ball Grid Array (TFBGA)
PI3WVR12612NEEX
NE
50-Pin, Thin Fine Pitch Ball Grid Array (TFBGA), Tape & Reel
PI3WVR12612ZLE
ZL
52-Pin, 3.5 x 9.0 mm (TQFN)
PI3WVR12612ZLEX
ZL
52-Pin, 3.5 x 9.0 mm (TQFN), Tape & Reel
Notes:
• Thermal characteristics can be found on the company web site at www.pericom.com/packaging/
• "E" denotes Pb-free and Green
• Adding an "X" at the end of the ordering code denotes tape and reel packaging
Pericom Semiconductor Corporation • 1-800-435-2336
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