313 PI2EQX6804 and PI2EQX6864 4-lane SAS/SATA ReDriver Application Note Introduction Pericom offers two 4-lane SAS/SATA redrivers, which support signals up to 6Gbps: PI2EQX6804-ANJE and PI2EQX6864-AZFE. These devices provide flexible output strength and de-emphasis controls to optimize signals. They pre-compensate for losses across long trace or noisy environment and enable the receiver to receive clean signals with an ideal eye opening. PI2EQX6804-ANJE provides pin strap and I2C options for output swing/de-emphasis configuration and input equalization, while PI2EQX6864-AZFE provides only I2C option. Packaging: 100-contact LFBGA (11x11mm) for PI2EQX6804-ANJE 56-contact TQFN (5x11mm) for PI2EQX6864-AZFE Main Application: Server Desktop Storage/Workstation Figure 1: Typical Application Example Page 1 of 10 AN313 Pericom Semiconductor Corp. www.pericom.com 7/6/2011 313 Output Swing/De-emphasis and Input Equalization of PI2EQX68x4-A through Pin Strap and I2C Control PI2EQX6804-A provides two options, outlined below, to configure output swing/de-emphasis and input equalization. PI2EQX6864-A provides only one option - I2C function, which is configured exactly the same way as PI2EQX6804-A. 1. pin-strap function 2. I2C function The option of the configuration method depends on the state of the MODE pin with 100k internal pull-up resistor. When MODE pin is set HIGH, all the configuration input pins determine all the configuration settings. Note that all of these control pins have 100k internal PULL-UP resistor, and, therefore, only external pull-down resistors are required. The configuration input pins include: D0_A, D1_A, D2_A, S0_A, S1_A, SEL0_A, SEL1_A, SEL2_A, D0_B, D1_B, D2_B, S0_B, S1_B, SEL0_B, SEL1_B, SEL2_B, DE_A, DE_B, LB# and PD#. When MODE pin is set LOW, all the internal configuration registers can be programmed by I2C interface. Note that during initial power-on, the value at the configuration input pins are latched to the configuration registers as the initial startup states. The integrated I2C interface operates as a slave device, supporting standard rate operation of 100Kbps, with 7bit addressing mode and LSB indication either a read or write operation as shown below. The address for a specific device is determined by A0, A1 and A4 pins with internal pull-up resistors. So up to eight PI2EQX6804-A devices can be connected to a single I2C bus. Data bytes must be 8-bits long and transferred with MSB first. Please refer to I2C data transfer diagram in Page13 of datasheet. Data byte definition is shown below. Please refer to Page 8 -11 of the datasheet for details. I2C input pins, SCL and SDA, are tolerant with +3.3V power. Page 2 of 10 AN313 Pericom Semiconductor Corp. www.pericom.com 7/6/2011 313 For I2C configuration sequence in details, please refer to Page 6-7 of this document. External Components Requirement PI2EQX68x4-A requires AC coupling capacitors for all redriver inputs and outputs. High-quality, low-ESR, X7R, 10nF, 0402-sized capacitors are recommended. Layout Design Guide Layout Considerations for Differential Pairs - The trace length miss-matching shall be less than 5 mils for the “+” and “–“ traces in the same pairs - Use wider trace width, with 100ohm differential impedance, to minimize the loss for long routes - Target differential Zo of 100ohm ±20% - More pair-to-pair spacing for minimal crosstalk coupling, it is recommended to have >3X gap spacing between differential pairs. - It is preferable to route differential lines exclusively on one layer of the board, particularly for the input traces - The use of vias should be avoided if possible, if vias must be used, they should be used sparingly and must be placed symmetrically for each side of a given differential pair. - Route the differential signals away from other signals and noise sources on the printed circuit board PCB Layout Trace Routings Figure 2: PCB Layout Trace Routings Page 3 of 10 AN313 Pericom Semiconductor Corp. www.pericom.com 7/6/2011 313 Power-Supply bypass Caution must be taken and details must be carefully observed in high-speed design and to provide a clean power supply. Here are the recommendations: The supply (VDD) and ground (GND) pins should be connected to power planes routed on adjacent layers of the printed circuit board. The distance to plane should be <50mil. The layer thickness of the dielectric should be minimized so that the VDD and GND planes create a low inductance supply with distributed capacitance. Be careful to supply bypassing through the proper use of required bypass capacitors. A low-ESR 0.01uF bypass capacitor should be connected to each VDD pin such that the capacitor is placed as close as possible to PI2EQX68x4-A. Smaller body size capacitors can help facilitate proper component placement. The distance of capacitors to IC body should be <100mil. One capacitor with capacitance in the range of 1uF to 10uF should be incorporated in the power supply bypassing design as well. It is can be either tantalum or an ultra-low ESR ceramic. Power Supply Sequencing Proper power supply sequencing is recommended for all devices. Always apply GND and VDD before applying signals, especially if the signal is not current limited. Caution: Do NOT exceed the absolute maximum ratings because stresses beyond the listed ratings can cause permanent damage to the device. Equalization Setting Table 1 below shows various Input Trace and Eye Test with different EQ settings Figure3 below shows PI2EQX68x4-A test setup for different EQ settings, where R is PI2EQX68x4-A. Signal Source: PRBS2^7-1 pattern, Differential Voltage is 600mV, Pre-emphasis is 0dB Input Trace SELx[2..0] Setting Fixture 24inch SMA Cable Signal Generator R TP3 D[2..0]=000 S[1..0]=00 Tektronic Sampling Scope TP4 Figure 3: PI2EQX68x4-A test setup for different equalization setting Page 4 of 10 AN313 Pericom Semiconductor Corp. www.pericom.com 7/6/2011 313 Input Trace Length Eye Diagram vs. EQ setting at 6Gb/s 6 inch FR4 Lab trace (-2dB loss at 6GHz) SEL[2..0] Setting 3.2dB (SEL[2,1,0] =010) 18 inch FR4 Lab trace (-6dB loss at 3GHz) 6.9dB (SEL[2,1,0] =100) 30 inch FR4 Lab trace (-10dB at 3GHz) 10.4dB (SEL[2,1,0] =110) 48 inch FR4 Lab trace (-16dB at 3GHz) 13.8dB (SEL[2,1,0] =111) Input Eye at TP3 Output Eye at TP4 Table 1: Eye Diagram at TP4 vs. Input FR4 trace and EQ setting at 6Gb/s for PI2EQX68x4-A Output Swing Setting Figure 4 below shows the PI2EQX68x4-A test setup for different output swing settings, where R is PI2EQX68x4-A. Signal Source: PRBS2^7-1 pattern, Differential Voltage is 500mV, Pre-emphasis is 0dB S[1..0] Setting Fixture 5cm 100ohm Trace MB R D[2..0]=000 SELx[2..0]=000 Agilent Sampling Scope TP4 Figure 4: PI2EQX68x4-A test setup for different output swing setting S[1..0]=00 S[1..0]=01 S[1..0]=10 S[1..0]=11 Output Swing at TP4 vs. OS setting at 3Gb/s Output Swing at TP4 vs. OS setting at 6Gb/s Table 2: Output Swing at TP4 vs. OS setting at 3Gb/s and 6Gb/s for PI2EQX68x4-A Page 5 of 10 AN313 Pericom Semiconductor Corp. www.pericom.com 7/6/2011 313 De-emphasis Setting Figure5 is PI2EQX68x4-A test setup for different De-emphasis setting, R is PI2EQX68x4-A. Signal Source: PRBS2^7-1 pattern, Differential Voltage is 500mV, Pre-emphasis is 0dB D[2..0] Setting Fixture 5cm 100ohm Trace MB R S[1..0]=00 SELx[2..0]=000 Agilent Sampling Scope TP4 Figure 5: PI2EQX68x4-A test setup for different De-emphasis setting D[2..0]=000 D[2..0]=010 D[2..0]=111 Output De-emphasis at TP4 vs. De-em setting at 3Gb/s Output De-emphasis at TP4 vs. De-em setting at 6Gb/s Table 3: De-emphasis at TP4 vs. D[2..0] setting at 3Gb/s and 6Gb/s for PI2EQX68x4-A I2C Configuration Sequence Note: there is one DUMMY byte to be added into sequence. Figure 6: WRITE Sequence Diagram Page 6 of 10 AN313 Pericom Semiconductor Corp. www.pericom.com 7/6/2011 313 Figure 7 below is one example for write sequence at Address = C0 (A4, A1, A0 are pulled down) and Data byte[0..11]=00,00,F0,00,00,FF,FF,FF,00,00,00,EF. Figure 7: I2C WRITE Sequence Sample Note: there is NO DUMMY byte to be added into sequence. Figure 8: I2C READ Sequence Diagram Page 7 of 10 AN313 Pericom Semiconductor Corp. www.pericom.com 7/6/2011 313 Note: Byte0=08 means Channel-A2 has signal input. Figure 9: I2C READ Sequence Sample Page 8 of 10 AN313 Pericom Semiconductor Corp. www.pericom.com 7/6/2011 313 Typical Application Circuit Figure 10 below shows the typical application circuit of PI2EQX6804-A. +3.3V +3.3V +1.2V D3 LED EC1 C1 + C2 C3 0.1u_0402 Q3 MMBT3904 0.1u_0402 0.1u_0402 0.1u_0402 SIG_A R18 or or or or or or or or or Open Open Open Open Open Open Open Open Open PRE_A SEL0_A SEL1_A SEL2_A S0_A S1_A D0_A D1_A D2_A SIG_A E9 C23 C24 C25 C26 C27 C28 C29 C30 HOST_RX 10n_0402 10n_0402 10n_0402 10n_0402 10n_0402 10n_0402 10n_0402 10n_0402 0ohm or Open 0ohm or Open 0ohm or Open MODE LB# PD# A3 A2 D2 D3 H1 J1 J4 H4 G5 F8 C6 A1 A4 A7 A10 B6 D1 D4 D7 D10 G1 G4 G7 G10 K1 K4 K7 K10 PRE-A SEL0_A SEL1_A SEL2_A S0_A S1_A D0_A D1_A D2_A SIG_B D2_B D1_B D0_B S1_B S0_B SEL2_B SEL1_B SEL0_B PRE-B PI2EQX6804-A@LBGA100 SIG_A B0TX+ B0TXB1TX+ B1TXB2TX+ B2TXB3TX+ B3TX- B0RX+ B0RXB1RX+ B1RXB2RX+ B2RXB3RX+ B3RX- MODE LB# PD# SCL SDA A0 A1 A4 B2 B3 B8 B9 C2 C3 C8 C9 H2 H3 H8 H9 J2 J3 J8 J9 R32 R33 R35 B5 E1 E2 E3 E6 E8 E4 E5 D5 A0TX+ A0TXA1TX+ A1TXA2TX+ A2TXA3TX+ A3TX- C7 B7 B10 C10 G8 G9 K9 K8 C15 C16 C17 C18 C19 C20 C21 C22 10n_0402 10n_0402 10n_0402 10n_0402 10n_0402 10n_0402 10n_0402 10n_0402 SIG_B F2 K5 J6 G6 F3 F5 F7 F9 F10 H5 Device_RX D2_B D1_B D0_B S1_B S0_B SEL2_B SEL1_B SEL0_B PRE_B R6 R13 R15 R21 R23 R25 R26 R27 R28 0ohm 0ohm 0ohm 0ohm 0ohm 0ohm 0ohm 0ohm 0ohm or or or or or or or or or Open Open Open Open Open Open Open Open Open A8 A9 D9 D8 H10 J10 J7 H7 A5 A6 H6 F6 K6 Device or Connector Device_TX A0 A1 R34 R36 SCL SDA 0ohm or Open 0ohm or Open NC NC NC NC NC NC NC 0ohm 0ohm 0ohm 0ohm 0ohm 0ohm 0ohm 0ohm 0ohm R7 470 +3.3V R30 R29 10k_0402 10k_0402 J5 E7 E10 D6 C5 F4 F1 R1 R2 R3 R4 R9 R12 R14 R20 R22 A0RX+ A0RXA1RX+ A1RXA2RX+ A2RXA3RX+ A3RX- GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND HOST_TX R10 470 VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD U1 C4 B4 B1 C1 G3 G2 K2 K3 Q2 MMBT3904 470 SIG_B R16 470 +1.2V HOST Controller D2 LED C4 22u_3528 HOST_SCLTo HOST_SDA I2C Host Controller Figure 10: Typical Application Circuit of PI2EQX6804-A Figure 11 below shows the typical application circuit of PI2EQX6864-A. R1 R2 4.7K 4.7K +3V3 +1V2 SCL SDA EC1 C1 C2 C3 C4 22u_3528 0.1u_0402 0.1u_0402 0.1u_0402 0.1u_0402 I2C_Host_SCL I2C_Host_SDA + To I2C Host Controller +3V3 D1 LED R3 PD# R4 Q1 MMBT3904 SIG_A Close to TX 470 57 56 55 54 53 52 51 50 49 C40 C42 C43 C44 C45 C46 C39 C41 U1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 HOST Controller C23 C24 C25 C26 C27 C28 C29 C30 10n_0402 10n_0402 10n_0402 10n_0402 10n_0402 10n_0402 10n_0402 10n_0402 VDD A0RX+ A0RXB0TX+ B0TXVDD A1RX+ A1RXB1TXB1TX+ VDD A2RX+ A2RXB2TXB2TX+ VDD A3RX+ A3RXB3TX+ B3TX- A0TX+ A0TXB0RX+ B0RXVDD A1TX+ A1TXB1RXB1RX+ VDD A2TX+ A2TXB2RXB2RX+ VDD A3TX+ A3TXB3RX+ B3RXVDD 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 10n_0402 10n_0402 10n_0402 10n_0402 10n_0402 10n_0402 10n_0402 10n_0402 Device_RX Device or Connector Close to TX C49 C51 C50 C53 C52 C54 C47 C48 10n_0402 10n_0402 10n_0402 10n_0402 10n_0402 10n_0402 10n_0402 10n_0402 Device_TX 21 22 23 24 25 26 27 28 VDD SIG_B MODE NC A4 A0 A1 LB# HOST_RX R5 +1V2 10n_0402 10n_0402 10n_0402 10n_0402 10n_0402 10n_0402 10n_0402 10n_0402 HGND GND GND NC SCL SDA PD# SIG_A VDD HOST_TX C32 C34 C35 C36 C37 C38 C31 C33 470 Open SIG_B PI2EQX6864-AZFE@TQFN56 LB# A1 A0 A4 Mode R6 R7 R8 R9 R10 0ohm 0ohm 0ohm 0ohm 0ohm or or or or or Open Open Open Open Open +3V3 D2 LED R11 R12 470 Q2 MMBT3904 470 Figure 11: Typical Application Circuit of PI2EQX6864-A Page 9 of 10 AN313 Pericom Semiconductor Corp. www.pericom.com 7/6/2011 313 PCB Layout Sample Figure12 shows the typical layout routing of PI2EQX6804-A. Top Layer View Bottom Layer View Figure 12: Typical Layout Routing of PI2EQX6804-A Figure12 shows the typical layout routing of PI2EQX6864-A. Top Layer View Bottom Layer View Figure 13: Typical Layout Routing of PI2EQX6864-A Page 10 of 10 AN313 Pericom Semiconductor Corp. www.pericom.com 7/6/2011