RT8121

RT8121
Single Phase PWM Controller with 1-bit VID
General Description
Features
RT8121 is a single phase PWM buck controller with one
integrated MOSFET driver for advanced microprocessor
application as VR12 VCCIO power. This controller
maintains the same features as the multi-phase product
family, but reduces the output to one phase for lower current
systems. Features of this controller include adjustable
operation frequency, power good indication, external erroramp compensation, over voltage protection, over current
protection, externally adjustable offset voltage, load
transient enhancement (quick response), and enable/
shutdown control to achieve optimal power management
solution for various applications. The RT8121 comes in
the WQFN-20L 3x3 package.
z
Single Phase Power Conversion
z
One Embedded MOSFET Driver with Internal
Bootstrap Diode
1-bit VID Table for VR12 VCCIO
Continuous Differential Inductor DCR Current Sense
Adjustable Soft-Start
Adjustable Frequency Typically at 200kHz
Power Good Indication
Adjustable Over Current Protection
Over Voltage Protection
Over Temperature Protection
Small 20-Lead WQFN Package
RoHS Compliant and Halogen Free
Ordering Information
Applications
Package Type
QW : WQFN-20L 3x3 (W-Type)
Lead Plating System
G : Green (Halogen Free and Pb Free)
Z : ECO (Ecological Element with
Halogen Free and Pb free)
z
z
z
z
z
z
z
z
z
z
z
VR12 VCCIO Voltage Regulator
Low Voltage, High Current DC/DC Converter
Pin Configurations
(TOP VIEW)
GND
GND
VID
PGOOD
BOOT
RT8121
z
Note :
Richtek products are :
RoHS compliant and compatible with the current requirements of IPC/JEDEC J-STD-020.
Suitable for use in SnPb or Pb-free soldering processes.
20 19 18 17 16
FBRTN
SS
COMP
FB
ADJ
1
15
2
14
GND
3
4
21
5
J1= : Product Code
J1=YM
DNN
7
8
9 10
OFS
RT/EN
VCC5
ISP
ISN
RT8121GQW
12
11
6
Marking Information
13
UGATE
PHASE
VCC12
LGATE
OCSET
WQFN-20L 3x3
YMDNN : Date Code
RT8121ZQW
J1 : Product Code
J1 YM
DNN
YMDNN : Date Code
DS8121-02 May 2011
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1
RT8121
Typical Application Circuit
VIN
4.5 to 13.2V
C11
R20
12V
C9
RT8121
R19
5
ADJ
13 VCC12
19, 20, 21 (Exposed Pad) GND
7
Q3
EN
PHASE 14
LGATE
ISP
R16
R1
C1
NTC
Q1
L
R2
VOUT
Q2
12
ISN
OCSET
9
R5
10
R6
D1
Option for
Positive OFS
R13
FB 4
COMP
Option for
Negative
OFS
18 VID
17 PGOOD
PGOOD
C5
Load
R8
VCC5
6 OFS
R14
C14
C2
8
C10
C3
R4
R3
RT/EN
RRT
11
R15
BOOT 16
UGATE 15
FBRTN
3
R7
C6
R9
SS 2
R12
R11
VCC_SNS
R21
C7
1
Option
R10
C8
VSS_SNS
C12
C13
R17
VTT
Function Block Diagram
Fault Logic
Offset
OFS
Transient
Response
Enhancement
FB
Driver
Logic
VCC12
MOSFET
Driver
EA
+
BOOT
UGATE
PHASE
LGATE
GND
COMP
+
CMP
PWM
OV
OT
-
+
RT/EN
Modulation
Waveform
Generator
Thermal
Protection
+ 150mV
EAP
VID
FBRTN
VR11 VID
Table
+-
PGOOD
Soft Start
and Fault
Logic
+
/10
VID Off
SS
OC
OV
OC
OT
ADJ
Current
Sense
Driver Logic
POR
OCSET
ISP
ISN
VCC12
Power On
Reset
5V
Regulator
VCC5
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2
DS8121-02 May 2011
RT8121
Functional Pin Description
Pin No.
Pin Name
1
FBRTN
2
SS
3
COMP
Pin Function
Return Ground. This pin is Negative Node of the differential Remote Voltage
sending.
Soft-Start Ramp Slope Set Pin. Connect this pin to FBRTN by a Capacitor to
Adjust soft-start slew rate.
Compensation Pin. Output of Error Amplifier and Input of PWM comparator.
4
FB
Inverting Input of Error Amplifier.
5
ADJ
6
OFS
7
RT/EN
Droop Set Pin. Connect a resistor from this pin to GND sets the load line slope.
Voltage Offset Pin. This pin sets no load output voltage offset. Connect a
resistor from this Pin to VCC5 or GND to bidirection set the output voltage
no-load offset.
Switching Frequency Set Pin. Connect this pin to GND by a resistor to adjust
switching frequency and operate with droop function.
8
VCC5
Internal 5V Regulator Output.
9
ISP
Non-invertering Input of Current Sense Amplifier.
10
ISN
Invertering Input of Current Sense Amplifier.
11
OCSET
Over Current Protection Threshold Set Pin.
12
LGATE
Lower Gate Driver. This pin drives the gate of low side MOSFETs.
13
VCC12
14
PHASE
15
UGATE
16
BOOT
17
PGOOD
12V Power Supply Input Pin.
Switch Node of High Side Driver. Connect this pin to high side MOSFETs
sources together with the low side MOSFETs drains and inductor.
Upper Gate Driver. This pin drives the gate of the high side MOSFETs.
Bootstrap Power Pin. This pin powers the high side MOSFETs drivers. Connect
this pin to the junction of the bootstrap capacitor with the cathode of the
bootstrap diode.
Power Good Indicator.
18
VID
DAC Voltage Identification Inputs.
19, 20,
GND
21 (Exposed Pad)
Ground Pin. The exposed pad must be soldered to a large PCB and connected
to GND for maximum power dissipation.
Table 1. Output Voltage Program
VID
DAC Output Voltage
1
0
1.050V
1.000V
DS8121-02 May 2011
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3
RT8121
Absolute Maximum Ratings
(Note 1)
Supply Input Voltage -------------------------------------------------------------------------------------- −0.3V to 15V
z BOOT to PHASE ------------------------------------------------------------------------------------------ 1.7V to 15V
z PHASE to GND
DC ------------------------------------------------------------------------------------------------------------- −2V to 15V
<20ns -------------------------------------------------------------------------------------------------------- −5V to 30V
z UGATE to PHASE
DC ------------------------------------------------------------------------------------------------------------- −0.3V to 15.3V
<20ns -------------------------------------------------------------------------------------------------------- −5V to 18V
z LGATE to GND
DC ------------------------------------------------------------------------------------------------------------- (GND − 0.3V) to (VCC + 0.3V)
<20ns -------------------------------------------------------------------------------------------------------- (GND − 5V) to (VCC + 5V)
z Input/Output Voltage -------------------------------------------------------------------------------------- −0.3V to 6.5V
z Power Dissipation, PD @ TA = 25°C
WQFN-20L 3x3 -------------------------------------------------------------------------------------------- 1.471W
z Package Thermal Resistance (Note 2)
WQFN-20L 3x3, θJA --------------------------------------------------------------------------------------- 68°C/W
WQFN-20L 3x3, θJC -------------------------------------------------------------------------------------- 7.5°C/W
z Lead Temperature (Soldering, 10 sec.) --------------------------------------------------------------- 260°C
z Junction Temperature ------------------------------------------------------------------------------------- 150°C
z Storage Temperature Range ---------------------------------------------------------------------------- −65°C to 150°C
z ESD Susceptibility (Note 3)
HBM (Human Body Mode) ------------------------------------------------------------------------------ 2kV
MM (Machine Mode) -------------------------------------------------------------------------------------- 200V
z
Recommended Operating Conditions
z
z
z
(Note 4)
Power Input Voltage, VIN --------------------------------------------------------------------------------- 4.5V to 13.2V
Junction Temperature Range ---------------------------------------------------------------------------- −40°C to 125°C
Ambient Temperature Range ---------------------------------------------------------------------------- −40°C to 85°C
Electrical Characteristics
(TA = 25°C, unless otherwise specified)
Parameter
VCC12 Supply Input
Symbol
VCC12 Supply Voltage
VVCC12
VCC12 Supply Current
IVCC12
Test Conditions
No Switching
Min
Typ
Max
Unit
10.8
12
13.2
V
--
6
--
mA
4.9
5
5.1
V
VCC5 Power
VCC5 Supply Voltage
VVCC5
ILOAD = 10mA
VCC5 Output Sourcing
IVCC5
10
--
--
mA
VCC12 Rising Threshold
VVCC12_th
9.2
9.6
10
V
VCC12 Hysteresis
VVCC12_hys
--
0.9
--
V
VCC5 Rising Threshold
VVCC5_ th
4.4
4.6
4.8
V
VCC5 Hysteresis
VVCC5_ hys
--
0.4
--
V
Power On Reset
To be continued
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4
DS8121-02 May 2011
To be continued
RT8121
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
--
--
0.4
V
180
200
220
kHz
1.52
1.6
1.68
V
VVCC5 −
1.68
VVCC5 −
1.6
VVCC5 −
1.52
V
--
22
--
%/V
−0.5
--
0.5
%
RT/EN
Chip Disable Threshold
VDIS
Running Frequency
fOSC
RT Pin Voltage
VRT, GND
RT Pin Voltage
VRT, VDD
Modulation Gain
ARAMP
RRT = 60kΩ
RRT = 60kΩ, when RT
connected to GND by a register
RRT = 60kΩ, when RT
connected to VCC5 by a register
RRT = 60kΩ
Reference Voltage Accuracy
DAC Accuracy
VID Input Low Voltage
VID
--
--
0.4
V
VID Input High Voltage
Error Amplifier
VID
0.8
--
--
V
DC Gain
Gain-Bandwidth
ADC
GBW
No Load
CLOAD = 10pF
---
80
10
---
dB
MHz
Slew Rate
SR
CLOAD = 10pF
10
--
--
V/μs
Output Voltage Range
VCOMP
0.5
--
3.6
V
Maximum Current
IEA_SLEW Slew
300
--
--
μA
--
--
0.4
V
Power Sequence
PGOOD Low Voltage
VPGOOD
IPGOOD = 4mA
Soft-Start Delay
TD1
0
--
5
ms
PGOOD Delay
Current Sense Amplifier
TD3
0.05
--
4
ms
Maximum Current
IGMMAX
100
--
--
μA
Input Offset Voltage
VOSCS
−1.5
0
1.5
mV
VCSP = 1.3V, sink current from
CSN
Soft-Start
Soft-Start Current
ISS1
Slew
12
16
20
μA
VID Change Current
ISS2
Slew
120
160
200
μA
0.6
1
--
A
--
1
--
Ω
0.6
1
--
A
--
0.8
--
Ω
125
150
175
mV
−10
--
10
mV
--
160
--
°C
Gate Driver
LGATE Drive Source
VBOOT – VPHASE = 12V,
VUGATE – VPHASE = 6V
– VPHASE = 12V,
V
RUGATEsk BOOT
VUGATE – VPHASE = 1V
ILGATEsr
VVCC12 = 12V, VLGATE = 6V
LGATE Drive Sink
RLGATEsk VVCC12 = 12V, VLGATE = 1V
UGATE Drive Source
UGATE Drive Sink
IUGATEsr
Protection
Over Voltage Threshold
VOVP
OCP Input Offset Voltage
VOCOFS
Thermal Shutdown
Sweep FB Voltage, VFB − VEAP
To be continued
DS8121-02 May 2011
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5
RT8121
Parameter
Dynamic Characteristic
Symbol
UGATE Rise Time
trUGATE
UGATE Fall Time
tfUGATE
LGATE Rise Time
trLGATE
LGATE Rise Time
tfLGATE
Conditions
CISS = 3000pF
Min
Typ
Max
Unit
-
15
-
ns
-
10
-
ns
-
15
-
ns
-
10
-
ns
Note 1. Stresses listed as the above "Absolute Maximum Ratings" may cause permanent damage to the device. These are for
stress ratings. Functional operation of the device at these or any other conditions beyond those indicated in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended
periods may remain possibility to affect device reliability.
Note 2. θJA is measured in natural convection at TA = 25°C on a high effective thermal conductivity four-layer test board of
JEDEC 51-7 thermal measurement standard. The measurement case position of θJC is on the exposed pad of the
package.
Note 3. Devices are ESD sensitive. Handling precaution is recommended.
Note 4. The device is not guaranteed to function outside its operating conditions.
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DS8121-02 May 2011
RT8121
Typical Operating Characteristics
Power On from RT/EN
Power Off from RT/EN
VOUT
(1V/Div)
VOUT
(1V/Div)
RT/EN
(5V/Div)
RT/EN
(5V/Div)
PGOOD
(2V/Div)
PGOOD
(2V/Div)
UGATE
(50V/Div)
VID = 1V, ILOAD = 1A
UGATE
(50V/Div)
Time (1ms/Div)
Time (400μs/Div)
Dynamic VID Up
Dynamic VID Down
VOUT
(500mV/Div)
VOUT
(500mV/Div)
VID
(1V/Div)
VID
(1V/Div)
VID from 0.675V up to 1.3V, ILOAD = 16A
VID from 1.3V down to 0.675V, ILOAD = 16A
Time (40μs/Div)
Time (40μs/Div)
Load Transient Response
Load Transient Response
1.2V ->
20A
1.2V ->
I LOAD
20A
7A
7A
Time (10μs/Div)
DS8121-02 May 2011
VID = 1.3V, fLOAD = 1kHz, ILOAD = 20A to 7A
VOUT
(20mV/Div)
VOUT
(20mV/Div)
VID = 1.3V, fLOAD = 1kHz, ILOAD = 7A to 20A
I LOAD
VID = 0.9V, ILOAD = 1A
Time (10μs/Div)
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RT8121
Over Voltage Protection
Over Current Protection
FB
(500mV/Div)
VOUT
(500mV/Div)
PGOOD
(2V/Div)
I LOAD
(50A/Div)
PGOOD
(2V/Div)
UGATE
(50V/Div)
UGATE
(50V/Div)
LGATE
(20V/Div)
Time (200μs/Div)
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Time (20μs/Div)
DS8121-02 May 2011
RT8121
Applications Information
Supply Voltage, VCC5 Regulation and POR
There are two supply voltage pins built in the RT8121:
VCC12 and VCC5. VCC12 is a power input pin which
receives external 12V voltage for embedded driver logic
operation. VCC5 is a power output pin which is the output
of an internal 5V LDO regulator. The mentioned 5V LDO
regulator regulates VCC12 to generate a 5V voltage source
for internal gate logic and external circuit biasing, e.g.,
OCP biasing. Since the VCC5 voltage is regulated, the
variation of VCC5 (2%) will be much smaller than Platform
ATX 5V (5% to 7%). The maximum supply current of VCC5
is 10mA, which is designed only for controller circuit
biasing. The recommended configuration of the RT8121
supply voltages is as follows: Platform ATX 12V to the
VCC12 pin, and decoupling capacitors on the VCC12 and
VCC5 pins (minimum 0.1μF).
The initialization of the RT8121 requires both the voltage
on the VCC12 and VCC5 to be ready. Since VCC5 is
regulated internally from VCC12, the VCC5 voltage will
be ready (>4.6V) after VCC12 reaches about 7V, so there
is no power sequence problem between VCC12 and VCC5.
After VCC5 > 4.6V and VCC12 > 9.6V, the internal PowerOn-Reset (POR) signal goes high. This POR signal
indicates the power supply voltages are all ready and
initiates soft-start sequence. When POR = low, The
RT8121 will try to turn off both high side and low side
MOSFETs to prevent catastrophic failure.
Switching Frequency
The switching frequency of the RT8121 is set by an external
resistor connected from the RT pin either to GND or to
VCC5. If resistor is connected from RT to GND, the load
line function will be enable as well. More details will be
described in the Load Line section. The frequency vs.
different RRT value is shown as Figure 2.
1000
Switching Frequency (kHz)1
The RT8121 is a single phase synchronous buck DC/DC
converter with embedded MOSFET driver for advanced
microprocessor application power.
800
600
400
200
0
0
10
20
30
40
50
60
70
80
RRT (kΩ)
Figure 2. Switching Frequency vs. RRT Resistance
Chip Enable
The enable function of the RT8121 is combined in the RT
pin. Besides frequency setting function, pulling the RT
pin to GND can also force the IC to enter soft shutdown
sequence. It is recommended to connect a control switch
from RT pin to GND in parallel with RT setting resistors.
The RT8121 will enter soft shutdown sequence when the
control switch is turned on.
Soft-Start
VCC12
9.6V
+
CMP
-
4.6V
+
CMP
-
POR
VCC5
(POR : Power ON Reset)
Figure 1. Circuit for Power Ready Detection
DS8121-02 May 2011
The VOUT soft-start slew rate is set by a capacitor from
the SS pin to FBRTN. Before Power On Reset (POR =
low), the SS pin is held at GND. After Power On Reset
(POR = high) and an extra delay of 1600μs (TD1), the
controller initiates ramping up. VOUT will always trace VEAP
during normal operation of the RT8121, where VEAP is the
positive input of compensation error amplifier, which can
be described as VEAP = VDAC − VADJ (The definition of VADJ
will be described later in the Load Line section). After
receiving valid VID code, VOUT continues ramping up or
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9
RT8121
down to the voltage specified by VID code. After VOUT
ramps to VEAP = VDAC − VADJ, the RT8121 stays in this
state (TD3) and then asserts PGOOD = high. The ramping
slew rate of TD2 is controlled by the external capacitor
connected to SS pin. The voltage of the SS pin will always
be VEAP + 0.7V, where the mentioned 0.7V is the typical
turn-on threshold of an internal power switch. Before
PGOOD = high, the slew rate of VEAP is limited to
16μA/CSS. When PGOOD = high, the slew rate of VEAP is
limited to 160mA/CSS. The soft start waveform is shown
in Figure 4.
C2
C3
R3
R2
R1
VOUT
FB
Soft-Start Current (ISS)
is Limited and Variant
Soft-Start
Circuit
VDAC
C1
COMP
EA
+
EAP
(Error AMP Positive Input)
ISS
SS
CSS
ADJ
RADJ
Figure 3. Circuit for Soft-Start and Dynamic VID
SS
DAC
PGOOD
EN
TD1
TD2
TD3
Figure 4. Soft-Start Waveform
TD1 is the delay time from power on reset state to the beginning of VOUT rising.
TD1 = 1600μs +
0.7V × CSS
16μA
VID × CSS
16μA
TD3 is the power good delay time.
TD2 =
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DS8121-02 May 2011
RT8121
Output Voltage Differential Sensing
Load Transient Quick Response
The RT8121 uses a high-gain low-offset error amplifier for
differential sensing. The CPU voltage is sensed between
the FB and FBRTN pins. A resistor (RFB) connects FB pin
with the positive remote sense pin of the CPU (VCCP),
while the FBRTN pin connects directly to the negative
remote sense pin of the CPU (VCCN). The error amplifier
compares VEAP = ( VDAC − VADJ) with the VFB to regulate
the output voltage.
In steady state, the voltage of VFB is controlled to be very
close to VEAP. While a load step transient from light load
to heavy load could cause VFB to be lower than VEAP by
several tens of mV. In conventional buck converter design
(without non-linear control) for CPU VR application, due
to limited control bandwidth, it is hard for the VR to prevent
VOUT undershoot during quick load transient from light load
to heavy load. Hence, the RT8121 builds in a state-ofthe-art quick response function which detects load
transient by comparing VFB and VEAP. If VFB suddenly
drops below “VEAP−VQR”where VQR is a predetermined
voltage (~40mV), the quick response indicator QR rises
up. When QR = high, the RT8121 turns on all high side
MOSFETs and turns off all low side MOSFETs. The
sensitivity of quick response can be adjusted by varying
the values of CFB and RFB. Smaller RFB and/or larger CFB
No-Load Offset
In Figure 5, IOFSN and IOFSP are used to generate no-load
offset. Either IOFSN or IOFSP is active during normal
operation. Connect a resistor from OFS pin to GND to
activate IOFSN. IOFSN flows through RFB from the FB pin to
VCCP. In this case, a negative no-load offset voltage (VOFSN)
is generated.
0.8 × RFB
VOFSN = IOFSN × RFB =
ROFS
Connect a resistor from OFS pin to VCC5 to activate IOFSP.
IOFSP flows through RFB from VCCP to FB pin. In this case,
a positive no-load offset voltage (VOFSP) is generated.
VOFSP = IOFSP × RFB =
VOUT
C2
RFB
R1
R1
VEAP = VDAC - VADJ
C1
COMP
FB
CFB
EA
+
QR Circuit
C1
IOUT
VOUT
IOFSN
QR
FB
VCC_SNS
(Positive Remote
Sense Pin of CPU)
Figure 6. Load Transient Quick Response
IOFSP
Output Current Sensing
+
+
VDAC
VSS_SNS
(Negative Remote
Sense Pin of CPU)
CFB
6.4 × RFB
ROFS
C2
RFB
will make QR easier to be triggered. Figure 6 is the circuit
and typical waveforms.
+-
EAP
COMP
-
FBRTN
RADJ ADJ
Figure 5. Circuit for VOUT Differential Sensing and NoLoad Offset
DS8121-02 May 2011
The RT8121 provides a low input offset Current Sense
Amplifier (CSA) to monitor the output current. The output
current of CSA (IX) is used for load line control and over
current protection. In this inductor current sensing
topology, RS and CS must be set according to the equation
below :
L
= RS × CS
DCR
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RT8121
Then the output current of CSA will follow the equation
below :
I × DCR - VOFS-CSA + 700n × (RISP + RS - RISN )
IX = L
RISN
700nA is a typical value of the CSA input offset current.
VOFS-CSA is the input offset voltage of CSA. VOFS-CSA of
the RT8121 is smaller than +/- 1.5mV. Usually, “VOFS-CSA
+ 700n x (RISP + RS - RISN)” is negligible except at very
light load and the equation can be simplified as the equation
below :
I × DCR
IX = L
RISN
VIN
UGATE
R1
C1
L
DCR
RS
CS
PHASE
CSA: Current
Sense Amplifier
R2
C2
ISP
+
700nA
VOFS_CSA
IX
Basically, the resistance of RADJ sets the resistance of
the load line. The temperature coefficient of the RADJ
compensates the temperature effect of the load line.
Over Current Protection (OCP)
BOOT
LGATE
temperature effect. In the RT8121, the positive input of
error amplifier is “VDAC − 0.1 x VADJ” and VOUT will follow
“VDAC − 0.1 x VADJ”. Thus, the output voltage which
decreases linearly with IOUT is obtained. The load line is
defined as :
1
VADJ = × Ix × R ADJ
2
1
ΔVADJ
ΔVOUT
1 DCR
1
LL =
= 10
= ×
× × R ADJ
ΔIOUT
ΔIOUT
2 RISN 10
RISP
In Figure 8, VOCSET is equal to VCC5 x R2/(R1 + R2). For
the RT8121, VADJ is proportional to IOUT and is thermally
compensated. Once VADJ is larger than VOCSET, OCP is
triggered and latched. The OCP function will not be
influenced by enabling or disabling load line since the
voltage on the ADJ pin always contains real time
information of load current. Once OCP is triggered, the
RT8121 will turn off both high side MOSFETs and low
side MOSFETs.
+
-
700nA
VCC5
ISN
-
RISN
R1
ADJ
OCSET
+
CMP
-
OCP
R2
Figure 7. Circuit for Current Sensing
Load Line
The RT8121 utilizes inductor DCR current sense technique
for load line control function. The sensed inductor current
IX is multiplied by 0.5 and sent to ADJ pin. After the current
0.5 x IX injects into the ADJ resistors, the voltage of the
ADJ pin is established. The VADJ is then multiplied by 0.1
and subtracted by VDAC to generate VEAP. Because IX is a
PTC (Positive Temperature Coefficient) current, an NTC
(Negative Temperature Coefficient) resistor is needed to
connect ADJ pin to GND. If the NTC resistor is properly
selected to compensate the temperature coefficient of IX,
the voltage on ADJ pin will be proportional to IOUT without
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Figure 8. Over Current Protection
Over Voltage Protection (OVP)
The over voltage protection monitors the output voltage
via the FB pin. Once VFB exceeds “VEAP + 150mV”, OVP
is triggered and latched. The RT8121 will turn on low side
MOSFET and turn off high side MOSFET to protect CPU.
A 20μs delay is used in OVP detection circuit to prevent
false trigger.
DS8121-02 May 2011
RT8121
Over Temperature Protection (OTP)
1) Modulator Characteristic
The over temperature protection function of the RT8121 is
built inside the controller to prevent overheat damage. OTP
occurs when the die temperature of the RT8121 exceeds
150°C, in which the RT8121 then turns off both high side
MOSFETs and low side MOSFETs.
The modulator consists of the PWM comparator and power
stage. The PWM comparator compares error amplifier EA
output (COMP) with oscillator (OSC) sawtooth wave to
provide a pulse-width modulated (PWM) gate-driving
signal. The PWM wave is smoothed out by the output
filter, LOUT and COUT. The output voltage (VOUT) is sensed
and fed to the inverting input of the error amplifier.
VIN
OSC
Driver
PWM
Comparator
ΔVOSC
L
-
VOUT
Driver
+
COUT
ESR
ZFB
COMP
ZIN
EA
+
REF
ZFB
C2
C1
C3
R2
VOUT
R3
R1
COMP
EA
+
ZIN
FB
REF
Figure 9. Compensation Circuit
Loop Compensation
The RT8121 is a voltage mode controller and requires
external compensation. To compensate a typical voltage
mode buck converter, there are two ordinary compensation
schemes, commonly known as type-II compensator and
type-III compensator. The choice of using type-II or
type-III compensator lies with the platform designers, and
the main concern deals with the position of the capacitor
ESR zero and mid-frequency to high frequency gain boost.
Typically, the ESR zero of output capacitor will tend to
stabilize the effect of output LC double poles. Hence, the
position of the output capacitor ESR zero in frequency
domain may influence the design of voltage loop
compensation. Figure 9 shows a typical control loop using
type-III compensator. Below is the compensator design
procedure.
DS8121-02 May 2011
The modulator transfer function is the small-signal transfer
function of VOUT/VCOMP (output voltage over the error
amplifier output). This transfer function is dominated by a
DC gain, a double pole, and an ESR zero as shown in
Figure 10.
The DC gain of the modulator is the input voltage (VIN)
divided by the peak-to-peak oscillator voltage VOSC. The
output LC filter introduces a double pole, 40dB/decade
gain slope above its corner resonant frequency, and a total
phase lag of 180 degrees. The resonant frequency of the
LC filter is expressed as :
fLC =
1
2π x LOUT x COUT
The ESR zero is contributed by the ESR associated with
the output capacitance. Note that this requires the output
capacitor to have enough ESR to satisfy stability
requirements. The ESR zero of the output capacitor is
expressed as the following equation :
1
fESR =
2π x COUT x ESR
2) Design the Compensator
A well-designed compensator regulates the output voltage
to the reference voltage VREF with fast transient response
and good stability. In order to achieve fast transient
response and accurate output regulation, an adequate
compensator design is necessary. The goal of the
compensation network is to provide adequate phase
margin (usually greater than 45°) and the highest bandwidth
(0dB crossing frequency, f C ) possible. It is also
recommended to manipulate loop frequency response that
its gain crosses over 0dB at a slope of -20dB/dec.
According to Figure 10, the location of poles and zeros
are :
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13
RT8121
1
2π x R2 x C1
1
=
2π x (R1 + R3 ) x C3
Thermal Considerations
fZ1 =
fZ2
For continuous operation, do not exceed absolute
maximum junction temperature. The maximum power
dissipation depends on the thermal resistance of IC
package, PCB layout, rate of surrounding airflow and
difference between junction to ambient temperature. The
maximum power dissipation can be calculated by following
the formula :
fP1 = 0
1
2π x C3 x R3
1
=
C1 x C2 x R2
2π x
C1 + C2
fP2 =
fP3
Generally, fZ1 and fZ2 are designed to cancel the double
pole of modulation. Usually, place fZ1 at a fraction of the
fLC, and place fZ2 at fLC. fP2 is usually placed at fESR to
cancel the ESR zero. And fP3 is placed below switching
frequency to cancel high frequency noise.
For given bandwith, R2, fZ1, fZ2, fP2, fP3, then
C1 =
C3 =
R1 =
R3 =
C2 =
1
2π x fZ1 x R2
Where TJ(MAX) is the maximum junction temperature, TA
is the ambient temperature and θJA is the junction to
ambient thermal resistance.
For recommended specifications of operating conditions
of RT8121, the maximum junction temperature is 125°C
and TA is the ambient temperature. The junction to ambient
thermal resistance θ JA is layout dependent. For
WQFN-20L 3x3 packages, the thermal resistance θJA is
68°C/W on the standard JEDEC 51-7 four-layer thermal
test board. The maximum power dissipation at TA = 25°C
can be calculated by the following formula :
[email protected]
2π x fC x R2
1
2π x fZ2 x C3
PD(MAX) = (125°C − 25°C) / (68°C/W) = 1.471W for
WQFN-20L 3x3 package
1
2π x fP2 x C3
2π x fP3
PD(MAX) = (TJ(MAX) − TA) / θJA
C1
x C1 x R2 -1
where [email protected] is open loop gain at cross over frequency
fP2
fP3
Compensation Gain
0
Closed Loop Gain
LOG
Open Loop Gain
LOG
fLC
fESR
fC
Figure 10. Bode Plot of Loop Gain
Frequency
Maximum Power Dissipation (W)1
Gain
fZ1 fZ2
The maximum power dissipation depends on operating
ambient temperature for fixed T J(MAX) and thermal
resistance θJA. For RT8121 package, the derating curve
in Figure 11 allows the designer to see the effect of rising
ambient temperature on the maximum power dissipation.
1.60
Four-Layer PCB
1.40
1.20
1.00
0.80
0.60
0.40
0.20
0.00
0
25
50
75
100
125
Ambient Temperature (°C)
Figure 11. Derating Curve for RT8121 Package
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14
DS8121-02 May 2011
RT8121
Layout Considerations
For best performance of the RT8121, the following
guidelines must be strictly followed :
The power components should be placed first. Keep the
connection between power components as short as
possible.
The shape of the phase plane (the connection plane
between high side MOSFETs, low side MOSFETs and
output inductors) has to be as square as possible. Long
traces, thin bars or separated islands must be avoided
in the phase plane.
inductor (the node connecting phase plane) and the
negative trace (ISN) comes from the negative node of
the output inductor (the node connecting output plane).
DO NOT connect the current-sense traces from the phase
plane or output plane. Only connect these traces from
both sides of the output inductor to achieve the goal of
precise Kelvin sense. The current-sense feedback loops
have to be routed away from switching elements, and the
current-sense RC elements have to be put near their
respective ISN or ISP pins of the RT8121 and also away
from noise switching elements. At lease 10 mm width is
suggested for current sense feedback loops.
Keep snubber circuits or damping elements near its
objects. Phase RC snubbers have to be close to low
side MOSFETs, UGATE damping resistor has to be
close to high side MOSFETs, and boot to phase damping
resistor has to be close to high side MOSFETs and
phase plane. Also, keep the traces of these snubber
circuits as short as possible.
The area of VIN plane (power stage 12V VIN) and VOUT
plane (output bulk capacitors and inductor connection
plane) has to be as wide as possible. Long traces or
thin bars must be avoided in these planes. The plane
trace width must be wide enough to carry large input/
output current (40mm/A).
The following traces have to be wide and short : UGATE,
LGATE, BOOT, PHASE, and VCC12. Make sure the
widths of these traces are wide enough to carry large
driving current (at least 40mm).
The voltage feedback loop contains two traces, VCC
and VSS, which are Kelvin sensed from CPU socket or
output capacitors. These two traces should have 10mm
width and be placed away from high (di/dt) switching
elements such as high side MOSFETs, low side
MOSFETs, phase plane etc. The circuit elements of
voltage feedback loop, such as feedback loop short
resistors and voltage loop compensation RCs, have to
be kept near the RT8121 and also away from switching
elements.
The current sense mechanism of the RT8121 is fully
differential Kelvin sense. Therefore, the current-sense
loop of the RT8121 contain two traces : the positive
trace(ISP) comes from the positive node the of output
DS8121-02 May 2011
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15
RT8121
Outline Dimension
1
1
2
2
DETAIL A
Pin #1 ID and Tie Bar Mark Options
Note : The configuration of the Pin #1 identifier is optional,
but must be located within the zone indicated.
Dimensions In Millimeters
Dimensions In Inches
Symbol
Min
Max
Min
Max
A
0.700
0.800
0.028
0.031
A1
0.000
0.050
0.000
0.002
A3
0.175
0.250
0.007
0.010
b
0.150
0.250
0.006
0.010
D
2.900
3.100
0.114
0.122
D2
1.650
1.750
0.065
0.069
E
2.900
3.100
0.114
0.122
E2
1.650
1.750
0.065
0.069
e
L
0.400
0.350
0.016
0.450
0.014
0.018
W-Type 20L QFN 3x3 Package
Richtek Technology Corporation
Richtek Technology Corporation
Headquarter
Taipei Office (Marketing)
5F, No. 20, Taiyuen Street, Chupei City
5F, No. 95, Minchiuan Road, Hsintien City
Hsinchu, Taiwan, R.O.C.
Taipei County, Taiwan, R.O.C.
Tel: (8863)5526789 Fax: (8863)5526611
Tel: (8862)86672399 Fax: (8862)86672377
Email: [email protected]
Information that is provided by Richtek Technology Corporation is believed to be accurate and reliable. Richtek reserves the right to make any change in circuit
design, specification or other related things if necessary without notice at any time. No third party intellectual property infringement of the applications should be
guaranteed by users when integrating Richtek products into any application. No legal responsibility for any said applications is assumed by Richtek.
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16
DS8121-02 May 2011