RT8116 5V/12V Single Synchronous Buck PWM Controller General Description Features The RT8116 is a low cost PWM controller with an integrated N-MOSFET gate driver for a single synchronous buck converter. The highly integrated 8-pin controller reduces size and cost of the power supply. The RT8116 can be used in a wide variety of applications, since it can work with either 5V or 12V supplies. It provides single feedback loop, voltage mode control with fast transient response. The output voltage can be precisely regulated to as low as 0.8V. Switching frequency is internally set at either 275kHz or 200kHz to save external component. The RT8116 also supports programmable soft-start function via an external capacitor. Protection features include programmable over current protection and under-voltage lockout (UVLO). z z z z z z z z z z z z z Ordering Information RT8116 z Package Type S : SOP-8 SP : SOP-8 (Exposed-Pad-Option 1) Lead Plating System G : Green (Halogen Free and Pb Free) A : 275kHz B : 200kHz Note : Richtek products are : ` Applications z z z z Desktop Computers Graphic Cards 3.3V to 12V Input DC/DC Regulators Low Voltage Distributed Power Supplies Pin Configurations (TOP VIEW) RoHS compliant and compatible with the current requirements of IPC/JEDEC J-STD-020. ` 4.5V to 13.2V Supply Voltage Range Voltage Mode PWM Control Single Buck PWM Controller with Integrated N-MOSFET Driver Integrated Boot-Strapped Diode 0.8V ±1% Internal Reference Internally Fixed Frequency at 275kHz or 200kHz Capacitor Programmable Soft-Start Enable/Shutdown Control On COMP/SD Pin 85% Maximum Duty Cycle Over Current Protection with Lossless Lower MOSFET RDS(ON) Input Under Voltage Lockout Protection Under Voltage Protection Pinless LGATE Over Current Protection Setting (LGOCS) RoHS Compliant and Halogen Free Suitable for use in SnPb or Pb-free soldering processes. Marking Information 8 PHASE UGATE 2 7 COMP/SD GND 3 6 FB LGATE/OCSET 4 5 VCC 8 PHASE BOOT RT8116GS : Product Number RT8116 GSYMDNN YMDNN : Date Code BOOT RT8116GSP : Product Number RT8116 GSPYMDNN SOP-8 YMDNN : Date Code DS8116-02 March 2011 UGATE 2 GND 3 LGATE/OCSET 4 GND 7 COMP/SD 6 FB 5 VCC 9 SOP-8 (Exposed Pad) www.richtek.com 1 RT8116 Typical Application Circuit VIN RT8116 R1 VCC 5 VCC BOOT 1 C1 7 COMP/SD CP EN RC 6 CC 3 FB UGATE 2 CIN RUGATE Q1 LOUT VOUT PHASE 8 LGATE/ 4 OCSET GND RBOOT CBOOT Q2 R5* COUT ROCSET C4* RFB2 RFB1 C6* R8* * : Optional Function Block Diagram VCC Internal Regulator POR BOOT UGATE BG/ Bias FB ISS PWM + + GM - - PHASE Gate Control VCC COMP/SD LGATE/ OCSET ramp Oscillator fault Fault Logic OC + - GND www.richtek.com 2 OCSET Sample /Hold DS8116-02 March 2011 RT8116 Functional Pin Description SOP-8 Pin No. SOP-8 (Exposed Pad) Pin Name 1 1 BOOT 2 2 UGATE 3 3, GND 9 (Exposed Pad) 4 4 LGATE/ OCSET 5 5 VCC 6 6 FB Pin Function Bootstrap Supply Pin for Upper Gate Driver. Connect the bootstrap capacitor between BOOT pin and the PHASE on the upper MOSFET. Upper Gate Driver Output. Connect this pin to gate of the high side N-Channel power MOSFET. This pin is monitored by the adaptive shoot-through protection circuitry to determine when the upper MOSFET is turned off. Ground. Acts as both signal and power ground for the IC. All voltage levels are measured with respect to this pin. Ties the pin directly to the low-side MOSFET source and ground plane with the lowest impedance. The exposed pad must be soldered to a large PCB and connected to GND for maximum power dissipation. The exposed pad must be soldered to a large PCB and connected to GND for maximum power dissipation. Lower gate Driver Output and OCP Set Pin. Connect this pin to the gate of the lower MOSFET; it provides the PWM-controlled gate drive (from VCC). This pin is also monitored by the adaptive shoot-through protection circuitry to determine when the lower MOSFET is turned off. During a short period of time following Power On Reset (POR) or shut down release, this pin is also used to determine the over current threshold of the converter. Connect a resistor (ROCSET) from this pin to GND. See the over current protection section for equations. Power Supply Pin. Connect this pin to a well-decoupled 5V or 12V bias supply. It is also the positive supply for the lower gate driver, LGATE. Feedback Voltage Pin. This pin is the inverting input of the error amplifier. FB senses the switcher output through an external voltage divider network. 7 7 COMP/SD Feedback Compensation Pin. This multiplexed pin can also be used as the SD pin. When COMP voltage is < 0.4V, the chip will be disabled. The compensation capacitor also acts as a soft-start capacitor. 8 8 PHASE Switch Node. Connect this pin to the source of the upper MOSFET and the drain of the lower MOSFET. DS8116-02 March 2011 www.richtek.com 3 RT8116 Absolute Maximum Ratings (Note 1) Control Voltage, VCC ------------------------------------------------------------------------------------z BOOT to PHASE, VBOOT−PHASE ----------------------------------------------------------------------z PHASE to GND DC -----------------------------------------------------------------------------------------------------------< 20ns -----------------------------------------------------------------------------------------------------z UGATE to PHASE DC -----------------------------------------------------------------------------------------------------------< 20ns -----------------------------------------------------------------------------------------------------z LGATE to GND DC -----------------------------------------------------------------------------------------------------------< 20ns -----------------------------------------------------------------------------------------------------z Input/Output Voltage ------------------------------------------------------------------------------------z Power Dissipation, PD @ TA = 25°C SOP-8 ------------------------------------------------------------------------------------------------------SOP-8 (Exposed Pad) ---------------------------------------------------------------------------------z Package Thermal Resistance (Note 2) SOP-8, θJA -----------------------------------------------------------------------------------------------SOP-8 (Exposed Pad), θJA ---------------------------------------------------------------------------SOP-8 (Exposed Pad), θJC ---------------------------------------------------------------------------z Lead Temperature (Soldering, 10 sec.) -------------------------------------------------------------z Junction Temperature -----------------------------------------------------------------------------------z Storage Temperature Range --------------------------------------------------------------------------z ESD Susceptibility (Note 3) HBM (Human Body Mode) ----------------------------------------------------------------------------MM (Machine Mode) ------------------------------------------------------------------------------------z Recommended Operating Conditions z z z z 15V 15V −0.5V to 15V −5V to 25V −0.3V to (VBOOT−PHASE + 0.3V) −5V to (VBOOT−PHASE + 5V) −0.3V to (VCC + 0.3V) −5V to (VCC + 5V) (GND − 3V) to 7V 0.833W 1.333/W 120°C/W 75°C/W 15°C/W 260°C 150°C –65°C to 150°C 2kV 200V (Note 4) Control Voltage, VCC ------------------------------------------------------------------------------------- 4.5V to 13.2V Supply Input Voltage, VIN ------------------------------------------------------------------------------- 2V to 12V Junction Temperature Range --------------------------------------------------------------------------- −40°C to 125°C Ambient Temperature Range --------------------------------------------------------------------------- −40°C to 85°C Electrical Characteristics (VCC = 12V, TA = 25°C, unless otherwise specified) Parameter Symbol Test Conditions Min Typ Max Unit Supply Input Supply Current ICC UGATE, LGATE Open -- 2 -- mA Shutdown Current ISHDN UGATE, LGATE Open -- 1 -- mA Power On Reset Threshold VCCR_TH VCC Rising 3.9 4.1 4.3 V Power On Reset Hysteresis VCC_HYS 0.26 0.45 0.64 V Power On Reset To be continued www.richtek.com 4 DS8116-02 March 2011 RT8116 Parameter Oscillator Symbol Frequency fOSC Ramp Amplitude ΔVOSC Test Conditions Min Typ Max RT8116A 250 275 300 RT8116B 180 200 220 -- 1.3 -- VP-P -- 85 -- % 0.792 0.8 0.808 V Maximum Duty Cycle Unit kHz Reference Reference Voltage V REF Error Amplifier Open Loop DC Gain A DC Guaranteed by Design -- 70 -- dB Gain Bandwidth GBW Guaranteed by Design -- 10 -- MHz Slew Rate SR Guaranteed by Design -- 6 -- V/μs Transconductance gm 2.8 3.6 -- mA/V Output Source Current ICOMPsr VFB < V REF 80 120 -- μA Output Sink Current ICOMPsk VFB < VREF 80 120 -- μA -- 0.1 1 μA 7 10 13 μA -- 100 -- % of VREF Input Bias Current Soft Start SS Source Current ISS VFB < V REF Switch Over Threshold PWM Controller Gate Driver UGATE Drive Source IUGATEsr VBOOT − VPHASE = 12V, max source current -- 1.2 -- A UGATE Drive Sink RUGATEsk VUGATE − VPHASE = 0.1V -- 3 -- Ω LGATE Drive Source ILGATEsr VCC = 12V, max source current -- 1.2 -- A LGATE Drive Sink RLG ATEsk VLGATE = 0.1V VUGATE − VPHASE = 1.2V to VLGATE =1.2V VUGATE − VPHASE = 1.2V to VLGATE = 1.2V -- 1.8 -- Ω -- 30 -- ns -- 30 -- ns -- 75 Deadtime between UGATE Off to LGATE On Deadtime Between LGATE Off to UGATE On Protection Under Voltage Protection V UVP_FB % LGATE OC Setting Current IOCSET Sourced from LGATE 9 10 11 μA Over Current Threshold V PHASE ROCSET = Open -- −375 -- mV Enable Threshold V EN 0.3 0.4 0.55 V Note 1. Stresses listed as the above “Absolute Maximum Ratings” may cause permanent damage to the device. These are for stress ratings. Functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may remain possibility to affect device reliability. Note 2. θJA is measured in natural convection at TA = 25°C on a high-effective four-layer thermal conductivity test board of JEDEC 51-7 thermal measurement standard. The measurement case positions of θJC are on the lead of the SOP package and on the exposed pad of the PSOP package. Note 3. Devices are ESD sensitive. Handling precaution is recommended. Note 4. The device is not guaranteed to function outside its operating conditions. DS8116-02 March 2011 www.richtek.com 5 RT8116 Typical Operating Characteristics Output Voltage vs. Load Current 1.530 95 1.525 90 1.520 Output Voltage (V) Efficiency (%) Efficiency vs. Load Current 100 85 80 75 70 65 1.515 1.510 1.505 1.500 1.495 1.490 60 55 VIN = VCC = 12V, VOUT = 1.5V 1.485 VIN = VCC = 12V, VOUT = 1.5V 1.480 50 0 5 10 15 20 25 0 30 3 6 12 15 18 21 24 27 30 Load Current (A) Load Current (A) Reference Voltage vs. Temperature Frequency vs. Temperature 0.820 300 0.815 290 0.810 280 Frequency (kHz)1 Reference Voltage (V) 9 0.805 0.800 0.795 0.790 0.785 270 260 250 240 230 220 0.780 0.775 VIN = VCC = 12V 210 VIN = VCC = 12V 200 0.770 -50 -25 0 25 50 75 100 125 -50 Power On VUGATE (20V/Div) VLGATE (10V/Div) VLGATE (10V/Div) V CC (10V/Div) V CC (10V/Div) VOUT (2V/Div) VOUT (2V/Div) Time (2.5ms/Div) www.richtek.com 6 0 25 50 75 100 125 Power Off VUGATE (20V/Div) VCC = VIN = 12V, VOUT = 1.5V, ILOAD = 10A -25 Temperature (°C) Temperature (°C) VCC = VIN = 12V, VOUT = 1.5V, ILOAD = 10A Time (5ms/Div) DS8116-02 March 2011 RT8116 COMP/SD Power On COMP/SD Power Off VUGATE (20V/Div) VUGATE (20V/Div) VLGATE (10V/Div) VLGATE (10V/Div) VCOMP (1V/Div) VOUT (2V/Div) VCOMP (1V/Div) VOUT (2V/Div) VCC = VIN = 12V, VOUT = 1.5V, ILOAD = 10A VCC = VIN = 12V, VOUT = 1.5V, ILOAD = 10A Time (2.5ms/Div) Time (1ms/Div) Load Transient Response Load Transient Response VUGATE (20V/Div) VUGATE (20V/Div) I LOAD (10A/Div) I LOAD (10A/Div) VOUT (50mV/Div) VOUT (50mV/Div) VCC = VIN = 12V, VOUT = 1.1V, L = 0.68μH, ILOAD = 15A to 0A VCC = VIN = 12V, VOUT = 1.1V, L = 0.68μH, ILOAD = 0A to 15A Time (10μs/Div) Time (10μs/Div) Over Current Protection Under Voltage Protection VUGATE (20V/Div) VCC = VIN = 12V, VOUT = 1.5V, ROCSET = 6.2k, Low Side MOSFET = IPD06N03 x 2 VLGATE (20V/Div) VLGATE (10V/Div) Inductor Current (20A/Div) VFB (500mV/Div) VOUT (2V/Div) VCC = VIN = 12V, VOUT = 1.5V, No Load Time (25μs/Div) DS8116-02 March 2011 VUGATE (10V/Div) Time (1ms/Div) www.richtek.com 7 RT8116 Application Information The RT8116 is a single-phase synchronous buck PWM controller with integrated N-MOSFET gate drivers. It provides single feedback loop, voltage mode control with fast transient response. An internal 0.8V reference allows the output voltage to be precisely regulated for low output voltage applications. A fixed frequency oscillator is integrated to eliminate external component count. The RT8116 also provides programmable soft-start function via an external capacitor. Protection features include programmable over current protection and under voltage lockout (UVLO). Supply Voltage and Power On Reset (POR) The input voltage range for VCC is from 4.5 V to 13.2 V with respect to GND. An internal linear regulator regulates the supply voltage for internal control logic circuit. A minimum 0.1μF ceramic capacitor is recommended to bypass the supply voltage. Place the bypassing capacitor physically near the IC. The VCC powers the integrated MOSFET driver. A bootstrap diode is embedded to facilitates PCB design and reduce the total BOM cost. No external Schottky diode is required in real applications. The power on reset (POR) circuit monitors the supply voltage at the VCC pin. If VCC exceeds the POR rising threshold voltage (typ. 4V), the controller is reset and prepares the PWM for operation. If VCC falls below the POR falling threshold during normal operation, all MOSFETs stop switching. The POR rising and falling threshold has a hysteresis to prevent noise caused reset. Vcc COMP/SD pin of RT8116 is a multiplexed pin. During softstart and normal converter operation, this pin represents the output of the error amplifier. When COMP/SD voltage falls or is externally pulled low below the enable level VEN, the chip shuts down. When the controller is shut down, UGATE and LGATE signals will go low. When the pull-down device is released and the COMP/SD pin rises above the VEN trip point, the RT8116 will begin a new initialization and soft-start cycle. This allows flexible power sequence control for specified application. In practical applications, connect a small signal MOFSET to COMP/SD pin to implement the enable/ disable function. External Soft-start The RT8116 provides an external soft-start function to prevent large inrush current and output voltage overshoot when the converter starts up. Soft-start begins when the OCP programming is complete. Figure 1 shows the typical soft-start sequence. During soft-start, an internal current source (10μA) is used to charge the external soft-start capacitor at the COMP/SD pin. VCOMP rises up, and the PWM Logic and gate drives are enabled. When the feedback voltage crosses 0.8V, the internal 0.8V reference takes over the behavior of the error operational transconductance amplifier and soft-start is complete. The RT8116 turns off the internal 10μA current source when soft-start is complete. 0.8V 0.8V COMP FB Chip Enable and Disable OCP Programming LG UG POR SS NORMAL UVLO Figure 1. Typical Soft-Start Sequence www.richtek.com 8 DS8116-02 March 2011 RT8116 Soft-Start Time To calculate the soft-start time, the following equation can be used. ( CP + CC ) x ΔV t ss = ISS where C C is the soft-start capacitor and also the compensation capacitor and CP is the additional capacitor from COMP/SD pin to the GND. CP forms the second pole. ISS is the soft-start current, ΔV is the VCOMP voltage from 0.5V to until it reaches regulation. tSS ΔV 0.5V 0.8V VCOMP current ( inductor current valley), and RLGDS(ON) is the LGATE On-Resistance. If ROCSET is not present, there will be no current path for IOCSET to build the OCP threshold. In this situation, the OCP threshold is internally preset to 375mV (typical.). Under Voltage Protection (UVP) The voltage on the FB pin is monitored for under voltage protection. If the FB voltage is lower than the UVP threshold (typically 75% x VREF) during normal operation, UVP will be triggered. When UVP is triggered, both UGATE and LGATE go low. The controller enters hiccup mode until the UVP condition is removed. Output Voltage Setting The RT8116 allows the output voltage of the DC/DC converter to be adjusted from 0.8V to 85% of the VIN supply voltage via an external resistor divider. It will try to maintain the feedback pin at the internal reference voltage. VFB Figure 2. Soft-Start Time VOUT Over Current Protection (OCP) The RT8116 provides over current protection by detecting the voltage drop across low side MOSFET when it is turned on. The over current trip threshold is programmable by an external resistor at the LGATE pin. When LGATE is turned off, the RT8116 samples and holds the phase voltage. The sample-and-hold voltage represents the inductor current valley and is compared to the OCP threshold. If the sensed phase voltage is lower than the OCP threshold, OCP will be triggered. Both UGATE and LGATE will go low, and the controller will enter the hiccup mode until the OCP condition is released. LGATE Over Current Setting (LGOCS) Over current threshold is externally programmed by adding a resistor (ROCSET) between LGATE and GND. Once VCC exceeds the POR threshold, an internal current source IOCSET flows through ROCSET. The voltage across ROCSET is stored as the over current protection threshold VOCSET. After that, the current source is switched off. ROCSET can be determined using the following equation : IVALLEY x RLGDS(ON) ROCSET = IOCSET where IVALLEY represents the desired inductor OCP trip DS8116-02 March 2011 RFB1 FB RFB2 Figure 3. Output Voltage Setting According to the resistor divider network above, the output voltage is set as : ⎛ ⎞ R VOUT = VFB x ⎜ 1 + FB1 ⎟ RFB2 ⎠ ⎝ Input Inrush Current To calculate the input inrush current, the following equation can be used. IINRUSH = COUT x VOUT tSS where IINRUSH is the input current during start up, COUT is the total output capacitance, VOUT is the desired output voltage, and tSS is the soft-start time. If the inrush current is higher than the OCP setting current, OCP is triggered. MOSFET Drivers The RT8116 integrates high current gate drivers for the MOSFETs to obtain high efficiency power conversion in synchronous buck topology. A dead time is used to prevent www.richtek.com 9 RT8116 the crossover conduction for high side and low side MOSFETs. Because both the two gate signals are off during the dead time, the inductor current freewheels through the body diode of the low side MOSFET. The freewheeling current and the forward voltage of the body diode contribute to the power loss. The RT8116 employs adaptive dead time control scheme to ensure safe operation without sacrificing efficiency. Furthermore, elaborate logic circuit is implemented to prevent cross conduction. the transient response will be slower. Therefore, the inductor design is a trade off between performance, size and cost. For high output current applications, two or more power MOSFETs are usually paralleled to reduce RDS(ON). The gate driver needs to provide more current to switch on/off these paralleled MOSFETs. Gate driver with lower source/ sink current capability result in longer rising/ falling time in gate signals, and therefore higher switching loss. where k is the ratio between the inductor ripple current and the rated output current. The RT8116 embeds high current gate drivers to obtain high efficiency power conversion. The embedded drivers contribute to the majority of the power dissipation of the controller. Therefore, SOP package is chosen for its power dissipation rating. If no gate resistor is used, the power dissipation of the controller can be approximately calculated using the following equation : PDRIVER = fSW x (QG_HIGH-SIDE x VBOOT + QG_LOW-SIDE x VDRIVER_LOW-SIDE ) where VBOOT represents the voltage across the bootstrap capacitor. It is important to ensure that the package can dissipate the switching loss and have enough room for safe operation. Inductor Selection The inductor plays an important role in step-down converters because it stores the energy from the input power rail and then released the energy to the load. From the viewpoint of efficiency, the DC resistance (DCR) of the inductor should be as small as possible to minimize conduction loss. In addition, because the inductor takes up most of the board space, its size is also important. Low profile inductors can save board space especially when the height has limitation. However, low DCR and low profile inductors are usually cost ineffective. Larger inductance results in lower ripple current, which means lower power loss. However, the inductor current rising time increases with inductance value. This means www.richtek.com 10 In general, the inductance is designed such that the ripple current ranges between 20% to 40% of the full load current. The minimum inductance required can be calculated using the following equation : VIN − VOUT V L(MIN) = x OUT fSW x k x IOUT_RATED VIN Input Capacitor Selection Voltage rating and current rating are the key parameters in selecting input capacitors. Conservatively speaking, an input capacitor should have a voltage rating 1.5 times greater than the maximum input voltage to be considered a safe design. The input capacitor is used to supply the input RMS current, which can be approximately calculated using the following equation : ⎛ ⎞ VOUT V x ⎜ 1 − OUT ⎟ VIN VIN ⎠ ⎝ The next step is to select a proper capacitor for the RMS current rating. One good design is to use more than one capacitor with low equivalent series resistance (ESR) in parallel to form a capacitor bank. Placing the ceramic capacitor close to the drain of the high side MOSFET is also helpful in reducing the input voltage ripple during heavy load. I RMS = IOUT x Output Capacitor Selection The output capacitor and the inductor form a low pass filter in the buck topology. In steady state condition, the ripple current flowing in and out of the capacitor results in ripple voltage. The output voltage ripples contains two components, ΔVOUT_ESR and ΔVOUT_C. ΔVOUT_ESR = ΔIL x ESR ΔVOUT_C = ΔIL x 1 8 x COUT x fSW When load transient occurs, the output capacitor supplies the load current before the controller can respond. Therefore, the ESR will dominate the output voltage sag during load transient. The output voltage sag can be DS8116-02 March 2011 RT8116 calculated using the following equation : VOUT_SAG = ESR x ΔIOUT For a given output voltage sag specification, the ESR value can be determined. Another parameter that has influence on the output voltage sag is the equivalent series inductance (ESL). The rapid change in load current results in di/dt during transient. Therefore ESL contributes to part of the voltage sag. Use a capacitor that has low ESL to obtain better transient performance. Generally, several capacitors connected in parallel will have better transient performance than just one single capacitor for the same total ESR. Unlike the electrolytic capacitor, the ceramic capacitor has relatively low ESR and can reduce the voltage deviation during load transient. However, the ceramic capacitor can only provide low capacitance value. Therefore, using a mixed combination of electrolytic capacitor and ceramic capacitor can also achieve better transient performance. MOSFET Selection The majority of power loss in the step-down power conversion is due to the loss in the power MOSFETs. For low voltage high current applications, the duty cycle of the high side MOSFET is small. Therefore, the switching loss of the high side MOSFET is of concern. Power MOSFETs with lower total gate charge are preferred in such kind of application. However, the small duty cycle of the high side MOSFET means that the low side MOSFET is on for most of the switching cycle. Therefore, the conduction loss tends to dominate the total power loss of the converter. To improve the overall efficiency, the MOSFETs with low RDS(ON) are preferred in the circuit design. In some cases, more than one MOSFET are connected in parallel to further decrease the on state resistance. However, this depends on the low side MOSFET driver's capability and the budget. Compensation Network Design The RT8116 is a voltage mode controller and requires external compensation to have an accurate output voltage regulation with fast transient response. As shown in Figure 4, the OTA works as the voltage controlled current source. The characteristic of OTA is as below : ΔI gm = OUT , where ΔVM = ( VIN+ ) − ( VIN− ) ΔVM and ΔVCOMP = ΔIOUT x ZOUT VIN+ + VIN- - gm IOUT VCOMP ZOUT Figure 4. Operational Transconductance Amplifier, OTA Figure 5 shows a typical buck control loop using Type II compensator. The control loop consists of the power stage, PWM comparator and a compensator. The PWM comparator compares VCOMP with the oscillator (OSC) sawtooth wave to provide a pulse width modulated (PWM) with an amplitude of VIN at the PHASE node. The PWM wave is smoothed by the output filter LOUT and COUT. The output voltage (VOUT) is sensed and fed to the inverting input of the error amplifier. VIN PWM Comparator UGATE + Driver Logic - ΔVOSC Q1 VOUT LOUT PAHSE LGATE Q2 COUT VREF + GM - FB RFB1 RFB2 COMP VCOMP CC CP RC Figure 5. Typical Voltage Mode Buck Converter Control Loop The modulator transfer function is the small signal transfer function of VOUT/VCOMP (output voltage over the error amplifier output). This transfer function is dominated by a DC gain, a double pole, and an ESR zero as shown in Figure 6. The RT8116 uses a high gain operational transconductance amplifier (OTA) as the error amplifier. DS8116-02 March 2011 www.richtek.com 11 RT8116 80 80 Loop Gain 60 fP1 40 40 Gain (dB) 20 0 Compensation Gain f Z1 fP2 0 -20 f LC Modulator Gain fC -40-40 -60-60 10Hz 10vdb(vo) 100Hz vdb(comp2)100 vdb(lo) 1.0KHz 10KHz 1k 10k Frequency (Hz) Frequency 100KHz 100k 1.0MHz 1M Figure 6. Typical Bode Plot of a Voltage Mode Buck Converter The DC gain of the modulator is the input voltage (VIN) divided by the peak to peak oscillator voltage, VOSC. VIN GainMODULATOR = ΔVOSC The output LC filter introduces a double pole, 40dB/decade gain slope above its corner resonant frequency, and a total phase lag of 180°C . The resonant frequency of the LC filter is expressed as : 1 fLC = 2π LOUT x COUT The ESR zero is contributed by the ESR associated with the output capacitance. Note that this requires that the output capacitor to have enough ESR to satisfy stability requirements. The ESR zero of the output capacitor is expressed as follows : 1 fESR = 2π x COUT x ESR The goal of the compensation network is to provide adequate phase margin (usually greater than 45°C) and the highest bandwidth (0dB crossing frequency). It is also recommended to manipulate the loop frequency response such that its gain crosses over 0dB at a slope of −20dB/ dec. According to Figure 5, the compensation network frequency is as below : fP1 = 0 1 ⎛ CC x Cp ⎞ 2π x R C x ⎜ ⎟ ⎝ CC + CP ⎠ 1 fZ1 = 2π x RC x CC fP2 = Determining the 0dB crossing frequency (fC, control loop www.richtek.com 12 bandwidth) is the first step of compensator design. Usually, fC is set to 0.1 to 0.3 times the switching frequency. The second step is to calculate the open loop modulator gain and find out the gain loss at fC. The third step is to design a compensator gain that can compensate the modulator gain loss at fC. The final step is to design fZ1 and fZ2 to allow the loop to have sufficient phase margin. fZ1 is designed to cancel one of the double poles of the modulator. Usually, place fZ1 before fLC. fP2 is usually placed below the switching frequency (typically, 0.5 to 1 times the switching frequency) to eliminate high frequency noise. Thermal Considerations For continuous operation, do not exceed absolute maximum junction temperature. The maximum power dissipation depends on the thermal resistance of the IC package, PCB layout, rate of surrounding airflow, and difference between junction and ambient temperature. The maximum power dissipation can be calculated by the following formula : PD(MAX) = (TJ(MAX) − TA) / θJA where TJ(MAX) is the maximum junction temperature, TA is the ambient temperature, and θJA is the junction to ambient thermal resistance. For recommended operating condition specifications of the RT8116, the maximum junction temperature is 125°C and TA is the ambient temperature. The junction to ambient thermal resistance, θJA, is layout dependent. For SOP-8 packages, the thermal resistance, θJA, is 120°C/W on a standard JEDEC 51-7 four-layer thermal test board. For PSOP-8 packages, the thermal resistance, θJA, is 75°C/ W on a standard JEDEC 51-7 four-layer thermal test board. The maximum power dissipation at TA = 25°C can be calculated by the following formulas : PD(MAX) = (125°C − 25°C ) / (120°C/W) = 0.833W for SOP-8 package PD(MAX) = (125°C − 25°C ) / (75°C/W) = 1.333W for PSOP-8 package The maximum power dissipation depends on operating ambient temperature for fixed T J(MAX) and thermal resistance, θJA. For RT8116 packages, the derating curves in Figure 7 allow the designer to see the effect of rising ambient temperature on the maximum power dissipation. DS8116-02 March 2011 Maximum Power Dissipation (W)1 RT8116 1.4 1.3 1.2 1.1 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 Four-Layer PCB and the inductors to aid in heat sinking. Using thick copper PCB can also reduces the resistance and inductance to obtain improve efficiency. PSOP-8 ` The bank of the output capacitor should be placed physically close to the load. This can minimize the impedance seen by the load and improve the transient response. ` Place all high frequency decoupling ceramic capacitors close to their decoupling targets. ` Small signal components should be located as close as possible to the IC. Small signal components include feedback components, current sensing components, compensation components, function setting components and any bypass capacitors. These components belong to the high impedance circuit loop and are inherently sensitive to noise pick-up. Therefore, they must be located close to their respective controller pins and away from the noisy switching nodes. SOP-8 0 25 50 75 100 125 Ambient Temperature (°C) Figure 7. Derating Curves for RT8116 Package Layout Considerations Layout planning plays a critical role in modern high frequency switching converter design. A circuit boards with careful layout can help the IC function properly and achieve low losses, low switching noise, and stable operation with improved performance. Without a careful layout, the PCB may radiate excessive noise, causing noise-induced IC problems which contribute to the converter instability. The following guidelines should be strictly followed to have better IC performance. ` ` Provide enough copper area around the power MOSFETs ` A multi-layer PCB design is recommended. Make use of one-single layer as the power ground and have a separate control signal ground as the reference of all signals. Power components should be placed first. Keep the connection between power components as short as possible. ` Input bulk capacitors should be placed close to the drain of the high side MOSFET and the source of the low side MOSFET. ` Place the VCC bypass capacitor as close as possible to the RT8116. ` Minimize the trace length between the power MOSFETs and its drivers. Since the drivers use short, high current pulses to drive the power MOSFETs, the driving traces should be as short and wide as possible to reduce trace inductance. This is especially true for the low side MOSFET, since this can reduce the possibility of the shoot-through. DS8116-02 March 2011 www.richtek.com 13 RT8116 Outline Dimension H A M J B F C I D Dimensions In Millimeters Dimensions In Inches Symbol Min Max Min Max A 4.801 5.004 0.189 0.197 B 3.810 3.988 0.150 0.157 C 1.346 1.753 0.053 0.069 D 0.330 0.508 0.013 0.020 F 1.194 1.346 0.047 0.053 H 0.170 0.254 0.007 0.010 I 0.050 0.254 0.002 0.010 J 5.791 6.200 0.228 0.244 M 0.400 1.270 0.016 0.050 8-Lead SOP Plastic Package www.richtek.com 14 DS8116-02 March 2011 RT8116 H A M EXPOSED THERMAL PAD (Bottom of Package) Y J X B F C I D Dimensions In Millimeters Dimensions In Inches Symbol Min Max Min Max A 4.801 5.004 0.189 0.197 B 3.810 4.000 0.150 0.157 C 1.346 1.753 0.053 0.069 D 0.330 0.510 0.013 0.020 F 1.194 1.346 0.047 0.053 H 0.170 0.254 0.007 0.010 I 0.000 0.152 0.000 0.006 J 5.791 6.200 0.228 0.244 M 0.406 1.270 0.016 0.050 X 2.000 2.300 0.079 0.091 Y 2.000 2.300 0.079 0.091 X 2.100 2.500 0.083 0.098 Y 3.000 3.500 0.118 0.138 Option 1 Option 2 8-Lead SOP (Exposed Pad) Plastic Package Richtek Technology Corporation Richtek Technology Corporation Headquarter Taipei Office (Marketing) 5F, No. 20, Taiyuen Street, Chupei City 5F, No. 95, Minchiuan Road, Hsintien City Hsinchu, Taiwan, R.O.C. Taipei County, Taiwan, R.O.C. Tel: (8863)5526789 Fax: (8863)5526611 Tel: (8862)86672399 Fax: (8862)86672377 Email: [email protected] Information that is provided by Richtek Technology Corporation is believed to be accurate and reliable. Richtek reserves the right to make any change in circuit design, specification or other related things if necessary without notice at any time. No third party intellectual property infringement of the applications should be guaranteed by users when integrating Richtek products into any application. No legal responsibility for any said applications is assumed by Richtek. DS8116-02 March 2011 www.richtek.com 15