BH2221FV Standard ICs 8bit 12ch D/A converter BH2221FV BH2221FV is an 8bit D/A converter for electronic adjustment. The 12-channel DC output voltage can be independently controlled by three-wire serial interface from micro-controller. The D/A converter can generate without loss by Rail-to-Rail output within the setting voltage. The built-in power ON reset circuit keeps the output state Low after the power is ON and prevents the unstable output state. !Applications The voltage adjustment for DVC, DSC etc. !Features 1) 8bit 12-channel D/A converters adopting R-2R system. 2) The full scale output voltage range : 2.7V∼5.5V. 3) 3-wire 12-bit serial interface. 4) POWER ON RESET circuit. 5) SSOP-B20 package. !Absolute maximum ratings (Ta=25°C) Parameter Symbol Limits Power supply voltage VCC −0.3~+7.0 V Maximum output voltage VIN −0.3~VCC V Tstg −55~+125 400 ∗ mW Storage temperature Power dissipation Pd Unit °C ∗Reduced by 4mW for each increase in Ta of 1°C over 25°C. This product is not designed for protection against radioactive rays. !Recommended operating conditions (Ta=25°C) Parameter Symbol Min. Typ. Max. Unit VCC supply voltage VCC 2.7 − 5.5 V VDD supply voltage VDD 2.7 − VCC V Analog output source current IOL − − 1.0 mA Analog output sink current IOH − − 1.0 mA Operating temperature range Clock frequency Limit load capacitance Topr −20 − 85 °C FSCLK − 1.0 − MHz CL − − 0.1 µF Please set to VCC ≥ VDD. 1/6 BH2221FV Standard ICs !Block diagram 20 GND AO4 3 R-2R DAC AO5 4 R-2R DAC 8bitREG + DEC AO6 5 R-2R DAC 8bitREG + DEC AO7 6 R-2R DAC 8bitREG + DEC AO8 7 R-2R DAC 8bitREG + DEC AO9 8 R-2R DAC 8bitREG + DEC AO10 9 VDD 10 VCC 19 AO2 R-2R DAC 18 AO1 16 CLK Serial interface 15 LD POWER_ON RESET 8bitREG + DEC VCC 8bitREG + DEC 8bitREG + DEC R-2R DAC 17 DI VCC VDD VDD VCC VCC R-2R DAC 8bitREG + DEC 8bitREG + DEC VCC 8bitREG + DEC R-2R DAC VCC 2 8bitREG + DEC 14 NC R-2R DAC 13 AO12 VCC AO3 VDD 1 VDD NC R-2R DAC 12 AO11 11 VCC !Pin descriptions Pin No. Pin name In / Out Functions 1 NC − 2 AO3 OUT 3 AO4 OUT 4 AO5 OUT 5 AO6 OUT 6 AO7 OUT 7 AO8 OUT 8 AO9 OUT 9 AO10 OUT 10 VDD − 11 VCC − 12 AO11 OUT 13 AO12 OUT 14 NC − No connected 15 LD IN Serial Load input pin 16 CLK IN Serial Clock input pin 17 DI IN Serial Data input pin 18 AO1 OUT 19 AO2 OUT 20 GND − No connected Analog output pins Power supply pin Power supply pin Analog output pins Analog output pins Common GND pin 2/6 BH2221FV Standard ICs !Electrical characteristics (unless otherwise noted, Ta=25°C, VCC=3.0V, VDD=3.0V, RL=OPEN, CL=0pF) Parameter Symbol Min. Typ. Max. Unit VCC system ICC − 0.6 1.5 mA VDD system IDD − 1.0 2.0 mA Conditions <Operating current> (80H set) CLK=1MHz <Logic interface> Input low voltage VIL GND − 0.2VCC V Input high voltage VIH 0.8VCC − VCC V Input low current IIL − − 10 µA Input high current IIH − − 10 µA ZS1 GND − 0.1 V 00H set IOH=0.0mA ZS2 GND − 0.2 V 00H set IOH=0.5mA ZS3 GND − 0.3 V 00H set IOH=1.0mA FS1 VCC −0.1 − VCC V FFH set IOL=0.0mA FS2 VCC −0.2 − VCC V FFH set IOL=0.5mA FS3 VCC −0.3 − VCC V FFH set IOL=1.0mA <Buffer amplifier> Minimum output voltage Maximum output voltage <DAC accuracy> Resolution RES − 8 − bit Differential nonlinearity error DNL −1.0 − 1.0 LSB Input code 02H~FDH Nonlinearity error INL −1.5 − 1.5 LSB Input code 02H~FDH !Circuit operation (1) Power on reset This LSI has a power on reset circuit that sets an analog output to low level in VCC power stand-up. Please be sure that the time constant meets below condition, because the output is undefined when VCC power stand up too rapidly. Parameter VCC supply voltage rise time Power on reset voltage Symbol Min. Typ. Max. Unit trVCC 10 − − ms VPOR − 1.9 − V Conditions VCC=0→2.7V 3/6 BH2221FV Standard ICs (2) Conditions of operating timing (unless otherwise noted,Ta=25°C, VCC=3.0V, VDD=3.0V) Symbol Min. Typ. Max. Unit CLK L level pulse width tCLKL 200 − − ns CLK H level pulse width tCLKH 200 − − ns tsDI 30 − − ns Parameter DI setup time DI hold time thDI 60 − − ns LD setup time tsLD 200 − − ns LD hold time thLD 100 − − ns LD "H" level pulse width tLDH 100 − − ns Analog output delay time tOUT − − 300 µs tCLKL Conditions CL=50pF, RL=10kΩ tCLKH CLK DI LAST DATA tsDI LD thDI tLDH thLD tsLD OUTPUT tOUT 4/6 BH2221FV Standard ICs (3) Command sending Control command is 3wire 12bit serial interface. (MSB first) Data is taken in with the rise edge of the CLK and output data is fixed in the LD high section. Data is maintained in the LD low section. LSB (LAST) MSB (FIRST) Data set D0 Channel select D8 D9 D10 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 0 0 0 0 0 0 0 0 GND 1 0 0 0 0 0 0 0 (VCC-GND) / 256×1 0 1 0 0 0 0 0 0 (VCC-GND) / 256×2 1 1 0 0 0 0 0 0 (VCC-GND) / 256×3 0 0 1 0 0 0 0 0 (VCC-GND) / 256×4 0 1 1 1 1 1 1 1 (VCC-GND) / 256×254 1 1 1 1 1 1 1 1 (VCC-GND) / 256×255 D11 •Data set Analog output voltage level •Channel select D8 D9 D10 D11 0 0 0 0 Don't Care 0 0 0 1 AO1 0 0 1 0 AO2 0 0 1 1 AO3 0 1 0 0 AO4 0 1 0 1 AO5 0 1 1 0 AO6 0 1 1 1 AO7 1 0 0 0 AO8 1 0 0 1 AO9 1 0 1 0 AO10 1 0 1 1 AO11 1 1 0 0 AO12 1 1 0 1 Don't Care 1 1 1 0 Don't Care 1 1 1 1 Don't Care Adress select 5/6 BH2221FV Standard ICs !Operation notes (1) Regarding to the DNL & INL This item is guaranteed under below condition. Input code 02H∼FDH (2) Regarding to the setting of the each voltage Set the VCC, VDD to become the following condition. When not satisfied, unnecessary current flows or D/A conversion is not correct. VCC ≥ VDD And the minimum output voltage of this LSI is fixed to the GND level. (3) Regarding to the power on reset function This function operates detecting the voltage level of the VCC. So, if the voltage level of the VCC become less than power on reset voltage when working, it is a possibility that the outputs become reset condition. !External dimensions (Units : mm) 11 0.3Min. 6.4±0.3 1.15±0.1 4.4±0.2 0.1 6.5±0.2 20 1 10 0.15±0.1 0.65 0.22±0.1 0.1 SSOP-B20 6/6