16Gb: x16 TwinDie DDR3L SDRAM

16Gb: x16 TwinDie DDR3L SDRAM
Description
TwinDie™ 1.35V DDR3L SDRAM
MT41K1G16 – 64 Meg x 16 x 2 Banks
Description
Options
Marking
• Configuration
– 64 Meg x 16 x 8 banks x 2 ranks
• FBGA package (Pb-free)
– 96-ball FBGA
(9.5mm x 14mm x 1.2mm)
• Timing – cycle time1
– 1.071ns @ CL = 13 (DDR3L-1866)
– 1.25ns @ CL = 11 (DDR3L-1600)
• Operating temperature
– Commercial (0°C ≤ T C ≤ 95°C)
– Industrial (-40°C ≤ T C ≤ 95°C)
• Revision
The 16Gb (TwinDie™) 1.35V DDR3L SDRAM uses two
Micron 8Gb DDR3L SDRAM x16 die for essentially two
ranks of 8Gb DDR3L SDRAM. Refer to Micron’s 8Gb
DDR3L SDRAM base part number MT41K512M16
(monolithic) data sheet for the specifications not included in this document.
Features
• Uses two 8Gb x16 Micron die in one package
• Two ranks (includes dual CS#, ODT, CKE, and ZQ
balls)
• VDD = V DDQ = 1.35V (1.283–1.425V); backward compatible to 1.5V operation
• 1.35V center-terminated push/pull I/O
• JEDEC-standard ballout
• Low-profile package
• TC of 0°C to 95°C
– 0°C to 85°C: 8192 refresh cycles in 64ms
– 85°C to 95°C: 8192 refresh cycles in 32ms
Note:
1G16
DGA
-107
-125
None
IT
:A
1. CL = CAS (READ) latency.
Table 1: Key Timing Parameters
Speed Grade
Data Rate (MT/s)
Target tRCD-tRP-CL
-1071
1866
13-13-13
13.91
13.91
13.91
-125
1600
11-11-11
13.75
13.75
13.75
Note:
tRCD
tRP
(ns)
(ns)
CL (ns)
1. Backward compatible to 1600, CL = 11 (-125).
Table 2: Addressing
Parameter
1 Gig x 16
Configuration
64 Meg x 16 x 8 banks x 2 ranks
Refresh count
8K
Row address
64K A[15:0]
Bank address
8 BA[2:0]
Column address
1K A[9:0]
Page size
2KB
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© 2014 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.
16Gb: x16 TwinDie DDR3L SDRAM
Description
FBGA Part Marking Decoder
Due to space limitations, FBGA-packaged components have an abbreviated part marking that is different from the
part number. Micron’s FBGA part marking decoder is available at www.micron.com/decoder.
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16Gb: x16 TwinDie DDR3L SDRAM
Ball Assignments and Descriptions
Ball Assignments and Descriptions
Figure 1: 96-Ball FBGA – x16 (Top View)
1
2
3
VDDQ
DQ13
VSSQ
4
5
6
7
8
9
DQ15
DQ12
VDDQ
VSS
VDD
VSS
UDQS#
DQ14
VSSQ
VDDQ
DQ11
DQ9
UDQS
DQ10
VDDQ
VSSQ
VDDQ
UDM
DQ8
VSSQ
VDD
VSS
VSSQ
DQ0
LDM
VSSQ
VDDQ
VDDQ
DQ2
LDQS
DQ1
DQ3
VSSQ
VSSQ
DQ6
LDQS#
VDD
VSS
VSSQ
VREFDQ
VDDQ
DQ4
DQ7
DQ5
VDDQ
ODT1
VSS
RAS#
CK
VSS
CKE1
ODT0
VDD
CAS#
CK#
VDD
CKE0
CS1#
CS0#
WE#
A10/AP
ZQ0
ZQ1
VSS
BA0
BA2
A15
VREFCA
VSS
VDD
A3
A0
A12/BC#
BA1
VDD
VSS
A5
A2
A1
A4
VSS
VDD
A7
A9
A11
A6
VDD
VSS
RESET#
A13
A14
A8
VSS
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
Note:
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1. Dark balls (with rings) designate balls that differ from the monolithic versions.
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16Gb: x16 TwinDie DDR3L SDRAM
Ball Assignments and Descriptions
Table 3: 96-Ball FBGA – x16 Ball Descriptions
Symbol
Type
Description
A[15:13], A12/BC#,
A11, A10/AP, A[9:0]
Input
Address inputs: Provide the row address for ACTIVATE commands, and the column
address and auto precharge bit (A10) for READ/WRITE commands, to select one
location out of the memory array in the respective bank. A10 sampled during a
PRECHARGE command determines whether the PRECHARGE applies to one bank
(A10 LOW, bank selected by BA[2:0]) or all banks (A10 HIGH). The address inputs also
provide the op-code during a LOAD MODE command. Address inputs are referenced
to VREFCA. A12/BC#: When enabled in the mode register (MR), A12 is sampled during
READ and WRITE commands to determine whether burst chop (on-the-fly) will be
performed (HIGH = BL8 or no burst chop, LOW = BC4). See Truth Table – Command in
the DDR3 SDRAM data sheet.
BA[2:0]
Input
Bank address inputs: BA[2:0] define the bank to which an ACTIVATE, READ,
WRITE, or PRECHARGE command is being applied. BA[2:0] define which mode
register (MR0, MR1, MR2, or MR3) is loaded during the LOAD MODE command.
BA[2:0] are referenced to VREFCA.
CK, CK#
Input
Clock: CK and CK# are differential clock inputs. All control and address input signals
are sampled on the crossing of the positive edge of CK and the negative edge of
CK#. Output data strobe (DQS, DQS#) is referenced to the crossings of CK and CK#.
CKE[1:0]
Input
Clock enable: CKE enables (registered HIGH) and disables (registered LOW) internal
circuitry and clocks on the DRAM. The specific circuitry that is enabled/disabled is dependent upon the DDR3 SDRAM configuration and operating mode. Taking CKE
LOW provides PRECHARGE POWER-DOWN and SELF REFRESH operations (all banks
idle),or active power-down (row active in any bank). CKE is synchronous for powerdown entry and exit and for self refresh entry. CKE is asynchronous for self refresh
exit. Input buffers (excluding CK, CK#, CKE, RESET#, and ODT) are disabled during
POWER-DOWN. Input buffers (excluding CKE and RESET#) are disabled during SELF
REFRESH. CKE is referenced to VREFCA.
CS#[1:0]
Input
Chip select: CS# enables (registered LOW) and disables (registered HIGH) the
command decoder. All commands are masked when CS# is registered HIGH. CS# provides for external rank selection on systems with multiple ranks. CS# is considered
part of the command code. CS# is referenced to VREFCA.
LDM
Input
Input data mask: LDM is a lower-byte, input mask signal for write data. Lower-byte
input data is masked when LDM is sampled HIGH along with the input data during a
write access. Although the LDM ball is input-only, the LDM loading is designed to
match that of the DQ and DQS balls. LDM is referenced to VREFDQ.
ODT[0:1]
Input
On-die termination: ODT enables (registered HIGH) and disables (registered LOW)
termination resistance internal to the DDR3 SDRAM. When enabled in normal
operation, ODT is only applied to each of the following balls: DQ[15:0], LDQS,
LDQS#, UDQS, UDQS#, LDM, and UDM for the x16; DQ0[7:0], DQS, DQS#, DM/TDQS,
and NF/TDQS# (when TDQS is enabled) for the x8; DQ[3:0], DQS, DQS#, and DM for
the x4. The ODT input is ignored if disabled via the LOAD MODE command. ODT is
referenced to VREFCA.
RAS#, CAS#, WE#
Input
Command inputs: RAS#, CAS#, and WE# (along with CS#) define the command
being entered and are referenced to VREFCA.
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16Gb: x16 TwinDie DDR3L SDRAM
Ball Assignments and Descriptions
Table 3: 96-Ball FBGA – x16 Ball Descriptions (Continued)
Symbol
Type
Description
RESET#
Input
Reset: RESET# is an active LOW CMOS input referenced to VSS. The RESET# input receiver is a CMOS input defined as a rail-to-rail signal with DC HIGH ≥ 0.8 × VDD and
DC LOW ≤ 0.2 × VDDQ. RESET# assertion and de-assertion are asynchronous.
UDM
Input
Input data mask: UDM is an upper-byte input mask signal for write data. Upperbyte input data is masked when UDM is sampled HIGH along with that input data
during a WRITE access. Although the UDM ball is input-only, the UDM loading is
designed to match that of the DQ and DQS balls. UDM is referenced to VREFDQ.
DQ[7:0]
I/O
Data input/output: Lower byte of bidirectional data bus for the x16 configuration.
DQ[7:0] are referenced to VREFDQ.
DQ[15:8]
I/O
Data input/output: Upper byte of bidirectional data bus for the x16 configuration.
DQ[15:8] are referenced to VREFDQ.
LDQS, LDQS#
I/O
Lower byte data strobe: Output with read data. Edge-aligned with read data.
Input with write data. Center-aligned to write data.
UDQS, UDQS#
I/O
Upper byte data strobe: Output with read data. Edge-aligned with read data.
Input with write data. DQS is center-aligned to write data.
VDD
Supply
Power supply: 1.35V, 1.283–1.45V.
VDDQ
Supply
DQ power supply: 1.35V, 1.283–1.45V.
VREFCA
Supply
Reference voltage for control, command, and address: VREFCA must be
maintained at all times (including self refresh) for proper device operation.
VREFDQ
Supply
Reference voltage for data: VREFDQ must be maintained at all times (excluding self
refresh) for proper device operation.
VSS
Supply
Ground.
DQ ground: Isolated on the device for improved noise immunity.
VSSQ
Supply
ZQ[1:0]
Reference
External reference ball for output drive calibration: This lower byte ball is tied
to an external 240Ω resistor (RZQ), which is tied to VSSQ.
NC
–
No connect: These balls should be left unconnected (the ball has no connection to
the DRAM or to other balls).
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16Gb: x16 TwinDie DDR3L SDRAM
Functional Description
Functional Description
The TwinDie DDR3L SDRAM is a high-speed, CMOS dynamic random access memory
device internally configured as two 8-bank DDR3L SDRAM devices.
Although each die is tested individually within the dual-die package, some TwinDie test
results may vary from a like die tested within a monolithic die package.
The DDR3L SDRAM uses a double data rate architecture to achieve high-speed operation. The double data rate architecture is an 8n-prefetch architecture with an interface
designed to transfer two data words per clock cycle at the I/O balls. A single read or
write access consists of a single 8n-bit-wide, one-clock-cycle data transfer at the internal DRAM core and eight corresponding n-bit-wide, one-half-clock-cycle data transfers
at the I/O balls.
The differential data strobe (DQS, DQS#) is transmitted externally, along with data, for
use in data capture at the DDR3L SDRAM input receiver. DQS is center-aligned with data for WRITEs. The read data is transmitted by the DDR3L SDRAM and edge-aligned to
the data strobes.
Read and write accesses to the DDR3L SDRAM are burst-oriented. Accesses start at a
selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVATE command, which is
then followed by a READ or WRITE command. The address bits registered coincident
with the ACTIVATE command are used to select the bank and row to be accessed. The
address bits (including CSn#, BAn, and An) registered coincident with the READ or
WRITE command are used to select the rank, bank, and starting column location for the
burst access.
This data sheet provides a general description, package dimensions, and the package
ballout. Refer to the Micron monolithic DDR3L data sheet for complete information regarding individual die initialization, register definition, command descriptions, and die
operation.
Industrial Temperature
The industrial temperature (IT) option, if offered, requires that the case temperature
not exceed –40°C or 95°C. JEDEC specifications require the refresh rate to double when
TC exceeds 85°C; this also requires use of the high-temperature self refresh option. Additionally, ODT resistance, IDD values, some IDD specifications and the input/output impedance must be derated when T C is < 0°C or > 95°C. See the DDR3 monolithic data
sheet for details.
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16Gb: x16 TwinDie DDR3L SDRAM
Functional Block Diagram
Functional Block Diagram
Figure 2: Functional Block Diagram (64 Meg x 16 x 8 Banks x 2 Ranks)
Rank 1
(64 Meg x 16 x 8 banks)
Rank 0
(64 Meg x 16 x 8 banks)
CS1#
RAS#
CKE1
CAS#
ODT1
WE#
CK
CK#
CS0#
CKE0
A[15:0],
BA[2:0]
ZQ1
ODT0
ZQ0
U/LDQS, U/LDQS#
DQ[15:0]
U/LDM
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16Gb: x16 TwinDie DDR3L SDRAM
Electrical Specifications
Electrical Specifications
Absolute Rating
Stresses greater than those listed may cause permanent damage to the device. This is a
stress rating only, and functional operation of the device at these or any other conditions outside those indicated in the device data sheet is not implied. Exposure to absolute maximum rating conditions for extended periods may adversely affect reliability.
Table 4: Absolute Maximum DC Ratings
Parameter
VDD supply voltage relative to VSS
Symbol
Min
Max
Units
Notes
VDD
–0.4
1.975
V
1
VDD supply voltage relative to VSSQ
VDDQ
–0.4
1.975
V
Voltage on any ball relative to VSS
VIN, VOUT
–0.4
1.975
V
Input leakage current
Any input 0V ≤ VIN ≤ VDD,
VREF pin 0V ≤ VIN ≤ 1.1V
(All other pins not under test = 0V)
II
–4
4
µA
VREF supply leakage current
VREFDQ = VDD/2 or VREFCA = VDD/2
(All other pins not under test = 0V)
IVREF
–2
2
µA
2
3, 4
Operating case temperature
Storage temperature
TC
0
95
°C
TSTG
–55
150
°C
1. VDD and VDDQ must be within 300mV of each other at all times, and VREF must not be
greater than 0.6 × VDDQ. When VDD and VDDQ are less than 500mV, VREF may be ≤ 300mV.
2. The minimum limit requirement is for testing purposes. The leakage current on the VREF
pin should be minimal.
3. MAX operating case temperature. TC is measured in the center of the package (see the
Temperature Test Point Location figure).
4. Device functionality is not guaranteed if the DRAM device exceeds the maximum TC during operation.
Notes:
Input/Output Capacitance
The lump capacitance values are not listed. Simulations should use actual models and
not lumped capacitance.
Temperature and Thermal Impedance
It is imperative that the DDR3L SDRAM device’s temperature specifications, shown in
the following table, be maintained in order to ensure the junction temperature is in the
proper operating range to meet data sheet specifications. An important step in maintaining the proper junction temperature is using the device’s thermal impedances correctly. Thermal impedances listed in the Thermal Characteristics table apply to the current die revision and packages.
Incorrectly using thermal impedances can produce significant errors. Read Micron
technical note TN-00-08, “Thermal Applications,” prior to using the values listed in the
thermal impedance table. For designs that are expected to last several years and require
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16Gb: x16 TwinDie DDR3L SDRAM
Electrical Specifications
the flexibility to use several DRAM die shrinks, consider using final target theta values
(rather than existing values) to account for increased thermal impedances from the die
size reduction.
The DDR3 SDRAM device’s safe junction temperature range can be maintained when
the T C specification is not exceeded. In applications where the device’s ambient temperature is too high, use of forced air and/or heat sinks may be required to satisfy the
case temperature specifications.
Table 5: Thermal Characteristics
Notes 1–3 apply to entire table
Parameter
Symbol
Value
Units
TC
0 to 85
°C
0 to 95
°C
Operating temperature
Notes
4
1. MAX operating case temperature TC is measured in the center of the package, as shown
below.
2. A thermal solution must be designed to ensure that the device does not exceed the
maximum TC during operation.
3. Device functionality is not guaranteed if the device exceeds maximum TC during
operation.
4. If TC exceeds 85°C, the DRAM must be refreshed externally at 2x refresh, which is a 3.9µs
interval refresh rate. The use of self refresh temperature (SRT) or automatic self refresh
(ASR) must be enabled.
Notes:
Figure 3: Temperature Test Point Location
Test point
Length (L)
0.5 (L)
0.5 (W)
Width (W)
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16Gb: x16 TwinDie DDR3L SDRAM
Electrical Specifications
Table 6: Thermal Impedance
ΘJA (°C/W)
Airflow =
0m/s
ΘJA (°C/W)
Airflow =
1m/s
ΘJA (°C/W)
Airflow =
2m/s
ΘJB (°C/W)
ΘJC (°C/W)
Notes
Low
conductivity
45.2
34.4
30.6
NA
3.0
1
High
conductivity
27.6
22.5
20.8
11
NA
Die
Rev.
Package
Substrate
A
96-ball
Note:
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DDR3L_16Gb_x16_2CS_TwinDie.pdf - Rev. B 03/15 EN
1. Thermal resistance data is based on a number of samples from multiple lots and should
be viewed as a typical number.
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16Gb: x16 TwinDie DDR3L SDRAM
Electrical Specifications – ICDD Parameters
Electrical Specifications – ICDD Parameters
Table 7: DDR3L ICDD Specifications and Conditions (Die Revision A)
Combined
Symbol
Individual
Die Status
Bus
Width
-125
-107
Units
ICDD0
ICDD0 =
IDD0 + IDD2P0 + 5
x16
83
85
mA
ICDD1
ICDD1 =
IDD1 + IDD2P0 + 5
x16
104
107
mA
ICDD2P0 (slow exit)
ICDD2P0 =
IDD2P0 + IDD2P0
x16
22
22
mA
ICDD2P1 (fast exit)
ICDD2P1 =
IDD2P1 + IDD2P0
x16
25
27
mA
ICDD2Q
ICDD2Q =
IDD2Q + IDD2P0
x16
45
47
mA
ICDD2N
ICDD2N =
IDD2N + IDD2P0
x16
47
49
mA
ICDD2N T
ICDD2NT =
IDD2NT + IDD2P0
x16
51
53
mA
ICDD3P
ICDD3P = IDD3P + IDD2P0
x16
47
49
mA
ICDD3N
ICDD3N =
IDD3N + IDD2P0
x16
62
64
mA
ICDD4R
ICDD4R =
IDD4R + IDD2P0 + 5
x16
201
211
mA
ICDD4W
ICDD4W =
IDD4W + IDD2P0 + 5
x16
201
211
mA
ICDD5B
ICDD5B =
IDD5B + IDD2P0
x16
256
261
mA
ICDD6
(room temperature)
ICDD6 =
IDD6 + IDD6
x16
48
48
mA
ICDD6ET
(extended temperature)
ICDD6ET =
IDD6ET + IDD6ET
x16
68
68
mA
ICDD7
ICDD7 =
IDD7 + IDD2P0 + 5
x16
236
246
mA
ICDD8
ICDD8 = 2 × IDD2P0 + 4
x16
26
26
mA
Note:
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1. ICDD values reflect the combined current of both individual die. IDDx represents individual die values.
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16Gb: x16 TwinDie DDR3L SDRAM
Package Dimensions
Package Dimensions
Figure 4: 96-Ball FBGA – Die Revision A (Package Code DGA)
Seating plane
A
96X Ø0.47
Dimensions apply
to solder balls postreflow on Ø0.42 SMD
ball pads.
0.1 A
Ball A1 ID
(covered by SR)
9 8 7
Ball A1 ID
3 2 1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
14 ±0.1
12 CTR
0.8 TYP
1.1 ±0.1
0.8 TYP
6.4 CTR
0.29 MIN
9.5 ±0.1
Notes:
1. All dimensions are in millimeters.
2. Solder ball material: SAC302 (96.8% Sn, 3% Ag, 0.2% Cu).
8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-4000
www.micron.com/products/support Sales inquiries: 800-932-4992
Micron and the Micron logo are trademarks of Micron Technology, Inc. TwinDie is a trademark of Micron Technology, Inc.
All other trademarks are the property of their respective owners.
This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein.
Although considered final, these specifications are subject to change, as further product development and data characterization sometimes occur.
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