2Gb: x4, x8 TwinDie DDR2 SDRAM Functionality TwinDie™ DDR2 SDRAM MT47H512M4 – 32 Meg x 4 x 8 Banks x 2 Ranks MT47H256M8 – 16 Meg x 8 x 8 Banks x 2 Ranks For the latest component data sheet, refer to Micron’s Web site: www.micron.com Functionality Options The 2Gb (TwinDie™) DDR2 SDRAM uses Micron’s 1Gb DDR2 monolithic die and, therefore, has similar functionality. This TwinDie data sheet is intended to provide a general description, package dimensions, and the ballout only. Refer to the Micron 1Gb DDR2 data sheet for complete information regarding individual die initialization, register definition, command descriptions, and die operation. • Configuration – 32 Meg x 4 x 8 banks x 2 ranks – 16 Meg x 8 x 8 banks x 2 ranks • FBGA package (lead-free) – 63-ball FBGA (8mm x 10mm) • Timing – cycle time1 – 2.5ns @ CL = 5 (DDR2-800) – 3.0ns @ CL = 5 (DDR2-667) • Self refresh – Standard • Operating temperature – Commercial (0°C ≤ TC ≤ 85°C) – Industrial (–40°C ≤ TC ≤ 95°C; –40°C ≤ TA ≤ 85°C) • Revision Features • Uses 1Gb Micron die • Two ranks (includes dual CS#, ODT, and CKE balls) • Each rank has 8 internal banks for concurrent operation • VDD = VDDQ = +1.8V ±0.1V • JEDEC-standard 63-ball ballout • Low-profile package size (1.2mm MAX thickness) Table 1: Marking 512M4 256M8 THN -25E -3 None None IT :H Notes: 1. CL = CAS (READ) latency Key Timing Parameters Data Rate (MT/s) Speed Grade CL = 5 CL = 4 CL = 3 (ns) tRP (ns) tRC (ns) tRFC CL = 6 -25E -3 – – 800 667 533 533 – 400 12.5 15 12.5 15 55 55 127.5 127.5 Table 2: tRCD (ns) Addressing Parameter Refresh count Row address Bank address Configuration Column address Rank address PDF: 09005aef83fa94e3/Source: 09005aef8266ac6e 2Gb_twindie_H.fm - Rev. B 7/10 EN 256 Meg x 8 512 Meg x 4 8K 16K A[13:0] 8 BA[2:0] 16 Meg x 8 x 8 x 2 1K A[9:0] 2 CS#[1:0] 8K 16K A[13:0] 8 BA[2:0] 32 Meg x 4 x 8 x 2 2K A[9:0], A11 2 CS#[1:0] 1 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2010 Micron Technology, Inc. All rights reserved. Products and specifications discussed herein are subject to change by Micron without notice. 2Gb: x4, x8 TwinDie DDR2 SDRAM Ball Assignments and Descriptions Ball Assignments and Descriptions Figure 1: 63-Ball FBGA Assignments – x4, x8 (Top View) 1 2 3 4 5 6 7 VDD NF, NU/RDQS# VSS VSSQ 8 9 A DQS#/NU VDDQ B NF, DQ6 VSSQ DM, DM/RDQS DQS VSSQ NF, DQ7 VDDQ DQ1 VDDQ VDDQ DQ0 VDDQ NF, DQ4 VSSQ DQ3 DQ2 VSSQ NF, DQ5 VDDL VREF VSS VSSDL CK VDD CKE0 WE# RAS# CK# ODT0 BA2 BA0 BA1 CAS# CS0# CS1# CKE1 A10 A1 A2 A0 VDD VSS A3 A5 A6 A4 ODT1 A7 A9 A11 A8 VSS A12 RFU RFU A13 C D E F G H J K L VDD Notes: PDF: 09005aef83fa94e3/Source: 09005aef8266ac6e 2Gb_twindie_H.fm - Rev. B 7/10 EN 1. The three balls with dots designate balls that differ from the monolithic versions. 2 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2010 Micron Technology, Inc. All rights reserved. 2Gb: x4, x8 TwinDie DDR2 SDRAM Ball Assignments and Descriptions Table 3: 63-Ball FBGA Ball Descriptions – x4, x8 Symbol Type Description A[13:0] Input BA[2:0] Input CK, CK# Input CKE[1:0] Input DM Input ODT[1:0] Input RAS#, CAS#, WE# CS#[1:0] Input Input DQ[3:0] DQ[7:0] DQS#, DQS I/O I/O I/O RDQS, RDQS# I/O VDD VDDL VDDQ VREF VSS VSSDL VSSQ NF NU Supply Supply Supply Supply Supply Supply Supply – – RFU – Address inputs: Provide the row address for ACTIVE commands, and the column address and auto precharge bit (A10) for READ/WRITE commands, to select one location out of the memory array in the respective bank. A10 sampled during a precharge command determines whether the PRECHARGE applies to one device bank (A10 LOW, device bank selected by BA[2:0]) or all device banks (A10 HIGH). The address inputs also provide the op-code during a LOAD MODE command. Bank address inputs: BA[2:0] define the bank to which an ACTIVE, READ, WRITE, or PRECHARGE command is being applied. BA[2:0] define which mode register (MR, EMR1, EMR2, and EMR3) is loaded during the LOAD MODE command. Clock: CK and CK# are differential clock inputs. All control, command, and address input signals are sampled on the crossing of the positive edge of CK and the negative edge of CK#. Clock enable: CKE enables (registered HIGH) and disables (registered LOW) the internal circuitry and clocks on the DDR2 SDRAM. Input data mask: DM is an input mask signal for write data. Input data is masked when DM is sampled HIGH, along with the input data, during a write access. DM is sampled on both edges of DQS. Although the DM balls are input-only, DM loading is designed to match that of the DQ and DQS balls. On-die termination: ODT enables (registered HIGH) and disables (registered LOW) termination resistance internal to the DDR2 SDRAM. When enabled in normal operation, ODT is applied only to the following balls: DQ, DQS, DQS#, and DM. The ODT input will be ignored if disabled via the LOAD MODE command. Command inputs: RAS#, CAS#, and WE# (along with CS#) define the command being entered. Chip select: CS# enables (registered LOW) and disables (registered HIGH) the command decoder. Data input/output: Bidirectional data bus for the x4 configuration. Data input/output: Bidirectional data bus for the x8 configuration. Data strobe: Output with read data. Edge-aligned with read data. Input with write data. Center-aligned with write data. DQS# is used only when differential data strobe mode is enabled via the LOAD MODE command. Redundant data strobe: For the x8 configuration only. RDQS is enabled/disabled via the LOAD MODE command to the extended mode register (EMR). When RDQS is enabled, RDQS is output with read data only and is ignored during write data. When RDQS is disabled, B3 becomes data mask (see DM ball). RDQS# is only used when both RDQS and the differential data strobe mode are enabled. Power supply: 1.8V ±0.1V. DLL power supply: 1.8V ±0.1V. DQ power supply: 1.8V ±0.1V. Isolated on the device for improved noise immunity. Reference voltage: VDD/2. Ground. DLL ground: Isolated on the device from Vss and Vssq. DQ ground: Isolated on the device for improved noise immunity. No function: These balls provide no functionality on the x4 configuration only. Not used: For the x8 configuration only. If EMR(E10) = 0, A2 is RDQS# and A8 is DQS#. If EMR(E10) = 1, then A2 and A8 are not used. Reserved for future use: Row address bits A14 and A15. PDF: 09005aef83fa94e3/Source: 09005aef8266ac6e 2Gb_twindie_H.fm - Rev. B 7/10 EN 3 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2010 Micron Technology, Inc. All rights reserved. 2Gb: x4, x8 TwinDie DDR2 SDRAM Functional Description Functional Description The 2Gb (TwinDie) DDR2 SDRAM is a high-speed, CMOS dynamic random access memory device that contains 2,147,483,648 bits and is internally configured as two 8-bank 1Gb DDR2 SDRAM devices. Although each die is tested individually within the dual-die package, some TwinDie test results may vary from a like die tested within a monolithic die package. Each DDR2 SDRAM die uses a double data rate architecture to achieve high-speed operation. The DDR2 architecture is essentially a 4n-prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O balls. A single read or write access consists of a single 4n-bit-wide, one-clock-cycle data transfer at the internal DRAM core and four corresponding n-bit-wide, one-half-clock-cycle data transfers at the I/O balls. Addressing of the TwinDie is identical to the monolithic device. Additionally, multiple chip selects select the desired rank. This TwinDie data sheet is intended to provide a general description, package dimensions, and the ballout only. Refer to the Micron 1Gb DDR2 data sheet for complete information regarding individual die initialization, register definition, command descriptions, and die operation. PDF: 09005aef83fa94e3/Source: 09005aef8266ac6e 2Gb_twindie_H.fm - Rev. B 7/10 EN 4 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2010 Micron Technology, Inc. All rights reserved. 2Gb: x4, x8 TwinDie DDR2 SDRAM Functional Block Diagrams Functional Block Diagrams Figure 2: Functional Block Diagram (32 Meg x 4 x 8 Banks x 2 Ranks) Rank 1 (32 Meg x 4 x 8 banks) Rank 0 (32 Meg x 4 x 8 banks) CS1# RAS# CKE1 CAS# ODT1 WE# CK CK# CS0# CKE0 A[13:0], BA[2:0] ODT0 DQS, DQS# DQ[3:0] DM Figure 3: Functional Block Diagram (16 Meg x 8 x 8 Banks x 2 Ranks) Rank 1 (16 Meg x 8 x 8 banks) Rank 0 (16 Meg x 8 x 8 banks) CS1# RAS# CKE1 CAS# ODT1 WE# CK CK# CS0# CKE0 A[13:0], BA[2:0] ODT0 DQS, DQS#, RDQS, RDQS# DQ[7:0] DM PDF: 09005aef83fa94e3/Source: 09005aef8266ac6e 2Gb_twindie_H.fm - Rev. B 7/10 EN 5 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2010 Micron Technology, Inc. All rights reserved. 2Gb: x4, x8 TwinDie DDR2 SDRAM Electrical Specifications Electrical Specifications Stresses greater than those listed may cause permanent damage to the device. This is a stress rating only, and functional operation of the devices at these or any other conditions outside those indicated in the device data sheet is not implied. Exposure to absolute maximum rating conditions for extended periods may adversely affect reliability. Table 4: Absolute Maximum Ratings Symbol Parameter Min Max Units Notes VDD VDDQ VDDL VIN, VOUT II VDD supply voltage relative to VSS VDDQ supply voltage relative to VSSQ VDDL supply voltage relative to VSSDL Voltage on any ball relative to VSS Input leakage current; Any input 0V ≤ VIN ≤ VDD (All other balls not under test = 0V) Output leakage current; 0V ≤ VOUT ≤ VDDQ; DQ and ODT are disabled VREF leakage current; VREF = valid VREF level –1.0 –0.5 –0.5 –0.5 –10 +2.3 +2.3 +2.3 +2.3 +10 V V V V µA 1 1, 2 1 3 –10 +10 µA –4 +4 µA IOZ IVREF Notes: 1. VDD, VDDQ, and VDDL must be within 300mV of each other at all times. 2. VREF ≤ 0.6 × VDDQ; however, VREF may be ≥ VDDQ provided that VREF ≤ 300mV. 3. Voltage on any I/O may not exceed voltage on VDDQ. Temperature and Thermal Impedance It is imperative that the DDR2 SDRAM device’s temperature specifications, shown in Table 5 on page 7, be maintained to ensure the junction temperature is in the proper operating range to meet data sheet specifications. An important step in maintaining the proper junction temperature is using the device’s thermal impedances correctly. Thermal impedances listed in Table 5 on page 7 apply to the current die revision and its packages. Incorrectly using thermal impedances can produce significant errors. Read Micron technical note TN-00-08: “Thermal Applications” prior to using the thermal impedances in Table 6 on page 7. For designs that are expected to last several years and require the flexibility to use several DRAM die shrinks, consider using final target theta values (rather than existing values) to account for increased thermal impedances from the reduction in die size. The DDR2 SDRAM device’s safe junction temperature range can be maintained when the TC specifications are not exceeded. In applications where the device’s ambient temperature is too high, use of forced air and/or heat sinks may be required to satisfy the case temperature specifications. PDF: 09005aef83fa94e3/Source: 09005aef8266ac6e 2Gb_twindie_H.fm - Rev. B 7/10 EN 6 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2010 Micron Technology, Inc. All rights reserved. 2Gb: x4, x8 TwinDie DDR2 SDRAM Electrical Specifications Table 5: Temperature Limits Symbol TSTG TC Parameter Min Max Units Notes Storage temperature Operating temperature – commercial –55 0 150 85 °C °C 1 2, 3 Notes: Table 6: 1. Maximum storage case temperature; TSTG is measured in the center of the package, as shown in Figure 4. This case temperature limit is allowed to be exceeded briefly during package reflow, as noted in technical note TN-00-15: “Recommended Soldering Parameters,” available on Micron’s Web site. 2. Maximum operating case temperature; TC is measured in the center of the package, as shown in Figure 4. 3. Device functionality is not guaranteed if the device exceeds maximum TC during operation. Thermal Impedance Die Rev Package H 63-ball θ JA (°C/W) θ JA (°C/W) θ JA (°C/W) Substrate Airflow = 0m/s Airflow = 1m/s Airflow = 2m/s θ JB (°C/W) 2-layer 4-layer Notes: Figure 4: 71.8 54.1 54.3 44.8 48.3 41.3 35.3 34.9 θ JC (°C/W) Notes 5.5 1 1. Thermal resistance data is based on a number of samples from multiple lots and should be viewed as a typical number. Temperature Test Point Location Test point Length (L) 0.5 (L) 0.5 (W) Width (W) Lmm x Wmm FBGA PDF: 09005aef83fa94e3/Source: 09005aef8266ac6e 2Gb_twindie_H.fm - Rev. B 7/10 EN 7 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2010 Micron Technology, Inc. All rights reserved. 2Gb: x4, x8 TwinDie DDR2 SDRAM Electrical Specifications ICDD Specifications and Conditions Table 7: DDR2 ICDD Specifications and Conditions Notes: 1–8 apply to the entire document; notes appear on page 9 Parameter/Condition Operating one bank active-precharge current: tCK = tCK (I ), tRC = tRC (I ), tRAS = tRAS MIN (I ); CKE is DD DD DD HIGH, CS# is HIGH between valid commands; Address bus inputs are switching; Data bus inputs are switching (inactive die is in IDD2P condition, but with inputs switching) Operating one bank active-read-precharge current: IOUT = 0mA; Burst length (BL) = 4, CL = CL (IDD), AL = 0; tCK = tCK (I ), tRC = tRC (I ), tRAS = tRAS MIN (I ), DD DD DD t RCD = tRCD (IDD); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are switching; Data pattern is the same as IDD4W (inactive die is in IDD2P condition, but with inputs switching) Precharge power-down current: All banks idle; tCK = tCK (IDD); CKE is LOW; Other control and address bus inputs are stable; Data bus inputs are floating Precharge quiet standby current: All banks idle; tCK = tCK (I ); CKE is HIGH, CS# is HIGH; Other control and DD address bus inputs are stable; Data bus inputs are floating Precharge standby current: All banks idle; tCK = tCK (IDD); CKE is HIGH, CS# is HIGH; Other control and address bus inputs are switching; Data bus inputs are switching (inactive die is in IDD2P condition, but with inputs switching) Active power-down current: All banks open; tCK = tCK (I ); CKE is LOW; Other control and address bus DD inputs are stable; Data bus inputs are floating (individual die status: ICDD3P = IDD3P + IDD2P) Active standby current: All banks open; tCK = tCK (IDD), tRAS = tRAS MAX (I ), tRP = tRP (I ); CKE is HIGH, CS# is DD DD HIGH between valid commands; Other control and address bus inputs are switching; Data bus inputs are switching (inactive die is in IDD2P condition, but with inputs switching) Operating burst write current: All banks open; Continuous burst writes; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRAS = tRAS MAX (I ), tRP = tRP (I ); CKE is HIGH, CS# is DD DD HIGH between valid commands; Address bus inputs are switching; Data bus inputs are switching (inactive die is in IDD2P condition, but with inputs switching) Operating burst read current: All banks open; Continuous burst reads; IOUT = 0mA; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (I ), tRAS = tRAS MAX (I ), tRP = tRP (I ); CKE is DD DD DD HIGH, CS# is HIGH between valid commands; Address bus inputs are switching; Data bus inputs are switching (inactive die is in IDD2P condition, but with inputs switching) Burst refresh current: tCK = tCK (IDD); REFRESH command at every tRFC (IDD) interval; CKE is HIGH, CS# is HIGH between valid commands; Other control and address bus inputs are switching; Data bus inputs are switching (inactive die is in IDD2P condition, but with inputs switching) PDF: 09005aef83fa94e3/Source: 09005aef8266ac6e 2Gb_twindie_H.fm - Rev. B 7/10 EN 8 Combined Symbol Individual Die Status ICDD0 -25E -3 Units ICDD0 = IDD0 + IDD2P 72 67 mA ICDD1 ICDD1 = IDD1 + IDD2P 82 77 mA ICDD2P ICDD2P = IDD2P + IDD2P 14 14 mA ICDD2Q ICDD2Q = IDD2Q + IDD2P 31 31 mA ICDD2N ICDD2N = IDD2N + IDD2P 35 31 mA ICDD3P Fast PDN exit MR[12] = 0 Slow PDN exit MR[12] = 1 ICDD3N = IDD3N + IDD2P 27 22 mA 17 17 mA 40 37 mA ICDD4W ICDD4W = IDD4W + IDD2P 132 127 mA ICDD4R ICDD4R = IDD4R + IDD2P 122 117 mA ICDD5 ICDD5 = IDD5 + IDD2P 152 147 mA ICDD3N Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2010 Micron Technology, Inc. All rights reserved. 2Gb: x4, x8 TwinDie DDR2 SDRAM Electrical Specifications Table 7: DDR2 ICDD Specifications and Conditions (continued) Notes: 1–8 apply to the entire document; notes appear on page 9 Parameter/Condition Self refresh current: CK and CK# at 0V; CKE ≤ 0.2V; Other control and address bus inputs are floating; Data bus inputs are floating Operating bank interleave read current: All banks interleaving reads; IOUT = 0mA; BL = 4, CL = CL (IDD), AL = tRCD (IDD) - 1 × tCK (IDD); tCK = tCK (IDD), tRC = tRC (IDD), tRRD = tRRD (I ), tRCD = tRCD (I ); CKE is HIGH, CS# is HIGH DD DD between valid commands; Address bus inputs are stable during deselects; Data bus inputs are switching (inactive die is in IDD2P condition, but with inputs switching) Notes: PDF: 09005aef83fa94e3/Source: 09005aef8266ac6e 2Gb_twindie_H.fm - Rev. B 7/10 EN Combined Symbol Individual Die Status -25E -3 Units ICDD6 ICDD6 = IDD6 + IDD6 14 14 mA ICDD7 ICDD7 = IDD7 + IDD2P 217 192 mA 1. ICDD/IDD specifications are tested after the device is properly initialized. 0°C ≤ TC ≤ +85°C. VDD = VDDQ = +1.8V ±0.1V; VDDL = +1.8V ±0.1V; VREF = VDDQ/2. 2. ICDD/IDD parameters are specified with ODT disabled. 3. Data bus consists of DQ, DM, DQS, DQS#, RDQS, and RDQS#. 4. ICDD/IDD values must be met with all combinations of EMR bits 10 and 11. 5. Definitions for Icdd/Idd conditions: 5a. LOW: VIN ≤ VIL(AC)max 5b. HIGH: VIN ≥ VIH(AC)min 5c. Stable: Inputs stable at a HIGH or LOW level 5d. Floating: Inputs at VREF = VDDQ/2 5e. Switching: Inputs changing between HIGH and LOW every other clock cycle (once per two clocks) for address and control signals 5f. Switching: Inputs changing between HIGH and LOW every other data transfer (once per clock) for DQ signals, not including masks or strobes 6. IDD1, IDD4R, and IDD7 require EMR1, A12 to be enabled during testing. 7. ICDD/IDD values reflect the combined current of both individual die. IDDX represents individual die values. 8. The following IDD values must be derated (IDD limits increase) on IT-option devices when operated outside of the range 0°C ≤ TC ≤ 85°C: 8a. When TC ≤ 0°C IDD2P and IDD3P(SLOW) must be derated by 4%; IDD4R and IDD5W must be derated by 2%; and IDD6 and IDD7 must be derated by 7% 8b. When TC ≥ 85°C IDD0, IDD1, IDD2N, IDD2Q, IDD3N, IDD3P(FAST), IDD4R, IDD4W, and IDD5W must be derated by 2%; IDD2P must be derated by 20%; IDD3P(SLOW) must be derated by 30%; and IDD6 must be derated by 80% (IDD6 will increase by this amount if TC < 85°C and the 2X refresh option is still enabled) 9 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2010 Micron Technology, Inc. All rights reserved. 2Gb: x4, x8 TwinDie DDR2 SDRAM Package Dimensions Package Dimensions Figure 5: 63-Ball FBGA Package Dimensions (Part Rev. H) 0.8 ±0.05 Seating plane 0.12 A 63X Ø0.45 Solder ball material: SAC305 (96.5% Sn, 3% Ag, 0.5% Cu). Dimensions apply to solder balls postreflow on Ø0.33 NSMD ball pads. A Ball A1 ID 9 8 7 3 2 Ball A1 ID 1 A B C D E 8 CTR F 10 ±0.1 G H J K 0.8 TYP L 0.8 TYP 1.2 MAX 6.4 CTR 0.25 MIN 8 ±0.1 Notes: 1. All dimensions are in millimeters. 8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900 www.micron.com/productsupport Customer Comment Line: 800-932-4992 Micron, the Micron logo, and TwinDie are trademarks of Micron Technology, Inc. All other trademarks are the property of their respective owners. This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein. Although considered final, these specifications are subject to change, as further product development and data characterization sometimes occur. PDF: 09005aef83fa94e3/Source: 09005aef8266ac6e 2Gb_twindie_H.fm - Rev. B 7/10 EN 10 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2010 Micron Technology, Inc. All rights reserved.