Crosstalk: A Challenge Overcome in Multi-Channel Long Reach 10Gb/s+ Serial Backplanes Bodhi Das, Xilinx ([email protected]) Roland Moedinger, ERNI ([email protected]) 2 Outline • Crosstalk • ERNI ERmet zeroXT connector • Xilinx Virtex-II Pro X FPGA – RocketIO X Transceiver Technology • Xilinx-ERNI backplane – – – – Architecture Details Passive Performance Active Performance with Tx only: Eye after channel Active Performance with both Tx and Rx: BER • Conclusion 3 Crosstalk 4 Crosstalk – A Challenge • Crosstalk can limit signal speed, esp. @4Gb/s+ • Crosstalk occurs when one signal couples with another • Wherever signal lines/pairs are very close to each other, it is a good candidate for crosstalk – – – – – Backplane connector pins, launch Silicon package pins Vias (in close proximity) in printed circuit boards Routes (in close proximity) in printed circuit boards Reflection due to impedance mismatch can cause crosstalk too • Improve all of the above 5 Crosstalk Details • Near End (NEXT) and Far End (FEXT) • FEXT is more significant – Cut down FEXT by adjusting the ratio of capacitive and inductive coupling • Pre-emphasis can magnify NEXT • Crosstalk depends on rise time • Different equalization schemes have different effect on crosstalk 6 Connector Technology: ERNI ERmet zeroXT ERmet zeroXT Shielding pins – Pin in Paste Signal pins – SMT 7 SMT / “Pin in Paste” soldering – ERmet zeroXT Signal pins 8 Signal pins Solder paste Shielding pins Termination to the board Cross section 9 Board Construction for SMT 0.1/4 mil 0.2/8 mil 0.15/ 6 mil Edge coupled stripline Layer 3 Layer 6 The traces are designed for 100 Ohm diff. Impedance. Copper layer thickness is 18 µm. Board material is Rogers 4350/4403 Contacts and Shielding – ERmet zeroXT unmated 10 mated Contact and Shielding Design Details – ERmet zeroXT Shielding details 11 Contact size ERmet zeroXT ERmet Intrinsic Crosstalk Measurement – ERmet zeroXT 12 Intrinsic Crosstalk Measurement – ERmet zeroXT 13 14 SMT Connector-Testboards Material FR4 Trace length 110 mm Trace width 0.2 mm / 8mil Microstripline technique. Measurement is done with Anritsu MP1763 B Bit Pattern generator and Agilent 86100 A TDR with a PRBS 2 exp 7 –1 signal. 15 Eye diagrams for row g-h 10 Gbit/s Max. Eye opening: 77 % 13.5 Gbit/s 60% 16 Impedance profile: ERmet zeroXT Row e-f Row g-h ERmet zeroXT Press-Fit: Stub Influence at 10Gb/s Max. Eye opening: 43% 2mm Stub on Daughtercard 17 67 % Without Stub. 18 S21 for 6 mil trace width Point to point connection 19 S21 for 10 mil tace width Point to point connection 20 Retention Force: Connector – Board F1 F5 F2 F3 F4 Force Location Force Sustained F1 1205 N F2 495 N F3 400 N F4 1197 N F5 880 N Connector is assembled on a FR4 testboard. Contacts are wired in a serial connection. Force is measured at the first interruption. zeroXT module with 40 Pin-in-paste and 80 SMT terminations. 21 Silicon Transceiver Technology: Xilinx RocketIO X in Virtex-II Pro X 22 Silicon Technology • Active transceiver chips are used to transmit and receive signals • Transceivers need to have signal compensation circuits to compensate for the loss incurred in passive channel • Compensation circuits are normally of two kinds: – “Pre”-emphasis on Transmit side – “Post”-equalization on Receive side – Various ways of doing both 23 Silicon Technology • RocketIO™ X transceiver in Virtex-II Pro™ X FPGA has programmable Tx pre-emphasis and Rx equalization – Can transmit and receive NRZ 10Gb/s+ signals on the same chip – Can compensate for a wide range of channel losses – Programmable Tx driver output swing as well – Elegant linear equalization – Low power silicon 24 Xilinx • • • • • • FPGA Up to 20 full-duplex 10G Serial RocketIO™ X transceivers (embedded) Up to 2 IBM® PowerPC® RISK Processor blocks (embedded) Based on Virtex-II Pro Platform FPGA technology LVDS I/O, SRAM, DSP, clk mgmt, etc. Up to 74448 logic cells and 33088 configurable logic blocks Compatible to SONET OC-48/192, PCI Express, Infiniband, XAUI (10GE and 10GFC), XFP (XFI), Xilinx Aurora, OIF CEI and UXPi™. • Numerous soft IP cores; built-in XBERT and ChipScope™ • 130nm standard CMOS process; flip-chip BGA package (1mm pitch) 25 RocketIO X Transceiver • • • • • • • • • First 10Gbps embedded transceiver in FPGA: available now! 2.488-10.3125 Gb/s serial NRZ signaling Programmable Tx output swing, Tx emp and linear Rx eq AC and DC coupling; 50 ohms on-chip termination 8B/10B and 64B/66B coding with Bypass option Monolithic clock synthesis and clock recovery system Various applications: backplane, chip-to-chip, chip-to-module, cable, … Worldwide RocketLABs for live customer demo and support Xilinx Design Services for help with backplane design, signal integrity 26 Xilinx Backplane Architecture 1.5" 3" 3" 3" 3" 3" 3" 22" Star Mesh Test structures all around 11" 27 Backplane Details • • • • • • • Rogers 4350 (Hybrid) and FR4 versions Area: 22” x 11” Thickness: 250mil for FR4, 200mil for Hybrid (Rogers) Total 22 layers: 8 sig, 10 gnd, 2 pwr, top, bottom ERNI ERmet zeroXT connector (SMT/ Pin-in-paste) Connectors every 3”, empty footprints every 1.5” 10 column zeroXT – 3 for switch cards (24 columns used) – 1 for all others 28 Backplane Details (contd.) • 3”, 4.5”, 6”, 7.5”, … 18”, 19.5” traces on backplane + 3” on Line Cards • 8 mil wide, 8 mil spaced differential stripline traces • 1 oz. (1.38mil thick) copper traces • Dual Star and Mesh routing configurations • Plated through hole (PTH) vias with and without backdrilling • Additional test structures (probe-accessible) • Manufactured in a high-volume third party backplane manufacturer’s facility: standard processing 29 Backplane Stack-Up • Similar for Rogers & FR4 • 22 Layers – 8 Signal, 10 Ground, 2 Power – Power layers to be FR4 – Rogers 4350/4403B pre-preg for hybrid backplane • Transmission line pairs – 1oz (1.38mil thick) copper – 8mil width – 8mil space • Dielectric thickness to vary depending on material – Detail stack-up shown in the paper • Backdrill to layers 6, 10, and 17 Layer # (from top) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 Value Top Ground Signal Ground Signal Ground Signal Ground Signal Ground Power Power Ground Signal Ground Signal Ground Signal Ground Signal Ground Bottom 30 Backplane Routing • Star architecture – – – – 2 switch card and 6 line card connectors 16 diff pairs for each length Total 16×6×2 = 192 pairs Lower 4 layers for outer switch card; upper 4 for inner • Mesh architecture – – – – – 7 line card connectors 2 diff pairs between each two connectors Total 7×(7-1) = 42 pairs Lower 4 signal layers used for mesh routing 2 of upper signal layers used for crosstalk test structures 31 Test Results / Measurement Data • Passive performance – S-parameters: both thru and crosstalk (NEXT, FEXT) • Obtain frequency response of passive channel • Insert S-parameters in simulation bench for complete channel simulation including Tx+pkg and Rx+pkg • Active performance with Tx only – Effect of Tx driver pre-emphasis on eye opening – Eye pattern after channel w/ and w/o crosstalk • Active performance with both Tx and Rx – Both Tx pre-emphasis and Rx equalization on – BER performance 32 Passive Performance 33 Backplane w/ Daughter Cards 34 20” FR4 BP + 6” FR4 DC + 2 0XT + 2 SMA Thru Insertion Loss (-15.4db @ 5GHz) Horizontal NEXT (-38.4db @ 5GHz) 35 20” FR4 BP + 6” FR4 DC + 2 0XT + 2 SMA Vertical NEXT (-40db @ 5GHz) Diagonal NEXT (-50db @ 5GHz) 36 20” Ro BP + 6” FR4 DC + 2 0XT + 2 SMA Thru Insertion Loss (-10.7db @ 5GHz) Horizontal NEXT (-34.5db @ 5GHz) 37 20” Ro BP + 6” FR4 DC + 2 0XT + 2 SMA Vertical NEXT (-45db @ 5GHz) Diagonal NEXT (-56.7db @ 5GHz) 38 Active Performance with Transmitter (Pre-emphasis only) 39 Thru + 7 FEXT Channels Thru Channel TX Daughtercard 1 TX MK322 Thru MK 322 0XT SIP 1000 Backplane Daughtercard 0XT SIP 1000 TX 7 Crosstalk Channels Eye after channel • Passive Channel: 20” FR4/Rogers BP + 6” FR4 (~3” each) DCs + 3” FR4 MK322 + 2 0XTs + 4 SMAs • Xilinx MK322 board seats Virtex-II Pro X FPGA • FPGA transmits 27-1 PRBS pattern • Pattern after the channel (eye) received by Agilent DCAj • Demo in booth# 112 DCAj DCA 40 Tx Output, No Pre-emphasis 41 29” FR4 + 2 0XT; No Pre-emphasis 42 Tx Output, w/ Pre-emphasis 29” FR4 + 2 0XT; w/ Pre-emphasis, w/o Xtalk 43 29” FR4 + 2 0XT; w/ Pre-emphasis, w/ 7 Channel FEXT 44 20” Rogers + 9” FR4 + 2 0XT; w/ Pre-emphasis, w/o Xtalk 45 20” Rogers + 9” FR4 + 2 0XT; w/ Pre-emphasis, w/ 7 channel FEXT 46 47 Active Performance with both Transmitter (Pre-emphasis) and Receiver (Equalization) 48 Thru + 7 FEXT Channels Thru Channel MK322 TX TX Thru 1 Daughtercard MK 322 0XT SIP 1000 TX 7 Crosstalk Channels Backplane Daughtercard 0XT SIP 1000 MK MK322 322 TX Thru RX TX DCA BERT LoopBack System BER • Passive Channel: 20” FR4 BP + 6” FR4 (~3” each) DCs + 6” FR4 (~3” each) MK322s + 2 0XTs + 6 SMAs + 2m coax • FPGA transmits 27-1 PRBS pattern • Data received at Rx looped back to Tx and sent out to Agilent 71612 BERT box • Better than 10-12 BER for 10Gb/s NRZ after 32” FR4 and 2 0XT and worst case crosstalk 49 Xilinx Minneapolis Lab Agilent 86100A DCA Agilent 81134ACl k Src Agilent 71612C BERT Rack 50 Conclusion • Importance of crosstalk in high-speed multi-channel signaling is highlighted • Manufacturability is addressed in design and process • Routing density / complexity and backplane size / thickness comparable to systems OEMs • It is established that a carefully designed backplane, with the right combination of active and passive technologies, can reliably transfer 10Gb/s NRZ data over 32” of FR4. • Open eyes are observed at the end of the channels comprising 20” of backplane (FR4 or Rogers) and 9” of additional FR4 on daughter cards and test boards.