EM4094 Data Sheet - EM Microelectronic

EM MICROELECTRONIC - MARIN SA
EM4094
Analog Front End Integrated Circuit for
13.56MHz RFID Base Station
General Description
Features
The EM4094 is an analogue front end for 13.56MHz RFID
reader systems. It is highly versatile so it can be used in
different reader systems having sub carrier frequencies
from 212kHz to 848kHz, hence covering ISO14443 and
ISO15693 standards.
The adaptability is achieved using a 3 wire serial interface
to program the system option bits.
The EM4094 operating voltage is comprised between 3.3V
and 5V.
The push-pull transmitter generates 200mW output RF
power into a 50 load. The output stage drivers are
capable of OOK or ASK modulation from 7% up to 30% of
AM modulation.
The EM4094 reader chip is available in SO16, TSSOP16,
TSSOP20 and SO20 package.











Applications



Low cost reader modules
Hand held reader





ISO15693 & ISO14443 type A standard compatibility
Optionally ISO14443 type B compliant
3.3V or 5V Power Supply (analogue and digital)
Antenna driver using OOK modulation, single or
double antenna drivers
Optionally ASK uplink modulation index adjustable
from 7% up to 30%
High output RF power of 200mW from 5V supply
Antenna short circuit protection
Multiple receiver inputs for high communication
reliability
848KHz BPSK internal decoder (ISO14443 type B
option only)
Multiple sub-carrier receiving compatibility
(212kHz, 424kHz and 848kHz)
Multiple sub-carrier coding compatibility
(Manchester, Miller, BPSK)
Built-in receive low-pass filter which cut-off frequencies
are selectable between 400kHz and 1MHz
Built-in receive high-pass filter cut-off frequency
selectable between 100kHz, 200kHz and 300kHz
Selectable receive gain from 0dB up to 40dB
Serial 3 pins interface for option selection
Power down mode controlled by the 3 wires SPI
Output Power: 200mW for SO20w and TSSOP-20
100mW for SO16w and TSSOP16

Operation temperature range -40C to +85C
Typical Application
VCC
VCC
DVDDA1
C10
1uF
VDD
C11
100nF
C9
100nF
AGD
C12
100nF
DVSS
VSS
C2
C1
L1
ANT1
C4
10pF
120pF
150pF
EN
1uH
DIN
C3
470pF
DOUT
Antenna
C5
47pF
C6
10nF
RFIN1
DOUT1
RFIN2
DCLK
OSCIN
C7
22pF
MCU INTERFACE
OSCOUT
13.56MHz
C8
22pF
Figure 1
Copyright  2014, EM Microelectronic-Marin SA
4094-DS, Version 6.0, 12-Dec-14
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EM4094
TABLE OF CONTENTS
1. BLOCK DIAGRAM ............................................................................................................................................ 3
2. HANDLING PROCEDURES ............................................................................................................................. 3
3. ABSOLUTE MAXIMUM RATINGS ................................................................................................................... 3
3.1 Absolute Maximum Ratings .................................................................................................................................................................... 3
3.2 Operating Conditions .............................................................................................................................................................................. 4
3.3 Electrical Characteristics – VDD = 5V ..................................................................................................................................................... 4
3.4 Timing Characteristics ............................................................................................................................................................................ 5
4. FUNCTIONAL DESCRIPTION .......................................................................................................................... 6
4.1 Power Supply (VDD & VSS) ................................................................................................................................................................... 6
4.2 Power management................................................................................................................................................................................ 6
4.3 Driver Power Supply (VDDA1, VSSA1 & VDDA2, VSSA2) ..................................................................................................................... 6
4.4 Band-Gap reference ............................................................................................................................................................................... 6
4.5 Internal Oscillator .................................................................................................................................................................................... 6
4.6 Antenna drivers ...................................................................................................................................................................................... 6
4.7 Modulator ............................................................................................................................................................................................... 6
4.8 Receiver ................................................................................................................................................................................................. 7
4.9 BPSK Decoder (ISO14443 Type B device version) ................................................................................................................................. 7
4.10 AGC system ......................................................................................................................................................................................... 8
4.11 Serial Interface ..................................................................................................................................................................................... 8
5. OPTION BITS .................................................................................................................................................... 9
6. APPLICATION INFORMATION ...................................................................................................................... 11
6.1 Oscillator .............................................................................................................................................................................................. 11
6.2 Antenna driver ...................................................................................................................................................................................... 11
6.3 Receiver ............................................................................................................................................................................................... 11
6.4. Option bits selection depending transponder IC ................................................................................................................................... 11
6.5 Antenna connection configurations ....................................................................................................................................................... 12
7. PIN CONFIGURATION……………………………………………………………………………………………… 15
8. PIN DESCRIPTION ......................................................................................................................................... 14
9. PACKAGE INFORMATION ............................................................................................................................ 15
9.1 TSSO16 – TSSOP20 Package dimensions .......................................................................................................................................... 15
9.2 SO16 and SO20 Package dimensions .................................................................................................................................................. 16
10. ORDERING INFORMATION ......................................................................................................................... 17
11. PRODUCT SUPPORT ................................................................................................................................... 17
Copyright  2014, EM Microelectronic-Marin SA
4094-DS, Version 6.0, 12-Dec-14
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EM4094
1. Block Diagram
OSCOUT
TT
EN
OSCIN
TRANSMITTER
DOUT1
SERIAL INTERFACE
VDDA1
OSCILLATOR
ANT1
DOUT
OPTION BITS
&
I/O MULTIPLEX
ANTENNA
DRIVER
DCLK
DIN
VSSA1
MODULATOR
BPSK
DECODER
VSSA2
VDD
VSS
ANT2
ANTENNA
DRIVER
BAND GAP
REFERENCE
VDDA2
RFIN2
DEMODULATOR
RFIN1
FILTER &
GAIN
STAGES
AGD
COMPARATOR
RECEIVER CHAIN
Figure 2
Note: BPSK decoder functionality only available on ISO14443 Type B version. In standard version, BPSK decoder is deactivated.
2. Handling Procedures
This device has built-in protection against high static
voltages or electric fields; however, anti-static precautions
must be taken as for any other CMOS component. Unless
otherwise specified, proper operation can only occur when
all terminal voltages are kept within the voltage range.
Unused inputs must always be tied to a defined logic
voltage level.
3. Absolute Maximum Ratings
3.1 Absolute Maximum Ratings
VSS = 0V
Parameters
Maximum voltage at VDD
Minimum voltage at VDD
Max. voltage other pads
Min. voltage other pads
Max. junction temperature
Storage temperature range
Electrostatic discharge max. to MIL-STD-883 method 3015 ref VSS
Electrostatic discharge max. to MIL-STD-883 method 3015 for pins
ANT1 & ANT2
Maximum Input / Output current on all pads except VDD, VDDA1,
VDDA2, VSS, VSSA1, VSSA2, ANT1 and ANT2
Maximum AC peak current on VDDA1, VDDA2, VSSA1, VSSA2,
ANT1 and ANT2 pads at 13MHz, duty cycle 50% (per antenna
driver)
Symbol
VVDDMAX
VVDDMIN
VMAX
VMIN
TJMAX
TSTO
VESD
Conditions
VVSS+6V
VVSS-0.3V
VVDD+0.3V
VVSS-0.3V
+125°C
-50 to +150°C
2KV
VESDANT
4KV
IIMAX
IOMAX
10mA
IANTMAX
100mA
Table 1
Stresses above these listed maximum ratings may cause
permanent damages to the device. This is a stress rating
only and functional operation of the device at these or at
any other conditions above those indicated in the operation
Copyright  2014, EM Microelectronic-Marin SA
4094-DS, Version 6.0, 12-Dec-14
section of this specification is not implied. Exposure
beyond specified operating conditions may affect device
reliability or cause malfunction.
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EM4094
3.2 Operating Conditions
Parameters
Power supply voltage (5V)
Power supply voltage (3.3V)
Operating junction temperature
Package Thermal resistor for SO16W (note 1)
Package Thermal resistor for TSSOP16 (note1)
Package Thermal resistor for SO20W (note 1)
Package Thermal resistor for TSSO20 (note 1)
Load impedance on ANT1 or ANT2 output
drivers
Quartz load capacitors (note 2)
Capacitors VDDA1, VSSA1 filtering (note 2)
Capacitors VDDA2, VSSA2 filtering (note 2)
Capacitors VDD, VSS filtering (note 2)
AGD filtering capacitors (note 2)
Symbol
VVDD
VVDD
TJ
RthJ-A
RthJ-A
RthJ-A
RthJ-A
Min.
4.5
3.3
-40
Typ.
5
Max.
5.5
3.6
+110
Units
V
V
°C
C/W
C/W
C/W
C/W
65
89
55
73.2
(7+j0) 
ZANT
C1 & C2
C7, C8 & C10
C5, C6 & C9
C11 & C12
C13
2 x 22pF
1nF, 100nF and 10F connected in parallel
1nF, 100nF and 10F connected in parallel
1nF, 100nF connected in parallel
100nF (optional 1nF in parallel)
Table 2
Note 1: No fan convection, reader chip mounted on a multi layer PCB.
The maximum operating temperature is calculated with the following formula:
Ta = (RTHja * P) - Tjmax
Tj: maximum junction temperature, Ta: ambient temperature
Note 2:
 For the capacitors, refer to the Typical Application schematic on the first page of the datasheet.
 The Quartz load capacitors are in COG ceramic technology (5%)
 Use COG ceramic technology (5%) for the 1nF capacitors.
 Use X7R ceramic technology (10%) for the 100nF capacitors.
 Use tantalum electrolytic technology for the 10F capacitors.
The package thermal resistors are based on a multi-layer test board and zero airflow. The package performance is highly
dependent on board and environmental conditions.
3.3 Electrical Characteristics – VDD = 5V
Unless otherwise specified: VVSS = VVSSA1 = VVSSA2 = 0V & VVDD = VVDDA1 = VVDDA2 = 5V, TJ= -40 to +110°C.
Parameters
Symbol
Test Conditions
Min
Typ
Max
General DC parameters
Supply current in power-down
IPD
1
5
mode
Supply current excluding antenna
Option bits value:
ION
12
20
driver current
04800001 (Hexa)
VAGD
AGD level
2.3
2.5
2.7
Power on reset level
VPOR
1.4
2.1
3.6
Antenna Drivers
IANT = 100mA
ANT1 (or ANT2) driver output
RAD
3
7
12
impedance
100% modulation index
IANT = 100mA
ANT1 (or ANT2) driver output
RAD
5
10
15
impedance
10% modulation index
Serial Interface
VIL
Input logic low
0.2VDD
VIH
Input logic high
0.8VDD
VOH
ISOURCE = 1mA
Output logic high
0.9VDD
VOL
ISINK = 1mA
Output logic low
0.1VDD
Maximum serial interface clock
Fmax
1
frequency
AM demodulation
RF amplitude at RFIN inputs
VRFIN
2.5
VVDD
RFIN input resistance
RRFIN
5
10
20
Receiver sensitivity @ 212kHz
(note 3)
1.5
3
Receiver sensitivity @ 424kHz
(note 3)
2.2
4.5
Receiver sensitivity @ 848kHz
VSENS
(note 3)
3.5
6
Units
µA
mA
V
V


V
V
V
V
MHz
VPP
k
mVpp
mVpp
mVpp
Table 3.a
Note 3: Sine wave envelope, max. gain, RF amplitude in VRFIN
Copyright  2014, EM Microelectronic-Marin SA
4094-DS, Version 6.0, 12-Dec-14
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EM4094
Electrical Characteristics – VDD = 3.3V
Unless otherwise specified: VVSS = VVSSA1 = VVSSA2 = 0V & VVDD = VVDDA1 = VVDDA2 = 3.3V, TJ= -40 to +110°C.
Parameters
Symbol
Test Conditions
Min
Typ
Max
Units
General DC parameters
Option bits value:
04800001 (Hexa)
Supply current excluding antenna
Includes also current in
ION
8.5
12
mA
driver current
the external 1.8k ohms +/
5% resistor connected on
AGD output
1.8k Ohms external
VAGD
AGD level
0.7
1.3
1.6
V
resistor on AGD
Power on reset level
VPOR
2.1
V
Antenna Drivers
IANT = 100mA
ANT1 (or ANT2) driver output
RAD
4
9.3
15

impedance
100% modulation index
IANT = 30mA
ANT1 (or ANT2) driver output
RAD
5
11
20

impedance
10% modulation index
Serial Interface
VIL
Input logic low
0.2VDD
V
VIH
Input logic high
0.8VDD
V
VOH
ISOURCE = 1mA
Output logic high
0.9VDD
V
VOL
ISINK = 1mA
Output logic low
0.1VDD
V
Maximum serial interface clock
Fmax
1
MHz
frequency
AM demodulation
RF amplitude at RFIN inputs
VRFIN
1.65
VVDD
VPP
RFIN input resistance
RRFIN
5
11.5
20
k
Receiver sensitivity @ 212kHz
(note 3)
4
mVpp
Receiver sensitivity @ 424kHz
(note 3)
6
mVpp
Receiver sensitivity @ 848kHz
VSENS
(note 3)
10
mVpp
Table 3.b
Note 3: Sine wave envelope, max. gain, RF amplitude in VRFIN
3.4 Timing Characteristics
Unless otherwise specified: VVSS = VVSSA1 = VVSSA2 = 0V & VVDD = VVDDA1 = VVDDA2 = 5V, TJ= -40 to +110°C.
Parameters
Xtal Oscillator
Symbol
Transconductance
gm
Set-up time after power down
AM demodulation
Recovery time of reception after
antenna modulation
Tset
Test Conditions
Min
Typ
Max
Units
Normal mode (note 4)
Hi oscillator mode (note 4)
Normal mode (note 5)
Hi oscillator mode (note 5)
0.3
1.5
0.1
0.8
0.9
2.7
0.45
2
5
1.6
4.0
1
3
15
mS
mS
mS
mS
Ms
Trec
100
µs
Table 4
Note 4: It is recommended to use the high gm transconductance.
Crystal electrical parameters:
 Quality factor min: 26000
 Series resistance typ: 20
 Static capacitance typ: 2.8pF
Note 5: gm transconductance for a VDD of 3.3 volts
Copyright  2014, EM Microelectronic-Marin SA
4094-DS, Version 6.0, 12-Dec-14
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EM4094
It is also possible to apply an external clock source, DC
coupled to OSCIN, according to Vi input levels, to drive the
internal oscillator.
When option bit 27 is set, OSCIN corresponds to the digital
input of the internal oscillator.
The oscillator start-up time can be decreased by setting
option bit 26 (oscillator gain).
4. Functional Description
The EM4094 Analog Front End can be adapted to any kind of
reader system using the 31 option bits.
The option bits chapter gives a global view and specifies all of the
reader chip options.
4.1 Power Supply (VDD & VSS)
The EM4094 analogue front end can operate at 3.3V or 5V. The
power supply voltage has to be the same on the analogue and
digital input lines (VDD, VDDA1, VDDA2).
It is strongly recommended to use a regulated supply. Power
supply ripples and noise, inside the receiver frequency range,
degrades the overall system performances.
To use the EM4094 at 3.3V, an external resistor has to be
connected on the AGD output to fix a voltage of 2.0V on AGD.
The external resistor can be switched off (using for example a
microcontroller I/O) when the reader chip is not used.
4.6 Antenna drivers
The antenna driver produces the RF signal from the
oscillator output. The PMOS and NMOS driver side are fed
by non-overlapping signals (3ns) to minimize the power
consumption.
The output resistance of each antenna driver is typically
7. Optionally, for ISO14443 Type B device version, It is
changed, during the field modulation, to set the right ASK
modulation index level (option bits 2, 3, 4).
The two integrated antenna drivers can be used in three
possible configurations depending on the output power
level (refer to application chapter on page 11).
When a single driver configuration is selected, the output
power level on the 50 load is 100mW.
For a 200mW output power, both drivers have to be used in
parallel configuration to double the output power (option bit
6).
The drivers can operate in push-pull configuration (option
bit 7). This mode can be used in case of direct antenna
connection. In that configuration, the reader antenna is
connected to the output drivers through a resonant
capacitor (LC tank adjusted to 13.56MHz)
Take note that, in direct antenna configuration, the output
power can exceed 200mW. Chip cooling requirements
must be carefully considered.
To be compliant with national country regulations, it could
be necessary to add a filtering structure between the IC
output stage drivers and the antenna. For more
information, please, refer to the product application note.
The short protection circuit (option bit 5) prevents damage
to the output driver when the ANT pin is shorted to ground
or to the power supply.
4.2 Power management
There are two available power modes. The selection of these
two modes is done with the Power up Flag (option bit 1).
There are two ways to put the EM4094 Analog Front End in
a power down state:
 Reseting the power up flag.
 Applying a low level on EN input. In that case, only the
analog circuitry goes to Power Down but the SPI
interface remains active.
When EN is changed to high (and power up flag is high)
the EM4094 goes immediately to the mode in which it was
before EN went low level.
In power-up mode, the oscillator is started followed by the
transmitter and the receiver. When the chip is ready to
operate (quartz oscillator, receiver operating points are
ready and transmitter is not shorted (if bit 5 is set) a 100s
ready pulse is generated on DOUT pin.
After that condition, the chip goes to normal operation
mode. DOUT corresponds to the demodulated signal
output and DOUT1 is the 13.56MHz-clock output
(Optionally, for ISO14443 Type B device version, DOUT1 is
used as BPSK clock output in ISO14443 type B standard).
4.7 Modulator
The modulator enables OOK or ASK modulation of the RF
signal on the antenna outputs (ANT1 and ANT2).
The ASK possibility is only available on the ISO14443 Type
B device version
4.3 Driver Power Supply (VDDA1, VSSA1 & VDDA2,
VSSA2)
Supply lines should be separately filtered for analogue chip
supply and antenna driver supplies.
Any variations in supply voltage directly modulate the
antenna driver and they are fed to the receiver’s input.
The power supply sensitivity range, for frequency
components which are in the receiving bandwidth, is the
same as the RFIN sensitivity.
When the device is in normal mode, DIN corresponds to
the modulator input.
A high input level, on DIN input, causes a low field (ASK
modulation index) or a field-stop if OOK modulation is
chosen.
4.4 Band-Gap reference
The reference voltage (2.5V) is generated internally by a
Band-gap reference and uses an external capacitor for blocking.
4.5 Internal Oscillator
The oscillator is driven by the13.56MHz external crystal to
generate the RF frequency. The external quartz crystal is
connected to the load capacitors as indicated in Figure 1.
Copyright  2014, EM Microelectronic-Marin SA
4094-DS, Version 6.0, 12-Dec-14
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EM4094
These three bits define 8 gain settings according to the
option bit table. The total gain range is 40dB.
The output signal, in normal mode, can be a digitized subcarrier, a 106kbit/s BPSK decoded bit stream (DOUT) or an
analogue output used for DSP decoding (DOUT1).
When a direct sub-carrier signal is selected, the tag answer
is displayed on the DOUT pin. In such configuration,
DOUT1 corresponds to the 13.56MHz clock output, which
can be used for synchronization of an external microcontroller used for decoding.
4.9 BPSK Decoder (ISO14443 Type B device version)
The internal BPSK decoder is designed to decode the
transponder's sub-carrier signal according to the
ISO14443-type B coding procedure described in the ISO
14443-B standard.
Upper trace: digital input (DIN) modulation input
Lower trace: transmitted field on ANT1 for ie
Reader modulation is set to OOK (100% AM)
First 80 pulses are used as start of frame. The initial Phase
State of the sub-carrier is defined as logical "1" and the first
phase transition represents a change from logical "1" to
logical "0". The sub-carrier frequency is 13.56MHz divided
by 16 and each bit period consists of 8 pulses according to
ISO14443-B standard.
The BPSK decoder is enabled by setting to a high level
option bit 22. When this option bit is set, the decoded bitstream is available on pin DOUT and the bit clock on pin
DOUT1. The data is valid on the rising edge of bit clock.
Upper trace: digital input (DIN) modulation input
Lower trace: transmitted field on ANT1 for ie
Reader modulation is set to 16% ASK
The selection between OOK and ASK modulation depth is
done using configuration bits 2, 3 and 4.
The field modulation index can be adjusted from 7% up to
30% covering all the ISO standard air interface
requirements.
Before and after a modulation phase, the receiver input is
disconnected from the antenna circuitry to preserve DC
operating point setting.
For high quality factor systems, it may be necessary to
prolong (option bit 25) the hold time after modulation to
allow settling of the resonant circuit.
Upper trace: digital output (DOUT1) BPSK clock
Bottom trace: digital output (DOUT) BPSK decoded data
4.8 Receiver
The receiver senses the envelope of the signal present on
the inputs RFIN1 or RFIN2 (option bit 14). These two
inputs, used with external components, permit the detection
of amplitude or phase modulated signals.
The BPSK decoder decodes the transponder's signal,
which can have a frequency offset. The transponders clock
extractor can omit or add some clock transitions at
modulation.
Successful operation, in such conditions, requires a
frequency adaptive decoder. When option bit 23 is set, the
decoder measures the average frequency of the 80 pulses
(SOF) and adjusts the internal shift register to the
appropriate length.
The decoder is capable of correct operation at incoming bitstream frequencies of 847.5kHz +/-10%.
Any RF frequency components still present in the envelope
signal are removed by a second order low pass filter.
The received signal DC component is removed by the high
pass filter, which has selectable corner frequency (option
bits 8 and 9).
The signal is amplified and further processed by the low
pass filtering stage, which corner frequency is selectable
(option bit 10).
The gain selection (option bits 11, 12 and 13) should be
chosen according to the reader system parameters.
Modifying the signal bandwidth changes noise level and
results in different input sensitivity.
Copyright  2014, EM Microelectronic-Marin SA
4094-DS, Version 6.0, 12-Dec-14
When the internal BPSK decoder is not activated and
option bit 24 is set, DOUT1 corresponds to the output of
the AGC amplifier.
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EM4094
When AGC system is disabled the receiver gain is directly
controlled by option bits 11, 12, 13
4.10 AGC system
The integrated AGC system can be activated via option bit
15. The AGC amplifier has a 40dB gain correction depth.
The AGC system is adapted to all RFID communication
protocols.
Before the transponder starts to emit the data, the receiver
gain is set to maximum (option bits 11,12,13).
When the reader detects a transponder signal that is above
the attack threshold the receiver gain is rapidly reduced
(option bits 18 and19) to fit the signal into a linear range of
the receiver.
The gain remains unchanged as long as the signal level is
above the decay threshold.
4.11 Serial Interface
The serial interface is used to control the EM4094 option
bits setting.
A high level on DCLK and a rising edge on DIN reset the
serial interface. After the reset, the DIN signal is shifted to
the internal register on every rising edge on DCLK.
During first 31 DCLK transitions, the DIN data are read to
the chip while during the 32nd transition the chip exits the
SPI configuration mode and enters the normal mode.
In normal mode:
 DIN is used to modulate the field (high DIN: low reader
filed for ASK or no field for OOK).
 DCLK must be low in normal mode.
 DOUT and DOUT1 are data and clock outputs in
normal mode.
When the received signal falls below the decay threshold
for a period of time set by option bits 20 and 21, the reader
logic establishes that the communication with one
transponder is finished and makes a fast decay to return to
the maximum gain.
The receiver is ready to demodulate the emission of the
next transponder, which can be far away from the reader
antenna. This feature is necessary for anti-collision
purposes.
If the EM4094 reader chip was in power-down mode before
entering normal mode (option bit 1 low or pin EN low) the
IC goes through a start-up procedure.
This means that the quartz oscillator is started (or external
clock source is enabled), the output driver is enabled and
the antenna drivers are checked for short circuit (if bit 5 is
set).
After the operation point of the receiver has settled, the
DOUT pin goes high for 100s and then the chip goes to
normal mode.
If a short circuit at the antenna driver output is detected, the
antenna driver is stopped, DOUT remains low and DOUT1
goes high.
With transponders that have a modulation DC level shift
significantly higher than modulation sub-carrier AC level,
the AGC can react on DC shift and decrease the system
gain too much.
It is possible not to attack the first pulse (option bit 16) in a
burst (for OOK modulation) to allow the DC level to settle
before AGC action. The time after which the first pulse in a
burst is not attacked (shortest sub-carrier stop in OOK
modulation is 1/10 of the time) is set by option bits 20, 21
as decay wait time. It is also possible to use slow decay
mode (option bit 17). The slow decay is started when the
received signal falls below the decay threshold. The decay
rate is one gain step per time defined by option bits 20 and
21.
If the EM4094 reader IC was powered-up before SPI
communication was started it goes directly to the normal
mode.
DCLK
DIN
31 Option bits
DOUT &
DOUT1
Serial
Interface
reset
Selection Option bits mode
Normal
Mode
Figure 6
Copyright  2014, EM Microelectronic-Marin SA
4094-DS, Version 6.0, 12-Dec-14
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EM4094
5. Option Bits
The EM4094 selection bits are:

Bit 1
Power up flag

Bit 2
Modulation index selection 0

Bit 3
Modulation index selection 1

Bit 4
Modulation index selection 2

Bit 5
Short circuit protection enable

Bit 6
Single or dual RF driver selection

Bit 7

Bit 8
Dual driver in phase or phase
phase opposite
Filter zero selection 1

Bit 9
Filter zero selection 2

Bit 10
Filter low pass selection 400kHz

Bit 11
Receive gain selection 0 (LSB)

Bit 12
Receiver gain selection 1

Bit 13
Receiver gain selection 2 (MSB)

Bit 14
AM / PM input channel selection

Bit 15
AGC On/Off selection

Bit 16
AGC attack mode selection

Bit 17
AGC decay mode selection

Bit 18
AGC attack rate (lsb)

Bit 19
AGC attack rate (msb)

Bit 20
AGC decay wait (lsb)

Bit 21
AGC decay wait (msb)

Bit 22

Bit 23
Output selection: direct sub-carrier
or BPSK data stream (ISO14443-B)
BPSK automatic frequency adjust

Bit 24
Analogue output selection

Bit 25
Hold delay after modulation selection

Bit 26
Oscillator gain selection

Bit 27
External oscillator

Bit 28 -> 31 Must be set to low level
Copyright  2014, EM Microelectronic-Marin SA
4094-DS, Version 6.0, 12-Dec-14
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EM4094
Power up flag
Bit 1
Description
0
Power down
1
Power up
AGC on off selection
Bit 15
0
AGC off
1
AGC on
Output driver configuration
Modulation Index
Bit 4
Bit 3
Bit 2
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
AGC attack mode selection
Bit 16
Description
0
Attack always
1
First pulse not attacked
Description
10% ASK typ.
OOK
ASK decrease 3%
ASK decrease 1.5%
ASK increase 3%
ASK increase 6%
ASK increase 12%
ASK increase 20%
Note: ASK only available on ISO14443 Type B device version
Short Circuit Protection
Bit 5
Description
0
Short circuit protection disabled
1
Short circuit protection enabled
Single or dual RF driver selection
Bit 6
Description
0
ANT1 only
1
ANT1 and ANT2
Dual driver in phase or phase opposite
Bit 7
Description
0
In phase driving
1
Differential driving
Receiving Chain Configuration
Filter zero selection
Bit 9
Bit 8
Description
0
0
High int. zero (~300kHz)
0
1
Mid. int. zero (~200kHz)
1
0
Low int. zero (~100kHz)
Filter low pass selection 400kHz
Bit 10
Description
0
High cut-off frequency (~1 MHz)
1
Mid. cut-off frequency (~400 kHz)
Receive gain selection 0 (Lsb)
Bit 11
Description
0
Nominal gain
1
Gain decreased for 5.7dB
Receive gain selection 1
Bit 12
Description
0
Nominal gain
1
Gain decreased for 11.4dB
Receive gain selection 2 (Msb)
Bit 13
Description
0
Nominal gain
1
Gain decreased for 22.8dB
AM/PM input channel selection
Bit 14
Description
0
RFIN1 input selected
1
RFIN2 input selected
Copyright  2014, EM Microelectronic-Marin SA
4094-DS, Version 6.0, 12-Dec-14
AGC decay mode selection
Bit 17
0
Fast decay
1
Slow decay
Description
Description
AGC attack rate
Bit 19
Bit 18
0
0
0
1
1
0
Description
~19 dB/s (average)
~9.5 dB/s (average)
~4.7 dB/s (average)
AGC decay wait
Bit 21
Bit 20
0
0
0
1
1
0
Description
~44s
~88s
~176s
BPSK Decoder
Output selection direct sub-carrier or BPSK 848kHz
Bit 22
Description
0
Sub-carrier
1
BPSK decoder
Note: BPSK only available on ISO14443 Type B device version
BPSK automatic frequency adjust
Bit 23
Description
0
Disabled
1
Enabled
Output selection analogue
Bit 24
Description
0
Analogue output disabled
1
Analogue output enabled
Bit 25
0
1
Description
Hold delay after modulation ~5s
Hold delay after modulation ~15s
Oscillator
Oscillator gain selection
Bit 26
0
Low gm
1
High gm
Description
External oscillator selection
Bit 27
Description
0
Internal quartz oscillator
1
External oscillator
Note:
It is recommended to set option bits 16 up to bit 21 and
option bits 23, 25 to “0”. Bit 26 should be set to “1”.
10
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EM4094
6. Application information
6.1 Oscillator
The frequency range allowed by the regulations is
13.56MHz  7 kHz. The correct load capacitance has to be
chosen according to the manufacturer’s guideline. COG
capacitors should be used. It is not recommended to
connect any components except quartz crystal and load
capacitors to the oscillator’s pins since any interference or
noise injected into the oscillator corrupts the system
performance.
When an external clock source is used the phase noise of
the clock has to be kept low since it also corrupts the
system performances.
6.2 Antenna driver
The correct load impedance for a single output driver
(100mW) is 7 resistive. The correct load impedance for a
double parallel output driver (option bit 6, 200mW) is 3.5
resistive.
The load impedance for a push-pull driver (bits 6, 7) must
be at least 14 resistive. In this configuration, the
consideration of chip power dissipation and junction
temperature is necessary. It is also possible to use this
configuration for low power systems with a direct antenna
connection if a load impedance higher than 14 is used.
Since the ASK modulation index is dependent on the load,
it will differ from those listed in the table.
6.3 Receiver
Systems using a 212kHz sub-carrier modulation should
use the medium filter selection and systems using a 424
kHz or 848kHz sub-carrier should use the high frequency
filter selection. When a 424kHz or 848kHz system with
on/off sub-carrier coding is used, the higher frequency zero
enables very fast response of the receiver to the pulse
burst with high DC level shift. When a BPSK system is
used, lower frequency zero decreases phase distortion of
the BPSK signal.
System option bits control the receiver gain. Different
receiver bandwidths result in different noise levels
therefore enabling different gain and sensitivity levels. The
combination of filter selection and gain selection allows the
system designer to choose the best combination for the
RFID reader.
For ISO15693 standard:
Option bit Suggested value
1
1
2,3,4
1,0,0
5
1
6,7
1,0
8,9
0,0
10
0
11,12,13
0,0,0
14
0
15
1
16 -> 21
0,0,0,0,0,0
22
0
23
0
24
0
25
0
26
1
27
0
28 -> 31
0,0,0,0
Configuration
Power up
OOK modulation
Short circuit enabled
Two drivers in phase
300kHz
1MHz
Nominal gain
RFIN1 selected
AGC activated
Standard configuration
Sub-carrier mode
BPSK not used
Analogue output disable
Hold delay set to 5us
High gm
Internal quartz
Normal IC mode
Tag sub-carrier: 424kHz or 484kHz
Modulation Index: 100%
Reception bandwidth: 300kHz – 1MHz
AGC: Nominal Gain
Configuration word value (Hexa): (msb) 02 00 40 33 (lsb)
For ISO14443 Type A standard:
Suggested
Option bit
value
1
1
6.4. Option bits selection depending transponder IC
The EM4094 transceiver is compliant with almost all
13.56MHz transponder ICs. The large combinations offered
by the EM4094 option bits permit to adapt the reader IC to
the tag communication protocol.
The below tables give the suggested option bit
configuration depending on the transponder IC used.
Configuration
Power up
2,3,4
5
1,0,0
1
OOK modulation
Short circuit enabled
6,7
8,9
1,0
0,0
Two drivers in phase
300kHz
10
11,12,13
0
0,0,0
14
15
0
1
16 -> 21
22
23
0,0,0,0,0,0
0
0
24
0
25
0
Analogue output
disable
Hold delay set to 5us
26
27
1
0
High gm
Internal quartz
28 -> 31
0,0,0,0
1MHz
Nominal gain
RFIN1 selected
AGC activated
Standard configuration
Sub-carrier mode
BPSK not used
Normal IC mode
Tag sub-carrier: 848kHz
Modulation Index: 100%
Reception bandwidth: 300kHz – 1MHz
AGC: Nominal Gain
Configuration word value (Hexa): (msb) 02 00 40 33 (lsb)
Copyright  2014, EM Microelectronic-Marin SA
4094-DS, Version 6.0, 12-Dec-14
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EM4094
For ISO14443 Type B standard:
Suggested
Option bit
value
1
1
Tag sub-carrier: 848kHz
Modulation Index: 10%
Reception bandwidth: 300kHz – 1MHz
AGC: Nominal Gain
Configuration word value (Hexa): (msb) 02 20 40 31 (lsb)
Configuration
Power up
2,3,4
5
0,0,0
1
10% ASK
Short circuit enabled
6,7
8,9
1,0
0,0
Two drivers in phase
300kHz
10
11,12,13
0
0,0,0
14
15
0
1
16 -> 21
22
23
0,0,0,0,0,0
0
0
24
0
25
0
Analogue output
disable
Hold delay set to 5us
26
27
1
0
High gm
Internal quartz
28 -> 31
0,0,0,0
1MHz
Nominal gain
RFIN1 selected
AGC activated
Standard configuration
Sub-carrier mode
BPSK selected
Normal IC mode
6.5 Antenna connection configurations
Single Output Driver (100mW)
VCC
VCC
VDDA1
C10
C8
VDD
C7
C12
VSSA1
C11
VSS
VCC
AGD
VDDA2
C13
C9
C5
C6
EM4094
VSSA2
EN
ANTENNA
DI N
L1
COAX
ANT1
DCLK
ANT2
DOUT
C3
uController
Interface
DOUT1
RFIN2
RFIN1
OSCOUT
C4
OSCI N
Y1
C1
C2
Figure 7
Copyright  2014, EM Microelectronic-Marin SA
4094-DS, Version 6.0, 12-Dec-14
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EM4094
Double parallel output driver (option bit 6, 200mW)
VCC
VCC
VDDA1
C10
C8
VDD
C7
C12
VSSA1
C11
VSS
VCC
AGD
VDDA2
C13
C9
C5
C6
EM4094
VSSA2
EN
ANTENNA
DIN
L1
COAX
ANT1
DCLK
ANT2
DOUT
C3
uController
Interface
DOUT1
RFIN2
RFIN1
OSCOUT
C4
OSCIN
Y1
C2
C1
Figure 8
Configuration for lower power systems with direct antenna connection
V CC
V CC
V DDA 1
C 10
C8
V DD
C7
C 12
VSSA1
C 11
VSS
V CC
A GD
V DDA 2
C 13
C9
C6
C5
EM4094
VSSA2
EN
D IN
L1
A N T1
C3
uController
D C LK
Interface
D OU T
C 14
A N T2
D OU T1
R FIN 1
R FIN 2
OS C OU T
C4
OS C IN
Y1
C1
C2
Figure 9
In such a configuration, the resonant frequency of the external LC tank has to be tuned accurately to 13.56MHz. The resonant
capacitor is composed by C14 in parallel with the capacitor divider (C3 and C4).
Copyright  2014, EM Microelectronic-Marin SA
4094-DS, Version 6.0, 12-Dec-14
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EM4094
7. Pin configuration
OSCIN
1
20
VDD
OSCOUT
2
19
EN
VDDA1
3
18
NC
ANT1
4
17
NC
VSSA1
5
16
AGD
VSSA2
6
15
VSS
ANT2
7
14
DOUT1
VDDA2
8
13
DOUT
RFIN2
9
12
DCLK
RFIN1
10
11
DIN
EM4094
SO20 or
TSSOP20
OSCIN
1
16
VDD
OSCOUT
2
15
EN
VDDA
3
14
AGD
ANT
4
13
VSS
VSSA
5
12
DOUT1
NC
6
11
DOUT
RFIN2
7
10
DCLK
RFIN1
8
9
EM4094
SO16 or
TSSOP16
DIN
Figure 10
The selection of the package SO16, TSSOP16, TSSOP20 or SO20 depends on the output power level.
8. Pin description
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Name
OSCIN
OSCOUT
VDDA1
ANT1
VSSA1
VSSA2
ANT2
VDDA2
RFIN2
RFIN1
DIN
DCLK
DOUT
DOUT1
VSS
AGD
NC
NC
EN
VDD
Description
Quartz oscillator input (no internal capacitor)
Quartz oscillator output (no internal capacitor)
Positive supply for antenna driver 5V
RF output (10 output impedance)
Negative supply for antenna driver 0V
Negative supply for antenna driver 0V
RF output (10 output impedance)
Positive supply for antenna driver 5V
RF input PM (maximum 5Vpp, DC coupled to AGD)
RF input AM (maximum 5Vpp, DC coupled to AGD)
SPI Data input / field modulation input
SPI Data clock
Digitized receive output / BPSK bit stream output
BPSK bit clock output / Analogue receive output
Negative supply 0V
Reference voltage output 2.5V
Not used
Not used
Enable input
Positive supply 5V
Table 5
The functionality of pins 13 and 14 is controlled via SPI interface depending on the system demands.
For SO16 and TSSOP16 versions, pins VSSA2, ANT2, VDDA2 are omitted.
All the pins marked NC should be connected to VSS.
Copyright  2014, EM Microelectronic-Marin SA
4094-DS, Version 6.0, 12-Dec-14
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EM4094
9. Package Information
9.1 TSSO16 – TSSOP20 Package dimensions
Figure 11
DIMENSION IN MM
SYMBOL
MIN.
NOM.
A
DIMENSION IN INCH
MAX.
MIN.
NOM.
MAX.
1.2
A1
0.05
A2
0.8
b
0.19
D (TSSOP16)
4.9
D (TSSOP20)
6.4
.047
0.15
.002
1.05
.031
0.3
.007
5
5.1
.193
.197
.2
6.5
6.6
.252
.256
.26
0.9
.006
.035
.041
.012
e
0.65 BSC.
.026 BSC.
E
6.40 BSC.
.252 BSC.
E1
4.3
4.4
4.5
.169
.173
.177
Table 6
Copyright  2014, EM Microelectronic-Marin SA
4094-DS, Version 6.0, 12-Dec-14
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EM4094
9.2 SO16 and SO20 Package dimensions
Figure 12
DIMENSION IN MM
SYMBOL
MIN.
NOM.
DIMENSION IN INCH
MAX.
MIN.
NOM.
MAX.
A
2.35
2.65
.093
.104
A1
0.10
0.30
.004
.012
D (SO16)
10.10
10.50
.398
.413
D (SO20)
12.60
13.00
.496
.512
e
1.27 BSC.
.050 BSC.
E
7.4
7.6
0.291
.299
H
10.00
10.65
.394
.419
Table 7
Copyright  2014, EM Microelectronic-Marin SA
4094-DS, Version 6.0, 12-Dec-14
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EM4094
10. Ordering Information
EM4094 V1 TP 16
A
Circuit Nb:
EM4094
Version:
“ “ = ISO15693 & ISO14443 A&B
V1 = ISO15693 & ISO14443 A compliant
Delivery Format:
A = Stick
B = Tape & Reel
Package
SO
TP = TSSOP
Nbr of pads
16
20
Standard Versions:
The versions below are considered standards and should be readily available. For the other delivery form, please contact EM
Microelectronic-Marin S.A. Please make sure to give the complete part number when ordering.
Part Number
EM4094TP16B+
EM4094SO20A+
EM4094V1TP16B+
EM4094V1SO20A+
Package
TSSOP 16
SO20
TSSOP 16
SO20
Delivery Format
Tape & Reel
Stick
Tape & Reel
Stick
ISO Standard
ISO15693 & ISO14443 A&B
ISO15693 & ISO14443 A&B
ISO15693 & ISO14443 A
ISO15693 & ISO14443 A
Table 8
Optional Versions:
The versions below are considered optional. For the other delivery form, please contact EM Microelectronic-Marin S.A. Please
make sure to give the complete part number when ordering.
Part Number
EM4094TP16A+
EM4094SO20B+
Package
TSSOP 16
SO20
Delivery Format
Stick
Tape & Reel
ISO Standard
ISO15693 & ISO14443 A&B
ISO15693 & ISO14443 A&B
Table 9
EM4094V2 with ISO/IEC 14443 type B functionality is licensed under Innovatron’s Contactless Card patents license for ISO/IEC
14443 B standard.
RATP/Innovatron Technology
12. Product Support
Check our web site under Products/RF Identification section. Questions can be sent to [email protected]
EM Microelectronic-Marin SA (“EM”) makes no warranties for the use of EM products, other than those expressly contained in EM's applicable
General Terms of Sale, located at http://www.emmicroelectronic.com. EM assumes no responsibility for any errors which may have crept into
this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any
commitment to update the information contained herein.
No licenses to patents or other intellectual property rights of EM are granted in connection with the sale of EM products, neither expressly nor
implicitly.
In respect of the intended use of EM products by customer, customer is solely responsible for observing existing patents and other intellectual
property rights of third parties and for obtaining, as the case may be, the necessary licenses.
Important note: The use of EM products as components in medical devices and/or medical applications, including but not limited to,
safety and life supporting systems, where malfunction of such EM products might result in damage to and/or injury or death of
persons is expressly prohibited, as EM products are neither destined nor qualified for use as components in such medical devices
and/or medical applications. The prohibited use of EM products in such medical devices and/or medical applications is exclusively at
the risk of the customer
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