Pin Information For The Stratix™ GX EP1SGX40D Device, ver 1.7 Bank Number B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 VREF Bank Pin Name/Function Optional Function(s) VREF0B2 VREF0B2 VREF0B2 VREF0B2 VREF0B2 VREF0B2 VREF0B2 VREF0B2 VREF0B2 VREF0B2 VREF0B2 VREF0B2 VREF0B2 VREF0B2 VREF0B2 VREF0B2 VREF0B2 VREF0B2 VREF0B2 VREF0B2 VREF0B2 VREF0B2 VREF0B2 VREF0B2 VREF0B2 VREF0B2 VREF0B2 VREF0B2 VREF0B2 VREF0B2 VREF0B2 VREF1B2 VREF1B2 VREF1B2 VREF1B2 VREF1B2 VREF1B2 VREF1B2 VREF1B2 VREF1B2 VREF1B2 VREF1B2 VREF1B2 VREF1B2 VREF1B2 VREF1B2 VCCA_PLL7 GND GNDA_PLL7 VCCG_PLL7 GNDG_PLL7 FPLL7CLKp FPLL7CLKn INPUT INPUT IO IO INPUT INPUT IO IO INPUT INPUT IO IO VREF0B2 INPUT INPUT IO IO INPUT INPUT IO IO INPUT INPUT IO IO INPUT INPUT IO IO INPUT INPUT IO IO INPUT INPUT IO IO INPUT INPUT IO IO INPUT INPUT IO Copyright © 2006 Altera Corp. Configuration Function F1020 DQS for x16 DQS for x32 J27 DIFFIO_RX44p DIFFIO_RX44n DIFFIO_TX44p DIFFIO_TX44n DIFFIO_RX43p DIFFIO_RX43n DIFFIO_TX43p DIFFIO_TX43n DIFFIO_RX42p DIFFIO_RX42n DIFFIO_TX42p DIFFIO_TX42n DIFFIO_RX41p DIFFIO_RX41n DIFFIO_TX41p DIFFIO_TX41n DIFFIO_RX40p DIFFIO_RX40n DIFFIO_TX40p DIFFIO_TX40n DIFFIO_RX39p DIFFIO_RX39n DIFFIO_TX39p DIFFIO_TX39n DIFFIO_RX38p DIFFIO_RX38n DIFFIO_TX38p DIFFIO_TX38n DIFFIO_RX37p DIFFIO_RX37n DIFFIO_TX37p DIFFIO_TX37n DIFFIO_RX36p DIFFIO_RX36n DIFFIO_TX36p DIFFIO_TX36n DIFFIO_RX35p DIFFIO_RX35n DIFFIO_TX35p DIFFIO_TX35n DIFFIO_RX34p DIFFIO_RX34n DIFFIO_TX34p Pin List (EP1SGX40D) K27 J26 K26 E29 E30 D29 D30 F27 F28 D31 D32 G27 G28 F29 F30 G25 G26 M24 E31 E32 J28 H28 F31 F32 H26 H27 G29 G30 H24 H25 G31 G32 L28 K28 H29 H30 J24 J25 K29 K30 K24 K25 H31 H32 L24 L25 J31 J32 L26 Page 1 of 34 Pin Information For The Stratix™ GX EP1SGX40D Device, ver 1.7 Bank Number VREF Bank Pin Name/Function Optional Function(s) B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 VREF1B2 VREF1B2 VREF1B2 VREF1B2 VREF1B2 VREF1B2 VREF1B2 VREF1B2 VREF1B2 VREF1B2 VREF1B2 VREF1B2 VREF1B2 VREF1B2 VREF1B2 VREF1B2 VREF1B2 VREF1B2 VREF2B2 VREF2B2 VREF2B2 VREF2B2 VREF2B2 VREF2B2 VREF2B2 VREF2B2 VREF2B2 VREF2B2 VREF2B2 VREF2B2 VREF2B2 VREF2B2 VREF2B2 VREF2B2 VREF2B2 VREF2B2 VREF2B2 VREF2B2 VREF2B2 VREF2B2 VREF2B2 VREF2B2 VREF2B2 VREF2B2 VREF2B2 VREF2B2 VREF2B2 VREF2B2 VREF2B2 VREF2B2 VREF2B2 IO VREF1B2 INPUT INPUT IO IO INPUT INPUT IO IO INPUT INPUT IO IO INPUT INPUT IO IO INPUT INPUT IO IO INPUT INPUT IO IO INPUT INPUT IO IO INPUT INPUT IO IO VREF2B2 INPUT INPUT IO IO INPUT INPUT IO IO INPUT INPUT IO IO CLK0n CLK0p IO CLK1p Copyright © 2006 Altera Corp. Configuration Function DIFFIO_TX34n DIFFIO_RX33p DIFFIO_RX33n DIFFIO_TX33p DIFFIO_TX33n DIFFIO_RX32p/RUP2 DIFFIO_RX32n/RDN2 DIFFIO_TX32p DIFFIO_TX32n DIFFIO_RX31p DIFFIO_RX31n DIFFIO_TX31p DIFFIO_TX31n DIFFIO_RX30p DIFFIO_RX30n DIFFIO_TX30p DIFFIO_TX30n DIFFIO_RX29p DIFFIO_RX29n DIFFIO_TX29p DIFFIO_TX29n DIFFIO_RX28p DIFFIO_RX28n DIFFIO_TX28p DIFFIO_TX28n DIFFIO_RX27p DIFFIO_RX27n DIFFIO_TX27p DIFFIO_TX27n DIFFIO_RX26p DIFFIO_RX26n DIFFIO_TX26p DIFFIO_TX26n DIFFIO_RX25p DIFFIO_RX25n DIFFIO_TX25p DIFFIO_TX25n DIFFIO_RX24p DIFFIO_RX24n DIFFIO_TX24p DIFFIO_TX24n DIFFIO_RX23p DIFFIO_RX23n DIFFIO_TX23p DIFFIO_TX23n CLK1n Pin List (EP1SGX40D) F1020 DQS for x16 DQS for x32 L27 P23 J29 J30 M25 M26 L29 L30 M27 M28 L31 L32 N25 N26 M29 M30 N27 N28 N29 N30 P25 P26 K31 K32 P24 R24 M31 M32 P27 P28 P29 P30 R27 R28 R23 N31 N32 R25 R26 P31 R31 K23 J23 R29 R30 M23 L23 T32 T31 T30 T29 Page 2 of 34 Pin Information For The Stratix™ GX EP1SGX40D Device, ver 1.7 Bank Number B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 VREF Bank Pin Name/Function Optional Function(s) VREF0B1 VREF0B1 VREF0B1 VREF0B1 VREF0B1 VREF0B1 VREF0B1 VREF0B1 VREF0B1 VREF0B1 VREF0B1 VREF0B1 VREF0B1 VREF0B1 VREF0B1 VREF0B1 VREF0B1 VREF0B1 VREF0B1 VREF0B1 VREF0B1 VREF0B1 VREF0B1 VREF0B1 VREF0B1 VREF0B1 VREF0B1 VREF0B1 VREF0B1 VREF0B1 VREF0B1 VREF0B1 VREF0B1 VREF1B1 VREF1B1 VREF1B1 VREF1B1 VREF1B1 VREF1B1 VREF1B1 VREF1B1 VCCA_PLL1 GND GNDA_PLL1 VCCG_PLL1 GNDG_PLL1 VCCA_PLL2 GND GNDA_PLL2 VCCG_PLL2 GNDG_PLL2 CLK2p CLK2n CLK3p IO INPUT INPUT IO IO INPUT INPUT IO IO INPUT INPUT IO IO VREF0B1 INPUT INPUT IO IO INPUT INPUT IO IO INPUT INPUT IO IO INPUT INPUT IO IO INPUT INPUT IO IO INPUT INPUT IO IO Copyright © 2006 Altera Corp. Configuration Function F1020 DQS for x16 DQS for x32 T27 T28 T25 T26 U27 CLK3n DIFFIO_RX22p DIFFIO_RX22n DIFFIO_TX22p DIFFIO_TX22n DIFFIO_RX21p DIFFIO_RX21n DIFFIO_TX21p DIFFIO_TX21n DIFFIO_RX20p DIFFIO_RX20n DIFFIO_TX20p DIFFIO_TX20n DIFFIO_RX19p DIFFIO_RX19n DIFFIO_TX19p DIFFIO_TX19n DIFFIO_RX18p DIFFIO_RX18n DIFFIO_TX18p DIFFIO_TX18n DIFFIO_RX17p DIFFIO_RX17n DIFFIO_TX17p DIFFIO_TX17n DIFFIO_RX16p DIFFIO_RX16n DIFFIO_TX16p DIFFIO_TX16n DIFFIO_RX15p DIFFIO_RX15n DIFFIO_TX15p DIFFIO_TX15n DIFFIO_RX14p DIFFIO_RX14n DIFFIO_TX14p DIFFIO_TX14n Pin List (EP1SGX40D) U28 U25 U26 U31 U32 U29 U30 V29 V30 T23 U24 V31 W31 AA23 AB23 Y31 Y32 AC23 AD23 V23 W29 W30 V27 V28 AA31 AA32 V25 V26 AC31 AC32 V24 W24 Y29 Y30 W27 W28 AB31 AB32 W25 W26 AA29 AA30 Y25 Y26 Page 3 of 34 Pin Information For The Stratix™ GX EP1SGX40D Device, ver 1.7 Bank Number VREF Bank Pin Name/Function Optional Function(s) B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 VREF1B1 VREF1B1 VREF1B1 VREF1B1 VREF1B1 VREF1B1 VREF1B1 VREF1B1 VREF1B1 VREF1B1 VREF1B1 VREF1B1 VREF1B1 VREF1B1 VREF1B1 VREF1B1 VREF1B1 VREF1B1 VREF1B1 VREF1B1 VREF1B1 VREF1B1 VREF1B1 VREF1B1 VREF1B1 VREF1B1 VREF1B1 VREF2B1 VREF2B1 VREF2B1 VREF2B1 VREF2B1 VREF2B1 VREF2B1 VREF2B1 VREF2B1 VREF2B1 VREF2B1 VREF2B1 VREF2B1 VREF2B1 VREF2B1 VREF2B1 VREF2B1 VREF2B1 VREF2B1 VREF2B1 VREF2B1 VREF2B1 VREF2B1 VREF2B1 INPUT INPUT IO IO INPUT INPUT IO IO VREF1B1 INPUT INPUT IO IO INPUT INPUT IO IO INPUT INPUT IO IO INPUT INPUT IO IO INPUT INPUT IO IO INPUT INPUT IO IO INPUT INPUT IO IO INPUT INPUT IO IO VREF2B1 INPUT INPUT IO IO INPUT INPUT IO IO INPUT Copyright © 2006 Altera Corp. Configuration Function DIFFIO_RX13p/RUP1 DIFFIO_RX13n/RDN1 DIFFIO_TX13p DIFFIO_TX13n DIFFIO_RX12p DIFFIO_RX12n DIFFIO_TX12p DIFFIO_TX12n DIFFIO_RX11p DIFFIO_RX11n DIFFIO_TX11p DIFFIO_TX11n DIFFIO_RX10p DIFFIO_RX10n DIFFIO_TX10p DIFFIO_TX10n DIFFIO_RX9p DIFFIO_RX9n DIFFIO_TX9p DIFFIO_TX9n DIFFIO_RX8p DIFFIO_RX8n DIFFIO_TX8p DIFFIO_TX8n DIFFIO_RX7p DIFFIO_RX7n DIFFIO_TX7p DIFFIO_TX7n DIFFIO_RX6p DIFFIO_RX6n DIFFIO_TX6p DIFFIO_TX6n DIFFIO_RX5p DIFFIO_RX5n DIFFIO_TX5p DIFFIO_TX5n DIFFIO_RX4p DIFFIO_RX4n DIFFIO_TX4p DIFFIO_TX4n DIFFIO_RX3p DIFFIO_RX3n DIFFIO_TX3p DIFFIO_TX3n DIFFIO_RX2p DIFFIO_RX2n DIFFIO_TX2p DIFFIO_TX2n DIFFIO_RX1p Pin List (EP1SGX40D) F1020 DQS for x16 DQS for x32 AB29 AB30 Y27 Y28 AC29 AC30 AA25 AA26 W23 AD31 AD32 AA27 AA28 AE31 AE32 AB26 AB27 AE29 AE30 AB24 AB25 AD29 AD30 AC24 AC25 AF29 AF30 AD24 AD25 AF31 AF32 AB28 AC28 AG31 AG32 AE24 AE25 AG29 AG30 AE26 AE27 AA24 AH31 AH32 AD28 AE28 AJ31 AJ32 AF25 AF26 AJ29 Page 4 of 34 Pin Information For The Stratix™ GX EP1SGX40D Device, ver 1.7 Bank Number VREF Bank Pin Name/Function Optional Function(s) B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 VREF2B1 VREF2B1 VREF2B1 VREF2B1 VREF2B1 VREF2B1 VREF2B1 VREF2B1 VREF2B1 VREF2B1 VREF2B1 INPUT IO IO INPUT INPUT IO IO FPLL8CLKn FPLL8CLKp IO IO VCCA_PLL8 GND GNDA_PLL8 VCCG_PLL8 GNDG_PLL8 IO IO IO IO IO IO IO IO IO IO VREF0B8 IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 VREF0B8 VREF0B8 VREF0B8 VREF0B8 VREF0B8 VREF0B8 VREF0B8 VREF0B8 VREF0B8 VREF0B8 VREF0B8 VREF0B8 VREF0B8 VREF0B8 VREF0B8 VREF0B8 VREF0B8 VREF0B8 VREF0B8 VREF0B8 VREF0B8 VREF0B8 VREF0B8 VREF0B8 VREF0B8 VREF0B8 VREF0B8 VREF1B8 VREF1B8 VREF1B8 VREF1B8 VREF1B8 VREF1B8 VREF1B8 VREF1B8 Copyright © 2006 Altera Corp. Configuration Function DIFFIO_RX1n DIFFIO_TX1p DIFFIO_TX1n DIFFIO_RX0p DIFFIO_RX0n DIFFIO_TX0p DIFFIO_TX0n F1020 AJ30 AF27 AF28 AH27 AH28 AG27 AG28 AH30 AH29 AG25 AG26 AD27 AC27 AD26 AC26 AK29 AK31 AL29 AL30 AM29 AK28 AL31 AL28 AJ28 AM28 AA22 AK30 AK27 AJ27 AL27 AH26 AM27 AG24 AJ26 AF24 AK26 AH24 AL26 AB22 AH25 AM26 AG23 AJ25 AM25 AK25 AE23 AL25 AF23 AC22 AJ24 DQ9B7 DQ9B6 DQ9B5 DQ9B4 DQ9B3 DQS9B DQ9B2 DQ9B1 DQ9B0 DQ8B7 DQ8B6 DQ8B5 DQ8B4 DQ8B3 DQS8B DQ8B0 DQ8B2 DQ8B1 DQ7B7 Pin List (EP1SGX40D) DQS for x16 DQS for x32 DQ3B15 DQ1B31 DQ3B14 DQ1B30 DQ3B13 DQ3B12 DQ1B29 DQ1B28 DQ3B11 DQ1B27 DQ3B10 DQ1B26 DQ3B9 DQ1B25 DQ3B8 DQ1B24 DQ3B7 DQ1B23 DQ3B6 DQ1B22 DQ3B5 DQ1B21 DQ3B4 DQ3B3 DQ1B20 DQ1B19 DQS3B DQ3B0 DQ3B2 DQ1B16 DQ1B18 DQ3B1 DQ1B17 DQ2B15 DQ1B15 Page 5 of 34 Pin Information For The Stratix™ GX EP1SGX40D Device, ver 1.7 Bank Number VREF Bank Pin Name/Function Optional Function(s) B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B12 B12 VREF1B8 VREF1B8 VREF1B8 VREF1B8 VREF1B8 VREF1B8 VREF1B8 VREF1B8 VREF1B8 VREF1B8 VREF1B8 VREF1B8 VREF1B8 VREF1B8 VREF2B8 VREF2B8 VREF2B8 VREF2B8 VREF2B8 VREF2B8 VREF2B8 VREF2B8 VREF2B8 VREF2B8 VREF2B8 VREF2B8 VREF2B8 VREF2B8 VREF2B8 VREF2B8 VREF2B8 VREF2B8 VREF2B8 VREF2B8 VREF2B8 VREF2B8 VREF3B8 VREF3B8 VREF3B8 VREF3B8 VREF3B8 VREF3B8 VREF3B8 VREF3B8 VREF3B8 VREF3B8 VREF3B8 VREF3B8 VREF3B8 VREF3B8 VREF3B8 IO IO VREF1B8 IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO VREF2B8 IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO VREF3B8 IO CLK5p IO CLK4p PLL_ENA MSEL0 MSEL1 MSEL2 IO IO Copyright © 2006 Altera Corp. Configuration Function DQ7B6 DQ7B5 DQ7B4 DQ7B3 DQS7B DQ7B2 DQ7B1 DQ7B0 FCLK3 FCLK2 DQ6B7 DQ6B6 DQ6B5 DQ6B4 PGM2 DQ6B3 DQS6B DQ6B2 CRC_ERROR DQ6B1 DQ6B0 RDN8 RUP8 DQ5B7 DQ5B6 DQ5B5 DQ5B4 RDYnBSY DQ5B3 DQS5B DQ5B2 nCS DQ5B1 DQ5B0 CS CLK5n CLK4n PLL_ENA MSEL0 MSEL1 MSEL2 PLL6_OUT3n PLL6_OUT3p Pin List (EP1SGX40D) F1020 AG22 AK24 AA21 AL24 AD22 AM24 AG21 AH23 AJ23 AK23 AL23 AM23 AE22 AF22 AH22 AL22 AJ22 AK22 AF21 AM22 AL21 AM21 AE21 AA20 AJ21 AK21 AD21 AF20 AH21 AJ20 AK20 AL20 AC21 AJ19 AG20 AH20 AB21 AG19 AH19 AE20 AA19 AL19 AK19 AM18 AL18 AC20 AD20 AB20 AB19 AH18 AG18 DQS for x16 DQS for x32 DQ2B14 DQ1B14 DQ2B13 DQ1B13 DQ2B12 DQ1B12 DQ2B11 DQ2B10 DQ2B9 DQ2B8 DQ1B11 DQS1B DQ1B10 DQ1B9 DQ1B8 DQ2B7 DQ2B6 DQ2B5 DQ2B4 DQ1B7 DQ1B6 DQ1B5 DQ1B4 DQ2B3 DQS2B DQ2B2 DQ1B3 DQ2B1 DQ2B0 DQ1B1 DQ1B0 DQ1B2 Page 6 of 34 Pin Information For The Stratix™ GX EP1SGX40D Device, ver 1.7 Bank Number VREF Bank Pin Name/Function Optional Function(s) B12 B12 B11 B11 B11 B11 B11 B11 B12 B12 B11 B11 VREF3B8 VREF3B8 VREF3B8 VREF3B8 VREF3B8 VREF3B8 VREF3B8 VREF3B8 IO IO IO IO IO IO IO IO VCC_PLL6_OUTB VCC_PLL6_OUTB VCC_PLL6_OUTA VCC_PLL6_OUTA VCCA_PLL6 GND GNDA_PLL6 VCCG_PLL6 GNDG_PLL6 VCCA_PLL12 GND GNDA_PLL12 VCCG_PLL12 GNDG_PLL12 CLK7p IO CLK6p IO nCE nCEO IO nIO_PULLUP VCCSEL PORSEL VREF0B7 IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 VREF0B7 VREF0B7 VREF0B7 VREF0B7 VREF0B7 VREF0B7 VREF0B7 VREF0B7 VREF0B7 VREF0B7 VREF0B7 VREF0B7 VREF0B7 VREF0B7 VREF0B7 VREF0B7 VREF0B7 VREF0B7 VREF0B7 VREF0B7 VREF0B7 VREF0B7 VREF0B7 VREF1B7 VREF1B7 VREF1B7 VREF1B7 VREF1B7 VREF1B7 Copyright © 2006 Altera Corp. Configuration Function PLL6_OUT2n PLL6_OUT2p PLL6_FBn PLL6_FBp PLL6_OUT1n PLL6_OUT1p PLL6_OUT0n PLL6_OUT0p F1020 DQS for x16 DQS for x32 AK18 AJ18 AH17 AG17 AK17 AJ17 AM17 AL17 AA18 AB18 AC18 AB17 AC17 AA17 AC16 CLK7n CLK6n/PLL12_OUT nCE nCEO PGM0 nIO_PULLUP VCCSEL PORSEL INIT_DONE DQ4B7 DQ4B6 nRS DQ4B5 DQ4B4 DQ4B3 RUnLU DQS4B DQ4B2 DQ4B1 PGM1 Pin List (EP1SGX40D) AB16 AD17 AA16 AG16 AH16 AJ16 AK16 AD16 AE16 AD18 AB15 AA15 AC15 Y16 AD19 AC19 AG15 AE19 AJ15 AE17 AH15 Y18 AK15 AD15 AL15 AF18 AL14 Y17 AM14 AE18 AM15 AF17 Page 7 of 34 Pin Information For The Stratix™ GX EP1SGX40D Device, ver 1.7 Bank Number VREF Bank Pin Name/Function Optional Function(s) B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 VREF1B7 VREF1B7 VREF1B7 VREF1B7 VREF1B7 VREF1B7 VREF1B7 VREF1B7 VREF1B7 VREF1B7 VREF1B7 VREF1B7 VREF1B7 VREF1B7 VREF1B7 VREF1B7 VREF1B7 VREF1B7 VREF1B7 VREF1B7 VREF1B7 VREF1B7 VREF1B7 VREF1B7 VREF2B7 VREF2B7 VREF2B7 VREF2B7 VREF2B7 VREF2B7 VREF2B7 VREF2B7 VREF2B7 VREF2B7 VREF2B7 VREF2B7 VREF2B7 VREF2B7 VREF2B7 VREF2B7 VREF2B7 VREF2B7 VREF2B7 VREF2B7 VREF2B7 VREF2B7 VREF2B7 VREF2B7 VREF2B7 VREF2B7 VREF2B7 IO IO IO IO IO IO IO IO IO IO IO IO VREF1B7 IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO VREF2B7 IO IO IO IO IO IO IO IO IO Copyright © 2006 Altera Corp. Configuration Function DQ4B0 RDN7 RUP7 DQ3B7 DQ3B6 DQ3B5 DEV_CLRn DQ3B4 DQ3B3 DQS3B DQ3B2 DQ3B1 DQ3B0 FCLK5 FCLK4 DQ2B7 DQ2B6 DQ2B5 DQ2B4 DQ2B3 DQS2B DQ2B2 DQ2B1 DQ2B0 DQ1B6 DQ1B5 DQ1B7 DQ1B4 DQ1B3 Pin List (EP1SGX40D) F1020 AK14 AC14 AF19 AG14 AE15 AH14 AB14 AL13 AD14 AM13 AF16 AJ14 Y15 Y14 AH13 AA14 AJ13 AE14 AK13 V14 AG13 W14 AF15 U14 AD13 AC13 AE13 W13 AF13 AA13 AB13 V13 AE12 U13 AF12 W12 AC12 AA12 AD12 AF14 W11 Y13 V11 AB11 V12 AB12 AF11 AE11 Y11 AC11 AA11 DQS for x16 DQS for x32 DQ1B15 DQ0B31 DQ1B14 DQ0B30 DQ1B13 DQ0B29 DQ1B12 DQ0B28 DQ1B11 DQ0B27 DQS1B DQ1B10 DQ0B26 DQ1B9 DQ0B25 DQ1B8 DQ0B24 DQ1B7 DQ1B6 DQ1B5 DQ0B23 DQ0B22 DQ0B21 DQ1B4 DQ0B20 DQ1B3 DQ0B19 DQS0B DQ1B2 DQ0B18 DQ1B1 DQ0B17 DQ1B0 DQ0B16 DQ0B14 DQ0B14 DQ0B13 DQ0B15 DQ0B12 DQ0B13 DQ0B15 DQ0B12 DQ0B11 DQ0B11 Page 8 of 34 Pin Information For The Stratix™ GX EP1SGX40D Device, ver 1.7 Bank Number VREF Bank Pin Name/Function Optional Function(s) B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B15 B15 B15 B15 B15 B15 B15 B15 B15 B15 B15 VREF2B7 VREF2B7 VREF2B7 VREF3B7 VREF3B7 VREF3B7 VREF3B7 VREF3B7 VREF3B7 VREF3B7 VREF3B7 VREF3B7 VREF3B7 VREF3B7 VREF3B7 VREF3B7 VREF3B7 VREF3B7 VREF3B7 VREF3B7 IO IO IO IO IO IO IO IO IO IO IO IO IO VREF3B7 IO IO IO IO IO IO GND/NC GND/NC GND/NC GND/NC GND/NC GND/NC GND/NC GND/NC VCCA_B15 GND/NC GND/NC VCCG_B15 GND RREFB16 GND/NC GND/NC GND/NC GND/NC GND/NC GND/NC GND/NC GND/NC GXB_RX11n GXB_RX11p GXB_TX11n GXB_TX11p GXB_RX10n GXB_RX10p GXB_TX10n GXB_TX10p VCCA_B15 B15 B15 B15 B15 B15 B15 B15 B15 B15 B15 B15 B15 B15 B15 B15 B15 B15 B15 Copyright © 2006 Altera Corp. Configuration Function DQS1B DQ1B2 DQ1B1 DQ1B0 DQ0B7 DQ0B6 DQ0B5 DQ0B4 DQ0B3 DQS0B DQ0B2 DQ0B1 DQ0B0 Pin List (EP1SGX40D) F1020 DQS for x16 DQS for x32 AD11 V10 AE10 W10 AC10 Y10 AD10 AD7 AC9 AA10 AF8 AB10 AF10 Y12 AC8 AE8 AF9 AD8 AD9 AE9 AL11 AM11 AH11 AJ11 AL9 AM9 AH9 AJ9 AD6 AL7 AM7 AC6 AB6 AC7 AL5 AM5 AH7 AJ7 AM3 AM2 AJ5 AJ4 AK2 AK1 AG5 AG4 AH2 AH1 AE5 AE4 AA6 DQS0B DQ0B10 DQ0B10 DQ0B9 DQ0B9 DQ0B8 DQ0B8 DQ0B7 DQ0B7 DQ0B6 DQ0B6 DQ0B5 DQ0B5 DQ0B4 DQ0B3 DQ0B4 DQ0B3 DQ0B2 DQ0B1 DQ0B0 DQ0B2 DQ0B1 DQ0B0 Page 9 of 34 Pin Information For The Stratix™ GX EP1SGX40D Device, ver 1.7 Bank Number B15 B15 B15 B15 B15 B15 B15 B15 B15 B15 B15 B15 B15 B15 B15 B15 B15 B15 B15 B15 B15 B15 B15 B15 B15 B15 B15 B15 B15 B15 B15 B14 B14 B14 B14 B14 B14 B14 B14 B14 B14 B14 B14 B14 B14 VREF Bank Pin Name/Function Optional Function(s) Configuration Function REFCLKB15n REFCLKB15p VCCG_B15 GND RREFB15 GXB_RX8n GXB_RX8p GXB_TX8n GXB_TX8p GXB_RX9n GXB_RX9p GXB_TX9n GXB_TX9p GND/NC GND/NC GND/NC GND/NC GND/NC GND/NC GND/NC GND/NC VCCA_B15 GND/NC GND/NC VCCG_B15 GND GND/NC GND/NC GND/NC GND/NC GND/NC GND/NC GND/NC GND/NC GND/NC GXB_RX7n GXB_RX7p GXB_TX7n GXB_TX7p GXB_RX6n GXB_RX6p GXB_TX6n GXB_TX6p VCCA_B14 REFCLKB14n REFCLKB14p VCCG_B14 GND RREFB14 GXB_RX4n GXB_RX4p Copyright © 2006 Altera Corp. F1020 DQS for x16 DQS for x32 AF2 AF1 W6 Y6 T8 AD2 AD1 AC5 AC4 AB2 AB1 AA5 AA4 Y2 Y1 W5 W4 V2 V1 U5 U4 V6 T2 T1 T6 U6 T7 P2 P1 R5 R4 M2 M1 N5 N4 K2 K1 L5 L4 H2 H1 J5 J4 R6 F2 F1 N6 P6 L7 D2 D1 Pin List (EP1SGX40D) Page 10 of 34 Pin Information For The Stratix™ GX EP1SGX40D Device, ver 1.7 Bank Number VREF Bank Pin Name/Function Optional Function(s) VREF0B4 VREF0B4 VREF0B4 VREF0B4 VREF0B4 VREF0B4 VREF0B4 VREF0B4 VREF0B4 VREF0B4 VREF0B4 VREF0B4 VREF0B4 VREF0B4 VREF0B4 VREF0B4 VREF0B4 VREF1B4 VREF1B4 VREF1B4 VREF1B4 VREF1B4 VREF1B4 GXB_TX4n GXB_TX4p GXB_RX5n GXB_RX5p GXB_TX5n GXB_TX5p GND/NC GND/NC GND/NC GND/NC GND/NC GND/NC GND/NC GND/NC VCCA_B14 GND/NC GND/NC VCCG_B14 GND RREFB13 GND/NC GND/NC GND/NC GND/NC GND/NC GND/NC GND/NC GND/NC IO IO IO IO IO IO VREF0B4 IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO B14 B14 B14 B14 B14 B14 B14 B14 B14 B14 B14 B14 B14 B14 B14 B14 B14 B14 B14 B14 B14 B14 B14 B14 B14 B14 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 Copyright © 2006 Altera Corp. Configuration Function F1020 G5 G4 B2 B1 E4 D4 B4 A4 E6 D6 B6 A6 E8 D8 M6 B8 A8 K6 L6 J7 B10 A10 E10 D10 B12 A12 E12 D12 H9 J8 K8 G8 J9 K9 N12 G9 K7 H8 L8 L9 H7 J10 L10 K10 M10 G10 N10 H10 P10 K11 R10 DQ0T0 DQ0T1 DQ0T2 DQS0T DQ0T3 DQ0T4 DQ0T5 DQ0T6 DQ0T7 DQ1T0 DQ1T1 DQ1T2 DQS1T DQ1T3 Pin List (EP1SGX40D) DQS for x16 DQS for x32 DQ0T0 DQ0T1 DQ0T2 DQ0T0 DQ0T1 DQ0T2 DQ0T3 DQ0T4 DQ0T3 DQ0T4 DQ0T5 DQ0T5 DQ0T6 DQ0T6 DQ0T7 DQ0T7 DQ0T8 DQ0T8 DQ0T9 DQ0T9 DQ0T10 DQ0T10 DQS0T DQ0T11 DQ0T11 Page 11 of 34 Pin Information For The Stratix™ GX EP1SGX40D Device, ver 1.7 Bank Number VREF Bank Pin Name/Function Optional Function(s) B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 VREF1B4 VREF1B4 VREF1B4 VREF1B4 VREF1B4 VREF1B4 VREF1B4 VREF1B4 VREF1B4 VREF1B4 VREF1B4 VREF1B4 VREF1B4 VREF1B4 VREF1B4 VREF1B4 VREF1B4 VREF1B4 VREF1B4 VREF1B4 VREF1B4 VREF1B4 VREF1B4 VREF1B4 VREF2B4 VREF2B4 VREF2B4 VREF2B4 VREF2B4 VREF2B4 VREF2B4 VREF2B4 VREF2B4 VREF2B4 VREF2B4 VREF2B4 VREF2B4 VREF2B4 VREF2B4 VREF2B4 VREF2B4 VREF2B4 VREF2B4 VREF2B4 VREF2B4 VREF2B4 VREF2B4 VREF2B4 VREF2B4 VREF2B4 VREF2B4 IO IO IO IO IO IO VREF1B4 IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO VREF2B4 IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO Copyright © 2006 Altera Corp. Configuration Function DQ1T4 DQ1T7 DQ1T5 DQ1T6 DQ2T0 DQ2T1 DQ2T2 DQS2T DQ2T3 DQ2T4 DQ2T5 DQ2T6 DQ2T7 FCLK6 FCLK7 DQ3T0 DQ3T1 DQ3T2 DQS3T DQ3T3 DQ3T4 DQ3T5 DEV_OE DQ3T6 DQ3T7 RUP4 RDN4 DQ4T0 nWS DQ4T1 Pin List (EP1SGX40D) F1020 DQS for x16 DQS for x32 H11 G11 J11 N11 L11 P11 N13 M11 R11 J12 M12 K12 P12 G12 R12 H12 T12 L12 U12 H13 R13 J13 L13 K13 M13 T14 P13 G13 T13 D14 N14 F14 P14 G14 R14 N15 E14 G17 H14 L14 J14 M14 G15 G18 H15 H19 K14 C14 G19 A15 L15 DQ0T12 DQ0T15 DQ0T13 DQ0T12 DQ0T15 DQ0T13 DQ0T14 DQ0T14 DQ1T0 DQ0T16 DQ1T1 DQ0T17 DQ1T2 DQ0T18 DQS0T DQ1T3 DQ0T19 DQ1T4 DQ0T20 DQ1T5 DQ1T6 DQ1T7 DQ0T21 DQ0T22 DQ0T23 DQ1T8 DQ0T24 DQ1T9 DQ0T25 DQ1T10 DQ0T26 DQS1T DQ1T11 DQ0T27 DQ1T12 DQ0T28 DQ1T13 DQ0T29 DQ1T14 DQ0T30 DQ1T15 DQ0T31 Page 12 of 34 Pin Information For The Stratix™ GX EP1SGX40D Device, ver 1.7 Bank Number VREF Bank Pin Name/Function Optional Function(s) B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 VREF2B4 VREF2B4 VREF2B4 VREF3B4 VREF3B4 VREF3B4 VREF3B4 VREF3B4 VREF3B4 VREF3B4 VREF3B4 VREF3B4 VREF3B4 VREF3B4 VREF3B4 VREF3B4 VREF3B4 VREF3B4 VREF3B4 VREF3B4 VREF3B4 VREF3B4 VREF3B4 VREF3B4 VREF3B4 VREF3B4 IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO VREF3B4 TMS TRST TCK IO TDI TDO IO CLK12p IO CLK13p VCCA_PLL11 GND GNDA_PLL11 VCCG_PLL11 GNDG_PLL11 TEMPDIODEp TEMPDIODEn VCCA_PLL5 GND GNDA_PLL5 VCCG_PLL5 GNDG_PLL5 VCC_PLL5_OUTA VCC_PLL5_OUTB IO IO IO IO IO IO IO IO IO IO nSTATUS B9 B10 B9 B9 B9 B9 B9 B9 B10 B10 B10 B10 B3 VREF0B3 VREF0B3 VREF0B3 VREF0B3 VREF0B3 VREF0B3 VREF0B3 VREF0B3 VREF0B3 VREF0B3 VREF0B3 Copyright © 2006 Altera Corp. Configuration Function DQ4T2 DQS4T DATA0 DQ4T3 DQ4T4 DQ4T5 DATA1 DQ4T6 DQ4T7 DATA2 TMS TRST TCK DATA3 TDI TDO CLK12n CLK13n/PLL11_OUT F1020 DQS for x16 DQS for x32 A14 M15 B14 H17 B15 K19 C15 N17 F15 H18 D15 J18 E15 N18 L19 N16 G16 J15 K15 J19 H16 J16 C16 D16 E16 F16 K16 L16 J17 M16 L21 L20 L18 PLL5_OUT0p PLL5_OUT0n PLL5_OUT1p PLL5_OUT1n PLL5_FBp PLL5_FBn PLL5_OUT2p PLL5_OUT2n PLL5_OUT3p PLL5_OUT3n nSTATUS Pin List (EP1SGX40D) L17 K17 M17 K18 M18 F18 E18 D17 C17 F17 E17 B17 A17 D18 C18 L22 Page 13 of 34 Pin Information For The Stratix™ GX EP1SGX40D Device, ver 1.7 Bank Number VREF Bank Pin Name/Function Optional Function(s) Configuration Function F1020 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 VREF0B3 VREF0B3 VREF0B3 VREF0B3 VREF0B3 VREF0B3 VREF0B3 VREF0B3 VREF0B3 VREF0B3 VREF0B3 VREF0B3 VREF1B3 VREF1B3 VREF1B3 VREF1B3 VREF1B3 VREF1B3 VREF1B3 VREF1B3 VREF1B3 VREF1B3 VREF1B3 VREF1B3 VREF1B3 VREF1B3 VREF1B3 VREF1B3 VREF1B3 VREF1B3 VREF1B3 VREF1B3 VREF1B3 VREF1B3 VREF2B3 VREF2B3 VREF2B3 VREF2B3 VREF2B3 VREF2B3 VREF2B3 VREF2B3 VREF2B3 VREF2B3 VREF2B3 VREF2B3 VREF2B3 VREF2B3 VREF2B3 VREF2B3 VREF2B3 nCONFIG DCLK CONF_DONE CLK14p IO CLK15p IO VREF0B3 IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO VREF1B3 IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO VREF2B3 IO IO IO IO nCONFIG DCLK CONF_DONE K20 J20 K21 B18 A18 C19 B19 M19 G20 E19 F19 H20 E20 F20 D19 J21 B20 C20 D20 E21 H21 G21 C21 D21 M20 F21 A21 B21 A22 F22 C22 D22 B22 E22 G22 H22 J22 A23 B23 C23 D23 E23 F23 A24 G23 B24 M21 C24 D24 H23 F24 Copyright © 2006 Altera Corp. CLK14n CLK15n DATA4 DQ5T0 DQ5T1 DATA5 DQ5T2 DQS5T DQ5T3 DATA6 DQ5T4 DQ5T5 DQ5T6 DQ5T7 RUP3 RDN3 DQ6T0 DQ6T1 DATA7 DQ6T2 DQS6T DQ6T3 CLKUSR DQ6T4 DQ6T5 DQ6T6 DQ6T7 FCLK0 FCLK1 DQ7T0 DQ7T1 DQ7T2 DQS7T DQ7T3 DQ7T4 DQ7T5 DQ7T6 DQ7T7 Pin List (EP1SGX40D) DQS for x16 DQS for x32 DQ2T0 DQ2T1 DQ1T0 DQ1T1 DQ2T2 DQS2T DQ2T3 DQ1T2 DQ2T4 DQ2T5 DQ2T6 DQ2T7 DQ1T4 DQ1T5 DQ1T6 DQ1T7 DQ2T8 DQ2T9 DQ2T10 DQ2T11 DQ1T8 DQ1T9 DQ1T10 DQS1T DQ1T11 DQ2T12 DQ1T12 DQ2T13 DQ1T13 DQ2T14 DQ2T15 DQ1T14 DQ1T15 DQ1T3 Page 14 of 34 Pin Information For The Stratix™ GX EP1SGX40D Device, ver 1.7 Bank Number VREF Bank Pin Name/Function Optional Function(s) B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 VREF2B3 VREF2B3 VREF2B3 VREF2B3 VREF2B3 IO IO IO IO IO GND IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO VREF3B3 IO IO IO IO IO IO IO IO IO IO IO GXB_GND GND VCCIO2 VCCIO2 VCCIO2 VCCIO2 VCCIO1 VCCIO1 VCCIO1 VCCIO1 VCCIO8 VCCIO8 VCCIO8 VCCIO8 VCCIO7 VCCIO7 VCCIO7 VCCIO7 VREF3B3 VREF3B3 VREF3B3 VREF3B3 VREF3B3 VREF3B3 VREF3B3 VREF3B3 VREF3B3 VREF3B3 VREF3B3 VREF3B3 VREF3B3 VREF3B3 VREF3B3 VREF3B3 VREF3B3 VREF3B3 VREF3B3 VREF3B3 VREF3B3 VREF3B3 VREF3B3 VREF3B3 VREF3B3 VREF3B3 VREF3B3 Copyright © 2006 Altera Corp. Configuration Function DQ8T1 DQ8T2 DQ8T0 DQS8T DQ8T3 DQ8T4 DQ8T5 DQ8T6 DQ8T7 DQ9T0 DQ9T1 DQ9T2 DQS9T DQ9T3 DQ9T4 DQ9T5 DQ9T6 DQ9T7 F1020 DQS for x16 DQS for x32 B25 E24 C25 A25 D25 K22 G24 A26 F25 E25 E26 B26 C26 D27 D26 F26 A27 B27 E27 C27 B30 M22 A28 D28 B28 E28 C28 B31 A29 B29 C30 C29 C31 DQ3T1 DQ1T17 DQ3T2 DQ3T0 DQS3T DQ1T18 DQ1T16 DQ3T3 DQ1T19 DQ3T4 DQ1T20 DQ3T5 DQ3T6 DQ1T21 DQ1T22 DQ3T7 DQ1T23 DQ3T8 DQ3T9 DQ1T24 DQ1T25 DQ3T10 DQ1T26 DQ3T11 DQ1T27 DQ3T12 DQ1T28 DQ3T13 DQ3T14 DQ1T29 DQ1T30 DQ3T15 DQ1T31 C32 N23 R32 T24 AK32 V32 U23 Y23 AM19 Y19 AM30 Y21 AF7 AM16 AM12 U11 Pin List (EP1SGX40D) Page 15 of 34 Pin Information For The Stratix™ GX EP1SGX40D Device, ver 1.7 Bank Number VREF Bank Pin Name/Function Optional Function(s) Configuration Function VCCIO4 VCCIO4 VCCIO4 VCCIO4 VCCIO3 VCCIO3 VCCIO3 VCCIO3 VCCP_B14 VCCP_B14 VCCP_B14 VCCP_B14 VCCP_B15 VCCP_B15 VCCP_B15 VCCP_B15 VCCP_B15 VCCP_B15 VCCR_B14 VCCR_B14 VCCR_B14 VCCR_B14 VCCR_B15 VCCR_B15 VCCR_B15 VCCR_B15 VCCR_B15 VCCR_B15 VCCT_B14 VCCT_B14 VCCT_B14 VCCT_B14 VCCT_B15 VCCT_B15 VCCT_B15 VCCT_B15 VCCT_B15 VCCT_B15 VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT Copyright © 2006 Altera Corp. F1020 DQS for x16 DQS for x32 A13 A16 G7 T11 A19 A30 N19 N21 M9 N9 P9 R9 W9 Y9 AA9 AB9 U9 V9 M8 N8 P8 R8 W8 Y8 AA8 AB8 U8 V8 M7 N7 P7 R7 W7 Y7 AA7 AB7 U7 V7 R15 P19 U15 V15 W22 AG12 P22 T17 V21 P15 R21 U18 W20 Pin List (EP1SGX40D) Page 16 of 34 Pin Information For The Stratix™ GX EP1SGX40D Device, ver 1.7 Bank Number VREF Bank Pin Name/Function Optional Function(s) Configuration Function VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT GXB_GND GXB_GND GXB_GND GXB_GND GXB_GND GXB_GND GXB_GND GXB_GND GXB_GND GXB_GND GXB_GND GXB_GND GXB_GND GXB_GND GXB_GND GXB_GND GXB_GND GXB_GND GXB_GND GXB_GND GXB_GND GXB_GND GXB_GND GXB_GND GXB_GND GXB_GND Copyright © 2006 Altera Corp. F1020 DQS for x16 DQS for x32 F11 R18 T21 W16 AG10 P21 T15 V19 F13 R20 U16 W18 W15 P20 T9 V17 U21 F9 R16 T19 V22 P17 R22 U20 W21 A2 AB4 AE2 AH3 AJ6 AK9 AL10 C1 C12 E9 H4 L2 R1 V5 A11 AD3 AF5 AH10 AK5 AL3 B3 C6 D11 F6 J3 N1 Pin List (EP1SGX40D) Page 17 of 34 Pin Information For The Stratix™ GX EP1SGX40D Device, ver 1.7 Bank Number VREF Bank Pin Name/Function Optional Function(s) Configuration Function GXB_GND GXB_GND GXB_GND GXB_GND GXB_GND GXB_GND GXB_GND GXB_GND GXB_GND GXB_GND GXB_GND GXB_GND GXB_GND GXB_GND GXB_GND GXB_GND GXB_GND GXB_GND GXB_GND GXB_GND GXB_GND GXB_GND GXB_GND GXB_GND GXB_GND GXB_GND GXB_GND GXB_GND GXB_GND GXB_GND GXB_GND GXB_GND GXB_GND GXB_GND GXB_GND GXB_GND GXB_GND GXB_GND GXB_GND GXB_GND GXB_GND GXB_GND GXB_GND GXB_GND GXB_GND GXB_GND GXB_GND GXB_GND GXB_GND GXB_GND GXB_GND Copyright © 2006 Altera Corp. F1020 DQS for x16 DQS for x32 T5 Y4 A7 AC2 AF3 AH6 AK3 AL1 AM8 C4 D7 F4 J1 M4 T3 W3 AA3 AE1 AG3 AJ3 AK8 AL8 B9 C9 E3 G3 K4 P3 U3 A5 AC1 AE6 AH5 AJ10 AK11 AM6 C3 D5 F3 H6 M3 R3 W2 AA2 AD5 AG2 AJ2 AK7 AL6 B7 C8 Pin List (EP1SGX40D) Page 18 of 34 Pin Information For The Stratix™ GX EP1SGX40D Device, ver 1.7 Bank Number VREF Bank Pin Name/Function Optional Function(s) Configuration Function GXB_GND GXB_GND GXB_GND GXB_GND GXB_GND GXB_GND GXB_GND GXB_GND GXB_GND GXB_GND GXB_GND GXB_GND GXB_GND GXB_GND GXB_GND GXB_GND GXB_GND GXB_GND GXB_GND GXB_GND GXB_GND GXB_GND GXB_GND GXB_GND GXB_GND GXB_GND GXB_GND GXB_GND GXB_GND GXB_GND GXB_GND GXB_GND GXB_GND GXB_GND GXB_GND GXB_GND GXB_GND GXB_GND GXB_GND GXB_GND GXB_GND GXB_GND GXB_GND GXB_GND GXB_GND GXB_GND GXB_GND GXB_GND GXB_GND GXB_GND GXB_GND Copyright © 2006 Altera Corp. F1020 DQS for x16 DQS for x32 E2 G2 K3 N3 U2 V4 A3 AB5 AE3 AH4 AJ8 AK10 AM4 C2 D3 E11 H5 L3 R2 W1 AA1 AD4 AG1 AJ1 AK6 AL4 B5 C7 E1 G1 J6 N2 U1 Y5 A9 AC3 AF4 AH8 AK4 AL2 AM10 C5 D9 F5 J2 M5 T4 Y3 AB3 B11 C10 Pin List (EP1SGX40D) Page 19 of 34 Pin Information For The Stratix™ GX EP1SGX40D Device, ver 1.7 Bank Number VREF Bank Pin Name/Function Optional Function(s) Configuration Function GXB_GND GXB_GND GXB_GND GXB_GND GXB_GND GXB_GND GXB_GND GXB_GND GXB_GND GXB_GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Copyright © 2006 Altera Corp. F1020 DQS for x16 DQS for x32 E5 G6 K5 P4 V3 C11 E7 H3 L1 P5 A20 AL12 D13 P18 T22 AG8 AG9 AM31 F10 R19 U19 Y20 AG6 AL32 F7 AF6 AE7 W19 AH12 B16 N20 T16 V16 Y24 A31 AL16 E13 P32 U10 W17 AG11 B13 F12 T10 U22 Y22 AG7 AM20 F8 R17 U17 Pin List (EP1SGX40D) Page 20 of 34 Pin Information For The Stratix™ GX EP1SGX40D Device, ver 1.7 Bank Number VREF Bank Pin Name/Function Optional Function(s) Configuration Function GND GND GND GND GND GND GND GND GND GND GND GND Copyright © 2006 Altera Corp. F1020 DQS for x16 DQS for x32 W32 AJ12 B32 N22 T18 V18 P16 AK12 C13 N24 T20 V20 Pin List (EP1SGX40D) Page 21 of 34 Pin Definitions For The Stratix™ GX EP1SGX Device, ver 1.7 Pin Name Pin Type (1st, 2nd, & 3rd Function) VREF[1..4]B[1..4,7,8] Input VCCIO[1..4]B[1..4,7,8] Power VCCINT Power VCC_PLL5_OUTA Power VCC_PLL5_OUTB Power VCC_PLL6_OUTA Power VCC_PLL6_OUTB Power VCCA_PLL[1,2,5,..,8,11,12] Power GNDA_PLL[1,2,5,..,8,11,12] Ground VCCG_PLL[1,2,5,..,8,11,12] Power GNDG_PLL[1,2,5,..,8,11,12] Ground GXB_GND Ground GND NC Ground No Connect nSTATUS Bidirectional (opendrain) Bidirectional (opendrain) nCONFIG Input DCLK Input nIO_PULLUP Input PORSEL Input VCCSEL Input nCE Input nCEO Output TMS TDI TCK TDO Input Input Input Output TRST MSEL[2..0] Input Input CONF_DONE Copyright © 2006 Altera Corp. Pin Description Supply and Reference Pins Input reference voltage for banks. If a bank is used for a voltage-referenced I/O standard, then these pins are used as the voltage-reference pins for the bank. If VREF pins are not used, they should be connected to Gnd. These are I/O supply voltage pins for banks 1 through 8. Each bank can support a different voltage level. VCCIO supplies power to the output buffers for all I/O standards. VCCIO also supplies power to the input buffers used for the LVTTL, LVCMOS, 1.5-V, 1.8-V, 2.5-V, 3.3-V PCI, and 3.3-V PCI-X I/O standards. These power pins are supplied with a 1.5V source. These are internal logic array voltage supply pins. VCCINT also supplies power to the input buffers used for the LVDS, LVPECL, 3.3-V PCML, HyperTransport™ technology, differential HSTL, GTL, GTL+, HSTL, SSTL, CTT, and 3.3-V AGP I/O standards. External clock output buffer power for PLL5 clock outputs PLL5_OUT[1..0]. The designer must connect this pin to the VCCIO of bank 9. External clock output buffer power for PLL5 clock outputs PLL5_OUT[3..2]. The designer must connect this pin to the VCCIO of bank 10. External clock output buffer power for PLL6 clock outputs PLL6_OUT[1..0]. The designer must connect this pin to the VCCIO of bank 11. External clock output buffer power for PLL6 clock outputs PLL6_OUT[3..2]. The designer must connect this pin to the VCCIO of bank 12. Analog power for PLLs[1,2,5,..,8,11,12]. The designer must connect this pin to 1.5 V, even if the PLL is not used. Analog ground for PLLs[1,2,5,..,8,11,12]. The designer can connect this pin to the GND plane on the board. Guard ring power for PLLs[1,2,5,..,8,11,12]. The designer must connect this pin to 1.5 V, even if the PLL is not used. Guard ring ground for PLLs[1,2,5,..,8,11,12]. The designer can connect this pin to the GND plane on the board. Transceiver Power Ground. These ground pins need to be connected to a ground island plane isolated from noisy digital ground. These ground pins need to be connected to digital ground. The digital ground is used for VCCINT and VCCIO return current. These pins should be left unconnected. Dedicated & Configuration/JTAG Pins This is a dedicated configuration status pin; it is not available as a user I/O pin. This is a dedicated configuration status pin; it is not available as a user I/O pin. Dedicated configuration control input. A low transition resets the target device; a low-to-high transition begins configuration. All I/O pins tri-state when nCONFIG is driven low. Clock input used to clock configuration data from an external source into the Stratix device. This is a dedicated pin used for configuration. IF nIO_PULLUP is driven high during configuration, the weak pull-ups on all user I/O pins are disabled. If driven low, the weak pull-ups are enabled during configuration. nIO_PULLUP can be pulled up to either 1.5, 1.8, 2.5, or 3.3 V. Dedicated input pin used to select POR delay times of 2 ms or 100 ms during powerup. When PORSEL is connected to ground, the POR time is 100 ms. When PORSEL is connected to 3.3 V, the POR time is 2 ms. VCCSEL is used to select which input buffer is used on all configuration pins. VCCSEL will control whether the 3.3-/2.5-V input buffer or the 1.8-/1.5-V input buffer is used. A "0" means 3.3/2.5 V and a "1" means 1.8/1.5 V. At powerup, VCCSEL accepts 3.3 Active-low chip enables. Dedicated chip enable input used to detect which device is active in a chain of devices. When nCE is low, the device is enabled. When nCE is high, the device is disabled. Output that drives low when device configuration is complete. During multi-device configuration, this pin feeds a subsequent device’s nCE pin. This is a dedicated JTAG input pin. This is a dedicated JTAG input pin. This is a dedicated JTAG input pin. This is a dedicated JTAG input pin. This is a dedicated JTAG input pin. Active low input, used to asynchronously reset the JTAG boundary scan circuit. Dedicated mode select control pins that set the configuration mode for the device. Pin Definitions (EP1SGX) Page 22 of 34 Pin Definitions For The Stratix™ GX EP1SGX Device, ver 1.7 Pin Name Pin Type (1st, 2nd, & 3rd Function) TEMPDIODEp Input TEMPDIODEn Input Pin Description Pin used in conjunction with the temperature sensing diode (bias-high input) inside the Stratix device. If the temperature sensing diode is not used then connect this pin to GND. Pin used in conjunction with the temperature sensing diode (bias-low input) inside the Stratix device. If the temperature sensing diode is not used then connect this pin to GND. PLL_ENA Input Clock and PLL Pins Dedicated input pin that drives the optional pllena port of all or a set of PLLs. If a PLL uses the pllena port, drive the PLL_ENA pin low to reset all PLLs including the counters to their default state. If VCCSEL = 0, then you must drive the PLL_ENA with a 3.3/2.5 V signal to enable the PLLs. If VCCSEL = 1, connect PLL_ENA to 1.8/1.5 V to enable the PLLs. FCLK[7..0] CLK[15..12]p CLK[15..12]n CLK[7..0]p CLK[7, 6, 5, 4, 3, 1]n CLK[2, 0]n Bidirectional Input I/O, Input Input I/O, Input Input PLL6_OUT[3..0]p I/O, Output PLL6_OUT[3..0]n I/O, Output PLL5_OUT[3..0]p I/O, Output PLL5_OUT[3..0]n I/O, Output DIFFIO_RX[44..0]p Input High speed source synchronous differential I/O receiver channels 0 to 44. Pins with an p suffix carry the positive signal for the differential channel If not used, these pins are dedicated input pins. DIFFIO_RX[44..0]n Input This pin is the complementary signal of the differential inputs. If not used for the differential pair, these pins are dedicated input pins. Pins with an n suffix carry the negative signal for the differential channel. DIFFIO_TX[44..0]p I/O, Output Dual-purpose source synchronous high speed differential I/O transmitter channels 0 to 44. Pins with an p suffix carry the positive signal for the differential channel. If not used, these pins are regular I/O pins. DIFFIO_TX[44..0]n I/O, Output PLL5_FBp PLL5_FBn PLL6_FBp PLL6_FBn I/O, Input I/O, Input I/O, Input I/O, Input INIT_DONE I/O, Output DATA[7..0] nRS I/O, Input I/O, Input DEV_CLRn I/O, Input DEV_OE I/O, Input CLKUSR I/O, Input RDYnBSY I/O, Output Copyright © 2006 Altera Corp. Dedicated fast regional clock pins. FCLK pins can also be used as input, output, or bidirectional pins. Dedicated global clock inputs 12 to 15. Negative terminal input for differential global clock input. May also be used as regular I/O Dedicated global clock inputs 0 to 7. Negative terminal input for differential global clock input. Or may be used as a regular I/O pin. Dedicated negative terminal input for differential global clock input. External clock outputs [3..0] from enhanced PLL 6. These pins can be differential (four output pin pairs) or single ended (eight clock outputs from PLL6). May also be used as regular I/O Negative terminal for external clock outputs [3..0] from PLL6. If the clock outputs are single ended, then each pair of pins (i.e., PLL6_OUT0p and PLL6_OUT0n are considered one pair) can be either in phase or 180 degrees out of phase. May also be used as regular I/O External clock outputs [3..0] from enhanced PLL 5. These pins can be differential (four output pin pairs) or single ended (eight clock outputs from PLL5). May also be used as regular I/O Negative terminal for external clock outputs [3..0] from PLL 5. If the clock outputs are single ended, then each pair of pins (i.e., PLL5_OUT0p and PLL5_OUT0n are considered one pair) can be either in phase or 180 degrees out of phase. May also be used as regular I/O Optional/Dual-Purpose Pins This pin is the complementary signal of the differential inputs and outputs. If not used for the differential pair, these pins are regular I/O pins. Pins with an n suffix carry the negative signal for the differential channel. External feedback input pin for PLL5. This pin can be used as a user I/O pin if external feedback mode is not used. Negative terminal input for external feedback input PLL5_FBp External feedback input pin for PLL6 Negative terminal p pinputpfor external feedback input PLL6_FBp p _ the pin indicates when the device has entered user mode. This pin can be used as a user I/O pin after configuration. Dual-purpose configuration input data pins. These pins can be used for configuration or as regular I/O pins. These pins can also be used as user I/O pins after configuration. Read strobe input pin. This pin can be used as a user I/O pin after configuration. Optional pin that allows you to override all clears on all device registers. When this pin is driven low, all registers are cleared; when this pin is driven high, all registers behave as defined in the users design. Optional pin that allows you to override all tri-states on the device. When this pin is driven low, all I/O pins are tri-stated; when this pin is driven high, all I/O pins behave as defined in the design. Optional user-supplied clock input. Synchronizes the initialization of one or more devices. This pin can be used as a user I/O pin after configuration. Ready not busy output. A high output indicates that the target device is ready to accept another data byte. A low output indicates that the target device is not ready to receive another data byte. This pin can be used as a user I/O pin after configuration Pin Definitions (EP1SGX) Page 23 of 34 Pin Definitions For The Stratix™ GX EP1SGX Device, ver 1.7 Pin Name Pin Type (1st, 2nd, & 3rd Function) nCS,CS I/O, Input nWS I/O, Input PGM[2..0] I/O, Output RUP[8..7],RUP[4..1] I/O, Input RDN[8..7],RDN[4..1] I/O, Input RUnLU I/O, Input VCCP_B[17..13] VCCR_B[17..13] VCCT_B[17..13] VCCG_B[17..13] VCCA_B[17..13] VCC VCC VCC VCC VCC GXB_RX[19..0]n I, Input GXB_RX[19..0]p I, Input GXB_TX[19..0]n O,Output GXB_TX[19..0]p O,Output REFCLKB[17..13]n I, Input REFCLKB[17..13]p I, Input High speed differential I/O reference clock negative. Connect any of these unused pins to ground through a 10K ohm resistor. High speed differential I/O reference clock positive. Connect any of these unused pins to 1.5V through a 10K ohm resistor. RREFB[17..13] I, Input Reference resistor for Gx side banks. Should be connected to a 2K of a tolerance of 1% to ground. In the PCB layout the trace from this pin to the resistor needs to be routed so that it avoids any aggressor signals. RREFB[15,14]A I, Input Reference resistor for Gx side banks. Should be connected to a 2K of a tolerance of 1% to ground. In the PCB layout the trace from this pin to the resistor needs to be routed so that it avoids any aggressor signals. Copyright © 2006 Altera Corp. Pin Description These are chip-select inputs that enable the Stratix device in the passive parallel asynchronous configuration mode. Drive nCS low and CS high to target a device for configuration. If a design requires an active high enable, use the CS pin and drive the nCS pin low. Active-low write strobe input to latch a byte of data on the DATA pins. This pin can be used as a user I/O pin after configuration. These output pins control one of eight pages in the EPC16 configuration device when using remote update or local update configuration modes. When not using remote update or local update configuration modes, these pins are user I/O pins. Reference pins for banks 8,7,4,3,2,1 The external precision resistors R UP must be connected to the designated RUP pin on that I/O bank. If not required, these pins are regular I/O pins. Reference pins for banks 8,7,4,3,2,1. The external precision resistors R DN must be connected to the designated RDN pin on that I/O bank. If not required, these pins are regular I/O pins. Pin Definitions Input control pin to select remote update or local update modes. If MSEL2 = 1, this is a input control pin to select remote update (RUnLU =1) or local update (RUnLU =0) modes. If MSEL2 = 0, the RUnLU pin is a user I/ O pin. GX ( I/O banks 13 to 17 ) Pins GX bank [17..13] digital power. This power is connected to 1.5V. GX bank [17..13] receiver power. This power is connected to 1.5V. GX bank [17..13] transmitter power. This power is connected to 1.5V. GX bank[17..13] guard ring power. This power is connected to 1.5V. GX bank [17..13] analog power. This power is connected to 3.3V. High speed differential I/O receiver channels negative. Connect any of these unused pins to ground through a 10K ohm resistor. High speed differential I/O receiver channels positive. Connect any of these unused pins to 1.5V through a 10K ohm resistor. High speed differential I/O transmitter channels negative. Connect any of these unused pins to ground through a 10K ohm resistor. High speed differential I/O transmitter channels positive. Connect any of these unused pins to 1.5V through a 10K ohm resistor. Pin Definitions (EP1SGX) Page 24 of 34 PLL & Bank Diagram For The Stratix GX™ EP1S40 Device, ver 1.7 Notes: 1.This is a top view of the silicon die. 2.This is a pictoral representation only to get an idea of placement on the device. Refer to the pin-list and the Quartus II for exact locations. VREF3B2 PLL5 PLL11 DQST4 DQST3 DQST2 DQST1 DQST0 VREF4B4 VREF3B4 VREF2B4 VREF1B4 VREF0B4 B4 B9 B10 VREF0B2 VREF1B2 B2 VREF2B2 LVDS clock network overlap in row 6-23, 37-53 B13 VREF0B3 Q0T DQST5 B14 VREF1B3 Q0R DQST6 B3 Q1T VREF2B3 Q1R DQST7 Q0A VREF3B3 Q0D DQST8 Q1A VREF4B3 Q1D DQST9 PLL7 Device Name PLL1 13,14,15,16,17 B17 Q4T Q4R Q4A 14 & 15 EP1SGX40G Q2D Q2A Q2R Q2T B15 Q3D Q3A Q3R Q3T B16 VREF0B1 VREF1B1 B1 VREF2B1 Q4D VREF3B1 PLL2 GX Bank # Utilized EP1SGX40D B8 PLL8 VREF1B8 VREF2B8 VERF3B8 VREF4B8 DQSB9 DQSB8 DQSB7 DQSB6 DQSB5 Copyright © 2006 Altera Corp. B7 B11 B12 VREF0B8 PLL12 PLL6 VREF0B7 VREF1B7 VREF2B7 VERF3B7 VREF4B7 DQSB4 DQSB3 DQSB2 DQSB1 DQSB0 PLL & Bank Diagram (EP1SGX40) Page 25 of 34 Power Flip Chip Global Power on Die Pkg route Left, Top, and Bottom Power and Ground are the same as Stratix Devices EPLL clock output power VCC_CLKOUT[0:7] isolated EPLL clock output power EPLL clock output ground VSSN VSSN plane EPLL clock output ground VCCN[4,7] VCCN[4,7]plane EPLL clock output ground VSSN VSSN plane PLL analog power VCCA[1:2, 5:8, 11:12] isolated PLL analog ground VSSA[1:2, 5:8, 11:12] isolated PLL digital power VCC[1:2, 5:8, 11:12] VCC plane PLL digital ground VSS[1:2, 5:8, 11:12] VSS plane PLL guard ring power VCCG[1:2, 5:8, 11:12] isolated PLL guard ring ground VSSG[1:2, 5:8, 11:12] isolated Noisy power VCCN[1:4,7:8] VCCN[1:4,7:8] plane Noisy ground VSSN VSS plane Quiet power VCC VCC plane Quiet ground VSS VSS plane Power Description Notes VSSN VCCA[3:4,9:10] VSSA[3:4,9:10] It is shorted to VCC in the package of the flip chip. It is shorted to VSS in the package of the flip chip. HSSI Global Power: Power and Ground are grouped in QUAD. Quad Order is 0,1,4,2,3 HSSI digital power (1.5 v ) HSSI RX power (1.5 v ) HSSI TX power (1.5 v ) HSSI CMU power (1.5 v ) HSSI Analog power (3.3 v ) HSSI VCCG (1.5 v ) HSSI substrate ground HSSI digital ground HSSI TX/RX ground HSSI CMU ground Marketing VCCP0 VCCP1 VCCP4 VCCP2 VCCP3 VCCR[0:3] VCCR[4:7] VCCR[16:19] VCCR[8:11] VCCR[12:15] VCCT[0:3] VCCT[4:7] VCCT[16:19] VCCT[8:11] VCCT[12:15] VCCM0 VCCM1 VCCM4 VCCM2 VCCM3 VCCAQ0 VCCAQ1 VCCAQ4 VCCAQ2 VCCAQ3 VCCGQ0 VCCGQ1 VCCGQ4 VCCGQ2 VCCGQ3 VSSASUB0 VSSASUB1 VSSASUB4 VSSASUB2 VSSASUB3 DGND DGND DGND DGND DGND HGND HGND HGND HGND HGND CGND Copyright © 2006 Altera Corp. Each Quad has 5 bumps connected to 2 isolated digital power balls Each Quad has 4 bumps connected to 1 isolated RX power ball Each Quad has 4 bumps connected to 1 isolated TX power ball VCCM# bump shares power with VCCT# of the same QUAD There are no pin associated with this pin name since they share the same bump power with VCCT# of the same Quad Each Quad has its own analog power. One bump--> one ball Provides power to Tx PLL and some biasing circuit Each Quad has its own VCCG power. One bump--> one ball Guard ring for TX PLL should be used to isolate noise to TX pll Each Quad has its own substrate ground. One bump--> one ball All digital grounds are connected to the HSSI ground plane at package level All TX/RX grounds are connected to the HSSI ground plane at package level All CMU grounds are connected to the HSSI ground plane at package level Global Power Page 26 of 34 CGND CGND CGND CGND Global Power on Die is the signal name that the schematics and layout use for this power or ground Pkg Route: 1) plane = indicates the power plane the bump/pad routes to in the pkg; 2) isolated = indicates the bump/pad is routed to the pkg ball without connect to any other pkg route or plane. Plane: A plane has multiple bump/pads connected to it which in turn connect to multiple balls. It does not necessarily imply a complete sheet of conductor; it may look be more like Swiss cheese. Net: Multiple bumps/balls can share the same net bus Copyright © 2006 Altera Corp. Global Power Page 27 of 34 Non-Migratable IO Pins Non-Migratable IO Pins 1020FBGA ( EP1SGX40 <--> EP1SGX25 ) 672FBGA ( EP1SGX25 <-->EP1SGX10) AA23 AB23 AC23 AD23 AG25 AG26 AH27 AH28 AH29 AH30 AJ29 AJ30 D29 D30 E29 E30 F27 F28 F29 F30 J23 K23 L23 M23 Copyright © 2006 Altera Corp. Non-Migratable IO Pins Page 28 of 34 Device Part Numbers Name EP1SGX10C EP1SGX10D EP1SGX25C EP1SGX25D EP1SGX25F EP1SGX40D EP1SGX40G Number of Fast PLL 2 2 2 2 2 4 4 Device Pin Count 672 672 672 672 / 1020 1020 1020 1020 # of Receiver Chs 22 22 39 39 39 45 45 # of Transmitter Chs 22 22 39 39 39 45 45 Speed (Mbps ) 1000 1000 1000 1000 1000 1000 1000 Receiver channels operate at 1,000 Mbps with DPA. Without DPA, the receiver channels operate at 840 Mpbs Device Part Numbers Name EP1SGX10C EP1SGX10D EP1SGX25C EP1SGX25D EP1SGX25F EP1SGX40D EP1SGX40G I/O Count (1) 672-Pin FineLine BGA 1,020 Pin FineLine BGA 330 330 426 426 542 542 548 548 Note 1 : The total number of I/O pins for each package described above include dedicated clock pins, and dedicated fast I/O pins. However it does not include High-Speed or the Clock Referance pins for High Speed I/O. Copyright © 2006 Altera Corp. Device Names_Device IO Count Page 29 of 34 What Added voltage value to power pins Added information to the VCCM , they share the same bump with VCCT. Added Non-Migrateble pins Added I/O pin count Added info regarding RREF pin Sent to Product Marketing Connected NC pins to RREF pins( NOTE 1) Connected NC pins to VCCx_Bxx ( NOTE 1 ) Connected unused NC pins on the HSSI side to GND. These pins are listed as NC/GND in this document and are listed as GND* in Quartus II software ( NOTE 1 and 2 ) Added pin status change information from rev 1.3 to rev 1.4. Pin changes are for EP1SGX10C, EP1SGX25C,EP1SGX25D,EP1SGX40 D only. Added section for 1SGX25C missing from 1.4. Changed DATA0 to be an IO after configuration. Note 1: Modifications in Rev 1.4 are recommendations for noise reduction. Do NOT make modifications to the board already laid out based on pin table Rev 1.3 . It is recommended that the pin table Rev 1.4 be implemented for new designs or re-designed boards only. NOTE 2 : GND/NC is shown as GND* in Quartus II software Add HSSI_GND to the pin list Wrong Bank was referenced in the GX25C device Update non-migration table change all references of GX_TX, GX_RX to GXB_TX, GXB_RX Change all references of HSSI_GND to GXB_GND Change pin description data[7..1] to include data0 Changed false references of RUP/RDN to different banks Updated pin description so only CLK0n and CLK2n were dedicated clock inputs. While the rest were also I/Os Updated pin description of VCCINT to expliciltly say it needs a 1.5V supply Updated the pin description for PLLENA Update pin description to explain what to do with unused pins for the transceivers and REFCLKB. Definition for RUnLU needed to be updated to correctly indicate poarity of signal for remote and local update. Also the pin definitions for GND and NC were added to the pin definition. Updated pin descriptions for items 74 though 78 of the pin descriptions. These describe the VCC voltages and the pin description was updated with more specific information as to what voltage to connect them to. Item 42 in the pin desription was updated to specify that the CLK[15..12]p pins are dedicated input clock pins Item 43 in the pin desription was updated to specify that the CLK[15..12]n pins are either clock inputs or regular I/O Item 47 through 50 which describe the PLL_OUT pins are updated to specify that they can be used as either I/O or Output Comment rev 1.2 Date 10/15/2002 rev 1.3 rev 1.3 rev 1.3 rev 1.3 rev 1.3 rev 1.4 12/17/2002 12/17/2002 12/17/200 1/10/2003 2/19/2003 5/30/2003 rev 1.4 5/30/2003 rev 1.4 5/30/2003 rev 1.4 5/30/2003 rev 1.42 7/30/2003 rev 1.43 rev 1.44 rev 1.45 9/10/2003 9/11/2003 9/17/2003 rev 1.46 9/19/2003 rev 1.47 10/21/2003 rev 1.48 12/11/2003 Items 80 through 83 was updated to describe the termination of the unused pins for GX_RX and GX_TX. Copyright © 2006 Altera Corp. Revision Notes Page 30 of 34 Items 85 and 86 was updated to describe the termination of the unused pins for REFCLK. Updated description for unused VREF pins so the it reads the same description as Quartus II Updated description for RREFB. Layout guidelines were added. Updated RREFB pins to address new Quartus change (please refer to the "RREFB pin change in 1.6" worksheet) Deleted DQS for x16 column in EP1SGX10C & EP1SGX10D pin-list Created pin definition for RREFB[15,14]A Added CRC_ERROR pins in pin list Copyright © 2006 Altera Corp. Revision Notes rev 1.49 rev 1.50 3/17/2004 6/2/2004 rev 1.60 4/27/2005 rev 1.70 2/22/2006 Page 31 of 34 EP1SGX40D.Change in 1.4 EP1SGX40D.Change in 1.4 Status in Rev 1.3 NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC Copyright © 2006 Altera Corp. Pin name AL11 AM11 AH11 AJ11 AL9 AM9 AH9 AJ9 AD6 AL7 AM7 AC6 AB6 AC7 AL5 AM5 AH7 AJ7 AM3 AM2 AJ5 AJ4 Y2 Y1 W5 W4 V2 V1 U5 U4 V6 T2 T1 T6 U6 T7 P2 P1 R5 R4 M2 M1 N5 N4 B4 A4 E6 D6 B6 A6 E8 D8 M6 B8 Status in Rev 1.4 GND/NC GND/NC GND/NC GND/NC GND/NC GND/NC GND/NC GND/NC VCCA_B15 GND/NC GND/NC VCCG_B15 GND RREFB15 GND/NC GND/NC GND/NC GND/NC GND/NC GND/NC GND/NC GND/NC GND/NC GND/NC GND/NC GND/NC GND/NC GND/NC GND/NC GND/NC VCCA_B15 GND/NC GND/NC VCCG_B15 GND RREFB15 GND/NC GND/NC GND/NC GND/NC GND/NC GND/NC GND/NC GND/NC GND/NC GND/NC GND/NC GND/NC GND/NC GND/NC GND/NC GND/NC VCCA_B14 GND/NC EP1SGX40D.Change in 1.4 Page 32 of 34 NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC Copyright © 2006 Altera Corp. A8 K6 L6 J7 B10 A10 E10 D10 B12 A12 E12 D12 AA9 AB9 U9 V9 M8 N8 AA8 AB8 U8 V8 M7 N7 AA7 AB7 U7 V7 GND/NC VCCG_B14 GND RREFB14 GND/NC GND/NC GND/NC GND/NC GND/NC GND/NC GND/NC GND/NC VCCP_B15 VCCP_B16 VCCP_B17 VCCP_B18 VCCP_B19 VCCP_B20 VCCR_B15 VCCR_B15 VCCR_B15 VCCR_B15 VCCT_B14 VCCT_B14 VCCT_B15 VCCT_B15 VCCT_B15 VCCT_B15 EP1SGX40D.Change in 1.4 Page 33 of 34 RREFB pin change in 1.6 Device EP1SGX10CF672 Status in Rev 1.5 RREFB15 RREFB15 Pin name Status in Rev 1.6 U7 RREFB15A K7 RREFB15 EP1SGX25CF672 RREFB15 RREFB15 U7 K7 RREFB15 RREFB15A EP1SGX25DF1020 RREFB14 RREFB14 RREFB15 RREFB15 L7 J7 AC7 T8 RREFB14 RREFB14A RREFB15A RREFB15 EP1SGX40DF1020 RREFB14 RREFB15 RREFB15 RREFB15 RREFB14 J7 AC7 T7 T8 L7 RREFB13 RREFB16 GND/NC RREFB15 RREFB14 Copyright © 2006 Altera Corp. RREFB pin change in 1.6 Page 34 of 34