eorex DDR Timing Mode Register and Extended Mode Register Set Cycle CLK, /CLK ~ ~ tIS tIH /CS tIS tIH tIS tIH tIS tIH /RAS /CAS /WE ‘ Low ‘ DSF tIS A0 to A10 BA0,1 CKE tIH Register set data ‘ High ‘ 1 eorex DDR Timing Special Mode Register Set Cycle CLK, /CLK ~ ~ tIS tIH /CS tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH /RAS /CAS /WE DSF A6 A0 to A10 BA0,1 CKE ‘ High ‘ DQS tDS DQ tDH Color Load Color Register 2 eorex DDR Timing Interleaved Bank Read ( BL=4, CL=3 ) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 CLK, /CLK /CS tRC tRC tRC tRC /RAS tRP tRAS tRAS tRAS tRP tRP tRAS /CAS /WE DSF BA0 BA1 tRCD A8 RAa A0 to A10 RAa tRCD tRCD RBb CAw tRCD RAc RBb CBx RBd RAc CAy RAe RBd CBz RAe Precharge Read Active DQM CKE tRPST ‘ High ‘ tDQSCK DQS tDQSCK tDQSCK tRPRE tDQCK tDQCK tDQCK DQ aw0 aw1 aw2 aw3 tRRD tRRD Bank #0 Bank #1 Active Read tRRD Precharge Active cy0 cy1 cy2 cy3 bx0 bx1 bx2 bx3 Active Read Bank #2 ( Idle ) Bank #3 ( Idle ) 3 tRRD Read Precharge Active eorex DDR Timing Interleaved Bank Read ( BL=4, CL=3, Auto Precharge ) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 CLK, /CLK /CS tRC tRC tRC tRC /RAS tRAS tRP tRAS tRAS tRP tRP tRAS /CAS /WE DSF BA0 BA1 tRCD tRCD A8 RAa RBb A0 to A10 RAa CAw RBb tRCD tRCD RAc CBx RBd RAc CAy RAe RBd CBz RAe DQM ‘ High ‘ CKE tDQSCK tDQSCK tDQCK tDQCK tDQSCK DQS tDQCK DQ aw0 aw1 aw2 aw3 tRRD Bank #0 Bank #1 Active bx0 bx1 bx2 bx3 tRRD Read tRRD tRRD Active AP Active cy0 cy1 cy2 cy3 Read Bank #2 ( Idle ) Bank #3 ( Idle ) 4 AP AP Read Active Active Read 23 eorex DDR Timing Interleaved Bank Read ( BL=8, CL=3 ) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 CLK, /CLK /CS /RAS tRAS tRAS tRAS tRAS /CAS /WE DSF BA0 BA1 tRCD tRCD A8 A0 to A10 RAa CAw RBb RDd RCc RBb RAa tRCD tRCD CBx RCc CCy RDd CDz DQM ‘ High ‘ CKE DQS DQ aw0 aw1 aw2 aw3 aw4 aw5 aw6 aw7 tRRD tRRD Bank #0 Bank #1 Active Active cy0 cy1 cy2 cy3 cy4 cy5 cy6 cy7 tRRD Precharge Read Precharge Read Active Bank #2 Bank #3 bx0 bx1 bx2 bx3 bx4 bx5 bx6 bx7 Read Precharge Active Precharge 5 Read dz0 dz1 dz2 dz3 dz4 dz5 eorex DDR Timing Interleaved Bank Read ( BL=8, CL=3, Auto Precharge ) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 CLK,/CLK /CS /RAS tRAS tRAS tRAS tRAS /CAS /WE DSF BA0 BA1 tRCD A8 A0 to A10 tRCD RAa RBb RBc RBd RAa CAw RBb CBx RBc CCy RBd CDd DQM ‘ High ‘ CKE DQS DQ aw0 aw1 aw2 aw3 aw4 aw5 aw6 aw7 tRRD Bank #0 Bank #1 Bank #2 Active tRRD Read Active bx0 bx1 bx2 bx3 bx4 bx5 bx6 bx7 cy0 cy1 cy2 cy3 cy4 cy5 cy6 cy7 dz0 dz1 dz2 dz3 dz4 dz5 dz6 dz7 tRRD AP AP Read Active AP Read Bank #3 Active 6 Read AP 22 23 eorex DDR Timing Interleaved Bank Write ( BL=8 ) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 CLK,/CLK /CS tRC /RAS tRAS tRP /CAS tRCD tRCD tRCD tRCD tRCD /WE DSF BA0 BA1 A8 A0 to A10 RAa RBb RCc RDd RAa RAa CAw RBb CBx RCc CCy RDd CDz RAa CAw DQM tDS tDH CKE ‘ High ‘ DQS DQ aw0 aw1 aw2 aw3 aw4 aw5 aw6 aw7 tRRD Bank #0 Bank #1 Bank #2 Active bx0 bx1 bx2 bx3 bx4 bx5 bx6 bx7 tRRD dz0 dz1 dz2 dz3 dz4 dz5 dz6 dz7 aw0 aw1 aw2 aw3 aw4 aw5 aw6 aw7 tRRD Pre charge Write Active cy0 cy1 cy2 cy3 cy4 cy5 cy6 dz7 Active Active Precharge Write Bank #3 Active 7 Write PreCharge Write Write Precharge eorex DDR Timing Interleaved Bank Write ( BL=8, Auto Precharge ) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 CLK,/CLK /CS tRC /RAS tRAS tRP tRAS /CAS tDQSS /WE DSF BA0 BA1 A8 A0 to A10 RAa RBb RCc RDd RAa RAa CAw RBb CBx RCc CCy RDd CDz RAa CAw DQM tDS tDH CKE ‘ High ‘ DQS DQ aw0 aw1 aw2 aw3 aw4 aw5 aw6 aw7 tRRD Bank #0 Bank #1 Bank #2 Active bx0 bx1 bx2 bx3 bx4 bx5 bx6 bx7 tRRD tRRD dz0 dz1 dz2 dz3 dz4 dz5 dz6 dz7 aw0 aw1 aw2 aw3 aw4 aw5 aw6 aw7 tRRD AP Write Active cy0 cy1 cy2 cy3 cy4 cy5 cy6 dz7 Write Active AP Write Active AP Write Bank #3 Active 8 Write AP eorex DDR Timing Page Mode Read / Write ( BL=8, CL=3 ) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 CLK,/CLK /CS tRAS tRP /RAS /CAS tDQSS tDQSS /WE DSF BA0 BA1 tRCD A8 A0 to A10 RAa RAa CAy CAx DQM tDS tDH ‘ High ‘ twPST CKE tDPL DQS twPRES DQ Bank #0 ax0 ax1 ax2 ax3 ax4 ax5 Active Read Burst stop ay0 ay1 ay2 ay3 ay4 ay5 ay6 ay7 Write Bank #1 Bank #2 ( Idle ) Bank #3 ( Idle ) 9 Precharge 23 eorex DDR Timing Page Mode Write/Read ( BL = 4, CL = 3 ) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 CLK./CLK tCCD /CS tRAS tRP tRP tRAS /RAS /CAS /WE DSF BA0 BA1 A8 RAa RBb A0 to A10 RAa RBb CAw CBx DQM ‘High ‘ CKE DQS tCDLR DQ bx0 bx1 bx2 bx3 aw0 aw1 aw2 aw3 tRRD Bank #0 Bank #1 Write Active Active Precharge Read Bank #2 ( Idle ) Bank #3 ( Idle ) 10 Precharge 22 23 eorex DDR Timing Auto Precharge Read ( BL=4, CL=3) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 CLK,/CLK /CS tRC tRC /RAS tRAS tRP tRAS tRP /CAS /WE DSF BA0 BA1 tRCD A8 RAa A0 to A10 RAa tRCD RAb CAw RAb CAx DQM CKE ‘ High ‘ tDQSCK tDQSCK tDQCK tDQCK DQS DQ Bank #0 aw0 aw1 aw2 aw3 Active Read AP by0 by1 by2 by3 Active Bank #1 ( Idle ) Bank #2 ( Idle ) Bank #3 ( Idle ) 11 Read AP 23 eorex DDR Timing Auto Precharge Write ( BL=4 ) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 CLK,/CLK /CS tRC tRC /RAS tRAS tRP tRAS tRP /CAS /WE DSF BA0 BA1 tRCD A8 RAa A0 to A10 RAa tRCD RAc RAb CAw RAb RAc CAx DQM CKE DQS DQ Bank #0 bx0 bx1 bx2 bx3 aw0 aw1 aw2 aw3 Active Write AP Active Bank #1 ( Idle ) Bank #2 ( Idle ) Bank #3 ( Idle ) 12 Write AP Active 23 eorex DDR Timing Block Write ( Auto Precharge ) 0 1 2 3 4 5 6 7 8 9 10 11 CLK,/CLK /CS /RAS /CAS tRCD tBWC /WE DSF BA0 BA1 A8 RAa RBb A0 to A10 RAa RBb CAx CBy DQM tDS tDH CKE ‘ High ‘ DQS tBPL DQ Bank #0 Active Bank #1 BW Active Mask Precharge AP BW Bank #2 ( Idle ) Bank #3 ( Idle ) Note: Column address 0-3 are ignored 13 12 13 14 15 16 17 18 19 20 21 22 23 eorex DDR Timing Power Down Mode 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 CLK,/CLK /CS /RAS /CAS /WE DSF DSF BA A8 A0 to A10 RAa RAa CAw RAa RAa CAx Active Read DQM CKE tIS tIS tIS tIS DQS aw0 aw1 aw2 aw3 DQ Pre-charge Standby Power Down Mode Active Standby Power Down Mode Bank #0 Active Read Precharge Bank #1( Idle ) Bank #2 ( Idle ) Bank #3 ( Idle ) 14 23 eorex DDR Timing Power Up Sequence & Auto Refresh (CBR) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CLK,/CLK ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ /CS /WE DSF BA0 BA1 ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ /CAS ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ /RAS A8 ~ ~ ‘ High ‘ ~ ~ ~ ~ CKE ‘ High ‘ ~ ~ ~ ~ ~ ~ ~ ~ DQS ~ ~ ~ ~ ~ ~ ~ ~ DQM ~ ~ ~ ~ ~ ~ A0 to A10 ‘ High ‘ Z ~ ~ ~ ~ ~ ~ ~ ~ DQ ‘ High ‘ Z tRFC tRFC tRFC Minimum 200 Cycle tMRD Any Command Inputs must be stable For 200us 1st Auto Refresh Command Precharge Command All Bank Mode Resister Extended Mode Resister Set Command Set Command With DLL Reset 2nd Auto Refresh Command ＊Minimum of 2 Refresh Cycles are required ＊ 15 20 21 22 23 eorex DDR Timing Auto Refresh Cycle 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 CLK,/CLK tRP tRFC tRFC /CS /RAS /CAS /WE DSF BA0 BA1 A8 A0 to A10 DQM CKE ‘ High ‘ DQ Auto Refresh (Arbitary Cycle) All Banks Precharge Auto Refresh 16 22 23 eorex DDR Timing Self Refresh Cycle 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 ~ ~ ~~ ~ ~ ~ ~ ~ ~ ~ ~ ~~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ CLK,/CLK /CS tRP /RAS /CAS /WE DSF BA0 BA1 A8 A0 to A10 DQM tIS tIS CKE ~ ~ DQS ~ ~ tIS ~ ~ DQ Minimum 200 Cycle Self Refresh Cycle No Operation Cycle All Banks Precharge Self Refresh Entry Arbitrary Cycle 17