MYX4DDR4256M16GE MYX4DDR364M16JT 4Gb - 256M x 16 DDR4 SDRAM Advanced information. Subject to change without notice. 1Gb - 64M x 16 DDR3 SDRAM Advanced information. Subject to change without notice. Features • Per-DRAM addressability • Tin-lead ball metalurgy Features • Connectivity test (x16) • VDD = VDDQ = 1.2V ±60mV • Tin-lead ball metallurgy Code • Post Options package repair (PPR) and soft post package • VPP = 2.5V, –125mV/+250mV • VDD = VDDQ = 1.35V (1.283-1.45V) repair (sPPR) modes • On-die, internal, adjustable VREFDQ generation • Configuration • Backward-compatible to VCC = VCCQ = 1.5V • JEDEC JESD-79-4 compliant • 1.2V pseudo open-drain I/O ±0.075V 64M x 16 64M16 • TC of 0°C to • 95°C 1.35V center-terminated push/pull I/O • Package: FBGA (Sn63 Pb37 solder) BG – 64ms, 8192-cycle refresh at 0°C to 85°C • Differential bidirectional data strobe Options Code • 8n-bit prefetch architecture – 32ms at 85°C to 95°C Footprint: 96-ball (8mm x 14mm) TW • Configuration • Differential inputs CK#)each • 8 internal banks (x16): 2clock groups of 4(CK, banks Timing - cycle time • •256M x 16 256M16 • 8 architecture internal banks • 8n-bit prefetch 1.5ns @ CL = 13 (DDR3-1866) -107 • Nominal and dynamic on-die termination (ODT) for • Programmable data strobe preambles • Package: FBGA (Sn63 Pb37 solder) BG data, strobe, and mask signals • Data strobe preamble training • •Foorprint: 96-ball (9mm x 14mm) GE Operating temperature • Programmable CAS READ latency (CL) • Command/Address latency (CAL) Industrial (-40°C ≤ TC ≤ +95°C) IT • Programmable CAS ADDITIVE latency (AL) • Timing - cycle time • Multipurpose register READ and WRITE capability • Programmable CAS WRITE latency (CWL) Enhanced ≤ TC ≤ +105°C) ET 75E • 0.750ns @ CL(-40°C = 18(DDR4-2666) • Write and read leveling • Fixed burst length (BL) of 8 and burst chop (BC) of • Self refresh mode • Part Marking: Label (L), Dot (D) 4 (via the mode register set [MRS]) • Operating temperature • Industrial (-40°C ≤ TC ≤ +95°C) IT • Low-power• auto self refresh (LPASR) Selectable BC4 or BL8 on-the-fly (OTF) • Temperature • controlled Self refreshrefresh mode (TCR) • Part Marking: Label (L), Dot (D) • TCrefresh of -40°C to 105°C • Fine granularity 64ms, 8192 cycle refresh at -40°C to 85°C • Self refresh abort • Maximum power 32ms, saving8192 cycle refresh at 85°C to 105°C • Automatic • Output driver calibrationself refresh (ASR) • Write • Nominal, park, andleveling dynamic on-die termination (ODT) • Multipurpose register • Data bus inversion (DBI) for data bus • Output driver calibration • Command/Address (CA) parity • Databus write cyclic redundancy check (CRC) Table 1: Key Table Timing 1: Parameters Key Timing Parameters tRCD-tRP-CL tRCD (ns) Data Rate (MT/s) Target tRCD-tRP-CL Speed Grade Speed Grade Data Rate (MT/s) Target -75E -107 1866 2666 18-18-18 13-13-13 *Backward compatible to 1600, CL = 11; 1866, CL = 13; 2133, CL = 15; and 2400, CL = 17. tRCD (ns) tRP (ns) 13.5 tRP (ns) CL (ns) CL (ns) 13.91 Micron Part. No. MT41K64M16TW-107AIT:J for the IT temp version Micron Part No. MT41K64M16TW-107AAT:J for the ET temp version Micron Part No. MT40A256M16GE-075E IT:B Revision 1.1 Micross US (Americas) 407.298.7100 • Micross UK (EMEA & ROW) +44 (0) 1603 788967 • [email protected] • www.micross.com November 16, 2015 • Revision 2.1 February 4, 2016 • 7725 N. Orange Blossom Trail • Orlando, FL 32810 • 407.298.7100 • [email protected] • www.micross.com Form #: CSI-D-686 Document 007 Form #: CSI-D-686 Document: 020 4Gb - 256M x 16 DDR44Gb: SDRAM x4, x8, x16 DDR4 SDRAM Advanced information. Subject to change without notice.Ball Assignments Figure 2: 96-Ball x16 Ball Assignments Figure 1: 96-Ball FBGA (Top View), TW 1 2 3 VDDQ VSSQ VPP 4 5 6 7 8 9 DQ8 UDQS_c VSSQ VDDQ VSS VDD UDQS_t DQ9 VDD VDDQ DQ12 DQ10 DQ11 DQ13 VSSQ VDD VSSQ DQ14 DQ15 VSSQ VDDQ VSS NF/UDM_n/ UDBI_n VSSQ NF/LDM_n/ LDBI_n VSSQ VSS VSSQ VDDQ LDQS_c DQ1 VDDQ ZQ VDDQ DQ0 LDQS_t VDD VSS VDDQ VSSQ DQ4 DQ2 DQ3 DQ5 VSSQ VDD VDDQ DQ6 DQ7 VDDQ VDD VSS CKE ODT CK_t CK_c VSS A A B B C C D D E E F F G G H H J J K K L L VDD WE_n/A14 ACT_n M M VREFCA BG0 A12/BC_n CAS-n/A15 VSS A10/AP N Figure 6: 96-Ball FBGA – x16 "GE" V A4 BA0 SS N A3 BA1 TEN A1 A5 ALERT_n A9 A7 VPP P P RESET_n A6 A0 VDD A8 A2 0.155 R R T PDF: 09005aef84af6dd0 4gb_ddr4_dram.pdf - Rev. E 11/15 EN PAR A11 NC 20 A 12 CTR 0.12 A 1.8 CTR Nonconductive overmold 0.8 TYP Ball A1 ID (covered by SR) Ball A1 ID Notes: 1. All dimensions are in millimeters. 2. Solder ball material: Sn63/Pb37 3. Micron – MT40A256M16 3 2 1 12 CTR 0.8 TYP 0.8 TYP 0.8 TYP 6.4 CTR A B C D E F G H J K L M N P R T Ball A1 ID A B C D E F G H J K L M N P R T 14 ±0.1 Seating plane 14 ±0.1 0.12 A © 2014 Micron Technology, Inc. All rights reserved. Package Dimensions 0.155 9 8 7 A VDD A13 1.8 CTR Notes: 1. See Ball Descriptions. Nonconductive 2. A slash “/” defines a selectable function. For example: Ball E7 = NF/LDM_n. If data mask overmold is enabled via the MRS, ball E7 = LDM_n. If data mask is disabled in the MRS, E7 = NF (no function). 3. Address 96X bits (including bank groups) are density- and configuration-dependent (see AdØ0.47 dressing). Dimensions apply Ball A1 ID to solder balls post(covered by SR) reflow on Ø0.42 SMD ballx8, pads. 9 8 7 Micron Technology, 3 2 Inc. 1 reserves the right to change products or specifications without notice. 4Gb: x4, x16 DDR4 SDRAM ure 6: 96-Ball FBGA – x16 "GE" 96X Ø0.47 Dimensions apply to solder balls postreflow on Ø0.42 SMD ball pads. Seating plane T VSS Figure 2: Package Dimensions 96-Ball FBGA Package - x16 (TW) 4Gb: x4, x8, x16 DDR4 SDRAM Package Dimensions CS_n RAS_n/A16 VDD 1.1 ±0.1 0.29 MIN 9 ±0.1 Notes: 1. All dimensions are in millimeters. 2. Solder ball material: SAC305 (Pb-free 96.5% Sn, 3% Ag, 0.5% Cu). 7725 N. Orange Blossom Trail, Orlando, FL 32810 407.298.7100 • [email protected] • www.micross.com 1.1 ±0.1