5420xL_ND14006E00

5420xL series
VCXO Module ICs with Built-in Varicap
OVERVIEW
The 5420xL series are LV-PECL output VCXO ICs that provide a wide frequency pulling range. They employ bipolar oscillator circuit and
recently developed varicap diode fabrication process that provides a low phase noise characteristic and a wide frequency pulling range
without any external components. Current consumption of the 5420xL series is reduced, it contributes to reduction of power consumption
in applications.
FEATURES
▪ VCXO with recently developed varicap diode built-in
▪ -40 to +105°C operating temperature range
▪ Oscillator: Fundamental frequency oscillation
▪ Differential LV-PECL output
▪ Output frequency (fOUT): 100 to 250MHz
▪ Output enable (OE) active selectable function
▪ Operating supply voltage range: 2.97 to 3.63V
Selectable Hi-Active or Low-Active by bonding wire
▪ Oscillator frequency range (for fundamental oscillation):
▪ Output terminal on standby state
100 to 170MHz (BL version)
OUT: VOH (DC), OUTN: VOL (DC)
150 to 200MHz (CL version)
200 to 250MHz (DL version)
▪ Wide frequency pulling range (typ)
±[email protected] version, VC=1.65±1.65V, fOUT=122.88MHz (γ=330, C0=1.6pF)
±[email protected] version, VC=1.65±1.65V, fOUT=155.52MHz (γ=330, C0=1.5pF)
* DL version: TBD
▪ Low phase noise (typ): [email protected] version, 1kHz Offset, fOUT=122.88MHz (γ=330, C0=1.6pF)
[email protected] version, 10MHz Offset, fOUT=122.88MHz
[email protected] version, 1kHz Offset, fOUT=155.52MHz (γ=330, C0=1.5pF)
[email protected] version, 10MHz Offset, fOUT=155.52MHz
* DL version: TBD
APPLICATIONS
Base station, SONET/SDH, Ethernet, Fibre Channel, LTE
SERIES CONFIGURATION
Version Name
Recommended operating frequency range
(fOSC)*1 [MHz]
Output frequency (fOUT)
5420BL
100MHz to 170MHz
fOSC
5420CL
150MHz to 200MHz
fOSC
200MHz to 250MHz
fOSC
*2
(5420DL)
*1. The recommended oscillation frequency is a yardstick value derived from the resonator used for NPC characteristics authentication. However, the
oscillation frequency range is not guaranteed. Specifically, the characteristics can vary greatly due to resonator characteristics and mounting conditions, so
the oscillation characteristics of components must be carefully evaluated.
The recommended characteristics for the crystal element are:
R1 < 20Ω, C0 < 1.5pF
*2. The version name in parentheses has been developed.
ORDERING INFORMATION
Device
Package
WF5420xL-4
Wafer form
CF5420xL-4
Chip form
Version name
WF5420□L-4
Form WF: Wafer form
CF: Chip(Die) form
Oscillation frequency range
B:100~170MHz
C:150~200MHz
SEIKO NPC CORPORATION - 1
5420xL series
PAD LAYOUT
(Unit: μm)
(700,475)
VDD OUTN
OUT
9
1
XT
Y
XTN
8
7
(0,0)
2
3
(-700,-475)
4 5
VC OEN OE
6
VSS
X
Chip size: 1.4mm×0.95mm
Chip thickness: 130μm
PAD size: 80μm×80μm (PAD No.1, 2, 3, 4, 5 pins)
110μm×80μm (PAD No.7, 8, 9 pins)
80μm×110μm (PAD No.6 pins)
Chip base: VSS potential
PIN DESCRIPTION and PAD COORDINATES
No.
Pin
I/O*1
1
XT
I
2
XTN
O
3
VC
I
4
OEN
5
Description
Pad Coordinates (Unit : μm)
X
Y
-595.0
116.0
-595.0
-159.0
Control voltage input pin
-200.2
-370.0
I
Output enable input pin (built-in pull-down resistor)
-12.4
-370.0
OE
I
Output enable input pin (built-in pull-up resistor)
156.2
-370.0
6
VSS
-
(-) ground
595.0
-355.0
7
OUT
O
Clock output pin (differential output)
554.1
370.0
8
OUTN
O
Clock output pin (differential reversing output)
324.3
370.0
9
VDD
-
(+) supply voltage
99.5
370.0
Crystal connection pin
*1.I: input, O: output
SEIKO NPC CORPORATION - 2
5420xL series
BLOCK DIAGRAM
VDD
RPU
OE
OEN
RPD
XT
CVC1
XTN
OUT
RVC1
OSC
Level
Shifter
Prebuf
OUTN
RVC2
CVC2
VSS
VC
The CF5420xL/WF5420xL incorporated standard PECL output schemes, which are un-terminated emitters.
SEIKO NPC CORPORATION - 3
5420xL series
SPECIFICATIONS
Absolute Maximum Ratings
VSS=0V
Parameter
Symbol
Condition
Rating
Unit
-0.3 to +5.0
V
XT, OE, OEN, VC pins
-0.3 to VDD+0.3
V
XTN, OUT, OUTN pins
-0.3 to VDD+0.3
V
*1
VDD
VDD pins
*1*2
VIN
Output voltage range
VOUT
Junction temperature*3
Tj
Supply voltage range
Input voltage range
*1*2
Storage temperature range*4
TSTG
Wafer, Chip form
+125
°C
-55 to +125
°C
*1. This parameter rating is the values that must never exceed even for a moment. This product may suffer breakdown if this parameter rating is exceeded.
Operation and characteristics are guaranteed only when the product is operated at recommended operating conditions.
*2. VDD is a VDD value of recommended operating conditions.
*3. Do not exceed the absolute maximum ratings. If they are exceeded, a characteristic and reliability will be degraded.
*4. When stored in nitrogen or vacuum atmosphere applied to IC itself only (excluding packaging materials).
Recommended Operating Conditions
VSS=0V
Parameter
Symbol
Conditions
Operating supply voltage
VDD
Between VDD and VSS pins*2
Input voltage
VIN
OE, OEN, VC pins
Operating temperature
Ta
Output load
RL
*1
Oscillator frequency range
Output frequency range
fOSC
fOUT
Rating
Unit
MIN
TYP
MAX
2.97
3.3
3.63
V
0
-
VDD
V
-40
-
+105
°C
Terminated to VDD-2V
49.5
50.0
50.5
Ω
5420BL
100
-
170
5420CL
150
-
200
5420DL
200
-
250
5420BL
100
-
170
5420CL
150
-
200
5420DL
200
-
250
MHz
MHz
*1. The oscillation frequency is a yardstick value derived from the crystal used for NPC characteristics authentication. However, the oscillation frequency
range is not guaranteed. Specifically, the characteristics can vary greatly due to crystal characteristics and mounting conditions, so the oscillation
characteristics of components must be carefully evaluated.
*2. Mount a ceramic chip capacitor that is larger than 0.01μF proximal to IC (within approximately 3mm) between VDD and VSS in order to obtain stable
operation of 5420xL series. In addition, the wiring pattern between IC and capacitor should be as wide as possible.
Note. Since it may influence the reliability if it is used out of range of recommended operating conditions, this product should be used within this range.
SEIKO NPC CORPORATION - 4
5420xL series
Electrical Characteristics
BL version
VDD=2.97 to 3.63V, VC=0.5VDD, VSS=0V, Ta= -40 to +105°C unless otherwise noted.
Parameter
Symbol
Rating
Conditions
MIN
TYP
MAX
Unit
Current consumption1
IDD1
measurement circuit 1, terminated to VDD-2V,
OE,OEN=Open
-
49
60
mA
Current consumption2
IDD2
measurement circuit 1, terminated to VDD-2V,
OE=Low or OEN=High
oscillator: operating, output: DC(VOH, VOL)
-
49
60
mA
VDD
-1.025
VDD
-1.085
VDD
-0.950
VDD
-1.005
VDD
-0.880
VDD
-0.880
V
OUT/OUTN pins
VDD
-1.810
VDD
-1.700
VDD
-1.620
V
High-level output voltage
(DC level)
Low-level output voltage
(DC level)
VOH
VOL
measurement circuit 2,
OUT/OUTN pins
Ta=0 to +105°C
Ta=-40 to 0°C
measurement circuit 2,
High-level input voltage
VIH
measurement circuit 3, OE/OEN pins
0.7VDD
-
-
V
Low-level input voltage
VIL
measurement circuit 3, OE/OEN pins
-
-
0.3VDD
V
Pull-up resistance
RPU
measurement circuit 3, OE pin
50
100
200
kΩ
Pull-down resistance
RPD
measurement circuit 3, OEN pin
50
100
200
kΩ
Oscillator block built-in
RVC1
Between VC and XT, measurement circuit 4
100
200
300
resistance
RVC2
Between VC and XTN, measurement circuit 4
100
200
300
Input leakage resistance*1
RVIN
VC pin, Ta=+25°C, measurement circuit 5
10
-
-
VC =0.3V
3.92
4.36
4.80
CVC1
Confirmed by acceptance sampling
using wafer monitor pattern.
Design value, excluding parasitic
capacitance
VC =1.65V
2.35
2.76
3.17
VC =3.0V
1.20
1.50
1.80
VC =0.3V
5.88
6.53
7.18
VC =1.65V
3.51
4.13
4.75
VC =3.0V
1.80
2.25
2.70
25
50
-
*1
Oscillator block built-in
capacitance
CVC2
Confirmed by acceptance sampling
using wafer monitor pattern.
Design value, excluding parasitic
capacitance
-3dB frequency, Ta=+25°C, design value
VDD=3.3V, VC=1.65V±1.65V,
frequency
measurement circuit 8, Crystal : 122.88MHz
*1. These prescriptions indicate the following contents.
Oscillator block built-in resistance: Resistance between VC-XT or VC-XTN
Input leakage resistance: Resistance between VC-VDD or VC-VSS (DC characteristic)
Refer to “VC Terminal Input Impedance”. (Page. 23)
Maximum modulation
FM
kΩ
MΩ
pF
pF
kHz
SEIKO NPC CORPORATION - 5
5420xL series
CL version
VDD=2.97 to 3.63V, VC=0.5VDD, VSS=0V, Ta= -40 to +105°C unless otherwise noted.
Parameter
Symbol
Rating
Conditions
MIN
TYP
MAX
Unit
Current consumption1
IDD1
measurement circuit 1, terminated to VDD-2V,
OE,OEN=Open
-
50
60
mA
Current consumption2
IDD2
measurement circuit 1, terminated to VDD-2V,
OE=Low or OEN=High
oscillator: operating, output: DC(VOH, VOL)
-
50
60
mA
VDD
-1.025
VDD
-1.085
VDD
-0.950
VDD
-1.005
VDD
-0.880
VDD
-0.880
V
OUT/OUTN pins
VDD
-1.810
VDD
-1.700
VDD
-1.620
V
High-level output voltage
(DC level)
Low-level output voltage
(DC level)
VOH
VOL
measurement circuit 2,
OUT/OUTN pins
Ta=0 to +105°C
Ta=-40 to 0°C
measurement circuit 2,
High-level input voltage
VIH
measurement circuit 3, OE/OEN pins
0.7VDD
-
-
V
Low-level input voltage
VIL
measurement circuit 3, OE/OEN pins
-
-
0.3VDD
V
Pull-up resistance
RPU
measurement circuit 3, OE pin
50
100
200
kΩ
Pull-down resistance
RPD
measurement circuit 3, OEN pin
50
100
200
kΩ
Oscillator block built-in
RVC1
Between VC and XT, measurement circuit 4
100
200
300
resistance*1
RVC2
Between VC and XTN, measurement circuit 4
100
200
300
Input leakage resistance*1
RVIN
VC pin, Ta=+25°C, measurement circuit 5
10
-
-
VC =0.3V
3.92
4.36
4.80
CVC1
Confirmed by acceptance sampling
using wafer monitor pattern.
Design value, excluding parasitic
capacitance
VC =1.65V
2.35
2.76
3.17
VC =3.0V
1.20
1.50
1.80
VC =0.3V
5.88
6.53
7.18
VC =1.65V
3.51
4.13
4.75
VC =3.0V
1.80
2.25
2.70
25
50
-
Oscillator block built-in
capacitance
CVC2
Confirmed by acceptance sampling
using wafer monitor pattern.
Design value, excluding parasitic
capacitance
-3dB frequency, Ta=+25°C, design value
VDD=3.3V, VC=1.65V±1.65V,
frequency
measurement circuit 8, Crystal : 155.52MHz
*1. These prescriptions indicate the following contents.
Oscillator block built-in resistance: Resistance between VC-XT or VC-XTN
Input leakage resistance: Resistance between VC-VDD or VC-VSS (DC characteristic)
Refer to “VC Terminal Input Impedance” (Page. 23).
Maximum modulation
FM
kΩ
MΩ
pF
pF
kHz
SEIKO NPC CORPORATION - 6
5420xL series
DL version (TBD)
VDD=2.97 to 3.63V, VC=0.5VDD, VSS=0V, Ta= -40 to +105°C unless otherwise noted.
Parameter
Symbol
Rating
Conditions
MIN
TYP
MAX
Unit
Current consumption1
IDD1
measurement circuit 1, terminated to VDD-2V,
OE,OEN=Open
-
(54)
(75)
mA
Current consumption2
IDD2
measurement circuit 1, terminated to VDD-2V,
OE=Low or OEN=High
oscillator: operating, output: DC(VOH, VOL)
-
(54)
(75)
mA
VDD
-1.025
VDD
-1.085
VDD
-0.950
VDD
-1.005
VDD
-0.880
VDD
-0.880
V
OUT/OUTN pins
VDD
-1.810
VDD
-1.700
VDD
-1.620
V
High-level output voltage
(DC level)
Low-level output voltage
(DC level)
VOH
VOL
measurement circuit 2,
OUT/OUTN pins
Ta=0 to +105°C
Ta=-40 to 0°C
measurement circuit 2,
High-level input voltage
VIH
measurement circuit 3, OE/OEN pins
0.7VDD
-
-
V
Low-level input voltage
VIL
measurement circuit 3, OE/OEN pins
-
-
0.3VDD
V
Pull-up resistance
RPU
measurement circuit 3, OE pin
50
100
200
kΩ
Pull-down resistance
RPD
measurement circuit 3, OEN pin
50
100
200
kΩ
Oscillator block built-in
RVC1
Between VC and XT, measurement circuit 4
100
200
300
resistance*1
RVC2
Between VC and XTN, measurement circuit 4
100
200
300
Input leakage resistance*1
RVIN
VC pin, Ta=+25°C, measurement circuit 5
10
-
-
VC =0.3V
(3.92)
(4.36)
(4.80)
CVC1
Confirmed by acceptance sampling
using wafer monitor pattern.
Design value, excluding parasitic
capacitance
VC =1.65V
(2.35)
(2.76)
(3.17)
VC =3.0V
(1.20)
(1.50)
(1.80)
VC =0.3V
(5.88)
(6.53)
(7.18)
VC =1.65V
(3.51)
(4.13)
(4.75)
VC =3.0V
(1.80)
(2.25)
(2.70)
25
50
-
Oscillator block built-in
capacitance
CVC2
Maximum modulation
frequency
FM
Confirmed by acceptance sampling
using wafer monitor pattern.
Design value, excluding parasitic
capacitance
-3dB frequency, Ta=+25°C, design value
VDD=3.3V, VC=1.65V±1.65V,
measurement circuit 8, Crystal : 245.76MHz
kΩ
MΩ
pF
pF
kHz
Values in parentheses ( ) are temporary.
*1. These prescriptions indicate the following contents.
Oscillator block built-in resistance: Resistance between VC-XT or VC-XTN
Input leakage resistance: Resistance between VC-VDD or VC-VSS (DC characteristic)
Refer to “VC Terminal Input Impedance” (TBD) (Page. 23).
SEIKO NPC CORPORATION - 7
5420xL series
Switching Characteristics
VDD = 2.97 to 3.63V, VC=0.5VDD, VSS= 0V, Ta = -40 to +105°C unless otherwise noted
Parameter
Symbol
Duty1
Duty cycle
Duty2
Output amplitude
VOPP
Output rise time
tr
Output fall time*1
tf
TYP
MAX
45
50
55
%
45
50
55
%
0.4
-
-
V
-40 to 90°C
-
0.3
0.5
measurement circuit 6
90 to 105°C
-
-
0.7
80% to 20% of output amplitude
-40 to 90°C
-
0.3
0.5
90 to 105°C
-
-
0.7
Measured at output cross point
Ta=25°C,VDD=3.3V, measurement circuit 6
Measured at 50% of output amplitude
Ta=25°C,VDD=3.3V, measurement circuit 6
Peak to peak of output waveform
Single-ended output signal, measurement circuit 6
ns
Single-ended output signal,
ns
Single-ended output signal,
measurement circuit 6
*2
Unit
MIN
20% to 80% of output amplitude
*1
Rating
Conditions
Output enable propagation delay
tOE
Ta=25°C, design value, measurement circuit 7
-
-
20
μs
Output disable propagation delay
tOD
Ta=25°C, design value, measurement circuit 7
-
-
200
ns
*1. Output rise time and output fall time may vary depending on measurement environment.
*2. Rating may vary depending on the power supply used, values of bypass capacitors, and other factors.
Note. The ratings are measured by using the NPC standard crystal and jig. They may vary due to crystal characteristics, so they must be carefully evaluated.
The recommended crystal element characteristics are R1 < 20Ω and C0 < 1.5pF.
SEIKO NPC CORPORATION - 8
5420xL series
Timing chart
[Used OE pin]
tPER
OUTN
OUT端子
tW
×100 (%) @Crossing Point
Duty1 = t
PER
tW
×100 (%) @50% Waveform
Duty2 = t
PER
tW
80% 80%
VOPP
OUT
OUTN端子
20%
DC
20%
tr
tf
VT
(VDD-2V)
tOD*1
OE
OE端子
OE Input Signal tr(OE) = tf(OE)<10ns
VIH
VIL
VDD
tOE*1
0V
*1. On an OE falling edge, the outputs go DC output state after the output disable propagation delay (tOD) has elapsed.
On an OE rising edge, the output starts after the output enable propagation delay (tOE) has elapsed.
[Used OEN pin]
tW
×100 (%) @Crossing Point
tPER
tW
×100 (%) @50% Waveform
Duty2 = t
PER
Duty1 =
tPER
OUT端子
OUTN
tW
80% 80%
DC
VOPP
OUT
OUTN端子
OEN端子
OEN
20%
20%
tr
tf
VT
(VDD-2V)
VIH
OEN Input Signal tr(OE) = tf(OE)<10ns
tOD*2
VDD
VIL
tOE*2
0V
*2: On an OEN rising edge, the outputs go DC output state after the output disable propagation delay (tOD) has elapsed.
On an OEN falling edge, the output starts after the output enable propagation delay (tOE) has elapsed.
SEIKO NPC CORPORATION - 9
5420xL series
FUNCTIONAL DESCRIPTION
OE Function
OE pin
Oscillator
Output
High/Open
Operating
Operating
Low
Operating
DC output
(built-in pull-up resistor)
During standby, OUT terminal is VOH level, OUTN is VOL level.
OEN Function
OEN pin
Oscillator
Output
Low/Open
Operating
Operating
High
Operating
DC output
(built-in pull-down resistor)
During standby, OUT terminal is VOH level, OUTN is VOL level.
When OE is set Low and OEN is set High, it gets NPC test mode.
Oscillation Start-up Detector Function
An oscillator startup detection circuit is built-in. The circuit disables the OUT/OUTN outputs until the oscillator starts. This
function prevents unstable oscillation and other problems, which can occur when power is applied, from appearing at the output.
Boot Function
At the time of oscillation starting, XTN pin potential is made into the VDD level. It makes negative resistance enlarged and it becomes easy
to start oscillation. Beware that a current flows into VC pin until it starts oscillation, when XTN pin is VDD level and the voltage below VDD
level is being applied to VC pin.
A boot function is canceled after an oscillation start.
SEIKO NPC CORPORATION - 10
5420xL series
MEASUREMENT CIRCUITS
These are measurement circuits for electrical characteristics and switching characteristics.
■ Note: Bypass capacitors specified in each measurement circuit below should be connected between VDD, VT and VSS. Load resistance
specified in each measurement circuit below should be connected to OUT and OUTN pins (excluding measurement circuit 4, 5).
Circuit wiring of bypass capacitors and load resistance should be connected as short as possible (within approximately 3mm). If
the circuit wiring is long, the required characteristics may not be realized. Also, if the values of bypass capacitors and load
resistance differ from the description in this document or are not connected, the required characteristics may not be realized.
Capacitor and resistor values used by NPC
Capacitors: 0.01μF GRM188B11H103K (Murata Manufacturing Co., Ltd.)
Resistors: 49.9Ω RN732ATTD49R9B25 (KOA Corporation)
MEASUREMENT CIRCUIT 1
Measurement Parameters: IDD1, IDD2
IDD1,IDD2
A
0.01μF(Ceramic Chip Capacitor)
VDD
XTN
OUT
5420xL
XT
VC
OE OEN
49.9Ω V
T
49.9Ω
OUTN
VDD-2V
VSS
0.01μF(Ceramic Chip Capacitor)
IDD1:OE=Open and OEN=Open
IDD2: (OE=Low and OEN=Open)
or (OE=Open and OEN=High)
SEIKO NPC CORPORATION - 11
5420xL series
MEASUREMENT CIRCUIT 2
Measurement Parameters: VOH, VOL
0.01μF(Ceramic Chip Capacitor)
0.01μF(Ceramic Chip Capacitor)
VDD
XTN
VDD
XTN
OUT
5420xL
XT
VC
OE OEN
OUT
5420xL
49.9Ω V
T
49.9Ω
VOH , VOL
OUTN
XT
49.9Ω
VDD-2V
OE OEN
VDD-2V
VSS
0.01μF(Ceramic Chip Capacitor)
OUT=VOH, OUTN=VOL
VOH , VOL
OUTN
VC
VSS
49.9Ω V
T
0.01μF(Ceramic Chip Capacitor)
OUT=VOL, OUTN=VOH
MEASUREMENT CIRCUIT 3
Measurement Parameters: RPU, RPD, VIH, VIL
0.01μF(Ceramic Chip Capacitor)
VDD
XTN
OUT
5420xL
XT
49.9Ω V
T
49.9Ω
OUTN
VC
OE OEN
VDD-2V
VSS
0.01μF(Ceramic Chip Capacitor)
IIL
VIL
A
A
IIH
VIH
OE PIN
VIH: VSS→VDD , voltage that changes enable output state
VIL: VDD→VSS , voltage that changes disable output state
OEN PIN
VIH: VSS→VDD , voltage that changes disable output state
VIL: VDD→VSS , voltage that changes enable output state
SEIKO NPC CORPORATION - 12
5420xL series
MEASUREMENT CIRCUIT 4
Measurement Parameters: RVC1, RVC2
0.01μF(Ceramic Chip Capacitor)
VDD
XTN
OUT
A
VDD
XTN
5420xL
IXT
A
IXTN
XT
0.01μF(Ceramic Chip Capacitor)
OUT
5420xL
XT
OUTN
VC
OE OEN
VSS
RVC1=VDD/IXT
VC
OE OEN
OUTN
VSS
RVC2=VDD/IXTN
(OE=Low and OEN=Open) or (OE=Open and OEN=High)
MEASUREMENT CIRCUIT 5
Measurement Parameters: RVIN
0.01μF(Ceramic Chip Capacitor)
VDD
XTN
OUT
5420xL
IVC
A
XT
VC
OE OEN
OUTN
VSS
RVIN=VDD/IVC
(OE=Low and OEN=Open)
or (OE=Open and OEN=High)
SEIKO NPC CORPORATION - 13
5420xL series
MEASUREMENT CIRCUIT 6
Measurement Parameters: Duty1, Duty2, VOPP, tr, tf
0.01μF(Ceramic Chip Capacitor)
VDD
XTN
OUT
5420xL
49.9Ω V
T
XT
Duty1 (Differential)
49.9Ω
OUTN
VC
OE OEN
VDD-2V Duty2, VOPP , tr, tf (Single Ended)
VSS
0.01μF(Ceramic Chip Capacitor)
MEASUREMENT CIRCUIT 7
Measurement Parameters: tOE, tOD
0.01μF(Ceramic Chip Capacitor)
VDD
XTN
OUT
5420xL
XT
VC
OE OEN
49.9Ω V
T
49.9Ω
VDD-2V
OUTN
VSS
0.01μF(Ceramic Chip Capacitor)
tOD:OE=VDD to VSS
or OEN=VSS to VDD
tOE:OE=VSS to VDD
or OEN=VDD to VSS
SEIKO NPC CORPORATION - 14
5420xL series
MEASUREMENT CIRCUIT 8
Measurement Parameters: FM
VDD=2.0V
0.01μF(Ceramic Chip Capacitor)
VDD
0.01μF
XTN
OUT
5420xL
XT
Signal
Generator
(AFG3102)
VC
OE OEN
VC input signal:
sine wave, VSS to VDD EXT Trigger In
Signal Source
Analyzer
(E5052A)
49.9Ω V
T
49.9Ω
0.01μF
OUTN
50Ω
VSS
VSS=-1.3V
0.01μF
(Ceramic Chip Capacitor)
SEIKO NPC CORPORATION - 15
5420xL series
REFERENCE DATA
The characters given below were measured using an NPC standards jig and standard crystal element, and do not represent a guarantee of
device characteristics.
Note that the characteristics will vary due to measurement environment and the oscillator element used.
Crystal used for measurement
Crystal parameters
Parameter
BL
CL
DL
fOSC(MHz)
122.88MHz
155.52MHz
245.76MHz
C0(pF)
1.6
1.5
TBD
γ(=C0/C1)
330
330
TBD
R1(Ω)
9
8
TBD
L1
C1
R1
C0
SEIKO NPC CORPORATION - 16
5420xL series
Pulling Range
[Measurement conditions] VDD= +2.0V, VSS= -1.3V, Ta= +25°C
* VC voltage in the graphs is adjusted to VSS= 0V. VC=1.65V standard
[5420BL] fOSC=122.88MHz
[5420CL] fOSC=155.52MHz
150
Pulling Range [ppm] VC=1.65V standard
Pulling Range [ppm] VC=1.65V standard
150
100
50
0
-50
-100
-150
100
50
0
-50
-100
-150
0.0
0.3
0.6
0.9
1.2
1.5
1.8
2.1
2.4
2.7
3.0
3.3
0.0
0.3
0.6
0.9
1.2
1.5
1.8
2.1
2.4
2.7
3.0
3.3
VC[V]
VC[V]
[5420DL] fOSC=245.76MHz
(TBD)
[Measurement circuit diagram]
VDD=2.0V
0.01μF(Ceramic Chip Capacitor)
VDD
XTN
Agilent
5052B
OUT
5420xL
XT
VC
OE OEN
49.9Ω V
T
49.9Ω
OUTN
50Ω
VSS
VC=-1.3V to 2.0V
VSS=-1.3V
0.01μF
(Ceramic Chip Capacitor)
0.01μF
(Ceramic Chip Capacitor)
SEIKO NPC CORPORATION - 17
5420xL series
Phase Noise
[Measurement conditions] VDD= +2.0V, VSS= -1.3V, Ta= +25°C
[5420BL] fOSC=122.88MHz
[5420CL] fOSC=155.52MHz
-60
-60
-70
-70
-80
Phase Noise [dBc/Hz]
Phase Noise [dBc/Hz]
-80
VC=VSS
V =V
C
-90
SS
VC=1/2(VDD+VSS)
VC=1/2(VDD+VSS)
VC=VDD
VC=VDD
-100
-110
-120
-130
-140
VC=VSS
V =V
C
-90
SS
VC=1/2(VDD+VSS)
VC=1/2(VDD+VSS)
VC=VDD
VC=VDD
-100
-110
-120
-130
-140
-150
-150
-160
1.E+01 1.E+02 1.E+03 1.E+04 1.E+05 1.E+06 1.E+07 1.E+08
-160
1.E+01 1.E+02 1.E+03 1.E+04 1.E+05 1.E+06 1.E+07 1.E+08
Offset Frequency [Hz]
Offset Frequency [Hz]
[5420DL] fOSC=245.76MHz
(TBD)
[Measurement circuit diagram]
VDD=2.0V
0.01μF(Ceramic Chip Capacitor)
VDD
XTN
Agilent
5052B
OUT
5420xL
XT
VC
OE OEN
49.9Ω V
T
49.9Ω
OUTN
50Ω
VSS
VC=-1.3V to 2.0V
VSS=-1.3V
0.01μF
(Ceramic Chip Capacitor)
0.01μF
(Ceramic Chip Capacitor)
SEIKO NPC CORPORATION - 18
5420xL series
Modulation Bandwidth
[Measurement conditions] VDD= +2.0V, VSS= -1.3V, Ta= +25°C
[5420BL] fOSC=122.88MHz
[5420CL] fOSC=155.52MHz
3
Fm [dB] 1kHz standard
Fm [dB] 1kHz standard
3
0
-3
-6
-9
0
-3
-6
-9
-12
-12
1
10
VC Input Frequency [kHz]
100
1
10
100
VC Input Frequency [kHz]
[5420DL] fOSC=245.76MHz
(TBD)
[Measurement circuit diagram] Measurement circuit 8
SEIKO NPC CORPORATION - 19
5420xL series
Negative Resistance
[5420BL] After release “Boot” function
0
0
-500
-500
-1000
Negative Resistance [Ω]
Negative Resistance [Ω]
[Measurement conditions] VDD= +3.3V, Ta= -25°C, C0= 0pF
[5420BL] When in “Boot” function
VC=0V
VC=1.65V
VC=3.3V
-1500
-2000
-2500
-1000
VC=1.65V
-1500
VC=3.3V
-2000
-2500
-3000
-3000
0
50
100
150
Frequency [MHz]
0
200
[5420CL] When in “Boot” function
50
100
150
200
Frequency [MHz]
[5420CL] After release “Boot” function
0
Negative Resistance [Ω]
0
Negative Resistance [Ω]
VC=0V
-500
-1000
VC=0V
VC=1.65V
VC=3.3V
-1500
-2000
-2500
-500
-1000
VC=0V
VC=1.65V
VC=3.3V
-1500
-2000
-2500
-3000
-3000
0
50
100
150
0
200
50
Frequency [MHz]
[5420DL] When in “Boot” function
100
Frequency [MHz]
150
200
[5420DL] After release “Boot” function
(TBD)
(TBD)
[Measurement circuit diagram]
0.01μF(Ceramic Chip Capacitor)
VDD
Network-Analyzer
(Agilent 4396B)
S-Parameter Test Set
(Agilent 85046A)
XTN
OUT
5420xL
XT
VC
OE OEN
OUTN
VSS
Measurement results using 4396B Agilent analyzer on NPC test jig.
Measurements will vary with test jig and measurement environment.
SEIKO NPC CORPORATION - 20
5420xL series
Drive Level
[Measurement conditions] VDD= +3.3V, Ta= +25°C
* VC voltage in the graphs is adjusted to VSS= 0V.
[5420CL] fOSC=155.52MHz
400
400
350
350
300
300
250
250
DL [uW]
DL [uW]
[5420BL] fOSC=122.88MHz
200
150
200
150
100
100
50
50
0
0
0
0.3
0.6
0.9
1.2
1.5
1.8
2.1
2.4
2.7
3
0
3.3
0.3
0.6
0.9
1.2
1.5
1.8
2.1
2.4
2.7
3
3.3
VC [V]
VC [V]
[5420DL] fOSC=245.76MHz
(TBD)
[Measurement circuit diagram]
0.01μF(Ceramic Chip Capacitor)
IX′tal
Tektronix CT-6
Current Probe
VDD
XTN
OUT
5420xL
XT
VC
OE OEN
49.9Ω V
T
49.9Ω
OUTN
VDD-2V
VSS
0.01μF(Ceramic Chip Capacitor)
SEIKO NPC CORPORATION - 21
5420xL series
Oscillator CL Characteristics
[Measurement conditions] VDD= +2.0V, VSS= -1.3V, Ta= +25°C
* VC voltage in the graphs is adjusted to VSS= 0V.
[5420CL] fOSC=155.52MHz
5.0
5.0
4.5
4.5
4.0
4.0
3.5
3.5
3.0
3.0
CLOSC [pF]
CLOSC [pF]
[5420BL] fOSC=122.88MHz
2.5
2.0
1.5
2.5
2.0
1.5
1.0
1.0
0.5
0.5
0.0
0.0
0.0
0.3
0.6
0.9
1.2
1.5
1.8
2.1
2.4
2.7
3.0
0.0
3.3
0.3
0.6
0.9
1.2
VC [V]
1.5
1.8
2.1
2.4
2.7
3.0
3.3
VC [V]
[5420DL] fOSC=245.76MHz
(TBD)
[Measurement circuit diagram]
VDD=2.0V
0.01μF(Ceramic Chip Capacitor)
VDD
XTN
Agilent
5052B
OUT
5420xL
XT
VC
OE OEN
49.9Ω V
T
CLosc =
49.9Ω
OUTN
50Ω
VSS
VC=-1.3V to 2.0V
VSS=-1.3V
0.01μF
(Ceramic Chip Capacitor)
CLOSC: Oscillator circuit equivalent capacitance determined by
oscillator frequency
0.01μF
(Ceramic Chip Capacitor)
C1
2
⎛ f OSC ⎞
⎜⎜
⎟⎟ − 1
⎝ fs ⎠
− C0
C1: Crystal element equivalent series capacitance
C0: Crystal element equivalent parallel capacitance
fs: Crystal element series resonance frequency
SEIKO NPC CORPORATION - 22
5420xL series
VC Terminal Input Impedance
[Measurement conditions] Ta= +25°C, VC= 0V
[5420BL, CL]
VC Input Impedance [kΩ]
600
500
400
300
200
100
0
0
10
20
30
40
50
60
70
VC Input Frequency [kHz]
80
90
100
[5420DL]
(TBD)
[Measurement circuit diagram]
VDD
XTN
OUT
5420xL
XT
Impedance
Analyzer
(HP 4194A)
VC
OE OEN
OUTN
VSS
VC input signal: 1kHz to 100kHz, 0.1VP-P
SEIKO NPC CORPORATION - 23
5420xL series
Output Waveform
[Measurement conditions] VDD= +3.3V, VC= +1.65V, Ta= +25°C
[5420BL] fOSC=122.88MHz
[5420CL] fOSC=155.52MHz
OUTN
OUTN
OUT
OUT
diff
diff
[5420DL] fOSC=245.76MHz
(TBD)
[Measurement circuit diagram] Measurement circuit 6
Measurement equipment: Oscilloscope DSO80604B (Agilent), Differential probe 1134A (Probe head E2678A)
SEIKO NPC CORPORATION - 24
5420xL series
Output Enable Propagation Delay
[Measurement conditions] VDD= +3.3V, VC= +1.65V, Ta= +25°C
[5420BL] fOSC=122.88MHz
[5420CL] fOSC=155.52MHz
OE
OE
OUT
OUT
OUTN
OUTN
[5420DL] fOSC=245.76MHz
(TBD)
* tOE is the time required for the output level to stabilize, and which varies depending on the power supply used, bypass capacitor values,
and other factors.
Measurement equipment: Power supply voltage PW18-1.8AQYB (KENWOOD)
[Measurement circuit diagram]
0.01μF(Ceramic Chip Capacitor)
VDD
XTN
OUT
5420xL
XT
VC
OE OEN
49.9Ω V
T
49.9Ω
Oscilloscope
(Agilent DSO80304B)
OUTN
VDD-2V
VSS
0.01μF(Ceramic Chip Capacitor)
Tektronix
AFG3012
49.9Ω
SEIKO NPC CORPORATION - 25
5420xL series
Please pay your attention to the following points at time of using the products shown in this document.
1. The products shown in this document (hereinafter ”Products”) are designed and manufactured to the generally accepted standards of
reliability as expected for use in general electronic and electrical equipment, such as personal equipment, machine tools and
measurement equipment. The Products are not designed and manufactured to be used in any other special equipment requiring
extremely high level of reliability and safety, such as aerospace equipment, nuclear power control equipment, medical equipment,
transportation equipment, disaster prevention equipment, security equipment. The Products are not designed and manufactured to be
used for the apparatus that exerts harmful influence on the human lives due to the defects, failure or malfunction of the Products.
If you wish to use the Products in that apparatus, please contact our sales section in advance.
In the event that the Products are used in such apparatus without our prior approval, we assume no responsibility whatsoever for any
damages resulting from the use of that apparatus.
2. NPC reserves the right to change the specifications of the Products in order to improve the characteristics or reliability thereof.
3. The information described in this document is presented only as a guide for using the Products. No responsibility is assumed by us for any
infringements of patents or other rights of the third parties which may result from its use. No license is granted by implication or otherwise
under any patents or other rights of the third parties. Then, we assume no responsibility whatsoever for any damages resulting from that
infringements.
4. The constant of each circuit shown in this document is described as an example, and it is not guaranteed about its value of the mass
production products.
5. In the case of that the Products in this document falls under the foreign exchange and foreign trade control law or other applicable laws and
regulations, approval of the export to be based on those laws and regulations are necessary. Customers are requested appropriately take
steps to obtain required permissions or approvals from appropriate government agencies.
SEIKO NPC CORPORATION
1-9-9, Hatchobori, Chuo-ku,
Tokyo 104-0032, Japan
Telephone: +81-3-5541-6501
Facsimile: +81-3-5541-6510
http://www.npc.co.jp/
Email:[email protected]
ND14006-E-00 2014.06
SEIKO NPC CORPORATION - 26