IDT8535-01
LOW SKEW, 1-TO-4 LVCMOS-TO-3.3V LVPECL
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
LOW SKEW, 1-TO-4
LVCMOS-TO-3.3V LVPECL
FANOUT BUFFER
FEATURES:
IDT8535-01
DESCRIPTION:
• Four differential 3.3V LVPECL outputs
• Selectable CLK0 or CLK1 inputs for redundant and multiple
frequency fanout applications
• Maximum output frequency: 266MHz
• CLK0 or CLK1 can accept LVCMOS or LVTTL input levels
• Translates LVCMOS and LVTTL levels to 3.3V LVPECL levels
• Output skew: 30ps (max.)
• Part-to-part skew: as low as 150ps
• Propagation delay: 1.9ns (max.)
• 3.3V operating supply
• Available in TSSOP package
The IDT8535-01 is a low skew, high performance 1-to-4 LVCMOS-to-3.3V
LVPECL fanout buffer. It has two single-ended clock inputs. The single-ended
clock input accepts LVCMOS or LVTTL input levels and translates them to 3.3V
LVPECL levels. The clock enable is internally synchronized to eliminate runt
pulses on the outputs during asynchronous assertion/deassertion of the clock
enable pin.
Guaranteed output and part-to-part skew characteristics make the IDT853501 ideal for those applications demanding well-defined performance and
repeatability.
FUNCTIONAL BLOCK DIAGRAM
D
CLK_EN
Q
LE
CLK0
0
Q0
xQ0
CLK1
1
Q1
xQ1
Q2
CLK_SEL
xQ2
Q3
xQ3
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
APRIL 2004
1
c
2004
Integrated Device Technology, Inc.
DSC 6196/6
IDT8535-01
LOW SKEW, 1-TO-4 LVCMOS-TO-3.3V LVPECL
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
PIN CONFIGURATION
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
Description
Power Supply Voltage
4.6
V
Input Voltage
–0.5 to VDD+0.5
V
VO
–0.5 to VDD+0.5 V
92.6
°C/W
VEE
1
20
Q0
CLK_EN
2
19
xQ0
θJA
Output Voltage
Package Thermal Impedance (0 lfpm)
CLK_SEL
3
18
VDD
TSTG
Storage Temperature
4
17
Q1
NC
5
16
xQ1
CLK1
6
15
Q2
NC
7
14
xQ2
NC
8
13
VDD
NC
9
12
Q3
VDD
10
11
xQ3
Unit
VDD
VI
CLK0
Max
–65 to +150
°C
NOTE:
1. Stresses beyond those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolutemaximum-rated conditions for extended periods may affect device reliability.
CAPACITANCE(TA = +25°C, f = 1MHz, VIN = 0V)
Parameter
CIN
RPULLUP
RPULLDOWN
Description
Typ.
Max.
Unit
Input Capacitance
—
4
pF
Input Pullup Resistor
51
—
KΩ
Input Pulldown Resistor
51
—
KΩ
TSSOP
TOP VIEW
PIN DESCRIPTION(1)
Symbol
Number
VEE
1
PWR
Type
CLK_EN
2
Input
Description
Negative Supply Pin
Pullup
Synchronizing Clock Enable. When HIGH, clock outputs follow clock input. When
LOW, Q outputs are forced LOW, xQ outputs are forced HIGH. LVCMOS / LVTTL
interface levels.
CLK_SEL
3
Input
Pulldown
Clock Select Input. When HIGH, selects CLK1 input. When LOW, selects CLK0
input. LVCMOS / LVTTL interface levels.
CLK0
4
Input
Pulldown
LVCMOS / LVTTL Clock Input
CLK1
6
Input
Pulldown
LVCMOS / LVTTL Clock Input
NC
5, 7, 8, 9
Unused
No Connection
VDD
10, 13, 18
Power
Positive Supply Pins
xQ3, Q3
11, 12
Output
Differential Output Pair. LVPECL interface levels.
xQ2 Q2
14, 15
Output
Differential Output Pair. LVPECL interface levels.
xQ1, Q1
16, 17
Output
Differential Output Pair. LVPECL interface levels.
xQ0, Q0
19, 20
Output
Differential Output Pair. LVPECL interface levels.
NOTE:
1. Pullup and Pulldown refer to internal input resistors. See Capacitance table for typical values.
2
IDT8535-01
LOW SKEW, 1-TO-4 LVCMOS-TO-3.3V LVPECL
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
CONTROL INPUT FUNCTION TABLE(1,2)
Inputs
Outputs
CLK_EN
CLK_SEL
Selected Source
Q0 to Q3
xQ0 to xQ3
0
0
CLK0
Disabled; LOW
Disabled; HIGH
0
1
CLK1
Disabled; LOW
Disabled; HIGH
1
0
CLK0
Enabled
Enabled
1
1
CLK1
Enabled
Enabled
NOTES:
1. After CLK_EN switches, the clock outputs are disabled or enabled following a rising and falling input clock edge as shown in the CLK_EN Timing Diagram below.
2. In active mode, the state of the outputs is a function of the CLK / xCLK and PCLK / xPCLK inputs as described in the Clock Input Function table.
Enabled
Disabled
CLK0, CLK1
≈
CLK EN
≈
≈
xQ0, xQ1, xQ2, xQ3
Q0, Q1, Q2, Q3
CLK_EN Timing Diagram
CLOCK INPUT FUNCTION TABLE(1)
Inputs
Outputs
CLK0 or CLK1
Q0 to Q3
xQ0 to xQ3
0
L
H
1
H
L
NOTE:
1. H = HIGH
L = LOW
3
IDT8535-01
LOW SKEW, 1-TO-4 LVCMOS-TO-3.3V LVPECL
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
POWER SUPPLY CHARACTERISTICS - COMMERCIAL
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
VDD
Positive Supply Voltage
3.135
3.3
3.465
V
IEE
Power Supply Current
—
—
50
mA
DC ELECTRICAL CHARACTERISTICS, LVCMOS / LVTTL - COMMERCIAL
Symbol
Parameter
Test Conditions
VIH
Input Voltage HIGH
VIL
Input Voltage LOW
IIH
IIL
Min.
Typ.
2
Input Current HIGH
Input Current LOW
Max.
Unit
VDD + 0.3
V
V
CLK0, CLK1
-0.3
1.3
CLK_EN, CLK_SEL
-0.3
0.8
CLK0, CLK1, CLK_SEL
VIN = VDD = 3.465V
150
CLK_EN
VIN = VDD = 3.465V
5
µA
µA
CLK0, CLK1, CLK_SEL
VIN = 0V, VDD = 3.465V
-5
CLK_EN
VIN = 0V, VDD = 3.465V
-150
DC ELECTRICAL CHARACTERISTICS, LVPECL - COMMERCIAL
Symbol
Parameter
Test Conditions
VOH
Output Voltage HIGH
VOL
Output Voltage LOW(1)
VSWING
(1)
Peak-to-Peak Output Voltage Swing
Min.
Typ.
Max.
Unit
VDD - 1.4
VDD - 1
V
VDD - 2
VDD - 1.7
V
0.6
0.85
V
NOTE:
1. Outputs terminated with 50Ω to VDD - 2V.
AC ELECTRICAL CHARACTERISTICS - COMMERCIAL
All parameters measured at 266MHz unless noted otherwise;
Cycle-to-cycle jitter on input = jitter on output; the part does not add jitter
Symbol
FMAX
tPD
Parameter
Test Conditions
Min.
Typ.
Output Frequency
Propagation Delay(1)
f ≤ 266MHz
1
Unit
266
MHz
1.9
ns
30
ps
150
ps
tSK(O)
Output Skew(2,4)
tSK(PP)
Part-to-Part Skew
tR
Output Rise Time
20 - 80% @ 50MHz
300
700
ps
tF
Output Fall Time
20 - 80% @ 50MHz
300
700
ps
52
%
odc
11
Max.
(3,4)
Output Duty Cycle
48
50
NOTES:
1. Measured from the VDD/2 of the input to the differential output crossingpoint.
2. Defined as skew between outputs as the same supply voltage and with equal load conditions. Measured at the output differential crosspoints
3. Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each
device, the outputs are measured at the differential crosspoints.
4. This parameter is defined in accordance with JEDEC Standard 65.
4
IDT8535-01
LOW SKEW, 1-TO-4 LVCMOS-TO-3.3V LVPECL
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
POWER SUPPLY CHARACTERISTICS - INDUSTRIAL
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
VDD
Positive Supply Voltage
3.135
3.3
3.465
V
IEE
Power Supply Current
—
—
55
mA
DC ELECTRICAL CHARACTERISTICS, LVCMOS / LVTTL - INDUSTRIAL
Symbol
Parameter
Test Conditions
VIH
Input Voltage HIGH
VIL
Input Voltage LOW
IIH
IIL
Min.
Typ.
2
Input Current HIGH
Input Current LOW
Max.
Unit
VDD + 0.3
V
V
CLK0, CLK1
-0.3
1.3
CLK_EN, CLK_SEL
-0.3
0.8
CLK0, CLK1, CLK_SEL
VIN = VDD = 3.465V
150
CLK_EN
VIN = VDD = 3.465V
5
µA
µA
CLK0, CLK1, CLK_SEL
VIN = 0V, VDD = 3.465V
-5
CLK_EN
VIN = 0V, VDD = 3.465V
-150
DC ELECTRICAL CHARACTERISTICS, LVPECL - INDUSTRIAL
Symbol
Parameter
Test Conditions
VOH
Output Voltage HIGH
VOL
Output Voltage LOW(1)
VSWING
(1)
Min.
Typ.
Max.
Unit
VDD - 1.4
VDD - 1
V
VDD - 2
VDD - 1.7
V
0.6
0.85
V
Peak-to-Peak Output Voltage Swing
NOTE:
1. Outputs terminated with 50Ω to VDD - 2V.
AC ELECTRICAL CHARACTERISTICS - INDUSTRIAL
All parameters measured at 266MHz unless noted otherwise;
Cycle-to-cycle jitter on input = jitter on output; the part does not add jitter
Symbol
FMAX
tPD
Parameter
Test Conditions
Min.
Typ.
Output Frequency
Propagation Delay(1)
f ≤ 266MHz
1
Max.
Unit
266
MHz
1.9
ns
30
ps
200
ps
tSK(O)
Output Skew(2,4)
tSK(PP)
Part-to-Part Skew
tR
Output Rise Time
20 - 80% @ 50MHz
300
700
ps
tF
Output Fall Time
20 - 80% @ 50MHz
300
700
ps
52
%
odc
(3,4)
Output Duty Cycle
48
50
NOTES:
1. Measured from the VDD/2 of the input to the differential output crossingpoint.
2. Defined as skew between outputs as the same supply voltage and with equal load conditions. Measured at the output differential crosspoints
3. Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each
device, the outputs are measured at the differential crosspoints.
4. This parameter is defined in accordance with JEDEC Standard 65.
5
IDT8535-01
LOW SKEW, 1-TO-4 LVCMOS-TO-3.3V LVPECL
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
PARAMETER MEASUREMENT INFORMATION
VDD
Scope
Z = 50Ω
Qx
LVPECL
50Ω
VDD = 2V
Z = 50Ω
xQx
50Ω
VEE = -1.3V ± 0.135V
Output Load Test Circuit
xQx
Qx
xQy
Qy
tSK(0)
Output Skew
xQx
Part 1
Qx
xQy
Part 2
Qy
tSK(PP)
Part-to-Part Skew
6
IDT8535-01
LOW SKEW, 1-TO-4 LVCMOS-TO-3.3V LVPECL
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
PARAMETER MEASUREMENT INFORMATION - CONTINUED
80%
80%
VSWING
Clock Outputs
20%
20%
tF
tR
Output Rise and Fall Time
CLK0, CLK1
xQ0, xQ1, xQ2, xQ3
Q0, Q1, Q2, Q3
tPD
Propagation Delay
xQ0, xQ1, xQ2, xQ3
Q0, Q1, Q2, Q3
Pulse Width
tPERIOD
tW
odc =
tPERIOD
odc and tPERIOD
7
IDT8535-01
LOW SKEW, 1-TO-4 LVCMOS-TO-3.3V LVPECL
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
APPLICATION INFORMATION
TERMINATION FOR LVPECL OUTPUTS
The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines.
FOUT and xFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to
ground) or current sources must be used for functionality. These outputs are designed to drive 50Ω transmission lines. Matched impedance techniques should
be used to maximize operating frequency and minimize signal distortion. The diagrams below show two different layouts which are recommended only as
guidelines. Other suitable clock layouts may exist. It is recommended that the board designers simulate to guarantee compatibility across all printed circuit and
clock component process variations.
3.3V
Zo = 50Ω
5
2
FOUT
Zo
5
2
Zo
FIN
Zo = 50Ω
Zo = 50Ω
FOUT
50Ω
FIN
50Ω
Zo = 50Ω
VDD - 2V
RTT
1
RTT =
3
2
Zo
Zo
3
2
Zo
(VOH + VOL / VDD - 2) - 2
LVPECL Output Termination, layout A
LVPECL Output Termination, layout B
8
IDT8535-01
LOW SKEW, 1-TO-4 LVCMOS-TO-3.3V LVPECL
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the IDT8535-01. Equations and example calculations are also provided.
POWER DISSIPATION:
The total power dissipation for the IDT8535-01 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation
for the VDD = 3.3V + 5% = 3.465V, which gives worst case results. Please refer to the following section, Calculations and Equations, for details on calculating
power dissipated in the load.
Power (core)MAX = VDD_MAX * ICC_MAX = 3.465 * 50mA = 173.25mW
Power (outputs)MAX = 30.2mW/Loaded Output Pair
If all outputs are loaded, the total power is 4 * 30.2mW = 120.8Mw
Total Power_MAX (3.465V, with all outputs switching) = 173.25mW + 120.8mW = 294.05mW
JUNCTION TEMPERATURE:
Junction temperature (tJ) is the temperature at the junction of the bond wire and bond pad. It directly affects the reliability of the device. The maximum
recommended junction temperature for this device is 125°C.
The equation for is as follows: tJ = θJA * Pd_total + TA
tJ = Junction Temperature
θJA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in Power Dissipation, above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance (θJA) must be used. Assuming a moderate air flow of 200
linear feet per minute and a multi-layer board, the appropriate value is 77.6°C/W per the following Thermal Resistance table. Therefore, tJ for an ambient
temperature of 70°C with all its outputs switching is:
70°C + 0.294W * 77.6°C/W = 92.81°C. This is well below the limit of 125°C.
This calculation is only an example. tJ will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (singlelayer or multi-layer).
THERMAL RESISTANCE
θJA for 20-pin TSSOP, forced convenction
θJA by Velocity (Linear Feet per mInute)
Multi-Layer PCB, JEDEC Standard Test boards
9
0
200
400
Unit
92.6
77.6
70.9
°C/W
IDT8535-01
LOW SKEW, 1-TO-4 LVCMOS-TO-3.3V LVPECL
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
CALCULATIONS AND EQUATIONS
VDD
Q1
VOUT
RL
50
VDD - 2V
LVPECL Output Driver Circuit and Termination
To calculate worst case power dissipation into the load, use the following equations, which assume a 50Ω load and a termination voltage of VDD – 2V.
For Logic HIGH: VOUT = VOH_MAX = VDD_MAX – 1V.
(VDD_MAX – VOH_MAX) = 1V
For Logic LOW: VOUT = VOL_MAX = VDD_MAX – 1.7V.
(VDD_MAX – VOL_MAX) = 1.7V
Pd_H is power dissipation when the output drives HIGH.
Pd_L is power dissipation when the output drives LOW.
Pd_H = {[ VOH_MAX – (VDD_MAX – 2V)] / RL} * (VDD_MAX – VOH_MAX) = {[ 2V – (VDD_MAX – VOH_MAX)] / RL} * (VDD_MAX – VOH_MAX) = [( 2V – 1V) / 50Ω] *
1V = 20mW.
Pd_L = {[ VOL_MAX – (VDD_MAX – 2V)] / RL} * (VDD_MAX – VOL_MAX) = {[ 2V – (VDD_MAX – VOL_MAX)] / RL} * (VDD_MAX – VOL_MAX) = [( 2V – 1.7V) / 50Ω] *
1.7V = 10.2mW.
Total Power Dissipation per output pair = Pd_H + Pd_L = 30.2mW
10
IDT8535-01
LOW SKEW, 1-TO-4 LVCMOS-TO-3.3V LVPECL
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
ORDERING INFORMATION
IDT XXXXX
Device Type
XX
Package
X
Process
CORPORATE HEADQUARTERS
2975 Stender Way
Santa Clara, CA 95054
Blank
I
Commercial (0°C to +70°C)
Industrial (-40°C to +85°C)
PG
Thin Shrink Small Outline Package
8535-01
Low Skew, 1-to-4 LVCMOS-to-3.3V LVPECL
Fanout Buffer
for SALES:
800-345-7015 or 408-727-6116
fax: 408-492-8674
www.idt.com
11
for Tech Support:
[email protected]
(408) 654-6459