ICS8534-01 LOW SKEW, 1-TO-22 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER General Description Features The ICS8534-01 is a low skew, 1-to-22 Differential-to-3.3V LVPECL Fanout Buffer and a HiPerClockS™ member of the HiPerClockS™ Family of High Performance Clock Solutions from IDT. The ICS8534-01 has two selectable clock inputs. The CLK, nCLK pair can accept most standard differential input levels. The PCLK, nPCLK pair can accept LVPECL, CML, or SSTL input levels. The device is internally synchronized to eliminate runt pulses on the outputs during asynchronous assertion/deassertion of the OE pin. The ICS8534-01’s low output and part-to-part skew characteristics make it ideal for workstation, server, and other high performance clock distribution applications. • • Twenty-two differential LVPECL outputs • CLK/nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL • PCLK/nPCLK supports the following input levels: LVPECL, CML, SSTL • • • Maximum output frequency: 500MHz • • • • Additive phase jitter, RMS): 0.04ps (typical) ICS Translates any single-ended input signal (LVCMOS, LVTTL, GTL) to LVPECL levels with resistor bias on nCLK input Full 3.3V supply mode 0°C to 85°C ambient operating temperature Available in both standard (RoHS 5) and lead-free (RoHS 6) packages. 1 Q0:Q21 22 nQ0:nQ21 VCCO nQ6 LE Q6 nQ5 Q5 nQ4 Q4 nQ3 Q Pullup D Q3 nQ2 Q2 nQ1 Q1 nQ0 VCCO QC11 nQ11 Q12 nQ12 Q13 nQ13 Q8 nQ8 Q9 nQ9 Q10 nQ10 ICS8534-01 15 34 16 33 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 VCCO nc nc VCC CLK nCLK CLK_SEL PCLK nPCLK VEE Q0 VCCO 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 3 46 4 45 5 44 6 43 7 42 8 41 9 40 10 39 11 38 12 37 13 36 14 35 1 2 VCCO Q14 nQ14 Q15 nQ15 Q16 nQ16 Q17 nQ17 Q18 nQ18 Q19 nQ19 Q20 nQ20 VCCO VCCO nPCLK Pullup/Pulldown 22 0 OE nc nc nQ21 Q21 PCLK Pulldown VCCO Q7 nQ7 Pullup CLK Pulldown nCLK Pullup/Pulldown OE Output skew: 100ps (maximum) Pin Assignment Block Diagram CLK_SEL Selectable differential CLK/nCLK or LVPECL clock inputs can accept the following differential input levels: LVDS, LVPECL, LVHSTL 64-Lead TQFP E-Pad 10mm x 10mm x 1.0mm package body Y package Top View IDT™ / ICS™ 3.3V LVPECL FANOUT BUFFER 1 ICS8534AY-01 REV. A DECEMBER 6, 2007 ICS8534-01 LOW SKEW, 1-TO-22 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER Table 1. Pin Descriptions Number Name Type Description 1, 16, 17, 32, 33, 48, 49, 64 VCCO Power 2, 3, 12, 13 nc Unused 4 VCC Power 5 CLK Input Pulldown Non-inverting differential clock input. 6 nCLK Input Pullup/ Pulldown Inverting differential clock input. Pulled to 2/3 VCC. 7 CLK_SEL Input Pullup 8 PCLK Input Pulldown Non-inverting differential LVPECL clock input. Pullup/ Pulldown Inverting differential LVPECL clock input. Pulled to 2/3 VCC. Output supply pins for LVPECL outputs. No connect. Core supply pin for LVPECL outputs. Clock select input. When HIGH, selects PCLK, nPCLK inputs. When LOW, selects CLK, nCLK inputs. LVCMOS / LVTTL interface levels. 9 nPCLK Input 10 VEE Power 11 OE Input 14, 15 nQ21, Q21 Output Differential clock outputs. LVPECL interface Levels. 18, 19 nQ20, Q20 Output Differential clock outputs. LVPECL interface Levels. 20, 21 nQ19, Q19 Output Differential clock outputs. LVPECL interface Levels. 22, 23 nQ18, Q18 Output Differential clock outputs. LVPECL interface Levels. 24, 25 nQ17, Q17 Output Differential clock outputs. LVPECL interface Levels. 26, 27 nQ16, Q16 Output Differential clock outputs. LVPECL interface Levels. 28, 29 nQ15, Q15 Output Differential clock outputs. LVPECL interface Levels. 30, 31 nQ14, Q14 Output Differential clock outputs. LVPECL interface Levels. 34, 35 nQ13, Q13 Output Differential clock outputs. LVPECL interface Levels. 36, 37 nQ12, Q12 Output Differential clock outputs. LVPECL interface Levels. 38, 39 nQ11, Q11 Output Differential clock outputs. LVPECL interface Levels. 40, 41 nQ10, Q10 Output Differential clock outputs. LVPECL interface Levels. 42, 43 nQ9, Q9 Output Differential clock outputs. LVPECL interface Levels. 44, 45 nQ8, Q8 Output Differential clock outputs. LVPECL interface Levels. 46, 47 nQ7, Q7 Output Differential clock outputs. LVPECL interface Levels. 50, 51 nQ6, Q6 Output Differential clock outputs. LVPECL interface Levels. 52, 53 nQ5, Q5 Output Differential clock outputs. LVPECL interface Levels. 54, 55 nQ4, Q4 Output Differential clock outputs. LVPECL interface Levels. 56, 57 nQ3, Q3 Output Differential clock outputs. LVPECL interface Levels. 58, 59 nQ2, Q2 Output Differential clock outputs. LVPECL interface Levels. 60, 61 nQ1, Q1 Output Differential clock outputs. LVPECL interface Levels. 59 nQ0, Q0 Output Differential clock outputs. LVPECL interface Levels. Negative supply pin. Pullup Output enable. When logic HIGH, the outputs are enabled (default). When logic LOW, the outputs are disabled and drive differential low: Qx = LOW, nQx = HIGH. LVCMOS / LVTTL interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. IDT™ / ICS™ 3.3V LVPECL FANOUT BUFFER 2 ICS8534AY-01 REV. A DECEMBER 6, 2007 ICS8534-01 LOW SKEW, 1-TO-22 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER Table 2. Pin Characteristics Symbol Parameter Test Conditions Minimum Typical Maximum Units CIN Input Capacitance 4 pF RPULLUP Input Pullup Resistor 37 kΩ RPULLDOWN Input Pulldown Resistor 75 kΩ Function Table Table 3. Control Input Function Table. Inputs Outputs OE CLK_SEL Q0:Q21 nQ0:nQ21 0 0 LOW HIGH 0 1 LOW HIGH 1 0 CLK nCLK 1 1 PCLK nPCLK Enabled Disabled nCLK, nPCLK CLK, PCLK OE nQ0:nQ21 Q0:Q21 Figure 1. OE Timing Diagram IDT™ / ICS™ 3.3V LVPECL FANOUT BUFFER 3 ICS8534AY-01 REV. A DECEMBER 6, 2007 ICS8534-01 LOW SKEW, 1-TO-22 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Item Rating Supply Voltage, VCC 4.6V Inputs, VI -0.5V to VCC + 0.5V Outputs, IO (LVPECL) Continuous Current Surge Current 50mA 100mA Package Thermal Impedance, θJA 22.3°C/W (0 lfpm) Storage Temperature, TSTG -65°C to 150°C DC Electrical Characteristics Table 4A. Power Supply DC Characteristics, VCC = VCCO = 3.3V ± 5%, VEE = 0V, TA = 0°C to 85°C Symbol Parameter VCC Test Conditions Minimum Typical Maximum Units Core Supply Voltage 3.135 3.3 3.465 V VCCO Output Supply Voltage 3.135 3.3 3.465 V IEE Power Supply Current 230 mA Maximum Units Table 4B. LVCMOS/LVTTL DC Characteristics, VCC = VCCO = 3.3V ± 5%, VEE = 0V, TA = 0°C to 85°C Symbol Parameter Test Conditions VIH Input High Voltage 2 VCC + 0.3 V VIL Input Low Voltage -0.3 0.8 V IIH Input High Current OE, CLK_SEL VCC = VIN = 3.465V 5 µA IIL Input Low Current OE, CLK_SEL VCC = 3.465V, VIN = 0V IDT™ / ICS™ 3.3V LVPECL FANOUT BUFFER 4 Minimum -150 Typical µA ICS8534AY-01 REV. A DECEMBER 6, 2007 ICS8534-01 LOW SKEW, 1-TO-22 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER Table 4C. Differential DC Characteristics, VCC = VCCO = 3.3V ± 5%, VEE = 0V, TA = 0°C to 85°C Symbol Parameter Test Conditions IIH Input High Current IIL Input Low Current VPP Peak-to-Peak Voltage; NOTE 1 VCMR Common Mode Input Voltage; NOTE 1, 2 Minimum Typical Maximum Units CLK VCC = VIN = 3.465V 150 µA nCLK VCC = VIN = 3.465V 5 µA CLK VCC = 3.465V, VIN = 0V -5 µA nCLK VCC = 3.465V, VIN = 0V -150 µA 0.15 1.3 V VEE + 0.5 VCC – 0.85 V Maximum Units NOTE 1: VIL should not be less than -0.3V. NOTE 2: Common mode input voltage is defined as VIH. Table 4C. LVPECL DC Characteristics, VCC = VCCO = 3.3V ± 5%, VEE = 0V, TA = 0°C to 85°C Symbol Parameter Test Conditions IIH Input High Current IIL Input Low Current VPP Peak-to-Peak Voltage; NOTE 1 VCMR Common Mode Input Voltage; NOTE 1, 2 VOH Minimum Typical PCLK VCC = VIN = 3.465V 150 µA nPCLK VCC = VIN = 3.465V 5 µA PCLK VCC = 3.465V, VIN = 0V -5 µA nPCLK VCC = 3.465V, VIN = 0V -150 µA 0.3 1.0 V VEE + 1.5 VCC V Output High Voltage; NOTE 3 VCCO – 1.4 VCCO – 0.9 V VOL Output Low Voltage; NOTE 3 VCCO – 2.0 VCCO – 1.7 V VSWING Peak-to-Peak Output Voltage Swing 0.6 1.0 V NOTE 1: VIL should not be less than -0.3V. NOTE 2: Common mode input voltage is defined as VIH. NOTE 3: Outputs terminated with 50Ω to VCCO – 2V. IDT™ / ICS™ 3.3V LVPECL FANOUT BUFFER 5 ICS8534AY-01 REV. A DECEMBER 6, 2007 ICS8534-01 LOW SKEW, 1-TO-22 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER AC Electrical Characteristics Table 5. VCC = VCCO = 3.3V ± 5%, VEE = 0V, TA = 0°C to 85°C Symbol Parameter fMAX Output Frequency tPD Propagation Delay; NOTE 1 tsk(o) Test Conditions Maximum Units 500 MHz 3.0 ns Output Skew; NOTE 2, 3 100 ps tsk(pp) Part-to-Part Skew; NOTE 3, 4 700 ps tjit Buffer Additive Phase Jitter, RMS, refer to Additive Phase Jitter section; NOTE 5 tR / tF Output Rise/ Fall Time tS Setup Time 1 ns tH Hold Time 0.5 ns odc Output Duty Cycle ƒ ≤ 500MHz Minimum 2.0 Integration Range: 12kHz - 20MHz 20% to 80% Typical 0.4 200 ps 700 ps ƒ ≤ 266MHz 48 52 % 266 < ƒ ≤ 500MHz 46 54 % All parameters measured at fMAX unless noted otherwise. Special thermal considerations may be required. See Applications Section. NOTE 1: Measured from the differential input crossing point to the differential output crossing point. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. NOTE 3: This parameter is defined in accordance with JEDEC Standard 65. Measured at the output differential cross points. NOTE 4: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions at the same temperature. Using the same type of inputs on each device, the outputs are measured at the differential cross points. NOTE 5: Driving only one input clock. IDT™ / ICS™ 3.3V LVPECL FANOUT BUFFER 6 ICS8534AY-01 REV. A DECEMBER 6, 2007 ICS8534-01 LOW SKEW, 1-TO-22 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER Additive Phase Jitter The spectral purity in a band at a specific offset from the fundamental compared to the power of the fundamental is called the dBc Phase Noise. This value is normally expressed using a Phase noise plot and is most often the specified plot in many applications. Phase noise is defined as the ratio of the noise power present in a 1Hz band at a specified offset from the fundamental frequency to the power value of the fundamental. This ratio is expressed in decibels (dBm) or a ratio of the power in the 1Hz band to the power in the fundamental. When the required offset is specified, the phase noise is called a dBc value, which simply means dBm at a specified offset from the fundamental. By investigating jitter in the frequency domain, we get a better understanding of its effects on the desired application over the entire time record of the signal. It is mathematically possible to calculate an expected bit error rate given a phase noise plot. 0 -10 Additive Phase Jitter, RMS @ 156.25MHz 12kHz to 20MHz = 0.04ps (typical) -20 -30 -40 -50 SSB Phase Noise dBc/Hz -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 -190 1k 10k 100k 1M 10M 100M Offset Frequency (Hz) device. This is illustrated above. The device meets the noise floor of what is shown, but can actually be lower. The phase noise is dependant on the input source and measurement equipment. As with most timing specifications, phase noise measurements has issues relating to the limitations of the equipment. Often the noise floor of the equipment is higher than the noise floor of the IDT™ / ICS™ 3.3V LVPECL FANOUT BUFFER 7 ICS8534AY-01 REV. A DECEMBER 6, 2007 ICS8534-01 LOW SKEW, 1-TO-22 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER Parameter Measurement Information 2V VCC VCC, Qx SCOPE nCLK, nPCLK VCCO V V Cross Points PP CMR CLK, PCLK LVPECL nQx VEE VEE -1.3V± 0.165V 3.3V LVPECL Output Load AC Test Circuit nQx Differential Input Level Par t 1 nQx Qx nQy Qx Par t 2 nQy Qy Qy tsk(o) tsk(pp) Part-to-Part Skew Output Skew nCLK, nPCLK 80% CLK, PCLK 80% VSW I N G Clock Outputs nQ0:nQ21 Q0:Q21 20% 20% tR tF tPD Propagation Delay IDT™ / ICS™ 3.3V LVPECL FANOUT BUFFER Output Rise/Fall Time 8 ICS8534AY-01 REV. A DECEMBER 6, 2007 ICS8534-01 LOW SKEW, 1-TO-22 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER Parameter Measurement Information, continued nQ0:nQ21 Q0:Q21 t PW t odc = PERIOD t PW x 100% t PERIOD - Output Duty Cycle/Pulse Width/Period Application Information Wiring the Differential Input to Accept Single Ended Levels Figure 2 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF = VCC/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VCC = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609. VCC R1 1K Single Ended Clock Input CLK, PCLK nCLK. nPCLK V_REF C1 0.1u R2 1K Figure 2. Single-Ended Signal Driving Differential Input IDT™ / ICS™ 3.3V LVPECL FANOUT BUFFER 9 ICS8534AY-01 REV. A DECEMBER 6, 2007 ICS8534-01 LOW SKEW, 1-TO-22 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER Differential Clock Input Interface common driver types. The input interfaces suggested here are examples only. If the driver is from another vendor, use their termination recommendation. Please consult with the vendor of the driver component to confirm the driver termination requirements. The CLK /nCLK accepts LVPECL, LVDS, LVHSTL and other differential signals. Both VSWING and VOH must meet the VPP and VCMR input requirements. Figures 3A to 3F show interface examples for the HiPerClockS CLK/nCLK input driven by the most 3.3V 3.3V 3.3V 3.3V R1 50 3.3V Zo = 50Ω R2 50 Zo = 50Ω CLK R1 100 CLK Zo = 50Ω nCLK Zo = 50Ω nCLK CML HiPerClockS CML Built-In Pullup HiPerClockS Figure 3A. HiPerClockS CLK/nCLK Input Driven by an IDT Open Collector CML Driver Figure 3B. HiPerClockS CLK/nCLK Input Driven by a Built-In Pullup CML Driver 3.3V 3.3V 3.3V R3 125 3.3V 3.3V R4 125 Zo = 50Ω 3.3V LVPECL Zo = 50Ω C1 Zo = 50Ω C2 CLK CLK Zo = 50Ω nCLK nCLK HiPerClockS HiPerClockS LVPECL R1 84 R5 100 - 200 R2 84 Figure 3C. HiPerClockS CLK/nCLK Input Driven by a 3.3V LVPECL Driver R6 100 - 200 R1 125 R2 125 Figure 3D. HiPerClockS CLK/nCLK Input Driven by a 3.3V LVPECL Driver with AC Couple 2.5V 3.3V 2.5V R3 120 3.3V R4 120 3.3V Zo = 50Ω Zo = 60Ω CLK CLK R1 100 Zo = 60Ω nCLK HiPerClockS SSTL R1 120 Zo = 50Ω R2 120 LVDS Figure 3E. HiPerClockS CLK/nCLK Input Driven by an SSTL Driver IDT™ / ICS™ 3.3V LVPECL FANOUT BUFFER nCLK HiPerClockS Figure 3F. HiPerClockS CLK/nCLK Input Driven by a 3.3V LVDS Driver 10 ICS8534AY-01 REV. A DECEMBER 6, 2007 ICS8534-01 LOW SKEW, 1-TO-22 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER LVPECL Clock Input Interface most common driver types. The input interfaces suggested here are examples only. If the driver is from another vendor, use their termination recommendation. Please consult with the vendor of the driver component to confirm the driver termination requirements. The PCLK /nPCLK accepts LVPECL, CML, SSTL and other differential signals. Both VSWING and VOH must meet the VPP and VCMR input requirements. Figures 4A to 4F show interface examples for the HiPerClockS PCLK/nPCLK input driven by the 3.3V 3.3V 3.3V 3.3V R1 50 3.3V Zo = 50Ω R2 50 Zo = 50Ω PCLK R1 100 PCLK Zo = 50Ω nPCLK Zo = 50Ω nPCLK CML HiPerClockS PCLK/nPCLK CML Built-In Pullup HiPerClockS PCLK/nPCLK Figure 4A. HiPerClockS PCLK/nPCLK Input Driven by an Open Collector CML Driver Figure 4B. HiPerClockS PCLK/nPCLK Input Driven by a Built-In Pullup CML Driver 3.3V 3.3V 3.3V 3.3V R3 125 3.3V R4 125 3.3V Zo = 50Ω R3 84 3.3V LVPECL PCLK Zo = 50Ω C1 Zo = 50Ω C2 R4 84 PCLK Zo = 50Ω nPCLK nPCLK HiPerClockS Input LVPECL R1 84 R2 84 R5 100 - 200 Figure 4C. HiPerClockS PCLK/nPCLK Input Driven by a 3.3V LVPECL Driver R6 100 - 200 R1 125 HiPerClockS PCLK/nPCLK R2 125 Figure 4D. HiPerClockS PCLK/nPCLK Input Driven by a 3.3V LVPECL Driver with AC Couple 2.5V 3.3V 3.3V 2.5V R3 120 3.3V 3.3V R4 120 R3 1k Zo = 50Ω R4 1k C1 Zo = 60Ω PCLK PCLK R5 100 Zo = 60Ω nPCLK SSTL R1 120 R2 120 nPCLK Zo = 50Ω HiPerClockS PCLK/nPCLK LVDS R1 1k Figure 4E. HiPerClockS PCLK/nPCLK Input Driven by an SSTL Driver (delete this figure IDT™ / ICS™ 3.3V LVPECL FANOUT BUFFER C2 R2 1k HiPerClockS PCLK/nPCLK Figure 4F. HiPerClockS PCLK/nPCLK Input Driven by a 3.3V LVDS Driver 11 ICS8534AY-01 REV. A DECEMBER 6, 2007 ICS8534-01 LOW SKEW, 1-TO-22 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER Recommendations for Unused Input and Output Pins Inputs: Outputs: CLK/nCLK Inputs LVPECL Outputs For applications not requiring the use of the differential input, both CLK and nCLK can be left floating. Though not required, but for additional protection, a 1kΩ resistor can be tied from CLK to ground. All unused LVPECL outputs can be left floating. We recommend that there is no trace attached. Both sides of the differential output pair should either be left floating or terminated. PCLK/nPCLK Inputs For applications not requiring the use of the differential input, both PCLK and nPCLK can be left floating. Though not required, but for additional protection, a 1kΩ resistor can be tied from PCLK to ground. LVCMOS Control Pins All control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. A 1kΩ resistor can be used. Termination for 3.3V LVPECL Outputs The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 5A and 5B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. FOUT and nFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive 50Ω 3.3V Zo = 50Ω 125Ω FOUT FIN Zo = 50Ω Zo = 50Ω FOUT 50Ω RTT = 125Ω 1 Z ((VOH + VOL) / (VCC – 2)) – 2 o Zo = 50Ω VCC - 2V RTT 84Ω Figure 5A. 3.3V LVPECL Output Termination IDT™ / ICS™ 3.3V LVPECL FANOUT BUFFER FIN 50Ω 84Ω Figure 5B. 3.3V LVPECL Output Termination 12 ICS8534AY-01 REV. A DECEMBER 6, 2007 ICS8534-01 LOW SKEW, 1-TO-22 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER EPAD Thermal Release Path In order to maximize both the removal of heat from the package and the electrical performance, a land pattern must be incorporated on the Printed Circuit Board (PCB) within the footprint of the package corresponding to the exposed metal pad or exposed heat slug on the package, as shown in Figure 6. The solderable area on the PCB, as defined by the solder mask, should be at least the same size/shape as the exposed pad/slug area on the package to maximize the thermal/electrical performance. Sufficient clearance should be designed on the PCB between the outer edges of the land pattern and the inner edges of pad pattern for the leads to avoid any shorts. application specific and dependent upon the package power dissipation as well as electrical conductivity requirements. Thus, thermal and electrical analysis and/or testing are recommended to determine the minimum number needed. Maximum thermal and electrical performance is achieved when an array of vias is incorporated in the land pattern. It is recommended to use as many vias connected to ground as possible. It is also recommended that the via diameter should be 12 to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. This is desirable to avoid any solder wicking inside the via during the soldering process which may result in voids in solder between the exposed pad/slug and the thermal land. Precautions should be taken to eliminate any solder voids between the exposed heat slug and the land pattern. Note: These recommendations are to be used as a guideline only. For further information, refer to the Application Note on the Surface Mount Assembly of Amkor’s Thermally/Electrically Enhance Leadfame Base Package, Amkor Technology. While the land pattern on the PCB provides a means of heat transfer and electrical grounding from the package to the board through a solder joint, thermal vias are necessary to effectively conduct from the surface of the PCB to the ground plane(s). The land pattern must be connected to ground through these vias. The vias act as “heat pipes”. The number of vias (i.e. “heat pipes”) are SOLDER PIN PIN PAD EXPOSED HEAT SLUG GROUND PLANE THERMAL VIA SOLDER PIN LAND PATTERN (GROUND PAD) SOLDER PIN PAD Figure 6. Assembly for Exposed Pad Thermal Release Path - Side View (drawing not to scale) IDT™ / ICS™ 3.3V LVPECL FANOUT BUFFER 13 ICS8534AY-01 REV. A DECEMBER 6, 2007 ICS8534-01 LOW SKEW, 1-TO-22 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER Power Considerations This section provides information on power dissipation and junction temperature for the ICS5334-01. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS534-01 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. • Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 230mA = 796.95mW • Power (outputs)MAX = 30mW/Loaded Output pair If all outputs are loaded, the total power is 22 * 30mW = 660mW Total Power_MAX (3.8V, with all outputs switching) = 796.95mW + 660mW = 153.08mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockS devices is 125°C. The equation for Tj is as follows: Tj = θJA * Pd_total + TA Tj = Junction Temperature θJA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming 0 air flow and a multi-layer board, the appropriate value is 17.2°C/W per Table 6 below. Therefore, Tj for an ambient temperature of 85°C with all outputs switching is: 85°C + 1.457W * 17.2°C/W = 110.1°C. This is below the limit of 125°C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board (single layer or multi-layer). Table 6. Thermal Resistance θJA for 64 Lead TQFP, Forced Convection θJA by Velocity Linear Feet per Minute Multi-Layer PCB, JEDEC Standard Test Boards IDT™ / ICS™ 3.3V LVPECL FANOUT BUFFER 0 200 500 22.3°C/W 17.2°C/W 15.1°C/W 14 ICS8534AY-01 REV. A DECEMBER 6, 2007 ICS8534-01 LOW SKEW, 1-TO-22 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER 3. Calculations and Equations. The purpose of this section is to derive the power dissipated into the load. LVPECL output driver circuit and termination are shown in Figure 7. VCCO Q1 VOUT RL 50Ω VCCO - 2V Figure 7. LVPECL Driver Circuit and Termination To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination voltage of VCCO – 2V. • For logic high, VOUT = VOH_MAX = VCCO_MAX – 0.9V (VCCO_MAX – VOH_MAX) = 0.9V • For logic low, VOUT = VOL_MAX = VCCO_MAX – 1.7V (VCCO_MAX – VOL_MAX) = 1.7V Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. Pd_H = [(VOH_MAX – (VCCO_MAX – 2V))/RL] * (VCCO_MAX – VOH_MAX) = [(2V – (VCCO_MAX – VOH_MAX))/RL] * (VCCO_MAX – VOH_MAX) = [(2V – 0.9V)/50Ω] * 0.9V = 19.8mW Pd_L = [(VOL_MAX – (VCCO_MAX – 2V))/RL] * (VCCO_MAX – VOL_MAX) = [(2V – (VCCO_MAX – VOL_MAX))/RL] * (VCCO_MAX – VOL_MAX) = [(2V – 1.7V)/50Ω] * 1.7V = 10.2mW Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW IDT™ / ICS™ 3.3V LVPECL FANOUT BUFFER 15 ICS8534AY-01 REV. A DECEMBER 6, 2007 ICS8534-01 LOW SKEW, 1-TO-22 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER Reliability Information Table 7. θJA vs. Air Flow Table for a 64 Lead TQFP, E-Pad θJA vs. Air Flow Linear Feet per Minute Multi-Layer PCB, JEDEC Standard Test Boards 0 200 500 22.3°C/W 17.2°C/W 15.1°C/W Transistor Count The transistor count for ICS8534-01 is: 1474 IDT™ / ICS™ 3.3V LVPECL FANOUT BUFFER 16 ICS8534AY-01 REV. A DECEMBER 6, 2007 ICS8534-01 LOW SKEW, 1-TO-22 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER Package Outline and Package Dimension Package Outline - Y Suffix for 64 Lead TQFP, E-Pad -HD VERSION EXPOSED PAD DOWN Table 8. Package Dimensions for 64 Lead TQFP, E-Pad Symbol N A A1 A2 b c D&E D1 & E1 D2 & E2 D3 & E3 e L θ ccc JEDEC Variation: ACD All Dimensions in Millimeters Minimum Nominal Maximum 64 1.20 0.05 0.10 0.15 0.95 1.00 1.05 0.17 0.22 0.27 0.09 0.20 12.00 Basic 10.00 Basic 7.50 Ref. 4.5 5.0 5.5 0.50 Basic 0.45 0.60 0.75 0° 7° 0.08 Reference Document: JEDEC Publication 95, MS-026 IDT™ / ICS™ 3.3V LVPECL FANOUT BUFFER 17 ICS8534AY-01 REV. A DECEMBER 6, 2007 ICS8534-01 LOW SKEW, 1-TO-22 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER Ordering Information Table 9. Ordering Information Part/Order Number Marking Package Shipping Packaging Temperature ICS8534AY-01 ICS8534AY-01 64 Lead TQFP Tray 0°C to +85°C ICS8534AY-01T ICS8534AY-01 64 Lead TQFP 500 Tape & Reel 0°C to +85°C ICS8534AY-01LF ICS8534AY-01LF “Lead-Free” 64 Lead TQFP Tray 0°C to +85°C ICS8534AY-01LFT ICS8534AY-01LF “Lead-Free” 64 Lead TQFP 500 Tape & Reel 0°C to +85°C NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant. While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications, such as those requiring extended temperature ranges, high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. IDT™ / ICS™ 3.3V LVPECL FANOUT BUFFER 18 ICS8534AY-01 REV. A DECEMBER 6, 2007 ICS8534-01 LOW SKEW, 1-TO-22 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER Revision History Sheet Rev Table A A T9 Page Description of Change Date 15 Updated Package Outline and Package Dimensions. 11/19/04 1 12 13 18 Features Section - added lead-free bullet. Added Recommendations for Unused Input and Output Pins section. Updated EPad Thermal Release Path section. Ordering Information Table. Added lead-free part number, marking and note. Updated format throughout the datasheet. 12/06/07 IDT™ / ICS™ 3.3V LVPECL FANOUT BUFFER 19 ICS8534AY-01 REV. A DECEMBER 6, 2007 ICS8534-01 LOW SKEW, 1-TO-22 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER Innovate with IDT and accelerate your future networks. Contact: www.IDT.com www.IDT.com For Sales For Tech Support 800-345-7015 408-284-8200 Fax: 408-284-2775 [email protected] 480-763-2056 Corporate Headquarters Asia Pacific and Japan Europe Integrated Device Technology, Inc. 6024 Silver Creek Valley Road San Jose, CA 95138 United States 800 345 7015 +408 284 8200 (outside U.S.) Integrated Device Technology Singapore (1997) Pte. Ltd. Reg. No. 199707558G 435 Orchard Road #20-03 Wisma Atria Singapore 238877 +65 6 887 5505 IDT Europe, Limited 321 Kingston Road Leatherhead, Surrey KT22 7TU England +44 (0) 1372 363 339 Fax: +44 (0) 1372 378851 © 2007 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. 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