ASIC Datasheet

2016
DF6811K IP Core
8-bit Fast Microcontroller v. 3.02
COMPANY OVERVIEW
Digital Core Design is a leading IP Core provider
and a System-on-Chip design house. The company
was founded in 1999 and since the very beginning
has been focused on IP Core architecture improvements. Our innovative, silicon proven solutions have been employed by over 300 customers
and with more than 500 hundred licenses sold to
companies like Intel, Siemens, Philips, General
Electric, Sony and Toyota. Based on more than 70
different architectures, starting from serial interfaces to advanced microcontrollers and SoCs, we
are designing solutions tailored to your needs.
CPU FEATURES
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FAST architecture, 4 times faster than the original
implementation
Software compatible with industry standard
68HC11
10 times faster multiplication
16 times faster division
De-multiplexed Address/Data Bus to allow easy
integration with external memories.
Interrupt Controller
Two power saving modes: STOP, WAIT
Fully synthesizable, static synchronous design with
no internal tri-states
No internal reset generator or gated clock
Scan test ready
IP CORE OVERVIEW
The following document contains a brief description of the DF6811K core functionality. The
DF6811K is an advanced, 8-bit MCU IP Core with
highly sophisticated, on-chip peripheral capabilities. The DF6811K has a FAST architecture, which is
4 times faster compared to the original implementation. In the standard configuration, the core has
major peripheral functions integrated on-chip. An
asynchronous serial communications interface
(SCI) and separate synchronous serial peripheral
interface (SPI), are included. The main 16-bit, freerunning timer system has three input capture and
five output-compare lines, and a real-time interrupt function. An 8-bit pulse accumulator subsystem can count external events or measure external
periods. Self-monitoring, on-chip circuitry is included, to protect the DF6811K against system
errors. A computer operating properly (COP)
watchdog system protects against software failures. An illegal opcode detection circuit provides a
non-maskable interrupt, if illegal opcode is detected. Two software-controlled power-saving modes WAIT and STOP are available, to conserve additional power. These modes make the D68HC11K IP
Core especially attractive for automotive and battery-driven applications. The DF6811K has a builtTM
in real time hardware On-Chip Debugger DoCD ,
allowing easy software debugging and validation.
The DF6811K is fully customizable - it is delivered
in the exact configuration, to meet user’s requirements. It includes fully automated test bench with
complete set of tests, allowing easy package validation at each stage of SoC design flow. The
DF6811K Microcontroller Core can be used
as a replacement for any of the following HC11
Microcontrollers:
MC68HC(L)11K0,
MC68HC(L)11K1, MC68HC(L)11K4, MC68HC11KS2,
MC68HC711K4,
MC68HC711KS2
and
MC68HC11KW1.
PERIPHERALS
The peripherals listed below are implemented
in the standard configuration of DF6811K.
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TM
DoCD
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I/O Ports
Interrupt Controller
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Two major modes of operation
Simple event counter
Gated time accumulation
Clocked by internal source or external pin
SPI – Master and Slave Serial Peripheral Interface
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Three independent input-capture
Five output-compare channels
Events capturing
Pulses and digital signals generation
Gated timers
Sophisticated comparator
8-bit Pulse accumulator
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16 bit free running counter
Four stage programmable prescaler
Real Time Interrupt
16-bit Compare/Capture Unit
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Dedicated vector and interrupt priority for each interrupt source
Main16-bit timer/counter system
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On-Chip Debugger
Processor execution control
Read, write all processor contents
Hardware execution breakpoints
Three wire communication interface
Software selectable polarity and phase of serial clock
SCK
System errors detection
Allows operation from a wide range of system clock
frequencies (build-in 5-bit timer)
Interrupt generation
Full-duplex UART - SCI
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Standard Non-return to Zero format
8 or 9 bit data transfer
Integrated baud rate generator
Noise, Overrun and Framing error detection
IDLE and BREAK characters generation
Wake-up block to recognize UART wake-up from IDLE
condition
Three SCI related interrupts
PWM – Modulation Timer/Counter
Memory extension unit and Chip select
1
Copyright © 1999-2016 DCD – Digital Core Design. All Rights Reserved.
All trademarks mentioned in this document are the property
of their respective owners.
DELIVERABLES
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Source code:
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VHDL Source Code or/and
VERILOG Source Code or/and
Encrypted, or plain text EDIF
VHDL & VERILOG test bench environment
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Active-HDL automatic simulation macros
ModelSim automatic simulation macros
Tests with reference responses
Technical documentation
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Installation notes
HDL core specification
Datasheet
Synthesis scripts
Example application
Technical support
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IP Core implementation support
3 months maintenance
● Delivery of the IP Core and documentation updates, minor
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and major versions changes
Phone & email support
PINS DESCRIPTION
PIN
clk
reset
cmf
halt
moda_lir
modb
irq
xirq
portx
adcdatai
adcdatao
adcclock
adccs
esi
eso
esck
ecs
TYPE
DESCRIPTION
input
Global system clock
input
Power on reset vector fetch
input
Clock monitor fail vector fetch
Output
Used during STOP to disable CLK
in/out
Mode A input LIR output
input
Mode B input
input
Interrupt input
input
Non-maskable interrupt input
in/out
Ports I/O pins shared with peripherals
D68HC11 Microcontroller pins
input
Serial ADC data input
output
Serial Data output
output
Serial Clock to external ADC
output
Chip Select to external ADC
Optional external ADC Controller pins
input
Serial EEPROM Data input
output
Serial EEPROM Data output
output
Serial EEPROM Clock
output
EEPROM Chip Select
Optional external EEPROM controller pins
clkdocd
docddatai
docddatao
docdclk
input
DoCDTM clock input
input
DoCDTM serial Data input
output
DoCDTM Serial Data Output
output
DoCDTM Serial Clock Output
DoCD debugger interface pins
DESIGN FEATURES
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One global system clock
Synchronous reset
All asynchronous input signals are synchronized
before internal use
LICENSING
Comprehensible and clearly defined licensing
methods without royalty-per-chip fees make use
of our IP Cores easy and simple.
Single-Site license option – dedicated to small and
middle sized companies, which run their business
in one place.
Multi-Site license option – dedicated to corporate
customers, who operate at several locations. The
licensed product can be used in selected company
branches.
In all cases the number of IP Core instantiations
within a project and the number of manufactured
chips are unlimited. The license is royalty-per-chip
free. There are no restrictions regarding the time
of use.
There are two formats of the delivered IP Core:
VHDL or Verilog RTL synthesizable source code
called HDL Source code
FPGA EDIF/NGO/NGD/QXP/VQM called Netlist
UNITS SUMMARY
Control Unit - Performs the core synchronization
and data flow control. This module manages execution of all instructions. The Control Unit also manages
execution of STOP instruction and wakes the processor up from the STOP mode.
Opcode Decoder - Performs an instruction opcode
decoding and the control functions for all other
blocks.
ALU - Arithmetic Logic Unit performs the arithmetic
and logic operations, during execution of an instruction. It contains accumulator (A), Condition Code
Register (CCREG), Index registers (X) and related logic
like arithmetic unit, logic unit and multiplier.
Bus Controller – Program Memory, Data Memory
& SFR’s (Special Function Register) interface - controls
access into the program and data memories and
special registers. It contains Program Counter (PC),
Stack Pointer (SP) register and related logic.
Interrupt Controller - extended IC has implemented
7-level interrupt priority control. The interrupt requests may come from external pin (IRQ), as well as
from particular peripherals. The DF6805 peripheral
systems generate maskable interrupts, which are
recognized only if the global interrupt mask bit (I)
in the CCR is cleared. Maskable interrupts are prioritized, according to default arrangement established
during reset. When interrupt condition occurs,
an interrupt status flag is set, to indicate the condition.
Timer, Compare Capture & COP Watchdog –
This timer system is based on a free-running, 16-bit
counter, with a 4-stage programmable prescaler.
2
Copyright © 1999-2016 DCD – Digital Core Design. All Rights Reserved.
All trademarks mentioned in this document are the property
of their respective owners.
A timer overflow function allows software to extend
the timing capability of the system, beyond the 16-bit
range of the counter. Three independent inputcapture functions are used, to automatically record
the time, when a selected transition is detected
at a respective timer input pin. Five output-compare
functions are included, for generating output signals
or for timing software delays. Since the input-capture
and output-compare functions may not be familiar to
all users, these concepts are explained in greater
detail. A programmable periodic interrupt circuit
called RTI is tapped off of the main 16-bit timer counter. Software can select one of four rates for the RTI,
which is most commonly used to pace the execution
of software routines. The COP watchdog function, is
loosely related to the main timer in that the clock
input to the COP system (clk*217) is tapped off the
free-running counter chain. The timer subsystem
involves more registers and control bits, than any
other subsystem on the MCU. Each of the three input-capture functions has its own 16-bit time capture
latch (input-capture register); and each of the five
output-compare functions has its own 16-bit compare
register. All timer functions, including the timer overflow and RTI, have their own interrupt controls and
separate interrupt vectors. Additional control bits
permit software, to control the edge(s), that trigger
each input-capture function and the automatic actions that result from output-compare functions.
Although hardwired logic is included to automate
many timer activities, this timer architecture is mainly
a software-oriented system. This structure is easily
adaptable to a very wide range of applications, although for some specific timing applications it is not as
efficient, as dedicated hardware.
SCI - The SCI is a full-duplex UART type, asynchronous
system, using standard non return to zero (NRZ) format : 1 start bit, 8 or 9 data bits and a 1 stop bit. The
D68HC11E resynchronizes the receiver bit clock on all
one to zero transitions in the bit stream. Therefore,
differences in baud rate, between the sending device
and the SCI, are not as likely to cause reception errors. Three logic samples are taken near the middle of
data bit time and majority logic decides the sense for
the bit. For the start and stop bits, seven logic samples are taken. Even if noise causes one of these
samples to be incorrect, the bit will still be received
correctly. The receiver also has the ability, to enter a
temporary standby mode (called receiver wakeup), to
ignore messages intended for a different receiver.
Logic automatically wakes the receiver up, in time to
see the first character of the next message. This
wakeup feature
greatly reduces CPU overhead in multi-drop SCI networks. The SCI transmitter can produce queued characters of idle (whole characters of all logic 1) and
break (whole characters of all logic 0). In addition to
the usual transmit data register empty (TDRE) status
flag, this SCI also provides transmit complete (TC)
indication that can be used in applications with a
modem.
SPI Unit – it’s a fully configurable master/slave Serial
Peripheral Interface, which allows user to configure
polarity and phase of serial clock signal SCK. It allows
the microcontroller, to communicate with serial peripheral devices. It is also capable of interprocessor
communications, in a multi-master system. A serial
clock line (SCK) synchronizes shifting and sampling of
the information, on the two independent serial data
lines. SPI data are simultaneously transmitted and
received. SPI system is flexible enough, to interface
directly with numerous standard product peripherals,
from several manufacturers. Data rates are as high as
CLK/4. Clock control logic allows a selection of clock
polarity and a choice of two fundamentally different
clocking protocols, to accommodate most available
synchronous serial peripheral devices. When the SPI
is configured as a master, software selects one of four
different bit rates for the serial clock. SPI automatically drives slave select outputs SSO[7:0] and address SPI
slave device, to exchange serially shifted data. Errordetection logic is included, to support interprocessor
communications. A write-collision detector indicates,
when an attempt is made to write data to the serial
shift register, while a transfer is in progress. A multiple-master mode-fault detector automatically disables SPI output drivers, if more than one SPI devices,
simultaneously attempt to become a bus master.
Pulse Accumulator – This system is based on an 8-bit
counter and can be configured, to operate as a simple
event counter or for gated time accumulation. Unlike
the main timer, the 8-bit pulse accumulator counter
can be read or written at any time (the 16-bit counter
in the main timer cannot be written). Control bits
allow the user, to configure and control the pulse
accumulator subsystem. Two maskable interrupts are
associated with the system, each having its own controls and interrupt vector. The PAI pin associated with
the pulse accumulator can be configured to act as a
clock (event counting mode) or as a gate signal, to
enable a free-running E divided by 64 clock to the 8bit counter (gated time accumulation mode). The
alternate functions of the pulse accumulator input
(PAI) pin, present some interesting application possibilities.
I/O Ports - All ports are 8-bit general-purpose bidirectional I/O system. The PORTA, PORTB, PORTC,
PORTD data registers have their corresponding data
direction registers DDRA, DDRC, DDRD to control
ports data flow. It assures that all DF6811’s ports
have full I/O selectable registers. Writes to any ports
pins cause data to be stored in the data registers.
If any port pins are configured as output, then data
registers are driven out of those pins. Reads from
port pins configured as input, causes that input pin is
read. If port pins is configured as output, during read
data register is read. Writes to any ports pins,
3
Copyright © 1999-2016 DCD – Digital Core Design. All Rights Reserved.
All trademarks mentioned in this document are the property
of their respective owners.
not configured as outputs, do not cause data to be
driven out of those pins, but the data is stored
in the output registers. Thus, if the pins later become
outputs, the last data written to port will be driven
out the port pins.
ADCCTRL – External ADC Controller, used
as an interface between DF6811 internal registers and
external serial/parallel ADC converter. This module
has several different options, so its details are described in a separate document.
EEPROMCTRL – External Serial EEPROM controller.
Manage data exchange between D68HC11E
and external EEPROM. During initialization copy contents of whole external EEPROM to internal EEPRAM
(EEPROM Mirror implemented in standard parallel
RAM). This module has several different options, so
its details are described in separate document.
OPTIONAL PERIPHERALS
Optional peripherals (not included in the presented
DF6811K Microcontroller Core) are also available.
The optional peripherals can be implemented upon
customer’s request.
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Memory expansion - unit able to extend the memory
space beyond the physical 64kB.
TIMER 2 - Timer 2 is available in DF6811KW1 only,
it comprises a 4-stage prescaler and a 16-bit counter.
It has three associated 16-bit output compare registers, along with a software-programmable input
Capture or output compare register. The functions of
Timer 2 share I/O with the pins of port J.
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FADD, FSUB- addition, subtraction
FMUL, FDIV- multiplication, division
FSQRT- square root
FUCOM- compare
FCHS - change sign
FABS - absolute value
FSIN, FCOS- sine, cosine
FPTAN, FPATAN- tangent, arcs tangent
Floating-Point Arithmetic Coprocessor (DFPAU)
IEEE-754 standard single precision
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FADD, FSUB - addition, subtraction
FMUL, FDIV- multiplication, division
FSQRT- square root
FUCOM - compare
FCHS - change sign
FABS - absolute value
Floating-Point Math Coprocessor (DFPMU) - IEEE754 standard single precision real, word and short
integers
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Master operation
Multi-master systems supported
Performs arbitration and clock synchronization
Interrupt generation
Supports speed up to 3,4Mb/s (standard, fast & HS
modes)
Allows operation from a wide range of clock frequencies (build-in 8-bit timer)
User-defined timing
Floating-Point Arithmetic Coprocessor (DFPAU)
IEEE-754 standard single precision
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TM
DoCD - Debug Unit – it’s a real-time hardware debugger, which provides debugging capability
of a whole SoC system. Unlike other on-chip debuggers, DoCD™ provides non-intrusive debugging
of running application. It can halt, run, step into
or skip an instruction, read/write any contents
of microcontroller, including all registers, internal,
external, program memories, all SFRs, including user
defined peripherals. Hardware breakpoints can be set
and controlled on program memory, internal
and external data memories, as well as on SFRs.
Hardware breakpoint is executed, if any write/read
occurs at particular address, with certain data pattern
or without pattern. The DoCDTM system includes
three-wire interface and complete set of tools,
to communicate and work with core in real time
debugging. It is built as scalable unit and some features can be turned off by the user, to save silicon
and reduce power consumption. When debugger is
not used, it is automatically switched to power save
mode. Finally, when debug option is no longer used,
whole debugger is turned off. The separate CLKDOCD
clock line allows the debugger to operate, while the
CPU is in STOP mode and the major clock line CLK is
stopped.
I2C Master & Slave bus controllers
FADD, FSUB - addition, subtraction
FMUL, FDIV- multiplication, division
FSQRT- square root
FUCOM - compare
FCHS - change sign
FABS - absolute value
Floating-Point Math Coprocessor (DFPMU) - IEEE754 standard single precision real, word and short
integers
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FADD, FSUB- addition, subtraction
FMUL, FDIV- multiplication, division
FSQRT- square root
FUCOM- compare
FCHS - change sign
FABS - absolute value
FSIN, FCOS- sine, cosine
FPTAN, FPATAN- tangent, arcs tangent
Additional special internal interrupt dedicated for
DFPAU or DFPMU
TIMER 3 - Timer 3 is available in DF6811KW1 only,
it comprises a 4-stage prescaler and a 16-bit counter.
It has three associated 16-bit output compare registers, along with a software-programmable input
Capture or output compare register. The functions of
Timer 3 share I/O with the pins of Port K
4
Copyright © 1999-2016 DCD – Digital Core Design. All Rights Reserved.
All trademarks mentioned in this document are the property
of their respective owners.
BLOCK DIAGRAM
OC1/PAI
OC1/OC2
OC1/OC3
Timer 1
OC1/OC4
IC4/OC1/OC5
IC1
Periodic interrupt
IC2
COP watchdog
IC3
Port A
Pulse accumulator
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
Port D
Internal EEPROM Memory
replaced by external serial
EEPROM Controlled
by EEPROMCTRL
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
Port E
ESI
ESO
ESCK
ECS
PE7
PE6
PE5
PE4
PE3
PE2
PE1
PE0
IRAM
IROM /
EPROM
SPI
SS
SCK
MOSI
MISO
SCI
TXD
RXD
ADC
DOCDDATAI
DOCDDATAO
DOCDCLK
Replaced by
External
SERIAL ADC
DoCD Debugger
ADCDATAI
ADCDATAO
ADCCLOCK
ADCCS
Timer 2
Timer 3
CHIP Select
CSPROG
CSGP2
CSGP1
CSIO
PWM
CSPROG
CSGP2
CSGP1
CSIO
Port H
XIRQ
IRQ
RESET
MODA/LIR
MODB
PH7
PH6
PH5
PH4
PH3
PH2
PH1
PH0
Port G
OC4/IC1
OC3
OC2
OC1
ECIN
PG7
PG6
PG5
PG4
PG3
PG2
PG1
PG0
RW
D68HC11
CPU
MEM
Expansion
XA18
XA17
XA16
XA15
XA14
XA13
DATA7
DATA6
DATA5
DATA4
DATA3
DATA2
DATA1
DATA0
Port F
Port C
PC7
PC6
PC5
PC4
PC3
PC2
PC1
PC0
ADDR7
ADDR6
ADDR5
ADDR4
ADDR3
ADDR2
ADDR1
ADDR0
Port B
PF7
PF6
PF5
PF4
PF3
PF2
PF1
PF0
ADDR15
ADDR14
ADDR13
ADDR12
ADDR11
ADDR0
ADDR9
ADDR8
Non-multiplexed address and data buses
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0
PK7
PK6
PK5
PK4
PK3
PK2
PK1
PK0
OC4/IC1
OC3
OC2
OC1
ECIN
Interrupts
&
mode
select
Port K
PJ7
PJ6
PJ5
PJ4
PJ3
PJ2
PJ1
PJ0
Port J
Controlled by
ADCCTRL
5
Copyright © 1999-2016 DCD – Digital Core Design. All Rights Reserved.
All trademarks mentioned in this document are the property
of their respective owners.
D68HC11 AND DF6811 MICROCONTROLLERSOVERVIEW
READY for Prg. and
Data memories
Compare\Capture
Main Timer System
-
-
-
-
-
DF6805
4.1
64k
64k
-
7
7
-
-
*
2/2*
1*
D68HC05
1.0
64k
64k
-
7
7
-
-
*
2/2*
1*
DF6808
3.2
64k
64k
-
7
7
-
-
*
2/2*
1*
D68HC08
1.0
64k
64k
-
7
7
-
-
*
2/2*
1*
D68HC11E
1.0
64k
64k
-
20
17
1*
*
5/3*
1*
D68HC11F
1.0
64K
64K
-
20
17
1*
*
5/3*
1*
D68HC11KW1
1.0
1M
1M
25
22
1*
*
13/6*
3*
D68HC11K
1.0
1M
1M
20
17
1*
*
5/3*
2*
DF6811E
4.4
64k
64k
-
20
17
1*
*
5/3*
1*
DF6811F
4.4
64k
64k
-
20
17
1*
*
5/3*
1*
DF6811K
4.4
1M
1M
20
17
1*
*
5/3*
2*
-
-
-
-
-
-
*
4
+
*
4
+
*
4
*
4
*
4
12 000
*
7
13 500
*
10
21 000
*
7
16 000
*
4
*
*
*
12 000
*
4
*
*
*
13 000
*
7
Size – ASIC gates
Data Pointers
2
2
DoCD Debugger
Real Time Interrupt
2
2
Interface for
additional SFRs
Interrupt levels
-
Pulse accumulator
Interrupt sources
64k
64k
64k
Watchdog Timer
Motorola Memory
Expansion Logic
64k
64k
64k
SPI M/S Interface
Paged Data Memory
space
1
1
1
I\O Ports
Physical Linear
memory space
D6802
D6803
D6809
Design
SCI (UART)
Speed acceleration
The main features of each DF68XX family member have been summarized in the table below. It gives a brief
member characteristic, helping you to select the most suitable IP Core for your application. You can specify
your own peripheral set (including listed above and the others) and request the core modifications.
3 900
6 000
9 000
*
-
6 700
*
-
6 700
*
-
8 900
*
-
8 900
16 000
D68HCXX family of High Performance Microcontroller Cores
+ optional
* configurable
CONTACT
Digital Core Design Headquarters:
Wroclawska 94, 41-902 Bytom, POLAND
e-mail:
tel.:
fax:
[email protected]
0048 32 282 82 66
0048 32 282 74 37
Distributors:
Please check:
http://dcd.pl/sales
6
Copyright © 1999-2016 DCD – Digital Core Design. All Rights Reserved.
All trademarks mentioned in this document are the property
of their respective owners.
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