ASIC Datasheet

2016
DI2CS IP Core
I2C Bus Interface - Slave v. 4.00
COMPANY OVERVIEW
Digital Core Design is a leading IP Core provider
and a System-on-Chip design house. The company
was founded in 1999 and since the very beginning
has been focused on IP Core architecture improvements. Our innovative, silicon proven solutions have been employed by over 300 customers
and with more than 500 hundred licenses sold to
companies like Intel, Siemens, Philips, General
Electric, Sony and Toyota. Based on more than 70
different architectures, starting from serial interfaces to advanced microcontrollers and SoCs, we
are designing solutions tailored to your needs.
IP CORE OVERVIEW
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The I C is a two-wire, bi-directional serial bus,
which provides simple and efficient method of data
transmission over short distance, between many
devices. The DI2CS core provides an interface between a microprocessor / microcontroller and an
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I C bus. It can work as a slave transmitter or a slave
receiver, depending on a working mode determined by the master device. The DI2CS core incor2
porates all features required by the latest I C specification, including clock synchronization, arbitration and High-speed transmission mode. The DI2CS
supports all transmission speed modes.
KEY FEATURES
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Conforms to v.4.0 of the I C specification
Slave operation
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Support for all transmission speeds
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Slave transmitter
Slave receiver
Standard (up to 100 kb/s)
Fast (up to 400 kb/s)
Fast Plus (up to 1 Mb/s)
High Speed (up to 3,4 Mb/s)
Allows operation from a wide range of input clock
frequencies
Simple interface allows easy connection to microprocessor/microcontroller devices
Interrupt generation
User-defined data setup time
Fully synthesizable
Static synchronous design with positive edge clocking and synchronous reset
No internal tri-states
Scan test ready
APPLICATIONS
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Embedded microprocessor boards
Consumer and professional audio/video
Low-power applications
Communication systems
Cost-effective reliable automotive systems
DELIVERABLES
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Source code:
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VHDL Source Code or/and
VERILOG Source Code or/and
Encrypted, or plain text EDIF
VHDL & VERILOG test bench environment
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Active-HDL automatic simulation macros
ModelSim automatic simulation macros
Tests with reference responses
Technical documentation
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Installation notes
HDL core specification
Datasheet
Synthesis scripts
Example application
Technical support
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IP Core implementation support
3 months maintenance
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Delivery of the IP Core and documentation updates, minor
and major versions changes
Phone & email support
SYMBOL
datai(7:0)
address(1:0)
datao(7:0)
cs
rd
we
scli
sdai
irq
sclo
sdao
rst
clk
LICENSING
Comprehensible and clearly defined licensing
methods without royalty-per-chip fees make use
of our IP Cores easy and simple.
Single-Site license option – dedicated to small and
middle sized companies, which run their business
in one place.
Multi-Site license option – dedicated to corporate
customers, who operate at several locations. The
licensed product can be used in selected company
branches.
In all cases the number of IP Core instantiations
within a project and the number of manufactured
chips are unlimited. The license is royalty-per-chip
free. There are no restrictions regarding the time
of use.
There are two formats of the delivered IP Core:
VHDL or Verilog RTL synthesizable source code
FPGA EDIF/NGO/NGD/QXP/VQM (Netlist)
1
Copyright © 1999-2016 DCD – Digital Core Design. All Rights Reserved.
All trademarks mentioned in this document are the property
of their respective owners.
BLOCK DIAGRAM
The figure below shows the DI2CS IP Core block diagram.
Receive
Receive
Data
datai(7:0)
datao(7:0)
address(1:0)
Shift
Register
CPU
Interface
cs
we
rd
Send Data
Input
Filter
sdai
Output
Register
sdao
Own
Address
Detection
irq
Control
Register
Control
Logic
Status
Register
rst
clk
Synchronization
Logic
Input
Filter
scli
Clock Stretching
Output
Register
sclo
IMPLEMENTATION
Figure below show the typical DI2CS implementations in system with Standard, Fast, Fast Plus and High-speed
devices.
VDD
RP
RP
SDA
SCL
RS
sdai
RS
RS
RS
sda
sdao
open drain
Master
device
DI2CS
scli
scl
sclo
open drain
2
Copyright © 1999-2016 DCD – Digital Core Design. All Rights Reserved.
All trademarks mentioned in this document are the property
of their respective owners.
DI2CX CORES OVERVIEW
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Spike filtering
User defined timing
High-speed mode
Fast Plus Mode
Fast mode
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Standard mode
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10-bit addressing
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7-bit addressing
Arbitration
Passive device interface
CPU interface
Slave operation
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Clock synchronization
3.0
3.0
3.0
3.0
Interrupt generation
DI2CM
DI2CS
DI2CSB
DI2CMS
Master operation
Design
I2C specification version
The main features of each Digital Core Design I C compliant cores have been summarized in the table below. It
gives a brief member characteristic, helping you to select the most suitable IP Core for your application.
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I2C Cores summary table
UNITS SUMMARY
CPU Interface – Performs the interface functions
between DI2CS internal blocks and microprocessor.
It allows easy connection of the core with
the microprocessor/microcontroller system.
Control Logic – Manages execution of all commands sent via interface. Synchronizes internal
data flow.
Shift Register – Controls SDA line, performs data
and address shifts during the data transmission
and reception.
Control Register – Contains five control bits used
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for performing all types of I C Bus transmissions.
Status Register – Contains seven status bits that
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indicate state of the I C Bus and the DI2CS core.
Input Filter – Performs spike filtering.
Synchronization Logic – Performs DI2CS core synchronization.
PERFORMANCE
The following table gives a survey about the Core
area and performance in ASIC devices (all key features included):
Technology
0.25 typical
0.25 typical
Optimization
Gates
area
700
speed
1350
Core performance in ASIC devices
Fmax
220 MHz
650 MHz
CONTACT
Digital Core Design Headquarters:
Wroclawska 94, 41-902 Bytom, POLAND
e-mail:
tel.:
fax:
[email protected]
0048 32 282 82 66
0048 32 282 74 37
Distributors:
Please check:
http://dcd.pl/sales
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Clock Stretching – Performs I C SCL clock stretching when DI2CS core is not ready for next transmission.
PINS DESCRIPTION
PIN
clk
rst
address(1:0)
cs
we
rd
scli
sdai
datai(7:0)
datao(7:0)
sclo
sdao
irq
TYPE
input
input
input
input
input
input
input
input
input
output
output
output
output
DESCRIPTION
Global clock
Global reset
Processor address lines
Chip select
Processor write strobe
Processor read strobe
I2C bus clock line (input)
I2C bus data line (input)
Processor data bus (input)
Processor data bus (output)
I2C bus clock line (output)
I2C bus data line (output)
Processor interrupt line
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Copyright © 1999-2016 DCD – Digital Core Design. All Rights Reserved.
All trademarks mentioned in this document are the property
of their respective owners.
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