IDT ICS40004AI01

ICS840004I-01
FEMTOCLOCKS™ CRYSTAL-TOLVCMOS/LVTTL FREQUENCY SYNTHESIZER
GENERAL DESCRIPTION
FEATURES
The ICS840004I-01 is a 4 output LVCMOS/LVTTL
Synthesizer optimized to generate Ethernet
HiPerClockS™ reference clock frequencies and is a member of
the HiPerClocksTM family of high performance
clock solutions from IDT. Using a 25MHz, 18pF
parallel resonant crystal, the following frequencies can be
generated based on the 2 frequency select pins (F_SEL1:0):
156.25MHz, 125MHz, and 62.5MHz. The ICS840004I-01 uses
IDT’s 3rd generation low phase noise VCO technology and can
achieve 1ps or lower typical random rms phase jitter, easily
meeting Ethernet jitter requirements. The ICS840004I-01 is
packaged in a small 20-pin TSSOP package.
• Four LVCMOS/LVTTL outputs,
17Ω typical output impedance
ICS
• Selectable crystal oscillator interface
or LVCMOS single-ended input
• Supports the following output frequencies: 156.25MHz,
125MHz and 62.5MHz
• VCO range: 560MHz - 700MHz
• RMS phase jitter @ 156.25MHZ (1.875MHz - 20MHz):
0.52ps (typical)
• Output supply modes:
Core/Output
3.3V/3.3V
3.3V/2.5V
2.5V/2.5V
• -40°C to 85°C ambient operating temperature
• Available in both standard (RoHS 5) and lead-free RoHS
(6) packages
FREQUENCY SELECT FUNCTION TABLE
F_SEL1 F_SEL0
0
0
0
1
1
1
Inputs
M Divider N Divider
Value
Value
25
4
Output Frequency (MHz)
(25MHz Ref.)
M/N
Ratio Value
6.25
156.25
25
5
5
125
0
25
10
2.5
62.5
1
25
5
5
125 (default)
BLOCK DIAGRAM
OE
PIN ASSIGNMENT
Pullup
2
F_SEL1:0 Pullup:Pullup
nPLL_SEL Pulldown
nXTAL_SEL
XTAL_IN
Pulldown
25MHz
OSC
F_SEL1:0
0
1
00
01
10
11
XTAL_OUT
REF_CLK Pulldown
1
Phase
Detector
VCO
0
N
÷4
÷5
÷10
÷5 (default)
Q0
Q1
MR
840004AGI-01
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
F_SEL1
GND
Q0
Q1
VDDO
Q2
Q3
GND
XTAL_IN
XTAL_OUT
ICS840004I-01
20-Lead TSSOP
Q2
M = ÷25 (fixed)
F_SEL0
nc
nXTAL_SEL
REF_CLK
OE
MR
nPLL_SEL
V DDA
nc
VDD
Q3
6.5mm x 4.4mm x 0.92mm
package body
G Package
Top View
Pulldown
1
REV. A OCTOBER 22, 2007
ICS840004I-01
FEMTOCLOCKS™ CRYSTAL-TOLVCMOS/LVTTL FREQUENCY SYNTHESIZER
TABLE 1. PIN DESCRIPTIONS
Number
2, 9
Name
F_SEL0,
F_SEL1
nc
Unused
3
nXTAL_SEL
Input
Pulldown
4
REF_CLK
Input
Pulldown
5
OE
Input
Pullup
6
MR
Input
Pulldown
7
nPLL_SEL
Input
Pulldown
8
VDDA
Power
10
11,
12
13, 19
14, 15
17, 18
16
VDD
XTAL_OUT,
XTAL_IN
GND
Q3, Q2,
Q1, Q0
VDDO
Power
1, 20
Type
Input
Description
Pullup
Input
Power
Output
Power
Frequency select pin. LVCMOS/LVTTL interface levels.
No connect.
Selects between the cr ystal or REF_CLK inputs as the PLL reference
source. When HIGH, selects REF_CLK. When LOW, selects XTAL
inputs. LVCMOS/LVTTL interface levels.
Single-ended LVCMOS/LVTTL reference clock input.
Output enable pin. When HIGH, the outputs are active. When LOW, the
outputs are in a high impedance state. LVCMOS/LVTTL interface levels.
Active HIGH Master Reset. When logic HIGH, the internal dividers are
reset causing the otuputs to go low. When logic LOW, the internal
dividers and the outputs are enabled. LVCMOS/LVTTL interface levels.
PLL Bypass. When LOW, the output is driven from the VCO output.
When HIGH, the PLL is bypassed and the output frequency =
reference clock frequency/N output divider.
LVCMOS/LVTTL interface levels.
Analog supply pin.
Core supply pin.
Cr ystal oscillator interface. XTAL_OUT is the output.
XTAL_IN is the input.
Power supply ground.
Single-ended clock outputs. LVCMOS/LVTTL interface levels.
17Ω typical output impedance.
Output supply pin.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
Parameter
CIN
Input Capacitance
Test Conditions
Minimum
Typical
4
Maximum
Units
pF
CPD
Power Dissipation Capacitance
8
pF
RPULLUP
Input Pullup Resistor
51
kΩ
RPULLDOWN
Input Pulldown Resistor
51
kΩ
ROUT
Output Impedance
VDDO = 3.3V±5%
17
Ω
VDDO = 2.5V±5%
21
Ω
840004AGI-01
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REV. A OCTOBER 22, 2007
ICS840004I-01
FEMTOCLOCKS™ CRYSTAL-TOLVCMOS/LVTTL FREQUENCY SYNTHESIZER
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VDD
4.6V
Inputs, VI
-0.5V to VDD + 0.5 V
Outputs, VO
-0.5V to VDD + 0.5V
Package Thermal Impedance, θJA
73.2°C/W (0 lfpm)
Storage Temperature, TSTG
-65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, VDDD = VDDA = 3.3V±5%, VDDO = 3.3V±5% OR 2.5V±5%, TA = -40°C TO 85°C
Symbol
VDD
Parameter
Core Supply Voltage
VDDA
Analog Supply Voltage
VDDO
Output Supply Voltage
IDD
IDDA
IDDO
Test Conditions
Minimum
3.135
Typical
3.3
Maximum
3.465
Units
V
3.135
3.3
3.465
V
3.135
3.3
3.465
V
2.375
2.5
2.625
V
Power Supply Current
100
mA
Analog Supply Current
Output Supply Current
12
10
mA
mA
Maximum
2.625
Units
V
TABLE 3B. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = VDDO = 2.5V±5%, TA = -40°C TO 85°C
Symbol
VDD
Parameter
Core Supply Voltage
Test Conditions
Minimum
2.375
Typical
2.5
VDDA
Analog Supply Voltage
2.375
2.5
2.625
V
VDDO
Output Supply Voltage
2.375
2.5
2.625
V
IDD
Power Supply Current
95
mA
IDDA
IDDO
Analog Supply Current
Output Supply Current
12
8
mA
mA
840004AGI-01
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REV. A OCTOBER 22, 2007
ICS840004I-01
FEMTOCLOCKS™ CRYSTAL-TOLVCMOS/LVTTL FREQUENCY SYNTHESIZER
TABLE 3C. LVCMOS/LVTTL DC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V±5% OR 2.5V±5%, OR
VDD = VDDA = 3.3V±5%, VDDO = 2.5V±5%, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
VIH
Input High Voltage
VIL
Input Low Voltage
IIH
Input
High Current
OE, F_SEL0:1
nPLL_SEL, MR,
nXTAL_SEL, REF_CLK
OE, F_SEL0:1
IIL
Input
Low Current
nPLL_SEL, MR,
nXTAL_SEL, REF_CLK
VOH
Output High Voltage; NOTE 1
VOL
Output Low Voltage; NOTE 1
Minimum Typical
Maximum
Units
VDD = 3.3V
2
VDD + 0.3
V
VDD = 2.5V
1.7
VDD + 0.3
V
VDD = 3.3V
-0.3
0.8
V
VDD = 2.5V
VDD = VIN = 3.465V or
2.625V
VDD = VIN = 3.465V or
2.625V
VDD = 3.465V or 2.5V,
VIN = 0V
-0.3
0.7
V
5
µA
150
µA
-150
µA
VDD = 3.465V or 2.5V,
VIN = 0V
-5
µA
VDDO = 3.3V ± 5%
2.6
V
VDDO = 2.5V ± 5%
1.8
V
VDDO = 3.3V or 2.5V ± 5%
0.5
V
NOTE 1: Outputs terminated with 50Ω to VDDO/2. See Parameter Measurement Information, Output Load Test Circuit.
TABLE 4. CRYSTAL CHARACTERISTICS
Parameter
Test Conditions
Minimum
Mode of Oscillation
Typical
Maximum
Units
Fundamental
Frequency
25
MHz
Equivalent Series Resistance (ESR)
50
Ω
Shunt Capacitance
7
pF
Drive Level
1
mW
Maximum
Units
NOTE: Characterized using an 18pF parallel resonant cr ystal.
TABLE 5A. AC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V±5%, TA = -40°C TO 85°C
Symbol
Parameter
fOUT
Output Frequency
t sk(o)
Output Skew; NOTE 1, 2
t jit(Ø)
RMS Phase Jitter (Random);
NOTE 3
t R / tF
odc
Output Rise/Fall Time
Output Duty Cycle
Test Conditions
Minimum
Typical
F_SEL[1:0] = 00
140
156.25
175
MHz
F_SEL[1:0] = 01 or 11
112
125
140
MHz
F_SEL[1:0] = 10
56
62.5
70
MHz
60
ps
156.25MHz, (1.875MHz - 20MHz)
0.52
ps
125MHz, (1.875MHz - 20MHz)
0.65
ps
62.5MHz, (1.875MHz - 20MHz)
0.55
ps
20% to 80%
200
700
ps
F_SEL[1:0] = 00 or 01
43
57
%
51
%
F_SEL[1:0] = 10 or 11
49
NOTE 1: Defined as skew between outputs at the same supply voltages and with equal load conditions.
Measured at VDDO/2.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 3: Please refer to the Phase Noise Plot.
840004AGI-01
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REV. A OCTOBER 22, 2007
ICS840004I-01
FEMTOCLOCKS™ CRYSTAL-TOLVCMOS/LVTTL FREQUENCY SYNTHESIZER
TABLE 5B. AC CHARACTERISTICS, VDD = VDDA = 3.3V±5%, VDDO = 2.5V±5%, TA = -40°C TO 85°C
Symbol
fOUT
t sk(o)
Parameter
Output Frequency
Test Conditions
Minimum
Typical
Maximum
Units
F_SEL[1:0] = 00
140
156.25
175
MHz
F_SEL[1:0] = 01 or 11
112
125
140
MHz
F_SEL[1:0] = 10
56
62.5
70
MHz
Output Skew; NOTE 1, 2
60
156.25MHz, (1.875MHz - 20MHz)
t jit(Ø)
RMS Phase Jitter (Random);
NOTE 3
t R / tF
Output Rise/Fall Time
odc
Output Duty Cycle
ps
0.48
ps
125MHz, (1.875MHz - 20MHz)
0.59
ps
62.5MHz, (1.875MHz - 20MHz)
0.53
ps
20% to 80%
200
700
F_SEL[1:0] = 00 or 01
43
57
%
51
%
Maximum
Units
F_SEL[1:0] = 10 or 11
49
NOTE 1: Defined as skew between outputs at the same supply voltages and with equal load conditions.
Measured at VDDO/2.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 3: Please refer to the Phase Noise Plot.
ps
TABLE 5C. AC CHARACTERISTICS, VDD = VDDA = VDDO = 2.5V±5%, TA = -40°C TO 85°C
Symbol
Parameter
fOUT
Output Frequency
t sk(o)
Output Skew; NOTE 1, 2
t jit(Ø)
RMS Phase Jitter (Random);
NOTE 3
t R / tF
Output Rise/Fall Time
odc
Output Duty Cycle
Test Conditions
Minimum
Typical
F_SEL[1:0] = 00
140
156.25
175
MHz
F_SEL[1:0] = 01 or 11
112
125
140
MHz
F_SEL[1:0] = 10
56
62.5
70
MHz
60
ps
156.25MHz, (1.875MHz - 20MHz)
0.50
ps
125MHz, (1.875MHz - 20MHz)
0.60
ps
62.5MHz, (1.875MHz - 20MHz)
0.51
200
700
F_SEL[1:0] = 00 or 01
44
56
%
51
%
F_SEL[1:0] = 10 or 11
49
NOTE 1: Defined as skew between outputs at the same supply voltages and with equal load conditions.
Measured at VDDO/2.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 3: Please refer to the Phase Noise Plot.
840004AGI-01
ps
20% to 80%
5
ps
REV. A OCTOBER 22, 2007
ICS840004I-01
FEMTOCLOCKS™ CRYSTAL-TOLVCMOS/LVTTL FREQUENCY SYNTHESIZER
TYPICAL PHASE NOISE
AT
62.5MHZ @3.3V
➤
0
-10
-20
1Gb Ethernet Filter
-40
62.5MHz
-50
RMS Phase Jitter (Random)
1.875MHz to 20MHz = 0.55ps
-60
-70
-80
-90
-100
Raw Phase Noise Data
-110
➤
NOISE POWER dBc
Hz
-30
-120
-130
-140
-150
➤
-160
-170
Phase Noise Result by adding
1Gb Ethernet Filter to raw data
-180
-190
100
1k
10k
100k
1M
10M
100M
OFFSET FREQUENCY (HZ)
TYPICAL PHASE NOISE
AT
62.5MHZ @2.5V
0
➤
-10
-20
1Gb Ethernet Filter
NOISE POWER dBc
Hz
-30
-40
62.5MHz
-50
RMS Phase Jitter (Random)
1.875MHz to 20MHz = 0.51ps
-60
-70
-80
-90
-100
Raw Phase Noise Data
-110
➤
-120
-130
-140
-150
➤
-160
-170
Phase Noise Result by adding
1Gb Ethernet Filter to raw data
-180
-190
100
1k
10k
100k
1M
10M
100M
OFFSET FREQUENCY (HZ)
840004AGI-01
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REV. A OCTOBER 22, 2007
ICS840004I-01
FEMTOCLOCKS™ CRYSTAL-TOLVCMOS/LVTTL FREQUENCY SYNTHESIZER
TYPICAL PHASE NOISE
125MHZ @3.3V
AT
0
➤
-10
-20
10Gb Ethernet Filter
-40
125MHz
-50
RMS Phase Jitter (Random)
1.875MHz to 20MHz = 0.65ps (typical)
-60
-70
-80
-90
Raw Phase Noise Data
-100
-110
➤
NOISE POWER dBc
Hz
-30
-120
-130
-140
-150
➤
-160
-170
Phase Noise Result by adding
10Gb Ethernet Filter to raw data
-180
-190
100
1k
10k
100k
1M
10M
100M
OFFSET FREQUENCY (HZ)
TYPICAL PHASE NOISE
125MHZ @2.5V
AT
0
➤
-10
-20
10Gb Ethernet Filter
NOISE POWER dBc
Hz
-30
-40
125MHz
-50
RMS Phase Jitter (Random)
1.875MHz to 20MHz = 0.60ps (typical)
-60
-70
-80
-90
-100
Raw Phase Noise Data
-110
➤
-120
-130
-140
-150
➤
-160
-170
Phase Noise Result by adding
10Gb Ethernet Filter to raw data
-180
-190
100
1k
10k
100k
1M
10M
100M
OFFSET FREQUENCY (HZ)
840004AGI-01
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REV. A OCTOBER 22, 2007
ICS840004I-01
FEMTOCLOCKS™ CRYSTAL-TOLVCMOS/LVTTL FREQUENCY SYNTHESIZER
TYPICAL PHASE NOISE
AT
156.25MHZ @3.3V
0
➤
-10
-20
10Gb Ethernet Filter
-40
156.25MHz
-50
RMS Phase Jitter (Random)
1.875MHz to 20MHz = 0.52ps (typical)
-60
-70
-80
-90
Raw Phase Noise Data
-100
-110
➤
NOISE POWER dBc
Hz
-30
-120
-130
-140
-150
➤
-160
-170
Phase Noise Result by adding
10Gb Ethernet Filter to raw data
-180
-190
100
1k
10k
100k
1M
10M
100M
OFFSET FREQUENCY (HZ)
TYPICAL PHASE NOISE
AT
156.25MHZ @2.5V
0
➤
-10
-20
10Gb Ethernet Filter
-40
156.25MHz
-50
RMS Phase Jitter (Random)
1.875MHz to 20MHz = 0.50ps (typical)
-60
-70
-80
-90
Raw Phase Noise Data
-100
-110
➤
NOISE POWER dBc
Hz
-30
-120
-130
-140
-150
➤
-160
-170
Phase Noise Result by adding
10Gb Ethernet Filter to raw data
-180
-190
100
1k
10k
100k
1M
10M
100M
OFFSET FREQUENCY (HZ)
840004AGI-01
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REV. A OCTOBER 22, 2007
ICS840004I-01
FEMTOCLOCKS™ CRYSTAL-TOLVCMOS/LVTTL FREQUENCY SYNTHESIZER
PARAMETER MEASUREMENT INFORMATION
2.05V±5%
VDDA = 2.05V±5%
1.65V±5%
VDDA = 1.65V±5%
1.25V±5%
SCOPE
VDD,
VDDO
SCOPE
VDD
Qx
LVCMOS
LVCMOS
VDDO
Qx
GND
GND
-1.65V±5%
-1.25V±5%
3.3V CORE/3.3V OUTPUT LOAD AC TEST CIRCUIT
3.3V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT
1.25V±5%
Phase Noise Plot
VDDA = 1.25V±5%
Noise Power
SCOPE
VDD,
VDDO
Qx
LVCMOS
Phase Noise Mask
GND
f1
2.5V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT
RMS PHASE JITTER
V
80%
DDO
80%
2
Clock
Outputs
V
DDO
Qy
f2
RMS Jitter = Area Under the Masked Phase Noise Plot
-1.25V±5%
Qx
Offset Frequency
20%
20%
tR
tF
2
tsk(o)
OUTPUT SKEW
OUTPUT RISE/FALL TIME
V
DDO
2
Q0:Q3
t PW
t
odc =
PERIOD
t PW
x 100%
t PERIOD
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
840004AGI-01
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REV. A OCTOBER 22, 2007
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FEMTOCLOCKS™ CRYSTAL-TOLVCMOS/LVTTL FREQUENCY SYNTHESIZER
APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise. The ICS840004I-01 provides
separate power supplies to isolate any high switching
noise from the outputs to the internal PLL. VDD, VDDA, and VDDO
should be individually connected to the power supply
plane through vias, and bypass capacitors should be
used for each pin. To achieve optimum jitter performance,
power supply isolation is required. Figure 1 illustrates how
a 10Ω resistor along with a 10µF and a .01μF bypass
capacitor should be connected to each VDDA.
3.3V or 2.5V
VDD
.01μF
10Ω
VDDA
.01μF
10μF
FIGURE 1. POWER SUPPLY FILTERING
CRYSTAL INPUT INTERFACE
The ICS840004I-01 has been characterized with 18pF parallel resonant crystals. The capacitor values shown in Figure 2
below were determined using a 25MHz, 18pF parallel resonant crystal and were chosen to minimize the ppm error.
XTAL_IN
C1
22p
X1
18pF Parallel Cry stal
XTAL_OUT
C2
22p
ICS84332
ICS840004I-01
FIGURE 2. CRYSTAL INPUt INTERFACE
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REV. A OCTOBER 22, 2007
ICS840004I-01
FEMTOCLOCKS™ CRYSTAL-TOLVCMOS/LVTTL FREQUENCY SYNTHESIZER
LVCMOS TO XTAL INTERFACE
impedance of the driver (Ro) plus the series resistance
(Rs) equals the transmission line impedance. In addition,
matched termination at the crystal input will attenuate the
signal in half. This can be done in one of two ways. First,
R1 and R2 in parallel should equal the transmission line
impedance. For most 50Ω applications, R1 and R2 can be
100Ω. This can also be accomplished by removing R1 and
making R2 50Ω.
The XTAL_IN input can accept a single-ended LVCMOS
signal through an AC couple capacitor. A general interface
diagram is shown in Figure 3. The XTAL_OUT pin can
be left floating. The input edge rate can be as slow as
10ns. For LVCMOS inputs, it is recommended that the
amplitude be reduced from full swing to half swing in order
to prevent signal interference with the power rail and to
reduce noise. This configuration requires that the output
VDD
VDD
R1
Ro
.1uf
Rs
Zo = 50
XTAL_IN
R2
Zo = Ro + Rs
XTAL_OUT
Figure 3. GENERAL DIAGRAM FOR LVCMOS DRIVER TO XTAL INPUT INTERFACE
RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS
INPUTS:
OUTPUTS:
CRYSTAL INPUTS
For applications not requiring the use of the crystal oscillator
input, both XTAL_IN and XTAL_OUT can be left floating.
Though not required, but for additional protection, a 1kΩ
resistor can be tied from XTAL_IN to ground.
LVCMOS OUTPUTS
All unused LVCMOS output can be left floating. We
recommend that there is no trace attached.
REF_CLK INPUT
For applications not requiring the use of the reference clock,
it can be left floating. Though not required, but for additional
protection, a 1kΩ resistor can be tied from the REF_CLK to
ground.
LVCMOS CONTROL PINS
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional
protection. A 1kΩ resistor can be used.
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REV. A OCTOBER 22, 2007
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FEMTOCLOCKS™ CRYSTAL-TOLVCMOS/LVTTL FREQUENCY SYNTHESIZER
LAYOUT GUIDELINE
The C1=22pF and C2=22pF are recommended for frequency accuracy. For different board layout, the C1 and C2
may be slightly adjusted for optimizing frequency accuracy.
1kΩ pullup or pulldown resistors can be used for the logic
control input pins.
Figure 4 shows a schematic example of the ICS840004I01. An example of LVCMOS termination is shown in this
schematic. Additional LVCMOS termination approaches are
shown in the LVCMOS Termination Application Note. In this
example, an 18pF parallel resonant 25MHz crystal is used.
Logic Control Input Examples
Set Logic
Input to
'1'
VDD
Set Logic
Input to
'0'
VDD
RU1
1K
VDD=3.3V
VDDO=3.3V
RU2
Not Install
To Logic
Input
pins
R3
36
RD1
Not Install
RD2
1K
U1
VDDO
VDD
VDD
VDDA
R2
10
Zo = 50 Ohm
To Logic
Input
pins
C3
10uF
VDD
C4
0.01u
1
2
3
4
5
6
7
8
9
10
F_SEL0
nc
nXTAL_SEL
REF_CLK
OE
MR
nPLL_SEL
VDDA
nc
VDD
F_SEL1
GND
Q0
Q1
VDDO
Q2
Q3
GND
XTAL_IN
XTAL_OUT
LVCMOS
20
19
18
17
16
15
14
13
12
11
C6
0.1u
VDD
R5
100
Zo = 50 Ohm
C5
0.1u
840004i_01
R4
100
XTAL_OUT
C2
22pF
LVCMOS
X1
XTAL_IN
Optional Termination
C1
22pF
If not using the crystal input, it can be left floating.
For additional protection the XTAL_IN pin can be
tied to ground.
Unused outputs can be left floating. There should be
no trace attached to unused outputs. Device
characterized and specification limits set with all
outputs terminated.
FIGURE 4. ICS840004I-01 SCHEMATIC EXAMPLE
840004AGI-01
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FEMTOCLOCKS™ CRYSTAL-TOLVCMOS/LVTTL FREQUENCY SYNTHESIZER
RELIABILITY INFORMATION
TABLE 6. θJAVS. AIR FLOW TABLE FOR 20 LEAD TSSOP
θJA by Velocity (Linear Feet per Minute)
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
0
200
500
114.5°C/W
73.2°C/W
98.0°C/W
66.6°C/W
88.0°C/W
63.5°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS840004I-01 is: 3796
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FEMTOCLOCKS™ CRYSTAL-TOLVCMOS/LVTTL FREQUENCY SYNTHESIZER
PACKAGE OUTLINE - G SUFFIX
FOR
20 LEAD TSSOP
TABLE 7. PACKAGE DIMENSIONS
Millimeters
SYMBOL
MIN
N
MAX
20
A
--
1.20
A1
0.05
0.15
A2
0.80
1.05
b
0.19
0.30
c
0.09
0.20
D
6.40
E
E1
6.60
6.40 BASIC
4.30
e
4.50
0.65 BASIC
L
0.45
0.75
α
0°
8°
aaa
--
0.10
Reference Document: JEDEC Publication 95, MO-153
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FEMTOCLOCKS™ CRYSTAL-TOLVCMOS/LVTTL FREQUENCY SYNTHESIZER
TABLE 8. ORDERING INFORMATION
Part/Order Number
Marking
Package
Shipping Packaging
Temperature
ICS840004AGI-01
ICS40004AI01
20 Lead TSSOP
tube
-40°C to 85°C
ICS840004AGI-01T
ICS40004AI01
20 Lead TSSOP
2500 tape & reel
-40°C to 85°C
ICS840004AGI-01lLF
ICS0004AI01L
20 Lead "Lead-Free" TSSOP
tube
-40°C to 85°C
ICS840004AGI-01LFT
ICS0004AI01L
20 Lead "Lead-Free" TSSOP
2500 tape & reel
-40°C to 85°C
NOTE: Par ts that are ordered with an "LF" suffix tot he par t number are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology, Incorporated (IDT) assumes no responsibility for either its use or for
infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial
applications. Any other applications such as those requiring extended temperature ranges, high reliability or other extraordinary environmental requirements are not recommended without additional
processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical
instruments.
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FEMTOCLOCKS™ CRYSTAL-TOLVCMOS/LVTTL FREQUENCY SYNTHESIZER
REVISION HISTORY SHEET
Rev
Table
Page
A
T8
15
840004AGI-01
Description of Change
Ordering Informatin Table - corrected standard marking and added Lead Free
marking.
16
Date
10/22/07
REV. A OCTOBER 22, 2007