ispLSI 3256E Data Sheet

ispLSI® 3256E Device Datasheet
June 2010
All Devices Discontinued!
Product Change Notifications (PCNs) have been issued to discontinue all devices in this
data sheet.
The original datasheet pages have not been modified and do not reflect those changes.
Please refer to the table below for reference PCN and current product status.
Product Line
ispLSI 3256E
Ordering Part Number
ispLSI 3256E-70LB320
ispLSI 3256E-100LB320
ispLSI 3256E-70LQA
ispLSI 3256E-100LQA
Product Status
Reference PCN
PCN#09-10
Discontinued
PCN#12-09
5555 N.E. Moore Ct. z Hillsboro, Oregon 97124-6421 z Phone (503) 268-8000 z FAX (503) 268-8347
Internet: http://www.latticesemi.com
ispLSI 3256E
®
In-System Programmable High Density PLD
Functional Block Diagram
• HIGH-DENSITY PROGRAMMABLE LOGIC
— 256 I/O Pins
— 12000 PLD Gates
— 512 Registers
— High Speed Global Interconnect
— Wide Input Gating for Fast Counters, State
Machines, Address Decoders, etc.
— Small Logic Block Size for Random Logic
ORP
H2
ORP
ORP
H1
G3
H0
A0
A1
OR
G2
ORP
G1
G0
Boundary
Scan
D Q
F3
D Q
F2
D Q
F1
ORP
ORP
OR
• IN-SYSTEM PROGRAMMABLE
— 5V In-System Programmable (ISP™) using Lattice
ISP or Boundary Scan Test (IEEE 1149.1) Protocol
— Increased Manufacturing Yields, Reduced Time-toMarket, and Improved Product Quality
— Reprogram Soldered Devices for Faster Debugging
B0
Array
B1
Twin
GLB
D Q
F0
D Q
E3
D Q
E2
D Q
B2
E1
Global Routing Pool
B3
E0
C0
C1
ORP
C2
C3
ORP
ORP
A3
D Q
D0
D1
ORP
D2
ORP
Array
A2
ORP
• HIGH PERFORMANCE E2CMOS® TECHNOLOGY
— fmax = 100 MHz Maximum Operating Frequency
— tpd = 10 ns Propagation Delay
— TTL Compatible Inputs and Outputs
— Electrically Erasable and Reprogrammable
— Non-Volatile
— 100% Tested at Time of Manufacture
— Unused Product Term Shutdown Saves Power
AND Array
ORP
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ORP
H3
ORP
Features
D3
ORP
0139A/3256E
• 100% IEEE 1149.1 BOUNDARY SCAN COMPATIBLE
Description
• OFFERS THE EASE OF USE AND FAST SYSTEM
SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY
OF FIELD PROGRAMMABLE GATE ARRAYS
— Complete Programmable Device Can Combine Glue
Logic and Structured Designs
— Five Dedicated Clock Input Pins
— Synchronous and Asynchronous Clocks
— Programmable Output Slew Rate Control to Minimize Switching Noise
— Flexible Pin Placement
— Optimized Global Routing Pool Provides Global
Interconnectivity
The ispLSI 3256E is a High Density Programmable Logic
Device containing 512 Registers, 256 Universal I/O pins,
five Dedicated Clock Input Pins, 16 Output Routing Pools
(ORP) and a Global Routing Pool (GRP) which allows
complete inter-connectivity between all of these elements. The ispLSI 3256E features 5V in-system
programmability and in-system diagnostic capabilities.
The ispLSI 3256E offers non-volatile reprogrammability
of the logic, as well as the interconnect to provide truly
reconfigurable systems.
• ispDesignEXPERT™ – LOGIC COMPILER AND COMPLETE ISP DEVICE DESIGN SYSTEMS FROM HDL
SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING
— Superior Quality of Results
— Tightly Integrated with Leading CAE Vendor Tools
— Productivity Enhancing Timing Analyzer, Explore
Tools, Timing Simulator and ispANALYZER™
— PC and UNIX Platforms
The basic unit of logic on the ispLSI 3256E device is the
Twin Generic Logic Block (Twin GLB) labelled A0, A1...H3.
There are a total of 32 Twin GLBs in the ispLSI 3256E
device. Each Twin GLB has 24 inputs, a programmable
AND array and two OR/Exclusive-OR Arrays and eight
outputs which can be configured to be either combinatorial or registered. All Twin GLB inputs come from the
GRP.
Copyright © 2010 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
3256e_10
1
March 2010
Specifications ispLSI 3256E
Functional Block Diagram
I/O 231
I/O 229
I/O 227
I/O 225
I/O 223
I/O 221
I/O 219
I/O 217
I/O 215
I/O 213
I/O 211
I/O 209
I/O 207
I/O 205
I/O 203
I/O 201
I/O 199
I/O 197
I/O 195
I/O 193
I/O 230
I/O 228
I/O 226
I/O 224
I/O 222
I/O 220
I/O 218
I/O 216
I/O 214
I/O 212
I/O 210
I/O 208
I/O 206
I/O 204
I/O 202
I/O 200
I/O 198
I/O 196
I/O 194
I/O 192
TMS/MODE
I/O 239
I/O 237
I/O 235
I/O 233
I/O 238
I/O 236
I/O 234
I/O 232
TCLK/SCLK
I/O 247
I/O 245
I/O 243
I/O 241
I/O 246
I/O 244
I/O 242
I/O 240
Input Bus
Input Bus
TDI/SDI
ISP and
Boundary
Scan TAP
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Generic
Logic
Blocks
BSCAN/ispEN
I/O 255
I/O 253
I/O 251
I/O 249
I/O 254
I/O 252
I/O 250
I/O 248
GOE0
GOE1
Figure 1. ispLSI 3256E Functional Block Diagram
ORP
H2
H3
I/O 49
I/O 51
I/O 53
I/O 55
I/O 48
I/O 50
I/O 52
I/O 54
I/O 57
I/O 59
I/O 61
I/O 63
I/O 56
I/O 58
I/O 60
I/O 62
I/O 182
I/O 180
I/O 178
I/O 176
I/O 183
I/O 181
I/O 179
I/O 177
I/O 174
I/O 172
I/O 170
I/O 168
I/O 175
I/O 173
I/O 171
I/O 169
F0
I/O 166
I/O 164
I/O 162
I/O 160
I/O 167
I/O 165
I/O 163
I/O 161
B0
E3
I/O 158
I/O 156
I/O 154
I/O 152
I/O 159
I/O 157
I/O 155
I/O 153
B1
E2
I/O 150
I/O 148
I/O 146
I/O 144
I/O 151
I/O 149
I/O 147
I/O 145
B2
E1
I/O 142
I/O 140
I/O 138
I/O 136
I/O 143
I/O 141
I/O 139
I/O 137
B3
E0
I/O 134
I/O 132
I/O 130
I/O 128
I/O 135
I/O 133
I/O 131
I/O 129
A1
F2
A2
F1
A3
Input Bus
I/O 40
I/O 42
I/O 44
I/O 46
I/O 191
I/O 189
I/O 187
I/O 185
F3
Global Routing Pool
(GRP)
C1
C0
Megablock
C2
ORP
C3
D1
D0
D2
ORP
ORP
Input Bus
Input Bus
I/O 41
I/O 43
I/O 45
I/O 47
I/O 190
I/O 188
I/O 186
I/O 184
A0
ORP
I/O 32
I/O 34
I/O 36
I/O 38
TDO/SDO
ORP
I/O 33
I/O 35
I/O 37
I/O 39
TRST
ORP
I/O 24
I/O 26
I/O 28
I/O 30
G0
ORP
I/O 25
I/O 27
I/O 29
I/O 31
G1
ORP
I/O 16
I/O 18
I/O 20
I/O 22
G2
G3
ORP
I/O 17
I/O 19
I/O 21
I/O 23
H0
ORP
I/O 8
I/O 10
I/O 12
I/O 14
Input Bus
I/O 9
I/O 11
I/O 13
I/O 15
H1
ORP
ORP
I/O 0
I/O 2
I/O 4
I/O 6
Input Bus
I/O 1
I/O 3
I/O 5
I/O 7
ORP
ORP
D3
ORP
Input Bus
CLK 0
CLK 1
CLK 2
IOCLK 1
IOCLK 0
TOE
2
I/O 120
I/O 122
I/O 124
I/O 126
I/O 121
I/O 123
I/O 125
I/O 127
Y0
Y1
Y2
Y3
Y4
I/O 112
I/O 114
I/O 116
I/O 118
I/O 113
I/O 115
I/O 117
I/O 119
I/O 88
I/O 90
I/O 92
I/O 94
I/O 89
I/O 91
I/O 93
I/O 95
I/O 104
I/O 106
I/O 108
I/O 110
I/O 80
I/O 82
I/O 84
I/O 86
I/O 81
I/O 83
I/O 85
I/O 87
I/O 105
I/O 107
I/O 109
I/O 111
I/O 72
I/O 74
I/O 76
I/O 78
I/O 73
I/O 75
I/O 77
I/O 79
I/O 97 I/O 96
I/O 99 I/O 98
I/O 101 I/O 100
I/O 103 I/O 102
I/O 64
I/O 66
I/O 68
I/O 70
I/O 65
I/O 67
I/O 69
I/O 71
RESET
0139isp/3256E
Specifications ispLSI 3256E
Description (continued)
All local logic block outputs are brought back into the
GRP so they can be connected to the inputs of any other
logic block on the device. The device also has 256 I/O
cells, each of which is directly connected to an I/O pin.
Each I/O cell can be individually programmed to be a
combinatorial input, a registered input, a latched input, an
output or a bidirectional I/O pin with 3-state control. The
signal levels are TTL compatible voltages and the output
drivers can source 4 mA or sink 8 mA. Each output can
be programmed independently for fast or slow output
slew rate to minimize overall output switching noise.
Clocks in the ispLSI 3256E device are provided through
five dedicated clock pins. The five pins provide three
clocks to the Twin GLBs and two clocks to the I/O cells.
The table below lists key attributes of the device along
with the number of resources available.
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An additional feature of the ispLSI 3256E is its Boundary
Scan capability, which is composed of cells connected
between the on-chip system logic and the device’s input
and output pins. All I/O pins have associated boundary
scan registers, with 3-state I/O using three boundary
scan registers and inputs using one.
The 256 I/O Cells are grouped into 16 sets of 16 bits.
Pairs of these I/O groups are associated with a logic
Megablock through the use of the ORP. Each Megablock
is able to provide one Product Term Output Enable
(PTOE) signal which is globally distributed to all I/O cells.
That PTOE signal can be generated within any GLB in the
Megablock. Each I/O cell can select either a Global OE
or a PTOE.
The ispLSI 3256E supports all IEEE 1149.1 mandatory
instructions, which include BYPASS, EXTEST and
SAMPLE.
Key Attributes of the ispLSI 3256E
Attribute
Four Twin GLBs, 32 I/O Cells and two ORPs are connected together to make a logic Megablock. The
Megablock is defined by the resources that it shares. The
outputs of the four Twin GLBs are connected to a set of
32 I/O cells by the ORP. The ispLSI 3256E device
contains eight of these Megablocks.
The GRP has as its inputs the outputs from all of the Twin
GLBs and all of the inputs from the bidirectional I/O cells.
All of these signals are made available to the inputs of the
Twin GLBs. Delays through the GRP have been equalized to minimize timing skew and logic glitching.
Quantity
Twin GLBs
32
Registers
512
I/O Pins
256
Global Clocks
5
Global OE
2
Test OE
1
Table - 003/3256E
3
Specifications ispLSI 3256E
Absolute Maximum Ratings 1
Supply Voltage Vcc ........................................................................... -0.5 to +7.0V
Input Voltage Applied ........................................................................ -2.5 to VCC +1.0V
Off-State Output Voltage Applied ..................................................... -2.5 to VCC +1.0V
Storage Temperature ........................................................................ -65 to 150°C
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Case Temp. with Power Applied ...................................................... -55 to 125°C
Max. Junction Temp. (TJ) with Power Applied (304-Pin PQFP) ...... 150°C
Max. Junction Temp. (TJ) with Power Applied (320-Ball BGA) ........ 140°C
1. Stresses above those listed under the “Absolute Maximum Ratings” may cause permanent damage to the device. Functional
operation of the device at these or at any other conditions above those indicated in the operational sections of this specification
is not implied (while programming, follow the programming specifications).
DC Recommended Operating Condition
PARAMETER
SYMBOL
TA
VCC
VIL
VIH
Ambient Temperature
Supply Voltage
MIN.
MAX.
UNITS
0
70
°C
4.75
5.25
V
V
Input Low Voltage
0
0.8
Input High Voltage
2.0
VCC +1
V
Table 2-0005/3256E
Capacitance (TA=25°C,f=1.0 MHz)
TYPICAL
UNITS
I/O Capacitance
10
pf
VCC = 5.0V, VI/O = 2.0V
Clock Capacitance
15
pf
VCC = 5.0V, VY = 2.0V
SYMBOL
C1
C2
PARAMETER
TEST CONDITIONS
Table 2-0006/3256E
Data Retention Specifications
PARAMETER
MINIMUM
MAXIMUM
20
–
Years
10000
–
Cycles
Data Retention
ispLSI Erase/Reprogram Cycles
UNITS
Table 2-0008/3256E
4
Specifications ispLSI 3256E
Switching Test Conditions
Input Pulse Levels
Figure 2. Test Load
GND to 3.0V
Input Rise and Fall Time
≤ 3ns 10% to 90%
Input Timing Reference Levels
1.5V
Output Timing Reference Levels
1.5V
Output Load
3-state levels are measured 0.5V from
steady-state active level.
+ 5V
R1
See Figure 2
Device
Output
Test
Point
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Table 2-0003/3256E
R2
CL*
Output Load conditions (See Figure 2)
*CL includes Test Fixture and Probe Capacitance.
TEST CONDITION
A
B
C
R1
R2
CL
470Ω
390Ω
35pF
0213A
Active High
∞
390Ω
35pF
Active Low
470Ω
390Ω
35pF
Active High to Z
at VOH -0.5V
∞
390Ω
5pF
Active Low to Z
at VOL +0.5V
470Ω
390Ω
5pF
Table 2 - 0004A
DC Electrical Characteristics
Over Recommended Operating Conditions
SYMBOL
CONDITION
PARAMETER
3
MIN.
TYP.
MAX. UNITS
VOL
VOH
IIL
IIH
IIL-isp
IIL-PU
IOS1
Output Low Voltage
IOL= 8 mA
–
–
Output High Voltage
IOH = -4 mA
2.4
–
–
V
Input or I/O Low Leakage Current
0V ≤ VIN ≤ VIL (Max.)
–
–
-10
μA
Input or I/O High Leakage Current
3.5V ≤ VIN ≤ VCC
–
–
10
μA
Bscan/ispEN Input Low Leakage Current
0V ≤ VIN ≤ VIL
–
–
-150
μA
I/O Active Pull-Up Current
0V ≤ VIN ≤ VIL
–
–
-150
μA
Output Short Circuit Current
VCC = 5V, VOUT = 0.5V
–
–
-200
mA
ICC2,4
Operating Power Supply Current
VIL = 0.0V, VIH = 3.0V
fTOGGLE = 1 MHz
–
300
–
mA
0.4
V
Table 2 - 0007isp/3256E
1. One output at a time for a maximum duration of one second. VOUT = 0.5V was selected to avoid test problems
by tester ground degradation. Characterized but not 100% tested.
2. Measured using sixteen 16-bit counters.
3. Typical values are at VCC = 5V and TA = 25°C.
4. Maximum ICC varies widely with specific device configuration and operating frequency. Refer to the Power Consumption
section of this datasheet and Thermal Management section of the Lattice Semiconductor Data Book or CD-ROM to estimate
maximum ICC.
5
Specifications ispLSI 3256E
External Switching Characteristics1, 2, 3
Over Recommended Operating Conditions
PARAMETER
TEST5
COND.
#2
-100
DESCRIPTION1
-70
MIN. MAX. MIN. MAX.
UNITS
tpd1
A
1 Data Prop. Delay, 4PT Bypass, ORP Bypass
—
10.0
—
15.0
ns
tpd2
A
2 Data Propagation Delay
—
13.0
—
18.0
ns
fmax
A
3 Clock Frequency with Internal Feedback
100
—
70.0
—
MHz
fmax (Ext.)
—
4 Clock Freq. with Ext. Feedback,1/(tsu2 + tco1)
77.0
—
50.0
—
MHz
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3
fmax (Tog.)
—
5 Clock Frequency, Max Toggle
100
—
83.0
—
MHz
tsu1
—
6 GLB Reg. Setup Time before Clock, 4PT bypass
5.5
—
9.0
—
ns
tco1
A
7 GLB Reg. Clock to Output Delay, ORP bypass
—
6.5
—
9.0
ns
th1
—
8 GLB Reg. Hold Time after Clock, 4PT bypass
0.0
—
0.0
—
ns
tsu2
—
9 GLB Reg. Setup Time before Clock
6.5
—
11.0
—
ns
tco2
—
10 GLB Reg. Clock to Output Delay
—
7.0
—
10.0
ns
th2
—
11 GLB Reg. Hold Time after Clock
0.0
—
0.0
—
ns
tr1
A
12 Ext. Reset Pin to Output Delay
—
13.5
—
15.0
ns
trw1
—
13 Ext. Reset Pulse Duration
6.5
—
12.0
—
ns
tptoeen
B
14 Input to Output Enable
—
16.0
—
19.0
ns
tptoedis
C
15 Input to Output Disable
—
16.0
—
19.0
ns
tgoeen
B
16 Global OE Output Enable
—
9.0
—
12.0
ns
tgoedis
C
17 Global OE Output Disable
—
9.0
—
12.0
ns
ttoeen
—
18 Test OE Output Enable
—
12.0
—
15.0
ns
4
ttoedis
—
19 Test OE Output Disable
—
12.0
—
15.0
ns
twh
—
20 Ext. Sync. Clock Pulse Duration, High
5.0
—
6.0
—
ns
twl
—
21 Ext. Sync. Clock Pulse Duration, Low
5.0
—
6.0
—
ns
tsu3
—
22 I/O Reg. Setup Time before Ext. Sync. Clock (Y3, Y4)
4.5
—
5.0
—
ns
th3
—
23 I/O Reg. Hold Time after Ext. Sync. Clock (Y3, Y4)
0.0
—
0.0
—
ns
1.
2.
3.
4.
5.
Unless noted otherwise, all parameters use 20 PTXOR path and ORP.
Refer to Timing Model in this data sheet for further details.
Standard 16-bit counter using GRP feedback.
fmax (Toggle) may be less than 1/(twh + twl). This is to allow for a clock duty cycle of other than 50%.
Reference Switching Test Conditions section.
Timing Ext.3256E.eps
6
Specifications ispLSI 3256E
Internal Timing Parameters1
Over Recommended Operating Conditions
PARAMETER
#2
-100
DESCRIPTION
MIN.
-70
MAX.
MIN.
MAX.
UNITS
Inputs
24 I/O Register Bypass
—
2.4
—
4.0
ns
25 I/O Latch Delay
—
10.3
—
14.0
ns
26 I/O Register Setup Time before Clock
4.8
—
5.8
—
ns
27 I/O Register Hold Time after Clock
-1.6
—
-2.5
—
ns
28 I/O Register Clock to Out Delay
—
5.8
—
8.5
ns
29 I/O Register Reset to Out Delay
—
5.8
—
7.5
ns
30 GRP Delay
—
2.3
—
3.2
ns
31 4 Product Term Bypass Path Delay (Comb.)
—
3.2
—
3.6
ns
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tiobp
tiolat
tiosu
tioh
tioco
tior
GRP
tgrp
GLB
t4ptbp
t4ptbr
t1ptxor
t20ptxor
txoradj
tgbp
tgsu
tgh
tgco
tgro
tptre
tptoe
tptck
ORP
torp
torpbp
32 4 Product Term Bypass Path Delay (Reg.)
—
3.1
—
4.8
ns
33 1 Product Term/XOR Path Delay
—
4.0
—
5.1
ns
34 20 Product Term/XOR Path Delay
—
4.1
—
5.2
ns
35 XOR Adjacent Path Delay3
—
4.3
—
5.7
ns
36 GLB Register Bypass Delay
—
1.5
—
1.6
ns
37 GLB Register Setup Time before Clock
0.3
—
1.2
—
ns
38 GLB Register Hold Time after Clock
5.0
—
7.6
—
ns
39 GLB Register Clock to Output Delay
—
1.6
—
3.0
ns
40 GLB Register Reset to Output Delay
—
5.2
—
5.2
ns
41 GLB Product Term Reset to Register Delay
—
4.0
—
4.4
ns
42 GLB Product Term Output Enable to I/O Cell Delay
—
6.5
—
6.9
ns
43 GLB Product Term Clock Delay
3.0
3.6
3.4
4.2
ns
44 ORP Delay
—
1.2
—
1.9
ns
45 ORP Bypass Delay
—
0.7
—
0.9
ns
1. Internal Timing Parameters are not tested and are for reference only.
2. Refer to Timing Model in this data sheet for further details.
3. The XOR adjacent path can only be used by hard macros.
Timing Int.3256E.eps
7
Specifications ispLSI 3256E
Internal Timing Parameters1
Over Recommended Operating Conditions
PARAMETER
#2
-100
DESCRIPTION
-70
MIN.
MAX.
MIN.
MAX.
—
2.6
—
3.3
UNITS
Outputs
46 Output Buffer Delay
tobs
47 Output Buffer Delay, Slew Limited Adder
—
17.6
—
18.3
ns
toen
48 I/O Cell OE to Output Enabled
—
5.5
—
5.7
ns
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tob
todis
49 I/O Cell OE to Output Disabled
—
5.5
—
5.7
ns
ns
Clocks
tgy0/1/2
50 Clock Delay, Y0 or Y1 or Y2 to Global GLB Clk Line
1.6
1.6
1.8
1.8
ns
tioy3/4
51 Clock Delay, Y3 or Y4 to I/O Cell Global Clock Line
0.3
1.6
0.8
2.5
ns
tgr
52 Global Reset to GLB and I/O Registers
—
4.5
—
4.6
ns
tgoe
53 Global OE Pad Buffer
—
5.9
—
7.5
ns
ttoe
54 Test OE Pad Buffer
—
6.1
—
8.9
ns
Global Reset
1. Internal Timing Parameters are not tested and are for reference only.
2. Refer to Timing Model in this data sheet for further details.
Timing Int.2.3256E.eps
8
Specifications ispLSI 3256E
ispLSI 3256E Timing Model
I/O Cell
GRP
GLB
ORP
I/O Cell
Feedback
#31
I/O Reg Bypass
I/O Pin
(Input)
#24
GRP
#30
Input
D Register Q
RST
#25 - 29
4 PT Bypass
GLB Reg Bypass
ORP Bypass
#32
#36
#45
20 PT
XOR Delays
GLB Reg
Delay
ORP
Delay
D
Q
#44
I/O Pin
(Output)
A
D LL
IS
C DE
O
N VIC
TI
N ES
U
ED
#33 - 35
#46, 47
#52
RST
#52
Reset
Y3,4
#37 - 40
#51
Control RE
PTs
OE
#41 - 43 CK
#50
Y0,1,2
#53
GOE0,1
#54
TOE
0902/3256E
Derivations of tsu, th and tco from the Product Term Clock 1
tsu
=
=
=
1.4 ns =
Logic + Reg su - Clock (min)
(tiobp + tgrp + t20ptxor) + (tgsu) - (tiobp + tgrp + tptck(min))
(#24+ #30+ #34) + (#37) - (#24+ #30+ #43)
(2.4 + 2.3 + 4.1) + (0.3) - (2.4 + 2.3 + 3.0)
th
=
=
=
4.5 ns =
Clock (max) + Reg h - Logic
(tiobp + tgrp + tptck(max)) + (tgh) - (tiobp + tgrp + t20ptxor)
(#24+ #30+ #43) + (#38) - (#24+ #30+ #34)
(2.4 + 2.3 + 3.6) + (5.0) - (2.4 + 2.3 + 4.1)
tco
=
=
=
13.7 ns =
Clock (max) + Reg co + Output
(tiobp + tgrp + tptck(max)) + (tgco) + (torp + tob)
(#24 + #30 + #43) + (#39) + (#44 + #46)
(2.4 + 2.3 + 3.6) + (1.6) + (1.2 + 2.6)
Table 2- 0042-3256E
Note: Calculations are based upon timing specifications for the ispLSI 3256E-100L.
9
#48, 49
Specifications ispLSI 3256E
Power Consumption
Power consumption in the ispLSI 3256E device depends
on two primary factors: the speed at which the device is
operating and the number of product terms used.
Figure 3 shows the relationship between power and
operating speed.
Figure 3. Typical Device Power Consumption vs fmax
ispLSI 3256E
A
D LL
IS
C DE
O
N VIC
TI
N ES
U
ED
600
ICC (mA)
500
400
300
200
0
20
40
60
80
100
fmax (MHz)
Notes: Configuration of 16 16-bit Counters
Typical Current at 5V, 25° C
ICC can be estimated for the ispLSI 3256E using the following equation:
ICC = 60 + (# of PTs * 0.48) + (# of nets * Max. freq * 0.0106) where:
# of PTs = Number of Product Terms used in design
# of nets = Number of Signals used in device
Max. freq = Highest Clock Frequency to the device
The ICC estimate is based on typical conditions (VCC = 5.0V, room temperature) and an assumption of two
GLB loads on average exists. These values are for estimates only. Since the value of ICC is sensitive to
operating conditions and the program in the device, the actual ICC should be verified.
0127/3256E
10
Specifications ispLSI 3256E
Pin Description
Pin Name
Description
Input/Output pins – These are the general purpose I/O pins used by the logic array.
GOE0, GOE1
Global Output Enable input pins.
TOE
Test Output Enable pin – This pin tristates all I/O pins when a logic low is driven.
RESET
Active Low (0) Reset pin – Resets all of the GLB and I/O registers in the device.
Y0, Y1, Y2
Dedicated Clock inputs. These clock inputs are connected to one of the clock inputs of all the GLBs on
the device.
Y3, Y4
Dedicated Clock inputs. These clock inputs are connected to one of the clock inputs of all the I/O cells
on the device.
A
D LL
IS
C DE
O
N VIC
TI
N ES
U
ED
I/O
BSCAN/ispEN
Input – Dedicated in-system programming enable input pin. When this pin is high, the BSCAN TAP
controller pins TMS, TDI, TDO and TCK are enabled. When this pin is brought low, the ISP State
Machine control pins MODE, SDI, SDO and SCLK are enabled. High-to-low transition of this pin will put
the device in the programming mode and put all I/O pins in the high-Z state.
TDI/SDI
Input – This pin performs two functions. It is the Test Data input pin when ispEN is logic high. When
ispEN is logic low, it functions as an input pin to load programming data into the device. SDI is also
used as one of the two control pins for the ISP State Machine.
TCK/SCLK
Input – This pin performs two functions. It is the Test Clock input pin when ispEN is logic high. When
ispEN is logic low, it functions as a clock pin for the Serial Shift Register.
TMS/MODE
Input – This pin performs two functions. It is the Test Mode Select input pin when ispEN is logic high.
When ispEN is logic low, it functions as a pin to control the operation of the ISP State Machine.
TRST/NC1
Input – Test Reset, active low to reset the Boundary Scan State Machine.
TDO/SDO
Output – This pin performs two functions. When ispEN is logic low, it functions as the pin to read the
ISP data. When ispEN is high, it functions as Test Data Out.
GND
Ground (GND)
VCC
Vcc
NC
1
No Connect.
1. NC pins are not to be connected to any active signals, VCC or GND.
Pin Locations
Signal
304-Pin PQFP
320-Ball BGA
GOE0, GOE1
195, 185
AD11, AC14
TOE
215
AC6
RESET
53
A17
Y0, Y1, Y2, Y3, Y4 43, 33, 205, 175, 165
A14, B11, AD8, AB16, AA18
ispEN/BSCAN
63
B19
SDI/TDI
23
C9
SCLK/TCK
73
D20
MODE/TMS
13
D7
TRST/NC1
225
AA5
SDO/TDO
155
AB21
GND
9, 19, 39, 49, 69, 85, 95, 115, 125, 145, 161, 171,
191, 201, 221, 237, 247, 267, 277, 297
D6, C8, B13, A16, D19, F21, H22, N23, T24, W21,
AA19, AB17, AC12, AD9, AA6, W4, U3, M2, J1, F4
VCC
1, 29, 59, 77, 105, 135, 153, 181, 211, 229, 257,
287, 304
D4, B10, B18, D21, K23, V23, AA21, AC15, AC7,
AA4, R2, G2, C3
NC1
A1, A2, A23, A24, B1, B2, B23, B24, AC1, AC2,
AC23, AC24, AD1, AD2, AD23, AD24
1. NC pins are not to be connected to any active signals, VCC or GND.
11
Specifications ispLSI 3256E
I/O Locations
Signal
PQFP
BGA
Signal
PQFP BGA
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
I/O 16
I/O 17
I/O 18
I/O 19
I/O 20
I/O 21
I/O 22
I/O 23
I/O 24
I/O 25
I/O 26
I/O 27
I/O 28
I/O 29
I/O 30
I/O 31
I/O 32
I/O 33
I/O 34
I/O 35
I/O 36
I/O 37
I/O 38
I/O 39
I/O 40
I/O 41
I/O 42
I/O 43
I/O 44
I/O 45
I/O 46
I/O 47
I/O 48
I/O 49
I/O 50
I/O 51
I/O 52
40
41
42
44
45
46
47
48
50
51
52
54
55
56
57
58
60
61
62
64
65
66
67
68
70
71
72
74
75
76
78
79
80
81
82
83
84
86
87
88
89
90
91
92
93
94
96
97
98
99
100
101
102
C13
D13
A13
B14
C14
D14
A15
B15
C15
D15
B16
C16
B17
D16
A18
C17
A19
D17
C18
A20
D18
C19
B20
A21
C20
B21
A22
C21
B22
C22
C23
D22
C24
E21
D23
E22
D24
E23
F22
E24
G21
F23
G22
F24
H21
G23
G24
J21
H23
J22
H24
J23
K21
I/O 53
I/O 54
I/O 55
I/O 56
I/O 57
I/O 58
I/O 59
I/O 60
I/O 61
I/O 62
I/O 63
I/O 64
I/O 65
I/O 66
I/O 67
I/O 68
I/O 69
I/O 70
I/O 71
I/O 72
I/O 73
I/O 74
I/O 75
I/O 76
I/O 77
I/O 78
I/O 79
I/O 80
I/O 81
I/O 82
I/O 83
I/O 84
I/O 85
I/O 86
I/O 87
I/O 88
I/O 89
I/O 90
I/O 91
I/O 92
I/O 93
I/O 94
I/O 95
I/O 96
I/O 97
I/O 98
I/O 99
I/O 100
I/O 101
I/O 102
I/O 103
I/O 104
I/O 105
103
104
106
107
108
109
110
111
112
113
114
116
117
118
119
120
121
122
123
124
126
127
128
129
130
131
132
133
134
136
137
138
139
140
141
142
143
144
146
147
148
149
150
151
152
154
156
157
158
159
160
162
163
Signal
I/O 106
I/O 107
I/O 108
I/O 109
I/O 110
I/O 111
I/O 112
I/O 113
I/O 114
I/O 115
I/O 116
I/O 117
I/O 118
I/O 119
I/O 120
I/O 121
I/O 122
I/O 123
I/O 124
I/O 125
I/O 126
I/O 127
I/O 128
I/O 129
I/O 130
I/O 131
I/O 132
I/O 133
I/O 134
I/O 135
I/O 136
I/O 137
I/O 138
I/O 139
I/O 140
I/O 141
I/O 142
I/O 143
I/O 144
I/O 145
I/O 146
I/O 147
I/O 148
I/O 149
I/O 150
I/O 151
I/O 152
I/O 153
I/O 154
I/O 155
I/O 156
I/O 157
I/O 158
PQFP BGA
164
166
167
168
169
170
172
173
174
176
177
178
179
180
182
183
184
186
187
188
189
190
192
193
194
196
197
198
199
200
202
203
204
206
207
208
209
210
212
213
214
216
217
218
219
220
222
223
224
226
227
228
230
AD20
AC19
AB18
AD19
AA17
AC18
AD18
AA16
AC17
AD17
AC16
AA15
AB15
AD16
AD15
AA14
AB14
AD14
AD13
AA13
AB13
AC13
AB12
AA12
AD12
AC11
AB11
AA11
AD10
AC10
AB10
AA10
AC9
AB9
AC8
AA9
AD7
AB8
AD6
AA8
AB7
AD5
AA7
AB6
AC5
AD4
AB5
AC4
AD3
AB4
AC3
AB3
AB2
Signal PQFP
I/O 159
I/O 160
I/O 161
I/O 162
I/O 163
I/O 164
I/O 165
I/O 166
I/O 167
I/O 168
I/O 169
I/O 170
I/O 171
I/O 172
I/O 173
I/O 174
I/O 175
I/O 176
I/O 177
I/O 178
I/O 179
I/O 180
I/O 181
I/O 182
I/O 183
I/O 184
I/O 185
I/O 186
I/O 187
I/O 188
I/O 189
I/O 190
I/O 191
I/O 192
I/O 193
I/O 194
I/O 195
I/O 196
I/O 197
I/O 198
I/O 199
I/O 200
I/O 201
I/O 202
I/O 203
I/O 204
I/O 205
I/O 206
I/O 207
I/O 208
I/O 209
I/O 210
I/O 211
231
232
233
234
235
236
238
239
240
241
242
243
244
245
246
248
249
250
251
252
253
254
255
256
258
259
260
261
262
263
264
265
266
268
269
270
271
272
273
274
275
276
278
279
280
281
282
283
284
285
286
288
289
BGA
AA3
AB1
Y4
AA2
Y3
AA1
Y2
W3
Y1
V4
W2
V3
W1
U4
V2
V1
T4
U2
T3
U1
T2
R4
R3
T1
R1
P4
P3
P2
P1
N1
N4
N3
N2
M3
M4
M1
L1
L2
L3
L4
K1
K2
K3
K4
J2
H1
J3
H2
J4
G1
H3
F1
H4
Signal PQFP
I/O 212
I/O 213
I/O 214
I/O 215
I/O 216
I/O 217
I/O 218
I/O 219
I/O 220
I/O 221
I/O 222
I/O 223
I/O 224
I/O 225
I/O 226
I/O 227
I/O 228
I/O 229
I/O 230
I/O 231
I/O 232
I/O 233
I/O 234
I/O 235
I/O 236
I/O 237
I/O 238
I/O 239
I/O 240
I/O 241
I/O 242
I/O 243
I/O 244
I/O 245
I/O 246
I/O 247
I/O 248
I/O 249
I/O 250
I/O 251
I/O 252
I/O 253
I/O 254
I/O 255
290
291
292
293
294
295
296
298
299
300
301
302
303
2
3
4
5
6
7
8
10
11
12
14
15
16
17
18
20
21
22
24
25
26
27
28
30
31
32
34
35
36
37
38
BGA
A
D LL
IS
C DE
O
N VIC
TI
N ES
U
ED
K22
J24
K24
L21
L22
L23
L24
M24
M21
M22
M23
N22
N21
N24
P24
P23
P22
P21
R24
R23
R22
R21
T23
U24
T22
U23
T21
V24
U22
W24
U21
V22
W23
Y24
V21
W22
Y23
AA24
Y22
AA23
AB24
Y21
AA22
AB23
AB22
AC22
AD22
AA20
AC21
AB20
AD21
AC20
AB19
12
G3
F2
E1
G4
F3
E2
D1
E3
D2
C1
E4
D3
C2
B3
C4
A3
D5
B4
C5
A4
B5
C6
A5
B6
C7
A6
D8
B7
A7
D9
B8
A8
B9
D10
C10
A9
A10
D11
C11
A11
A12
D12
C12
B12
Specifications ispLSI 3256E
Pin Configuration
304
303
302
301
300
299
298
297
296
295
294
293
292
291
290
289
288
287
286
285
284
283
282
281
280
279
278
277
276
275
274
273
272
271
270
269
268
267
266
265
264
263
262
261
260
259
258
257
256
255
254
253
252
251
250
249
248
247
246
245
244
243
242
241
240
239
238
237
236
235
234
233
232
231
230
229
VCC
I/O 224
I/O 223
I/O 222
I/O 221
I/O 220
I/O 219
GND
I/O 218
I/O 217
I/O 216
I/O 215
I/O 214
I/O 213
I/O 212
I/O 211
I/O 210
VCC
I/O 209
I/O 208
I/O 207
I/O 206
I/O 205
I/O 204
I/O 203
I/O 202
I/O 201
GND
I/O 200
I/O 199
I/O 198
I/O 197
I/O 196
I/O 195
I/O 194
I/O 193
I/O 192
GND
I/O 191
I/O 190
I/O 189
I/O 188
I/O 187
I/O 186
I/O 185
I/O 184
I/O 183
VCC
I/O 182
I/O 181
I/O 180
I/O 179
I/O 178
I/O 177
I/O 176
I/O 175
I/O 174
GND
I/O 173
I/O 172
I/O 171
I/O 170
I/O 169
I/O 168
I/O 167
I/O 166
I/O 165
GND
I/O 164
I/O 163
I/O 162
I/O 161
I/O 160
I/O 159
I/O 158
VCC
ispLSI 3256E 304-Pin PQFP Pinout Diagram
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
228
227
226
225
224
223
222
221
220
219
218
217
216
215
214
213
212
211
210
209
208
207
206
205
204
203
202
201
200
199
198
197
196
195
194
193
192
191
190
189
188
187
186
185
184
183
182
181
180
179
178
177
176
175
174
173
172
171
170
169
168
167
166
165
164
163
162
161
160
159
158
157
156
155
154
153
A
D LL
IS
C DE
O
N VIC
TI
N ES
U
ED
VCC
I/O 225
I/O 226
I/O 227
I/O 228
I/O 229
I/O 230
I/O 231
GND
I/O 232
I/O 233
I/O 234
MODE/TMS
I/O 235
I/O 236
I/O 237
I/O 238
I/O 239
GND
I/O 240
I/O 241
I/O 242
SDI/TDI
I/O 243
I/O 244
I/O 245
I/O 246
I/O 247
VCC
I/O 248
I/O 249
I/O 250
Y1
I/O 251
I/O 252
I/O 253
I/O 254
I/O 255
GND
I/O 0
I/O 1
I/O 2
Y0
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
GND
I/O 8
I/O 9
I/O 10
RESET
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
VCC
I/O 16
I/O 17
I/O 18
ispEN/BSCAN
I/O 19
I/O 20
I/O 21
I/O 22
I/O 23
GND
I/O 24
I/O 25
I/O 26
SCLK/TCK
I/O 27
I/O 28
I/O 29
ispLSI 3256E
VCC
I/O 30
I/O 31
I/O 32
I/O 33
I/O 34
I/O 35
I/O 36
GND
I/O 37
I/O 38
I/O 39
I/O 40
I/O 41
I/O 42
I/O 43
I/O 44
I/O 45
GND
I/O 46
I/O 47
I/O 48
I/O 49
I/O 50
I/O 51
I/O 52
I/O 53
I/O 54
VCC
I/O 55
I/O 56
I/O 57
I/O 58
I/O 59
I/O 60
I/O 61
I/O 62
I/O 63
GND
I/O 64
I/O 65
I/O 66
I/O 67
I/O 68
I/O 69
I/O 70
I/O 71
I/O 72
GND
I/O 73
I/O 74
I/O 75
I/O 76
I/O 77
I/O 78
I/O 79
I/O 80
I/O 81
VCC
I/O 82
I/O 83
I/O 84
I/O 85
I/O 86
I/O 87
I/O 88
I/O 89
I/O 90
GND
I/O 91
I/O 92
I/O 93
I/O 94
I/O 95
I/O 96
I/O 97
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
Top View
1. NC pins are not to be connected to any active signals, VCC or GND.
13
I/O 157
I/O 156
I/O 155
TRST/NC1
I/O 154
I/O 153
I/O 152
GND
I/O 151
I/O 150
I/O 149
I/O 148
I/O 147
TOE
I/O 146
I/O 145
I/O 144
VCC
I/O 143
I/O 142
I/O 141
I/O 140
I/O 139
Y2
I/O 138
I/O 137
I/O 136
GND
I/O 135
I/O 134
I/O 133
I/O 132
I/O 131
GOE0
I/O 130
I/O 129
I/O 128
GND
I/O 127
I/O 126
I/O 125
I/O 124
I/O 123
GOE1
I/O 122
I/O 121
I/O 120
VCC
I/O 119
I/O 118
I/O 117
I/O 116
I/O 115
Y3
I/O 114
I/O 113
I/O 112
GND
I/O 111
I/O 110
I/O 109
I/O 108
I/O 107
Y4
I/O 106
I/O 105
I/O 104
GND
I/O 103
I/O 102
I/O 101
I/O 100
I/O 99
SDO/TDO
I/O 98
VCC
Specifications ispLSI 3256E
Signal Configuration
ispLSI 3256E 320-Ball BGA Signal Diagram
24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
A
NC1
NC1
I/O
26
I/O
23
I/O
19
I/O
16
I/O
14
RESET
GND
I/O
6
Y0
I/O
2
I/O
252
I/O
251
I/O
248
I/O
247
I/O
243
I/O
240
I/O
237
I/O
234
I/O
231
I/O
227
NC1
NC1
A
B
NC1
NC1
I/O
28
I/O
25
I/O
22
ispEN/
BSCAN
VCC
I/O
12
I/O
10
I/O
7
I/O
3
GND
I/O
255
Y1
VCC
I/O
244
I/O
242
I/O
239
I/O
235
I/O
232
I/O
229
I/O
225
NC1
NC1
B
C
I/O
32
I/O
30
I/O
29
I/O
27
I/O
24
I/O
21
I/O
18
I/O
15
I/O
11
I/O
8
I/O
4
I/O
0
I/O
254
I/O
250
I/O
246
SDI/
I/O
GND
TDI
236
I/O
233
I/O
230
I/O
VCC
226
I/O
224
I/O
221
C
D
I/O
36
I/O
34
I/O
31
VCC
I/O
20
I/O
17
I/O
13
I/O
9
I/O
5
I/O
1
I/O
253
I/O
249
I/O
245
I/O
241
I/O
I/O
GND 228 VCC 223
I/O
220
I/O
218
D
E
I/O
39
I/O
37
I/O
35
I/O
33
I/O
222
I/O
219
I/O
217
I/O
214
E
F
I/O
43
I/O
41
I/O
38
GND
GND
I/O
216
I/O
213
I/O
210
F
G
I/O
46
I/O
45
I/O
42
I/O
40
I/O
215
I/O
212
I/O
VCC 208
G
I/O
209
I/O
206
I/O
204
H
I/O
238
A
D LL
IS
C DE
O
N VIC
TI
N ES
U
ED
SCLK/
TCK
GND
MODE/
TMS
H
I/O
50
I/O
48
GND
I/O
44
I/O
211
J
I/O
54
I/O
51
I/O
49
I/O
47
I/O
207
I/O
205
I/O
203 GND
J
K
I/O
55
VCC
I/O
53
I/O
52
I/O
202
I/O
201
I/O
200
I/O
199
K
L
I/O
59
I/O
58
I/O
57
I/O
56
I/O
198
I/O
197
I/O
196
I/O
195
L
M
I/O
60
I/O
63
I/O
62
I/O
61
ispLSI 3256E
I/O
193
I/O
I/O
192 GND 194
M
N
I/O
66
GND
I/O
64
I/O
65
Bottom View
I/O
189
I/O
190
I/O
191
I/O
188
N
P
I/O
67
I/O
68
I/O
69
I/O
70
I/O
184
I/O
185
I/O
186
I/O
187
P
R
I/O
71
I/O
72
I/O
73
I/O
74
I/O
180
I/O
181
VCC
I/O
183
R
T
GND
I/O
75
I/O
77
I/O
79
I/O
175
I/O
177
I/O
179
I/O
182
T
U
I/O
76
I/O
78
I/O
81
I/O
83
I/O
I/O
172 GND 176
I/O
178
U
V
I/O
80
VCC
I/O
84
I/O
87
I/O
168
W
I/O
82
I/O
85
I/O
88
GND
Y
I/O
86
I/O
89
I/O
91
I/O
94
AA
I/O
90
I/O
92
I/O
95
AB
I/O
93
I/O
96
I/O SDO/ I/O
97 TDO 102
I/O
101
I/O
103
AC
NC1
NC1
I/O
98
AD
NC1
NC1
I/O
99
I/O
VCC 100 GND
I/O
170
I/O
173
I/O
174
V
I/O
GND 166
I/O
169
I/O
171
W
I/O
161
I/O
163
I/O
165
I/O
167
Y
I/O
VCC
159
I/O
162
I/O
164
AA
I/O
110
I/O
113
I/O
117
I/O
121
I/O
125
I/O
129
I/O
133
I/O
137
I/O
141
I/O
145
I/O
GND
148
I/O
105
I/O
GND
108
Y3
I/O
118
I/O
122
I/O
126
I/O
128
I/O
132
I/O
136
I/O
139
I/O
143
I/O
146
I/O
152
I/O
155
I/O
157
I/O
158
I/O
160
AB
I/O
104
I/O
107
I/O
111
I/O
114
I/O
I/O
GOE I/O
116 VCC
1
127 GND 131
I/O
135
I/O
138
I/O
I/O
140 VCC TOE 150
I/O
153
I/O
156
NC1
NC1
AC
I/O
106
I/O
109
I/O
112
I/O
115
I/O
119
AD
Y4
I/O
120
I/O
123
I/O
124
I/O GOE I/O
130
0
134 GND
24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
1. NC pins are not to be connected to any active signals, VCC or GND.
Note: Ball A1 indicator dot on top side of package.
14
9
I/O
149
TRST/
NC1
Y2
I/O
142
I/O
144
I/O
147
I/O
151
I/O
154
NC1
NC1
8
7
6
5
4
3
2
1
Specifications ispLSI 3256E
Part Number Description
ispLSI
3256E – XXX X
XXXX
X
Device Family
Grade
Blank = Commercial
Device Number
Package
QA = PQFP (Without Heat Sink)
B320 = BGA
A
D LL
IS
C DE
O
N VIC
TI
N ES
U
ED
Speed
100 = 100 MHz fmax
70 = 70 MHz fmax
Power
L = Low
Ordering Information
COMMERCIAL
FAMILY
ispLSI
fmax (MHz)
tpd (ns)
ORDERING NUMBER
ispLSI
3256E-100LQA1
100
10
100
10
ispLSI 3256E-100LB320
70
15
3256E-70LQA1
70
15
ispLSI
ispLSI 3256E-70LB320
1. Discontinued per PCN #12A-09.
Revision History
Date
Version
—
—
Previous Lattice releases.
Change Summary
March 2007
09
Updated Part Number Description and Ordering Information.
March 2010
10
Updated Part Number Description and Ordering Information.
15
PACKAGE
304-Pin PQFP (Without Heat Sink)
320-Ball BGA
304-Pin PQFP (Without Heat Sink)
320-Ball BGA