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FUJITSU MICROELECTRONICS
CONTROLLER MANUAL
CM44-10122-4E
F2MC-16LX
16-BIT MICROCONTROLLER
MB90390 Series
HARDWARE MANUAL
F2MC-16LX
16-BIT MICROCONTROLLER
MB90390 Series
HARDWARE MANUAL
The information for microcontroller supports is shown in the following homepage.
Be sure to refer to the "Check Sheet" for the latest cautions on development.
"Check Sheet" is seen at the following support page
"Check Sheet" lists the minimal requirement items to be checked to prevent problems beforehand in system development.
http://edevice.fujitsu.com/micom/en-support/
FUJITSU MICROELECTRONICS LIMITED
PREFACE
■ Objectives and intended reader
Thank you very much for your continued patronage of Fujitsu semiconductor products.
The MB90390 series has been developed as a general-purpose version of the F2MC-16LX series,
which is an original 16-bit single-chip microcontroller compatible with the Application Specific IC
(ASIC).
This manual explains the functions and operation of the MB90390 series for designers who actually
use the MB90390 series to design products. Please read this manual first.
Note: F2MC is the abbreviation of FUJITSU Flexible Microcontroller.
■ Trademark
The company names and brand names herein are the trademarks or registered trademarks of their
respective owners.
■ License
Purchase of Fujitsu I2C components conveys a license under the Philips I2C Patent Rights to use,
these components in an I2C system provided that the system conforms to the I2C Standard
Specification as defined by Philips.
■ Structure of this preliminary manual
CHAPTER 1 OVERVIEW
The MB90390 Series is a family member of the F2MC-16LX microcontrollers.
CHAPTER 2 CPU
This chapter explains the CPU.
CHAPTER 3 INTERRUPTS
This chapter explains the functions and operations of the interrupt and extended intelligent I/O
service (EI2OS) for MB90390 series.
CHAPTER 4 DELAYED INTERRUPT
This chapter explains the functions and operations of the delayed interrupt.
CHAPTER 5 CLOCKS
This chapter describes the clocks used by MB90390 series microcontrollers.
CHAPTER 6 CLOCK MODULATOR
This chapter provides an overview of the Clock Modulator and its features. It describes the
register structure and operation of the Clock Modulator.
CHAPTER 7 RESETS
This chapter describes resets for the MB90390 series microcontrollers.
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CHAPTER 8 LOW-POWER CONTROL CIRCUIT
This chapter explains the functions and operations of the low-power control circuits.
CHAPTER 9 MEMORY ACCESS MODES
This chapter explains the functions and operations of the memory access modes.
CHAPTER 10 I/O PORTS
This chapter explains the functions and operations of the I/O ports.
CHAPTER 11 TIME-BASE TIMER
This chapter explains the functions and operations of the time-base timer.
CHAPTER 12 WATCHDOG TIMER
This chapter explains the functions and operations of the watchdog timer.
CHAPTER 13 16-BIT I/O TIMER
This chapter explains the functions and operations of the 16-bit I/O timer.
CHAPTER 14 16-BIT RELOAD TIMER (WITH EVENT COUNT FUNCTION)
This chapter explains the functions and operations of the 16-bit reload timer (with the event
count function).
CHAPTER 15 WATCH TIMER
This chapter explains the functions and operations of the Watch Timer.
CHAPTER 16 8/16-BIT PPG
This chapter explains the 8/16-bit PPG and explains its functions.
CHAPTER 17 DTP/EXTERNAL INTERRUPTS
This chapter explains the functions and operations of the DTP/external interrupts.
CHAPTER 18 8/10-BIT A/D CONVERTER
This chapter describes the functions and operation of the 8/10-bit A/D converter.
CHAPTER 19 UART0, UART1
This chapter explains the UART0, UART1 functions and operations.
CHAPTER 20 UART2, UART3
This chapter explains the functions and operation of UART2, UART3.
CHAPTER 21 400 kHz I2C INTERFACE
This section describes the functions and operation of the fast I2C interface.
CHAPTER 22 SERIAL I/O
This chapter explains the functions and operations of the serial I/O.
CHAPTER 23 CAN CONTROLLER
This chapter explains the functions and operations of the CAN controller.
CHAPTER 24 STEPPING MOTOR CONTROLLER
This chapter explains the functions and operations of the stepping motor controller.
CHAPTER 25 SOUND GENERATOR
This chapter explains the functions and operations of the sound generator.
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CHAPTER 26 ADDRESS MATCH DETECTION FUNCTION
This chapter explains the address match detection function and operation.
CHAPTER 27 ROM MIRRORING MODULE
This chapter explains the ROM mirroring module.
CHAPTER 28 3M-BIT FLASH MEMORY
This chapter explains the functions and operation of the 3M-bit flash memory.
CHAPTER 29 EXAMPLES OF SERIAL PROGRAMMING CONNECTION
This chapter provides examples of F2MC-16LX MB90F394H(A) serial programming connection.
APPENDIX
The appendixes provide I/O maps, instructions, and other information.
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The contents of this document are subject to change without notice.
Customers are advised to consult with sales representatives before ordering.
The information, such as descriptions of function and application circuit examples, in this document are presented solely for the
purpose of reference to show examples of operations and uses of FUJITSU MICROELECTRONICS device; FUJITSU
MICROELECTRONICS does not warrant proper operation of the device with respect to use based on such information. When
you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of
such use of the information. FUJITSU MICROELECTRONICS assumes no liability for any damages whatsoever arising out of
the use of the information.
Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license
of the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of FUJITSU
MICROELECTRONICS or any third party or does FUJITSU MICROELECTRONICS warrant non-infringement of any thirdparty's intellectual property right or other right by using such information. FUJITSU MICROELECTRONICS assumes no
liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use of
information contained herein.
The products described in this document are designed, developed and manufactured as contemplated for general use, including
without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed
and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured,
could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss
(i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life
support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible
repeater and artificial satellite).
Please note that FUJITSU MICROELECTRONICS will not be liable against you and/or any third party for any claims or
damages arising in connection with above-mentioned uses of the products.
Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such
failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and
prevention of over-current levels and other abnormal operating conditions.
Exportation/release of any products described in this document may require necessary procedures in accordance with the
regulations of the Foreign Exchange and Foreign Trade Control Law of Japan and/or US export control laws.
The company names and brand names herein are the trademarks or registered trademarks of their respective owners.
Copyright ©2007-2008 FUJITSU MICROELECTRONICS LIMITED All rights reserved.
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CONTENTS
CHAPTER 1
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
1.10
CHAPTER 2
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.7.1
2.7.2
2.7.3
2.7.4
2.8
2.9
2.10
2.11
CPU ............................................................................................................ 25
Outline of the CPU ............................................................................................................................
Memory Space ..................................................................................................................................
Memory Space Map ..........................................................................................................................
Linear Addressing .............................................................................................................................
Bank Addressing Types ....................................................................................................................
Multi-byte Data in Memory Space .....................................................................................................
Registers ...........................................................................................................................................
Accumulator (A) ...........................................................................................................................
User Stack Pointer (USP) and System Stack Pointer (SSP) .......................................................
Processor Status (PS) .................................................................................................................
Program Counter (PC) .................................................................................................................
Register Bank ...................................................................................................................................
Prefix Codes .....................................................................................................................................
Interrupt Disable Instructions ............................................................................................................
Precautions for Use of "DIV A, Ri" and "DIVW A, RWi" Instructions ................................................
CHAPTER 3
3.1
3.2
3.3
3.4
3.5
3.5.1
3.5.2
3.5.3
3.6
3.7
3.7.1
3.7.2
3.8
OVERVIEW ................................................................................................... 1
Product Overview ............................................................................................................................... 2
Features .............................................................................................................................................. 3
Block Diagram of MB90V390H ........................................................................................................... 6
Block Diagram of MB90V390HA/MB90V390HB ................................................................................. 7
Block Diagram of MB90394HA/MB90F394H(A) ................................................................................. 8
Pin Assignment ................................................................................................................................... 9
Package Dimensions ........................................................................................................................ 12
Pin Functions .................................................................................................................................... 13
Input-Output Circuits ......................................................................................................................... 19
Handling Device ................................................................................................................................ 22
26
27
30
32
33
35
36
39
40
41
44
45
47
49
51
INTERRUPTS ............................................................................................. 53
Outline of Interrupts ..........................................................................................................................
Interrupt Vector .................................................................................................................................
Interrupt Control Registers (ICR) ......................................................................................................
Interrupt Flow ....................................................................................................................................
Hardware Interrupts ..........................................................................................................................
Hardware Interrupt Operation ......................................................................................................
Occurrence and Release of Hardware Interrupt ..........................................................................
Multiple interrupts ........................................................................................................................
Software Interrupts ...........................................................................................................................
Extended Intelligent I/O Service (EI2OS) ..........................................................................................
Extended Intelligent I/O Service Descriptor (ISD) .......................................................................
EI2OS Status Register (ISCS) .....................................................................................................
Operation Flow of and Procedure for Using the Extended Intelligent I/O Service (EI2OS) ..............
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54
57
59
62
64
65
66
68
69
71
73
75
77
3.9
Exceptions ........................................................................................................................................ 80
CHAPTER 4
4.1
4.2
4.3
Outline of Delayed Interrupt Module ................................................................................................. 82
Delayed Interrupt Register ................................................................................................................ 83
Delayed Interrupt Operation ............................................................................................................. 84
CHAPTER 5
5.1
5.2
5.3
5.3.1
5.3.2
5.4
5.5
5.6
5.7
106
107
108
109
114
121
RESETS .................................................................................................... 125
Resets .............................................................................................................................................
Reset Cause and Oscillation Stabilization Wait Times ...................................................................
External Reset Pin ..........................................................................................................................
Reset Operation ..............................................................................................................................
Reset Cause Bits ............................................................................................................................
Status of Pins in a Reset ................................................................................................................
CHAPTER 8
8.1
8.2
8.3
8.4
8.5
8.5.1
8.5.2
8.5.3
8.6
8.7
8.8
CLOCK MODULATOR ............................................................................. 105
Overview of Clock Modulator ..........................................................................................................
Register Description of Clock Modulator ........................................................................................
Registers of Clock Modulator ..........................................................................................................
Clock Modulator Control Register (CMCR) ...............................................................................
Clock Modulation Parameter Register (CMPR) .........................................................................
Application Note of the Clock Modulator .........................................................................................
CHAPTER 7
7.1
7.2
7.3
7.4
7.5
7.6
CLOCKS ..................................................................................................... 85
Clocks ............................................................................................................................................... 86
Block Diagram of the Clock Generation Block .................................................................................. 89
Clock Selection Registers ................................................................................................................. 91
Clock Selection Register (CKSCR) ............................................................................................. 92
PLL and Special Configuration Control Register (PSCCR) ......................................................... 95
Clock Mode ....................................................................................................................................... 97
Oscillation Stabilization Wait Time .................................................................................................. 100
Connection of an Oscillator or an External Clock to the Microcontroller ......................................... 101
Output of the main clock HCLK and HCLKX .................................................................................. 103
CHAPTER 6
6.1
6.2
6.3
6.3.1
6.3.2
6.4
DELAYED INTERRUPT ............................................................................. 81
126
128
130
131
133
136
LOW-POWER CONTROL CIRCUIT ........................................................ 137
Overview of Low-Power Consumption Mode ..................................................................................
Block Diagram of the Low-Power Consumption Control Circuit .....................................................
Low-Power Consumption Mode Control Register (LPMCR) ...........................................................
CPU Intermittent Operation Mode ..................................................................................................
Standby Mode .................................................................................................................................
Sleep Mode ...............................................................................................................................
Time-base Timer Mode .............................................................................................................
Stop Mode .................................................................................................................................
Status Change Diagram .................................................................................................................
Status of Pins in Standby Mode and during Reset .........................................................................
Usage Notes on Low-Power Consumption Mode ...........................................................................
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138
141
143
147
148
149
151
153
156
158
159
CHAPTER 9
9.1
9.2
9.3
MEMORY ACCESS MODES .................................................................... 163
Outline of Memory Access Modes .................................................................................................. 164
Mode Pins of Memory Access Mode .............................................................................................. 165
Mode Data of Memory Access Mode .............................................................................................. 166
CHAPTER 10 I/O PORTS ................................................................................................ 169
10.1 I/O Ports ..........................................................................................................................................
10.2 I/O Port Registers ...........................................................................................................................
10.2.1 Port Data Register .....................................................................................................................
10.2.2 Data Direction Register .............................................................................................................
10.2.3 Analog Input Enable Register ....................................................................................................
10.2.4 Input Level Select Register ........................................................................................................
170
171
172
174
175
176
CHAPTER 11 TIME-BASE TIMER .................................................................................. 177
11.1
11.2
11.3
Outline of Time-base Timer ............................................................................................................ 178
Time-base Timer Control Register .................................................................................................. 179
Operations of Time-base Timer ...................................................................................................... 181
CHAPTER 12 WATCHDOG TIMER ................................................................................ 183
12.1
12.2
Outline of Watchdog Timer ............................................................................................................. 184
Watchdog Timer Operation ............................................................................................................. 187
CHAPTER 13 16-BIT I/O TIMER ..................................................................................... 191
13.1 Outline of 16-Bit I/O Timer ..............................................................................................................
13.2 16-Bit I/O Timer Registers ..............................................................................................................
13.3 16-bit Free-run Timer ......................................................................................................................
13.3.1 Data Register .............................................................................................................................
13.3.2 Control Status Register .............................................................................................................
13.3.3 16-bit Free-run Timer Operation ................................................................................................
13.4 Output Compare .............................................................................................................................
13.4.1 Output Compare Register ..........................................................................................................
13.4.2 Control Status Register of Output Compare ..............................................................................
13.4.3 16-bit Output Compare Operation .............................................................................................
13.5 Input Capture ..................................................................................................................................
13.5.1 Input Capture Register Details ..................................................................................................
13.5.2 16-bit Input Capture Operation ..................................................................................................
192
194
196
197
198
201
203
204
205
210
215
216
221
CHAPTER 14 16-BIT RELOAD TIMER (WITH EVENT COUNT FUNCTION) ................ 223
14.1 Outline of 16-Bit Reload Timer (with Event Count Function) ..........................................................
14.2 16-Bit Reload Timer (with Event Count Function) ..........................................................................
14.2.1 Timer Control Status Register (TMCSR) ...................................................................................
14.2.2 Register Layout of 16-bit Timer Register (TMR)/16-bit Reload Register (TMRLR) ...................
14.3 Internal Clock and External Clock Operations of 16-bit Reload Timer ...........................................
14.4 Underflow Operation of 16-bit Reload Timer ..................................................................................
14.5 Output Pin Functions of 16-bit Reload Timer ..................................................................................
14.6 Counter Operation State .................................................................................................................
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224
226
227
230
231
233
234
235
CHAPTER 15 WATCH TIMER ........................................................................................ 237
15.1 Outline of Watch Timer ...................................................................................................................
15.2 Watch Timer Registers ...................................................................................................................
15.2.1 Timer Control Register ..............................................................................................................
15.2.2 Sub-second Registers ...............................................................................................................
15.2.3 Second/Minute/Hour Registers ..................................................................................................
238
239
240
244
245
CHAPTER 16 8/16-BIT PPG ........................................................................................... 247
16.1 Outline of 8/16-bit PPG ...................................................................................................................
16.2 Block Diagram of 8/16-bit PPG .......................................................................................................
16.3 8/16-bit PPG Registers ...................................................................................................................
16.3.1 PPG0 Operation Mode Control Register (PPGC0) ....................................................................
16.3.2 PPG1 Operation Mode Control Register (PPGC1) ....................................................................
16.3.3 PPG0/1 Clock Select Register (PPG01) ....................................................................................
16.3.4 Reload Register (PRLL/PRLH) ..................................................................................................
16.4 Operations of 8/16-bit PPG .............................................................................................................
16.5 Selecting a Count Clock for 8/16-bit PPG .......................................................................................
16.6 Controlling Pin Output of 8/16-bit PPG Pulses ...............................................................................
16.7 8/16-bit PPG Interrupts ...................................................................................................................
16.8 Initial Values of 8/16-bit PPG Hardware .........................................................................................
248
250
254
255
257
259
261
262
264
265
266
267
CHAPTER 17 DTP/EXTERNAL INTERRUPTS .............................................................. 269
17.1
17.2
17.3
17.4
17.5
Outline of DTP/External Interrupts ..................................................................................................
DTP/External Interrupt Registers ....................................................................................................
Operations of DTP/External Interrupts ............................................................................................
Switching between External Interrupt and DTP Requests ..............................................................
Notes on Using DTP/External Interrupts .........................................................................................
270
271
273
275
276
CHAPTER 18 8/10-BIT A/D CONVERTER ..................................................................... 279
18.1 Outline of the 8/10-Bit A/D Converter ............................................................................................. 280
18.2 Configuration of the 8/10-Bit A/D Converter ................................................................................... 282
18.3 8/10-Bit A/D Converter Pins ............................................................................................................ 284
18.4 8/10-Bit A/D Converter Registers ................................................................................................... 286
18.4.1 Analog Input Enable / A/D Converter Select Register ............................................................... 287
18.4.2 A/D Control Status Register 1 (ADCS1) .................................................................................... 288
18.4.3 A/D control status register 0 (ADCS0) ....................................................................................... 290
18.4.4 A/D Data Register (ADCR0, ADCR1) ........................................................................................ 292
18.5 8/10-Bit A/D Converter Interrupts ................................................................................................... 294
18.6 Operation of the 8/10-Bit A/D Converter ......................................................................................... 295
18.6.1 Conversion using EI2OS ............................................................................................................ 297
18.6.2 A/D conversion data protection function .................................................................................... 298
18.7 Notes on the 8/10-Bit A/D Converter .............................................................................................. 300
18.8 Sample Program 1 for the 8/10-Bit A/D Converter (Single Conversion Mode Using EI2OS) ......... 301
18.9 Sample Program 2 for the 8/10-Bit A/D Converter (Continuous Conversion Mode Using EI2OS)
.......................................................................................................................................................... 304
18.10 Sample Program 3 for the 8/10-Bit A/D Converter (Stop Conversion Mode Using EI2OS) ............ 307
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CHAPTER 19 UART0, UART1 ........................................................................................ 311
19.1 Features of UART0, UART1 ...........................................................................................................
19.2 UART0, UART1 Block Diagram ......................................................................................................
19.3 UART0, UART1 Registers ..............................................................................................................
19.3.1 Serial Mode Control Register (UMC) .........................................................................................
19.3.2 Status Register (USR) ...............................................................................................................
19.3.3 Input Data Register (UIDR) and Output Data Register (UODR) ................................................
19.3.4 Rate and Data Register (URD) ..................................................................................................
19.4 UART0, UART1 Operation .............................................................................................................
19.5 Baud Rate .......................................................................................................................................
19.6 Internal and External Clock .............................................................................................................
19.7 Transfer Data Format .....................................................................................................................
19.8 Parity Bit .........................................................................................................................................
19.9 Interrupt Generation and Flag Set Timings .....................................................................................
19.9.1 Flag Set Timings for a Receive Operation (Mode0, Mode1, Mode3) ........................................
19.9.2 Flag Set Timings for a Receive Operation (in Mode 2) .............................................................
19.9.3 Flag Set Timings for a Transmit Operation ................................................................................
19.9.4 Status Flag During Transmit and Receive Operation ................................................................
19.10 UART0, UART1 Application Example .............................................................................................
312
313
314
315
317
319
320
322
323
326
327
328
329
330
331
332
333
334
CHAPTER 20 UART2, UART3 ........................................................................................ 337
20.1 Overview of UART2, UART3 ..........................................................................................................
20.2 Configuration of UART2, UART3 ....................................................................................................
20.3 UART2, UART3 Pins ......................................................................................................................
20.4 UART2, UART3 Registers ..............................................................................................................
20.4.1 Serial Control Register (SCR2/SCR3) .......................................................................................
20.4.2 Serial Mode Register (SMR2/SMR3) .........................................................................................
20.4.3 Serial Status Register (SSR2/SSR3) .........................................................................................
20.4.4 Reception and Transmission Data Register (RDR2/RDR3 and TDR2/TDR3) ..........................
20.4.5 Extended Status/Control Register (ESCR2/ESCR3) .................................................................
20.4.6 Extended Communication Control Register (ECCR2/ECCR3) ..................................................
20.4.7 Baud Rate Generator Register 0 and 1 (BGR02/03 and BGR12/13) ........................................
20.5 UART2, UART3 Interrupts ..............................................................................................................
20.5.1 Reception Interrupt Generation and Flag Set Timing ................................................................
20.5.2 Transmission Interrupt Generation and Flag Set Timing ...........................................................
20.6 UART2, UART3 Baud Rates ..........................................................................................................
20.6.1 Setting the Baud Rate ...............................................................................................................
20.6.2 Reload Counter .........................................................................................................................
20.7 Operation of UART2, UART3 .........................................................................................................
20.7.1 Operation in Asynchronous Mode (Op. Modes 0 and 1) ...........................................................
20.7.2 Operation in Synchronous Mode (Operation Mode 2) ...............................................................
20.7.3 Operation with LIN Function (Operation Mode 3) ......................................................................
20.7.4 Direct Access to Serial Pins ......................................................................................................
20.7.5 Bidirectional Communication Function (Normal Mode) .............................................................
20.7.6 Master/Slave Communication Function (Multiprocessor Mode) ................................................
20.7.7 LIN Communication Function ....................................................................................................
20.7.8 Sample Flowcharts for UART2, UART3 in LIN Communication (Operation Mode 3) ................
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338
342
347
349
350
352
354
357
359
362
364
365
369
371
373
375
378
380
382
385
388
392
393
395
398
399
20.8
Notes on Using UART2, UART3 ..................................................................................................... 401
CHAPTER 21 400 kHz I2C INTERFACE ......................................................................... 405
21.1 I2C Interface Overview ....................................................................................................................
21.2 I2C Interface Registers ...................................................................................................................
21.2.1 Bus Status Register (IBSR) .......................................................................................................
21.2.2 Bus Control Register (IBCR) .....................................................................................................
21.2.3 Ten Bit Slave Address Register (ITBA) .....................................................................................
21.2.4 Ten Bit Address Mask Register (ITMK) .....................................................................................
21.2.5 I2C Seven Bit Slave Address Register (ISBA) ...........................................................................
21.2.6 I2C Data Register (IDAR) ..........................................................................................................
21.2.7 I2C Clock Control Register (ICCR) ............................................................................................
21.2.8 Noise Filter Configuration Register (INFCR) .............................................................................
21.3 I2C Interface Operation ...................................................................................................................
21.4 Programming Flow Charts ..............................................................................................................
406
408
410
413
422
423
425
427
428
431
432
435
CHAPTER 22 SERIAL I/O ............................................................................................... 437
22.1 Outline of Serial I/O ........................................................................................................................
22.2 Serial I/O Registers .........................................................................................................................
22.2.1 Serial Mode Control Status Register (SMCS) ...........................................................................
22.2.2 Serial Shift Data Register (SDR) ...............................................................................................
22.3 Serial I/O Prescaler (CDCR) ...........................................................................................................
22.4 Serial I/O Operation ........................................................................................................................
22.4.1 Shift Clock .................................................................................................................................
22.4.2 Serial I/O Operation ...................................................................................................................
22.4.3 Shift Operation Start/Stop Timing ..............................................................................................
22.4.4 Interrupt Function of the Extended Serial I/O Interface .............................................................
438
439
440
444
445
446
447
448
450
453
CHAPTER 23 CAN CONTROLLER ................................................................................ 455
23.1 Features of CAN Controller ............................................................................................................
23.2 Block Diagram of CAN Controller ...................................................................................................
23.3 List of Overall Control Registers .....................................................................................................
23.4 List of Message Buffers (ID Registers) ...........................................................................................
23.5 List of Message Buffers (DLC Registers and Data Registers) ........................................................
23.6 Classifying the CAN Controller Registers .......................................................................................
23.6.1 Control Status Register (CSR) ..................................................................................................
23.6.2 Bus Operation Stop Bit (HALT = 1) ...........................................................................................
23.6.3 Last Event Indicator Register (LEIR) .........................................................................................
23.6.4 Receive and Transmit Error Counters (RTEC) ..........................................................................
23.6.5 Bit Timing Register (BTR) ..........................................................................................................
23.6.6 Message Buffer Valid Register (BVALR) ...................................................................................
23.6.7 IDE register (IDER) ....................................................................................................................
23.6.8 Transmission Request Register (TREQR) ................................................................................
23.6.9 Transmission RTR Register (TRTRR) .......................................................................................
23.6.10 Remote Frame Receiving Wait Register (RFWTR) ...................................................................
23.6.11 Transmission Cancel Register (TCANR) ...................................................................................
23.6.12 Transmission Complete Register (TCR) ....................................................................................
x
456
457
458
460
463
466
467
472
474
476
477
479
480
481
482
483
484
485
23.6.13 Transmission Interrupt Enable Register (TIER) .........................................................................
23.6.14 Reception Complete Register (RCR) ........................................................................................
23.6.15 Remote Request Receiving Register (RRTRR) ........................................................................
23.6.16 Receive Overrun Register (ROVRR) .........................................................................................
23.6.17 Reception Interrupt Enable Register (RIER) .............................................................................
23.6.18 Acceptance Mask Select Register (AMSR) ...............................................................................
23.6.19 Acceptance Mask Registers 0 and 1 (AMR0 and AMR1) ..........................................................
23.6.20 Message Buffers ........................................................................................................................
23.6.21 ID Register x (x = 0 to 15) (IDRx) ..............................................................................................
23.6.22 DLC Register x (x = 0 to 15) (DLCRx) .......................................................................................
23.6.23 Data Register x (x = 0 to 15) (DTRx) .........................................................................................
23.7 Transmission of CAN Controller .....................................................................................................
23.8 Reception of CAN Controller ..........................................................................................................
23.9 Reception Flowchart of CAN Controller ..........................................................................................
23.10 How to Use the CAN Controller ......................................................................................................
23.11 Procedure for Transmission by Message Buffer (x) .......................................................................
23.12 Procedure for Reception by Message Buffer (x) .............................................................................
23.13 Setting Configuration of Multi-level Message Buffer .......................................................................
23.14 Setting the redirection of CAN1 and CAN3 RX/TX pin ...................................................................
23.15 Setting the CAN Direct Mode Register ...........................................................................................
23.16 Precautions when Using CAN Controller ........................................................................................
486
487
488
489
490
491
493
495
496
498
499
501
504
507
508
510
512
514
516
518
519
CHAPTER 24 STEPPING MOTOR CONTROLLER ....................................................... 521
24.1 Outline of Stepping Motor Controller ..............................................................................................
24.2 Stepping Motor Controller Registers ...............................................................................................
24.2.1 PWM Control 0 register .............................................................................................................
24.2.2 PWM1 and PWM2 Compare Registers .....................................................................................
24.2.3 PWM1 and PWM2 Select Registers ..........................................................................................
24.3 Notes on Using the Stepping Motor Controller ...............................................................................
522
523
524
526
527
531
CHAPTER 25 SOUND GENERATOR ............................................................................. 533
25.1 Outline of Sound Generator ............................................................................................................
25.2 Sound Generator Registers ............................................................................................................
25.2.1 Sound Generator Control Register ............................................................................................
25.2.2 Frequency Data register ............................................................................................................
25.2.3 Amplitude Data Register ............................................................................................................
25.2.4 Decrement Grade Register ........................................................................................................
25.2.5 Tone Count Register .................................................................................................................
534
535
536
539
540
541
542
CHAPTER 26 ADDRESS MATCH DETECTION FUNCTION ......................................... 543
26.1
26.2
26.3
26.4
Outline of the Address Match Detection Function ..........................................................................
Registers of the Address Match Detection Function .......................................................................
Operation of the Address Match Detection Function ......................................................................
Example of the Address Match Detection Function ........................................................................
544
545
547
548
CHAPTER 27 ROM MIRRORING MODULE ................................................................... 551
27.1
Outline of ROM Mirroring Module ................................................................................................... 552
xi
27.2
ROM Mirroring Register (ROMM) ................................................................................................... 553
CHAPTER 28 3M-BIT FLASH MEMORY ........................................................................ 555
28.1 Overview of 3M-bit Flash Memory ..................................................................................................
28.2 Block Diagram of the Entire Flash Memory and Sector Configuration of the Flash Memory ..........
28.3 Write/Erase Modes .........................................................................................................................
28.4 Flash Memory Control Status Register (FMCS) .............................................................................
28.5 Starting the Flash Memory Automatic Algorithm ............................................................................
28.6 Confirming the Automatic Algorithm Execution State .....................................................................
28.6.1 Data Polling Flag (DQ7) ............................................................................................................
28.6.2 Toggle Bit Flag (DQ6) ................................................................................................................
28.6.3 Timing Limit Exceeded Flag (DQ5) ...........................................................................................
28.6.4 Sector Erase Timer Flag (DQ3) .................................................................................................
28.6.5 Toggle Bit-2 Flag (DQ2) ............................................................................................................
28.7 Detailed Explanation of Writing to and Erasing Flash Memory .......................................................
28.7.1 Setting The Read/Reset State ...................................................................................................
28.7.2 Writing Data ...............................................................................................................................
28.7.3 Erasing All Data (Erasing Chips) ...............................................................................................
28.7.4 Erasing Optional Data (Erasing Sectors) ...................................................................................
28.7.5 Suspending Sector Erase ..........................................................................................................
28.7.6 Restarting Sector Erase ............................................................................................................
28.8 Notes on using 3M-bit Flash Memory .............................................................................................
28.9 Reset Vector Address in Flash Memory .........................................................................................
28.10 Example of Programming 3M-bit Flash Memory ............................................................................
556
557
559
561
563
565
567
569
570
571
573
575
576
577
579
580
582
583
584
586
587
CHAPTER 29 EXAMPLES OF SERIAL PROGRAMMING CONNECTION .................... 591
29.1
29.2
29.3
29.4
29.5
Basic Configuration of MB90F394H(A) Serial Programming Connection .......................................
Example of Serial Programming Connection ..................................................................................
Example of Serial Programming Connection (Power Supplied From the Programmer) .................
Example of Minimum Connection to the Flash Microcontroller Programmer
(User Power Supply Used) .............................................................................................................
Example of Minimum Connection to the Flash Microcontroller Programmer
(Power Supplied From the Programmer) ........................................................................................
592
596
598
600
602
APPENDIX ......................................................................................................................... 605
APPENDIX A I/O Maps ..............................................................................................................................
APPENDIX B Instructions ...........................................................................................................................
B.1 Instruction Types ............................................................................................................................
B.2 Addressing .....................................................................................................................................
B.3 Direct Addressing ...........................................................................................................................
B.4 Indirect Addressing ........................................................................................................................
B.5 Execution Cycle Count ...................................................................................................................
B.6 Effective address field ....................................................................................................................
B.7 How to Read the Instruction List ....................................................................................................
B.8 F2MC-16LX Instruction List ............................................................................................................
B.9 Instruction Map ...............................................................................................................................
APPENDIX C Timing Diagrams in Flash Memory Mode ............................................................................
xii
606
621
622
623
625
631
639
642
643
646
660
682
APPENDIX D List of Interrupt Vectors ........................................................................................................ 690
INDEX................................................................................................................................... 695
xiii
xiv
Main changes in this edition
Page
621 to 681
Changes (For details, refer to main body.)
Changed the entire part of "APPENDIX B Instructions"
The vertical lines marked in the left side of the page show the changes.
Reference: Main changes (Rev.2 → Rev.3)
Page
Changes (For details, refer to main body.)
Added the following part number.
(MB90V390HA, MB90V390HB, MB90394HA, MB90F394HA)
-
Register name and pin name are changed.
(Program bank register (PCB) → Program counter bank register (PCB))
(Additional bank register (ADB) → Additional data bank register (ADB))
(ESCR3 → ESCR2/ESCR3)
(SIN3 → SIN2/SIN3)
(SOT3 → SOT2/SOT3)
(SMR3 → SMR2,SMR3)
(ECCR3 → ECCR2/ECCR3)
(BGR03/13 → BGR02/BGR03,BGR12/BGR13)
(SSR3 → SSR2/SSR3)
(RDR3 → RDR2/RDR3)
(SCR3 → SCR2/SCR3)
(TDR3 → TDR2/TDR3)
(SCK3 → SCK2/SCK3)
(UODR0, 1, 2 → UODR0, UODR1)
(UIDR0, 1, 2 → UIDR0, UIDR1)
Function name is changed.
(UART0, 1, 2 → UART0, UART1)
(UART3 → UART2, UART3)
(UART3 synchronous clock mode → UART2, UART3 synchronous clock mode)
(3M/4M-BIT FLASH MEMORY → 3M-BIT FLASH MEMORY)
3
Table 1.2-1 Features of the MB90390 Series (1/3) is changed.
(UART of MB90V390H : 3 channels → 2 channels)
4
Table 1.2-1 Features of the MB90390 Series (2/3) is changed.
(Clock Modulator is added.)
5
Table 1.2-1 Features of the MB90390 Series (3/3) is changed.
(15 years → 20 years*)
(* is added.)
13
Table 1.8-1 Pin Description (1/6)
Pin name of pin number 98 is changed.
(P00 to P05 → P05)
22
● Preventing latch-up is changed.
(Therefore, the maximum voltage ratings must not be exceeded. By the same token, make sure that the
analog supply voltage (AVCC and AVRH) should not exceed the digital supply voltage. is added.)
23
● Power supply input pins (VCC/VSS) is changed.
xv
Reference: Main changes (Rev.2 → Rev.3)
Page
24
Changes (For details, refer to main body.)
● Crystal Oscillator Circuit is changed.
(Please ask the crystal maker to evaluate the oscillational characteristics of the crystal and this device. is
added.)
● Turning-on Sequence of Power Supply to A/D Converter and Analog Inputs is changed.
((turning on/off the analog and digital power supplies simultaneously is acceptable) is deleted.)
● Note on operation during PLL clock mode is changed.
55
Figure 3.1-2 Overview of Software Interrupts is changed.
(ILM : Interrupt level mask register → S :Stack flag)
59
Notes is changed.
(• ICS1 and ICS0 are valid for write only. S1 and S0 are valid for read only. is added.)
(<Additional information> is added.)
63
Figure 3.4-2 Register Saving During Interrupt Processing is changed.
(DPB → DTB)
68
Figure 3.5-2 Registers Saved in Stack is changed.
(DPB → DTB)
70
Figure 3.6-1 Occurrence and Release of Software Interrupt is changed.
(ILM : Interrupt level mask register → S :Stack flag)
78
● When data transfer continues (when the stop condition is not satisfied) is changed.
((Table 3.8-1 "Execution time when the extended EI2OS continues" + Table 3.8-2 "Data transfer compensation values for extended EI2OS execution time") machine cycles → ((Table 3.8-1 + Table 3.8-2) machine
cycles)
103
Summary of 5.7 Output of the main clock HCLK and HCLKX is changed.
105
CHAPTER 6 CLOCK MODULATOR
Notes is changed.
112
Table 6.3-1 Function of Each Bit of the Clock Modulator Control Register (3/3)
Function of bit1 is changed.
(6 ms → 6 µs)
113
Table 6.3-2 States of the Modulator is changed.
(modulator power on, waiting modulator startup time (> 6 ms) →
modulator power on, waiting modulator startup time (> 6 µs))
114
Figure 6.3-3 Modulation Parameter Register is changed.
(CMPRL (upper) → CMPRH (upper))
(XX0000010 B → XX000010B)
141
Figure 8.2-1 Block Diagram of the Low-power Consumption Control Circuit is changed.
(Osc. stab. wait clear → Oscillation stabilization wait time clear)
158
8.7 Status of Pins in Standby Mode and during Reset is added.
175
■ Analog Input Enable Registers
Note is changed.
(ANIN 0 to 7 → AN0 to AN7)
(ANIN 8 to 14 → AN8 to AN14)
184
Figure 12.1-1 Watchdog Timer Block Diagram is changed.
187
■ State Transition Diagram of the Watchdog Timer is added.
188
■
■
■
■
189
■ Watchdog Timer Behavior at Reset is added.
Watchdog Counter is changed.
Watchdog Stop is changed.
Watchdog Deactivation is added.
Watchdog Timer Behavior in Stop Mode, Time-base Timer Mode, and Sleep Mode is added.
xvi
Reference: Main changes (Rev.2 → Rev.3)
Page
Changes (For details, refer to main body.)
220
Table 13.5-3 Input Capture Edge Register Bits (Upper and Lower)
Bit name of bit10 is changed.
(IUCE → IUCE1/IUCE5)
bit2 is changed.
234
Figure 14.5-1 Output Pin Function of 16-bit Reload Timer (1) is changed.
Figure 14.5-2 Output Pin Function of 16-bit Reload Timer (2) is changed.
235
Figure 14.6-1 Counter State Transitions is changed.
239
Figure 15.2-1 Watch Timer Registers
WTCR is changed.
(0 0 0 - - 0 0 0 → 000XX000)
WTSR is changed.
(- - - X X X X X → XXXXXXXX)
WTBR1 is changed.
(- - X X X X X X → XXXXXXXX)
WTHR is changed.
(- - - X X X X X → XXXXXXXX)
WTMR is changed.
(- - X X X X X X → XXXXXXXX)
Notes is changed.
(timer control register (WTC) → timer control register (WTCR))
243
Table 15.2-2 Timer Control Register (Upper) is changed.
245
Figure 15.2-5 Configuration of the Second/Minute/Hour Registers is changed.
(00354CH is deleted.)
250
Figure 16.2-1 8/16-bit PPG ch.0 Block Diagram is changed.
(PRLBH0 → PRLL0)
((Temporary buffer) is added.)
251
Figure 16.2-2 8/16-bit PPG ch.1 Block Diagram is changed.
(PRLBH1 → PRLL1)
((Temporary buffer) is added.)
252, 253
●
●
●
●
●
●
●
●
●
Details of pins in block diagram is added.
PPG operation mode control register 0 (PPGC0) is added.
PPG0/1 count clock select register (PPG01) is added.
PPG0 reload registers (PRLH0 and PRLL0) is added.
PPG0 down counter (PCNT0) is added.
PPG0 temporary buffer (PRLBH0) is added.
Reload register L/H selector is added.
Count clock selector is added.
PPG output control circuit is added.
254
■ 8/16-bit PPG Registers
PPGCn is changed.
((0)(-)(0)(0)(0)(-)(-)(1) → (0)(X)(0)(0)(0)(X)(X)(1))
PPGCm is changed.
((0)(-)(0)(0)(0)(0)(0)(1) → (0)(X)(0)(0)(0)(0)(0)(1))
PPGnm is changed.
((0)(0)(0)(0)(0)(0)(-)(-) → (0)(0)(0)(0)(0)(0)(X)(X))
259
Figure 16.3-3 Configuration of the PPG0/1 Clock Select Register (PPG01)
PCM1 and PCS1 in "Clock input from time-base timer" are changed.
(0 → 1)
xvii
Reference: Main changes (Rev.2 → Rev.3)
Page
Changes (For details, refer to main body.)
260
Table 16.3-3 Bit Function Description of the Clock Select Register (PPG01)
PCS1 and PCM1 in "Clock input from time-base timer" are changed.
(0 → 1)
261
■ Reload Register (PRLL/PRLH)
Address of PRLLn is changed.
(ch6 00350BH → ch.6 00350CH)
264
■ Selecting a Count Clock for 8/16-bit PPG
Note is added.
271
■ Interrupt/DTP Enable Register (ENIR: Interrupt Request Enable Register)
Note is added.
272
■ Interrupt/DTP Flags (EIRR: External Interrupt Request Register)
Note is changed.
285
Note is changed.
(ANIN 0 to 7 → AN0 to AN7)
(ANIN 8 to 14 → AN8 to AN14)
287
Figure 18.4-2 Configuration of the Upper Bits of Analog Input Enable / A/D Converter Select Register
(ADER1)
A/D converter input selection bit is changed.
(ANIN 0 to 7 → AN0 to AN7)
(ANIN 8 to 14 → AN8 to AN14)
289
Table 18.4-1 Function Description of Each Bit of Control Status Register 1 (ADCS1)
Function of bit12 is changed.
(Once this bit is set, it is not cleared by itself, write "0" to clear this bit. is added.)
291
Table 18.4-2 Function Description of Each Bit of Control Status Register 0 (ADCS0)
Function of bit5,bit4 and bit3 is changed.
(Note is added.)
298
● Data protection function when EI2OS is used is changed.
(the PAUS bit is cleared to 0 and conversion resumes. → When the data transfer to memory is completed,
conversion resumes, but once PAUS bit is set, it is not cleared by itself, write "0" to clear PAUS bit.)
312
Summary of 19.1 Features of UART0, UART1 is changed.
(The UARTs 1 and 2 have the identical function as UART0. is deleted.)
314
■ UART0, UART1 Registers
Serial mode control register is changed.
(UMC2 is deleted.)
(ch.2 000028H is deleted.)
Status register is changed.
(USR2 is deleted.)
(ch.2 000029H is deleted.)
Input data register/Output data register is changed.
(UIDR2 and UODR2 is deleted.)
(ch.2 00002AH is deleted.)
Rate and data register is changed.
(URD2 is deleted.)
(ch.2 00002BH is deleted.)
xviii
Reference: Main changes (Rev.2 → Rev.3)
Page
Changes (For details, refer to main body.)
315
Figure 19.3-1 Configuration of the Serial Mode Control Register (UMC) is changed.
(UMC2 is deleted.)
(000028H is deleted.)
Serial Output enable is changed.
(SOT0,1,2 → SOT0, SOT1)
316
Table 19.3-1 Function of Each Bit of the Serial Control Register
Function of bit1 and bit0 is changed.
(Note is deleted.)
317
Figure 19.3-2 Configuration of the Status Register (USR) is changed.
(USR2 is deleted.)
(000029H is deleted.)
319
Figure 19.3-3 Input Data Register (UIDR) and Output Data Register (UODR) is changed.
(00002AH is deleted.)
320
Figure 19.3-4 Configuration of the Rate and Data Register (URD) is changed.
(URD2 is deleted.)
(00002BH is deleted.)
327
■ Transfer Data Format is changed.
(UMC0, 1, 2 → UMC0, UMC1)
(SIN0, 1, 2 → SIN0, SIN1)
(SOUT0, 1, 2 → SOUT0, SOUT1)
328
Summary of 19.8 Parity Bit is changed.
(URD0, 1, 2 → URD0, URD1)
(UMC0, 1, 2 → UMC0, UMC1)
337
CHAPTER 20 UART2, UART3
Note is added.
339
Table 20.1-1 UART2, UART3 Functions (2/2)
Function of LIN bus options is changed.
((UART3) / ICU3 (UART2, MB90V390HA/MB90V390HB only) is added.)
341
Table 20.1-4 UART2, UART3 Interrupt and EI2OS is changed.
342
■ Block Diagram of UART2, UART3 is changed.
(• LIN Synch Break Generation Circuit is added.)
347
Table 20.3-1 UART2, UART3 Pins is changed.
348
Figure 20.3-1 Block Diagram of UART2, UART3 Pins is changed.
(Note:UART2 is functionally the same as UART3, except the registers and pin numbers is added.)
349
Figure 20.4-1 UART2, UART3 Registers is changed.
350
Figure 20.4-2 Configuration of the Serial Control Register (SCR2/SCR3) is changed.
(SCR2: 0035D9H is added.)
352
Figure 20.4-3 Configuration of the Serial Mode Register (SMR2/SMR3)
SMR2: 0035D8H is added.
Serial data output enable bit of LIN-UART is changed.
(disable SOT3 pin (high Z) → General purpose I/O port)
(enable SOT3 pin (TxData) → LIN-UART serial data output pin)
Serial clock output enable bit of LIN-UART is changed.
(External Serial Clock Input → General purpose I/O port or LIN-UART clock input pin)
(Internal Serial Clock Output → Serial clock output pin of LIN-UART)
354
Figure 20.4-4 Configuration of the Serial Status Register (SSR2/SSR3) is changed.
(SSR2: 0035DBH is added.)
xix
Reference: Main changes (Rev.2 → Rev.3)
Page
357
Changes (For details, refer to main body.)
Figure 20.4-5 Transmission and Reception Data Registers (RDR2/RDR3 and TDR2/TDR3) is changed.
(RDR2/TDR2: 0035DAH is changed.)
("0 0 0 0 0 0 0 0B [TDR3] (MB90V390H/MB90F394H)" is deleted.)
Summary of 20.4.5 Extended Status/Control Register (ESCR2/ESCR3) is changed.
359
360
Figure 20.4-6 Configuration of the Extended Status/Control Register (ESCR2/ESCR3) is changed.
(ESCR2: 0035DDH is added.)
Table 20.4-4 Function of Each Bit of the Extended Status/Control Register (ESCR2/ESCR3)
Function of bit10 is changed.
("• A set value of this bit is effective only for the TXE bit of serial control register (SCR) is "0". " is added.)
Bit name of bit8 is changed.
(Serial clock edge selection bit → Sampling clock edge selection bit)
361
Table 20.4-5 Description of the Interaction of SOPE and SIOP is changed.
362
Figure 20.4-7 Configuration of the Extended Communication Control Register (ECCR2/ECCR3) is changed.
(ECCR2: 0035DCH is added.)
(00000XXXB → X0000XXXB)
(BIE * is deleted in bit2)
364
Figure 20.4-8 Bit Configuration of Baud Rate Generator Register (BGR02/03 and BGR12/13)
BGR02: 0035DEH and BGR12: 0035DFH are added.
Access of bit15 is changed.
(- → R)
bit7 to bit0 is changed.
(BGR0 → BGR7 to BGR0)
(Baud rate Generator Register 0 → Baud rate Generator Register 02,03)
(Read bit 0 to 7 of actual count → Read bit 7 to 0 of transmission reload counter)
bit14 to bit8 is changed.
(BGR1 → BGR14 to BGR8)
(Baud rate Generator Register 1 → Baud rate Generator Register 12,13)
(Read bit 8 to 14 of actual count → Read bit 14 to 8 of transmission reload counter)
365
Table 20.5-1 Interrupt Control Bits and Interrupt Causes of LIN-UART2, UART3
Input Capture Unit is changed.
(ICP3, ICS23, ICE3 is added.)
367
● LIN Synchronization Field Edge Detection Interrupts is changed.
(ICU1/5 → ICU1/ICU3/ICU5)
Table 20.5-2 UART2, UART3 Interrupt and EI2OS is changed.
368
● For UART2 Reception is changed.
● For UART2 Transmission is changed.
373
● Baud rates determined using the dedicated baud rate generator (reload counter) is changed.
(These baud rates are used in asynchronous mode or synchronous mode (master). To set the clock source,
select the internal clock and the use of the baud rate generator clock (SMR2/SMR3:EXT=0, OTO=0) is
added.)
● Baud rates determined using external clock (one-to-one mode) is changed.
(These baud rates are used in synchronous mode (slave). To set the clock source, select the external clock and
its direct use (SMR2/SMR3:EXT=1, OTO=1). is added.)
● Baud rates determined using the dedicated baud rate generator with external clock is changed.
379
■ Clearing Reload Counters is changed.
(Writing "0" to the REST bit does not clear the counters and they restart from reload value immediately. →
Writing "1" to the REST bit does not clear the counters and they restart from reload value immediately.)
xx
Reference: Main changes (Rev.2 → Rev.3)
Page
Changes (For details, refer to main body.)
383
● Reception operation is changed.
(To read received data, check the error flag status upon completion of reception of one-frame data and, if the
data has been received normally, read the received data from the Reception Data Register (RDR2/RDR3). If a
reception error has occurred, perform error handling. is added.)
384
Figure 20.7-2 Data Transmitted with Parity Enabled is added.
● Data signaling method is added.
● Data transfer method is added.
385
● Transfer data format is changed.
386
● Clock supply is changed.
387
● Communication is changed.
(P: "0" for even parity, "1" odd parity → P: "1" for even parity, "0" odd parity)
388
Table 20.7-2 LIN Break Length is changed.
(LBL0 → LBL1)
(LBL1 → LBL0)
389
● UART2, UART3 as LIN slave is changed.
(ICU counter register → ICU data register)
(Note is added.)
391
Figure 20.7-9 LIN Bus Timing and UART2, UART3 Signals
LBIE disable is changed.
392
■ UART2, UART3 Direct Pin Access is changed.
393
Figure 20.7-10 Settings for UART2, UART3 Operation Mode 0 and 2
Mode0 of EXT is changed.
( → 0)
Mode0 of SCKE is changed.
( → 0)
Mode0 of LBIE is changed.
( → X)
Mode0 of LBD is changed.
( → X)
Mode0 of LBL1 is changed.
( → X)
Mode0 of LBL0 is changed.
( → X)
Mode2 of CCO is changed.
( → )
Mode0 of SCES is changed.
(X → +)
Mode0 of LBR is changed.
( → 0)
395
Figure 20.7-13 Settings for UART2, UART3 Operation Mode 1
Mode1 of EXT is changed.
( → 0)
Mode1 of SCKE is changed.
( → 0)
Mode1 of MD0 is changed.
(0 → 1)
397
Figure 20.7-15 Master/Slave Communication Flowchart is changed.
(Set SOT3 pin as the serial data output pin. → Set SOT2/SOT3 pin as the port input pin.)
xxi
Reference: Main changes (Rev.2 → Rev.3)
Page
Changes (For details, refer to main body.)
398
Figure 20.7-16 Settings for UART2, UART3 in Operation Mode 3 (LIN)
Mode3 of EXT is changed.
( → 0)
Mode3 of SCKE is changed.
( → 0)
Mode3 of SCES is changed.
(0 → +)
399
Figure 20.7-18 UART2, UART3 LIN Master Flow Chart is changed.
(RXE=0, RIE=1 → RXE=1, RIE=1)
401
● Enabling operations is changed.
(control register (SCR3) → serial control register (SCR2/SCR3))
408, 409
■ I2C Interface Registers is changed.
(ITBA → ITBAH)
(ITBA → ITBAL)
(ITMK → ITMKH)
(ITMK → ITMKL)
(Figure is added in Noise filter configuration register (INFCR))
422
Table 21.2-3 Function of Each Bit of the Ten Bit Slave Address Register (ITBA)
Bit name of bit9 to bit0 is changed.
(TBA9 to 0 → TA9 to TA0)
423
■ Ten Bit Address Mask Register (ITMK) is changed.
(ITMK → ITMKH)
(ITMK → ITMKL)
426
Table 21.2-6 Function of Each Bit of the I2C Seven Bit Slave Address Mask Register
Bit name of bit14 to bit8 is changed.
(SMK → SM6 to SM0)
429
Table 21.2-8 Function of Each Bit of the I2C Clock Control Register
Function of bit14 is changed.
Function of bit13 is changed.
(Notes is changed.)
430
■ Clock Prescaler Settings is changed.
(INFCR:SEL[1:0]=01B is added.)
Table 21.2-10 Common Machine Clock Frequencies is changed.
(400 kBit (Noise filter enabled) n Bit rate [kBit] →
400 kbit (Noise filter enabled, INFCR:SEL[1:0]= 01B) n Bit rate [kbit])
431
21.2.8 Noise Filter Configuration Register (INFCR) is added.
453
Figure 22.4-8 Interrupt Signal Output Timing of the Extended Serial I/O Interface is changed.
545
26.2 Registers of the Address Match Detection Function is changed.
(PADR0 to PADR5 → PADR0, PADR1, PADR3 to PADR5)
549
Figure 26.4-2 Example of Program Patch Processing is changed.
557
Figure 28.2-1 Block Diagram of the Entire Flash Memory is changed.
(AQ0 to AQ17 AQ-1 → AQ0 to AQ18)
xxii
Reference: Main changes (Rev.2 → Rev.3)
Page
Changes (For details, refer to main body.)
563
Table 28.5-1 Command Sequence Table
1st bus write cycle is changed in Address of Auto-select.
(FxAAA → FxAAAA)
Notes is changed.
(• The addresses Fx in the table mean FF, FE, FD, FB, FA and F9 for 3M-bit Flash Memory and FF, FE, FD,
FC, FB, FA, F9 and F8 for the 4M-bit Flash Memory. Use these addresses as the access target bank values for
operations. → • The addresses Fx in the table mean FF, FE, FD, FB, FA and F9 for 3M-bit Flash Memory.
Use these addresses as the access target bank values for operations.)
■ Suspending Erasing of Flash Memory Sectors is changed.
582
584
(after a maximum period of 15µs has elapsed. → after a maximum period of 20µs has elapsed.)
("Sector Erase Suspend command should be entered more than 20µs after Sector Erase command or Sector
Erase Restart command is issued." is added)
● Input of a hardware reset (RST) is changed.
593
Table 29.1-1 Pins Used for Fujitsu Standard Serial Onboard Programming
Additional information of VCC is changed.
606
Table A-1 I/O Map (1/6)
Register of Address 00000DH is changed.
(Analog Input Enable 1/ ADC Select → Analog Input Enable 1)
607
Table A-1 I/O Map (2/6)
Address 000028H to 00002BH is changed.
(UART2 → Reserved)
Register and Abbreviation in Address 00002FH are changed.
(Serial I/O Prescaler/Edge Selector → Serial I/O Prescaler)
Register of Address 000030H is changed.
(External Interrupt Enable → External/DTP Enable Register)
608
Table A-1 I/O Map (3/6)
Register and Peripheral in Address 00003BH are changed.
(ROM Correction Control Status 1 → Program address detection control status register 1)
(ROM Correction 1 → Program Address Detection 1)
Register of Address 00003EH is changed.
(PPG2 and PPG3 clock select register → PPG2/PPG3 clock control register)
609
Table A-1 I/O Map (4/6)
Initial value of Address 00005FH is changed.
(0XXXXXX0B → 0XXXXX00B)
610
Table A-1 I/O Map (5/6)
Initial value of Address 00006FH is changed.
(XXXXXXX1B → XXXXXX+*1B)
Register and Peripheral in Address 00009EH are changed.
(ROM Correction Control Status 0 → Program address detection control status register 0)
(ROM Correction 0 → Program Address Detection0)
* is added.
xxiii
Reference: Main changes (Rev.2 → Rev.3)
Page
Changes (For details, refer to main body.)
613
Table A-2 I/O Map (35XX Addresses) (2/8)
Initial value of Address 00351AH is changed.
(11111111B is added.)
Initial value of Address 00351CH is changed.
(000000XXB → X0000XXXB)
Abbreviation of Address 00352EH is changed.
(TCCS0 → TCCSL0)
Abbreviation of Address 00352FH is changed.
(TCCS0 → TCCSH0)
614
Table A-2 I/O Map (35XX Addresses) (3/8)
Abbreviation of Address 00353EH is changed.
(TCCS1 → TCCSL1)
Abbreviation of Address 00353FH is changed.
(TCCS1 → TCCSH1)
615
Table A-2 I/O Map (35XX Addresses) (4/8)
Abbreviation of Address 00354AH is changed.
(WTBR → WTBR(0))
Abbreviation of Address 00354BH is changed.
(WTBR → WTBR(0))
Abbreviation of Address 00354CH is changed.
(WTBR → WTBR(1))
616
Table A-2 I/O Map (35XX Addresses) (5/8)
Register of Address 00356FH is changed.
(CAN RX/TX redirect register → CAN2 RX/TX pin switching register)
Address 0035A9H is changed.
617
Table A-2 I/O Map (35XX Addresses) (6/8)
Address 0035D0H to 0035DFH are changed.
618
Table A-2 I/O Map (35XX Addresses) (7/8)
Register and Peripheral in Address 0035E0H to 0035E5H are changed.
(ROM Correction Address 0 → Program Address Detection Register0)
(ROM Correction Address 1 → Program Address Detection Register1)
(ROM Correction 0 → Address Match Detection 0)
Register and Peripheral in Address 0035F0H to 0035F8H are changed.
(ROM Correction Address 3 → Program Address Detection Register3)
(ROM Correction Address 4 → Program Address Detection Register4)
(ROM Correction Address 5 → Program Address Detection Register5)
(ROM Correction 1 → Address Match Detection 1)
619
Table A-2 I/O Map (35XX Addresses)
*1 and *2 are added.
646
Table B.8-1 41 Transfer Instructions (Byte) is changed.
(MOV @AL,AH / MOV @A,T → MOV @AL,AH)
647
Table B.8-2 38 Transfer Instructions (Byte) is changed.
(MOVW @AL,AH / MOVW @A,T → MOVW @AL,AH)
The vertical lines marked in the left side of the page show the changes.
xxiv
CHAPTER 1
OVERVIEW
The MB90390 Series is a family member of the F2MC16LX microcontrollers.
1.1 Product Overview
1.2 Features
1.3 Block Diagram of MB90V390H
1.4 Block Diagram of MB90V390HA/MB90V390HB
1.5 Block Diagram of MB90394HA/MB90F394H(A)
1.6 Pin Assignment
1.7 Package Dimensions
1.8 Pin Functions
1.9 Input-Output Circuits
1.10 Handling Device
1
CHAPTER 1 OVERVIEW
1.1
Product Overview
Table 1.1-1 lists the product overview.
■ Product Overview
Table 1.1-1 Product Overview
2
Features
MB90V390H
MB90V390HA
MB90V390HB
MB90394HA
MB90F394H(A)
Product type
Evaluation sample
ROM version
Flash version
CPU
F2MC-16LX CPU
System clock
On-chip PLL clock multiplier (×1, ×2, ×3, ×4, ×6, 1/2 when PLL stop)
Minimum instruction execution time: 42 ns (4 MHz osc. PLL×4)
External
ROM memory
384 KBytes
Boot-block
Flash memory
384 KBytes
Hard-wired reset vector.
RAM
MB90V390H: 16 KBytes
MB90V390HA: 30 KBytes
MB90V390HB: 30 KBytes
10 KBytes
10 KBytes
Package
PGA-299
ROM/Flash
memory
LQFP-120
CHAPTER 1 OVERVIEW
1.2
Features
Table 1.2-1 lists the features of the MB90390 series.
■ Features
Table 1.2-1 Features of the MB90390 Series (1/3)
Features
MB90V390H
MB90V390HA
MB90V390HB
MB90394HA
MB90F394H(A)
2 channels
UART
Full duplex double buffer
Supports asynchronous/synchronous (with start/stop bit) transfer
Baud rate: 4808/9615/10417/19230/38460/62500/500000bps (asynchronous)
500k/1M/2Mbps (synchronous) at System clock = 24MHz
UART (SCI / LIN)
2 channels
1 channel (MB90V390H)
I2C (400kbps)
1 channel
Serial I/O
Transfer can be started from MSB or LSB
Supports internal clock synchronized transfer and external clock synchronized transfer
Supports positive-edge and negative-edge clock synchronization
Baud rate: 31.25k/62.5k/125k/500k/1Mbps at System clock = 24MHz
1 channel
-
15 input channels
A/D Converter
10-bit or 8-bit resolution
Conversion time: 4.9 μs (per one channel)
16-bit Reload
Timer
(2 channels)
Operation clock frequency: fsys/21, fsys/23, fsys/25 (fsys = System clock frequency)
Supports External Event Count function
Watch Timer
Directly operates with the oscillation clock
Read/Write accessible Second/Minute/Hour registers
Signals interrupts
16-bit I/O Timer
(2 channels)
Signals an interrupt when overflow
Supports Timer Clear when a match with Output Compare (Ch. 0)
Operation clock freq.: fsys/21, fsys/22, fsys/23, fsys/24, fsys/25, fsys/26, fsys/27 (fsys = System clock
freq.)
I/O Timer 0 (clock input FRCK0) corresponds to ICU0/ICU1, OCU0/OCU1/OCU2/OCU3
I/O Timer 1 (clock input FRCK1) corresponds to ICU2/ICU3/ICU4/ICU5, OCU4/OCU5/OCU6/
OCU7
16-bit Output
Compare
(8 channels)
Signals an interrupt when a match with 16-bit I/O Timer
Eight 16-bit compare registers.
A pair of compare registers can be used to generate an output signal.
OCU6/OCU7 outputs are shared with ICU3/ICU5 inputs
3
CHAPTER 1 OVERVIEW
Table 1.2-1 Features of the MB90390 Series (2/3)
Features
MB90V390H
MB90V390HA
MB90V390HB
MB90F394H(A)
16-bit Input
Capture
(6 channels)
Rising edge, falling edge or rising & falling edge sensitive
Six 16-bit Capture registers
Signals an interrupt upon external event
ICU3/ICU5 inputs are shared with OCU6/OCU7 outputs
8/16-bit
Programmable
Pulse Generator
(6 channels)
Supports 8-bit and 16-bit operation modes
Twelve 8-bit reload counters
Twelve 8-bit reload registers for "L" pulse width
Twelve 8-bit reload registers for "H" pulse width
A pair of 8-bit reload counters can be configured as one 16-bit reload counter or as 8-bit prescaler
plus 8-bit reload counter
Operation clock freq.: fsys/21, fsys/22, fsys/23, fsys/24 or [email protected]=5MHz
(fsys = System clock frequency, fosc = Oscillation clock frequency)
5 channels
CAN Interface
4
MB90394HA
2 channels
Conforms to CAN Specification Version 2.0 Part A and B
Automatic re-transmission in case of error
Automatic transmission responding to Remote Frame
Prioritized 16 message buffers for data and ID’s
Supports multiple messages
Flexible configuration of acceptance filtering:
Full bit compare / Full bit mask / Two partial bit masks
Supports up to 1Mbps
Stepper Motor
Controller
(6 channels)
Four high current outputs with controlled slew rate for each channel
Synchronized two 8-bit PWM’s for each channel
External Interrupt
(8 channels)
Can be programmed edge sensitive or level sensitive
Sound Generator
8-bit PWM signal is mixed with tone frequency from 8-bit reload counter
PWM frequency: 62.5kHz, 31.2kHz, 15.6kHz, 7.8kHz at System clock = 16MHz
Tone frequency: PWM frequency / 2 / (reload value + 1)
I/O Ports
Virtually all external pins can be used as general purpose I/O
All push-pull outputs
Bit-wise programmable as input/output or peripheral signal
Port-wise programmable as CMOS Hysteresis or Automotive Hysteresis input (default)
Clock Modulator
Spread spectrum clock modulator for reducing electromagnetic emissions.
Frequency and Phase Modulation modes.
MB90F394H: do not use frequency modulation!
MB90F394H, MB90V390H, and MB90V390HA:
Do not use CAN message buffer RAM and clock modulator at the same time!
CHAPTER 1 OVERVIEW
Table 1.2-1 Features of the MB90390 Series (3/3)
Features
Flash Memory
MB90V390H
MB90V390HA
MB90V390HB
MB90394HA
-
MB90F394H(A)
Supports automatic programming,
Embedded Algorithm Write/Erase/
Erase-Suspend/Resume commands.
A flag indicating completion of the
algorithm
Number of erase cycles: 10,000 times.
Data retention time: 20 years *
Hard-wired reset vector available in
order to point to a fixed boot sector in
Flash Memory.
Boot block configuration.
Erase can be performed on each block.
Block protection with external
programming voltage
*: This value comes from the technology qualification (using Arrehenius equation to translate high temperature
measurements into normalized value at +85 °C).
5
CHAPTER 1 OVERVIEW
1.3
Block Diagram of MB90V390H
Figure 1.3-1 shows a block diagram of the MB90V390H.
■ Block Diagram of MB90V390H
Figure 1.3-1 Block Diagram of MB90V390H
X0,X1
RST
Clock
Controller
16LX
CPU
IO Timer0
FRCK0
Input
Capture
6ch
IN[5:0]
Output
Compare
8ch
OUT[7:0]
Prescaler x4*
IO Timer1
FRCK1
UART 4*ch
8/16-bit
PPG
6ch
SOT[3*:0]
SCK[3*:0]
SIN[3*:0]
Prescaler
SOT4
SCK4
SIN4
AVcc
AVss
AN[14:0]
AVRH
AVRL
ADTG
TIN[1:0]
TOT[1:0]
WOT
Serial I/O
F2MC-16LX bus
RAM
16KBytes
PPG0[5:0]
PPG1[5:0]
CAN
5*ch
RX[4:0]
TX[4:0]
SMC
6ch
PWM1M[5:0]
PWM1P[5:0]
PWM2M[5:0]
PWM2P[5:0]
DVcc[3:0]
DVss[3:0]
10-bit A/D
converter
15ch
External
Interrupt
INT[7:0]
16-bit Reload
Timer 2ch
Sound
Generator
SGO
SGA
I2C
Interface*
SDA*
SCL*
Watch
Timer
*: Not available on all MB90390 devices
6
CHAPTER 1 OVERVIEW
1.4
Block Diagram of MB90V390HA/MB90V390HB
Figure 1.4-1 shows a block diagram of the MB90V390HA/MB90V390HB devices.
■ Block Diagram of MB90V390HA/MB90V390HB
Figure 1.4-1 Block Diagram of MB90V390HA/MB90V390HB
X0,X1
RST
Clock
Controller
16LX
CPU
IO Timer0
FRCK0
Input
Capture
6ch
IN[5:0]
Output
Compare
8ch
OUT[7:0]
Prescaler x4*
IO Timer1
FRCK1
UART 4*ch
8/16-bit
PPG
6ch
SOT[3*:0]
SCK[3*:0]
SIN[3*:0]
Prescaler
SOT4
SCK4
SIN4
AVcc
AVss
AN[14:0]
AVRH
AVRL
ADTG
TIN[1:0]
TOT[1:0]
WOT
Serial I/O
F2MC-16LX bus
RAM
30KBytes
PPG0[5:0]
PPG1[5:0]
CAN
5*ch
RX[4:0]
TX[4:0]
SMC
6ch
PWM1M[5:0]
PWM1P[5:0]
PWM2M[5:0]
PWM2P[5:0]
DVcc[3:0]
DVss[3:0]
10-bit A/D
converter
15ch
External
Interrupt
INT[7:0]
16-bit Reload
Timer 2ch
Sound
Generator
SGO
SGA
I2C
Interface*
SDA*
SCL*
Watch
Timer
*: Not available on all MB90390 devices
7
CHAPTER 1 OVERVIEW
1.5
Block Diagram of MB90394HA/MB90F394H(A)
Figure 1.5-1 shows a block diagram of the MB90394HA/MB90F394H(A) devices.
■ Block Diagram of MB90394HA/MB90F394H(A)
Figure 1.5-1 Block Diagram of MB90394HA/MB90F394H(A)
X0,X1
RST
Clock
Controller
16LX
CPU
IO Timer0
FRCK0
Input
Capture
6ch
IN[5:0]
ROM/Flash
384KBytes
Output
Compare
8ch
OUT[7:0]
Prescaler x3
IO Timer1
FRCK1
UART 3ch
8/16-bit
PPG
6ch
SOT[3,1,0]
SCK[3,1,0]
SIN[3,1,0]
Prescaler
SOT4
SCK4
SIN4
AVcc
AVss
AN[14:0]
AVRH
AVRL
ADTG
TIN[1:0]
TOT[1:0]
WOT
Serial I/O
F2MC-16LX bus
RAM
10KBytes
PPG0[5:0]
PPG1[5:0]
CAN
2ch
RX[1:0]
TX[1:0]
SMC
6ch
PWM1M[5:0]
PWM1P[5:0]
PWM2M[5:0]
PWM2P[5:0]
DVcc[3:0]
DVss[3:0]
10-bit A/D
converter
15ch
External
Interrupt
INT[7:0]
16-bit Reload
Timer 2ch
Watch
Timer
Sound
Generator
SGO
SGA
I2C
Interface*
SDA
SCL
*: I2C interface is not available on MB90F394H(A)
8
CHAPTER 1 OVERVIEW
1.6
Pin Assignment
This chapter shows the pin assignments for the MB90390 series.
■ Pin Assignment of MB90V390H
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
1
90
2
89
3
88
4
87
5
86
6
85
7
84
8
83
9
82
81
10
11
80
MB90V390H
Pin Assignment
12
13
79
78
14
77
15
76
16
75
17
74
18
73
72
19
20
71
As seen with LQFP-120 probe cable
21
70
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
RST
MD0
MD1
MD2
DVSS
DVCC
PA7/PWM2M5
PA6/PWM2P5
PA5/PWM1M5
PA4/PWM1P5
PA3/PWM2M4
PA2/PWM2P4
PA1/PWM1M4
PA0/PWM1P4
DVSS
DVCC
P87/PWM2M3
P86/PWM2P3
P85/PWM1M3
P84/PWM1P3
P83/PWM2M2
P82/PWM2P2
P81/PWM1M2
P80/PWM1P2
DVSS
DVCC
P77/PWM2M1
P76/PWM2P1
P75/PWM1M1
P74/PWM1P1
P93/SIN3
P94/SCK3
P95/SOT3
P96/WOT
AVCC
AVRH
AVRL
AVSS
P60/AN0
P61/AN1
P62/AN2
P63/AN3
P64/AN4
P65/AN5
P66/AN6
P67/AN7
VSS
PB0/PPG02/TX3/AN8
PB1/PPG03/RX3/AN9
PB2/PPG04/TX4/AN10
PB3/PPG05/RX4/AN11
PB4/SIN4/AN12
PB5/SCK4/AN13
PB6/SOT4/AN14
DVCC
DVSS
P70/PWM1P0
P71/PWM1M0
P72/PWM2P0
P73/PWM2M0
41
61
40
62
30
39
63
29
38
64
28
37
65
27
36
66
26
35
67
25
34
68
24
33
69
23
32
22
31
P30/RX0
P31/TX0
P32/TIN1
P33/TOT1
P34/SOT0
P35/SCK0
P36/SIN0
P37/SIN1
P40/SCK1
P41/SOT1
P42/SDA
P43/SCL
P44
P45/ADTG
VCC
VSS
C
P46/INT0
P47/INT1
P50/PPG10
P51/PPG11
P52/PPG12
P53/PPG13
P54/PPG14
P55/PPG15
P56/PPG00/RX2
P57/PPG01/TX2
P90/SIN2
P91/SCK2
P92/SOT2
119
120
P27/INT7
P26/INT6
P25/INT5
P24/INT4
P23/INT3
P22/INT2
P21/RX1
P20/TX1
P17/SGA
P16/SGO
P15/TOT0
P14/TIN0
X0
X1
VSS
VCC
P13/OUT5
P12/OUT4
P11/OUT3
P10/OUT2
P07/OUT1
P06/OUT0
P05/IN5/OUT7
P04/IN4
P03/IN3/OUT6
P02/IN2
P01/IN1
P00/IN0
P97/FRCK1/HCLKX
PB7/FRCK0/HCLK
Figure 1.6-1 Pin Assignment of MB90V390H
Note:
In other devices of the MB90390 series some pin functions are not available.
9
CHAPTER 1 OVERVIEW
■ Pin Assignment of MB90V390HA/MB90V390HB
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
1
90
2
89
3
88
4
87
5
86
6
85
7
84
8
83
9
82
81
10
11
80
MB90V390HA/HB
Pin Assignment
12
13
79
78
14
77
15
76
16
75
17
74
18
73
72
19
20
71
As seen with LQFP-120 probe cable
21
70
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
P93/SIN3
P94/SCK3
P95/SOT3
P96/WOT
AVCC
AVRH
AVRL
AVSS
P60/AN0
P61/AN1
P62/AN2
P63/AN3
P64/AN4
P65/AN5
P66/AN6
P67/AN7
VSS
PB0/PPG02/TX3/AN8
PB1/PPG03/RX3/AN9
PB2/PPG04/TX4/AN10
PB3/PPG05/RX4/AN11
PB4/SIN4/AN12
PB5/SCK4/AN13
PB6/SOT4/AN14
DVCC
DVSS
P70/PWM1P0
P71/PWM1M0
P72/PWM2P0
P73/PWM2M0
41
61
40
62
30
39
63
29
38
64
28
37
65
27
36
66
26
35
67
25
34
68
24
33
69
23
32
22
31
P30/RX0
P31/TX0
P32/TIN1
P33/TOT1
P34/SOT0
P35/SCK0
P36/SIN0
P37/SIN1
P40/SCK1
P41/SOT1
P42/SDA
P43/SCL
P44
P45/ADTG
VCC
VSS
C
P46/INT0
P47/INT1
P50/PPG10
P51/PPG11
P52/PPG12
P53/PPG13
P54/PPG14
P55/PPG15
P56/PPG00/RX2
P57/PPG01/TX2
P90/SIN2
P91/SCK2
P92/SOT2
119
120
P27/INT7
P26/INT6
P25/INT5
P24/INT4
P23/INT3
P22/INT2
P21/RX1
P20/TX1
P17/SGA
P16/SGO
P15/TOT0
P14/TIN0
X0
X1
VSS
VCC
P13/OUT5
P12/OUT4
P11/OUT3
P10/OUT2
P07/OUT1
P06/OUT0
P05/IN5/OUT7
P04/IN4
P03/IN3/OUT6
P02/IN2
P01/IN1
P00/IN0
P97/FRCK1/HCLKX
PB7/FRCK0/HCLK
Figure 1.6-2 Pin Assignment of MB90V390HA/MB90V390HB
Note:
In other devices of the MB90V390H series some pin functions are not available.
10
RST
MD0
MD1
MD2
DVSS
DVCC
PA7/PWM2M5
PA6/PWM2P5
PA5/PWM1M5
PA4/PWM1P5
PA3/PWM2M4
PA2/PWM2P4
PA1/PWM1M4
PA0/PWM1P4
DVSS
DVCC
P87/PWM2M3
P86/PWM2P3
P85/PWM1M3
P84/PWM1P3
P83/PWM2M2
P82/PWM2P2
P81/PWM1M2
P80/PWM1P2
DVSS
DVCC
P77/PWM2M1
P76/PWM2P1
P75/PWM1M1
P74/PWM1P1
CHAPTER 1 OVERVIEW
■ Pin Assignment of MB90394HA/MB90F394H(A)
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
1
90
2
89
3
88
4
87
5
86
6
85
7
84
8
83
9
82
81
10
11
80
MB90394HA/MB90F394H(A)
Pin Assignment
12
13
79
78
14
77
15
76
16
75
17
74
18
73
72
19
20
71
LQFP-120
21
70
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
RST
MD0
MD1
MD2
DVSS
DVCC
PA7/PWM2M5
PA6/PWM2P5
PA5/PWM1M5
PA4/PWM1P5
PA3/PWM2M4
PA2/PWM2P4
PA1/PWM1M4
PA0/PWM1P4
DVSS
DVCC
P87/PWM2M3
P86/PWM2P3
P85/PWM1M3
P84/PWM1P3
P83/PWM2M2
P82/PWM2P2
P81/PWM1M2
P80/PWM1P2
DVSS
DVCC
P77/PWM2M1
P76/PWM2P1
P75/PWM1M1
P74/PWM1P1
P93/SIN3
P94/SCK3
P95/SOT3
P96/WOT
AVCC
AVRH
AVRL
AVSS
P60/AN0
P61/AN1
P62/AN2
P63/AN3
P64/AN4
P65/AN5
P66/AN6
P67/AN7
VSS
PB0/PPG02/TX3/AN8
PB1/PPG03/RX3/AN9
PB2/PPG04/TX4/AN10
PB3/PPG05/RX4/AN11
PB4/SIN4/AN12
PB5/SCK4/AN13
PB6/SOT4/AN14
DVCC
DVSS
P70/PWM1P0
P71/PWM1M0
P72/PWM2P0
P73/PWM2M0
41
61
40
62
30
39
63
29
38
64
28
37
65
27
36
66
26
35
67
25
34
68
24
33
69
23
32
22
31
P30/RX0
P31/TX0
P32/TIN1
P33/TOT1
P34/SOT0
P35/SCK0
P36/SIN0
P37/SIN1
P40/SCK1
P41/SOT1
P42/SDA*
P43/SCL*
P44
P45/ADTG
VCC
VSS
C
P46/INT0
P47/INT1
P50/PPG10
P51/PPG11
P52/PPG12
P53/PPG13
P54/PPG14
P55/PPG15
P56/PPG00/RX2
P57/PPG01/TX2
P90/SIN2
P91/SCK2
P92/SOT2
119
120
P27/INT7
P26/INT6
P25/INT5
P24/INT4
P23/INT3
P22/INT2
P21/RX1
P20/TX1
P17/SGA
P16/SGO
P15/TOT0
P14/TIN0
X0
X1
VSS
VCC
P13/OUT5
P12/OUT4
P11/OUT3
P10/OUT2
P07/OUT1
P06/OUT0
P05/IN5/OUT7
P04/IN4
P03/IN3/OUT6
P02/IN2
P01/IN1
P00/IN0
P97/FRCK1/HCLKX
PB7/FRCK0/HCLK
Figure 1.6-3 Pin Assignment of MB90394HA/MB90F394H(A)
*: I2C is not available in MB90F394H(A).
11
CHAPTER 1 OVERVIEW
1.7
Package Dimensions
Figure 1.7-1 shows the package dimensions.
Note that the dimensions shown below are reference dimensions. For formal
dimensions of each package, contact us.
■ Package Dimensions
Figure 1.7-1 Package Dimensions
120-pin plastic LQFP
Lead pitch
0.50 mm
Package width ×
package length
16.0 × 16.0 mm
Lead shape
Gullwing
Sealing method
Plastic mold
M ounting height
1.70 mm MAX
Weight
0.88 g
Code
(Reference)
P-LFQFP120-16×16-0.50
(FPT-120P-M21)
120-pin plastic LQFP
(FPT-120P-M21)
Note 1) * : These dimensions do not include resin protrusion.
Resin protrusion is +0.25(.010) MAX(each side).
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
18.00±0.20(.709±.008)SQ
+0.40
* 16.00 –0.10 .630 +.016
–.004 SQ
90
61
91
60
0.08(.003)
Details of "A" part
+0.20
1.50 –0.10
+.008
(Mounting height)
.059 –.004
INDEX
0~8°
120
LEAD No.
1
30
0.50(.020)
C
"A"
31
2002 FUJITSU LIMITED F120033S-c-4-4
0.22±0.05
(.009±.002)
0.08(.003)
M
0.145
.006
+0.05
–0.03
+.002
–.001
0.60±0.15
(.024±.006)
0.25(.010)
Dimensions in mm (inches).
Note: The values in parentheses are ref erence values.
Please confirm the latest Package dimension by following URL.
http://edevice.fujitsu.com/fj/DATASHEET/ef-ovpklv.html
12
0.10±0.05
(.004±.002)
(Stand off)
CHAPTER 1 OVERVIEW
1.8
Pin Functions
Table 1.8-1 lists the pin description.
■ Pin Functions
Table 1.8-1 Pin Description (1/6)
Pin No.
Pin name
107
X1
Circuit type
Function
Oscillation output
A
108
X0
90
RST
Oscillation input
B
P00 to P02
93 to 95
General purpose I/O
D
IN0 to IN2
Inputs for the Input Captures 0 to 2
P03
96
IN3
General purpose I/O
D
OUT6
Input for the Input Capture 3
Output for the Output Compare 6
P04
97
98
Reset input
General purpose I/O
D
IN4
Input for the Input Capture 4
P05
General purpose I/O
IN5
D
OUT7
Output for the Output Compare 7
P06 to P07
P10 to P13
99 to 104
Input for the Input Capture 5
General purpose I/O
D
OUT0 to
OUT5
Outputs for the Output Compares
P14
109
General purpose I/O
D
TIN0
TIN0 input for the 16-bit Reload Timer 0
P15
110
General purpose I/O
D
TOT0
TOT0 output for the 16-bit Reload Timer 0
P16
111
General purpose I/O
D
SGO
SGO output for the Sound Generator
P17
112
General purpose I/O
D
SGA
SGA output for the Sound Generator
13
CHAPTER 1 OVERVIEW
Table 1.8-1 Pin Description (2/6)
Pin No.
Pin name
Circuit type
P20
113
General purpose I/O
D
TX1
TX output for CAN Interface 1
P21
114
General purpose I/O
D
RX1
RX input for CAN Interface 1
P22 to P27
115 to 120
General purpose I/O
D
INT2 to INT7
External interrupt inputs for INT2 to INT7
P30
1
General purpose I/O
D
RX0
RX input for CAN Interface 0
P31
2
General purpose I/O
D
TX0
TX output for CAN Interface 0
P32
3
General purpose I/O
D
TIN1
TIN1 input for the 16-bit Reload Timer 1
P33
4
General purpose I/O
D
TOT1
TOT1 output for the 16-bit Reload Timer 1
P34
5
General purpose I/O
D
SOT0
SOT output for UART0
P35
6
General purpose I/O
D
SCK0
SCK input/output for UART0
P36
7
General purpose I/O
D
SIN0
SIN input for UART0
P37
8
General purpose I/O
D
SIN1
SIN input for UART1
P40
9
General purpose I/O
D
SCK1
SCK input/output for UART1
P41
10
General purpose I/O
D
SOT1
SOT output for UART1
P42
11
SDA *
General purpose I/O
D
P43
12
13
14
Function
SCL *
P44
Serial data for I2C interface
General purpose I/O
D
D
Serial clock for I2C interface
General purpose I/O
CHAPTER 1 OVERVIEW
Table 1.8-1 Pin Description (3/6)
Pin No.
Pin name
Circuit type
P45
14
General purpose I/O
D
ADTG
External trigger input of the A/D Converter
P46, P47
18, 19
20 to 25
General purpose I/O
D
INT0, INT1
External interrupt inputs for INT0, INT1
P50 to P55
General purpose I/O
PPG10 to
PPG15
D
Outputs for the Programmable Pulse Generators
P56
26
PPG00
General purpose I/O
D
RX2 *
PPG01
General purpose I/O
D
TX2 *
SIN2 *
General purpose I/O
D
SIN input for UART2
P91
29
SCK2 *
General purpose I/O
D
SCK input/output for UART2
P92
30
SOT2 *
General purpose I/O
D
SOT output for UART2
P93
31
Output for the Programmable Pulse Generator 1
TX output for CAN Interface 2
P90
28
Output for the Programmable Pulse Generator 0
RX input for CAN Interface 2
P57
27
Function
General purpose I/O
D
SIN3
SIN input for UART3 (High Speed UART)
P94
32
General purpose I/O
D
SCK3
SCK input/output for UART3 (High Speed UART)
P95
33
General purpose I/O
D
SOT3
SOT output for UART3 (High Speed UART)
P96
34
General purpose I/O
D
WOT
WOT output for the Watch Timer
P60 to P67
39 to 46
General purpose I/O
E
AN0 to AN7
Inputs for the A/D Converter
15
CHAPTER 1 OVERVIEW
Table 1.8-1 Pin Description (4/6)
Pin No.
Pin name
Circuit type
PB0
General purpose I/O
PPG02
48
TX3 *
Output for the Programmable Pulse Generator 2
E
TX output for CAN Interface 3
AN8
Input for the A/D Converter
PB1
General purpose I/O
PPG03
49
RX3 *
Output for the Programmable Pulse Generator 3
E
RX input for CAN Interface 3
AN9
Input for the A/D Converter
PB2
General purpose I/O
PPG04
50
TX4 *
Output for the Programmable Pulse Generator 4
E
TX output for CAN Interface 4
AN10
Input for the A/D Converter
PB3
General purpose I/O
PPG05
51
RX4 *
Output for the Programmable Pulse Generator 5
E
RX input for CAN Interface 4
AN11
Input for the A/D Converter
PB4
52
SIN4
General purpose I/O
E
AN12
SCK4
General purpose I/O
E
AN13
SOT4
General purpose I/O
E
AN14
16
PWM1P0
PWM1M0
PWM2P0
PWM2M0
SOT output for the Serial I/O
Input for the A/D Converter
P70 to P73
57 to 60
SCK input/output for the Serial I/O
Input for the A/D Converter
PB6
54
SIN input for the Serial I/O
Input for the A/D Converter
PB5
53
Function
General purpose I/O
F
Output for Stepping Motor Controller ch. 0
CHAPTER 1 OVERVIEW
Table 1.8-1 Pin Description (5/6)
Pin No.
Pin name
Circuit type
P74 to P77
61 to 64
PWM1P1
PWM1M1
PWM2P1
PWM2M1
General purpose I/O
F
Output for Stepping Motor Controller ch. 1
P80 to P83
67 to 70
PWM1P2
PWM1M2
PWM2P2
PWM2M2
General purpose I/O
F
Output for Stepping Motor Controller ch. 2
P84 to P87
71 to 74
PWM1P3
PWM1M3
PWM2P3
PWM2M3
General purpose I/O
F
Output for Stepping Motor Controller ch. 3
PA0 to PA3
77 to 80
PWM1P4
PWM1M4
PWM2P4
PWM2M4
General purpose I/O
F
Output for Stepping Motor Controller ch. 4
PA4 to PA7
81 to 84
PWM1P5
PWM1M5
PWM2P5
PWM2M5
General purpose I/O
F
Output for Stepping Motor Controller ch. 5
PB7
91
FRCK0
General purpose I/O
D
HCLK
FRCK1
FRCK0 input for the 16-bit I/O Timer 0
Oscillation Clock output
P97
92
Function
General purpose I/O
D
HCLKX
FRCK1 input for the 16-bit I/O Timer 1
Inverted Oscillation Clock output
55,
65,
75,
85
DVCC
-
Dedicated power supply pins for the high current output buffers
(Pin No. 57 to 84)
56,
66,
76,
86
DVSS
-
Dedicated ground pins for the high current output buffers
(Pin No. 57 to 84)
17
CHAPTER 1 OVERVIEW
Table 1.8-1 Pin Description (6/6)
Pin No.
Pin name
Circuit type
Function
35
AVCC
-
Dedicated power supply pin (5V) for the A/D converter
36
AVRH
-
Dedicated pos. reference voltage pin for the A/D converter
37
AVRL
-
Dedicated neg. reference voltage pin for the A/D converter
38
AVSS
-
Dedicated power supply pin (0V) for the A/D converter
88, 89
MD1, MD0
C
These are input pins used to designate the operating mode. They should
be connected directly to VCC or VSS.
87
MD2
G
This is an input pin used to designate the operating mode. It should be
connected directly to VCC or VSS.
15,
105
VCC
-
These are power supply (5V) input pins
16,
47,
106
VSS
-
These are power supply (0V) input pins
17
C
-
This is the power supply stabilization capacitor pin. It should be
connected to a 0.1 μF or more ceramic capacitor.
*: Pin function may not be available in some devices of the MB90390 series.
18
CHAPTER 1 OVERVIEW
1.9
Input-Output Circuits
Table 1.9-1 lists the input-output circuits.
■ Input-output Circuits
Table 1.9-1 I/O Circuit Types (1/3)
Type
Circuit
Remarks
A
• Oscillation feedback resistor: 1 MΩ approx.
X1
Clock input
P-ch
N-ch
X0
Standby control signal
B
•
VCC
CMOS Hysteresis input with pull-up resistor
(50 kΩ approx.).
R(pull-up)
R
CMOS HYS
C
R
CMOS HYS
• EVA device: CMOS Hysteresis input
• Flash device: CMOS input
19
CHAPTER 1 OVERVIEW
Table 1.9-1 I/O Circuit Types (2/3)
Type
Circuit
Remarks
D
• CMOS output
• CMOS Hysteresis input
• Automotive Hysteresis input
VCC
P-ch
Note: The input characteristics may be different for
different pins/devices. Refer to the data sheet.
N-ch
R
CMOS Hysteresis
R
Automotive HYS
E
•
•
•
•
VCC
CMOS output
CMOS Hysteresis input
Automotive Hysteresis input
Analog input
P-ch
Note: The input characteristics may be different for
different pins/devices. Refer to the data sheet.
N-ch
P-ch
Analog input
N-ch
R
CMOS Hysteresis
R
Automotive HYS
20
CHAPTER 1 OVERVIEW
Table 1.9-1 I/O Circuit Types (3/3)
Type
Circuit
Remarks
F
• CMOS high current output
• CMOS Hysteresis input
• Automotive Hysteresis input
VCC
P-ch
High current
N-ch
R
CMOS Hysteresis
R
Automotive HYS
G
R
CMOS Hysteresis
• EVA device: CMOS Hysteresis input with pulldown resistor (50 kΩ approx.).
• Flash device: CMOS input without pull-down.
R(pull-down)
21
CHAPTER 1 OVERVIEW
1.10
Handling Device
Special care is required for the following when handling the device:
• Preventing latch-up
• Treatment of unused pins
• Stabilization of power supply voltage
• Using external clock
• Power supply input pins (VCC/VSS)
•
•
•
•
•
•
Pull-up/pull-down resistors
Crystal Oscillator Circuit
Turning-on Sequence of Power Supply to A/D Converter and Analog Inputs
Connection of Unused Pins of A/D Converter if A/D Converter is unused
Precautions at power on
Note on operation during PLL clock mode
■ Handling the Device
● Preventing latch-up
CMOS IC chips may suffer latch-up under the following conditions:
• A voltage higher than VCC or lower than VSS is applied to an input or output pin.
• A voltage higher than the rated voltage is applied between VCC and VSS.
• The AVCC power supply is applied before the VCC voltage.
Latch-up may increase the power supply current drastically, causing thermal damage to the device.
Therefore, the maximum voltage ratings must not be exceeded. By the same token, make sure that the
analog supply voltage (AVCC and AVRH) should not exceed the digital supply voltage.
● Treatment of unused pins
Leaving unused input pins open may result in misbehavior or latch up and possible permanent damage of
the device. Therefore they must be pulled up or pulled down through resistors. In this case those resistors
should be more than 2 kΩ. Unused bidirectional pins should be set to the output state and can be left open,
or the input state with the above described connection.
● Stabilization of power supply voltage
If the power supply voltage varies acutely even within the operation assurance range of the VCC power
supply voltage, a malfunction may occur. The VCC power supply voltage must therefore be stabilized.
As stabilization guidelines, stabilize the power supply voltage so that VCC ripple fluctuations (peak to peak
value) in the commercial frequencies (50 Hz to 60 Hz) fall within 10% of the standard VCC power supply
voltage and the transient fluctuation rate becomes 0.1V/ms or less in instantaneous fluctuation for power
supply switching.
22
CHAPTER 1 OVERVIEW
● Using external clock
To use external clock, drive the X0 pin and leave X1 pin open.
Figure 1.10-1 is a diagram of how to use external clock.
Figure 1.10-1 Using External Clock
MB90390 Series
MB90590
Series
X0
Open
X1
● Power supply input pins (VCC/VSS)
• If there are multiple VCC and VSS pins, from the point of view of device design, pins to be of the same
potential are connected the inside of the device to prevent such malfunctioning as latch-up.
To reduce unnecessary radiation, prevent malfunctioning of the strobe signal due to the rise of ground
level, and keep the total output current standard, be sure to connect the VCC and VSS pins to the power
supply and ground externally.
• Connect VCC and VSS to the device from the power supply source with lowest possible impedance.
• To prevent power supply noise, connect a capacitor of about 0.1 μF as a bypass capacitor between VCC
and VSS in the vicinity of VCC and VSS pins of the device.
Figure 1.10-2 Power Supply input Pins (VCC/VSS)
Vcc
Vss
Vcc
Vss
Vss
Vcc
MB90390
Series
Vcc
Vss
Vss
Vcc
● Pull-up/pull-down resistors
The MB90390 Series does not support internal pull-up/pull-down resistors option. Use external components
where needed.
23
CHAPTER 1 OVERVIEW
● Crystal Oscillator Circuit
Noises around X0 or X1 pins may be possible causes of abnormal operations. Make sure to provide bypass
capacitors via shortest distance from X0, X1 pins, crystal oscillator (or ceramic resonator) and ground lines,
and make sure, to the utmost effort, that lines of oscillation circuit not cross the lines of other circuits.
It is highly recommended to provide a printed circuit board art work surrounding X0 and X1 pins with a
ground area for stabilizing the operation. Please ask the crystal maker to evaluate the oscillational
characteristics of the crystal and this device.
● Turning-on Sequence of Power Supply to A/D Converter and Analog Inputs
Make sure to turn on the A/D converter power supply (AVCC, AVRH, AVRL) and analog inputs (AN0 to
AN14) after turning-on the digital power supply (VCC). Turn-off the digital power after turning off the A/D
converter supply and analog inputs. In this case, make sure that the voltage not exceed AVRH or AVCC.
● Connection of Unused Pins of A/D Converter if A/D Converter is unused
Connect unused pins of A/D converter to AVCC = VCC, AVSS = AVRH = AVRL = VSS.
● Precautions at power on
To prevent a malfunction of the internal step-down circuit, the voltage rise time at power-on should be 50
μs or more (between 0.2 V and 2.7 V).
● Note on operation during PLL clock mode
On this microcontroller, if in case the crystal oscillator breaks off or an external reference clock input stops
while the PLL clock mode is selected, a self-oscillator circuit contained in the PLL may continue its
operation at its self-running frequency. However, Fujitsu will not guarantee results of operations if such
failure occurs.
24
CHAPTER 2
CPU
This chapter explains the CPU.
2.1 Outline of the CPU
2.2 Memory Space
2.3 Memory Space Map
2.4 Linear Addressing
2.5 Bank Addressing Types
2.6 Multi-byte Data in Memory Space
2.7 Registers
2.8 Register Bank
2.9 Prefix Codes
2.10 Interrupt Disable Instructions
2.11 Precautions for Use of "DIV A, Ri" and "DIVW A, RWi" Instructions
25
CHAPTER 2 CPU
2.1
Outline of the CPU
The F2MC-16LX CPU core is a 16-bit CPU designed for applications that require highspeed real-time processing, such as home-use or vehicle-mounted electronic
appliances. The F2MC-16LX instruction set is designed for controller applications, and
is capable of high-speed, highly efficient control processing.
■ Outline of the CPU
In addition to 16-bit data, the F2MC-16LX CPU core can process 32-bit data by using an internal 32-bit
accumulator. (32-bit data can be processed with some instructions.) Up to 16 Mbytes of memory space
(expandable) can be used, which can be accessed by either the linear pointer or bank method. The
instruction system, based on the F2MC-8 A-T architecture, has been reinforced by adding instructions
compatible with high-level languages, expanding addressing modes, reinforcing multiplication and division
instructions, and enhancing bit processing. The features of the F2MC-16LX CPU are explained below.
● Minimum instruction execution time: 42 ns (at 4-MHz oscillation, 6 times clock multiplication)
● Maximum memory space: 16 Mbytes, accessed in linear or bank mode
● Instruction set optimized for controller applications
• Rich data types: Bit, byte, word, long word
• Extended addressing modes: 23 types
• High-precision operation (32-bit length) based on 32-bit accumulator
● Powerful interrupt functions
Eight priority levels (programmable)
● CPU-independent automatic transfer
Up to 16 channels of the extended intelligent I/O service
● Instruction set compatible with high-level language (C)/multitasking
System stack pointer/instruction set symmetry/barrel-shift instructions
● Improved execution speed: 4-byte queue
26
CHAPTER 2 CPU
2.2
Memory Space
An F2MC-16LX CPU has a 16-Mbyte memory space. All data program input and output
managed by the F2MC-16LX CPU are located in this 16-Mbyte memory space. The CPU
accesses the resources by indicating their addresses using a 24-bit address bus.
■ Outline of CPU Memory Space
All I/O, programs and data are located in the 16-megabyte memory space of the F2MC-16LX CPU. The
CPU is able to access each resource through an address indicated by the 24-bit address bus.
Figure 2.2-1 shows a sample relationship between the F2MC-16LX system and memory map.
Figure 2.2-1 Sample Relationship between F2MC-16LX System and Memory
F2MC-16LX device
FFFFFFH
FFFC00H
Programs
FF0000H *1
100000H
010000H
008000 / 004000H *2
Vector table area
Program area
ROM area
External area *4
ROM Mirror area
(FF bank image)
External area *4
F2MC-16LX
CPU
Internal Bus
020000H
000D00H *3
Data
EI2OS
000380H
000180H
000100H
Data Area
General-Purpose Register
EI2OS
Descriptor area
RAM area
External area *4
0000C0H
Interrupts
0000B0H
Peripheral circuits
000020H
General-purpose
ports
000000H
Interrupt Control
Register Area
Peripheral Function
Control Register Area
I/O Port Control
Register Area
I/O area
*1: The size of the built-in ROM differs for each model.
*2: The area accessible by the image differs for each model
(see “CHAPTER27 ROM MIRRORING MODULE”).
*3: The size of the built-in RAM differs for each model.
*4: Access is not possible in single-chip mode.
27
CHAPTER 2 CPU
■ ROM Area
● Vector table area (address: FFFC00H to FFFFFFH)
This area is used as a vector table for vector call instructions, interrupt vectors, and reset vectors.
This area is allocated at the highest addresses of the ROM area. The start address of the corresponding
processing routine is set as data in each vector table address.
● Program area (address: Up to FFFBFFH)
ROM is built in as an internal program area.
The size of built-in ROM differs for each model.
■ RAM Area
● Data area (address: From 000100H to 0010FFH (for 4KByte))
The static RAM is built in as an internal data area.
The size of built-in RAM differs for each model.
● General-purpose register area (address: 000180H to 00037FH)
Auxiliary registers used for 8-bit, 16-bit, and 32-bit arithmetic operations and transfer are allocated in this
area.
Since this area is allocated to a part of the RAM area, it can be used as ordinary RAM.
When this area is used as a general-purpose register, general-purpose register addressing enables highspeed access with short instructions.
● Extended intelligent I/O service (EI2OS) descriptor area (address: 000100H to 00017FH)
This area retains the transfer modes, I/O addresses, transfer count, and buffer addresses.
Since this area is allocated to a part of the RAM area, it can be used as ordinary RAM.
■ I/O Area
● Interrupt control register area (address: 0000B0H to 0000BFH)
The interrupt control registers (ICR00 to ICR15) correspond to all peripheral functions that have an
interrupt function. These registers set interrupt levels and control the extended intelligent I/O service
(EI2OS).
● Peripheral function control register area (address: 000020H to 0000AFH)
This register controls the built-in peripheral functions and inputs and outputs data.
● I/O port control register area (address: 000000H to 00001FH)
This register controls I/O ports, and inputs and outputs data.
28
CHAPTER 2 CPU
■ Address Generation Types
The F2MC-16LX has the following two addressing modes:
● Linear addressing
An entire 24-bit address is specified by an instruction.
● This register Bank addressing.
The eight high-order bits of an address are specified by an appropriate bank register, and the remaining 16
low-order bits are specified by an instruction.
29
CHAPTER 2 CPU
2.3
Memory Space Map
The memory space of the MB90390 Series is shown in Figure 2.3-1.
■ Memory Space Map
The ROM data in the high-order portion of FF-bank can be seen as an image in the higher 00-bank in order
to support the small model C compiler. Since the low-order 16 bits are identical, this part of the ROM data
can be referenced without using the far specification in the pointer declaration.
For example, when "00C000H" is accessed, the contents of ROM at "FFC000H" are read. However, since
the ROM area in the FF bank exceeds 48 KBytes (resp. 32 KBytes for MB90V390H/MB90V390HA/
MB90V390HB), its entire image cannot be mirrored in the 00 bank.
On MB90394HA/MB90F394H(A), the image between "FF4000H" / "FF8000H"* to "FFFFFFH" is visible
in bank 00, whereas the data between "FF0000H" to "FF3FFFH" / "FF7FFFH"* is only visible in bank FF.
On MB90V390H/MB90V390HA/MB90V390HB, the image between "FF8000H" to "FFFFFFH" is visible in
bank 00, whereas the data between "FF0000H" to "FF7FFFH" is only visible in bank FF.
*: Can be selected by MS bit in ROM register (see Section "27.2 ROM Mirroring Register (ROMM)").
30
CHAPTER 2 CPU
Figure 2.3-1 Memory Space Map
MB90394HA/
F394H(A)
FFFFFFH
FF0000H
FEFFFFH
FE0000H
FDFFFF H
ROM (FF bank)
ROM (FE bank)
ROM (FD bank)
MB90V390HA/HB
FFFFFFH
FF0000H
FEFFFFH
FE0000H
FDFFFF H
FD0000H
FCFFFF H
FD0000H
FCFFFF H
FC0000H
FBFFFFH
FC0000H
FBFFFFH
FB0000H
FA F F F F H
FA 0 0 0 0 H
F9FFFFH
ROM (FB bank)
ROM (FA bank)
ROM (F9 bank)
F90000H
FB0000H
FA F F F F H
FA 0 0 0 0 H
F9FFFFH
ROM (FF bank)
ROM (FE bank)
ROM (FD bank)
ROM (FC bank)
ROM (FB bank)
ROM (FA bank)
ROM (F9 bank)
MB90V390H
FFFFFFH
FF0000H
FEFFFFH
ROM (FD bank)
FD0000H
FCFFFF H
ROM (FC bank)
FC0000H
FBFFFFH
FB0000H
FA F F F F H
FA 0 0 0 0 H
F9FFFFH
ROM (F8 bank)
F80000H
00FFFFH
004000H
or
008000H
ROM (Image of
FF bank)
003FFFH
003500H
00FFFFH
008000H
0070FFH
004100H
0028FFH
000100H
0000BFH
000000H
ROM (Image of
FF bank)
RAM 12Kbytes
ROM (F8 bank)
00FFFFH
008000H
ROM (Image of
FF bank)
0050FFH
004100H
RAM 4Kbytes
Peripheral
003500H
003500H
0030FFH
0030FFH
RAM 12Kbytes
0000BFH
000000H
ROM (F9 bank)
003FFFH
RAM 12Kbytes
000100H
000100H
Peripheral
ROM (FA bank)
RAM 6Kbytes
Peripheral
RAM 10Kbytes
ROM (FB bank)
F80000H
003FFFH
Peripheral
ROM (FE bank)
FE0000H
FDFFFF H
F90000H
F8FFFFH
F90000H
F8FFFFH
8017FFH
800000H
ROM (FF bank)
Peripheral
0000BFH
000000H
Peripheral
31
CHAPTER 2 CPU
2.4
Linear Addressing
There are two types of linear addressing:
• 24-bit operand specification: Directly specifies a 24-bit address using operands.
• 32-bit register indirect specification: Indirectly specifies the 24 low-order bits of a 32bit general-purpose register value as the address
■ 24-bit Operand Specification
Figure 2.4-1 shows an example of linear method (24-bit register operand specification). Figure 2.4-2 shows
an example of linear method (32-bit register indirect specification).
Figure 2.4-1 Example of Linear Method (24-bit Register Operand Specification)
JMPP 123456H
Old program counter
+ program bank
17
17452D H
452D
JMPP 123456H
123456 H
New program counter
+ program bank
12
Next instruction
3456
Figure 2.4-2 Example of Linear Method (32-bit Register Indirect Specification)
MOV A, @RL1+7
Old AL
090700 H
XXXX H
3A
+7
RL1
(The high-order eight bits are ignored.)
New AL
32
003AH
240906F9
CHAPTER 2 CPU
2.5
Bank Addressing Types
In the bank method, the 16-Mbyte space is divided into 256 64-Kbyte banks. The
following five bank registers are used to specify the banks corresponding to each
space:
• Program counter bank register (PCB)
• Data bank register (DTB)
• User stack bank register (USB)
• System stack bank register (SSB)
• Additional data bank register (ADB)
■ Bank Addressing Types
● Program counter bank register (PCB)
The 64-Kbyte bank specified by the PCB is called a program (PC) space. The PC space contains instruction
codes, vector tables, and immediate value data, for example.
● Data bank register (DTB)
The 64-Kbyte bank specified by the DTB is called a data (DT) space. The DT space contains readable/
writable data, and control/data registers for internal and external resources.
● User stack bank register (USB)/system stack bank register (SSB)
The 64-Kbyte bank specified by the USP or SSP is called a stack (SP) space. The SP space is accessed
when a stack access occurs during a push/pop instruction or interrupt register saving. The S flag in the
condition code register determines the stack space to be accessed.
● Additional data bank register (ADB)
The 64-Kbyte bank specified by the ADB is called an additional (AD) space. The AD space, for example,
contains data that cannot fit into the DT space.
Table 2.5-1 lists the default spaces used in each addressing mode, which are pre-determined to improve
instruction coding efficiency. To use a non-default space for an addressing mode, specify a prefix code
corresponding to a bank before the instruction. This enables access to the bank space corresponding to the
specified prefix code.
After reset, the DTB, USB, SSB, and ADB are initialized to "00H". The PCB is initialized to a value
specified by the reset vector. After reset, the DT, SP, and AD spaces are allocated in bank "00H" (000000H
to 00FFFFH), and the PC space is allocated in the bank specified by the reset vector.
33
CHAPTER 2 CPU
Table 2.5-1 Default Space
Default space
Program space
Addressing mode
PC indirect, program access, branch
Data space
Addressing mode using @RW0, @RW1, @RW4, or @RW5, @A, addr16, and dir
Stack space
Addressing mode using PUSHW, POPW, @RW3, or @RW7
Additional space
Addressing mode using @RW2 or @RW6
Figure 2.5-1 shows the physical addresses of each space.
Figure 2.5-1 Physical Addresses of Each Space
FFFFFF H
Program space
FF0000 H
FF H
:
PCB (Program counter bank register)
B3 H
: ADB (Additional data bank register)
92 H
: USB (User stack bank register)
68 H
: DTB (Data bank register)
4B H
: SSB (System stack bank register)
B3FFFF H
Additional space
Physical address
B30000 H
92FFFF H
User stack space
920000 H
68FFFF H
680000 H
Data space
4BFFFF H
System stack space
4B0000 H
000000 H
34
CHAPTER 2 CPU
2.6
Multi-byte Data in Memory Space
Data is written to memory from the low-order addresses. Therefore, for a 32-bit data
item, the low-order 16 bits are transferred before the high-order 16 bits.
If a reset signal is input immediately after the low-order bits are written, the high-order
bits might not be written.
■ Multi-byte Data Allocation in Memory Space
Figure 2.6-1 is a diagram of multi-byte data configuration in memory. The low-order eight bits of a data
item are stored at address n, then address n+1, address n+2, address n+3, etc.
Figure 2.6-1 Sample Allocation of Multi-byte Data in Memory
MSB
"H"
LSB
01010101B
11001100B
11111111B
00010100B
01010101
11001100
11111111
Address n
00010100
"L"
■ Accessing Multi-byte Data
Fundamentally, accesses are made within a bank. For an instruction accessing a multi-byte data item,
address "FFFFH" is followed by address "0000H" of the same bank. Figure 2.6-2 shows an execution of
MOVW A, 080FFFFH.
Figure 2.6-2 Execution of MOVW A, 080FFFFH
"H"
80FFFF H
AL before execution
??
??
AL after execution
23 H
01H
01H
·
·
·
23 H
800000 H
"L"
35
CHAPTER 2 CPU
2.7
Registers
The F2MC-16LX registers are largely classified into two types: special registers in the
CPU and general-purpose registers in memory. The special registers are dedicated
internal hardware of the CPU, and they have specific use defined by the CPU
architecture. The general-purpose registers share the CPU address space with RAM.
The general-purpose registers are the same as the special registers in that they can be
accessed without using an address. The applications of the general-purpose registers
can be specified by the user however, as is ordinary memory space.
■ Special Registers
The F2MC-16LX CPU core has the following special registers:
• Accumulator (A=AH:AL): Two 16-bit accumulators (Can be used as a single 32-bit accumulator.)
• User stack pointer (USP): 16-bit pointer indicating the user stack area
• System stack pointer (SSP): 16-bit pointer indicating the system stack area
• Processor status (PS): 16-bit register indicating the system status
• Program counter (PC): 16-bit register holding the address of the program
• Program counter bank register (PCB): 8-bit register indicating the PC space
• Data bank register (DTB): 8-bit register indicating the DT space
• User stack bank register (USB): 8-bit register indicating the user stack space
• System stack bank register (SSB): 8-bit register indicating the system stack space
• Additional data bank register (ADB): 8-bit register indicating the AD space
• Direct page register (DPR): 8-bit register indicating a direct page
Figure 2.7-1 is a diagram of the special registers.
36
CHAPTER 2 CPU
Figure 2.7-1 Special Registers
AH
AL
Accumulator
USP
User stack pointer
SSP
System stack pointer
PS
Processor status
PC
Program counter
DPR
Direct page register
PCB
Program counter bank register
DTB
Data bank register
USB
User stack bank register
SSB
System stack bank register
ADB
Additional data bank register
8bits
16bits
32bits
37
CHAPTER 2 CPU
■ General-purpose Registers
The F2MC-16LX general-purpose registers are located from addresses "000180H" to "00037FH" (maximum
configuration) of main storage. The register bank pointer (RP) indicates which of the above addresses are
currently being used as a register bank. Each bank has the following three types of registers. These registers
are mutually dependent as described in Figure 2.7-2.
• R0 to R7:
8-bit general-purpose register
• RW0 to RW7: 16-bit general-purpose register
• RL0 to RL3:
32-bit general-purpose register
Figure 2.7-2 General-purpose Registers
MSB
LSB
16bits
000180 H + RP*10 H
RW0
Low-order
RL0
First address of
general-purpose register
RW1
RW2
RL1
RW3
R1
R0
RW4
R3
R2
RW5
R5
R4
RW6
R7
R6
RW7
RL2
RL3
High-order
The relationship between the high-order and low-order bytes of a byte or word register is expressed as
follows:
RW (i+4) = R (i×2+1) × 256+R (i×2) [i=0 to 3]
The relationship between the high-order and low-order bytes of RLi and RWi can be expressed as follows:
RL (i) = RW (i×2+1) × 65536+RW (i×2) [i=0 to 3]
38
CHAPTER 2 CPU
2.7.1
Accumulator (A)
The accumulator (A) register consists of two 16-bit arithmetic operation registers (AH
and AL), and is used as a temporary storage for operation results and transfer data.
■ Accumulator (A)
The A register consists of two 16-bit arithmetic operation registers (AH and AL). The A register is used as
a temporary storage for operation results and transfer data. During 32-bit data processing, AH and AL are
used together. Only AL is used for word processing in 16-bit data processing mode or for byte processing
in 8-bit data processing mode (see Figure 2.7-3 and Figure 2.7-4). The data stored in the A register can be
operated upon with the data in memory or registers (Ri, RWi, or RLi). In the same manner as with the
F2MC-8L, when a word or shorter data item is transferred to AL, the previous data item in AL is
automatically sent to AH (data preservation function). The data preservation function and operation
between AL and AH help improve processing efficiency.
When a byte or shorter data item is transferred to AL, the data is sign-extended or zero-extended and stored
as a 16-bit data item in AL. The data in AL can be handled either as word or byte long.
When a byte-processing arithmetic operation instruction is executed on AL, the high-order eight bits of AL
before operation are ignored. The high-order eight bits of the operation result all become zeroes.
The A register is not initialized by a reset. The A register holds an undefined value immediately after a
reset.
Figure 2.7-3 32-bit Data Transfer
MOVL A,@R W1+6
Old A
XXXX H
MSB
XXXX H
A6 H
DTB
New A
8F74 H
AH
LSB
A61540 H
8FH
74 H
A6153EH
2B H
52 H
15 H
38 H
+6
2B52H
RW1
AL
Figure 2.7-4 AL-AH Transfer
MSB
MOVW A,@R W1+6
Old A
XXXX H
1234H
DTB
New A
1234H
1234H
A6H
LSB
A61540 H
8FH
74 H
A6153E H
2B H
52 H
15H
38 H
+6
RW1
39
CHAPTER 2 CPU
2.7.2
User Stack Pointer (USP) and System Stack Pointer
(SSP)
USP and SSP are 16-bit registers that indicate the memory addresses for saving and
restoring data when a push/pop instruction or subroutine is executed.
■ User Stack Pointer (USP) and System Stack Pointer (SSP)
USP and SSP are 16-bit registers that indicate the memory addresses for saving and restoring data in the
event of a push/pop instruction or subroutine execution. The USP and SSP registers are used by stack
instructions. The USP register is enabled when the S flag in the processor status register is "0", and the SSP
register is enabled when the S flag is "1" (see Figure 2.7-5). Since the S flag is set when an interrupt is
accepted, register values are always saved in the memory area indicated by SSP during interrupt
processing. SSP is used for stack processing in an interrupt routine, while USP is used for stack processing
outside an interrupt routine. If the stack space is not divided, use only the SSP.
During stack processing, the high-order eight bits of an address are indicated by SSB (for SSP) or USB (for
USP). USP and SSP are not initialized by a reset. Instead, they hold undefined values.
Figure 2.7-5 Stack Manipulation Instruction and Stack Pointer
Example 1 PUSHW A when the S flag is "0"
Before execution
AL
S flag
After execution
AL
MSBLSB
C6F326H
A624 H
USB
C6 H
USP
F328 H
0
SSB
56 H
SSP
1234 H
A624 H
USB
C6 H
USP
F326 H
0
SSB
56 H
SSP
1234 H
C6F326H
A6H
24H
A624 H
USB
C6 H
USP
F328 H
561232 H
XX H
XXH
1
SSB
56 H
SSP
1234 H
A624 H
USB
C6 H
USP
F328 H
561232H
A6 H
24H
1
SSB
56 H
SSP
1232 H
XX H
XX H
User stack is used because
the S flag is "0".
Example 2 PUSHW A when the S flag is "1"
AL
AL
System stack is used because
the S flag is "1".
Note:
Specify an even-numbered address in the stack pointer whenever possible.
40
CHAPTER 2 CPU
2.7.3
Processor Status (PS)
The PS register consists of the bits controlling the CPU Operation and the bits
indicating the CPU status.
■ Processor Status (PS)
As shown in Figure 2.7-6, the high-order byte of the PS register consists of a register bank pointer (RP) and
an interrupt level mask register (ILM). The RP indicates the start address of a register bank. The low-order
byte of the PS register is a condition code register (CCR), containing the flags to be set or reset depending
on the results of instruction execution or interrupt occurrences.
Figure 2.7-6 Processor Status (PS) Structure
bit
15
PS
13 12
8
ILM
0
7
RP
CCR
■ Condition Code Register (CCR)
Figure 2.7-7 is a diagram of condition code register configuration.
Figure 2.7-7 Condition Code Register (CCR) Configuration
bit
Initial value
7
6
5
4
3
2
1
0
-
I
S
T
N
Z
V
C
-
0
1
*
*
*
*
*
CCR
*: Undefined
● I: Interrupt enable flag:
Interrupts other than software interrupts are enabled when the I flag is "1" and are masked when the I flag is
"0". The I flag is cleared by a reset.
● S: Stack flag:
When the S flag is "0", USP is enabled as the stack manipulation pointer.
When the S flag is "1", SSP is enabled as the stack manipulation pointer.
The S flag is set by an interrupt reception or a reset.
41
CHAPTER 2 CPU
● T: Sticky bit flag:
"1" is set in the T flag when there is at least one "1" in the data shifted out from the carry after execution of
a logical right/arithmetic right shift instruction. Otherwise, "0" is set in the T flag. In addition, "0" is set in
the T flag when the shift amount is zero.
● N: Negative flag:
The N flag is set when the MSB of the operation result is "1", and is otherwise cleared.
● Z: Zero flag:
The Z flag is set when the operation result is all zeroes, and is otherwise cleared.
● V: Overflow flag:
The V flag is set when an overflow of a signed value occurs as a result of operation execution and is
otherwise cleared.
● C: Carry flag:
The C flag is set when a carry-up or carry-down from the MSB occurs as a result of operation execution,
and is otherwise cleared.
■ Register Bank Pointer (RP)
The RP register indicates the relationship between the general-purpose registers of the F2MC-16LX and the
built-in RAM addresses. Specifically, the RP register indicates the first memory address of the currently
used register bank in the following conversion expression: [00180H + (RP) × 10H] (see Figure 2.7-8). The
RP register consists of five bits, and can take a value between "00H" and "1FH". Register banks can be
allocated at addresses from "000180H" to "00037H" in memory.
Even within that range, however, the register banks cannot be used as general-purpose registers if the banks
are not in built-in RAM. The RP register is initialized to all "0" by a reset. An instruction may transfer an
eight-bit immediate value to the RP register; however, only the low-order five bits of that data are used.
Figure 2.7-8 Register Bank Pointer (RP)
Initial value
42
B4
B3
B2
B1
B0
0
0
0
0
0
RP
CHAPTER 2 CPU
■ Interrupt Level Mask Register (ILM)
The ILM register consists of three bits, indicating the CPU interrupt masking level. An interrupt request is
accepted only when the level of the interrupt is higher than that indicated by these three bits. Level 0 is the
highest priority interrupt, and level 7 is the lowest priority interrupt (see Table 2.7-1). Therefore, for an
interrupt to be accepted, its level value must be smaller than the current ILM value. When an interrupt is
accepted, the level value of that interrupt is set in ILM. Thus, an interrupt of the same or lower level cannot
be accepted subsequently. ILM is initialized to all zeroes by a reset. An instruction may transfer an eight-bit
immediate value to the ILM register, but only the low-order three bits of that data are used.
Figure 2.7-9 Interrupt Level Register (ILM)
Initial value
ILM2
ILM1
ILM0
0
0
0
ILM
Table 2.7-1 Levels Indicated by the Interrupt Level Mask (ILM) Register
ILM2
ILM1
ILM0
Level value
Acceptable interrupt level
0
0
0
0
Interrupt disabled
0
0
1
1
0 only
0
1
0
2
Level value smaller than 1
0
1
1
3
Level value smaller than 2
1
0
0
4
Level value smaller than 3
1
0
1
5
Level value smaller than 4
1
1
0
6
Level value smaller than 5
1
1
1
7
Level value smaller than 6
43
CHAPTER 2 CPU
2.7.4
Program Counter (PC)
The PC register is a 16-bit counter that indicates the low-order 16 bits of the memory
address of an instruction code to be executed by the CPU. The high-order eight bits of
the address are indicated by the PCB. The PC register is updated by a conditional
branch instruction, subroutine call instruction, interrupt, or reset. The PC register can
also be used as a base pointer for operand access.
■ Program Counter (PC)
Figure 2.7-10 shows the program counter.
Figure 2.7-10 Program Counter
PCB
FEH
PC
ABCDH
Next instruction to be executed
FEABCD H
44
CHAPTER 2 CPU
2.8
Register Bank
A register bank consists of eight words. The register bank can be used as the following
general-purpose registers for arithmetic operations: byte registers R0 to R7, word
registers RW0 to RW7, and long word registers RL0 to RL3. In addition, the register
bank can be used as instruction pointers.
■ Register Bank
Table 2.8-1 lists the functions of the registers. Table 2.8-2 indicates the relationship between the registers.
In the same manner as for an ordinary RAM area, the register bank values are not initialized by a reset. The
status before a reset is maintained. When the power is turned on, however, the register bank will have an
undefined value.
Table 2.8-1 Register Functions
R0 to R7
Used as operands of instructions.
Note: R0 is also used as a counter for barrel shift or normalization instructions.
RW0 to RW7
Used as pointers.
Used as operands of instructions.
Note: RW0 is used as a counter for string instructions.
RL0 to RL3
Used as long pointers.
Used as operands of instructions.
Table 2.8-2 Relationship between Registers
RW0
RL0
RW1
RW2
RL1
RW3
R0
RW4
R1
RL2
R2
RW5
R3
R4
RW6
R5
RL3
R6
RW7
R7
45
CHAPTER 2 CPU
● Direct page register (DPR) <Initial value: 01H>
DPR specifies addr8 to addr15 of the instruction operands in direct addressing mode as shown in Figure
2.8-1. DPR is eight bits long, and is initialized to "01H" by a reset. DPR can be read or written to by an
instruction.
Figure 2.8-1 Generating a Physical Address in Direct Addressing Mode
DTB register
DPR register
αααααααα
ββββββββ
γγγγγγγγ
LSB
MSB
24-bit physical
address
Direct address during instruction
ααααααααββββββββγγγγγγγγ
● Program counter bank register (PCB) <Initial value: Value in reset vector>
● Data bank register (DTB) <Initial value: 00H>
● User stack bank register (USB) <Initial value: 00H>
● System stack bank register (SSB) <Initial value: 00H>
● Additional data bank register (ADB) <Initial value: 00H>
Each bank register indicates the memory bank where the PC, DT, SP (user), SP (system), or AD space is
allocated. All bank registers are one byte long. PCB is initialized to "00H" by a reset. Bank registers other
than PCB can be read or written to. PCB can be read but cannot be written to.
PCB is updated when the JMPP, CALLP, RETP, RETIQ, or RETF instruction branching to the entire 16Mbyte space is executed or when an interrupt occurs. For operation of each register, see Section "2.2
Memory Space".
46
CHAPTER 2 CPU
2.9
Prefix Codes
Placing a prefix code before an instruction partially changes the operation of the
instruction. Three types of prefix codes can be used: bank select prefix, common
register bank prefix, and flag change disable prefix.
■ Bank Select Prefix
The memory space used for accessing data is determined for each addressing mode.
When a bank select prefix is placed before an instruction, the memory space used for accessing data by that
instruction can be selected regardless of the addressing mode.
Table 2.9-1 lists the bank select prefixes.
Table 2.9-1 Bank Select Prefix
Bank select prefix
Space selected
PCB
PC space
DTB
Data space
ADB
AD space
SPB
Either the SSP or USP space is used according to the stack flag value.
Use the following instructions with care:
● String instructions (MOVS, MOVSW, SCEQ, SCWEQ, FILS, FILSW)
The bank register specified by an operand is used regardless of the prefix.
● Stack manipulation instructions (PUSHW, POPW)
SSB or USB is used according to the S flag regardless of the prefix.
● I/O access instructions
MOV A, io / MOV io, A /MOVX A, io / MOVW A, io /MOVW io, A / MOV io, #imm8
MOV io, #imm16 / MOVB A, io:bp / MOB io:bp, A /SETB io:bp / CLRB io:bp
BBC io:bp, rel / BBS io:bp, rel WBTC, WBTS
The I/O space of the bank is used regardless of the prefix.
● Flag change instructions (AND CCR,#imm8, OR CCR,#imm8)
The instruction is executed normally, but the prefix affects the next instruction.
● POPW PS
SSB or USB is used according to the S flag regardless of the prefix. The prefix affects the next instruction.
● MOV ILM,#imm8
The instruction is executed normally, but the prefix affects the next instruction.
47
CHAPTER 2 CPU
● RETI
SSB is used regardless of the prefix.
■ Common Register Bank Prefix (CMR)
To simplify data exchange between multiple tasks, the same register bank must be accessed relatively
easily regardless of the RP value. When CMR is placed before an instruction that accesses a register bank,
that instruction accesses the common bank (the register bank selected when RP=0) at addresses from
"000180H" to "00018FH" regardless of the current RP value. Use the following instructions with care:
● String instructions (MOVS, MOVSW, SCEQ, SCWEQ, FILS, FILSW)
If an interrupt request occurs during execution of a string instruction with a prefix code, the prefix code
becomes invalid when the string instruction is resumed after the interrupt is processed. Thus, the string
instruction is executed falsely after the interrupt is processed. Do not prefix any of the above string
instructions with CMR.
● Flag change instructions (AND CCR,#imm8, OR CCR,#imm8, POPW PS)
The instruction is executed normally, but the prefix affects the next instruction.
● MOV ILM,#imm8
The instruction is executed normally, but the prefix affects the next instruction.
■ Flag Change Disable Prefix (NCC)
To disable flag changes, use the flag change disable prefix code (NCC). Placing NCC before an instruction
disables flag changes associated with that instruction. Use the following instructions with care:
● String instructions (MOVS, MOVSW, SCEQ, SCWEQ, FILS, FILSW)
If an interrupt request occurs during execution of a string instruction with a prefix code, the prefix code
becomes invalid when the string instruction is resumed after the interrupt is processed. Thus, the string
instruction is executed incorrectly after the interrupt is processed. Do not prefix any of the above string
instructions with NCC.
● Flag change instructions (AND CCR,#imm8, OR CCR,#imm8, POPW PS)
The instruction is executed normally, but the prefix affects the next instruction.
● Interrupt instructions (INT #vct8, INT9, INT addr16, INTP addr24, RETI)
CCR changes according to the instruction specifications regardless of the prefix.
● JCTX @A
CCR changes according to the instruction specifications regardless of the prefix.
● MOV ILM,#imm8
The instruction is executed normally, but the prefix affects the next instruction.
48
CHAPTER 2 CPU
2.10
Interrupt Disable Instructions
Interrupt requests are not sampled for the following ten instructions:
- MOV ILM,#imm8 - PCB - SPB
- OR
CCR,#imm8 - NCC
- AND CCR,#imm8 - ADB - CMR - POPW PS
- DTB
■ Interrupt Disable Instructions
If a valid interrupt request occurs during execution of any of the above instructions, the interrupt can be
processed only when an instruction other than the above is executed. For details, see Figure 2.10-1.
Figure 2.10-1 Interrupt Disable Instruction
Interrupt disable instruction
•••••••••••
(a)
(a) Ordinary
instruction
Interrupt request
Interrupt acceptance
■ Restrictions on Interrupt Disable Instructions and Prefix Instructions
When a prefix code is placed before an interrupt disable instruction, the prefix code affects the first
instruction after the code other than the interrupt disable instruction. For details, see Figure 2.10-2.
Figure 2.10-2 Interrupt Disable Instructions and Prefix Codes
Interrupt disable instruction
MOV A, FFH
CCR:XXX10XXB
NCC
MOV ILM,#imm8
••••
ADD A,01H
CCR:XXX10XXB
CCR does not change with NCC.
49
CHAPTER 2 CPU
■ Consecutive Prefix Codes
When competitive prefix codes are placed consecutively, the latter becomes valid.
In the figure below, competitive prefix codes are PCB, ADB, DTB, and SPB. For details, see
Figure 2.10-3.
Figure 2.10-3 Consecutive Prefix Codes
Prefix code
•••••
ADB
DTB
PCB
ADD A,01H
••••
PCB is valid as the prefix code
50
CHAPTER 2 CPU
2.11
Precautions for Use of "DIV A, Ri" and "DIVW A, RWi"
Instructions
Set "00H" in the bank register before using the "DIV A, Ri" and "DIVW A, RWi"
instructions.
■ Precautions for Use of "DIV A, Ri" and "DIVW A, RWi" Instructions
Table 2.11-1 Precautions for Use of "DIV A, Ri" and "DIVW A, RWi" Instructions (i = 0 to 7)
Instruction
Bank register affected
by the execution of the
instructions listed on the
left
Address that stores the remainder
DIV A, R0
(DTB: Upper 8 bits) + (0180H + RP × 10H + 8H : Lower 16 bits)
DIV A, R1
(DTB: Upper 8 bits) + (0180H + RP × 10H + 9H : Lower 16 bits)
DIV A, R4
(DTB: Upper 8 bits) + (0180H + RP × 10H + CH : Lower 16 bits)
(DTB: Upper 8 bits) + (0180H + RP × 10H + DH : Lower 16 bits)
DIV A, R5
DTB
DIVW A, RW0
(DTB: Upper 8 bits) + (0180H + RP × 10H + 0H : Lower 16 bits)
DIVW A, RW1
(DTB: Upper 8 bits) + (0180H + RP × 10H + 2H : Lower 16 bits)
DIVW A, RW4
(DTB: Upper 8 bits) + (0180H + RP × 10H + 8H : Lower 16 bits)
DIVW A, RW5
(DTB: Upper 8 bits) + (0180H + RP × 10H + AH : Lower 16 bits)
DIV A, R2
(ADB: Upper 8 bits) + (0180H + RP × 10H + AH : Lower 16 bits)
(ADB: Upper 8 bits) + (0180H + RP × 10H + EH : Lower 16 bits)
DIV A, R6
ADB
DIVW A, RW2
(ADB: Upper 8 bits) + (0180H + RP × 10H + 4H : Lower 16 bits)
DIVW A, RW6
(ADB: Upper 8 bits) + (0180H + RP × 10H + EH : Lower 16 bits)
DIV A, R3
(USB *2: Upper 8 bits) + (0180H + RP × 10H + BH : Lower 16 bits)
DIV A, R7
DIVW A, RW3
DIVW A, RW7
USB
SSB *1
(USB *2: Upper 8 bits) + (0180H + RP × 10H + FH : Lower 16 bits)
(USB *2: Upper 8 bits) + (0180H + RP × 10H + 6H : Lower 16 bits)
(USB *2: Upper 8 bits) + (0180H + RP × 10H + EH : Lower 16 bits)
*1: Depends on the S bit of the CCR register.
*2: In the event that the S bit of the CCR register is "0"
If the value of the bank registers (DTB, ADB, USB, and SSB) is "00H", the remainder after division is
stored in the register of the instruction operands. Otherwise, the upper eight bits is specified by the bank
register corresponding to the register of the instruction operand, and the lower 16 bits is the same as the
address of the register of the instruction operand. The remainder is stored in the bank register specified by
the upper eight bits.
51
CHAPTER 2 CPU
Example:
If "DIV A,R0" is executed with DTB = 053H and RP = 03H, the address of R0 is "0180H" + RP ("03H")
× "10H" + "08H" (R0 corresponding address) = 0001B8H. Since the data bank register (DTB) is
specified by "DIV A,R0" as the bank register, the remainder is stored in address "05301B8H", which
was obtained by adding the bank address "053H".
Note:
For information about the bank register and Ri and RWi registers, see Section "2.7 Registers".
■ Use of the "DIV A, Ri" and "DIVW A, RWi" Instructions without Precautions
To enable users to develop programs without having to take precautions for using the "DIV A,Ri" and
"DIVW A,RWi" instructions, special compilers and assemblers are available. The special compiler does not
generate the instructions in Table 2.11-1. The special assemblers have a function that replaces the
instructions in Table 2.11-1 with equivalent instruction strings. For the MB90390 series, use the following
types of compilers and assemblers:
● Compiler
cc907 V02L06 or later, or fcc907s V30L02 or later
● Assembler
asm907a V03L04 or later, or fasm907s V30L04 (Rev. 300004) or later
52
CHAPTER 3
INTERRUPTS
This chapter explains the functions and operations of
the interrupt and extended intelligent I/O service (EI2OS)
for MB90390 series.
3.1 Outline of Interrupts
3.2 Interrupt Vector
3.3 Interrupt Control Registers (ICR)
3.4 Interrupt Flow
3.5 Hardware Interrupts
3.6 Software Interrupts
3.7 Extended Intelligent I/O Service (EI2OS)
3.8 Operation Flow of and Procedure for Using the Extended Intelligent
I/O Service (EI2OS)
3.9 Exceptions
53
CHAPTER 3 INTERRUPTS
3.1
Outline of Interrupts
The F2MC-16LX has interrupt functions that terminate the currently executing
processing and transfer control to another specified program when a specified event
occurs. There are four types of interrupt functions:
• Hardware interrupt: Interrupt processing due to an internal resource event
• Software interrupt: Interrupt processing due to a software event occurrence
instruction
• Extended intelligent I/O service (EI2OS): Transfer processing due to an internal
resource event
• Exception: Termination due to an operation exception
■ Hardware Interrupts
A hardware interrupt is activated by an interrupt request from an internal resource. A hardware interrupt
request occurs when both the interrupt request flag and the interrupt enable flag in an internal resource are
set. Therefore, an internal resource must have an interrupt request flag and interrupt enable flag to issue a
hardware interrupt request.
● Specifying an interrupt level
An interrupt level can be specified for the hardware interrupt. To specify an interrupt level, use
the level setting bits (IL0, IL1, and IL2) of the interrupt controller.
● Masking a hardware interrupt request
A hardware interrupt request can be masked by using the I flag of the processor status register
(PS) in the CPU and the ILM bits (IL0, IL1, and IL2). When an unmasked interrupt request
occurs, the CPU saves 12 bytes of data that consists of registers PS, PC, PCB, DTB, ADB, DPR,
and A in the memory area indicated by the SSB and SSP registers.
54
CHAPTER 3 INTERRUPTS
Figure 3.1-1 Overview of Hardware Interrupts
PS
F2MC-16LX bus
Register file
Microcode
IR
I
ILM
Check
Comparator
PS
I
ILM
IR
B unit
:Processor status
:Interrupt enable flag
:Interrupt level mask register
:Instruction register
:Bus interface unit
F M C - 1 6 LX . CPU
2
Enable FF
AND
Cause FF
Interrupt level IL
Level comparator
Peripheral
Interrupt
controller
■ Software Interrupts
Interrupts requested by executing the INT instruction are software interrupts. An interrupt request by the
INT instruction does not have an interrupt request or enable flag. An interrupt request is issued always by
executing the INT instruction.
No interrupt level is assigned to the INT instruction. Therefore, ILM is not updated when the INT
instruction is used. Instead, the I flag is cleared and the continuing interrupt requests are suspended.
Figure 3.1-2 Overview of Software Interrupts
PS
I
F2MC-16LX
bus
Register file
Microcode
S
B unit
IR
F 2 M C - 1 6 LX · C P U
Queue
PS
I
S
IR
B unit
:Processor status
:Interrupt enable flag
:Stack flag
:Instruction register
:Bus interface unit
Fetch
Save
Instruction bus
RAM
■ Extended Intelligent I/O Service (EI2OS)
The extended intelligent I/O service automatically transfers data between an internal resource and memory.
This processing is traditionally performed by an interrupt processing program, but the EI2OS enables data
to be transferred in a manner similar to a DMA (direct memory access) operation.
To activate the extended intelligent I/O service function from an internal resource, the interrupt control
register (ICR) of the interrupt controller must have an extended intelligent I/O service enable flag (ISE).
The extended intelligent I/O service is started when an interrupt request occurs with "1" specified in the
ISE flag.
To generate a normal interrupt using a hardware interrupt request, set the ISE flag to "0".
55
CHAPTER 3 INTERRUPTS
Figure 3.1-3 Overview of the Extended Intelligent I/O Service (EI2OS)
Memory space
by IOA
I/O register
I/O register
Peripheral
Interrupt request
CPU
➂
➂
ISD
by ICS
➁
➀
Interrupt control register
Interrupt controller
by BAP
➃
Buffer
➀ I/O requests transfer.
➁ The interrupt controller selects the
descriptor.
➂ The transfer source and destination
are read from the descriptor.
by DCT
➃ Data is transferred between I/O and
memory.
■ Exceptions
Exception processing is basically the same as interrupt processing. When an exception is detected between
instructions, exception processing is performed. In general, exception processing occurs as a result of an
unexpected operation. Therefore, use exception processing only for debugging programs or for activating
recovery software in an emergency.
56
CHAPTER 3 INTERRUPTS
3.2
Interrupt Vector
An interrupt vector uses the same area for both hardware and software interrupts. For
example, interrupt request number INT42 is used for a delayed hardware interrupt and
for software interrupt INT #42. Therefore, the delayed interrupt and INT #42 call the
same interrupt processing routine. Interrupt vectors are allocated between addresses
"FFFC00H" and "FFFFFFH" as shown in Table 3.2-1.
■ Interrupt Vector
Table 3.2-1 Interrupt Vectors (1/2)
Interrupt
request
Interrupt cause
Interrupt control
register
Number
Address
Vector
address L
Vector
address H
Vector
address
bank
Mode
register
INT 0 *1
−
−
−
FFFFFCH
FFFFFDH
FFFFFEH
Unused
INT 1 *1
−
−
−
FFFFF8H
FFFFF9H
FFFFFAH
Unused
.
.
.
−
−
−
.
.
.
.
.
.
.
.
.
.
.
.
INT 7 *1
−
−
−
FFFFE0H
FFFFE1H
FFFFE2H
Unused
INT 8
Reset
−
−
FFFFDCH
FFFFDDH
FFFFDEH
FFFFDFH
INT 9
INT9 instruction
−
−
FFFFD8H
FFFFD9H
FFFFDAH
Unused
INT 10
Exception
−
−
FFFFD4H
FFFFD5H
FFFFD6H
Unused
INT 11
Time-base Timer
FFFFD1H
FFFFD2H
Unused
0000B0H
FFFFD0H
ICR00
FFFFCCH
FFFFCDH
FFFFCEH
Unused
FFFFC8H
FFFFC9H
FFFFCAH
Unused
FFFFC4H
FFFFC5H
FFFFC6H
Unused
FFFFC0H
FFFFC1H
FFFFC2H
Unused
FFFFBCH
FFFFBDH
FFFFBEH
Unused
FFFFB8H
FFFFB9H
FFFFBAH
Unused
FFFFB4H
FFFFB5H
FFFFB6H
Unused
FFFFB0H
FFFFB1H
FFFFB2H
Unused
FFFFACH
FFFFADH
FFFFAEH
Unused
FFFFA8H
FFFFA9H
FFFFAAH
Unused
FFFFA4H
FFFFA5H
FFFFA6H
Unused
INT 12
External Interrupt INT0 to INT7
INT 13
CAN0 RX
ICR01
INT 14
CAN0 TX/NS
INT 15
CAN1 RX
ICR02
INT 16
CAN1 TX/NS
INT 17
PPG0/PPG1 (CAN2 RX)*2
ICR03
INT 18
PPG2/PPG3 (CAN2 TX/NS)*2
INT 19
PPG4/PPG5 (CAN3 RX)*2
ICR04
INT 20
PPG6/PPG7 (CAN3 TX/NS)*2
INT 21
PPG8/PPG9 (CAN4 RX)*2
ICR05
INT 22
PPGA/PPGB (CAN4 TX/NS)*2
0000B1H
0000B2H
0000B3H
0000B4H
0000B5H
57
CHAPTER 3 INTERRUPTS
Table 3.2-1 Interrupt Vectors (2/2)
Interrupt
request
INT 23
Interrupt cause
Interrupt control
register
Number
Address
ICR06
0000B6H
16-bit Reload Timer 0
INT 24
16-bit Reload Timer 1
INT 25
Input Capture 0/1
ICR07
INT 26
Output Compare 0/1
INT 27
Input Capture 2/3 / Output
Compare 6
ICR08
0000B7H
0000B8H
Vector
address L
Vector
address H
Vector
address
bank
Mode
register
FFFFA0H
FFFFA1H
FFFFA2H
Unused
FFFF9CH
FFFF9DH
FFFF9EH
Unused
FFFF98H
FFFF99H
FFFF9AH
Unused
FFFF94H
FFFF95H
FFFF96H
Unused
FFFF90H
FFFF91H
FFFF92H
Unused
INT 28
Output Compare 2/3
FFFF8CH
FFFF8DH
FFFF8EH
Unused
INT 29
Input Capture 4/5 / Output
Compare 7
FFFF88H
FFFF89H
FFFF8AH
Unused
INT 30
Output Compare 4/5 (I2C)
*2, *3
FFFF84H
FFFF85H
FFFF86H
Unused
INT 31
A/D Converter
FFFF80H
FFFF81H
FFFF82H
Unused
FFFF7CH
FFFF7DH
FFFF7EH
Unused
FFFF78H
FFFF79H
FFFF7AH
Unused
FFFF74H
FFFF75H
FFFF76H
Unused
FFFF70H
FFFF71H
FFFF72H
Unused
FFFF6CH
FFFF6DH
FFFF6EH
Unused
FFFF68H
FFFF69H
FFFF6AH
Unused
FFFF64H
FFFF65H
FFFF66H
Unused
FFFF60H
FFFF61H
FFFF62H
Unused
FFFF5CH
FFFF5DH
FFFF5EH
Unused
FFFF58H
FFFF59H
FFFF5AH
Unused
FFFF54H
FFFF55H
FFFF56H
Unused
ICR09
ICR10
INT 32
I/O Timer 0/1 / Watch Timer
INT 33
Serial I/O
ICR11
INT 34
Sound Generator
INT 35
UART0 RX
ICR12
INT 36
UART0 TX
INT 37
UART1 RX
ICR13
INT 38
UART1 TX
INT 39
UART3 (/UART2)*2 RX
ICR14
INT 40
UART3 (/UART2)*2TX
INT 41
Flash Memory
ICR15
0000B9H
0000BAH
0000BBH
0000BCH
0000BDH
0000BEH
0000BFH
INT 42
Delayed Interrupt
INT 43
−
−
−
FFFF50H
FFFF51H
FFFF52H
Unused
.
.
.
−
−
−
.
.
.
.
.
.
.
.
.
.
.
.
INT 254
−
−
−
FFFC04H
FFFC05H
FFFC06H
Unused
INT 255
−
−
−
FFFC00H
FFFC01H
FFFC02H
Unused
*1: When PCB is "FFH", the vector area for the CALLV instruction is the same as that for INT #vct8 (#0 to #7).
Care must be taken when using the vector for the CALLV instruction.
*2: The interrupt cause is shared with the interrupt of MB90V390HA/MB90V390HB in parentheses.
*3: The interrupt cause is shared with the interrupt of MB90394HA in parentheses.
58
CHAPTER 3 INTERRUPTS
3.3
Interrupt Control Registers (ICR)
The interrupt control registers are in the interrupt controller. Each interrupt control
register has a corresponding I/O that has an interrupt function. The interrupt control
registers have the following three functions:
• Setting an interrupt level for corresponding peripherals
• Selecting whether to use an ordinary interrupt or extended intelligent I/O service for
the corresponding peripherals
• Selecting the extended intelligent I/O service channel
Do not access an interrupt control register by using a read-modify-write (RMW)
instruction, as doing so causes a misoperation.
■ Interrupt Control Register (ICR)
Figure 3.3-1 shows an interrupt control register (ICR).
Figure 3.3-1 Interrupt Control Register (ICR)
bit
8/0
15/7
14/6
13/5
12/4
11/3
10/2
9/1
ICS3
ICS2
ICS1
or
S1
ICS0
or
S0
ISE
IL2
IL1
IL0
W
W
R/W
R/W
R/W
R/W
*
*
Interrupt control register
00000111B when reset
*: "1" is read always. ICS1 and ICS0 are valid for write only. S1 and S0 are valid for read only.
Notes:
• ICS3 to ICS0 can only be enabled when you activate EI2OS. Set ISE bit to "1" if you activate
EI2OS. Otherwise, set ISE bit to "0". Any value can be set to ICS3 to ICS0 if you don’t activate
EI2OS.
• ICS1 and ICS0 are valid for write only. S1 and S0 are valid for read only.
<Additional information>
The extended intelligent I/O service channel select bits (ICR: ICS3 to ICS0) are valid for write
only. The extended intelligent I/O service status bits (ICR: S1, S0) are valid for read only. When
reading, "1" is returned from bit6, bit7/bit14, bit15 (ICS2, ICS3).
[bit10 to bit8, bit2 to bit0] IL0, IL1, and IL2 (interrupt level setting bits)
These bits are readable and writable, and specify the interrupt level of the corresponding internal
resources. Upon a reset, these bits are initialized to level 7 (no interrupt). Table 3.3-1 shows an interrupt
level setting bits and interrupt levels.
59
CHAPTER 3 INTERRUPTS
Table 3.3-1 Interrupt Level Setting Bits and Interrupt Levels
IL2
IL1
IL0
Level
0
0
0
0 (Strongest)
0
0
1
1
0
1
0
2
0
1
1
3
1
0
0
4
1
0
1
5
1
1
0
6 (Weakest)
1
1
1
7 (No interrupt)
[bit11, bit3] ISE (extended intelligent I/O service enable bits)
The ISE bit is readable and writable. In response to an interrupt request, EI2OS is activated when "1" is
set in the ISE bit and an interrupt sequence is activated when "0" is set in the ISE bit. Upon completion
of EI2OS, the ISE bit is cleared to a zero. If the corresponding peripheral does not have the EI2OS
function, the ISE bit must be set to "0" on the software side.
Upon a reset, the ISE bit is initialized to "0".
[bit15 to bit12, bit7 to bit4] ICS3 to ICS0 (extended intelligent I/O service channel select bits)
ICS3 to ICS0 are write-only bits. These bits specify the EI2OS channel. The values set in these bits
determine the intelligent I/O service descriptor addresses in memory, which is explained later. The ICS
bits are initialized by a reset.
Table 3.3-2 lists ICS bits, channel numbers, and descriptor addresses.
60
CHAPTER 3 INTERRUPTS
Table 3.3-2 ICS Bits, Channel Numbers, and Descriptor Addresses
ICS3
ICS2
ICS1
ICS0
Selected channel
Descriptor address
0
0
0
0
0
000100H
0
0
0
1
1
000108H
0
0
1
0
2
000110H
0
0
1
1
3
000118H
0
1
0
0
4
000120H
0
1
0
1
5
000128H
0
1
1
0
6
000130H
0
1
1
1
7
000138H
1
0
0
0
8
000140H
1
0
0
1
9
000148H
1
0
1
0
10
000150H
1
0
1
1
11
000158H
1
1
0
0
12
000160H
1
1
0
1
13
000168H
1
1
1
0
14
000170H
1
1
1
1
15
000178H
[bit13 and bit12, bit5 and bit4] S0 and S1 (extended intelligent I/O service status)
S0 and S1 are read-only bits. The values set in these bits indicate the end condition of EI2OS. These bits
are initialized to "00B" upon a reset.
Table 3.3-3 shows the S bits and end conditions.
Table 3.3-3 S Bits and End Conditions
S1
S0
End condition
0
0
EI2OS running or not activated
0
1
Termination by count
1
0
Reserved
1
1
Termination by request from resource
61
CHAPTER 3 INTERRUPTS
3.4
Interrupt Flow
Figure 3.4-1 shows the interrupt flow.
■ Interrupt Flow
Figure 3.4-1 Interrupt Flow
I: Flag in CCR
ILM: Level register in CPU
IF: Internal resource interrupt request
IE: Internal resource interrupt enable flag
ISE: EI2OS enable flag
IL: Internal resource interrupt request level
S: Flag in CCR
I & IF & IE = 1
AND
ILM > IL
YES
NO
NO
YES
ISE = 1
Fetching and decoding
the next instruction
Saving PS, PC, PCB, DTB,
ADB, DPR, and A into the
stack of SSP, and setting ILM=IL
Executing the extended
intelligent I/O service
YES
INT instruction
NO
Executing an ordinary
instruction
NO
Completion of
string instruction
repetition
YES
Updating PC
62
Saving PS, PC, PCB, DTB, ADB,
DPR, and A into the stack of SSP,
and setting I=0 and ILM=IL
S← 1
Fetching the interrupt vector
CHAPTER 3 INTERRUPTS
Figure 3.4-2 Register Saving During Interrupt Processing
Word (16 bits)
MSB
LSB
"H"
SSP (SSP value before interrupt)
AH
AL
DPR
ADB
DTB
PCB
PC
PS
"L"
SSP (SSP value after interrupt)
63
CHAPTER 3 INTERRUPTS
3.5
Hardware Interrupts
In response to an interrupt request signal from an internal resource, the CPU pauses
current program execution and transfers control to the interrupt processing program
defined by the user. This function is called the hardware interrupt function.
■ Hardware Interrupts
A hardware interrupt occurs when the relevant conditions are satisfied as a result of two operations:
comparison between the interrupt request level and the value in the interrupt level mask register (ILM) of
PS in the CPU, and hardware reference to the I flag value of PS.
The CPU performs the following processing when a hardware interrupt occurs:
•
Saves the values in the PC, PS, AH, AL, PCB, DTB, ADB, and DPR registers of the CPU to the system
stack.
•
Sets ILM in the PS register. The currently requested interrupt level is automatically set.
•
Fetches the corresponding interrupt vector value and branches to the processing indicated by that value.
■ Structure of Hardware Interrupt
Hardware interrupts are handled by the following three sections:
● Internal resources
Interrupt enable and request bits: Used to control interrupt requests from resources.
● Interrupt controller
ICR: Assigns interrupt levels and determines the priority levels of simultaneously requested interrupts.
● CPU
I and ILM: Used to compare the requested and current interrupt levels and to identify the interrupt enable
status.
Microcode: Interrupt processing step
The status of these sections are indicated by the resource control registers for internal resources, the ICR
for the interrupt controller, and the CCR value for the CPU. To use a hardware interrupt, set the three
sections beforehand by using software.
The interrupt vector table referenced during interrupt processing is assigned to addresses "FFFC00H" to
"FFFFFFH" in memory. These addresses are shared with software interrupts. Table D-2 shows the interrupt
causes, interrupt vectors, and interrupt control registers
64
CHAPTER 3 INTERRUPTS
3.5.1
Hardware Interrupt Operation
An internal resource that has the hardware interrupt request function has an interrupt
request flag and interrupt enable flag. The interrupt request flag indicates whether an
interrupt request exists, and the interrupt enable flag indicates whether the relevant
internal resource requests an interrupt to the CPU. The interrupt request flag is set
when an event occurs that is unique to the internal resource. When the interrupt enable
flag indicates "enable", the resource issues an interrupt request to the interrupt
controller.
■ Hardware Interrupt Operation
When two or more interrupt requests are received at the same time, the interrupt controller compares the
interrupt levels (IL) in ICR, selects the request at the highest level (the smallest IL value), then reports that
request to the CPU. If multiple requests are at the same level, the interrupt controller selects the request
with the lowest interrupt number. The relationship between the interrupt requests and ICRs is determined
by the hardware.
The CPU compares the received interrupt level and the ILM in the PS register. If the interrupt level is
smaller than the ILM value and the I bit of the PS register is set to "1", the CPU activates the interrupt
processing microcode after the currently executing instruction is completed. The CPU references the ISE
bit of the ICR of the interrupt controller at the beginning of the interrupt processing microcode, checks that
the ISE bit is "0" (interrupt), and activates the interrupt processing body.
The interrupt processing body saves 12 bytes (PS, PC, PCB, DTB, ADB, DPR, and A) to the memory area
indicated by SSB and SSP, fetches three bytes of interrupt vector and loads them onto PC and PCB,
updates the ILM of PS to a level value of the received interrupt, sets the S flag, then performs branch
processing. As a result, the interrupt processing program defined by the user is executed next.
Figure 3.5-1 illustrates the flow from the occurrence of a hardware interrupt until there is no interrupt
request in the interrupt processing program.
65
CHAPTER 3 INTERRUPTS
3.5.2
Occurrence and Release of Hardware Interrupt
Figure 3.5-1 shows the occurrence and release of hardware interrupt.
■ Occurrence and Release of Hardware Interrupt
Figure 3.5-1 Occurrence and Release of Hardware Interrupt
Microcode
PS
IR
I
ILM
Check
Comparator
PS
I
ILM
IR
:Processor status
:Interrupt enable flag
:Interrupt level mask register
:Instruction register
Peripheral
Enable FF
AND
Cause FF
Interrupt level IL
F2M C - 1 6 LX . C P U
Level comparator
F2MC-16LX bus
Register file
Interrupt
controller
1. An interrupt cause occurs in a peripheral.
2. The interrupt enable bit in the peripheral is referenced. If interrupts are enabled, the peripheral issues an
interrupt request to the interrupt controller.
3. Upon reception of the interrupt request, the interrupt controller determines the priority levels of
simultaneously requested interrupts. Then, the interrupt controller transfers the interrupt level of the
corresponding interrupt to the CPU.
4. The CPU compares the interrupt level requested by the interrupt controller with the ILM bit of the
processor status register.
5. If the comparison shows that the requested level is higher than the current interrupt processing level, the
I flag value of the same processor status register is checked.
6. If the check in step 5. shows that the I flag indicates interrupt enable status, the requested level is
written to the ILM bit. Interrupt processing is performed as soon as the currently executing instruction
is completed, then control is transferred to the interrupt processing routine.
7. When the interrupt cause of step 1. is cleared by software in the user interrupt processing routine, the
interrupt request is completed.
The time required for the CPU to execute the interrupt processing in steps 6. and 7. is shown below.
Interrupt start:
24 + 6 × (Table 3.3-2 machine cycles)
Interrupt return: 15 + 6 × (Table 3.3-2 machine cycles) RETI instruction
66
CHAPTER 3 INTERRUPTS
Table 3.5-1 Compensation Values for Interrupt Processing Cycle Count
Address pointed to by the stack pointer
Interpolation value [cycles]
External 8-bit
+4
External even-numbered address
+1
External odd-numbered address
+4
Internal even-numbered address
0
Internal odd-numbered address
+2
67
CHAPTER 3 INTERRUPTS
3.5.3
Multiple interrupts
As a special case, no hardware interrupt request can be accepted while data is being
written to the I/O area. For MB90390 Series, this includes the address ranges "00H" to
"BFH", ("3100H" to "31FFH", "3300H" to "33FFH",) "3500H" to "35FFH", "3700H" to
"37FFH", "3900H" to "39FFH", "3B00H" to "3BFFH", "3D00H" to "3DFFH" and "3F00H" to
"3FFFH". This is intended to prevent the CPU from operating falsely because of an
interrupt request issued while an interrupt control register for a resource is being
updated. If an interrupt occurs during interrupt processing, a higher-level interrupt is
processed first.
■ Multiple Interrupts
The F2MC-16LX CPU supports multiple interrupts. If an interrupt of a higher level occurs while another
interrupt is being processed, control is transferred to the high-level interrupt after the currently executing
instruction is completed. After processing of the high-level interrupt is completed, the original interrupt
processing is resumed. An interrupt of the same or lower level may be generated while another interrupt is
being processed. If this happens, the new interrupt request is suspended until the current interrupt
processing is completed, unless the ILM value or I flag is changed by an instruction.
The extended intelligent I/O service cannot be activated from multiple sources; while an extended
intelligent I/O service is being processed, all other interrupt requests or extended intelligent I/O service
requests are suspended.
Figure 3.5-2 shows the order of the registers saved in the stack.
Figure 3.5-2 Registers Saved in Stack
Word (16 bits)
MSB
LSB
"H"
SSP (SSP value before interrupt)
AH
AL
DPR
ADB
DTB
PCB
PC
PS
"L"
68
SSP (SSP value after interrupt)
CHAPTER 3 INTERRUPTS
3.6
Software Interrupts
In response to execution of a special instruction, control is transferred from the
program currently executed by the CPU to the interrupt processing program defined by
the user. This is called the software interrupt function. A software interrupt occurs
always when the software interrupt instruction is executed.
■ Software Interrupts
The CPU performs the following processing when a software interrupt occurs:
•
Saves the values in the PC, PS, AH, AL, PCB, DTB, ADB, and DPR registers of the CPU to the system
stack.
•
Sets "1" in the PS register. Interrupts are automatically disabled.
•
Fetches the corresponding interrupt vector value, then branches to the processing indicated by that
value.
A software interrupt request issued by the INT instruction has no interrupt request or enable flag. A
software interrupt request is always issued by executing the INT instruction.
The INT instruction does not have an interrupt level. Therefore, the INT instruction does not update ILM.
The INT instruction clears the I flag to suspend subsequent interrupt requests.
■ Structure of Software Interrupts
Software interrupts are handled within the CPU:
CPU.....Microcode: Interrupt processing step
■ List of MB90390 Interrupt Vectors
Table D-1 lists the Interrupt vectors.
As shown in Table D-1, software interrupts share the same interrupt vector area with hardware interrupts.
For example, interrupt request number INT 12 is used for external interrupt #0 to #7 of a hardware interrupt
as well as for INT #12 of a software interrupt. Therefore, external interrupt #0 and INT #12 call the same
interrupt processing routine.
■ Software Interrupt Operation
When the CPU fetches and executes the software interrupt instruction, the software interrupt processing
microcode is activated. The software interrupt processing microcode saves 12 bytes (PS, PC, PCB, DTB,
ADB, DPR, and A) to the memory area indicated by SSB and SSP. The microcode then fetches three bytes
of interrupt vector and loads them onto PC and PCB, resets the I flag, and sets the S flag. Then, the
microcode performs branch processing. As a result, the interrupt processing program defined by the user
application program is executed next.
Figure 3.6-1 shows the occurrence and release of software interrupt.
69
CHAPTER 3 INTERRUPTS
Figure 3.6-1 Occurrence and Release of Software Interrupt
➀
PS
F2MC-16LX bus
Register file
➁
Microcode
F2M C - 1 6 LX. C P U
I
S
B unit
IR
Queue
Fetch
PS
I
S
IR
B unit
:Processor status
:Interrupt enable flag
:Stack flag
:Instruction register
:Bus interface unit
Save
Instruction bus
RAM
1. The software interrupt instruction is executed.
2. Special CPU registers in the register file are saved according to the microcode corresponding to the
software interrupt instruction.
3. The interrupt processing is completed with the RETI instruction in the user interrupt processing routine.
■ Others
When the program counter bank register (PCB) is "FFH", the CALLV instruction vector area overlaps the
table of the INT #vct8 instruction. When designing software, ensure that the CALLV instruction does not
use the same address as that of the #vct8 instruction.
Table D-2 shows the interrupt causes, interrupt vectors, and interrupt control registers.
70
CHAPTER 3 INTERRUPTS
3.7
Extended Intelligent I/O Service (EI2OS)
The EI2OS function automatically transfers data between input and output and memory.
An interrupt processing program was conventionally used for such processing, but
EI2OS enables data transfer to be performed like DMA (direct memory access).
■ Extended Intelligent I/O Service (EI2OS)
EI2OS has the following advantages over the conventional method:
•
The program size can be small because it is not necessary to write a transfer program.
•
No internal register is used for transfer, eliminating the need for register saving and increasing the
transfer speed.
•
Transfer can be terminated from I/O, preventing unnecessary data from being transferred.
•
The buffer address may either be incremented or left unupdated.
•
The I/O register address may either be incremented or left unupdated.
At the end of EI2OS, processing automatically branches to an interrupt processing routine after the end
condition is set. Thus, the user can identify the end condition.
To implement EI2OS, the hardware is distributed in two blocks. Each block has the following registers and
descriptors.
•
Interrupt control register: Exists in the interrupt controller and indicates the ISD address.
•
Extended intelligent I/O service descriptor (ISD): Exists in RAM and holds the transfer mode, I/O
address, number of transfers, and buffer address.
Figure 3.7-1 shows the outline of extended intelligent I/O service.
71
CHAPTER 3 INTERRUPTS
Figure 3.7-1 Outline of Extended Intelligent I/O Service
Memory space
by IOA
I/O register
•••••••••••••••
I/O register
Peripheral
CPU
Interrupt request ➀
➂
ISD
➂
by ICS
➁
Interrupt control register
Interrupt controller
by BAP
➃
Buffer
➀ I/O requests transfer.
➁ The interrupt controller selects the
descriptor.
➂ The transfer source and destination
by
are read from the descriptor.
DCT
➃ Data is transferred between I/O and
memory.
Note:
The area that can be specified by IOA is between "000000H" and "00FFFFH".
The area that can be specified by BAP is between "000000H" and "FFFFFFH".
The maximum transfer count that can be specified by DCT is 65536.
■ Structure
EI2OS is handled by the following four sections:
Internal resources
Interrupt enable and request bits: Used to control interrupt requests from resources.
Interrupt controller
ICR: Assigns interrupt levels, determines the priority levels of simultaneously interrupt requests, and
selects the EI2OS operation.
CPU
I and ILM: Used to compare the interrupt request and current interrupt levels and to identify the
interrupt enable status
Microcode: EI2OS processing step
RAM
Descriptor: Describes the EI2OS transfer information.
72
CHAPTER 3 INTERRUPTS
3.7.1
Extended Intelligent I/O Service Descriptor (ISD)
The extended intelligent I/O service descriptor exists between "000100H" and "00017FH"
in built-in RAM, and consists of the following items:
• Data transfer control data
• Status data
• Buffer address pointer
■ Extended Intelligent I/O Service Descriptor (ISD)
Figure 3.7-2 shows the configuration of the extended intelligent I/O service descriptor.
Figure 3.7-2 Extended Intelligent I/O Service Descriptor Configuration
"H"
High-order 8 bits of data counter (DCTH)
Low-order 8 bits of data counter (DCTL)
High-order 8 bits of I/O address pointer (IOAH)
Low-order 8 bits of I/O address pointer (IOAL)
EI 2OS status (ISCS)
High-order 8 bits of buffer address pointer (BAPH)
000100 H + 8 × ICS
Medium-order 8 bits of buffer address pointer (BAPM)
ISD start address
Low-order 8 bits of buffer address pointer (BAPL)
"L"
■ Data Counter (DCT)
This is a 16-bit register that works as a counter corresponding to the number of data items transferred. This
counter is decremented by one before data transfer. EI2OS is terminated when this counter reaches "0".
Figure 3.7-3 is a diagram of the data counter configuration.
Figure 3.7-3 Data Counter Configuration
bit 15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
DCT
B15 B14 B13 B12 B11 B10 B09 B08 B07 B06 B05 B04 B03 B02 B01 B00 (Undefined when reset)
73
CHAPTER 3 INTERRUPTS
■ I/O Register Address Pointer (IOA)
This is a 16-bit register that indicates the low-order address (A15 to A00) of the buffer and I/O register
used for data transfer. The high-order address (A23 to A16) are all zeroes, and any I/O between addresses
"000000H" and "00FFFFH" can be specified. Figure 3.7-4 shows the I/O register address pointer
configuration.
Figure 3.7-4 I/O Register Address Pointer Configuration
bit 15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
IOA
A15 A14 A13 A12 A11 A10 A09 A08 A07 A06 A05 A04 A03 A02 A01 A00 (Undefined when reset)
■ Buffer Address Pointer (BAP)
This 24-bit register holds the address used for the next EI2OS transfer. BAP exists for each EI2OS channel.
Therefore, each EI2OS channel can be used for transfer with anywhere in the 16-Mbyte space. If the BF bit
of ISCS is set to "0" (update enabled), only the low-order 16 bits of BAP changes and BAPH does not
change.
74
CHAPTER 3 INTERRUPTS
EI2OS Status Register (ISCS)
3.7.2
This 8-bit register indicates the update direction (increment/decrement), transfer data
format (byte/word), and transfer direction of the buffer address pointer and the I/O
register address pointer. This register also indicates whether the buffer address pointer
or I/O register address pointer is updated or fixed.
■ EI2OS Status Register (ISCS)
Figure 3.7-5 is a diagram of the ISCS configuration.
Figure 3.7-5 ISCS Configuration
bit
7
6
5
Reserved Reserved Reserved
4
3
2
1
0
IF
BW
BF
DIR
SE
ISCS
(Undefined when reset)
Note: Always write "0" to bit7 to bit5 of ISCS.
Each bit is described below.
[bit4] IF: Specify whether the I/O register address pointer is updated or fixed.
0: The I/O register address pointer is updated after data transfer.
1: The I/O register address pointer is not updated after data transfer.
Note:
Only increment is allowed.
[bit3] BW: Specify the transfer data length.
0: Byte
1: Word
[bit2] BF: Specify whether the buffer address pointer is updated or fixed.
0: The buffer address pointer is updated after data transfer.
1: The buffer address pointer is not updated after data transfer.
Note:
Only the low-order 16 bits of the buffer address are updated. Only increment is allowed.
[bit1] DIR: Specify the data transfer direction.
0: I/O address pointer → Buffer address pointer
1: Buffer address pointer → I/O address pointer
75
CHAPTER 3 INTERRUPTS
[bit0] SE: Control the termination of the extended intelligent I/O service based on resource requests.
0: The extended intelligent I/O service is not terminated by a resource request.
1: The extended intelligent I/O service is terminated by a resource request.
76
CHAPTER 3 INTERRUPTS
3.8
Operation Flow of and Procedure for Using the Extended
Intelligent I/O Service (EI2OS)
Figure 3.8-1 shows the EI2OS operation flow. Figure 3.8-2 shows the EI2OS use flow.
■ EI2OS Operation Flow
Figure 3.8-1 EI2OS Operation Flow
BAP:
IOA:
ISD:
ISCS:
DCT:
ISE:
S1 and S0:
Interrupt request issued
from internal resource
ISE = 1
Buffer address pointer
I/O address pointer
EI2OS descriptor
EI2OS status
Data counter
EI2OS enable bit
EI2OS end status
NO
Interrupt sequence
YES
Reading ISD/ISCS
End request from resource
YES
SE = 1
NO
DIR = 1
YES
NO
Data indicated by IOA
⇓ (Data transfer)
Memory indicated by BAP
IF = 0
YES
NO
BF = 0
Data indicated by BAP
⇓ (Data transfer)
Memory indicated by IOA
Update value
depends on BW.
Updating IOA
Update value
depends on BW.
Updating BAP
YES
NO
Decrementing DCT
DCT = 00B
YES
NO
Setting S1 and S0 to "01B"
Setting S1 and S0 to "11B"
Setting S1 and S0 to "00B"
Clearing resource
interrupt request
Clearing ISE to "0"
CPU operation return
Interrupt sequence
77
CHAPTER 3 INTERRUPTS
Figure 3.8-2 EI2OS Use Flow
Processing by EI2OS
Processing by CPU
EI2OS initialization
Normal
termination
(Interrupt request)
AND (ISE = 1)
JOB execution
Data transfer
Re-setting of extended intelligent
I/O service
(Switching channels)
Processing data in buffer
The extended EI2OS execution time for each flow is described below.
● When data transfer continues (when the stop condition is not satisfied)
(Table 3.8-1 + Table 3.8-2) machine cycles
● When a stop request is issued from a resource
(36 + 6 × Table 3.8-3) machine cycles
● When the counting is completed
(Table 3.8-1 + Table 3.8-2 + 21 + 6 × Table 3.8-3) machine cycles
Table 3.8-1 Execution Time when the Extended EI2OS Continues
Set to "0"
ISCS SE bit
I/O address pointer
Set to "1"
Fixed
Updated
Fixed
Updated
Fixed
32
34
33
35
Updated
34
36
35
37
Buffer address pointer
78
CHAPTER 3 INTERRUPTS
Table 3.8-2 Data Transfer Compensation Values for Extended EI2OS Execution Time
Internal access
I/O address pointer
Buffer address pointer
Internal
access
B/E
O
B/E
0
+2
O
+2
+4
B: Byte data transfer
E: Even address word transfer
O: Odd address word transfer
Table 3.8-3 Compensation Values for Interrupt Handling Times
Address pointed to by the stack pointer
Interpolation value [cycles]
External 8-bit
+4
External even-numbered address
+1
External odd-numbered address
+4
Internal even-numbered address
0
Internal odd-numbered address
+2
79
CHAPTER 3 INTERRUPTS
3.9
Exceptions
The F2MC-16LX performs exception processing when the following event occurs:
■ Execution of an Undefined Instruction
Exception processing is fundamentally the same as interrupt processing. When an exception is detected
between instructions, exception processing is performed separately from ordinary processing. In general,
exception processing is performed as a result of an unexpected operation. Fujitsu recommends using
exception processing only for debugging or for activating emergency recovery software.
■ Exception Due to Execution of an Undefined Instruction
The F2MC-16LX handles all codes that are not defined in the instruction map as undefined instructions.
When an undefined instruction is executed, processing equivalent to the INT 10 software interrupt
instruction is performed. Specifically, the AL, AH, DPR, DTB, ADB, PCB, PC, and PS values are saved
into the system stack, and processing branches to the routine indicated by the interrupt number 10 vector. In
addition, the I flag is cleared and the S flag is set. The PC value saved in the stack is the address at which
the undefined instruction is stored. Processing can be restored by the RETI instruction, but is of no use,
however, because the same exception occurs again.
80
CHAPTER 4
DELAYED INTERRUPT
This chapter explains the functions and operations of
the delayed interrupt.
4.1 Outline of Delayed Interrupt Module
4.2 Delayed Interrupt Register
4.3 Delayed Interrupt Operation
81
CHAPTER 4 DELAYED INTERRUPT
4.1
Outline of Delayed Interrupt Module
The delayed interrupt source module is used to generate interrupts for switching tasks.
Using this module, interrupt requests to the F2MC-16LX CPU can be issued and
canceled by software.
■ Block Diagram of Delayed Interrupt
Figure 4.1-1 is a block diagram of the delayed interrupt source module.
Figure 4.1-1 Block Diagram
F2MC-16LX bus
Delayed interrupt cause issuance/cancellation decoder
Cause latch
■ Notes on Operation
This lock is set by writing "1" to the corresponding bit of DIRR, and is cleared by writing "0" to the same
bit. Therefore, interrupt processing is reactivated immediately after control returns from interrupt
processing, unless the software is designed so that the cause of the interrupt is cleared within the interrupt
processing routine.
82
CHAPTER 4 DELAYED INTERRUPT
4.2
Delayed Interrupt Register
DIRR controls issuance and cancellation of delayed interrupt requests. Writing "1" to
this register issues a delayed interrupt request, and writing "0" cancels the delayed
interrupt request. Upon a reset, the request is canceled.
■ Delayed Interrupt Cause Issuance/Cancellation Register (DIRR: Delayed Interrupt
Request Register)
Figure 4.2-1 Delayed Interrupt Cause/Cancel Register (DIRR)
R/W
X
-
Address
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
Initial value
00009FH
-
-
-
-
-
-
-
R0
XXXXXXX0B
-
-
-
-
-
-
-
R/W
:
:
:
Readable and writable
Undefined
Undefined bit
Table 4.2-1 Functional Explanation of Each Bit of the Delayed Interrupt Cause/Cancel Register (DIRR)
Bit name
bit15 to bit9
bit8
Function
-:
Undefined bit
• When these bits are read, the values are undefined.
• Writing to these bits does not affect operation.
R0:
Delayed interrupt
request output bit
•
•
•
•
This bit sets the generation/cancel of a delayed interrupt request.
When this bit is "1", a delayed interrupt request is output.
When this bit is "0", the delayed interrupt request is cleared.
When a reset is specified, interrupt causes are canceled (cleared to "0").
83
CHAPTER 4 DELAYED INTERRUPT
4.3
Delayed Interrupt Operation
When the CPU writes "1" to the relevant bit of DIRR by software, the request latch in the
delayed interrupt source module is set and an interrupt request is issued to the
interrupt controller.
■ Delayed Interrupt Occurrence
When the CPU writes "1" to the relevant bit of DIRR by software, the request latch in the delayed interrupt
source module is set and an interrupt request is issued to the interrupt controller. If this interrupt has the
highest priority or if there is no other interrupt request, the interrupt controller issues an interrupt request to
the F2MC-16LX CPU. The F2MC-16LX CPU compares the ILM bit of its internal CCR register and the
interrupt request, and starts the hardware interrupt processing microprogram as soon as the current
instruction is completed if the interrupt level of the request is higher than that of the ILM bit. The interrupt
processing routine for this interrupt is thus executed.
Figure 4.3-1 Delayed Interrupt Issuance
F2MC-16LX CPU
Delayed interrupt source moduleInterrupt controller
WRITE
Other requests
ICR yy
IL
CMP
CMP
DIRR
ICR xx
ILM
INTA
84
CHAPTER 5
CLOCKS
This chapter describes the clocks used by MB90390
series microcontrollers.
5.1 Clocks
5.2 Block Diagram of the Clock Generation Block
5.3 Clock Selection Registers
5.4 Clock Mode
5.5 Oscillation Stabilization Wait Time
5.6 Connection of an Oscillator or an External Clock to the
Microcontroller
5.7 Output of the main clock HCLK and HCLKX
85
CHAPTER 5 CLOCKS
5.1
Clocks
The clock generation block controls the operation of the internal clock that controls
operation of the CPU and peripheral functions. This internal clock is called the machine
clock. One internal clock cycle is called one machine cycle. Other clocks include a
clock generated by source oscillation, called an oscillation clock, and a clock generated
by the internal PLL oscillation, called a PLL clock.
■ Clocks
The clock generation block contains the oscillation circuit that generates the oscillation clock. An external
oscillator is attached to this circuit. The oscillation clock can also be supplied by inputting an external clock
to the clock generation block. The clock generation block also contains the PLL clock multiplier circuit,
which generates six clocks whose frequencies are multiples of the oscillation clock frequency. The clock
generation block controls the oscillation stabilization wait time and PLL clock multiplication as well as
internal clock operation by changing the clock with a clock selector.
● Oscillation clock (HCLK)
The oscillation clock is generated either from an external oscillator attached to the oscillation circuit or by
the input of an external clock.
● Main clock (MCLK)
The main clock, whose frequency is the oscillation clock frequency divided by 2, supplies the clock input
to the time-base timer and the clock selector.
● PLL clock (PCLK)
The PLL clock is obtained by multiplying the oscillation clock frequency with the internal PLL clock
multiplier circuit (PLL oscillation circuit). Selection can be made from among six different PLL clocks.
● Clock Modulator (CLOMO)
The clock modulator reduces the electromagnetic interference - EMI, by spreading the spectrum of the
clock signal over a wide range of different frequencies. The modulator provides two operation modes: 1)
phase modulation mode and 2) frequency modulation mode. Please refer to "CHAPTER 6 CLOCK
MODULATOR" for more detail.
86
CHAPTER 5 CLOCKS
● Machine clock (φ)
The machine clock controls the operation of the CPU and peripheral functions. One clock cycle is regarded
as one machine cycle (1/φ). An operating machine clock can be selected from among the main clock
(whose frequency is the source clock frequency divided by 2) and the other six clocks (whose frequencies
are multiples of the source clock frequency).
Note:
Although an oscillation clock of 3 MHz to 8 MHz can be generated if the operating voltage is 5 V, the
maximum operating frequency for the CPU and peripheral functions is 24 MHz. If a frequency
multiplier rate or the peak frequency of the clock modulator exceeds the operating frequency as
specified, devices will not operate correctly.
■ Clock Supply Map
Since the machine clock generated in the clock generation block is supplied as the clock that controls the
operation of the CPU and peripheral functions, the operation of the CPU and the peripheral functions is
affected by switching between the main clock and the PLL clock (clock mode) and by a change in the PLL
clock multiplier. Since some peripheral functions receive frequency-divided output from the time-base
timer, a peripheral unit can select the clock best suited for this operation. Figure 5.1-1 shows the clock
supply map.
87
CHAPTER 5 CLOCKS
Figure 5.1-1 Clock Supply Map
Peripheral function
4
Watchdog timer
8/16-bit PPG
PPG00 to PPG05
Pin
PPG10 to PPG15
Clock generation block
MCS
bit
8/16-bit PPG
Pin
CAN0 to CAN4
RX/TX
Pins
Time-base timer
TIN0/TIN1
1 2 3 4 6 8
16-bit reload
timer 0/1
PLL multiplier circuit
Pins
TOUT0/TOUT1
Pins
PCLK
SIN0/SIN1/SIN2/(SIN3)
Clock Selector
φC
UART0/UART1/
UART2(UART/3)
+
Serial I/O
Clock Modulator
X0
Pin
X1
Pin
System
clock
generation
circuit
HCLK
Divideby-2
Clock Selector
MCLK
Pins
...
SOT0/SOT1/SOT2/(SOT3)
Pins ...
SCK0/SCK1/SCK2/(SCK3)
Pins ...
φ
AN0 to AN14
10-bit ADC
(15 ch)
Pins ...
SGO
Pin
Sound Generator
SGA
Pin
16-bit free-run
timer 0/1
CPU
FRCK0/FRCK1
Pins
IN0 to IN5
16-bit input capture
(6 ch)
Output compare
(8 ch)
Pins ...
OUT0 to OUT7
Pins ...
PWM pins
Pin
SMC (6 ch)
HCLK
MCLK
PCLK
φ
φC
88
: Oscillation clock
: Main clock
: PLL clock
: Machine clock
: CAN0 to CAN4 clock
Pin
3
...
DVxx pins
...
Oscillation stabilization wait control
Note: I2C Interface is optional and not shown in this diagram
CHAPTER 5 CLOCKS
5.2
Block Diagram of the Clock Generation Block
The clock generation block consists of five blocks:
• System clock generation circuit
• PLL multiplier circuit
• Clock selector
• Clock selection register (CKSCR)
• Oscillation stabilization wait time selector
■ Block Diagram of the Clock Generation Block
Figure 5.2-1 shows a block diagram of the clock generation block.
Figure 5.2-1 Block Diagram of the Clock Generation Block
Low-Power Consumption Mode Control Register (LPMCR)
-
STP SLP SPL RST TMD CG1 CG0
RST
Pin
Interm.
cycle sel.
CPU intermittent
operation
selector
Pin highimpedance
control circuit
Pin highimpedance
control
Internal reset
generation
circuit
Internal
reset
CPU clock
control
circuit
Stop and
sleep signals
Standby
control
circuit
Stop signal
Interrupt
clearing
Peripheral
clock control
circuit
Clock
Selector
CS2
2
PLL multiplier circuit
Pin
HCLK
X1
Oscillation
stabilization
wait time
interval selector
2
Bit8 of PLL and
Special Configuration
Control Register
(PSCCR) : bit8
Peripheral
clock
Oscillation stabilization wait clear
Machine clock
X0
CPU
clock
Pin
System clock
generation circuit
Divideby-2
MCM WS1 WS0
-
MCS CS1 CS0
Clock Selection register (CKSCR)
Mainclock
Divideby-1024
Divideby-2
Divideby-4
Divideby-4
Divideby-4
Divideby-2
Time-base Timer
Watchdog Timer
Note: The Clock Modulator is not shown in this diagram, please refer to
chapter 6 for details.
89
CHAPTER 5 CLOCKS
● System clock generation circuit
The system clock generation circuit generates an oscillation clock (HCLK) from an external oscillator
attached to it. Alternatively, an external clock can be input to this circuit.
● PLL multiplier circuit
The PLL multiplier circuit multiplies the oscillation clock frequency through PLL oscillation and supplies a
clock whose frequency is a multiple of the oscillation clock frequency to the CPU clock selector.
● Clock selector
From among the main clock and six different PLL clocks, the clock selector selects the clock that is
supplied to the CPU and peripheral clock control circuits.
● Clock selection register (CKSCR)
The clock selection register is used to switch between the oscillation clock and a PLL clock and is also used
to select an oscillation stabilization wait time and a PLL clock multiplier.
● Oscillation stabilization wait time selector
This oscillation stabilization wait time selector selects an oscillation stabilization wait time for the
oscillation clock when the stop mode is released. Selection is made from among four different time-base
timer outputs. In all other cases, an oscillation stabilization wait time is not selected.
90
CHAPTER 5 CLOCKS
5.3
Clock Selection Registers
This section lists the clock selection registers and describes the function of each
register in detail.
■ Clock Selection Registers
Figure 5.3-1 shows the clock selection register.
Figure 5.3-1 Clock Selection Registers
bit
Address:
0000A1H
Reserved
bit
Address:
0 0 3 5 C FH
15
13
MCM WS1
12
11
10
9
8
WS0
Reserved
MCS
CS1
CS0
R/W
R/W
R/W
R
R/W
R/W
R/W
R/W
15
14
13
12
11
10
9
Reserved Reserved Reserved Reserved Reserved Reserved Reserved
-
R/W
W
R
X
-
14
-
-
-
W
W
W
Initial value
(CKSCR)
8
CS2
11111100B
Initial value
(PSCCR)
XXXX0000B
W
: Readable and Writable
: Write only
: Read only
: Undefined value
: Undefined
91
CHAPTER 5 CLOCKS
5.3.1
Clock Selection Register (CKSCR)
The clock selection register (CKSCR) is used to switch between the main clock and a
PLL clock and is also used to select an oscillation stabilization wait time and a PLL
clock multiplier.
■ Configuration of the Clock Selection Register (CKSCR)
Figure 5.3-2 shows the configuration of the clock selection register (CKSCR). Table 5.3-1 describes the
function of each bit of the clock selection register (CKSCR).
Figure 5.3-2 Configuration of the Clock Selection Register (CKSCR)
14
13
bit 15
Address:
0 0 0 0 A 1 H Reserved MCM WS1
12
11
10
9
8
WS0
Reserved
MCS
CS1
CS0
R/W
R/W
R/W
R/W
R/W
R/W
R
R/W
0
(LPMCR)
Initial value
11111100B
CS2(PLLC register:bit8)
CS2 CS1 CS0
Multiplier selection bits
The resulting clock for 4 and 5 MHz crystal
is given in parentheses.
0
0
0
1 x HCLK (4MHz / 5 MHz)*
0
0
1
2 x HCLK (8MHz / 10 MHz)*
0
1
0
3 x HCLK (12MHz / 15 MHz)*
0
1
1
4 x HCLK (16MHz / 20 MHz)*
1
0
0
2 x HCLK (8MHz / 10 MHz)
1
0
1
4 x HCLK (16MHz / 20 MHz)
1
1
0
6 x HCLK (24MHz / Set up Prohibition)
1
1
1
Prohibition
*: The setting exceeded 20MHz is disabled.
Machine clock selection bit
MCS
0
PLL clock selected.
1
Main clock selected.
Oscillation stabilization wait time selection bits
WS1 WS0
0
0
210/ HCLK(Approx. 256/204.8 μs)
0
1
213/ HCLK (Aprox. 2.05/1.64 ms)
1
0
215/ HCLK (Aprox. 8.19/6.55 ms)
1
1
2 17/ HCLK (Aprox. 32.77/26.22 ms)*
0
Machine clock indication bit
Running on a PLL clock.
1
Running on the main clock.
MCM
HCLK : Oscillation clock
R/W : Readable and writable
: Read only
R
: Initial value
The corresponding time interval for an oscillation clock
of 4 MHz / 5 MHz is given in parentheses.
* If a power-on reset occurs the oscillation stabilization
ait time is 218/HCLK (approx. 65.54 ms).
Note:
The machine clock selection bit is initialized to main clock selection at a reset.
92
CHAPTER 5 CLOCKS
Table 5.3-1 Clock Selection Register (CKSCR) (1/2)
Bit name
bit15
bit14
bit13
bit12
bit11
Function
Reserved
Note:
Always write "1" to this bit.
MCM:
Machine clock
indication bit
• This bit indicates whether the main clock or a PLL clock has been selected as the
machine clock.
• When this bit is "0", a PLL clock has been selected. When it is 1, the main clock has
been selected.
• If MCS = 0 and MCM = 1, the PLL clock oscillation stabilization wait time is in effect.
• Writing this bit has no effect on operation.
WS1 and WS0:
Oscillation
stabilization wait time
selection bits
Reserved
• These bits select an oscillation stabilization wait time of the oscillation clock when stop
mode was released, sub-clock mode changes to main clock mode, or PLL clock mode.
• These bits are initialized to "11B" by all reset causes.
Notes:
The oscillation stabilization wait time must be set to a value appropriate for the
oscillator used. See Section "7.2 Reset Cause and Oscillation Stabilization Wait
Times". These bits can be set to "00B" and "01B"only for main clock mode.
When PLL stop mode is returned to PLL clock mode, the oscillation stabilization wait
time requires 214/HCLK or more. When changing to PLL clock mode, these bits must
be set to "10B" or "11B".
wait time at 4 MHz
source oscillation
wait time at 5 MHz
source oscillation
WS1
WS0
0
0
approx. 256 s (210 counts of
source oscillation)
approx. 205 s (210 counts of
source oscillation)
0
1
approx. 2.05 ms (213 counts of
source oscillation)
approx. 1.64 ms (213 counts of
source oscillation)
1
0
approx. 8.19 ms (215 counts of
source oscillation)
approx. 6.56 ms (215 counts of
source oscillation)
1
1
approx. 33.77 ms (217 counts
of source oscillation)
approx. 26.21 ms (217 counts
of source oscillation)
Note:
Always write "1" to this bit.
93
CHAPTER 5 CLOCKS
Table 5.3-1 Clock Selection Register (CKSCR) (2/2)
bit10
Bit name
Function
MCS:
Machine clock
selection bit
• This bit specifies whether the main clock or a PLL clock is selected as the machine
clock.
• When this bit is "0", a PLL clock is selected. When it is 1, the main clock is selected.
• If this bit has been set to "1" and "0" is written to it, the oscillation stabilization wait
time for the PLL clock starts. As a result, the time-base timer is automatically cleared,
and the TBOF bit of the time-base timer control register (TBTC) is also cleared.
• For PLL clocks, the oscillation stabilization wait time is fixed at 214/HCLK (the
oscillation stabilization wait time is approx. 4.1 ms for an oscillation clock frequency of
4 MHz).
• When the main clock has been selected, the operating clock frequency is the oscillation
clock frequency divided by 2 (that is, the operating clock is 2 MHz when the oscillation
clock frequency is 4 MHz).
• This bit is initialized to "1" by all reset causes.
Note:
When the MCS bit is "1", write "0" to it only when the time-base timer interrupt is
masked by the TBIE bit of the time-base timer control register (TBTC) or the interrupt
level register (ILM).
•
•
•
•
bit9
bit8
CS1 and CS0:
Multiplier selection
bits
These bits and CS2 bit in PSCCR register select a PLL clock multiplier.
Selection can be made from among six different multipliers.
These bits are initialized to "00B"by all reset causes.
Recommended settings of CS2 to CS0:
CS2
CS1
CS0
0
0
0
× 1 For machine clock up to 20MHz *1
0
0
1
× 2 For machine clock up to 20MHz *1
0
1
0
× 3 For machine clock up to 20MHz *1
0
1
1
× 4 For machine clock up to 20MHz *1
1
0
0
× 2 For machine clock above 20MHz *1
1
0
1
× 4 For machine clock above 20MHz *1
1
1
0
× 6 For machine clock above 20MHz *1
1
1
1
× 8 *2 For machine clock above 20MHz *1
PLL clock multiplier
*1 : Refer to the AC Characteristics Section in the Data Sheet.
*2 : Not specified for all devices. Refer to the AC Characteristics Section in the Data Sheet.
Note:
When the MCS or MCM bit is "0", writing to these bits is not allowed. Write to the
CS2, CS1 and CS0 bits only after setting the MCS bit to "1" (main clock mode).
HCLK: Oscillation clock
94
CHAPTER 5 CLOCKS
5.3.2
PLL and Special Configuration Control Register (PSCCR)
The PLL and Special Configuration Control Register adds the selection of a PLL clock
multiplier.
■ Configuration of the PLL and Special Configuration Control Register (PSCCR)
Figure 5.3-3 shows the configuration of the PLL and Special Configuration Control Register (PSCCR).
Table 5.3-2 describes the function of each bit of the PLL and Special Configuration Control Register
(PSCCR).
Figure 5.3-3 Configuration of the PLL and Special Configuration Control Register (PSCCR)
14
13
12
11
bit 15
Address:
0 0 3 5 C F H Reserved Reserved Reserved Reserved Reserved
-
-
-
-
W
10
9
Reserved Reserved
W
W
8
Initial value
CS2
(PSCCR)
W
CS2
Additional multiplier selection bit
0
PLL clock multiplier x1, x2, x3, x4 (depending
on the setting of the CS1 and CS0 bits of CKSCR)
1
PLL clock multiplier x2, x4, x6, x8 (depending
on the setting of the CS1 and CS0 bits of CKSCR)
Reserved
0
Reserved
0
Reserved
0
W
X
-
XXXX0000 B
Reserved bit
Always write "0" to this bit
The value read from this bit is always "X".
Reserved bit
Always write "0" to this bit
The value read from this bit is always "X".
Reserved bit
Always write "0" to this bit
The value read from this bit is always "X".
Reserved
Reserved bits
XXXX
Always write "0" to this bit
The value read from these bit is always "X".
: Write only
: Undefined value
: Undefined
: Initial value
95
CHAPTER 5 CLOCKS
Table 5.3-2 PLL and Special Configuration Control Register (PSCCR)
Bit name
bit15
to
bit9
bit8
Function
Reserved:
Reserved bit
• These bits are reserved bits.
• Always write "0" to these bits.
• Reading these bits always returns "X".
CS2:
Multiplier selection
bit2
• This bit and CS1 and CS0 bits of the Clock selection register (CKSCR) select a PLL
clock multiplier.
• About the relationship between setting CS2, CS1 and CS0 bits and the PLL clock
multiplier selection, please see Table 5.3-1.
• This bit is initialized to "0" by all reset causes.
• Reading this bit always returns "X".
Note:
When the MCS or MCM bit is "0", changing the setting of this bit is not allowed.
Change this bit only after setting the MCS bit to "1" and waiting for MCM = 1 (main
clock mode).
Note:
The PSCCR register is a write-only register, so the read value is different from the write value. Therefore, instructions
that perform a read-modify-write (RMW) instructions, such as the INC/DEC instruction, cannot be used.
96
CHAPTER 5 CLOCKS
5.4
Clock Mode
Two clock modes are provided: main clock mode and PLL clock mode.
■ Main Clock Mode and PLL Clock Mode
● Main clock mode
In main clock mode, a clock whose frequency is the oscillation clock frequency divided by 2 is used as the
operating clock for the CPU and peripheral resources, and the PLL clocks are disabled.
● PLL clock mode
In PLL clock mode, a PLL clock is used as the operating clock for the CPU and peripheral resources. A
PLL clock multiplier is selected with the clock selection register (CKSCR: CS1 and CS0) and the PLL and
special configuration control register (PSCCR: CS2).
■ Clock Mode Transition
Transition among main clock mode, and PLL clock mode is performed by writing to the MCS bit of the
clock selection register (CKSCR).
● Transition from main clock mode to PLL clock mode
When the MCS bit of the clock selection register (CKSCR) is rewritten from "1" to "0" in main clock
mode, switching from the main clock to a PLL clock occurs after the PLL clock oscillation stabilization
wait time (214/HCLK).
● Transition from PLL clock mode to main clock mode
When the MCS bit of the clock selection register (CKSCR) is rewritten from "0" to "1" in PLL clock mode,
switching from the PLL clock to the main clock occurs when the edges of the PLL clock and the main
clock coincide (after 1 to 8 PLL clocks).
Note:
Even though the MCS bit of the clock selection register (CKSCR) is rewritten, machine clock
switching does not occur immediately. When operating a resource that depends on the machine
clock, confirm that machine clock switching has been performed by referring to the MCM bit of the
clock selection register (CKSCR) before operating the resource.
In attempting to switch the clock mode, do not attempt to switch to another clock mode or low-power
consumption mode until the first switching is completed. The MCM bit of the clock selection register
(CKSCR) indicate that switching is completed.
■ Selection of a PLL Clock Multiplier
Writing a value from "00B" to "11B" to the CS1 and CS0 bits of the clock selection register (CKSCR) and
"0" or "1" to the CS2 bit of the PLL and special configuration control register (PSCCR) selects a PLL clock
multiplier of 1 to 4, 6 or 8 (refer to Table 5.3-1 bit8 and bit9).
97
CHAPTER 5 CLOCKS
■ Machine Clock
The machine clock may be a PLL clock output from the PLL multiplier circuit or a clock whose frequency
is the source oscillation frequency divided by 2. This machine clock is supplied to the CPU and peripheral
functions. The main clock or PLL clock can be selected by writing to the MCS bit of the clock selection
register (CKSCR).
■ Clock Modulator
For using the clock modulator, please refer to "CHAPTER 6 CLOCK MODULATOR".
Figure 5.4-1 shows the status change diagram for machine clock selection.
Figure 5.4-1 Status Change Diagram for Machine Clock Selection
Main
MCS = 1
MCM = 1
CS1, CS0 = XX
CS2 = x
(1)
(6)
(8)
(7)
(9)
Main
PLLx
MCS = 0
MCM = 1
(10)
(11)
(2)
CS1, CS0 = XXB (3)
CS2 = x
(4)
(5)
(7)
CS1, CS0 = 00B
CS2 = 0
(7)
(7)
(6)
(6)
(7)
CS1, CS0 = 11B
CS2 = 0
PLL4A: Multiplied
MCS = 0
MCM = 0
(6)
PLL6
Main
MCS = 1
MCM = 0
CS1, CS0 = 10B
CS2 = 1
(7)
(6) CS1, CS0 = 00B
CS2 = 1
PLL4A Main
MCS = 1
MCM = 0
CS1, CS0 = 01B
CS2 = 1
CS1, CS0 = 10B
CS2 = 0
PLL4: Multiplied
MCS = 0
MCM = 0
(6)
(7)
PLL2A: Multiplied
MCS = 0
MCM = 0
PLL2A Main
MCS = 1
MCM = 0
CS1, CS0 = 00B
CS2 = 1
CS1, CS0 = 01B
CS2 = 0
PLL3: Multiplied
MCS = 0
MCM = 0
PLL4
Main
MCS = 1
MCM = 0
CS1, CS0 = 11B
CS2 = 0
98
PLL2: Multiplied
MCS = 0
MCM = 0
PLL3
Main
MCS = 1
MCM = 0
CS1, CS0 = 10B
CS2 = 0
(7)
(6) CS1, CS0 = 00B
CS2 = 0
PLL2
Main
MCS = 1
MCM = 0
CS1, CS0 = 01B
CS2 = 0
(7)
PLL1: Multiplied
MCS = 0
MCM = 0
PLL1
Main
MCS = 1
MCM = 0
PLL6: Multiplied
MCS = 0
MCM = 0
(6)
PLL8
Main
MCS = 1
MCM = 0
CS1, CS0 = 11B
CS2 = 1
CS1, CS0 = 01B
CS2 = 1
CS1, CS0 = 10B
CS2 = 1
PLL8: Multiplied
MCS = 0
MCM = 0
(6)
CS1, CS0 = 11B
CS2 = 1
CHAPTER 5 CLOCKS
(1)
Writing "0" to the MCS bit
(2)
End of PLL clock oscillation stabilization wait & CS2 = 0 & CS1, CS0 = 00B
(3)
End of PLL clock oscillation stabilization wait & CS2 = 0 & CS1, CS0 = 01B
(4)
End of PLL clock oscillation stabilization wait & CS2 = 0 & CS1, CS0 = 10B
(5)
End of PLL clock oscillation stabilization wait & CS2 = 0 & CS1, CS0 = 11B
(6)
Writing "1" to the MCS bit (including watchdog timer reset)
(7)
Timing of synchronization between the PLL clock and the main clock
(8)
End of PLL clock oscillation stabilization wait & CS2 = 1 & CS1, CS0 = 00B
(9)
End of PLL clock oscillation stabilization wait & CS2 = 1 & CS1, CS0 = 01B
(10)
End of PLL clock oscillation stabilization wait & CS2 = 1 & CS1, CS0 = 10B
(11)
End of PLL clock oscillation stabilization wait & CS2 = 1 & CS1, CS0 = 11B
MCS
: Machine clock selection bit of the clock selection register (CKSCR)
MCM
: Machine clock indication bit of the clock selection register (CKSCR)
CS1, CS0
: Multiplier selection bits of the clock selection register (CKSCR)
CS2
: Multiplier selection bit of the PLL and special configuration control register (PSCCR)
Note:
The initial value for the machine clock setting is main clock (MCS of CKSCR = 1).
99
CHAPTER 5 CLOCKS
5.5
Oscillation Stabilization Wait Time
When the power is turned on or when stop mode is released an oscillation stabilization
wait time is required after oscillation begins because there is no oscillation. When
switching from the main clock to a PLL clock occurs, an oscillation stabilization wait
time is also required after PLL oscillation starts.
■ Oscillation Stabilization Wait Time
Ceramic and crystal oscillators generally require several milliseconds to stabilize at their natural frequency
(oscillation frequency) when oscillation starts. For this reason, CPU operation is not allowed immediately
after oscillation starts but is allowed only after full oscillation stabilization. After the oscillation
stabilization wait time has elapsed, the clock is supplied to the CPU. Because the oscillation stabilization
time depends on the type of oscillator (crystal, ceramic, etc.), the proper oscillation stabilization wait time
for the oscillator used must be selected. An oscillation stabilization wait time is selected by setting the
clock selection register (CKSCR).
When switching from the main clock to a PLL clock occurs, the CPU continues to operate on the main
clock during the PLL oscillation stabilization wait time. After this interval, the operating clock switches to
the PLL clock.
Figure 5.5-1 shows the operation immediately after oscillation starts.
Figure 5.5-1 Operation Immediately after Oscillation Starts
Oscillator-activated
oscillation time
Oscillation stabilization wait interval
X1
Start of oscillation
100
Stable oscillation
Normal operation
start or switching to
PLL clock
CHAPTER 5 CLOCKS
5.6
Connection of an Oscillator or an External Clock to the
Microcontroller
The MB90390 series microcontroller contains a system clock generation circuit.
Connecting an external oscillator to this circuit generates the system clock.
Alternatively, an externally generated clock can be input to the microcontroller.
■ Connection of an Oscillator or an External Clock to the Microcontroller
● Example of connecting a crystal or ceramic oscillator to the microcontroller
Connect a crystal or ceramic oscillator as shown in the example in Figure 5.6-1.
Figure 5.6-1 Example of Connecting a Crystal or Ceramic Oscillator to the Microcontroller
MB90390 series
X0
X1
101
CHAPTER 5 CLOCKS
● Example of connecting an external clock to the microcontroller
As shown in the example in Figure 5.6-2, connect an external clock to pin X0. Pin X1 must be open.
Figure 5.6-2 Example of Connecting an External Clock to the Microcontroller
MB90390 series
X0
~
102
X1
open
CHAPTER 5 CLOCKS
5.7
Output of the main clock HCLK and HCLKX
For the control of output of the main clock HCLK and HCLKX, the clock output Enable
Register is used.
■ Clock Output Enable Register
Figure 5.7-1 Clock Output Enable Register (CKOE)
bit
Address:
0 0 0 0 3 FH
15
14
13
12
11
10
-
-
-
-
-
-
-
-
-
-
-
-
9
8
CKXOE CKOE
R/W
CKOE
HCLK : Oscillation clock
HCLKX : Inverted Oscillation clock
: Readable and writable
R/W
: Undefined value
X
: Undefined
: Initial value
Initial value
X X X X X X 0 0B
R/W
HCLK output enable
0
HCLK output is disabled
1
HCLK output is enabled
CKXOE
0
HCLKX output enable
HCLKX output is disabled
1
HCLKX output is enabled
Table 5.7-1 Function of Each Bit of the Clock Output Enable Register
Bit name
Function
bit15 to
bit10
Undefined
-
bit9
CKXOE
If this bit is set to "1" the HCLKX output on pin 92 (P97) is enabled. If it is
set to "0" the HCLKX output is disabled
bit8
CKOE
If this bit is set to "1" the HCLK output on pin 91 (PB7) is enabled.
If it is set to "0" the HCLK output is disabled
103
CHAPTER 5 CLOCKS
104
CHAPTER 6
CLOCK MODULATOR
This chapter provides an overview of the Clock
Modulator and its features. It describes the register
structure and operation of the Clock Modulator.
Notes: • Do not use frequency modulation with
MB90F394H
• Do not use CAN message buffer RAM and clock
modulation at the same time with MB90F394H,
MB90V390H and MB90V390HA.
6.1 Overview of Clock Modulator
6.2 Register Description of Clock Modulator
6.3 Registers of Clock Modulator
6.4 Application Note of the Clock Modulator
105
CHAPTER 6 CLOCK MODULATOR
6.1
Overview of Clock Modulator
This section gives an overview of the Clock Modulator.
■ Overview
The clock modulator is intended for the reduction of electromagnetic interference - EMI, by spreading the
spectrum of the clock signal over a wide range of frequencies.
The modulator offers two modes: 1) phase modulation mode and 2) frequency modulation mode
In both cases the module is fed with an unmodulated reference clock with frequency F0, provided by the
PLL circuit. This reference clock is phase modulated by a triangular waveform or frequency modulated,
controlled by a random signal.
In general, the frequency modulation mode leads to better EMI behavior than phase modulation mode.
The mean frequency of the modulated clock is equal to the reference clock frequency F0.
Figure 6.1-1 Frequency Spectrum of the Modulated Clock (Fundamentals Only)
modulation range
frequency
Fmin
F0
Fmax
■ Modulation Degree and Frequency Resolution in Frequency Modulation Mode
Maximum and minimum frequencies (Fmax and Fmin) of the modulated clock are well defined by the
modulation degree parameter. Furthermore the resolution of the modulation range is selectable in 7 steps
from "L" (1) to "H" (7). Higher resolution implies a finer granularity of discrete frequencies in the spectrum
of the modulated clock but less possible modulation degrees.
In general the highest possible frequency resolution combined with the highest possible modulation degree
results in the highest EMI reduction. But for some cases lower modulation degrees may result in a better
EMI behavior. Please refer to the table of possible settings in Table 6.3-4.
106
CHAPTER 6 CLOCK MODULATOR
6.2
Register Description of Clock Modulator
Clock Modulator has the following two registers.
• Clock Modulation Parameter Register
• Clock Modulation Control Register
■ Clock Modulator Registers
bit
Address: 0035C0 H
Address: 0035C2 H
15
0
CMPR
Parameter Register
CMCR
Control/Status Register
107
CHAPTER 6 CLOCK MODULATOR
6.3
Registers of Clock Modulator
This section lists the clock modulator registers and describes the function of each
register in detail.
■ Registers of Clock Modulator
Figure 6.3-1 Registers of Clock Modulator
Address: bit 7
0035C0H
6
5
4
3
2
1
0
MP7 MP6 MP5 MP4 MP3 MP2 MP1 MP0
CMPRL (lower)
Initial value
1 1 1 1 1 1 0 1B
R/W R/W R/W R/W R/W R/W R/W R/W
bit 15
0035C1H
108
13
12
11
10
9
8
-
-
MP13 MP12 MP11 MP10 MP9 MP8
-
-
R/W R/W R/W R/W R/W R/W
bit 7
0035C2H
14
6
5
4
3
ReReReserved served served
-
R/W R/W R/W R/W
-
PMOD
2
1
0
FMOD
FMOD PDX
RUN
R
R/W R/W
CMPRH (upper)
Initial value
X X 0 0 0 0 0 1 0B
CMCR
Initial value
0 0 0 1 X 0 0 0B
CHAPTER 6 CLOCK MODULATOR
6.3.1
Clock Modulator Control Register (CMCR)
The Clock Modulator Control Register (CMCR) has the following functions:
• Set the modulator to power down mode
• Modulator enable/disable in phase or frequency modulation mode
• Indicates the status of the modulator
■ Clock Modulator Control Register (CMCR)
Figure 6.3-2 Configuration of the Clock Modulator Control Register (CMCR)
bit 7
Address:
0035C2H
6
5
4
3
Re- RePMOD Reserved served served
-
R/W R/W R/W R/W
-
2
1
0
FMOD
FMOD PDX
RUN
R
R/W R/W
CMCR
Initial value
0 0 0 1 X 0 0 0B
bit 0
PDX
Power down bit
0
power down mode
1
power up mode
bit 1
FMOD
Frequency modulation enable bit
0
Frequency modulation mode disabled
1
Frequency modulation mode enabled
bit 2
FMOD
RUN
Modulator status in frequency modulation mode
0
Clock frequency unmodulated or phase modulated
1
Clock frequency modulated
bit 4 to bit 6
Reserved
Reserved
bit 4
bit 5, bit 6
Always write "1" to this bit
Always write "0" to these bit
bit 7
PMOD
R/W
R
X
-
:
:
:
:
Readable and writable
Read only
Undefined value
Undefined
:
Initial value
Phase modulation enabled
0
Phase modulation disabled
1
Phase modulation enabled
The clock modulator offers two different operation modes:
• phase modulation
• frequency modulation
In general frequency modulation results in better EMI behavior.
The phase modulation mode can be enabled with just one bit (PMOD). There is no additional configuration
necessary.
The remaining bits (FMODRUN, FMOD, PDX) control or indicate the status of the frequency modulation
mode. Frequency modulation mode needs some additional configuration (CMPR register).
109
CHAPTER 6 CLOCK MODULATOR
■ Clock Modulator Control Register Contents
Table 6.3-1 Function of Each Bit of the Clock Modulator Control Register (1/3)
Bit name
Function
PMOD:
Phase modulation
enable bit
Writing "0": Phase modulation disabled (default).
Writing "1": Modulator enabled in phase modulation mode, MCU is running with phase
modulated clock
• To enable the modulator in phase modulation mode, PMOD must be set to "1".
For phase modulation mode, the modulator must remain in power down mode. I.e.
PDX must be set to "0".
• Before the modulator can be enabled, the PLL must deliver a stable reference clock
(PLL lock time must be elapsed - refer to the CLOCK chapter in the hardware
manual).
• The specified PLL frequency range for phase modulation mode is 15MHz to
25MHz.
• Whenever the PLL output frequency is changed or the PLL is switched OFF e.g. in
power down modes, the modulator must be disabled before → PMOD=0 and 4 NOP
cycles must follow the PMOD-bit access.
• After enabling the phase modulation mode, the clock switches immediately to
modulated clock without glitches in the clock signal.
Please refer to the application note for a description of the recommended startup
sequence.
• The modulator must not be set to phase modulation and frequency modulation mode
at the same time (PMOD=1 and FMOD=1, PDX=1). Before the modulator can be
enabled in phase modulation mode (PMOD=1), the FMOD, FMODRUN and PDX
bit must be "0".
• The FMODRUN status flag is "0" if the modulator is enabled in phase modulation
mode.
The status of the clock signal is indicated by PMOD. PMOD=1 clock is phase
modulated.
• The pulse width of the phase modulated clock signal can vary ± 1.2 ns.
E.g. at F0 = 20 MHz unmodulated input clock, T0 = 50ns. Tmodmin = 50ns - 1.2 ns
= 48.8 ns → Fmodmax = 1/48.8 ns = 20.49 MHz.
bit6, bit5
Reserved
Always write "0" to these bits.
bit4
Reserved
Always write "1" to this bit.
bit3
Undefined
bit7
110
-
CHAPTER 6 CLOCK MODULATOR
Table 6.3-1 Function of Each Bit of the Clock Modulator Control Register (2/3)
Bit name
Function
"0": MCU is running with unmodulated or phase modulated clock
"1": MCU is running with frequency modulated clock
• FMODRUN indicates the status of the modulator output clock in frequency
modulation mode (FMOD=1). If the output clock is frequency modulated,
FMODRUN is set to "1", otherwise FMODRUN is set to "0".
• FMODRUN does not indicate a phase modulated clock (PMOD=1). If the modulator
is enabled in phase modulation mode, FMODRUN is set to "0".
• After enabling the frequency modulation mode by setting FMOD to "1", the
modulator is calibrated. During this time, the clock is unmodulated. Therefore it
takes several μs before the output clock switches to modulated clock and the
FMODRUN bit is set to "1". The calibration time depends on the frequency of the
oscillator (refer to the table).
bit2
FMOD RUN:
Modulator status
in frequency
modulation mode
bit
Oscillator
Fc
Calibration time
4 MHz
64.00 μs
5 MHz
51.20 μs
6 MHz
42.67 μs
calibration time = 256/Fc
• During normal operation, after calibration is finished, the clock is not switched to
unmodulated clock anymore.
• Due to the synchronization of the FMOD signal and the synchronized switching to
unmodulated clock, it takes less than 9 × T0 (input clock period) before FMODRUN
changes to "0" and the clock switches to unmodulated clock after the modulator is
disabled.
• The FMODRUN bit is read only. Writing to FMODRUN has no effect.
• Before changing the parameter register CMPR, the modulator must be disabled →
FMOD=0 and FMODRUN=0.
111
CHAPTER 6 CLOCK MODULATOR
Table 6.3-1 Function of Each Bit of the Clock Modulator Control Register (3/3)
Bit name
bit1
bit0
Function
FMOD:
Frequency
modulation
enable bit
"0": Frequency modulation disabled.
"1": Frequency modulation enabled.
Note: Do not set this bit to "1" with MB90F394H.
• To enable the modulator in frequency modulation mode, FMOD must be set to "1".
• Before the modulator can be enabled, the PLL must deliver a stable reference clock
(PLL lock time must be elapsed).
• The specified PLL frequency range for frequency modulation mode is 15 MHz to 25
MHz.
• Each PLL output frequency offers a set of possible modulation parameters. The
selected setting (CMPR register) and the PLL frequency must match.
Please refer to the CMPR register description.
• Whenever the PLL output frequency is changed or the PLL is switched OFF e.g. in
power down modes, the modulator must be disabled before → FMOD=0 and
FMODRUN=0.
• Before the modulator can be enabled, it must be switched from power down to active
mode by setting PDX to "1". And the startup time of 6 μs must be awaited.
Please refer to the application note for a description of the recommended startup
sequence.
• Before the modulator can be enabled in frequency modulation mode, a proper setting
must be selected via the parameter register CMPR.
• The modulator must not be set to frequency modulation and phase modulation mode
at the same time (FMOD=1, PDX=1 and PMOD=1). Before the modulator can be
enabled in frequency modulation mode (FMOD=1, PDX=1), the PMOD bit must be
set to "0".
• After enabling the frequency modulation mode by setting FMOD to "1", the
modulator is calibrated. During this time, the clock is unmodulated. Therefore the
output clock does not switch immediately to modulated clock. The status of the
clock (frequency modulated / unmodulated) is indicated by the FMODRUN status
bit. Please refer to the FMODRUN bit description.
• Due to the synchronization of the FMOD signal and the synchronized switching to
unmodulated clock, it takes less than 9 × T0 (input clock period) before the clock
switches to unmodulated clock after the modulator is disabled. The modulator can be
disabled at any time.
• Before changing the parameter register CMPR, the modulator must be disabled →
FMOD=0 and FMODRUN=0.
PDX:
Power down bit
"0": Power down mode
"1": Power up
• PDX is the power down signal for the modulator. Before the frequency modulation
mode can be enabled, this bit must be set to "1" and the startup time of 6 μs must be
awaited. Please refer to the application note for a description of the recommended
startup sequence.
• For phase modulation mode (PMOD bit), the modulator must remain in power down
mode. I.e. PDX must be set to "0".
• Before switching to power down mode (PDX=0), the modulator must be disabled →
FMOD=0 and FMODRUN=0.
Figure 6.3-2 shows the status of the modulator.
112
CHAPTER 6 CLOCK MODULATOR
Table 6.3-2 States of the Modulator
PMOD
FMOD
PDX
FMODRUN
(read only)
modulator disabled
0
0
0
0
modulator enabled in phase modulation mode,
modulator is running
1
0
0
0
modulator power on,
waiting modulator startup time (> 6 μs)
0
0
1
0
modulator enabled in frequency modulation mode,
modulator is calibrating, modulation not active
0
1
1
0
modulator is running in frequency modulation mode
modulation is active
0
1
1
1
others not allowed
113
CHAPTER 6 CLOCK MODULATOR
6.3.2
Clock Modulation Parameter Register (CMPR)
The Modulation Parameter Register (CMPR) determines the modulation degree in
frequency modulation mode.
■ Modulation Parameter Register
Figure 6.3-3 Modulation Parameter Register
Address:
0035C0H
bit 7
6
5
4
3
2
1
0
MP7 MP6 MP5 MP4 MP3 MP2 MP1 MP0
CMPRL (lower)
Initial value
1 1 1 1 1 1 0 1B
R/W R/W R/W R/W R/W R/W R/W R/W
bit 15
0035C1H
14
13
12
11
10
9
8
MP13 MP12 MP11 MP10 MP9 MP8
R/W R/W R/W R/W R/W R/W
R/W
X
CMPRH (upper)
Initial value
X X 0 0 0 0 1 0B
: Readable and writable
: Undefined value
: Undefined
• The modulation parameter determines the degree of modulation and the maximal and minimal occurring
frequencies in the modulated clock. Please refer to the application note for a description of an approach
to select the optimal setting.
• Each set of possible modulation parameters refers to a particular PLL frequency. The PLL frequency
and the selected parameter must match. Please refer to Table 6.3-3.
• The modulation parameter affects only the frequency modulation mode. Phase modulation mode has a
fixed setting which cannot be changed.
Note:
The modulation parameter must be changed only when the modulator is disabled and the RUN flag
is "0" (FMOD=0, FMODRUN=0).
114
CHAPTER 6 CLOCK MODULATOR
■ Modulation Parameter Register Contents
Table 6.3-3 Function of Each Bit of the Modulation Parameter Register (CMPR)
Bit name
bit15,
bit14
Function
Undefined
bit13 to
bit0
MP13 to MP0:
Modulation
Parameter bits
Depending on the PLL frequency the following modulation parameter settings are
possible. The corresponding CMPR register value is stated in the most right column.
n periods
reference clock
+ phase skew
n periods
modulated clock
n periods
F0:
Frequency of unmodulated input clock (PLL frequency)
T0:
Period of unmodulated input clock (PLL clock period)
resolution:
resolution of frequencies in the modulated clock. "L" (1) to "H" (7)
Fmin:
minimal frequency occurring in the frequency modulated clock
Fmax:
maximal frequency occurring in the frequency modulated clock
phase skew:
The maximal phase shift of the modulated clock relative to the unmodulated
reference clock in terms of clock periods of the unmodulated clock.
Example: phase skew=1.44
In worst case, a sequence of n periods of the modulated clock can be 1.44 × T0
shorter or 1.44 × T0 longer than a sequence of n periods of the unmodulated
reference clock.
n can be any number > 50 periods
phase skew 50:
phase skew for sequences with n<= 50 periods
CMPR:
register setting of the CMPR register
115
CHAPTER 6 CLOCK MODULATOR
Note:
NOT ALL SETTINGS ARE ALLOWED ON EVERY DEVICE!
Please consider the actual maximal allowed clock frequency of the MCU (refer to the data sheet).
E.g. if the maximal clock frequency of the device is 25MHz, the setting F0=15MHz, resolution=7,
moddegree=2 is not allowed, because the maximal occurring frequency in the modulated clock is
28.33 MHz, which is above the allowed 25MHz.
Table 6.3-4 lists the modulation parameter settings.
Table 6.3-4 Modulation Parameter Settings (1/5)
Fmin (MHz)
Fmax
(MHz)
± phase
skew
50
[periods]
± phase
skew
Min/Max
[periods]
CMPR
F0 (MHz)
resolution
mod
degree
15
1
1
14.09
16.03
0.27
0.72
027FH
15
1
2
13.69
16.58
0.53
1.44
047EH
15
1
3
13.31
17.18
0.8
2.16
067DH
15
1
4
12.95
17.81
1.06
2.88
087CH
15
1
5
12.61
18.50
1.33
3.59
0A7BH
15
1
6
12.29
19.24
1.59
4.31
0C7AH
15
1
7
11.98
20.05
1.86
5.03
0E79H
15
1
8
11.69
20.92
2.13
5.75
1078H
15
1
9
11.41
21.87
2.39
6.47
1277H
15
1
10
11.15
22.92
2.66
7.19
1476H
15
1
11
10.90
24.07
2.92
7.91
1675H
15
1
12
10.65
25.34
3.19
8.63
1874H
15
1
13
10.42
26.75
3.45
9.34
1A73H
15
1
14
10.20
28.33
3.72
10.06
1C72H
15
1
15
9.99
30.11
3.98
10.78
1E71H
15
1
16
9.78
32.12
4.25
11.5
2070H
15
2
1
13.69
16.58
0.39
1.02
02BEH
15
2
2
12.95
17.81
0.78
2.03
04BCH
15
2
3
12.29
19.24
1.17
3.05
06BAH
15
2
4
11.69
20.92
1.56
4.06
08B8H
15
2
5
11.15
22.92
1.95
5.08
0AB6H
15
2
6
10.65
25.34
2.34
6.09
0CB4H
116
CHAPTER 6 CLOCK MODULATOR
Table 6.3-4 Modulation Parameter Settings (2/5)
Fmin (MHz)
Fmax
(MHz)
± phase
skew
50
[periods]
± phase
skew
Min/Max
[periods]
CMPR
F0 (MHz)
resolution
mod
degree
15
2
7
10.20
28.33
2.73
7.11
0EB2H
15
2
8
9.78
32.12
3.13
8.13
10B0H
15
3
1
13.31
17.18
0.78
1.86
02FDH
15
3
2
12.29
19.24
1.56
3.72
04FAH
15
3
3
11.41
21.87
2.34
5.58
06F7H
15
3
4
10.65
25.34
3.13
7.44
08F4H
15
3
5
9.99
30.11
3.91
9.3
0AF1H
15
4
1
12.95
17.81
0.75
2
033CH
15
4
2
11.69
20.92
1.5
4
0538H
15
4
3
10.65
25.34
2.25
6
0734H
15
4
4
9.78
32.12
3
8
0930H
15
5
1
12.61
18.50
1.13
3.94
037BH
15
5
2
11.15
22.92
2.25
7.88
0576H
15
5
3
9.99
30.11
3.38
11.81
0771H
15
6
1
12.29
19.24
1.5
2.67
03BAH
15
6
2
10.65
25.34
3
5.34
05B4H
15
7
1
11.98
20.05
1.81
3.95
03F9H
15
7
2
10.20
28.33
3.63
7.91
05F2H
16
1
1
15.00
17.14
0.27
0.72
027FH
16
1
2
14.58
17.73
0.53
1.44
047EH
16
1
3
14.17
18.37
0.8
2.16
067DH
16
1
4
13.79
19.05
1.06
2.88
087CH
16
1
5
13.43
19.79
1.33
3.59
0A7BH
16
1
6
13.09
20.58
1.59
4.31
0C7AH
16
1
7
12.76
21.45
1.86
5.03
0E79H
16
1
8
12.45
22.38
2.13
5.75
1078H
16
1
9
12.15
23.41
2.39
6.47
1277H
16
1
10
11.87
24.53
2.66
7.19
1476H
16
1
11
11.60
25.76
2.92
7.91
1675H
117
CHAPTER 6 CLOCK MODULATOR
Table 6.3-4 Modulation Parameter Settings (3/5)
Fmin (MHz)
Fmax
(MHz)
± phase
skew
50
[periods]
± phase
skew
Min/Max
[periods]
CMPR
F0 (MHz)
resolution
mod
degree
16
1
12
11.35
27.13
3.19
8.63
1874H
16
1
13
11.10
28.65
3.45
9.34
1A73H
16
1
14
10.86
30.34
3.72
10.06
1C72H
16
1
15
10.64
32.25
3.98
10.78
1E71H
16
2
1
14.58
17.73
0.39
1.02
02BEH
16
2
2
13.79
19.05
0.78
2.03
04BCH
16
2
3
13.09
20.58
1.17
3.05
06BAH
16
2
4
12.45
22.38
1.56
4.06
08B8H
16
2
5
11.87
24.53
1.95
5.08
0AB6H
16
2
6
11.35
27.13
2.34
6.09
0CB4H
16
2
7
10.86
30.34
2.73
7.11
0EB2H
16
3
1
14.17
18.37
0.78
1.86
02FDH
16
3
2
13.09
20.58
1.56
3.72
04FAH
16
3
3
12.15
23.41
2.34
5.58
06F7H
16
3
4
11.35
27.13
3.13
7.44
08F4H
16
3
5
10.64
32.25
3.91
9.3
0AF1H
16
4
1
13.79
19.05
0.75
2
033CH
16
4
2
12.45
22.38
1.5
4
0538H
16
4
3
11.35
27.13
2.25
6
0734H
16
5
1
13.43
19.79
1.13
3.94
037BH
16
5
2
11.87
24.53
2.25
7.88
0576H
16
5
3
10.64
32.25
3.38
11.81
0771H
16
6
1
13.09
20.58
1.5
2.67
03BAH
16
6
2
11.35
27.13
3
5.34
05B4H
16
7
1
12.76
21.45
1.81
3.95
03F9H
16
7
2
10.86
30.34
3.63
7.91
05F2H
20
1
1
18.60
21.63
0.27
0.72
027FH
20
1
2
18.08
22.38
0.53
1.44
047EH
20
1
3
17.58
23.20
0.8
2.16
067DH
118
CHAPTER 6 CLOCK MODULATOR
Table 6.3-4 Modulation Parameter Settings (4/5)
Fmin (MHz)
Fmax
(MHz)
± phase
skew
50
[periods]
± phase
skew
Min/Max
[periods]
CMPR
F0 (MHz)
resolution
mod
degree
20
1
4
17.11
24.07
1.06
2.88
087CH
20
1
5
16.66
25.01
1.33
3.59
0A7BH
20
1
6
16.24
26.02
1.59
4.31
0C7AH
20
1
7
15.84
27.13
1.86
5.03
0E79H
20
1
8
15.46
28.33
2.13
5.75
1078H
20
1
9
15.09
29.64
2.39
6.47
1277H
20
1
10
14.74
31.08
2.66
7.19
1476H
20
1
11
14.41
32.67
2.92
7.91
1675H
20
2
1
18.08
22.38
0.39
1.02
02BEH
20
2
2
17.11
24.07
0.78
2.03
04BCH
20
2
3
16.24
26.02
1.17
3.05
06BAH
20
2
4
15.46
28.33
1.56
4.06
08B8H
20
2
5
14.74
31.08
1.95
5.08
0AB6H
20
3
1
17.58
23.20
0.78
1.86
02FDH
20
3
2
16.24
26.02
1.56
3.72
04FAH
20
3
3
15.09
29.64
2.34
5.58
06F7H
20
4
1
17.11
24.07
0.75
2
033CH
20
4
2
15.46
28.33
1.5
4
0538H
20
4
3
14.09
34.42
2.25
6
0734H
20
5
1
16.66
25.01
1.13
3.94
037BH
20
5
2
14.74
31.08
2.25
7.88
0576H
20
6
1
16.24
26.02
1.5
2.67
03BAH
20
7
1
15.84
27.13
1.81
3.95
2BF5H
24
1
1
22.14
26.20
0.27
0.72
027FH
24
1
2
21.52
27.13
0.53
1.44
047EH
24
1
3
20.93
28.12
0.8
2.16
067DH
24
1
4
20.38
29.19
1.06
2.88
087CH
24
1
5
19.85
30.34
1.33
3.59
0A7BH
24
1
6
19.35
31.59
1.59
4.31
0C7AH
119
CHAPTER 6 CLOCK MODULATOR
Table 6.3-4 Modulation Parameter Settings (5/5)
Fmin (MHz)
Fmax
(MHz)
± phase
skew
50
[periods]
± phase
skew
Min/Max
[periods]
CMPR
F0 (MHz)
resolution
mod
degree
24
1
7
18.87
32.95
1.86
5.03
0E79H
24
2
1
21.52
27.13
0.39
1.02
02BEH
24
2
2
20.38
29.19
0.78
2.03
04BCH
24
2
3
19.35
31.59
1.17
3.05
06BAH
24
3
1
20.93
28.12
0.78
1.86
02FDH
24
3
2
19.35
31.59
1.56
3.72
04FAH
24
3
3
17.99
36.04
2.34
5.58
06F7H
24
4
1
20.38
29.19
0.75
2
033CH
24
5
1
19.85
30.34
1.13
3.94
037BH
24
6
1
19.35
31.59
1.5
2.67
03BAH
24
7
1
18.87
32.95
1.81
3.95
03F9H
25
1
1
23.01
27.36
0.27
0.72
027FH
25
1
2
22.37
28.33
0.53
1.44
047EH
25
1
3
21.76
29.37
0.8
2.16
067DH
25
1
4
21.19
30.49
1.06
2.88
087CH
25
1
5
20.64
31.70
1.33
3.59
0A7BH
25
1
6
20.12
33.00
1.59
4.31
0C7AH
25
2
1
22.37
28.33
0.39
1.02
02BEH
25
2
2
21.19
30.49
0.78
2.03
04BCH
25
2
3
20.12
33.00
1.17
3.05
06BAH
25
3
1
21.76
29.37
0.78
1.86
02FDH
25
3
2
20.12
33.00
1.56
3.72
04FAH
25
4
1
21.19
30.49
0.75
2
033CH
25
5
1
20.64
31.70
1.13
3.94
037BH
25
6
1
20.12
33.00
1.5
2.67
03BAH
120
CHAPTER 6 CLOCK MODULATOR
6.4
Application Note of the Clock Modulator
Startup/stop sequence for phase modulation mode.
Startup/stop sequence for frequency modulation mode.
Modulation parameter for frequency modulation mode.
■ Recommended Startup Sequence for Phase Modulation Mode
start
1.
Switch ON PLL
2.
Wait PLL lock time (refer to the MCM flag description in the CLOCK chapter
of the hardware manual).
3.
Enable phase modulation mode (PMOD=1).
The clock switches immediately to modulated clock
... running...
stop
4.
Disable modulator PMOD=0
5.
4 NOP cycles
6.
Disable PLL, switch to power down mode, etc.
Note:
Do not enable the modulator before the PLL lock time has elapsed. Do not disable the PLL while the
modulator is running.
■ Recommended Startup Sequence for Frequency Modulation Mode
start
1.
Switch modulator from power down to power up mode PDX=1
2.
Switch ON PLL
3.
Wait PLL lock time (refer to the MCM flag description in the CLOCK chapter
of the hardware manual). At the same time the modulator starts up.
4.
Set CMPR register to a proper setting
5.
Enable frequency modulation mode FMOD=1
After the calibration is finished, the clock switches from unmodulated to
modulated clock and the FMODRUN flag changes to "1"
... running...
stop
6.
Disable modulator FMOD=0
7.
Wait until FMODRUN changes to "0"
8.
Switch to power down mode PDX=0
9.
Disable PLL, switch to power down mode, etc.
121
CHAPTER 6 CLOCK MODULATOR
Note:
Do not enable the modulator before the PLL lock time has elapsed. Do not disable the PLL while the
modulator is running.
■ Modulation Parameter for Frequency Modulation Mode
It is not possible to recommend a particular modulation parameter setting to achieve a particular reduction
in EMI. The best setting depends much on the actual application, the whole system and the requirements.
In order to find the optimal modulation parameter setting in frequency modulation mode, the following
approach is recommended.
1.
define the required PLL frequency based on
performance needs
e.g. 16 MHz
2.
determine the maximal allowed clock frequency of
the MCU
e.g. 32 MHz
3.
choose the setting with the highest resolution and
the highest modulation degree, whose maximal
frequency is below the maximal allowed clock
frequency of the MCU.
e.g. resolution:7, degree:2, CMPR=05F2H
(Fmax= 30.34 MHz)
4.
perform EMI measurements
5.
if the EMI measurements does not fulfill the
requirements, you may either
6.
122
reduce the modulation degree at the same
frequency resolution
(this may improve the reduction in the upper
frequency band > 100 MHz, but decrease the
reduction of the fundamental < 100 MHz)
e.g. resolution:7, degree:1, CMPR=03F9H
or
increase the modulation degree at a lower
frequency resolution
(this may improve the reduction of the fundamental
< 100 MHz, but worsen the reduction in the upper
frequency band > 100 MHz)
or
e.g. resolution:5, degree:3, CMPR=0771H
repeat item 3) with the new setting and continue
until the best settings is identified
CHAPTER 6 CLOCK MODULATOR
■ Recommended Settings
Table 6.4-1 lists the some example conditions for PLL clock.
Table 6.4-1 Some Example Conditions for PLL Clock
F0
PLL clock
frequency
maximal allowed
MCU clock
frequency (refer
to the data
sheet)
15 MHz
clock modulator setting
resolution
modulation
degree
Fmax
CMPR
20 MHz
6
1
19.24 MHz
03BAH
15 MHz
25 MHz
7
1
20.05 MHz
03F9H
15 MHz
32 MHz
7
2
28.33 MHz
05F2H
16 MHz
20 MHz
5
1
19.79 MHz
037BH
16 MHz
25 MHz
7
1
21.45 MHz
03F9H
16 MHZ
32 MHz
7
2
30.34 MHz
05F2H
20 MHz
25 MHz
4
1
24.07 MHz
033CH
20 MHz
32 MHz
7
1
27.13 MHz
2BF5H
24 MHz
32 MHz
6
1
31.59 MHz
03BAH
25 MHz
32 MHz
5
1
31.70 MHz
037BH
123
CHAPTER 6 CLOCK MODULATOR
124
CHAPTER 7
RESETS
This chapter describes resets for the MB90390 series
microcontrollers.
7.1 Resets
7.2 Reset Cause and Oscillation Stabilization Wait Times
7.3 External Reset Pin
7.4 Reset Operation
7.5 Reset Cause Bits
7.6 Status of Pins in a Reset
125
CHAPTER 7 RESETS
7.1
Resets
If a reset is generated, the CPU immediately stops the current execution process and
waits for the reset to be cleared. The CPU then begins processing at the address
indicated by the reset vector.
The four causes of a reset are as follows
• Power-on reset
• Watchdog timer overflow
• External reset request via the RST pin
• Software reset request
■ Causes of a Reset
Table 7.1-1 lists the causes of a reset.
Table 7.1-1 Causes of a Reset
Type of reset
Cause
Machine clock
Watchdog
timer
Oscillation
stabilization
wait
Power-on
When the power is turned on
Main clock
(MCLK)
Stop
Yes
External pin
"L" level input to RST pin
Main clock
(MCLK)
Stop
No
Software
A "0" is written to the RST
bit of the low-power
consumption mode control
register (LPMCR).
Main clock
(MCLK)
Stop
No
Watchdog timer overflow
Main clock
(MCLK)
Stop
No
Watchdog timer
Main clock: Oscillation clock frequency divided by 2
126
CHAPTER 7 RESETS
● External reset
An external reset is generated by the "L" level input to an external reset pin (RST pin). The minimum
required period of the "L" level is 16 machine cycles (16/φ). The oscillation stabilization wait time is not
required for external resets.
In the MB90390 series the external reset has to be Min 100 μs for wake-up from Main-Time base timer
mode and Min 100 μs + Oscillation time of oscillator + 16 machine cycles for wake-up from Stop mode.
Refer to the AC characteristics section of the data sheet.
Reference:
If the reset cause is generated during a write operation (during the execution of a transfer instruction
such as MOV), the CPU waits for the reset to be cleared after completion of the instruction only for
reset requests via the RST pin. Therefore, the normal write operation is completed even though a reset
is input concurrently.
Note that a reset may prevent the data transfer requested by a string-processing instruction (such as
MOVS) from being completed because the reset is accepted before a specified number of bytes are
transferred.
● Software reset
A software reset is an internal reset generated by writing "0" to the RST bit of the low-power consumption
mode control register (LPMCR). The oscillation stabilization wait time is not required for a software reset.
● Watchdog timer reset
A watchdog timer reset is generated by a watchdog timer overflow that occurs when "0" is written to the
WTE bit of the watchdog timer control register (WDTC) within a given time after the watchdog timer is
activated. The oscillation stabilization wait time can be set by the clock selection register (CKSCR).
● Power-on reset
A power-on reset is generated when the power is turned on. In this case the oscillation stabilization wait
time is fixed to at 218 HCLK cycles (approx. 65.54 ms at 4MHz source oscillation). When the oscillation
stabilization wait time has elapsed, the reset is executed.
Reference Definition of clocks
HCLK: Oscillation clock
MCLK: Main clock
φ: Machine clock (CPU operating clock)
1/φ: Machine cycle (CPU operating clock period)
See "CHAPTER 5 CLOCKS", for details on machine clocks.
127
CHAPTER 7 RESETS
7.2
Reset Cause and Oscillation Stabilization Wait Times
The MB90390 series has four reset causes. The oscillation stabilization wait time for a
reset depends on the reset cause.
■ Reset Causes and Oscillation Stabilization Wait Times
Table 7.2-1 lists the reset causes and oscillation stabilization wait times.
Table 7.2-1 Reset Causes and Oscillation Stabilization Wait Times
Reset cause
Oscillation stabilization wait time
The corresponding time interval for an oscillation clock
frequency of 4 MHz is given in parentheses.
Power-on reset
always 218/HCLK (approx. 65.54 ms at 4 MHz oscillator)
Watchdog timer
None
External reset via the RST pin
None; though bits WS1 and WS0 are initialized to "11B".
Software reset
None; though bits WS1 and WS0 are initialized to "11B".
HCLK:
Oscillation clock
WS1 and WS0: Oscillation stabilization wait time selection bits of the clock selection register (CKSCR)
Figure 7.2-1 shows the oscillation stabilization wait times at a power-on reset.
Figure 7.2-1 Oscillation Stabilization Wait Times at a Power-on Reset
Evaluation/flash model
Vcc
217/HCLK
217/HCLK
CLK
CPU operation
Voltage step-down
circuit stabilization
wait interval
HCLK: Oscillation clock
128
Oscillation
stabilization wait
time
CHAPTER 7 RESETS
Note:
Ceramic and crystal oscillators generally require an oscillation stabilization wait time of several
milliseconds, until stabilization at a natural frequency is attained. A proper oscillation stabilization
wait time must be set for the particular oscillator used.
See Section "5.5 Oscillation Stabilization Wait Time", for details about oscillation stabilization wait times.
■ Oscillation Stabilization Wait and Reset State
A reset operation in response to a power-on reset and other resets during stop mode is performed after the
oscillation stabilization wait time has elapsed. This time interval is generated by the time-base timer. If the
external reset has not been cleared after the interval, the reset operation is performed after the external reset
is cleared.
129
CHAPTER 7 RESETS
7.3
External Reset Pin
The external reset pin (RST pin) is an input pin used exclusively for a reset. Inputting an
"L" level signal generates an internal reset. For the MB90390 series, resets are
generated in synchronization with the CPU operating clock. However, the I/O port pins
are affected by the external reset pin (RST pin) in an asynchronous manner.
■ Block Diagrams of the External Reset Pin
● Block diagram of internal reset
Figure 7.3-1 Block Diagram of Internal Reset
CPU operating clock
(PLL multiplier circuit with an
HCLK frequency divided by 2)
RST
CPU
P-ch
Synchronization
circuit
Pin
N-ch
Input
buffer
Peripheral
functions
I/O port or
other pin
Note:
Inputs to the RST are accepted during cycles in which memory is not affected to prevent memory
from being destroyed by a reset during a write operation.
A clock is required to initialize the internal circuit. In particular, an operation with an external clock
requires clock input together with reset input.
130
CHAPTER 7 RESETS
7.4
Reset Operation
When a reset is cleared, the memory locations from which the mode data and the reset
vectors are read are selected according to the setting of the mode pins, and a mode
fetch is performed. Mode setting data determines the CPU operating mode and the
execution start address after a reset operation ends. For power-on or recovery from
stop mode by a reset, a mode fetch is performed when the oscillation stabilization wait
time elapses.
■ Overview of Reset Operation
Figure 7.4-1 shows the reset operation flow.
Figure 7.4-1 Reset Operation Flow
Power-on reset
Stop mode
External reset
Software reset
Watchdog timer reset
During a reset
Oscillation stabilization wait
and reset state
Fetching the mode data
Mode fetch
(Reset operation)
Normal operation
(Run state)
Pin state and function
change associated with
external bus mode
Fetching the reset vector
CPU executes an instruction,
fetching instruction codes from
the address indicated by the
reset vector.
■ Mode Pins
Setting the mode pins (MD0 to MD2) specifies how to fetch the reset vector and the mode data. Fetching
the reset vector and the mode data is performed in the reset sequence. See Section "9.2 Mode Pins of
Memory Access Mode", for details on mode pins.
131
CHAPTER 7 RESETS
■ Mode Fetch
When the reset is cleared, the CPU transfers the reset vector and the mode data to the appropriate registers
in the CPU core by hardware. The reset vector and mode data are allocated to the four bytes from
"FFFFDCH" to "FFFFDFH". The CPU outputs these addresses to the bus immediately after the reset is
cleared and then fetches the reset vector and mode data. Using mode fetching, the CPU can begin
processing at the address indicated by the reset vector.
Figure 7.4-2 shows the transfer of the reset vector and mode data.
Figure 7.4-2 Transfer of Reset Vector and Mode Data
Memory space
FFFFDFH
Mode data
FFFFDEH
Bit23 to bit16 of reset vector
FFFFDDH
Bit15 to bit8 of reset vector
FFFFDCH
Bit7 to bit0 of reset vector
F2MC-16LX CPU core
Mode
register
Reset
sequence
MicroROM
PCB
PC
● Mode data (address: FFFFDFH)
Only a reset operation changes the contents of the mode register. The mode register setting is valid after a
reset operation. See Section "9.3 Mode Data of Memory Access Mode", for details on mode data.
● Reset vector (address: FFFFDCH to FFFFDEH)
The execution start address after the reset operation ends is written as the reset vector. Execution starts at
the address contained in the reset vector.
Note:
For MB90F394H(A), the reset vector and the mode data have different predetermined values by the
hardwired logic.
For more information, refer to Section "28.9 Reset Vector Address in Flash Memory".
132
CHAPTER 7 RESETS
7.5
Reset Cause Bits
A reset cause can be identified by reading the watchdog timer control register (WDTC).
■ Reset Cause Bits
As shown in Figure 7.5-1, a flip-flop is associated with each reset cause. The contents of the flip-flops are
obtained by reading the watchdog timer control register (WDTC). If the cause of a reset must be identified
after the reset has been cleared, the value read from the WDTC should be processed by the software and a
branch made to the appropriate program.
Figure 7.5-1 Block Diagram of Reset Cause Bits
RST pin
No periodic clear
RST="L"
External reset
request
detection circuit
Power-on
detection
circuit
Watchdog timer
reset generation
detection circuit
Watchdog timer
control register
(WDTC)
RST bit set
LPMCR, RST
bit write
detection circuit
Clear
S
R
S
Q
R
S
Q
R
Q
R
S
F/F
F/F
F/F
F/F
Delay
circuit
Q
Reading of
watchdog timer
control register
(WDTC)
Internal data bus
S :
R :
Q :
F/F:
Set
Reset
Output
Flip Flop
133
CHAPTER 7 RESETS
■ Correspondence between Reset Cause Bits and Reset Causes
Figure 7.5-2 shows the configuration of the reset cause bits of the watchdog timer control register (WDTC).
Table 7.5-1 maps the correspondence between the reset cause bits and reset causes. See Table 12.1-2 in
Section "12.1 Outline of Watchdog Timer", for details.
Figure 7.5-2 Configuration of Reset Cause Bits (Watchdog Timer Control Register)
Watchdog timer control register (WDTC)
Address: bit15
0000A8 H
bit8 bit7
(TBTC)
bit6
PONR
-
R
-
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
WRST ERST SRST WTE WT1 WT0 X - X X X X X B
R
R
R
W
W
W
R : Read only
W : Write only
X : Undefined
Table 7.5-1 Correspondence between Reset Cause Bits and Reset Causes
Reset cause
PONR
WRST
ERST
SRST
Power-on reset
1
X
X
X
Watchdog timer overflow
*
1
*
*
External reset request via RST pin
*
*
1
*
Software reset request
*
*
*
1
*: Previous state defined
X: Undefined
■ Notes about Reset Cause Bits
● Multiple reset causes generated at the same time
When multiple reset causes are generated at the same time, the corresponding reset cause bits of the
watchdog timer control register (WDTC) are also set to "1". If, for example, an external reset request via
the RST pin and the watchdog timer overflow occur at the same time, the ERST and the WRST bits are
both set to "1".
● Power-on reset
For a power-on reset, because the PONR bit is set to "1" but all other reset cause bits are undefined, the
software should be programmed so that it will ignore all reset cause bits except the PONR bit if it is "1".
134
CHAPTER 7 RESETS
● Clearing the reset cause bits
The reset cause bits are cleared only when the watchdog timer control register (WDTC) is read. Any bit
corresponding to a reset cause that has already been generated is not cleared even though another reset is
generated (a setting of "1" is retained).
Note:
If the power is turned on under conditions where no power-on reset occurs, the value in WDTC
register may not be guaranteed.
135
CHAPTER 7 RESETS
7.6
Status of Pins in a Reset
This section describes the status of pins when a reset occurs.
■ Status of Pins During a Reset
The status of pins during a reset depends on the settings of mode pins (MD2 to MD0).
● When internal vector mode has been set: (MD2 to MD0 = 011B)
All I/O pins (resource pins) are high impedance, and mode data is read from the built-in ROM.
■ Status of Pins after Mode Data is Read
The status of pins after mode data has been read depends on the mode data (M1 and M0 = 00B).
● When single-chip mode has been selected (M1 and M0 = 00B)
All I/O pins (resource pins) are high impedance, and mode data is read from the built-in ROM.
Note:
For those pins that change to high impedance when a reset cause is generated, confirm that devices
connected to the pins do not malfunction.
136
CHAPTER 8
LOW-POWER CONTROL
CIRCUIT
This chapter explains the functions and operations of
the low-power control circuits.
8.1 Overview of Low-Power Consumption Mode
8.2 Block Diagram of the Low-Power Consumption Control Circuit
8.3 Low-Power Consumption Mode Control Register (LPMCR)
8.4 CPU Intermittent Operation Mode
8.5 Standby Mode
8.6 Status Change Diagram
8.7 Status of Pins in Standby Mode and during Reset
8.8 Usage Notes on Low-Power Consumption Mode
137
CHAPTER 8 LOW-POWER CONTROL CIRCUIT
8.1
Overview of Low-Power Consumption Mode
The MB90390 series has the following CPU operating modes, any of which can be used
depending on operating clock selection and clock operation control:
• Clock mode (PLL clock mode or main clock mode)
• CPU intermittent operating mode (PLL clock intermittent operating mode or main
clock intermittent operating mode)
• Standby mode (sleep mode, time-base timer mode or stop mode)
■ CPU Operating Modes and Current Consumption
Figure 8.1-1 shows the relationship between the CPU operating modes and current consumption.
Figure 8.1-1 CPU Operating Mode and Current Consumption
Current consumption
Several tens
of mA
CPU operating
mode
PLL clock mode
Multiplied-by-eight clock
Multiplied-by-six clock
Multiplied-by-four clock
Multiplied-by-three clock
Multiplied-by-two clock
Multiplied-by-one clock
Multiplied-by-eight clock
PLL clock intermittent
operating mode
Multiplied-by-six clock
Multiplied-by-four clock
Multiplied-by-three clock
Multiplied-by-two clock
Multiplied-by-one clock
Main clock mode (1/2 clock mode)
Main clock intermittent operating mode
Several mA
Standby mode
Sleep model
Time-base timer mode
Several μA
Stop mode
Low-power consumption mode
Note:
This figure is only an indication of the degree of power consumption for each mode. Actual current
consumption values may not agree with those in the figure.
138
CHAPTER 8 LOW-POWER CONTROL CIRCUIT
■ Clock Mode
● PLL clock mode
In this mode, a PLL clock that is a multiple of the oscillation clock (HCLK) is used to operate the CPU and
peripheral functions.
● Main clock mode
In this mode, the main clock, with the oscillation clock (HCLK) frequency divided by 2 is used to operate
the CPU and peripheral functions. In the main clock mode, the PLL multiplier circuit is inactive.
Reference:
For the clock mode, see Section "5.4 Clock Mode".
■ CPU Intermittent Operating Mode
In this mode, the CPU is operated intermittently while high-speed clock pluses are supplied to peripheral
functions, thereby reducing power consumption. In this mode, intermittent clock pulses are supplied only to
the CPU while it is accessing a register, internal memory, peripheral function, or external unit.
■ Standby Mode
In this mode, the low-power consumption control circuit stops supplying the clock to the CPU (sleep mode)
or the CPU and peripheral functions (time-base timer mode) or stops the oscillation clock itself (stop
mode), thereby reducing power consumption.
● PLL sleep mode
The PLL sleep mode is activated to stop the CPU operating clock in the PLL clock mode. Components
excluding the CPU operate on the PLL clock.
● Main sleep mode
The main sleep mode is activated to stop the CPU operating clock in the main clock mode. Components
excluding the CPU operate on the main clock.
● Time-base timer mode
The time-base timer mode causes the operation of functions, excluding the oscillation clock, time-base
timer, and clock timer, to stop. All functions other than the time-base timer and clock timer are inactivated.
Please note that the status differentiates between Main-Time-base timer mode and PLL-Time-base timer
mode. The resulting state depends on the clock which is selected by the MCS-bit in CKSCR. See also
Figure 8.6-1.
The power consumption is significantly higher in PLL-Time-base timer mode. Please refer to your data
sheet for specific values.
139
CHAPTER 8 LOW-POWER CONTROL CIRCUIT
● Stop mode
The stop mode cause the oscillation to stop. All functions are inactivated.
Note:
Because the stop mode turn off the oscillation clock, data can be retained at the lowest power
consumption.
In attempting to switch the clock mode, do not attempt to switch to another clock mode or low-power
consumption mode until the first switching is completed. The MCM bit of the clock selection register
(CKSCR) indicate that switching is completed.
140
CHAPTER 8 LOW-POWER CONTROL CIRCUIT
8.2
Block Diagram of the Low-Power Consumption Control
Circuit
The low-power consumption control circuit consists of the following seven blocks:
• CPU intermittent operation selector
• Standby control circuit
• CPU clock control circuit
• Peripheral clock control circuit
• Pin high-impedance control circuit
• Internal reset generation circuit
• Low-power consumption mode control register (LPMCR)
■ Block Diagram of the Low-power Consumption Control Circuit
Figure 8.2-1 shows a block diagram of the low-power consumption control circuit.
Figure 8.2-1 Block Diagram of the Low-power Consumption Control Circuit
Low-Power Consumption Mode Control Register (LPMCR)
STP SLP SPL RST TMD CG1 CG0
RST
Reserved
Pin
intermittent
cycle
selector
CPU intermittent
operation
selector
Pin highimpedance
control circuit
Pin Hi-Z
control
Internal reset
generation
circuit
Internal
reset
CPU clock
control
circuit
CPU
clock
Stop and
sleep signals
Standby
control
circuit
Stop signal
Interrupt
clearing
Peripheral
clock control
circuit
Oscillation stabilization wait time clear
Machine clock
Clock
Selector
CS2
Bit8 of PLL and
Special Configulation
Control Register
(PSCCR)
Peripheral
clock
Oscillation
stabilization
wait time
interval selector
2
2
PLL multiplier circuit
MCM WS1 WS0
-
MCS CS1 CS0
Clock Selection register (CKSCR)
Mainclock
X0
Pin
HCLK
X1
Pin
System clock
generation circuit
Divideby-2
Divideby-1024
Divideby-2
Divideby-4
Divideby-4
Divideby-4
Divideby-2
Time-base Timer
Watchdog Timer
141
CHAPTER 8 LOW-POWER CONTROL CIRCUIT
● CPU intermittent operation selector
This selector selects the number of clock pulses to halt the CPU during the CPU intermittent operation
mode.
● Standby control circuit
The standby control circuit controls the CPU clock control and the peripheral clock control circuits and
turns the low-power consumption mode on and off.
● CPU clock control circuit
This circuit controls clocks supplied to the CPU. This circuit controls clocks supplied to peripheral
functions for the peripheral clock control circuit.
● Peripheral clock control circuit
This circuit controls clocks supplied to peripheral functions.
● Pin high-impedance control circuit
This circuit makes external pins high-impedance in the time-base timer mode and stop mode. For pins with
the pull-up option, this circuit disconnects the pull-up resistor in the stop mode.
● Internal reset generation circuit
This circuit generates an internal reset signal.
● Low-power consumption mode control register (LPMCR)
This register is used to switch to and release the standby mode and to set the CPU intermittent operation
function.
142
CHAPTER 8 LOW-POWER CONTROL CIRCUIT
8.3
Low-Power Consumption Mode Control Register (LPMCR)
This register switches to or releases the low-power consumption mode. This register
also sets the number of CPU clock pulses to halt during the CPU intermittent operation
mode.
■ Low-power Consumption Mode Control Register (LPMCR)
Figure 8.3-1 shows the configuration of the low-power consumption mode control register (LPMCR).
Figure 8.3-1 Configuration of the Low-power Consumption Mode Control Register (LPMCR)
bit15
Address:
0000A0H
(CKSCR)
bit7
bit6
bit5
bit4
bit3
bit2
bit1
STP
SLP
SPL
RST
TMD
CG1
CG0 served
W
W
R/W
W
R/W
R/W
R/W
Re-
Reserved
0
00011000B
R/W
Reserved bit
Count bit for CPU clock temporary halt cycle
0
0
0 cycles (CPU clock = Resource clock)
0
1
8 cycles (CPU clock: Resource clock =1:3 to 4 approx.)
1
0
16 cycles (CPU clock: Resource clock = 1:5 to 6 approx.)
1
1
32 cycles (CPU clock: Resource clock = 1:9 to 10 approx.)
TMD
Time-base timer mode bit
0
Switches to the time-base timer mode
1
No change, no effect on operation
RST
Internal reset signal generation bit
0
Generates an internal reset signal of three machine cycles.
1
No change, no effect on operation
Pin state setting bit
(for time-base timer mode and stop mode)
SPL
0
Retained
1
High impedance
SLP
: Readable and writable
: Write only
: Initial value
Initial value
Always write "0" to this bit
CG1 CG0
R/W
W
bit0
Sleep mode bit
0
No change, no effect on operation
1
Switches to sleep mode.
STP
Stop mode bit
0
No change, no effect on operation
1
Switches to stop mode.
143
CHAPTER 8 LOW-POWER CONTROL CIRCUIT
Table 8.3-1 Function Description of Each Bit of the Low-power Consumption Mode Control Register
(LPMCR)
Bit name
Function
STP:
Stop mode bit
•
•
•
•
•
This bit indicates switching to the stop mode.
When "1" is written to this bit, a switch to the stop mode is performed.
Writing "0" in this bit has no effect on operation.
This bit is cleared to "0" by a reset or when an interrupt request occurs.
The read value of this bit is always "0".
bit6
SLP:
Sleep mode bit
•
•
•
•
•
This bit indicates switching to a sleep mode.
When "1" is written to this bit, a switch to a sleep mode is performed.
Writing "0" in this bit has no effect on operation.
This bit is cleared to "0" by a reset or when an interrupt request occurs.
The read value of this bit is always "0".
bit5
SPL:
Pin state setting bit
(for time-base timer
mode and stop mode)
•
•
•
•
This bit is enabled only in the time-base timer mode and stop mode.
When this bit is "0", the level of the external pins is retained.
When this bit is "1", the status of the external pins changes to high-impedance.
This bit is initialized to "0" by a reset.
bit4
RST:
Internal reset signal
generation bit
• When "0" is written to this bit, an internal reset signal of three machine cycles is
generated.
• Writing "1" in this bit has no effect on operation.
• The read value of this bit is always "1".
bit3
TMD:
Time-base timer
mode bit
• This bit indicates switching to the time-base timer mode.
• When "0" is written to this bit in the main clock mode or PLL clock mode, a switch to
time-base timer mode is performed.
• This bit is cleared to "1" by a reset or when an interrupt request occurs.
• The read value of this bit is always "1".
bit2
bit1
CG1, CG0:
Bits for selecting
clock count for CPU
temporary halt cycle
• These bits set the number of CPU clock pulses per cycle to halt the CPU for the CPU
intermittent operation function.
• The clock supplied to the CPU is stopped for the specified number of pulses after the
execution of each instruction.
• Four types of clock counts are selectable.
• These bits are initialized to "00B" by a reset.
bit0
Reserved
• Always write "0" to this bit.
bit7
144
CHAPTER 8 LOW-POWER CONTROL CIRCUIT
■ Access to the Low-power Consumption Mode Control Register
Writing in the low-power consumption mode control register executes a change in the low-power
consumption mode (including the stop mode, sleep mode, and time-base timer mode). Only the instructions
listed in Table 8.3-2 should be used for this purpose.
The low-power consumption mode transition instruction in Table 8.3-2 must always be followed by an
array of instructions highlighted by a line below.
MOV
LPMCR, #H’XX
; the low-power mode transition instruction in Table 8.3-2
NOP
NOP
JMP
$+3
; jump to next instruction
MOV
A, #H’10
; any instruction
The device does not guarantee its operation after returning from the low-power consumption mode if you
place an array of instructions other than the one enclosed in the line. To access the low-power consumption
mode control register (LPMCR) with C language, refer to "Notes on Accessing the Low-Power
Consumption Mode Control Register (LPMCR) to Enter the Standby Mode" in the Section "8.8 Usage
Notes on Low-Power Consumption Mode". If other instructions are used for switching to a low-power
consumption mode, operation cannot be assured. To control functions not listed in Table 8.3-1, any
instruction can be used.
When word-length is used for writing the low-power consumption mode control register, even addresses
must be used. Using odd addresses to switch to a low-power consumption mode may result in a
malfunction.
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CHAPTER 8 LOW-POWER CONTROL CIRCUIT
■ Priorities of the STP, SLP, and TMD Bits
If the stop mode, sleep mode, and time-base timer mode are requested concurrently, the stop mode request,
time-base timer mode request, and sleep mode request are given priorities in this order for processing.
Note:
To set a pin to high impedance when the pin is shared by a peripheral function and a port in stop
mode or time-base timer mode, disable the output of peripheral functions, and set the STP bit of the
low-power consumption mode control register (LPMCR) to "1" or set the TMD bit to "0".
This applies to the following pins:
P03/IN3/OUT6, P05/IN5/OUT7, P06/OUT0, P07/OUT1, P10/OUT2, P11/OUT3, P12/OUT4,
P13/OUT5, P15/TOT0, P16/SGO, P17/SGA, P20/TX1, P31/TX0, P33/TOT1, P34/SOT0, P35/SCK0
Table 8.3-2 Instructions to be Used for Switching to a Low-power Consumption Mode
MOV io,#imm8
MOV dir,#imm8
MOV eam,#imm8
MOV eam,Ri
MOV io,A
MOV dir,A
MOV addr16,A
MOV eam,A
MOVW io,#imm16
MOVW dir,#imm16
MOVW eam,#imm16
MOVW eam,RWi
MOVW io,A
MOVW dir,A
MOVW addr16,A
MOVW eam,A
SETB io:bp
SETB dir:bp
SETB addr16:bp
CLRB io:bp
CLRB dir:bp
CLRB addr16:bp
MOV @RLi+disp8,A
MOVW @RLi+disp8,A
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CHAPTER 8 LOW-POWER CONTROL CIRCUIT
8.4
CPU Intermittent Operation Mode
This mode is used for intermittent operation of the CPU while external buses and
peripheral functions continue to operate at high speeds. The purpose of this mode is to
reduce power consumption.
■ CPU Intermittent Operation Mode
This mode halts the supply of the clock pulse to the CPU for a certain period. The halt occurs after the
execution of every instruction that accesses a register, built-in memory (ROM and RAM), I/O, peripheral
functions, or the external bus. Internal bus cycle activation is therefore delayed. While high-speed
peripheral clock pulses are supplied to peripheral functions, the execution speed of the CPU is reduced,
thereby enabling low-power consumption processing.
• The low-power consumption mode control register (LPMCR: CG1 and CG0) is used to select the
number of clock pulses per halt cycle of the clock supplied to the CPU.
• External bus operation uses the same clock as that used for peripheral functions.
• Instruction execution time in the CPU intermittent mode can be calculated. A correction value should be
obtained by multiplying the execution count of instructions that access a register, internal memory,
internal peripheral functions, or the external bus by the number of clock pulses per halt cycle. Add this
corrective value to the normal execution time. Figure 8.4-1 shows the clock pulses during the CPU
intermittent operation.
Figure 8.4-1 Clock Pulses During the CPU Intermittent Operation
Peripheral clock
CPU clock
Halt cycle
Execution
cycle of one
instruction
Internal bus activation
147
CHAPTER 8 LOW-POWER CONTROL CIRCUIT
8.5
Standby Mode
The standby mode includes the sleep (PLL sleep, main sleep), time-base timer, and stop
modes.
■ Operation Status During Standby Mode
Table 8.5-1 shows operation statuses during standby mode.
Table 8.5-1 Operation Status During Standby Mode
Condition
for switch
Main
clock
PLL sleep
mode
MCS=0
SLP=1
Active
Main sleep
mode
MCS=1
SLP=1
Time-base
timer mode
(SPL=0)
TMD=0
Standby mode
Sleep
mode
Timebase timer
mode
Stop
mode
Machine
clock
CPU
Active
TMD=0
Stop mode
(SPL=0)
STP=1
Active
Active
Release
event
Retained
Inactive
Reset
or
Interrupt
Inactive *
Hi-Z
Inactive
Retained
Inactive
Stop mode
(SPL=1)
Pin
Active
Active
Time-base
timer mode
(SPL=1)
Peripheral
Inactive
STP=1
Hi-Z
*: The time-base timer and watch timer operate.
SPL:
Pin state setting bit of low-power consumption mode control register (LPMCR)
SLP:
Sleep mode bit of low-power consumption mode control register (LPMCR)
STP:
Stop mode bit of low-power consumption mode control register (LPMCR)
TMD: Time-base timer mode bit of low-power consumption mode control register (LPMCR)
MCS: Machine clock selection bit of clock selection register (CKSCR)
Hi-Z: High-impedance
Note:
To set a pin to high impedance when the pin is shared by a peripheral function and a port in stop
mode or time-base timer mode, disable the output of peripheral functions, and set the STP bit of the
low-power consumption mode control register (LPMCR) to "1" or set the TMD bit to "0".
This applies to the following pins:
P03/IN3/OUT6, P05/IN5/OUT7, P06/OUT0, P07/OUT1, P10/OUT2, P11/OUT3, P12/OUT4,
P13/OUT5, P15/TOT0, P16/SGO, P17/SGA, P20/TX1, P31/TX0, P33/TOT1, P34/SOT0, P35/SCK0
148
CHAPTER 8 LOW-POWER CONTROL CIRCUIT
8.5.1
Sleep Mode
This mode causes the CPU operating clock to stop while other components continue to
operate. When the low-power consumption mode control register (LPMCR) indicates a
switch to a sleep mode, a switch to the PLL sleep mode occurs if the PLL clock mode
has been set. A switch to the main sleep mode occurs if the main clock mode has been
set.
■ Switching to Sleep Mode
Writing "1" in the SLP bit and the TMD bit and "0" in the STP bit of the low-power consumption mode
control register (LPMCR) triggers a switch to a sleep mode. At this time, if the MSC bit is "0" in the clock
selection register (CKSCR), a switch to the PLL sleep mode is triggered. If the MSC bit is "1", a switch to
the main sleep mode is triggered.
Note:
When "1" is written to the SLP and STP bits at the same time, the STP bit setting overrides the SLP
bit setting and the mode switches to the stop mode. When "1" is written to the SLP bit and "0" is
written to the TMD bit at the same time, the TMD bit setting overrides the SLP bit setting and the
mode switches to the time-base timer mode.
● Data retention function
In a sleep mode, the contents of dedicated registers, such as accumulators, and the built-in RAM are
retained.
● Operation during an interrupt request
Writing "1" in the SLP bit of the low-power consumption mode control register during an interrupt request
does not trigger a switch to a sleep mode. If the CPU does not accept the interrupt, the CPU executes the
next instruction. If the CPU accepts the interrupt, CPU operation immediately branches to the interrupt
processing routine.
● Status of pins
During a sleep mode, all pins (excluding those used for bus I/O or bus control) retain their previous status.
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CHAPTER 8 LOW-POWER CONTROL CIRCUIT
■ Release of Sleep Mode
The low-power consumption control circuit releases sleep modes when a reset is input or an interrupt
occurs.
● Return by a reset
A sleep mode is initialized to the main clock mode by a reset.
● Return by an interrupt
If an interrupt request of level seven or higher is issued from a peripheral circuit during a sleep mode, the
sleep mode is released. After the mode is released, the interrupt is handled as an ordinary interrupt. If the
interrupt is accepted according to the setting of the I flag of the condition code register (CCR), interrupt
level mask register (ILM), and interrupt control register (ICR), the CPU executes the interrupt processing.
If the interrupt is not accepted, the CPU executes the instruction following the instruction specifying the
sleep mode.
Figure 8.5-1 shows the release of a sleep mode when an interrupt occurs.
Figure 8.5-1 Release of Sleep Mode by Interrupt Occurrence
Interrrupt from peripheral function
Set the enable flag.
IL smaller than 7
INT occurrence?
NO
(IL smaller than 7)
Sleep mode is
not released.
Sleep mode is
not released.
YES
YES
I=0
Next instruction
is executed.
NO
ILM smaller than IL
YES
Sleep mode is
released.
Next instruction
is executed.
NO
Interrupt is executed.
Note:
When interrupt processing is executed, the CPU normally executes the instruction that follows the
instruction in which switching to a sleep mode has been specified. The CPU then proceeds to
interrupt processing. If the switching to sleep mode and acceptance of an external bus hold request
occur at the same time, however, the CPU may proceed to interrupt processing before executing the
next instruction.
150
CHAPTER 8 LOW-POWER CONTROL CIRCUIT
8.5.2
Time-base Timer Mode
This mode causes all functions, excluding oscillation, the time-base timer, and the
clock timer, to stop. In this mode, only the time-base timer and clock timer operate.
■ Switching to the Time-base Timer Mode
When "0" is written to the TMD bit of the low-power consumption mode control register (LPMCR) in the
PLL clock mode or main clock mode, switching to the time-base timer mode occurs.
Please note that the status differentiates between Main-Time-base timer mode and PLL-Time-base timer
mode. The resulting state depends on the clock which is selected by the MCS-bit in CKSCR. See also
Figure 8.6-1.
The power consumption is significantly higher in PLL-Time-base timer mode. Please refer to your data
sheet for specific values.
● Data retention function
In the time-base timer mode, the contents of dedicated registers, such as accumulators, and the built-in
RAM are retained.
● Operation during an interrupt request
Writing "0" in the TMD bit of the low-power consumption mode control register (LPMCR) during an
interrupt request does not trigger a switch to the time-base timer mode.
● Status of pins
Whether the external pins in the time-base timer mode retain the state they had immediately before
switching to the time-base timer mode or go to the high-impedance state can be controlled by the lowpower consumption mode control register (LPMCR: SPL).
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CHAPTER 8 LOW-POWER CONTROL CIRCUIT
■ Release of Time-base Timer Mode
The low-power consumption control circuit releases the time-base timer mode when a reset is input or an
interrupt occurs.
● Return by a reset
The time-base timer mode is initialized to the main clock mode by a reset.
Note:
The RST signal must be asserted for at least 100 μs in Main-Time-base Timer Mode.
● Return by an interrupt
If an interrupt request of level seven or higher is issued from a peripheral circuit during the time-base timer
mode (IL2, IL1, and IL0 of the interrupt control register (ICR) do not indicate "111B"), the low-power
consumption mode control circuit releases the time-base timer mode. After the mode is released, the
interrupt is handled as an ordinary interrupt. If the interrupt is accepted according to the setting of the I flag
of the condition code register (CCR), interrupt level mask register (ILM), or interrupt control register
(ICR), the CPU executes the interrupt processing. If the interrupt is not accepted, the CPU executes the
instruction following the instruction specifying the time-base timer mode.
Note:
When interrupt processing is executed, the CPU normally executes the instruction following the
instruction in which switching to the time-base timer mode has been specified. The CPU then
proceeds to interrupt processing. If the switching to the time-base timer mode and acceptance of an
external bus hold request occur at the same time, however, the CPU may proceed to interrupt
processing before executing the next instruction.
Wake up from Main-Time-base timer mode by interrupt is internally delayed up to 40 μs.
To set a pin to high impedance when the pin is shared by a peripheral function and a port in timebase timer mode, disable the output of peripheral functions, and set the TMD bit of the low-power
consumption mode control register (LPMCR) to "0".
This applies to the following pins:
P03/IN3/OUT6, P05/IN5/OUT7, P06/OUT0, P07/OUT1, P10/OUT2, P11/OUT3, P12/OUT4,
P13/OUT5, P15/TOT0, P16/SGO, P17/SGA, P20/TX1, P31/TX0, P33/TOT1, P34/SOT0, P35/SCK0
152
CHAPTER 8 LOW-POWER CONTROL CIRCUIT
8.5.3
Stop Mode
Because this mode causes oscillation to stop and inactivates all functions, data can be
retained by the lowest power consumption.
■ Switching to the Stop Mode
When "1" is written to the STP bit of the low-power consumption mode control register (LPMCR),
switching to the stop mode occurs.
● Data retention function
In the stop mode, the contents of the dedicated registers, such as accumulators, and the built-in RAM are
retained.
● Operation during an interrupt request
Writing "1" in the STP bit of the low-power consumption mode control register (LPMCR) does not trigger
a switch to the stop mode.
● Status of pins
Whether the external pins in the stop mode retain the state they had immediately before switching to the
stop mode or go to the high-impedance state can be controlled by the SPL bit of the low-power
consumption mode control register (LPMCR).
153
CHAPTER 8 LOW-POWER CONTROL CIRCUIT
■ Release of Stop Mode
The low-power consumption control circuit releases the stop mode when a reset is input or an interrupt
occurs. Because oscillation of the operating clock is halted before returning from the stop mode, the lowpower consumption control circuit enters the oscillation stabilization wait state, then releases the stop
mode.
● Return by a reset
After the stop mode is released by a reset, the oscillation stabilization wait state is set. The reset sequence is
executed after the oscillation stabilization wait time.
Note:
The RST signal must be asserted for at least 100 μs + oscillation time of the oscillator + 16 machine
clock cycles in Stop Mode. Refer to the AC Characteristics Section of the data sheet.
●
Return by an interrupt
If an interrupt request of level seven or higher is issued from a peripheral circuit during the stop mode (IL2,
IL1, and IL0 of the interrupt control register (ICR) do not indicate "111B"), the low-power consumption
mode control circuit releases the stop mode. The interrupt is then handled as an ordinary interrupt after the
oscillation stabilization wait time of the main clock specified by the WS1 and WS0 bits of the clock
selection register (CKSCR). If the interrupt is accepted according to the setting of the I flag of the condition
code register (CCR), interrupt level mask register (ILM), and interrupt control register (ICR), the CPU
executes the interrupt processing. If the interrupt is not accepted, the CPU executes the instruction
following the instruction specifying the stop mode.
Note:
When interrupt processing is executed, the CPU normally executes the instruction following the
instruction in which switching to the stop mode has been specified. The CPU then proceeds to
interrupt processing. If the switching to the stop mode and acceptance of an external bus hold
request occur at the same time, however, the CPU may proceed to interrupt processing before
executing the next instruction.
Figure 8.5-2 shows the release of the stop mode (external reset).
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CHAPTER 8 LOW-POWER CONTROL CIRCUIT
Figure 8.5-2 Release of the Stop Mode (External Reset)
RST pin
Stop mode
Main clock
Oscillating
Oscillation stabilization wait
Oscillating
PLL clock
Inactive
Inactive
Main clock
CPU clock
Inactive
CPU operation
Reset sequence Execution
Reset released.
Stop mode released.
Notes:
• To set a pin to high impedance when the pin is shared by a peripheral function and a port in stop
mode, disable the output of peripheral functions, and set the STP bit of the low-power
consumption mode control register (LPMCR) to "1".
This applies to the following pins:
P03/IN3/OUT6, P05/IN5/OUT7, P06/OUT0, P07/OUT1, P10/OUT2, P11/OUT3, P12/OUT4,
P13/OUT5, P15/TOT0, P16/SGO, P17/SGA, P20/TX1, P31/TX0, P33/TOT1, P34/SOT0, P35/
SCK0
• In PLL stop mode, the main clock and PLL multiplication circuit stop. During recovery from PLL
stop mode, it is necessary to allot the main clock oscillation stabilization wait time and PLL clock
oscillation stabilization wait time. The oscillation stabilization wait times for the main clock and
PLL clock are counted simultaneously according to the value specified in the oscillation
stabilization wait time selection bits (CKSCR: WS1, WS0) in the clock selection register. The
oscillation stabilization wait time selection bits (CKSCR: WS1, WS0) in the clock selection register
must be selected accordingly to account for the longer of main clock and PLL clock oscillation
stabilization wait time. The PLL clock oscillation stabilization wait time, however, requires 214/
HCLK or more. Set the oscillation stabilization wait time selection bits (CKSCR: WS1, WS0) in the
clock selection register to "10B" or "11B".
155
CHAPTER 8 LOW-POWER CONTROL CIRCUIT
8.6
Status Change Diagram
Figure 8.6-1 shows the status change diagram.
■ Status Change Diagram
Figure 8.6-1 Status Change Diagram
External reset, watchdog timer
reset, software reset
Power-on
Reset
Power-on reset
Osc
MCS=0
Main clock mode
PLL clock mode
MCS=1
SLP=1
SLP=1
Int
Main sleep mode
TMD=0
Int
STP=1
Int
TMD=0
STP=1
Main stop
mode
PLL stop mode
Osc
Main clock oscillation
stabilization wait
Int: Interrupt
Osc: Oscillation stabilization wait end
156
PLL sleep mode
PLLTime-base
timer mode
MainTime-base
timer mode
Int
Int
Int
Osc
PLL clock oscillation
stabilization wait
CHAPTER 8 LOW-POWER CONTROL CIRCUIT
■ Operation Status in Each Operating Mode
Table 8.6-1 lists the operation status in each operating mode.
Table 8.6-1 Operation Status in Each Operating Mode
Operation status
Main clock
PLL clock
PLL
CPU
Peripheral
Watch
timer
Time-base
timer
Active
Active
Inactive
Inactive
Active
Active
Active
Active
Inactive
Inactive
Active
Active
Active *
Active *
Clock
source
Active
Active
PLL sleep
Active
Active
PLL stop
Inactive
Inactive
PLL oscillation
stabilization wait
Active
Active
PLL time-base timer
PLL clock
Main
Inactive
Inactive
Active
Active
Main sleep
Active
Main time-base timer
Inactive
Main stop
Inactive
Main oscillation
stabilization wait
Active
Power-on reset
Inactive
Inactive
Inactive
Active
Reset
Inactive
Active
Inactive
Main clock
*: During reset phase, both timers start running as soon as a clock is available (not immediately in power-on).
At the end of the reset phase, the timer value is reset to the initial value.
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CHAPTER 8 LOW-POWER CONTROL CIRCUIT
8.7
Status of Pins in Standby Mode and during Reset
The status of pins in the standby mode and during reset are described for the single
chip mode.
■ Status of Each Pin in the Single Chip Mode
Table 8.7-1 lists the status of each pin in the single chip mode.
Table 8.7-1 Status of Each Pin in the Single Chip Mode
Standby mode
Pin name
Stop mode/time-base timer mode
Reset
Sleep
SPL = 0
SPL = 1
P00 to P07
P10 to P17
P20, P21
P30 to P37
P40 to P45
Input disabled *4/
status before the
mode retained *2
P50 to P57
P60 to P67
P70 to P77
Input disabled *4 /
output Hi-Z *5
Not affected
Input not possible *3/
output Hi-Z *5
P80 to P87
P90 to P97
PA0 to PA7
PB0 to PB7
P46, P47,
P22 to P27
Input enabled *1/
status before the
mode retained *2
Input enabled *1/
output Hi-Z *5
*1: These pins are "Input enabled" in stop mode/time-base timer mode only if the corresponding bit of
the ENIR register is set to "1". Otherwise the inputs are disabled.
*2: "Status before the mode retained" means that it keep previous output state when output or that the
input is "not possible" when input.
*3: "Input not possible" means that the gate connected to the input pin is functioning as input but the
internal circuit can not accept this input signal because the internal circuit is not functioning.
*4: "Input disabled" means that the gate connected to the input pin is disabled.
*5: "Output Hi-Z" means that the pin driving transistor is placed in the drive prohibited state to set the
pin to high impedance.
158
CHAPTER 8 LOW-POWER CONTROL CIRCUIT
8.8
Usage Notes on Low-Power Consumption Mode
Note the following four items when using the low-power consumption mode:
• Switching to a standby mode and interrupt
• Notes on the transition to standby mode
• Release of a standby mode by an interrupt
• Release of the stop mode
• Oscillation stabilization wait time
• Switching to the clock modes
• Notes on Accessing the Low-Power Consumption Mode Control Register (LPMCR) to
Enter the Standby Mode
■ Switching to a Standby Mode and Interrupt
During an interrupt request to the CPU from a peripheral function, the CPU ignores the setting of the lowpower consumption mode control register (LPMCR) even if "1" is written to the STP and SLP bits or if "0"
is written to the TMD bit. Thus, switching to each standby mode is disabled (even after processing of the
interrupt is completed, there is no switch to a standby mode). If the interrupt level is seven or a higher
priority, this action does not depend on whether the interrupt request is accepted by the CPU. However,
during execution of interrupt processing by the CPU, if the interrupt request flag for the interrupt is cleared
and no other interrupt requests have been issued, switching to a standby mode can be performed.
■ Notes on the Transition to Standby Mode
To set a pin to high impedance when the pin is shared by a peripheral function and a port in stop mode or
time-base timer mode, use the following procedure:
• Disable the output of peripheral functions.
• Set the SPL bit to "1", STP bit to "1", or TMD bit to "0" in the low-power mode control register
(LPMCR).
■ Release of the Standby Mode by an Interrupt
If an interrupt request of interrupt level seven or a higher priority is issued from a peripheral function
during the sleep, time-base timer, or stop mode, the standby mode is released, which does not depend on
whether the CPU accepts the interrupt.
After the release of the standby mode by an interrupt, normal processing is performed. The CPU branches
to the interrupt handling routine provided that the priority of the interrupt request indicated by the interrupt
level setting bits (IL2, IL1, and IL0 of ICR) is higher than the interrupt level mask register (ILM) and the
interrupt enable flag (I) of the condition code register (CCR) is set to "1" (enabled).
If the interrupt is not accepted, the CPU starts the execution with the instruction following the instruction in
which switching to the standby mode has been specified.
When interrupt processing is executed normally, the CPU first executes the instruction following the
instruction in which switching to the standby mode has been specified. The CPU then proceeds to interrupt
processing. Depending on the condition when switching to a standby mode was performed, however, the
CPU may proceed to interrupt processing before executing the next instruction.
159
CHAPTER 8 LOW-POWER CONTROL CIRCUIT
Note:
If the CPU does not branch to the interrupt processing routine immediately after a return, action such
as interrupt disabling must be taken before a standby mode is set.
■ Release of the Stop Mode
The stop mode can be released by an input that has been set as an external interrupt input cause before the
system enters the stop mode. As an input cause, an "H" signal, "L" signal, rising edge, or falling edge can
be selected.
■ Oscillation Stabilization Wait Time
● Clock oscillation stabilization wait time
Because the oscillator for oscillation is halted in the stop mode, an oscillation stabilization wait time is
required. A time period selected by the WS1 and WS0 bits of the clock selection register (CKSCR) is used
as the oscillation stabilization wait time. The WS1 and WS0 bits can be set to "00B" only in the main clock
mode.
● PLL clock oscillation stabilization wait time
In main clock mode, the PLL multiplication circuit stops. When changing to PLL clock mode, it is
necessary to reserve the PLL clock oscillation stabilization wait time.
In PLL stop mode, the main clock and PLL multiplication circuit stop. During recovery from PLL stop
mode, it is necessary to allot the main clock oscillation stabilization wait time and PLL clock oscillation
stabilization wait time. The oscillation stabilization wait times for the main clock and PLL clock are
counted simultaneously according to the value specified in the oscillation stabilization wait time selection
bits (CKSCR: WS1, WS0) in the clock selection register. The oscillation stabilization wait time selection
bits (CKSCR: WS1, WS0) in the clock selection register must be selected accordingly to account for the
longer of main clock and PLL clock oscillation stabilization wait time. The PLL clock oscillation
stabilization wait time, however, requires 214/HCLK or more. Set the oscillation stabilization wait time
selection bits (CKSCR: WS1, WS0) in the clock selection register to "10B" or "11B".
■ Clock Mode Switching
When the clock mode is switched, the mode should not switch to the low power consumption mode, or
other clock mode until the switching termination. To check the switching termination, the MCM bit of the
clock selection register (CKSCR) is read. The other switching to other clock mode or to low power
consumption mode may not be done before the switching termination.
160
CHAPTER 8 LOW-POWER CONTROL CIRCUIT
■ Notes on Accessing the Low-power Consumption Mode Control Register (LPMCR) to
Enter the Standby Mode
● To access the low-power consumption mode control register (LPMCR) with assembler language
To set the low-power consumption mode control register (LPMCR) to enter the standby mode, use the
instruction listed in Table 8.3-2.
The low-power consumption mode transition included in Table 8.3-2 must always be followed by an array
of instructions highlighted by a line below.
MOV
LPMCR, #H’XX
; the low-power mode transition instruction in Table 8.3-2
NOP
NOP
JMP
$+3
; jump to next instruction
MOV
A, #H’10
; any instruction
The device does not guarantee its operation after returning from the low-power consumption mode if you
place an array of instructions other than the one enclosed in the line.
● To access the low-power consumption mode control register (LPMCR) with C language
To enter the standby mode using the low-power consumption mode control register (LPMCR), use one of
the following methods (1) to (3) to access the register.
(1)Specify the standby mode transition instruction as a function and insert two _wait_nop() built-in
functions after that instruction. If any interrupt other than the interrupt to return from the standby mode can
occur within the function, optimize the function during compilation to suppress the LINK and UNLINK
instructions from occurring.
Example: Time-base timer mode transition function
Void enter_time-base(){
IO_LPMCR_byte = 0x10;
/* Set LPMCR TMD bit to "0" */
wait_nop();
wait_nop();
}
(2)Define the standby mode transition instruction using _asm statements and insert two NOP and JMP
instructions after that instruction.
Example: Transition to sleep mode
_asm(" MOV I:_IO_LPMCR, #H’58");
/* Set LPMCR SLP bit to "1" */
_asm(" NOP");
_asm(" NOP");
_asm(" JMP $+3");
/* Jump to next instruction */
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CHAPTER 8 LOW-POWER CONTROL CIRCUIT
(3)
Define the standby mode transition instruction between #pragma asm and #pragma endasm and
insert two NOP and JMP instructions after that instruction.
Example: Transition to stop mode
#pragma asm
MOV I:_IO_LPMCR, #H’98
/* Set LPMCR STP bit to "1" */
NOP
NOP
JMP $+3
#pragma endasm
162
/* Jump to next instruction */;
CHAPTER 9
MEMORY ACCESS MODES
This chapter explains the functions and operations of
the memory access modes.
9.1 Outline of Memory Access Modes
9.2 Mode Pins of Memory Access Mode
9.3 Mode Data of Memory Access Mode
163
CHAPTER 9 MEMORY ACCESS MODES
9.1
Outline of Memory Access Modes
In the F2MC-16LX, the following two memory access modes are provided for each of the
access methods and access areas:
• Operation mode
• Bus mode
■ Memory access Modes
Operation mode
RUN
Flash programming
Bus mode
Single chip
For the MB90390 Series, the external bus function is not supported. Therefore the following part of this
document is not fully supported. In user applications, please use the MB90390 Series in the single chip
mode.
To set the MB90390 Series into the single chip mode, the mode inputs (MD2 to MD0) should be "011B"
and the most significant two bits of the mode data (M1 and M0) should be "00B".
● Operation mode
Operation mode means the mode for controlling the device operation status. The operation mode is
specified by the MDx mode setting pin and the Mx bit in mode data.
● Bus mode
Bus mode means the mode for controlling the built-in ROM operation and external access function. The
bus mode is specified by the MDx mode setting pin and the Mx bit in mode data. The MDx mode setting
pin specifies the bus mode for reading the reset vector and mode data, and the Mx bit in mode data
specifies the bus mode for normal operation.
164
CHAPTER 9 MEMORY ACCESS MODES
9.2
Mode Pins of Memory Access Mode
Table 9.2-1 describes the operations specified by combinations of the MD2 to MD0
external pins.
■ Mode Pins
Table 9.2-1 Mode Pins and Modes
Mode pin setting
Mode name
Reset vector
access area
External data
bus width
MD2
MD1
MD0
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
Flash memory serial
programming *1, *2
-
-
1
1
1
Flash memory *2
-
-
Remarks
Reserved
Internal vector mode
Internal
(Mode data)
Reset sequence and later
segments are controlled
based on mode data.
Reserved
Mode for use of a
parallel programmer
*1: Data cannot be written only by setting the flash serial programming mode by mode pins.
Other must be set. For details, see the examples of flash memory serial programming connection.
*2: Not available on MB90V390H/MB90V390HA/MB90V390HB/MB90394HA
165
CHAPTER 9 MEMORY ACCESS MODES
9.3
Mode Data of Memory Access Mode
Mode data is stored at "FFFFDFH" of main memory and used for controlling the CPU
operation. This data is fetched during a reset sequence and stored in the mode register
inside the device. The mode register value can be changed only by a reset sequence.
The setting of this register is valid after the reset sequence.
Always set the reserved bits to "0".
■ Mode Data
Figure 9.3-1 shows the mode data structure.
Figure 9.3-1 Mode Data Structure
bit
Mode data
7
6
5
4
3
2
1
0
M1
M0
0
0
0
0
0
0
Function extension bit (reserved area)
Bus mode setting bits
■ Bus Mode Setting Bits
These bits are used to specify the operation mode after the reset sequence is completed. Table 9.3-1 lists the
bus mode setting bits and functions.
Table 9.3-1 Bus Mode Setting Bits and Functions
166
M1
M0
Function
0
0
Single chip mode
0
1
1
0
1
1
(Inhibited)
CHAPTER 9 MEMORY ACCESS MODES
Figure 9.3-2 shows the access areas and physical addresses in each bus mode.
Figure 9.3-2 Access Areas and Physical Addresses in Each Bus Mode
FFFFFFH
FF0000H
FEFFFFH
FE0000H
FDFFFFH
FD0000H
FCFFFFH
FC0000H
FBFFFFH
FB0000H
FAFFFFH
ROM (FF bank)
ROM (FE bank)
ROM (FD bank)
ROM (FC bank)
ROM (FB bank)
ROM (FA bank)
FA0000H
F9FFFFH
F90000H
00FFFFH
008000H
0050FFH
004100H
003FFFH
ROM (F9 bank)
ROM (Image of
FF bank)
RAM 4KBytes
Peripheral
003500H
0030FFH
RAM 12KBytes
000100H
0000BFH
000000H
: No access
Peripheral
: Internal access
Note:
This is only an example for the demonstration of different access areas. Any specific device might
differ from the shown map. Please refer to the respective Data sheet or Section "2.3 Memory Space
Map".
167
CHAPTER 9 MEMORY ACCESS MODES
■ Recommended Setting
Table 9.3-2 lists a sample recommended setting of mode pins and mode data.
Table 9.3-2 Sample Recommended Setting of Mode Pins and Mode Data
Sample setting
MD2
MD1
MD0
M1
M0
Single chip
0
1
1
0
0
Note:
For the MB90390 series devices with Flash memory, the mode data have predetermined values by
the hard-wired logic.
For more information, refer to Section "28.9 Reset Vector Address in Flash Memory".
168
CHAPTER 10
I/O PORTS
This chapter explains the functions and operations of
the I/O ports.
10.1 I/O Ports
10.2 I/O Port Registers
169
CHAPTER 10 I/O PORTS
10.1
I/O Ports
Each pin of the ports can be specified as input or output using the direction register if
the corresponding peripheral does not use the pin. When a pin is specified as input, the
logic level at the pin is read. When a pin is specified as output, the data register value is
read. The above also applies to a read operation for the read-modify-write (RMW)
instructions.
■ I/O Ports
When a pin is used as an output of other peripheral function, the peripheral output value is read regardless
of the direction register value.
It is generally recommended that the read-modify-write (RMW) instructions should not be used for setting
the data register prior to setting the port as an output. This is because the read-modify-write (RMW)
instruction in this case results reading the logic level at the port rather than the register value.
Figure 10.1-1 is a block diagram of the I/O ports.
Figure 10.1-1 I/O Port Block Diagram
Internal data bus
Data register read
Data register
Data register write
Direction register
Direction register write
Direction register read
170
Pin
CHAPTER 10 I/O PORTS
10.2
I/O Port Registers
There are four types of I/O port registers:
• Port data register (PDR0 to PDRB)
• Port direction register (DDR0 to DDRB)
• Analog input enable register (ADER)
• Input level select register (ILSR)
■ I/O Port Registers
Figure 10.2-1 shows the I/O port registers.
Figure 10.2-1 I/O Port Registers
bit
15/7
14/6
13/5
12/4
11/3
10/2
9/1
8/0
Address: 000000 H
P07
P06
P05
P04
P03
P02
P01
P00
Port 0 data register (PDR0)
Address: 000001 H
P17
P16
P15
P14
P13
P12
P11
P10
Port 1 data register (PDR1)
Address: 000002 H
P27
P26
P25
P24
P23
P22
P21
P20
Port 2 data register (PDR2)
Address: 000003 H
P37
P36
P35
P34
P33
P32
P31
P30
Port 3 data register (PDR3)
Address: 000004 H
P47
P46
P45
P44
P43
P42
P41
P40
Port 4 data register (PDR4)
Address: 000005 H
P57
P56
P55
P54
P53
P52
P51
P50
Port 5 data register (PDR5)
Address: 000006 H
P67
P66
P65
P64
P63
P62
P61
P60
Port 6 data register (PDR6)
Address: 000007 H
P77
P76
P75
P74
P73
P72
P71
P70
Port 7 data register (PDR7)
Address: 000008 H
P87
P86
P85
P84
P83
P82
P81
P80
Port 8 data register (PDR8)
Address: 000009 H
P97
P96
P95
P94
P93
P92
P91
P90
Port 9 data register (PDR9)
Address: 00000A H
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
Port A data register (PDRA)
Address: 00000B H
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0
Port B data register (PDRB)
Address: 000010 H
D07
D06
D05
D04
D03
D02
D01
D00
Port 0 direction register (DDR0)
Address: 000011 H
D17
D16
D15
D14
D13
D12
D11
D10
Port 1 direction register (DDR1)
Address: 000012 H
D27
D26
D25
D24
D23
D22
D21
D20
Port 2 direction register (DDR2)
Address: 000013 H
D37
D36
D35
D34
D33
D32
D31
D30
Port 3 direction register (DDR3)
Address: 000014 H
D47
D46
D45
D44
D43
D42
D41
D40
Port 4 direction register (DDR4)
Address: 000015 H
D57
D56
D55
D54
D53
D52
D51
D50
Port 5 direction register (DDR5)
Address: 000016 H
D67
D66
D65
D64
D63
D62
D61
D60
Port 6 direction register (DDR6)
Address: 000017 H
D77
D76
D75
D74
D73
D72
D71
D70
Port 7 direction register (DDR7)
Address: 000018 H
D87
D86
D85
D84
D83
D82
D81
D80
Port 8 direction register (DDR8)
Address: 000019 H
D97
D96
D95
D94
D93
D92
D91
D90
Port 9 direction register (DDR9)
Address: 00001A H
DA7
DA6
DA5
DA4
DA3
DA2
DA1
DA0
Port A direction register (DDRA)
Address: 00001B H
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
Port B direction register (DDRB)
15/7
14/6
13/5
12/4
11/3
10/2
9/1
8/0
Address: 00000C H
ADE7
ADE6
ADE5
ADE4
ADE3
ADE2
ADE1
ADE0
Port 6 analog input enable register (ADER0)
Address: 00000D H
ADSEL
ADE14
ADE13
ADE12
ADE11
ADE10
ADE9
ADE8
Port B analog input enable register (ADER1)
Address: 00000E H
IL7
IL6
IL5
IL4
IL3
IL2
IL1
IL0
Input level select register (ILSR)
Address: 00000F H
ILSPB
ILI2C
ILRX0
ILRX1
ILB
ILA
IL9
IL8
Input level select register (ILSR)
bit
171
CHAPTER 10 I/O PORTS
10.2.1
Port Data Register
Note that Read/Write for I/O ports differ from Read/Write for memory in the following
points:
• Input mode
Read: The level at the corresponding pin is read.
Write: Data is written to an output latch.
• Output mode
Read: The data register latch value is read.
Write: Data is written to an output latch and output to the corresponding pin.
■ Port Data Register
Figure 10.2-2 shows the port data registers.
Figure 10.2-2 Port Data Registers
PDR0
Address: 000000 H
PDR1
Address: 000001 H
PDR2
Address: 000002 H
PDR3
Address: 000003 H
PDR4
Address: 000004 H
PDR5
Address: 000005 H
PDR6
Address: 000006 H
PDR7
Address: 000007 H
PDR8
Address: 000008 H
PDR9
Address: 000009 H
PDRA
Address: 00000A H
PDRB
Address: 00000B H
172
bit
7
6
5
4
3
2
1
0
P07
P06
P05
P04
P03
P02
P01
P00
15
14
13
12
11
10
9
8
P17
P16
P15
P14
P13
P12
P11
P10
7
6
5
4
3
2
1
0
P27
P26
P25
P24
P23
P22
P21
P20
15
14
13
12
11
10
9
8
P37
P36
P35
P34
P33
P32
P31
P30
7
6
5
4
3
2
1
0
P47
P46
P45
P44
P43
P42
P41
P40
15
14
13
12
11
10
9
8
P57
P56
P55
P54
P53
P52
P51
P50
7
6
5
4
3
2
1
0
P67
P66
P65
P64
P65
P62
P61
P60
15
14
13
12
11
10
9
8
P77
P76
P75
P74
P73
P72
P71
P70
7
6
5
4
3
2
1
0
P87
P86
P85
P84
P83
P82
P81
P80
15
14
13
12
11
10
9
8
P97
P96
P95
P94
P93
P92
P91
P90
7
6
5
4
3
2
1
0
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
15
14
13
12
11
10
9
8
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0
Initial value
Access
XXXXXXXXB
R/W
XXXXXXXXB
R/W
XXXXXXXXB
R/W
XXXXXXXXB
R/W
XXXXXXXXB
R/W
XXXXXXXXB
R/W
XXXXXXXXB
R/W
XXXXXXXXB
R/W
XXXXXXXXB
R/W
XXXXXXXXB
R/W
XXXXXXXXB
R/W
XXXXXXXXB
R/W
CHAPTER 10 I/O PORTS
■ Reading the Port Data Register
When a Port Data register is read, the value depends on the corresponding bit in the Data Direction Register
and on the current status of the resource that is connected to the same pin (if applicable).
The following cases are possible:
DDR value
Resource
Read value
0 (input)
enabled
Resource value
1 (output)
enabled
Resource value
0 (input)
disabled
Pin value
1 (output)
disabled
PDR value
173
CHAPTER 10 I/O PORTS
10.2.2
Data Direction Register
When a pin is used as a port, the corresponding pin is controlled as described below:
0: Input mode
1: Output mode
■ Data Direction Register
Figure 10.2-3 shows the data direction registers.
Figure 10.2-3 Data Direction Registers
DDR0
Address: 000010 H
DDR1
Address: 000011 H
DDR2
Address: 000012 H
DDR3
Address: 000013 H
DDR4
Address: 000014 H
DDR5
Address: 000015 H
DDR6
Address: 000016 H
DDR7
Address: 000017 H
DDR8
Address: 000018 H
DDR9
Address: 000019 H
DDRA
Address: 00001A H
DDRB
Address: 00001B H
bit
7
6
5
4
3
2
1
0
Initial value
Access
D07
D06
D05
D04
D03
D02
D01
D00
00000000B
R/W
00000000B
R/W
00000000B
R/W
00000000B
R/W
00000000B
R/W
00000000B
R/W
00000000B
R/W
00000000B
R/W
00000000B
R/W
00000000B
R/W
00000000B
R/W
00000000B
R/W
15
14
13
12
11
10
9
8
D17
D16
D15
D14
D13
D12
D11
D10
7
6
5
4
3
2
1
0
D27
D26
D25
D24
D23
D22
D21
D20
15
14
13
12
11
10
9
8
D37
D36
D35
D34
D33
D32
D31
D30
7
6
5
4
3
2
1
0
D47
D46
D45
D44
D43
D42
D41
D40
15
14
13
12
11
10
9
8
D57
D56
D55
D54
D53
D52
D51
D50
7
6
5
4
3
2
1
0
D67
D66
D65
D64
D65
D62
D61
D60
15
14
13
12
11
10
9
8
D77
D76
D75
D74
D73
D72
D71
D70
7
6
5
4
3
2
1
0
D87
D86
D85
D84
D83
D82
D81
D80
15
14
13
12
11
10
9
8
D97
D96
D95
D94
D93
D92
D91
D90
7
6
5
4
3
2
1
0
DA7
DA6
DA5
DA4
DA3
DA2
DA1
DA0
15
14
13
12
11
10
9
8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
■ Reading the Data Direction Register
The Data Direction Register can be read independently from the status of the corresponding resource.
However, the value of the DDR influences the result of a read access on the Port Data Register.
174
CHAPTER 10 I/O PORTS
10.2.3
Analog Input Enable Register
This register controls the port 6 and port B pins as described below:
0: Port input/output mode
1: Analog input mode
If an external pin is used as an analog input for the A/D converter, the corresponding bit
should be set to "1".
■ Analog Input Enable Registers
Figure 10.2-4 shows the analog input enable register.
Figure 10.2-4 Analog Input Enable Registers (ADER1/ADER0)
Address:
00000D H
00000C H
bit 15
Initial value:
14
13
12
11
10
9
8
ADSEL ADE14 ADE13 ADE12 ADE11 ADE10 ADE9 ADE8
7
6
5
4
3
2
1
0
ADE7 ADE6 ADE5 ADE4 ADE3 ADE2 ADE1 ADE0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
ADER1/ADER0
Note:
If bit15 (ADSEL) is set to "0" the pins AN0 to AN7 (Port P60 to P67) are selected as inputs for the
A/D Converter. If this bit is set to "1" the pins AN8 to AN14 (Port PB0 to PB6) are selected as inputs
for the A/D Converter.
175
CHAPTER 10 I/O PORTS
10.2.4
Input Level Select Register
The Input Level Select Register allows to switch from Automotive Hysteresis input
levels to CMOS Hysteresis input levels.
■ Input Level Select Register
The input level select register (ILSR) is located on addresses "0EH" and "0FH".
Figure 10.2-5 Input Level Select Register (ILSR)
Address:
00000F H
00000E H
bit
15
14
ILSPB ILI2C
Initial value:
13
12
ILRX0 ILRX1
11
10
9
8
7
6
5
4
3
2
1
0
ILB
ILA
IL9
IL8
IL7
IL6
IL5
IL4
IL3
IL2
IL1
IL0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
ILSR
[bit15] ILSPB
If the ILSPB bit is set to "0", the input level of P44 will be selected by IL4 (bit4 of ILSR). If the ILSPB
bit is set to "1", the input level of P44 will be the opposite of the one selected by the IL4 bit. The initial
value of this bit is "0".
The initial value of this register is "0000H", so the input levels for all ports will be "Automotive
Hysteresis" after reset.
[bit14] ILI2C
If the ILI2C bit is set to "0", the input level of P42/SDA and P43/SCL will be selected by IL4 (bit4 of
ILSR). If the ILI2C bit is set to "1", the input level of P42/SDA and P43/SCL will be the opposite of the
one selected by the IL4 bit. The initial value of this bit is "0".
[bit13] ILRX0
If the ILRX0 bit is set to "0", the input level of P30/RX0 will be selected by IL3 (bit3 of ILSR). If the
ILRX0 bit is set to "1", the input level of P30/RX0 will be the opposite of the one selected by the IL3
bit. The initial value of this bit is "0".
[bit12] ILRX1
If the ILRX1 bit is set to "0", the input level of P21/RX1 will be selected by IL2 (bit2 of ILSR). If the
ILRX1 bit is set to "1", the input level of P21/RX1 will be the opposite of the one selected by the IL2
bit. The initial value of this bit is "0".
[bit11 to bit0] ILB to IL0
These bits set the input level of the corresponding port. IL0 sets the input level of Port0, ILB sets the
input level of PortB. Setting these bits to "0" selects the "Automotive Hysteresis" input level, setting
these bits to "1" selects the "CMOS Hysteresis" input level. The initial value of these bits is "0".
176
CHAPTER 11
TIME-BASE TIMER
This chapter explains the functions and operations of
the time-base timer.
11.1 Outline of Time-base Timer
11.2 Time-base Timer Control Register
11.3 Operations of Time-base Timer
177
CHAPTER 11 TIME-BASE TIMER
11.1
Outline of Time-base Timer
The time-base timer consists of an 18-bit time-base counter and a control register. The
18-bit time-base counter divides the system clock. The time-base timer issues
interrupts at specified intervals based on carry signals of the time-base counter.
■ Outline of Time-base Timer
When the power is turned on, the time-base counter can be cleared to all zeroes by setting the stop mode or
by software (writing "0" to the TBR bit). The time-base counter is incremented while the source oscillation
is input.
The time-base counter can be used as a timer for supplying clock to the watchdog timer or for oscillation
stabilization wait time.
■ Block Diagram of Time-base Timer
Figure 11.1-1 shows a block diagram of the time-base timer.
Figure 11.1-1 Block Diagram of Time-base Timer
WTE
Output enable
WT1
WT0
Reset
control
Two-bit
counter
Selector
Reset
Time-base counter
f/2
Power-on
reset
STOP
mode
1
1
1
1
1
1
1
1
2
11
12
13
14
15
16
17
2
TBC0
178
2
2
2
TBOF
Selector
2
218
IRQ
TBOF
Clear
2
EI OS
1/210 to 1/217 Time-base division output
WS1
WS0
2
Clear
control
TBR
TBC1
2
1
Selector
Osciliation stabilization wait completion signal
CHAPTER 11 TIME-BASE TIMER
11.2
Time-base Timer Control Register
The time-base timer control register controls interrupts of the time-base timer and can
clear the time-base counter.
■ Time-base Timer Control Register (TBTC)
Figure 11.2-1 Configuration of the Time-base Timer Control Register (TBTC)
Address:
0000A9 H
15
14
13
-
-
-
- R/W R/W W R/W R/W
R/W
12
11
10
9
Initial value
1XX00100B
8
bit9
bit8
TBC1
TBC0
0
0
1.024 ms (at 4 MHz)
0
1
4.096 ms (at 4 MHz)
1
0
16.384 ms (at 4 MHz)
1
1
131.072 ms (at 4 MHz)
Time-base Timer Interval Control
bit10
Time-base Timer Reset
TBR
0
1
Read
Write
clear all bits to "0"
always "1"
no effect
bit11
TBOF
Time-base Timer Interrupt Request Flag
Read
Write
0
no interrupt
clear this bit
1
interrupt request
no effect
bit12
TBIE
Time-base Timer Interrupt Enable
0
disable Interrupt
1
enable Interrupt
bit13
-
Undefined
-
-
bit14
-
Undefined
-
-
bit15
Reserved
Reser ved
0
R/W
W
X
-
:
:
:
:
Readable and writable
Write only (read always returns "0")
Undefined value
Undefined
:
Initial value
1
always write "1" to this bit
179
CHAPTER 11 TIME-BASE TIMER
Table 11.2-1 Function Description of Each Bit of the Time-base Timer Control Register
Bit name
Function
This is a reserved bit. When writing data to the TBTC register ensure that "1" is
written to this bit.
bit15
Reserved bit
bit14
Undefined bit
−
bit13
Undefined bit
−
bit12
TBIE
This bit is used to enable interval interrupts based on the time-base timer. Writing
"1" to this bit enables interrupts, and writing "0" disables interrupts. This bit is
initialized to "0" upon a reset. This bit is readable and writable.
TBOF
This is an interrupt request flag for the time-base timer. While the TBIE bit is "1",
an interrupt request is issued when "1" is written to TBOF. This bit is set to "1" for
each interval specified with the TBC1 and TBC0 bits.
This bit is cleared by writing "0", transition to stop or a reset. Writing "1" has no
effect.
"1" is always read by a read-modify-write (RMW) instruction.
TBR
This bit clears all bits of the time-base timer counter to "0".
Writing "0" clears the time-base counter.
Writing "1" has no effect.
"1" is always read from this bit.
TBC1/TBC0
These bits are used to set the time-base timer interval.
Table 11.2-2 lists the specifiable intervals.
bit11
bit10
bit9, bit8
Table 11.2-2 shows the settings for TBC1 and TBC0:
Table 11.2-2 Selecting the Time-base Timer Interval
180
TBC1
TBC0
Interval at 4 MHz source oscillation
0
0
1.024 ms
0
1
4.096 ms
1
0
16.384 ms
1
1
131.072 ms
CHAPTER 11 TIME-BASE TIMER
11.3
Operations of Time-base Timer
The time-base timer functions as a watch-dog timer clock source, timer for oscillation
stabilization wait time, and interval timer for generating interrupts at specified intervals.
■ Time-base Counter
The time-base counter consists of an 18-bit counter for a clock generated by dividing the source oscillation
input by two. This clock is used to generate the machine clock. While the source oscillation is input, the
time-base counter keeps counting. The time-base counter is cleared by a power-on reset, transition to stop
or writing "0" to the TBR bit of the TBTC register.
■ Interval Interrupt Function
Interrupts are generated at specified intervals according to the carry signals of the time-base counter. The
TBOF flag is set at the intervals specified with the TBC1 and TBC0 bits of the TBTC register. The flag is
written to reference to the time at which the time-base timer is cleared last.
Upon transition to stop mode, the time-base timer is used as a timer for oscillation stabilization wait time
upon recovery. Therefore, the TBOF flag is immediately cleared upon mode transition.
181
CHAPTER 11 TIME-BASE TIMER
182
CHAPTER 12
WATCHDOG TIMER
This chapter explains the functions and operations of
the watchdog timer.
12.1 Outline of Watchdog Timer
12.2 Watchdog Timer Operation
183
CHAPTER 12 WATCHDOG TIMER
12.1
Outline of Watchdog Timer
The watchdog timer consists of a two-bit watchdog counter, control register, and
watchdog reset controller. The two-bit watchdog counter uses the carry signals of an
18-bit time-base counter as a clock source.
■ Watchdog Timer Block Diagram
Figure 12.1-1 shows the diagram of the configuration of the watchdog timer.
Figure 12.1-1 Watchdog Timer Block Diagram
Watchdog timer control register (WDTC)
PONR
WRST ERST SRST WTE WT1 WT0
Watchdog timer
2
Activate
Reset occurrence
Sleep mode
Time-base timer mode
Stop mode
Counter clear
control circuit
Count clock
selector
Deactivate
2-bit counter
Reset
occurrence
Watchdog reset
generation circuit
Internal reset
generation
circuit
Clear
4
(Time-base timer counter)
Main clock
(HCLK divided by 2)
HCLK : Oscillation clock
184
21
22
28
29
210
211 212
213
214
215
216
217 218
CHAPTER 12 WATCHDOG TIMER
■ Watchdog Timer Control Register (WDTC)
Figure 12.1-2 Configuration of Watchdog Timer Control Register (WDTC)
bit7
bit6
PONR
-
R
R : Read only
W : Write only
X : Undefined value
- : Undefined
-
Address :
0000A8H
bit5
bit4
WRST ERST SRST
R
R
bit2
bit1
bit0
Initial value
WTE
WT1
WT0
XXXXX111B
W
W
W
bit3
R
[bit7, bit5 to bit3] PONR, WRST, ERST, and SRST
These flags indicate the reset causes. The flags are set upon a reset as described in Table 12.1-1.
All bits are cleared to "0" after the WDTC register is read. These bits are read-only bits.
Table 12.1-1 Reset Cause Registers
Reset cause
PONR
WRST
ERST
SRST
Power-on
1
-
-
-
Watchdog timer
*
1
*
*
External pin
*
*
1
*
RST bit
*
*
*
1
*: The previous value is maintained.
[bit2] WTE
While the watchdog timer is stopped, writing "0" to this bit activates the watchdog timer. Subsequently,
writing "0" clears the watchdog timer counter. Writing "1" has no effect.
The watchdog timer is stopped by power-on or reset by watchdog timer. "1" is always read from this
bit.
185
CHAPTER 12 WATCHDOG TIMER
[bit1, bit0] WT1, WT0
These bits are used to select the watchdog timer interval. Only the data items written during watchdog
timer activation are valid. Data items that are written outside watchdog timer activation are ignored.
Table 12.1-2 lists the interval settings.
These bits are write only bits.
Table 12.1-2 Watchdog Timer Interval Selection Bit
Interval *
WT1
WT0
Main clock cycle count
Minimum
Maximum
0
0
approx. 3.58 ms
approx. 4.61 ms
214 plus or minus 211
cycles
0
1
approx. 14.33 ms
approx. 18.43 ms
216 plus or minus 213
cycles
1
0
approx. 57.23 ms
approx. 73.73 ms
218 plus or minus 215
cycles
1
1
approx. 458.7 ms
approx. 589.82 ms
221 plus or minus 218
cycles
*: For a source oscillation of 4 MHz.
Note:
The interval time uses the carry signal of the time-base timer or clock timer as a count clock. If the
time-base timer or clock timer is cleared, the interval time of the watchdog timer may become long.
The time-base timer is also cleared by writing "0" to the TBR bit in the time-base timer control
register (TBTC), transition from main clock mode to PLL clock mode.
186
CHAPTER 12 WATCHDOG TIMER
12.2
Watchdog Timer Operation
The watchdog timer function enables detection of program surge.
If the watchdog timer is not accessed within the specified time due to, for example, a
program surge, the watchdog timer resets the system.
■ State Transition Diagram of the Watchdog Timer
The watchdog timer has four states:
Inactive:
The watchdog timer does not operate.
Running: The watchdog counter is counting up from "0".
Stopped:
The watchdog counter is stopped at count value "0".
Overflow: The watchdog counter asserts a watchdog reset.
Figure 12.2-1 State Transition Diagram of the Watchdog Timer
Inactive
(Initial State)
Write "0"
to WTE
Reset
Reset
Release of stop mode by interrupt
Release of time-base timer mode by interrupt
Release of sleep mode by interrupt
Running
Start counting from 0
Stopped
count = 0
Transition to stop mode
Transition to time-base timer mode
Transition to sleep mode
Counter
overflow
Overflow
Assert watchdog reset
Always
Write "0" to WTE
187
CHAPTER 12 WATCHDOG TIMER
■ Activation
The watchdog timer is activated by writing "0" to the WTE bit of the WDTC register while the watchdog
timer is stopped. At the same time, the WT1 and WT0 bits are used to set the watchdog timer reset interval.
Only the interval setting specified during activation is valid.
■ Watchdog Counter
Once the watchdog timer is activated, the watchdog timer counter must be periodically cleared within the
program. Writing "0" to the WTE bit of the WDTC register clears the watchdog counter. The watchdog
counter consists of a two-bit counter which uses the carry signals of the time-base timer as a clock source.
Therefore, the watchdog reset time may become longer than the setting if the time-base counter is cleared.
Figure 12.2-2 is a diagram of the watchdog timer operation.
Figure 12.2-2 Watchdog Timer Operation
Time-base
Watch-dog
00
01
10
00
01
10
11
00
WTE write
Watchdog
activation
Watchdog
clear
Watchdog reset
■ Watchdog Stop
The watchdog timer is stopped by transition to stop mode, time-base timer mode or sleep mode.
■ Watchdog Deactivation
The watchdog timer is deactivated by any kind of reset
■ Watchdog Timer Behavior in Stop Mode, Time-base Timer Mode, and Sleep Mode
When transition to stop mode, time-base timer, mode or sleep mode occurs, watchdog timer is cleared and
stops. When CPU is release from stop mode, time-base timer mode, or sleep mode, watchdog timer starts
counting again from cleared state (Table 12.2-1).
188
CHAPTER 12 WATCHDOG TIMER
■ Watchdog Timer Behavior at Reset
When any kind of reset is asserted, the watchdog timer is deactivated and remains inactive after reset is
released (Table 12.2-1).
Table 12.2-1 : Watchdog Timer Clear and Stop Conditions
Mode
Reset
WDTC
register
WTE=0
Stop mode
Sleep mode
Time-base
timer mode
Transition
to the mode
Writing
to the register
Transition
to the mode
Transition
to the mode
Transition
to the mode
Watchdog state during
the mode
Inactive
N/A
Stopped
(keep cleared)
Stopped
(keep cleared)
Stopped
(keep cleared)
Watchdog reset during
the mode
Does not occur
N/A
Does not occur
Does not occur
Does not occur
Inactive
Running (start
counting from
cleared state)
Running (start
counting from
cleared state)
Running (start
counting from
cleared state)
Running (start
counting from
cleared state)
Counter clear timing
Watchdog state after
leaving the mode
This Table assumes that the previous watchdog state was "Running".
189
CHAPTER 12 WATCHDOG TIMER
190
CHAPTER 13
16-BIT I/O TIMER
This chapter explains the functions and operations of
the 16-bit I/O timer.
13.1 Outline of 16-Bit I/O Timer
13.2 16-Bit I/O Timer Registers
13.3 16-bit Free-run Timer
13.4 Output Compare
13.5 Input Capture
191
CHAPTER 13 16-BIT I/O TIMER
13.1
Outline of 16-Bit I/O Timer
The MB90390 Series contains two 16-bit free-run timer modules, four output compare
modules, and three input capture modules and supports six input channels and eight
output channels. The following sections describe the 16-bit free-run timer, Output
Compare and Input Capture.
■ 16-bit Free-run Timer
The two 16-bit free-run timers consist of a 16-bit up counter, control register, and prescaler each. The
values output from this timers counter are used as the base timer for input capture and output compare.
● Eight counter clocks are available.
Internal clock: φ, φ/2, φ /4, φ/8, φ/16, φ/32, φ/64, φ/128 (φ is machine clock)
● An interrupt can be generated upon a counter overflow or a match with compare register 0 and 1.
● The counter value can be initialized to "0000H" upon a reset, software clear, or match with compare
register 0 for timer 0, resp. compare register 4 for timer 1.
■ Output Compare (2 Channels Per One Module)
The four output compare modules consist of two 16-bit compare registers, compare output latch, and
control register each.
Output Compare 0 and 1 (channels OUT0, OUT1, OUT2 and OUT3) are assigned to Free-run Timer 0 and
Output Compare 2 and 3 (channels OUT4, OUT5, OUT6 and OUT7) are assigned to Free-run Timer 1.
When a 16-bit free-run timer value matches the corresponding compare register value, the output level is
reversed and an interrupt can be issued.
● The two compare registers can be used independently for each Output Compare.
Output pins and interrupt flags corresponding to compare registers
● Output pins can be controlled based on pairs of the two compare registers.
Output pins can be reversed by using the two compare registers.
● Initial values for output pins can be set.
● Interrupts can be generated upon a compare match.
192
CHAPTER 13 16-BIT I/O TIMER
■ Input Capture (2 Channels per One Module)
The three input capture modules consist of two 16-bit capture registers and control registers each
corresponding to two independent external input pins.
Input Capture 0 (channels IN0 and IN1) is assigned to Free-run Timer 0 and Input Capture 1 and 2
(channels IN2, IN3, IN4 and IN5) are assigned to Free-run Timer 1.
The 16-bit free-run timer values can be stored in the capture register and an interrupt is issued
simultaneously upon detection of an edge of a signal input from an external input pin.
● The detection edge of an external input signal can be specified.
Rising, falling, or both edges
● Two input channels can operate independently.
● An interrupt can be issued upon a valid edge of an external input signal.
The intelligent I/O service can be activated upon an input capture interrupt.
■ Block Diagram of 16-bit I/O Timer
Figure 13.1-1 shows a block diagram of the 16-bit I/O timer.
Figure 13.1-1 Block Diagram of 16-bit I/O Timer
Control logic
To each block
Interrupt
16-bit free-run timer 0/1
16-bit timer
FRCK
Bus
Clear
Output compare 0/2/4/6
Compare register 0
T Q
Output compare 1/3/5/7
Compare register 1
T Q
OUT0
OUT2
OUT4
OUT6
OUT1
OUT3
OUT5
OUT7
Input capture 0/2/4
Capture register 0
Input capture 1/3/5
Capture register 1
Edge selection
IN0
IN2
IN4
Edge selection
IN1
IN3
IN5
193
CHAPTER 13 16-BIT I/O TIMER
13.2
16-Bit I/O Timer Registers
The 16-bit I/O timer has the following three registers:
• 16-bit free-run timer register
• 16-bit output compare register
• 16-bit input capture register
■ 16-bit Free-run Timer 0 and 1
bit 15
0
Address:
00352C H
TCDT0
Timer data register 0
00353C H
TCDT1
Timer data register 1
00352E H
TCCSH0
TCCSL0
Timer status register 0
00353E H
TCCSH1
TCCSL1
Timer status register 1
■ 16-bit Output Compare
Address: bit 15
003530 H
003532 H
194
0
OCCP0/OCCP1
Compare register 0/1
003534 H
003536 H
OCCP2/OCCP3
Compare register 2/3
003538 H
00353A H
OCCP4/OCCP5
Compare register 4/5
00356A H
00356C H
OCCP6/OCCP7
Compare register 6/7
000058 H
000059 H
OCS1
OCS0
Control status register 0/1
00005A H
00005B H
OCS3
OCS2
Control status register 2/3
00005C H
00005D H
OCS5
OCS4
Control status register 4/5
003568 H
003569 H
OCS7
OCS6
Control status register 6/7
CHAPTER 13 16-BIT I/O TIMER
■ 16-bit Input Capture
Address: bit 15
003520 H
003522 H
0
IPCP0/IPCP1
Capture register 0/1
003524 H
003526 H
IPCP2/IPCP3
Capture register 2/3
003528 H
00352A H
IPCP4/IPCP5
Capture register 4/5
000054 H
000055 H
ICS0/ICS1
0035C9 H
ICS4/ICS5
ICE01
0035CAH
0035CBH
Control register 2/3
ICS2/ICS3
000056 H
Control register 4/5
Capture Edge register 0/1
ICE23
ICE45
Control register 0/1
Capture Edge register 2/3
Capture Edge register 4/5
195
CHAPTER 13 16-BIT I/O TIMER
13.3
16-bit Free-run Timer
The 16-bit free-run timer consists of a 16-bit up counter and a control status register.
The count values of this timer are used as the base timer for the output compares and
input captures.
• Eight counter clock frequencies are available.
• An interrupt can be generated upon a counter value overflow.
• The counter value can be initialized upon a match with compare register 0 (free-run
timer 0) or compare register 4 (free-run timer 1), depending on the mode.
• Two separate timers are available on MB90390 series.
■ 16-bit Free-run Timer Block Diagram
Figure 13.3-1 16-bit Free-run Timer Block Diagram
φ
Interrupt request
IVF
IVFE STOP MODE CLR CLK2 CLK1 CLK0
Divider
FRCK
Comparator 0 /1
Bus
16-bit up counter
Clock
Count value output
Note: The figure above is also valid for Timer 1
Timer 0 is connected to ICU0/ICU1 and OCU0/OCU1/OCU2/OCU3
Timer 1 is connected to ICU2/ICU3/ICU4/ICU5, OCU4/OCU5/OCU6/OCU7
196
T15
to
T00
CHAPTER 13 16-BIT I/O TIMER
13.3.1
Data Register
The data register can read the count value of the 16-bit free-run timer. The counter value
is cleared to "0000B" upon a reset. The timer value can be set by writing a value to this
register. However, ensure that the value is written while the operation is stopped
(STOP=1).
The data register must be accessed by the word access instructions.
■ Data Register of Free-run Timer
Figure 13.3-2 Data Register of Free-run Timer (TCDT0/TCDT1)
Address:
bit 15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
352CH
352DH
Tn15 Tn14 Tn13 Tn12 Tn11 Tn10 Tn9 Tn8 Tn7 Tn6 Tn5 Tn4 Tn3 Tn2 Tn1 Tn0
353CH
353DH
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
TCDT0/TCDT1
Initial value
0000000000000000B
bit0 to bit7
lower bits
TCDT0/TCDT1
Tn0
Timer Data Reg. 0
Tn1
Timer Data Reg. 1
Tn2
Timer Data Reg. 2
Tn3
Timer Data Reg. 3
Tn4
Timer Data Reg. 4
Tn5
Timer Data Reg. 5
Tn6
Timer Data Reg. 6
Tn7
Timer Data Reg. 7
n = 0, 1
bit8 to bit15
TCDT0/TCDT1
R/W
:
Readable and writable
upper bits
Tn8
Timer Data Reg. 8
Tn9
Timer Data Reg. 9
Tn10
Timer Data Reg. 10
Tn11
Timer Data Reg. 11
Tn12
Timer Data Reg. 12
Tn13
Timer Data Reg. 13
Tn14
Timer Data Reg. 14
Tn15
Timer Data Reg. 15
n = 0, 1
The 16-bit free-run timer is initialized upon the following factors:
•
Reset
•
Clear bit (CLR) of control status register
•
Free-run timer 0: A match between compare register 0 and the timer counter value.
•
Free-run timer 1: A match between compare register 4 and the timer counter value.
197
CHAPTER 13 16-BIT I/O TIMER
13.3.2
Control Status Register
The control status register sets the operation mode of the 16-bit free-run timer, starts
and stops the 16-bit free-run timer, and controls interrupts.
■ Control Status Register of Free-run Timer (Lower)
Figure 13.3-3 Control Status Register of Free-run Timer (TCCSL0/TCCSL1)
Address: bit 7
00352EH
00353EH
IVF
6
5
4
3
2
1
0
TCCSL0/TCCSL1
Initial value
0 0 0 0 0 0 0 0B
IVFE STOP MODE CLR CLK2 CLK1 CLK0
R/W R/W R/W R/W R/W R/W R/W R/W
bit 2
bit1
CLK2
CLK1
bit 0
0
0
0
φ
0
0
1
φ/2
0
1
0
φ/4
0
1
1
φ/8
1
0
0
φ / 16
1
0
1
φ / 32
1
1
0
φ / 64
1
1
1
φ / 128
CLK0
Count Clock Selection
φ = MCU clock
bit 3
CLR
0
1
Clear Timer
Read
Write
read always "0"
no effect
clear timer to "0000B"
bit 4
MODE
0
1
Set Reset condition of timer
Initialization by reset or clear bit
Init. by reset, clear bit, or compare reg. 0 (4)
bit 5
STOP
0
1
Stop the timer
Counter enabled
Counter disabled (stop)
bit 6
IVFE
Interrupt enable bit
0
Interrupt disabled
1
Interrupt enabled
bit 7
IVF
R/W
198
Interrupt request flag bit
Read
Write
:
Readable and writable
0
No interrupt
clear this bit
:
Initial value
1
Interrupt request
no effect
CHAPTER 13 16-BIT I/O TIMER
Table 13.3-1 Control Status Register of Free-run Timer (Lower)
Bit name
bit7
bit6
IVF:
Interrupt request flag
bit and clear bit
IVFE:
Function
•
•
•
•
This bit is the interrupt request flag bit and clear bit
Writing "0": A possible interrupt is cleared.
Writing "1": No effect.
"1" is always read during a read-modify-write (RMW) instructions cycle.
• This bit enables the interrupt request
• Writing "0": Interrupt disabled.
• Writing "1": Interrupt enabled.
bit5
STOP:
STOP bit
• The STOP bit is used to stop the timer.
• Writing "0": Counter enabled (operation).
• Writing "1": Counter disabled (stop).
bit4
MODE:
MODE bit
• "0": Initialization by reset or clear bit
• "1": Free-run timer 0: Initialization by reset, clear bit, or compare register 0
Free-run timer 1: Initialization by reset, clear bit, or compare register 4
CLR:
CLR bit
• The CLR bit initializes the operating free-run timer to the value "0000B"
• Writing "0": no effect.
• Writing "1": Counter is initialized.
Note:
To initialize the counter value while the timer is stopped, write "0000B" to the data
register.
bit3
These bits are used to select the count clock for the 16-bit-free-run timer. The clock is
updated immediately after a value is written to these bits. Therefore, ensure that the
input capture operations are stopped before a value is written to these bits.
bit2 to
bit0
CLK2, CLK1,
CLK0:
CLK2
CLK1
CLK0
Count
clock
φ=
20 MHz
φ=
16 MHz
φ=
8 MHz
φ=
4 MHz
φ=
1 MHz
0
0
0
φ
50 ns
62.5 ns
125 ns
0.25 μs
1 μs
0
0
1
φ /2
100 ns
125 ns
0.25 μs
0.5 μs
2 μs
0
1
0
φ /4
0.2 μs
0.25 μs
0.5 μs
1 μs
4 μs
0
1
1
φ /8
0.4 μs
0.5 μs
1 μs
2 μs
8 μs
1
0
0
φ / 16
0.8 μs
1 μs
2 μs
4 μs
16 μs
1
0
1
φ / 32
1.6 μs
2 μs
4 μs
8 μs
32 μs
1
1
0
φ / 64
3.2 μs
4 μs
8 μs
16 μs
64 μs
1
1
1
φ / 128
6.4 μs
8 μs
16 μs
32 μs
128 μs
199
CHAPTER 13 16-BIT I/O TIMER
■ Control Status Register of Free-run Timer (Upper)
Figure 13.3-4 Control Status Register of Free-run Timer (TCCSH0/1)
Address: bit 15 14
00352FH ECKE 00353FH
13
12
11
10
9
8
-
-
-
-
-
-
-
-
-
-
-
-
-
R/W
TCCSH0/TCCSH1
Initial value
0xxxxxxx
ECKE
0
R/W
:
Readable and writable
-
:
Undefined
:
Initial value
1
B
External clock enable
Internal time clock
external clock from FRCK
Table 13.3-2 Control Status Register of Free-run Timer (Upper)
Bit name
bit15
bit14 to
bit8
200
ECKE:
External clock enable
bit
Undefined
Function
• This bit chose between internal time clock and external clock from FRCK
• Writing "0": Internal clock selected.
• Writing "1": External clock selected.
−
CHAPTER 13 16-BIT I/O TIMER
13.3.3
16-bit Free-run Timer Operation
The 16-bit free-run timer starts counting from counter value "0000B" after the reset is
released. The counter value is used as the reference time for the 16-bit output compare
and 16-bit input capture operations.
■ 16-bit Free-run Timer Operation
The counter value is cleared in the following conditions:
•
When an overflow occurs
•
When a match with the output compare register 0 (free-run timer 0) or output compare register 4 (freerun timer 1) occurs (This depends on the mode.)
•
When "1" is written to the CLR bit of the TCCS register during operation
•
When "0000H" is written to the TCDT register during stop
•
Reset
An interrupt can be generated when an overflow occurs or when the counter matches with the compare
register 0 (4). (Compare match interrupts can be used only in an appropriate mode.)
■ Clearing the Counter by an Overflow
Figure 13.3-5 Clearing the Counter by an Overflow
Counter value
FFFF H
Overflow
BFFF H
7FFF H
3FFF H
0000 H
Time
Reset
Interrupt
201
CHAPTER 13 16-BIT I/O TIMER
■ Clearing the Counter Upon a Match with Output Compare Register 0 (4)
Figure 13.3-6 Clearing the Counter Upon a Match with Output Compare Register 0 (4)
Counter value
FFFF H
Match
BFFF H
Match
7FFF H
3FFF H
Time
0000 H
Reset
Compare
register value
Interrupt
BFFFH
■ 16-bit Free-run Timer Timing
● 16-bit free-run timer clear timing (match with the compare register 0/4)
The counter can be cleared upon a reset, software clear, or a match with the compare register 0 (4). By a
reset or software clear, the counter is immediately cleared. By a match with compare register 0 (4), the
counter is cleared in synchronization with the count timing.
Figure 13.3-7 16-bit Free-run Timer Clear Timing (Match with the Compare Register 0/4)
φ
N
Compare
register value
Compare match
Counter value
202
N
0000H
CHAPTER 13 16-BIT I/O TIMER
13.4
Output Compare
The output compare module consists of two 16-bit compare registers, two compare
output pins, and one control register. If the value written to the compare register of this
module matches the 16-bit free-run timer value, the output level of the pin can be
reversed and an interrupt can be issued.
■ Output Compare
•
Four separate Output Compare Modules are available on MB90390 series.
•
For each module, two compare registers exist which can be used independently. Depending on the
mode setting, the two compare registers can be used to control pin outputs.
•
The initial value for each pin output can be specified separately.
•
An interrupt can be issued upon a match as a result of comparison.
•
One pulse width modulated signal can be generated for each module.
•
Three pulse width modulated signals are possible for each of the two Free-run Timers.
■ Output Compare Block Diagram
Figure 13.4-1 shows a block diagram of output compare.
Figure 13.4-1 Output Compare Block Diagram
16-bit timer counter value (T15 to T00)
T
Compare control
Q
OTE0
OUT0
CMP0EXT / CMP4EXT
Compare register 0
CMOD1
16-bit timer counter value (T15 to T00)
Bus
CMOD0
T
Compare control
Q
OTE1
OUT1
Compare register 1
ICP1
ICP0 ICE1 ICE0
Controller
Control blocks
Compare 1
interrupt
Compare 0
interrupt
Note: The figure above is also valid for Output Compare Unit 2/3, 4/5, and 6/7
Figure 13.4-5 shows the block diagram of output selection (OCU Module 1)
203
CHAPTER 13 16-BIT I/O TIMER
13.4.1
Output Compare Register
These 16-bit compare registers are compared with the 16-bit free-run timer. Since the
initial register values are undefined, set appropriate value before enabling the
operation. These registers must be accessed by the word access instructions. When
the value of the register matches that of the 16-bit free-run timer, a compare signal is
generated and the output compare interrupt flag is set. If output is enabled, the output
level corresponding to the compare register is reversed.
To rewriting the compare register, within the compare interrupt routine or compare
operation is disabled. Be sure not to occur simultaneously a compare match and
writing the compare register.
■ Output Compare Register
Figure 13.4-2 Output Compare Register (OCCP)
bit 15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Address:
003530 H
003531 H C15 C14 C13 C12 C11 C10 C09 C08 C07 C06 C05 C04 C03 C02 C01 C00
003532 H
003533 H R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
003534 H
003535 H
003536 H
003537 H
OCCP0
OCCP1
:
OCCP7
Initial value
XXXXXXXXXXXXXXXX
bit0 to bit7
OCCPn
003538 H
003539 H
00353A H
00353B H
00356A H
00356B H
00356C H
00356E H
lower bits
C00
Compare Data Reg. 0
C01
Compare Data Reg. 1
C02
Compare Data Reg. 2
C03
Compare Data Reg. 3
C04
Compare Data Reg. 4
C05
Compare Data Reg. 5
C06
Compare Data Reg. 6
C07
Compare Data Reg. 7
n = 0, 1, 2, 3, 4, 5, 6, 7
bit8 to bit15
OCCPn
R/W
204
:
Readable and writable
upper bits
C08
Compare Data Reg. 8
C09
Compare Data Reg. 9
C10
Compare Data Reg. 10
C11
Compare Data Reg. 11
C12
Compare Data Reg. 12
C13
Compare Data Reg. 13
C14
Compare Data Reg. 14
C15
Compare Data Reg. 15
n = 0, 1, 2, 3, 4, 5, 6, 7
B
CHAPTER 13 16-BIT I/O TIMER
13.4.2
Control Status Register of Output Compare
The control status register sets the operation mode of output compare, starts and stops
output compare, controls interrupts, and sets the external output pins.
■ Control Status Register of Output Compare (Lower)
Figure 13.4-3 Control Status Register of Output Compare (OCS0/OCS2/OCS4/OCS6)
5 4
3
Address: bit 7 6
000058 H ICPm ICPn ICEm ICEn
00005A H
00005CH R/W R/W R/W R/W -
003568 H
2
1
0
CSTm CSTn
-
R/W R/W
OCS0
OCS4
OCS2
OCS6
Initial value
0 0 0 0 X X 0 0B
bit 0
CSTn
Comparison with timer for unit n
0
Compare operation disabled for unit n
1
Compare operation enabled for unit n
bit 1
CSTm
Comparison with timer for unit m
0
Compare operation disabled for unit m
1
Compare operation enabled for unit m
bit 4
Compare interrupt enable for unit n
ICEn
0
Output compare interrupt disabled for unit n
1
Output compare interrupt enabled for unit n
bit 5
Compare interrupt enable for unit m
ICEm
0
Output compare interrupt disabled for unit m
1
Output compare interrupt enabled for unit m
bit 6
ICPn
Compare match enable for unit n
0
No compare match for unit n
1
Compare match for unit n
bit 7
ICPm
Compare match enable for unit m
R/W
:
Readable and writable
0
No compare match for unit m
X
:
:
Undefined value
1
Compare match for unit m
:
Initial value
-
Undefined
n = 0, 2, 4, 6 m = 1, 3, 5, 7
205
CHAPTER 13 16-BIT I/O TIMER
Table 13.4-1 Control Status Register of Output Compare (Lower)
Bit name
bit7
ICPm
bit6
ICPn
bit5
ICEm
bit4
ICEn
bit3, bit2
bit1
CSTm
bit0
CSTn
n = 0, 2, 4, 6
206
Undefined
m = 1, 3, 5, 7
Function
• These bits are used as output compare interrupt flags. "1" is set to these bits when the
compare register value matches the 16-bit free-run timer value. While the interrupt
request bits (ICEm and ICEn) are enabled, an output compare interrupt occurs when
the ICPm and ICPn bits are set. These bits are cleared by writing "0".
• "0": No compare match.
• "1": Compare match.
• Writing "1" has no effect.
• "1" is always read by a read-modify-write (RMW) instruction.
Note:
ICPn: Corresponds to output compare n.
ICPm: Corresponds to output compare m.
• These bits are used as output compare interrupt enable flags. While the "1" is written to
these bits, an output compare interrupt occurs when an interrupt flag (ICPm or ICPn) is
set.
• Writing "0": Output compare interrupt disabled.
• Writing "1": Output compare interrupt enabled.
Note:
ICEn: Corresponds to output compare unit n.
ICEm: Corresponds to output compare unit m.
• These bits are used to enable the compare register before the compare operation is
enabled
• Writing "0": Compare operation disabled.
• Writing "1": Compare operation enabled.
Note:
Ensure that a value is written to the compare register before the compare operation is
enabled.
CSTn: Corresponds to output compare n.
CSTm: Corresponds to output compare m.
Since output compare is synchronized with the 16-bit free-run timer clock, stopping
the 16-bit free-run timer stops compare operation.
CHAPTER 13 16-BIT I/O TIMER
■ Control Status Register of Output Compare (Upper)
Figure 13.4-4 Control Status Register of Output Compare (OCS1/OCS3/OCS5/OCS7)
Address: bit 15 14
000059 H CMOD1
00005B H
00005DH R/W -
13
12
11
10
9
8
-
CMOD0 OTEm OTEn OTDm OTDn
-
R/W R/W R/W R/W R/W
003569 H
OCS1
OCS5
OCS3
OCS7
Initial value
0XX00000B
bit 8
OTDn
0
Output Pin Level Select for unit n
Sets "0" for compare pin output for unit n
1
Sets"1" for compare pin output for unit n
bit 9
OTDm
0
Output Pin Level Select for unit m
Sets "0" for compare pin output for unit m
1
Sets"1" for compare pin output for unit m
bit 10
OTEn
0
1
Output Pin Select for unit n
General-purpose port for correspond. pin of unit n
Output compare pin output for unit n
bit11
OTEm
0
1
R/W
:
Readable and writable
X
-
:
:
Undefined value
Undefined
:
Initial value
Output Pin Select for unit m
General-purpose port for correspond. pin of unit m
Output compare pin output for unit m
bit 15
bit 12
CMOD1
CMOD0
0
0
Define Comparison mode for Pin
Refer to table 13.4-3.
n = 0, 2, 4, 6 m = 1, 3, 5, 7
207
CHAPTER 13 16-BIT I/O TIMER
Table 13.4-2 Control Status Register of Output Compare (Upper)
Bit name
Function
bit15, bit12
CMOD0,
CMOD1
These bits define the operation mode for the pin output value. Depending on the
defined mode, the level is reversed upon a match with different compare registers. See
Table 13.4-3 and Section "13.4.3 16-bit Output Compare Operation" for details.
bit14, bit13
Undefined
-
bit11
OTEm
bit10
OTEn
bit9
OTDm
bit8
OTDn
n = 0, 2, 4, 6
208
m = 1, 3, 5, 7
These bits are used to enable the output compare output pins. The initial value for these
bits is "0".
• "0": General-purpose port.
• "1": Output compare pin output.
Note:
OTEn: Corresponds to output compare n.
OTEm: Corresponds to output compare m.
When they are specified as outputs, the corresponding bits of the Port Direction
Registers should also be set to "1".
These bits are used to change the pin output level when the compare pin output is
enabled. The initial value of the compare pin output is "0". Ensure that the compare
operation is stopped before a value is written. When read, these bits indicate the output
compare pin output value.
• Writing "0": Sets "0" for compare pin output.
• Writing "1": Sets "1" for compare pin output.
Note:
OTDn: Corresponds to output compare n.
OTDm: Corresponds to output compare m.
CHAPTER 13 16-BIT I/O TIMER
Table 13.4-3 Function of CMOD1 and 0 Bits
Pin output value reversed upon match with register no.
OCS1
Register OCCPx
CMOD1
CMOD0
OUT0
OUT1
x
0
0
1
1
0
0/1
x
OCS3
Register OCCPx
CMOD1
CMOD0
OUT2
OUT3
0
0
2
3
0
1
2
2/3
1
0
0/2
0/3
1
1
0/2
0/2/3
OCS5
Register OCCPx
CMOD1
CMOD0
OUT4
OUT5
x
0
4
5
x
1
4
4/5
OCS7
Register OCCPx
CMOD1
CMOD0
OUT6
OUT7
0
0
6
7
0
1
6
6/7
1
0
4/6
4/7
1
1
4/6
4/6/7
Figure 13.4-5 Block Diagram of Output Selection (OCU Module 1)
Compare
Control 2
OUT2
CMOD1
CMP0EXT
CMOD0
Compare
Control 3
OUT3
For OCU module 1, which requires a match with Output Compare Register 0 if CMOD[1:0] = 10B, the
comparison result from module 0 is carried inside by the CMP0EXT signal. Of course, this does not apply
to module 0 itself. Here, no other register can be used but OCCP0 and OCCP1.
The equivalent situation applies to OCU module 3, where the result from module 2 is needed as
CMP4EXT.
209
CHAPTER 13 16-BIT I/O TIMER
13.4.3
16-bit Output Compare Operation
In the 16-bit output compare operation, an interrupt request flag can be set and the
output level can be reversed when the specified compare register value matches the 16bit free-run timer value. The CMOD0 and CMOD1 bits can be used to define the
corresponding compare registers for each pin.
■ Sample Output Waveform when CMOD[1:0] = 00B
When CMOD[1:0] = 00B, the output level of the pin corresponding to the compare register is reversed on
every match with the register value. Each output value is controlled by one compare register.
OUT0: The level is only reversed by a match with compare register 0.
OUT1: The level is only reversed by a match with compare register 1.
Figure 13.4-6 Sample of Output Waveform when CMOD[1:0] = 00B
Counter value
FFFFH
BFFFH
7FFFH
3FFFH
0000H
Time
Reset
OCCP0 value
BFFFH
OCCP1 value
7FFFH
OUT0
OUT1
Compare 0
interrupt
Compare 1
interrupt
Note: In this figure, the initial value is "0" for both pins.
210
CHAPTER 13 16-BIT I/O TIMER
■ Sample Output Waveform with Two Compare Registers when CMOD[1:0] = 01B
When CMOD[1:0] = 01B, the output level of the pin corresponding to compare register 0 (2) is reversed
upon every match with the register value. This is identical to the behavior for CMOD[1:0] = 00B. However,
the output level of the second pin is reversed upon a match with either compare register 0 or compare
register 1 (3). This allows to define a pulsed signal with one edge defined by the value in compare register
0 and the other edge defined by compare register 1 (3) or vice versa. If both compare registers have the
same value, the operation is identical to the case for CMOD[1:0] = 00B.
A pulse width modulated signal with differing frequency can be defined by using this mode together with
the reset option by compare register match for the Free-run timer (MODE-bit in TCCSL0/TCCSL1
registers).
OUT0 (2): The level is only reversed by a match with compare register 0 (2).
OUT1 (3): The level is reversed by a match with compare register 0 (2) or with compare register 1 (3).
For OUT4, OUT5, OUT6 and OUT7, compare register 4 plays the same role as compare register 0 above.
Figure 13.4-7 Sample of a Output Waveform when CMOD[1:0] = 01B (No Timer Reset by Match)
Counter value
FFFFH
BFFFH
7FFFH
3FFFH
0000H
Time
Reset
OCCP0 value
BFFFH
OCCP1 value
7FFFH
OUT0
OUT1
Note: In this figure, the initial value is "0" for both pins.
Figure 13.4-8 Sample of a Output Waveform when CMOD[1:0] = 01B (With Timer Reset by Match)
Counter value
FFFFH
BFFFH
7FFFH
3FFFH
0000H
Time
Reset
OCCP0 value
BFFFH
OCCP1 value
7FFFH
OUT0
OUT1
Note: In this figure, the initial value is "0" for both pins.
211
CHAPTER 13 16-BIT I/O TIMER
■ Sample Output Waveform when CMOD[1:0] = 10B
The operation mode defined by CMOD[1:0] = 10B is intended for the use of three pulse width modulated
signals for each free-run timer instead of two. If this mode is set to OCU module 1, a match of the timer
value with compare register 0 reverses both OUT2 and OUT3. For the third pulsed signal, the
CMOD[1:0] bits of OCU module 0 should be set to "01B".
In register OCS1: CMOD[1:0] = 01B
OUT0: The level is only reversed by a match with compare register 0.
OUT1: The level is reversed by a match with compare register 0 or with compare register 1.
In register OCS3: CMOD[1:0] = 10B
OUT2: The level is reversed by a match with compare register 0 or with compare register 2.
OUT3: The level is reversed by a match with compare register 0 or with compare register 3.
For OUT4, OUT5, OUT6 and OUT7, compare register 4 plays the same role as compare register 0 above.
Figure 13.4-9 Output Waveform when OCS1:CMOD[1:0] = 01B and OCS3:CMOD[1:0] = 10B
Counter value
FFFFH
BFFFH
7FFFH
3FFFH
0000H
Time
Reset
OCCP0 value
BFFFH
OCCP1 value
7FFFH
OCCP2 value
3FFFH
OCCP3 value
5FFFH
OUT0
OUT1
OUT2
OUT3
Note: In this figure, the initial value is "0" for all pins. Timer reset is by match with compare register 0.
212
CHAPTER 13 16-BIT I/O TIMER
■ Sample Output Waveform when CMOD[1:0] = 11B
When CMOD[1:0] = 11B, the output level of the OUT3 (OUT7) pin is reversed by the compare registers 0,
2 or 3 (4, 6 or 7). For the pin OUT1 (OUT5), this setting is identical to CMOD[1:0] = 01B (see also Table
13.4-3).
OUT0: The level is only reversed by a match with compare register 0.
OUT1: The level is reversed by a match with compare register 0 or with compare register 1.
OUT2: The level is reversed by a match with compare register 0 or with compare register 2.
OUT3: The level is reversed by a match with compare register 0, compare register 2 or with compare
register 3.
For OUT4, OUT5, OUT6 and OUT7, compare register 4 plays the same role as compare register 0 above.
Figure 13.4-10 Output Waveform when OCS1:CMOD[1:0] = 11B and OCS3:CMOD[1:0] = 11B
Counter value
FFFFH
BFFFH
7FFFH
3FFFH
0000H
Time
Reset
OCCP0 value
BFFFH
OCCP1 value
7FFFH
OCCP2 value
3FFFH
OCCP3 value
5FFFH
OUT0
OUT1
OUT2
OUT3
Note: In this figure, the initial value is "0" for all pins. Timer reset is by match with compare register 0.
213
CHAPTER 13 16-BIT I/O TIMER
■ Output Compare Timing
In output compare operation, a compare match signal is generated when the free-run timer value matches
the specified compare register value. The output value can be reversed and an interrupt can be issued. The
output reverse timing upon a compare match is synchronized with the counter timing.
● Compare operation upon update of compare register
When the compare register is updated, comparison with the counter value is not performed.
● Interrupt timing
Figure 13.4-11 Interrupt Timing
φ
N
Counter value
Compare register
value
N+1
N
Compare match
Interrupt
● Output pin change timing
Figure 13.4-12 Output Pin Change Timing
Counter value
Compare register
value
Compare match
signal
Pin output
214
NN+1
N+1
N
N
CHAPTER 13 16-BIT I/O TIMER
13.5
Input Capture
Input capture detects a rising or falling edge or both edges of an external input signal
and stores a 16-bit free-run timer value at that time in a register. In addition, input
capture can generate an interrupt upon detection of an edge. Input capture consists of
an input capture data register and a control register.
■ Input Capture
Each input capture has a corresponding external input pin.
● The valid edge of an external input can be selected from the following three types:
Table 13.5-1 Types of External Input Edges
Rising edge
Falling edge
Both edges
● An interrupt can be generated upon detection of a valid edge of an external input.
■ Input Capture Block Diagram
Figure 13.5-1 shows the input capture block diagram.
Figure 13.5-1 Input Capture Block Diagram
IN0
Edge detection
Capture data register 0
Count value from Free-run Timer
EG11 EG10 EG01 EG00
IEI1
IEI0
Bus
Capture data register 1
Edge detection
ICP1
ICP0
IN1
ICE1 ICE0
Interrupt
Interrupt
Note: The figure above is also valid for Input Capture Unit 2/3 and 4/5
215
CHAPTER 13 16-BIT I/O TIMER
13.5.1
Input Capture Register Details
Input capture has the three registers listed. These registers store a value from the 16-bit
free-run timer when a valid edge of the corresponding external pin input waveform is
detected. (The registers must be accessed in word mode. No values can be written to
the registers.)
• Input capture data register
• Input capture control register
• Input capture edge register
■ Input Capture Data Register
Figure 13.5-2 Input Capture Data Register (IPCP)
Address: bit 15
003520H
003522H
003524H
R
003526H
003528H
00352AH
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
IPCP0 to IPCP5
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Initial value
XXXXXXXXXXXXXXXXB
IPCPn
lower bits
CP00
Input Capt. Data Reg. 0
CP01
Input Capt. Data Reg. 1
CP02
Input Capt. Data Reg. 2
CP03
Input Capt. Data Reg. 3
CP04
Input Capt. Data Reg. 4
CP05
Input Capt. Data Reg. 5
CP06
Input Capt. Data Reg. 6
CP07
Input Capt. Data Reg. 7
n = 0,1,2,3,4,5
IPCPn
R
216
:
Read only
upper bits
CP08
Input Capt. Data Reg. 8
CP09
Input Capt. Data Reg. 9
CP10
Input Capt. Data Reg. 10
CP11
Input Capt. Data Reg. 11
CP12
Input Capt. Data Reg. 12
CP13
Input Capt. Data Reg. 13
CP14
Input Capt. Data Reg. 14
CP15
Input Capt. Data Reg. 15
n = 0,1,2,3,4,5
CHAPTER 13 16-BIT I/O TIMER
■ Control Status Register
Figure 13.5-3 Control Status Register (ICS)
Address: bit 15/7 14/6 13/5 12/4 11/3 10/2 9/1 8/0
000054 H
000055 H
000056 H
R/W R/W R/W R/W R/W R/W R/W R/W
ICS01
ICS23
ICS45
Initial value
0 0 0 0 0 0 0 0B
bit9/bit1
bit8/bit0
EGn1
EGn0
0
0
No edge detection (stop)
0
1
Rising edge detection
1
0
Falling edge detection
1
1
Both edges detection
bit11/bit3
bit10/bit2
EGm1
EGm0
0
0
No edge detection (stop)
0
1
Rising edge detection
1
0
Falling edge detection
1
1
Both edges detection
Edge selection bit (input capture n)
Edge selection bit (input capture m)
bit12/bit4
Interrupt Enable Bit (input capture n)
ICEn
0
Disable Interrupt
1
Enable Interrupt
bit13/bit5
Interrupt Enable Bit (input capture m)
ICEm
0
Disable Interrupt
1
Enable Interrupt
bit14/bit6
ICPn
Interrupt request flag bit (input capture n)
Read
Write
0
No valid detected
Clear this bit
1
Valid detected
No effect
bit15/bit7
ICPm
R/W
:
Readable and writable
:
Initial value
Interrupt request flag bit (input capture m)
Read
Write
0
No valid detected
Clear this bit
1
Valid detected
No effect
n = 0, 2, 4 m = 1, 3, 5
217
CHAPTER 13 16-BIT I/O TIMER
Table 13.5-2 Input Capture Control Status Register Bits (Upper and Lower)
Bit name
Function
ICPn+1/3:
Interrupt request flag
bit (Input capture
n+1/3)
• This bit is used as interrupt request flag for input capture n and m
• "1" is set to this bit upon detection of a valid edge of an external input pin.
• While the interrupt enable bit (ICEn+1/3) is set, an interrupt can be generated
upon detection of a valid edge.
• Writing "0" will clear this bit.
• Writing "1" has no effect.
• In read-modify-write (RMW) instruction, "1" is always read.
bit14/bit6
ICPn/2:
Interrupt request flag
bit (Input capture n/
2)
• This bit is used as interrupt request flag for input capture n and m
• "1" is set to this bit upon detection of a valid edge of an external input pin.
• While the interrupt enable bit (ICEn/2) is set, an interrupt can be generated upon
detection of a valid edge.
• Writing "0" will clear this bit.
• Writing "1" has no effect.
• In read-modify-write (RMW) instruction, "1" is always read.
bit13/bit5
ICEn+1/3:
Interrupt request
enable bit (Input
capture n+1/3)
• This bit is used to enable input capture interrupt request for input capture n+1/3
• While "1" is written to this bit, an input capture interrupt is generated when the
interrupt flag (ICPn+1/3) is set.
bit12/bit4
ICEn/2:
Interrupt request
enable bit (Input
capture n/2)
• This bit is used to enable input capture interrupt request for input capture n/2
• While "1" is written to this bit, an input capture interrupt is generated when the
interrupt flag (ICPn/2) is set.
bit11/bit10
bit3/bit2
EG[n+1]1, EG[n+1]0 /
EG31, EG30
• These bits are used to specify the valid edge polarity of an external input for
input capture n+1/3
• These bits are also used to enable input capture operation
bit9/bit8
bit1/bit0
EGn1, EGn0 / EG21,
EG20
• These bits are used to specify the valid edge polarity of an external input for
input capture n/2
• These bits are also used to enable input capture operation
bit15/bit7
n = 0, 4
218
CHAPTER 13 16-BIT I/O TIMER
■ Input Capture Edge Register (ICE01, ICE23, ICE45)
Figure 13.5-4 Input Capture Edge Register (ICE)
Address: bit 15/7 14/6 13/5 12/4 11/3 10/2 9/1 8/0
0035C9 H
0035CAH
0035CBH
-
-
-
-
-
-
-
-
-
-
Initial value
X X X X X 0 X XB *
* ICE01 and ICE45 ("X" otherwise)
R/W R
R
bit8/bit0
IEIn
Valid edge indication bit (input capture n)
0
Falling edge detected
1
Rising edge detected
bit9/bit1
IEIm
Valid edge indication bit (input capture m)
0
Falling edge detected
1
Rising edge detected
R/W
:
Readable and writable
R
:
Read only bit
-
:
Undefined
0
External Input Capture connection
:
Initial value
1
UART3 to Input Capture connection
bit10
(Only Input capture 1 and 5)
IUCE
Input Capture to UART3 connection enable
n = 0, 2, 4
m = 1, 3, 5
219
CHAPTER 13 16-BIT I/O TIMER
Table 13.5-3 Input Capture Edge Register Bits (Upper and Lower)
Bit name
bit15 to bit11,
bit7 to bit3
bit10
bit2
bit9, bit1
bit8, bit0
n = 0, 2, 4
220
Undefined
Function
−
IUCE1/IUCE5:
Input Capture to
UART3
connection enable
• This bit selects the capture source for Input Capture Unit 1 and 5, and is used by
UART3-LIN-Operation
• Writing "0": The capture source is external.
• Writing "1": The capture source is UART3.
MB90V390HA/
MB90V390HB:
IUCE3:
Input Capture to
UART2
connection enable
The IUCE3 bit exists only for MB90V390HA/MB90V390HB.
• This bit selects the capture source for Input Capture Unit 3, and is used by
UART2-LIN-Operation
• Writing "0": The capture source is external.
• Writing "1": The capture source is UART2.
MB90394HA,
MB90F394H(A):
Undefined
For MB90394HA, MB90F394H(A), this bit is undefined.
IEIm:
Valid edge
indication bit
• This bit is a valid edge indication bit for capture register IPCP1, IPCP3 and
IPCP5, to indicate that a rising or falling edge is detected
• "0": falling edge detected.
• "1": rising edge detected.
• This bit is read only.
Note:
The read value is meaningless, if EGm1, EGm0 = 00B.
IEIn:
Valid edge
indication bit
• This bit is a valid edge indication bit for capture register IPCP0, IPCP2 and
IPCP4, to indicate that a rising of falling edge is detected
• "0": falling edge detected.
• "1": rising edge detected.
• This bit is read only.
Note:
The read value is meaningless, if EGn1, EGn0 = 00B.
m = 1, 3, 5
CHAPTER 13 16-BIT I/O TIMER
13.5.2
16-bit Input Capture Operation
In 16-bit input capture operation, an interrupt can be generated upon detection of at the
specified edge, fetching the 16-bit free-run timer value and writing it to the capture
register.
■ Sample of Input Capture Fetch Timing
•
Capture 0: Rising edge
•
Capture 1: Falling edge
•
Capture example: Both edges
Figure 13.5-5 Sample of Input Capture Fetch Timing
Counter value
FFFF H
BFFF H
7FFF H
3FFF H
0000 H
Time
Reset
IN0
IN1
IN example
Capture 0
Capture 1
Capture
example
Undefined
3FFFH
Undefined
Undefined
7FFFH
BFFFH
3FFFH
Capture 0
interrupt
Capture 1
interrupt
Capture
interrupt
221
CHAPTER 13 16-BIT I/O TIMER
■ Input Capture Input Timing
● Capture timing for input signals
Figure 13.5-6 Capture Timing for Input Signals
φ
Counter value
Input capture
input
N
N+1
Valid edge
Capture signal
Capture register
Interrupt
222
N+1
CHAPTER 14
16-BIT RELOAD TIMER
(WITH EVENT COUNT
FUNCTION)
This chapter explains the functions and operations of
the 16-bit reload timer (with the event count function).
14.1 Outline of 16-Bit Reload Timer (with Event Count Function)
14.2 16-Bit Reload Timer (with Event Count Function)
14.3 Internal Clock and External Clock Operations of 16-bit Reload
Timer
14.4 Underflow Operation of 16-bit Reload Timer
14.5 Output Pin Functions of 16-bit Reload Timer
14.6 Counter Operation State
223
CHAPTER 14 16-BIT RELOAD TIMER (WITH EVENT COUNT FUNCTION)
14.1
Outline of 16-Bit Reload Timer (with Event Count Function)
The 16-bit reload timer consists of a 16-bit down-counter, a 16-bit reload register, one
input pin (TIN) and one output pin (TOT), and a control register. The input clock can be
selected from one external clock and three types of internal clock.
■ Outline of 16-bit Reload Timer (with Event Count Function)
The output pin (TOT) outputs a toggle output waveform in reload mode and outputs a square waveform
indicating counting in one-shot mode. The input pin (TIN) is used for event input in event count mode, and
can be used for trigger input or gate input in internal clock mode.
The MB90390 Series has two 16-bit reload timers.
■ Intelligent I/O Service (EI2OS) Function and Interrupts
The timer includes a circuit that supports EI2OS. The timer can activate EI2OS when an underflow occurs.
EI2OS can be used with both timers on this product. However, as both timers (ch.0 and ch.1) are connected
to the same interrupt control register (ICRx) in the interrupt controller, ch.0 and ch.1 cannot be assigned to
different EI2OS services. Also, as the two timers have different interrupt vectors, they can be assigned to
two different interrupt services. However, as ch.0 and ch.1 share an interrupt control register as described
above, the same interrupt level applies to both channels.
224
CHAPTER 14 16-BIT RELOAD TIMER (WITH EVENT COUNT FUNCTION)
■ Block Diagram of 16-bit Reload Timer
Figure 14.1-1 shows a block diagram of the 16-bit reload timer.
Figure 14.1-1 Block Diagram of 16-bit Reload Timer
16
16-bit reload register
8
Reload
RELD
UF
16-bit down-counter
OUTE
16
OUTL
F2 M C - 16 L X B U S
2
OUT
CTL.
GATE
INTE
IRQ
UF
CSL1
Clock selector
CNTE
CSL0
TRG
Clear
EI2OS CLR
Re-trigger
2
EXCK
φ
2
1
φ
2
3
φ
5
2
Port (TIN)
IN CTL
3
Prescaler
clear
Output enable
Port (TOT)
MOD2
MOD1
Peripheral clock
UART baud rate (ch.0)
A/D converter (ch.1)
MOD0
3
225
CHAPTER 14 16-BIT RELOAD TIMER (WITH EVENT COUNT FUNCTION)
14.2
16-Bit Reload Timer (with Event Count Function)
The 16-bit reload timer has the following two types of registers:
• Timer control register (TMCSR)
• 16-bit timer register (TMR)/16-bit reload register (TMRLR)
■ 16-bit Reload Timer Register
Address: bit 15
000051 H
000053 H
-
Address: bit 7
000050 H
MOD0
000052 H
14
13
12
11
-
-
-
CSL1 CSL0 MOD2 MOD1
-
-
-
R/W R/W R/W R/W
6
5
4
3
OUTE OUTL RELD I NTE
10
2
UF
9
8
1
0
CNTE TRG
TMCSR0/TMCSR1 (upper)
Initial value
XXXX0000
B
TMCSR0/TMCSR1 (lower)
Initial value
0 0 0 0 0 0 0 0B
R/W R/W R/W R/W R/W R/W R/W R/W
Address: bit 15
003541 H
003543 H
14
13
12
11
10
9
8
TMR/TMRLR0/TMRLR1 (upper)
Initial value
XXXXXXXX
B
R/W R/W R/W R/W R/W R/W R/W R/W
Address: bit
003540 H
003542 H
7
6
5
4
3
2
1
0
Initial value
XXXXXXXXB
R/W R/W R/W R/W R/W R/W R/W R/W
226
R/W
:
Readable and writable
X
:
Undefined value
-
:
Undefined
TMR/TMRLR0/TMRLR1 (lower)
CHAPTER 14 16-BIT RELOAD TIMER (WITH EVENT COUNT FUNCTION)
14.2.1
Timer Control Status Register (TMCSR)
Controls the operation mode and interrupts for the 16-bit timer. Only modify bits other
than UF, CNTE, and TRG when CNTE = 0.
■ Register Layout of Timer Control Register (TMCSR)
Address: bit 15
000051 H
000053 H
14
13
12
-
-
-
CSL1 CSL0 MOD2 MOD1
-
-
-
R/W R/W R/W R/W
5
4
-
Address: bit 7 6
000050 H
MOD0 OUTE
000052 H
11
3
OUTL RELD I NTE
10
2
UF
9
1
TMCSR0/TMCSR1 (upper)
8
Initial value
XXXX0000
B
TMCSR0/TMCSR1 (lower)
0
Initial value
0 0 0 0 0 0 0 0B
CNTE TRG
R/W R/W R/W R/W R/W R/W R/W R/W
R/W
:
Readable and writable
X
:
Undefined value
-
:
Undefined
■ Register Contents of Timer Control Register (TMCSR)
[bit11, bit10] CSL1, CSL0 (Clock select 1, 0)
The count clock select bits. Table 14.2-1 lists the clock sources for CSL bit settings.
Table 14.2-1 Clock Sources for CSL Bit Settings
CSL1
CSL0
Clock Source (Machine cycle φ = 16 MHz)
0
0
φ/21 (0.125 μs)
0
1
φ/23 (0.5 μs)
1
0
φ/25 (2.0 μs)
1
1
External event count mode
227
CHAPTER 14 16-BIT RELOAD TIMER (WITH EVENT COUNT FUNCTION)
[bit9, bit8, bit7] MOD2, MOD1, MOD0
These bits set the operation mode and I/O pin functions.
The MOD2 bit selects the I/O functions. When MOD2 = 0, the input pin functions as a trigger input. In
this case, the reload register contents is loaded to the counter when an active edge is input to the input
pin and count operation proceeds. When MOD2 = 1, the timer operates in gate counter mode and the
input pin functions as a gate input. In this mode, the counter only counts while an active level is input to
the input pin.
The MOD1 and MOD0 bits set the pin functions for each mode. Table 14.2-2 and Table 14.2-3 list the
MOD2, MOD1 and MOD0 bit settings.
Table 14.2-2 MOD2, MOD1, MOD0 Bit Settings (1)
MOD2
MOD1
MOD0
Input Pin Function
Active Edge or Level
0
0
0
Trigger disabled
-
0
0
1
Trigger input
Rising edge
0
1
0
Falling edge
0
1
1
Both edges
1
x
0
1
x
1
Gate input
"L" level
"H" level
Internal clock mode (CSL0, CSL1 = 00B, 01B, or 10B)
Table 14.2-3 MOD2, MOD1, MOD0 Bit Settings (2)
MOD2
x
228
MOD1
MOD0
Input Pin Function
Active Edge or Level
0
0
-
-
0
1
Trigger input
Rising edge
1
0
Falling edge
1
1
Both edges
•
Event counter mode (CSL0,CSL1 = 11B)
•
Bits marked as x in the table can be set to any value.
CHAPTER 14 16-BIT RELOAD TIMER (WITH EVENT COUNT FUNCTION)
[bit6] OUTE
Output enable bit. The TOT pin functions as a general-purpose port when this bit is "0" and as the timer
output pin when this bit is "1". In reload mode, the output waveform toggles. In one-shot mode, TOT
outputs a square waveform that indicates that counting is in progress.
[bit5] OUTL
This bit sets the output level for the TOT pin.
Table 14.2-4 OUTE, RELD, and OUTL Settings
OUTE
RELD
OUTL
Output Waveform
0
x
x
General-purpose port
1
0
0
Output an "H" level square waveform during counting.
1
0
1
Output an "L" level square waveform during counting.
1
1
0
Toggle output. Starts with "L" level output.
1
1
1
Toggle output. Starts with "H" level output.
[bit4] RELD (Reload)
This bit enables reload operations. When RELD is "1", the timer operates in reload mode. In this mode,
the timer loads the reload register contents into the counter and continues counting whenever an
underflow occurs (when the counter value changes from "0000H" to "FFFFH"). When RELD is "0", the
timer operates in one-shot mode. In this mode, the count operation stops when an underflow occurs due
to the counter value changing from "0000H" to "FFFFH".
[bit3] INTE (Interrupt enable)
Timer interrupt request enable bit. When INTE is "1", an interrupt request is generated when the UF bit
changes to "1". When INTE is "0", no interrupt request is generated, even when the UF bit changes to
"1".
[bit2] UF (Underflow)
Timer interrupt request flag. UF is set to "1" when an underflow occurs (when the counter value
changes from "0000H" to "FFFFH"). Cleared by writing "0" or by the intelligent I/O service. Writing
"1" to this bit has no meaning. Read as "1" by read-modify-write (RMW) instructions.
[bit1] CNTE (Count enable)
Timer count enable bit. Writing "1" to CNTE sets the timer to wait for a trigger. Writing "0" stops count
operation.
[bit0] TRG (Trigger)
Software trigger bit. Writing "1" to TRG applies a software trigger, causing the timer to load the reload
register contents to the counter and start counting. Writing "0" has no meaning. Reading always returns
"0". Applying a trigger using this register is only valid when CNTE = 1. Writing "1" has no effect if
CNTE = 0.
229
CHAPTER 14 16-BIT RELOAD TIMER (WITH EVENT COUNT FUNCTION)
14.2.2
Register Layout of 16-bit Timer Register (TMR)/16-bit
Reload Register (TMRLR)
• TMR contents (for reading)
Reading this register reads the count value of the 16-bit timer. The initial value is
undefined. Always read this register using the word access instructions.
• TMRLR contents (for writing)
The 16-bit reload register holds the initial count value. The initial value is undefined.
Always write to this register using the word access instructions.
■ Register Layout of 16-bit Timer Register (TMR)/16-bit Reload Register (TMRLR)
Address: bit 15
003541 H
003543 H
14
13
12
11
10
9
8
TMR/TMRLR0/TMRLR1 (upper)
Initial value
XXXXXXX
X
B
R/W R/W R/W R/W R/W R/W R/W R/W
Address: bit
003540 H
003542 H
7
6
5
4
3
2
1
0
Initial value
XXXXXXX
R/W R/W R/W R/W R/W R/W R/W R/W
230
R/W
:
Readable and writable
X
:
Undefined value
TMR/TMRLR0/TMRLR1 (lower)
XB
CHAPTER 14 16-BIT RELOAD TIMER (WITH EVENT COUNT FUNCTION)
14.3
Internal Clock and External Clock Operations of 16-bit
Reload Timer
The machine clock divided by 21, 23, or 25 can be selected as the clock sources for
operating the timer from an internal divide clock. The external input pin can be selected
as either a trigger input or gate input by a register setting.
If an external clock is selected, the TIN pin functions as an external event input pin to
count the number of valid edges set in the register.
■ Internal Clock Operation of 16-bit Reload Timer
Writing "1" to both the CNTE and TRG bits in the control register enables and starts counting at one time.
Using the TRG bit as a trigger input is always available when the timer is enabled (CNTE = 1), regardless
of the operation mode.
Figure 14.3-1 shows the activation and operation of 16-bit reload timer counter. A time period T (T:
machine cycle) is required from the counter start trigger being input until the reload register data is loaded
into counter.
Figure 14.3-1 Activation and Operation of 16-bit Reload Timer Counter
Count clock
Counter
Reload data
-1
-1
-1
Data load
CNTE (bit)
TRG (bit)
T
231
CHAPTER 14 16-BIT RELOAD TIMER (WITH EVENT COUNT FUNCTION)
■ Input Pin Functions of 16-bit Reload Timer (in Internal Clock Mode)
The TIN pin can be used as either a trigger input or a gate input when an internal clock is selected as the
clock source. When used as a trigger input, input of an active edge causes the timer to load the reload
register contents to the counter and then start count operation after clearing the internal prescaler. Input a
pulse width of at least 2T (T is the machine cycle) to TIN.
Figure 14.3-2 shows the trigger input operation of 16-bit reload timer.
Figure 14.3-2 Trigger Input Operation of 16-bit Reload Timer
Count clock
Rising edge detected
TIN
Prescaler clear
Counter
Reload data
0000H
-1
-1
-1
Load
2T to
2.5T
When used as a gate input, the counter only counts while the active level specified by the MOD0 bit of the
control register is input to the TIN pin. In this case, the count clock continues to operate unless stopped.
The software trigger can be used in gate mode, regardless of the gate level. Input a pulse width of at least
2T (T is the machine cycle) to the TIN pin. Figure 14.3-3 shows the gate input operation of 16-bit reload
timer.
Figure 14.3-3 Gate Input Operation of 16-bit Reload Timer
Count clock
TIN
Counter
When MOD0 = 1 (Count when "H" is input)
-1
-1
-1
■ External Event Counter
The TIN pin functions as an external event input pin when an external clock is selected. The counter counts
on the active edge specified in the register. Input a pulse width of at least 4T (T is the machine cycle) to the
TIN pin.
232
CHAPTER 14 16-BIT RELOAD TIMER (WITH EVENT COUNT FUNCTION)
14.4
Underflow Operation of 16-bit Reload Timer
An underflow is defined for this timer as the time when the counter value changes from
"0000H" to "FFFFH". Therefore, an underflow occurs after (reload register setting + 1)
counts.
■ Underflow Operation of 16-bit Reload Timer
If the RELD bit in the control register is "1" when the underflow occurs, the contents of the reload register
is loaded into the counter and counting continues. When RELD is "0", counting stops with the counter at
"FFFFH".
The UF bit in the control register is set when the underflow occurs. If the INTE bit is "1" at this time, an
interrupt request is generated.
Figure 14.4-1 shows the underflow operation of 16-bit reload timer.
Figure 14.4-1 Underflow Operation of 16-bit Reload Timer
Count clock
Counter
0000H
Reload data
-1
-1
-1
Data load
Underflow set
[RELD=1]
Count clock
Counter
0000H
FFFFH
Underflow set
[RELD=0]
233
CHAPTER 14 16-BIT RELOAD TIMER (WITH EVENT COUNT FUNCTION)
14.5
Output Pin Functions of 16-bit Reload Timer
In reload mode, the TOT pin performs toggle output (inverts at each underflow). In oneshot mode, the TOT pin functions as a pulse output that shows a particular level while
the count is in progress.
■ Output Pin Functions of 16-bit Reload Timer
The OUTL bit of the control register sets the output polarity. When OUTL = 0, the initial value for toggle
output is "0" and the one-shot pulse output is "1" while the count is in progress. The output waveforms are
opposite when OUTL = 1.
Figure 14.5-1 and Figure 14.5-2 show the output pin function of 16-bit reload timer (1).
Figure 14.5-1 Output Pin Function of 16-bit Reload Timer (1)
Count start
Underflow
Level is opposite when
OUTL = 1
TOT
General-purpose port
OUTE
CNTE
Trigger
[RELD=1,OUTL=0]
Figure 14.5-2 Output Pin Function of 16-bit Reload Timer (2)
Underflow
TOT
Level is opposite
when OUTL = 1
General-purpose port
OUTE
CNTE
Trigger
Waiting for a trigger
[RELD=1,OUTL=0]
234
CHAPTER 14 16-BIT RELOAD TIMER (WITH EVENT COUNT FUNCTION)
14.6
Counter Operation State
The counter state is determined by the CNTE bit in the control register and the internal
WAIT signal. Available states are: CNTE = 0 and WAIT = 1 (STOP state), CNTE = 1 and
WAIT = 1 (WAIT state for trigger), and CNTE = 1 and WAIT = 0 (RUN state).
■ Counter Operation State
Figure 14.6-1 shows the counter state transitions.
Figure 14.6-1 Counter State Transitions
Reset
State transitions by hardware
STOP
CNTE=0, WAIT=1
State transitions by external input
State transitions by register access
TIN pin: Input disabled
TOT pin:
OUTE=0: General-purpose port
OUTE=1: Initial value output
Counter: Retains the value while
counting stopped.
Value undefined after reset.
CNTE=0
CNTE=0
CNTE=1
TRG=1
CNTE=1
TRG=0
WAIT
CNTE=1, WAIT=1
RUN
TIN pin: Only trigger input enabled*
TOT pin:
OUTE=0: General-purpose port
OUTE=1: Initial value output
TIN pin: Functions as TIN pin*
TOT pin:
RELD • UF
Counter: Retains the value while
counting stopped.
Value undefined after reset until
load.
OUTE=0: General-purpose port
OUTE=1: Function as TOT pin
Counter: Running
TRG=1
LOAD
External trigger from TIN
CNTE=1, WAIT=0
TRG=1
CNTE=1, WAIT=0
Load contents of the reload
register to the counter.
RELD
UF
External trigger from TIN
Load complete
*: Before using TIN pin, the corresponding bit of the DDR must be set to "0"
235
CHAPTER 14 16-BIT RELOAD TIMER (WITH EVENT COUNT FUNCTION)
236
CHAPTER 15
WATCH TIMER
This chapter explains the functions and operations of
the Watch Timer.
15.1 Outline of Watch Timer
15.2 Watch Timer Registers
237
CHAPTER 15 WATCH TIMER
15.1
Outline of Watch Timer
The Watch Timer consists of the Timer Control register, Sub-second register, Second/
Minute/Hour registers, 1/2 clock divider, 22-bit prescaler and Second/Minute/Hour
counters. The oscillation frequency of the MCU is assumed to be at 4MHz or 5MHz for
the aimed operation of the Watch Timer. The Watch Timer operates as the real-world
timer and provides the real-world time information.
■ Block Diagram of Watch Timer
Figure 15.1-1 shows a block diagram of the Watch Timer.
Figure 15.1-1 Block Diagram of Watch Timer
Oscillation
clock
OE
22-bit
21bit prescaler
Prescaler
1/2 Clock
Divider
OE
WOT
CO
EN
Sub-second
register
UPDT
Second Counter
CI
EN
CO
LOAD
ST
6bits
INTE0
INT0
INTE1
Minute Counter
Hour Counter
CO
CO
6bits
5bits
Second/Minute/Hour register
INT1
INTE2
INT2
INT3
INT3
IRQ
238
CHAPTER 15 WATCH TIMER
15.2
Watch Timer Registers
The Watch Timer has the following five types of registers:
• Timer control register (WTCR)
• Subsecond register (WTBR)
• Second register (WTSR)
• Minute register (WTMR)
• Hour register (WTHR)
■ Watch Timer Registers
Figure 15.2-1 Watch Timer Registers
Timer control register
Address:
000060 H
000061 H
bit 15
14
13
12
11
10
9
8
INTE3 INT3 INTE2 INT2 INTE1 INT1 INTE0 INT0
R/W
7
6
5
Reserved Reserved Reserved
4
-
3
-
2
1
UPDT OE
0
ST
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
-
-
R/W
R/W
R/W
0
0
0
0
0
0
0
0
0
0
X
X
0
0
0
Initial value: 0
WTCR
Sub-second register (0)
Address:
00354A H
00354B H
bit
Initial value:
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Second register/
Sub-second register (1)
bit 15
Address:
00354C H
00354D H
Initial value:
WTBR1
WTSR
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
-
S5
S4
S3
S2
S1
S0
-
-
D21
D20
D19
D18
D17
D16
-
-
R/W
R/W
R/W
R/W
R/W
R/W
-
-
R/W
R/W
R/W
R/W
R/W
R/W
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Hour Register/
Minute Register
bit
Address:
00354E H
00354F H
15
14
-
-
-
Initial value:
X
X
WTBR0
WTHR
WTMR
13
12
11
10
9
8
7
6
5
4
3
2
1
0
-
H4
H3
H2
H1
H0
-
-
M5
M4
M3
M2
M1
M0
-
-
R/W
R/W
R/W
R/W
R/W
-
-
R/W
R/W
R/W
R/W
R/W
R/W
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Notes:
• Clearing the clock counter affects the watchdog counter and interval interrupts that use clock
timer output.
• To clear the clock timer by writing "0" to the WTR bit in the clock timer control register (WTCR),
set the WTIE bit to "0" and set the clock timer to interrupt inhibited state. Before permitting an
interrupt, clear the interrupt request issued by writing "0" to the WTOF flag.
239
CHAPTER 15 WATCH TIMER
15.2.1
Timer Control Register
The timer control register starts and stops the Watch Timer, controls interrupts, and
sets the external output pins.
■ Timer Control Register (Lower)
Figure 15.2-2 Configuration of the Watch Timer Control Register (Lower)
bit
Address:
000060 H
7
6
5
R/W R/W R/W
4
3
2
1
0
-
-
-
- R/W R/W R/W
WTCR
Initial value
0 0 0 X X 0 00B
bit 0
ST
0
Start bit
reset all counters and prescaler to "0"
1
start operation
bit 1
OE
0
Output enable bit
use corresponding pin as general purpose I/O
1
set WOT to pin (Watch timer output)
bit 2
UPDT
Update bit
0
no effect
1
Update counter with data values
bit 5
Reserved
0
Reserved bit
-
1
-
bit6
Reserved
0
Reserved bit
-
1
-
bit7
Reserved
240
R/W
:
Readable and writable
-
:
Undefined
:
Initial value
0
Reserved bit
-
1
-
CHAPTER 15 WATCH TIMER
Table 15.2-1 Timer Control Register (Lower)
Bit name
bit7 to
bit5
Reserved
bit4,
bit3
Undefined
Function
These are reserved bits. Always write "0" to these bits.
−
bit2
UPDT: Update bit
The UPDT bit is prepared for modifying the Second/Minute/Hour counter values.
To modify the counter values, write the modified data in the Second/Minute/Hour
registers. Then set the UPDT bit to "1". The register values are loaded to the counter
at the next CO signal from the 22-bit prescaler. The UPDT bit is reset by the hardware
when the counter values are updated. However, if the set operation by software and
the reset operation by hardware occur at the same time, the UPDT bit will not be
reset.
Note:
If this bit is set during "59 second", normal up count operation is executed and this
bit is reset to "0" without reflecting the Second/Minute/Hour register values.
Writing "0" to the UPDT bit has no effect and a read-modify-write (RMW)
instruction results in reading "0".
bit1
OE:
Output enable bit
When the OE bit is set to "1", the WOT external pin serves as the output for the
Watch Timer. Otherwise it can be used as a general purpose I/O or for another
peripheral block.
bit0
ST: Start bit
When the ST bit is set to "1", the Watch Timer loads Second/Minute/Hour values
from the registers and starts its operation. When it is reset to "0", all the counters and
the prescalers are reset to "0" and halts.
241
CHAPTER 15 WATCH TIMER
■ Timer Control Register (Upper)
Figure 15.2-3 Configuration of the Timer Control Register (Upper)
bit 15
14
13
12
11
10
9
8
WTCR
Address:
000061 H
Initial value
00000000B
R/W R/W R/W R/W R/W R/W R/W R/W
bit8
INT0
Interrupt request bit 0
write
read
0
clear interrupt
no interrupt request
1
no effect
interrupt request
bit9
INTE0
Interrupt enable bit 0
0
Interrupt disabled
1
Interrupt enabled
bit10
Interrupt request bit 1
INT1
write
read
0
clear interrupt
no interrupt request
1
no effect
interrupt request
bit11
INTE1
Interrupt enable bit 1
0
Interrupt disabled
1
Interrupt enabled
bit 12
Interrupt request bit 2
INT2
write
read
0
clear interrupt
no interrupt request
1
no effect
interrupt request
bit13
INTE2
Interrupt enable bit 2
0
Interrupt disabled
1
Interrupt enabled
bit14
Interrupt request bit 3
INT3
0
1
write
read
clear interrupt
no interrupt request
no effect
interrupt request
bit 15
R/W
242
:
Readable and writable
:
Initial value
INTE3
Interrupt enable bit 3
0
1
Interrupt disabled
Interrupt enabled
CHAPTER 15 WATCH TIMER
Table 15.2-2 Timer Control Register (Upper)
Bit name
bit15, bit13,
bit11, bit9
bit14, bit12,
bit10, bit8
Function
INTE3 to INTE0
INTE3 to INTE0 are the interrupt flags. They are set when the second counter, minute
counter and hour counter overflow respectively. If a INT bit is set while the
corresponding INTE bit is "1", the Watch Timer signals an interrupt. These flags are
intended to signal an interrupt every second/minute/hour/day.
Writing "0" to the INT bits clears the flags and writing "1" does not have any effect.
Any read-modify-write (RMW) instruction performed on the INT bit results reading
"1".
INT3 to INT0
INT3 to INT0 are the interrupt flags. They are set when the second counter, minute
counter and hour counter overflow respectively. If a INT bit is set while the
corresponding INTE bit is "1", the Watch Timer signals an interrupt. These flags are
intended to signal an interrupt every second/minute/hour/day.
Writing "0" to the INT bits clears the flags and writing "1" does not have any effect.
Any read-modify-write (RMW) instruction performed on the INT bit results reading
"1".
243
CHAPTER 15 WATCH TIMER
15.2.2
Sub-second Registers
The sub-second register stores a reload value for the 22-bit prescaler that divides the
oscillation clock. The reload value is usually set so that the 22-bit prescaler will output
exactly within a one-second cycle. This register is not initialized by reset, but 22-bit
prescaler is initialized by reset.
■ Sub-second Register
Figure 15.2-4 Configuration of the Sub-second Register
Sub-second register (0)
Address:
00354A H
00354B H
bit
Initial value:
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
7
6
5
4
3
2
1
0
WTBR0
Sub-second register (1)
Address:
00354C H
bit
Initial value:
R/W
:
Readable and writable
X
:
Undefined value
-
:
Undefined
-
-
D21
D20
D19
D18
D17
D16
-
-
R/W
R/W
R/W
R/W
R/W
R/W
X
X
X
X
X
X
X
WTBR1
X
Table 15.2-3 Sub-second Register
Bit name
bit15 to
bit0
WTBR (0):D15 to D0
bit5 to
bit0
WTBR (1):D21 to D16
244
Function
The Sub-second register stores the reload value for the 22-bit prescaler. This value
is reloaded after the reload counter reaches "0". Note that when modifying all
three bytes, make sure the reload operation will not be performed in between the
write instructions. Otherwise the 22-bit prescaler loads the incorrect value of the
combination of new data and old data bytes. It is generally recommended that the
Sub-Second register are updated while the ST bit is "0". If the sub-second registers
are set to "0", the 22-bit prescaler does not operate at all.
The input clock frequency always equals the oscillation clock frequency and it is
intended to be 4MHz or 5MHz. The reload value of the 22-bit prescaler for 4MHz
operation frequency is typically set to "1E847FH", and for 5MHz operation
frequency: "26259FH".
CHAPTER 15 WATCH TIMER
15.2.3
Second/Minute/Hour Registers
The Second/Minute/Hour registers stores the time information. It is a binary
representation of the second, minute and hour.
Reading these registers simply returns the counter values. These registers are write
accessible however, the written data is loaded in the counters after the UPDT bit is set
to "1". These registers and counter are initialized by reset.
■ Second/Minute/Hour Registers
Figure 15.2-5 Configuration of the Second/Minute/Hour Registers
Second register
Address:
00354D H
bit
Initial value:
Hour Register/
Minute Register
bit
Address:
00354E H
00354F H
Initial value:
WTSR
15
14
13
12
11
10
9
8
-
-
S5
S4
S3
S2
S1
S0
-
-
R/W
R/W
R/W
R/W
R/W
R/W
X
X
X
X
X
X
X
X
15
14
13
12
10
9
8
WTHR
11
WTMR
7
6
5
4
3
2
1
0
-
-
-
H4
H3
H2
H1
H0
-
-
M5
M4
M3
M2
M1
M0
-
-
-
R/W
R/W
R/W
R/W
R/W
-
-
R/W
R/W
R/W
R/W
R/W
R/W
X
X
X
X
X
X
X
X
X
X
X
X
X
X
R/W
:
Readable and writable
X
:
Undefined value
-
:
Undefined
X
X
Notes:
Since there are three byte-registers, make sure the obtained values from the registers are
consistent.
i.e. Obtained value of "1 hour, 59 minute, 59 second" could be "0 hour 59 minute, 59 second" or "1
hour, 0 minute, 0 second" or "2 hour, 0 minute, 0 second".
Also when the operation clock of the MCU is the half of the oscillation clock (When the PLL is
stopped), the read values from these registers may be corrupt. This is due to the synchronization of
the read operation and the count operation. Therefore it is recommended to use a second interrupt
to trigger the read instructions.
245
CHAPTER 15 WATCH TIMER
246
CHAPTER 16
8/16-BIT PPG
This chapter explains the 8/16-bit PPG and explains its
functions.
16.1 Outline of 8/16-bit PPG
16.2 Block Diagram of 8/16-bit PPG
16.3 8/16-bit PPG Registers
16.4 Operations of 8/16-bit PPG
16.5 Selecting a Count Clock for 8/16-bit PPG
16.6 Controlling Pin Output of 8/16-bit PPG Pulses
16.7 8/16-bit PPG Interrupts
16.8 Initial Values of 8/16-bit PPG Hardware
247
CHAPTER 16 8/16-BIT PPG
16.1
Outline of 8/16-bit PPG
The 8/16-bit Programmable Pulse Generator (PPG) consists of two eight-bit down
counters, four eight-bit reload registers, one 16-bit control register, two external pulse
output signals, and two interrupt outputs. The following functions are implemented:
■ Function of 8/16-bit PPG
● 8-bit PPG output, 2-channel independent operation mode:
Two independent channels of PPG output operation are implemented.
● 16-bit PPG output operation mode:
One channel of 16-bit PPG output operation is implemented.
● 8+8-bit PPG output operation mode:
8-bit PPG output operation is implemented at specified intervals, using channel 0 output as channel 1 clock
input.
● PPG output operation:
Pulse waves are output at specified intervals and duty ratio. With an external circuit, this module can be
used as a D/A converter.
The MB90390 Series contains six PPG’s. The following sections only describe the functionality of the
PPG0/PPG1. The remaining PPG’s have the identical function and the register addresses should be found
in the I/O map.
Figure 16.1-1 shows the connection of internal PPG modules and external pins.
248
CHAPTER 16 8/16-BIT PPG
Figure 16.1-1 Relationship between PPG Modules and External Pins
PPG0 / PPG1
PPG2 / PPG3
Internal
Modules
PPG4 / PPG5
PPG6 / PPG7
PPG8 / PPG9
PPGA / PPGB
PPG00
PPG10
PPG01
PPG11
PPG02
PPG12
PPG03
External
Pins
PPG13
PPG04
PPG14
PPG05
PPG15
249
CHAPTER 16 8/16-BIT PPG
16.2
Block Diagram of 8/16-bit PPG
Figure 16.2-1 shows a 8/16-bit PPG ch.0 block diagram. Figure 16.2-2 shows a 8/16-bit
PPG ch.1 block diagram.
■ Block Diagram of 8/16-bit PPG
Figure 16.2-1 8/16-bit PPG ch.0 Block Diagram
PPG00 output enable
PPG00
Peripheral clock 16-division
Peripheral clock 8-division
Peripheral clock 4-division
Peripheral clock 2-division
Peripheral clock
PPG00
Output latch
Invert
Clear
PEN0
In MB90390 series, this IRQ signal merged
with the Channel1 IRQ signal by OR logic.
Count clock
selection
Time-base counter output,
512-division of main clock
"L"/"H" selection
PCNT
(down counter)
S
RQ
IRQ
Reload
ch.1 borrow
"L"/"H" selector
PRLL0
PRLBH0
(Temporary buffer)
PIE0
PRLH0
PUF0
"L" data bus
"H" data bus
PPGC0
(Operation mode control)
250
CHAPTER 16 8/16-BIT PPG
Figure 16.2-2 8/16-bit PPG ch.1 Block Diagram
PPG10 output enable
PPG10
Peripheral clock 16-division
Peripheral clock 8-division
Peripheral clock 4-division
Peripheral clock 2-division
Peripheral clock
PPG10
Output latch
Invert
Clear
PEN1
In MB90390 series, this IRQ signal merged
with the Channel0 IRQ signal by OR logic.
S
RQ
PCNT
(down counter)
ch.0 borrow
Time-base counter output,
512-division of main clock
"L"/"H" selection
IRQ
Reload
"L"/"H" selector
PRLL1
PRLBH1
(Temporary buffer)
PIE1
PRLH1
PUF1
"L" data bus
"H" data bus
PPGC1
(Operation mode control)
251
CHAPTER 16 8/16-BIT PPG
● Details of pins in block diagram
Table 16.2-1 lists the actual pin names and interrupt request numbers of the 8-/16-bit PPG timer.
Table 16.2-1 Pins and Interrupt Request Numbers in Block Diagram
Channel
Output Pin
PPG0
P56/PPG00
PPG1
P50/PPG10
PPG2
P57/PPG01
PPG3
P51/PPG11
PPG4
PB0/PPG02
PPG5
P52/PPG12
PPG6
PB1/PPG03
PPG7
P53/PPG13
PPG8
PB2/PPG04
PPG9
P54/PPG14
PPGA
PB3/PPG05
PPGB
P55/PPG15
Interrupt Request Number
#17 (11H)
#18 (12H)
#19 (13H)
#20 (14H)
#21 (15H)
#22 (16H)
● PPG operation mode control register 0 (PPGC0)
This register enables or disables operation of the 8-/16-bit PPG timer 0, the pin output, and an underflow
interrupt. It also indicates the occurrence of an underflow.
● PPG0/1 count clock select register (PPG01)
This register sets the count clock of the 8-/16-bit PPG timer 0.
● PPG0 reload registers (PRLH0 and PRLL0)
These registers set the High width or Low width of the output pulse. The value set in these registers are
reloaded to the PPG0 down counter (PCNT0) when the 8-/16-bit PPG timer 0 is started.
● PPG0 down counter (PCNT0)
This counter is an 8-bit down counter that alternately reloads the values set in the PPG0 reload registers
(PRLH0 and PRLL0) to decrement. When an underflow occurs, the pin output is inverted. This counter is
concatenated for use as a single-channel 16-bit PPG down counter.
● PPG0 temporary buffer (PRLBH0)
This buffer prevents deviation of the output pulse width caused at writing to the PPG reload registers
(PRLH0 and PRLL0). This buffer stores the PRLH0 values temporarily and enables it in synchronization
with the timing of writing to the PRLL0.
252
CHAPTER 16 8/16-BIT PPG
● Reload register L/H selector
This selector detects the current pin output level to select which register value, Low reload register
(PRLL0) or High reload register (PRLH0), should be reloaded to the PPG0 down counter.
● Count clock selector
This selector selects the count clock to be input to the PPG0 down counter from five frequency-divided
clocks of the machine clock or the frequency-divided clocks of the time-base timer.
● PPG output control circuit
This circuit inverts the pin output level and the output when an underflow occurs.
253
CHAPTER 16 8/16-BIT PPG
16.3
8/16-bit PPG Registers
The 8/16-bit PPG has the following five types of registers:
• PPGC0 (PPGC2, PPGC4, PPGC6, PPGC8, PPGCA) Operation Mode Control Register
• PPGC1 (PPGC3, PPGC5, PPGC7, PPGC9, PPGCB) Operation Mode Control Register
• PPG01 (PPG23, PPG45, PPG67, PPG89, PPGAB) Clock Select Register
• Reload register "H"
• Reload register "L"
■ 8/16-bit PPG Registers
PPGn Operation Mode Control Register
bit
7
Address: ch.0 000038H
ch.2 00003CH
ch.4 000040H
PEN0
ch.6 000044H
ch.8 000048H
(R/W)
ch.A 00004CH
(0)
PPGm Operation Mode Control Register
Address: ch.1 000039H
bit 15
ch.3 00003DH
ch.5 000041H
PEN1
ch.7 000045H
ch.9 000049H
(R/W)
ch.B 00004DH
(0)
PPGnm Clock Select Register
Address: ch.01 00003AH
ch.23 00003EH
ch.45 000042H
ch.67 000046H
ch.89 00004AH
ch.AB 00004EH
Reload register H
Address: ch.0 003501H
ch.1 003503H
ch.2 003505H
ch.3 003507H
ch.4 003509H
ch.5 00350BH
ch.6 00350DH
ch.7 00350FH
ch.8 003511H
ch.9 003513H
ch.A 003515H
ch.B 003517H
Reload register L
Address: ch.0 003500H
ch.1 003502H
ch.2 003504H
ch.3 003506H
ch.4 003508H
ch.5 00350AH
ch.6 00350CH
ch.7 00350EH
ch.8 003510H
ch.9 003512H
ch.A 003514H
ch.B 003516H
254
bit
7
6
5
4
PE00
3
PIE0
2
1
0
Reserved
PUF0
PPGCn
(-)
(X)
14
(R/W) (R/W) (R/W)
(0)
(0)
(0)
(-)
(X)
13
12
11
10
PE10
PIE1
PUF1
MD1
(-)
(X)
(W)
(1)
9
8
MD0 Reserved
PPGCm
(-)
(X)
6
(R/W) (R/W) (R/W) (R/W) (R/W)
(0)
(0)
(0)
(0)
(0)
5
4
3
2
(W)
(1)
1
0
(-)
(X)
(-)
(X)
9
8
PCS2 PCS1 PCS0 PCM2 PCM1 PCM0
PPGnm
(R/W) (R/W)
(0)
(0)
bit
15
14
(R/W) (R/W)
(0)
(0)
13
12
(R/W) (R/W)
(0)
(0)
11
10
PRLHn
PRLHm
(R/W) (R/W) (R/W) (R/W) (R/W)
(X)
(X)
(X)
(X)
(X)
bit
7
6
5
4
3
(R/W) (R/W)
(X)
(X)
2
1
(R/W)
(X)
0
PRLLn
PRLLm
(R/W)
(X)
(R/W) (R/W) (R/W) (R/W)
(X)
(X)
(X)
(X)
(R/W) (R/W)
(X)
(X)
(R/W)
(X)
n = 0, 2, 4, 6, 8, A
m = 1, 3, 5, 7, 9, B
CHAPTER 16 8/16-BIT PPG
16.3.1
PPG0 Operation Mode Control Register (PPGC0)
PPGC0 is a five-bit control register that selects the operation mode of the block,
controls pin outputs, selects count clock, and controls triggers.
■ PPG0 Operation Mode Control Register (PPGC0)
Figure 16.3-1 Configuration of the PPG0 Operation Mode Control Register
PPG0 operation mode control register
7
6
bit
Address:
ch.0, 000038H
PEN0
Read/write
Initial value
(R/W)
(0)
(-)
(X)
5
4
3
2
1
0
PE00
PIE0
PUF0
-
-
Reserved
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(-)
(X)
(-)
(X)
(W)
(1)
PPGC0
bit 0
Other ch.:
ch.2 00003CH
ch.4 000040H
ch.6 000044H
ch.8 000048H
ch.A 00004CH
Reserved
1
Reserved bit
When setting PPGC0, always set this bit to "1".
bit 3
PUF0
PPG counter underflow bit
0
PPG counter underflow is not detected.
1
PPG counter underflow is detected.
bit 4
PIE0
PPG interrupt enable bit
0
Interrupt disabled.
1
Interrupt enabled.
bit 5
PE00
PPG00 pin output enable bit
0
Pulse output disabled (general-purpose port).
1
Pulse output enabled.
bit 7
PEN0
R/W
:
Readable and writable
X
:
Undefined value
-
:
Undefined
:
Initial value
Operation enable bit
0
Stop ( "L" level output maintained).
1
PPG operation enabled.
255
CHAPTER 16 8/16-BIT PPG
Table 16.3-1 Bit Function Description of the PPG0 Operation Mode Control Register
Bit name
Function
bit7
PEN0:
Operation enable bit
When set to "1", this bit enables the counter operation of the PPG. When operation is
disabled but output is enabled (bit5), a "L" level is maintained at the output.
bit5
PE00:
PPG00 pin output
enable bit
When set to "1", this bit enables the pulse output. For MB90390 Series, the pulse signal is
output to the "PPG00" external pin. When disabled, the pin can be used as generalpurpose port.
bit4
PIE0:
PPG interrupt enable
bit
While this bit is "1", an interrupt request is issued as soon as PUF0 is set to "1". No
interrupt request is issued while this bit is set to "0".
bit3
PUF0:
PPG counter
underflow bit
In 8-bit PPG 2-channel mode or 8-bit prescaler + 8-bit PPG mode, this bit is set to "1"
when an underflow occurs as a result of the ch.0 counter value becoming from "00H" to
"FFH". In 16-bit PPG mode, this bit is set to "1" when an underflow occurs as a result of
the Channel 0 and 1 counter value changing from "0000H" to "FFFFH". To set this bit to
"0", write "0". Writing "1" to this bit has not effect. Upon a read operation during a readmodify-write (RMW) instruction, "1" is read.
bit0
Reserved bit.
This is a reserved bit. When setting PPGC0, always set this bit to "1".
256
CHAPTER 16 8/16-BIT PPG
16.3.2
PPG1 Operation Mode Control Register (PPGC1)
PPGC1 is a seven-bit control register that selects the operation mode of the block,
controls pin outputs, selects count clock, and controls triggers.
■ PPG1 Operation Mode Control Register (PPGC1)
Figure 16.3-2 Configuration of the PPG1 Operation Mode Control Register
PPG1 operation mode
bit
control register
Address:
ch.1 000039H
Read/write
Initial value
15
14
13
PEN1
-
PE10
PIE1
(R/W)
(0)
(-)
(X)
(R/W)
(0)
(R/W)
(0)
Other ch.:
ch.3 00003DH
ch.5 000041H
ch.7 000045H
ch.9 000049H
ch.B 00004DH
12
11
10
9
PUF1
MD1
MD0
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
8
Reserved
PPGC1
(W)
(1)
bit 8
Reserved
1
Reserved bit
When setting PPGC1, always set this bit to "1".
bit 10
bit 9
MD1
MD0
0
0
PPG count mode
8-bit PPG 2ch independent mode
0
1
8-bit prescaler + 8-bit PPG 1ch mode
1
0
Reserved
1
1
16-bit PPG 1ch mode
bit 11
PUF1
PPG counter underflow bit
0
PPG counter underflow is not detected.
1
PPG counter underflow is detected.
bit 12
PIE1
PPG interrupt enable bit
0
Interr upt disabled.
1
Interrupt enabled.
bit 13
PE10
PPG10 pin output enable bit
0
Pulse output disabled (general-purpose port).
1
Pulse output enabled.
bit 15
PEN1
Operation enable bit
R/W
:
Readable and writable
0
Stop ( retains the "L" level output).
X
:
Undefined value
1
PPG operation enabled.
-
:
Undefined
:
Initial value
257
CHAPTER 16 8/16-BIT PPG
Table 16.3-2 Bit Function Description of the PPG1 Operation Mode Control Register
Bit name
bit15
PEN1:
Operation enable bit
When set to "1", this bit enables the counter operation of the PPG. When operation
is disabled but output is enabled (bit13), a "L" level is maintained at the output.
bit13
PE10:
PPG10 pin output
enable bit
When set to "1", this bit enables the pulse output. For MB90390 Series, the pulse
signal is output to the "PPG10" external pin. When disabled, the pin can be used as
general-purpose port.
bit12
PIE1:
PPG interrupt enable
bit
While this bit is "1", an interrupt request is issued as soon as PUF1 is set to "1". No
interrupt request is issued while this bit is set to "0".
PUF1:
PPG counter
underflow bit
In 8-bit PPG 2-channel mode or 8-bit prescaler + 8-bit PPG mode, this bit is set to
"1" when an underflow occurs as a result of the ch.0 counter value becoming from
"00H" to "FFH". In 16-bit PPG mode, this bit is set to "1" when an underflow occurs
as a result of the Channel 0 and 1 counter value changing from "0000H" to "FFFFH".
To set this bit to "0", write "0". Writing "1" to this bit has not effect. Upon a read
operation during a read-modify-write instruction, "1" is read.
MD1, MD0:
PPG count mode
These bits select the PPG timer operation mode as described in Figure 16.3-2. Do
not set "10B" in these bits.
To write "01B" to these bits, ensure that "01B" is not written to the PEN0 bit of
PPGC0 or PEN1 bit of PPGC1. Write "11B" or "00B" in both the PEN0 and PEN1
bits simultaneously.
To write "11B" to these bits, update PPGC0 and PPGC1 by word transfer and write
"11B" or "00B" to both the PEN0 and PEN1 bits simultaneously.
Reserved bit.
This is a reserved bit. When setting PPGC1, always write "1" to this bit.
bit11
bit10, bit9
bit8
258
Function
CHAPTER 16 8/16-BIT PPG
16.3.3
PPG0/1 Clock Select Register (PPG01)
The PPG0/1 Clock Select Register (PPG01) is an 8-bit control register that controls the
counter clock of the 8/16-bit PPG.
■ PPG0/1 Clock Select Register (PPG01)
Figure 16.3-3 Configuration of the PPG0/1 Clock Select Register (PPG01)
PPG0/1 Clock Select Registers
Address:
bit
ch.01 00003AH
Other ch.:
ch.23 00003EH
ch.45 000042H
ch.67 000046H
ch.89 00004AH
ch.AB 00004EH
7
6
5
4
3
2
1
0
PCS2 PCS1 PCS0 PCM2 PCM1 PCM0
-
-
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
(-)
(-)
PPG01
Initial value
0 0 0 0 0 0 X XB
bit 4
bit 3
bit 2
PCM2
PCM1
PCM0
0
0
0
Peripheral Clock
0
0
1
Peripheral Clock/2
0
1
0
Peripheral Clock/4
0
1
1
Peripheral Clock/8
1
0
0
Peripheral Clock/16
1
1
1
Clock input from time-base timer
bit 7
bit 6
bit 5
PCS2
PCS1
PCS0
0
0
0
Peripheral Clock
0
0
1
Peripheral Clock/2
0
1
0
Peripheral Clock/4
Count clock selection bit (ch.0)
Count clock selection bit (ch.1)
R/W
:
Readable and writable
0
1
1
Peripheral Clock/8
X
:
Undefined value
1
0
0
Peripheral Clock/16
-
:
Undefined
1
1
1
Clock input from time-base timer
:
Initial value
259
CHAPTER 16 8/16-BIT PPG
Table 16.3-3 Bit Function Description of the Clock Select Register (PPG01)
Bit name
Function
These bits select the operation clock for the down counter of Channel 1 as described
below.
Note:
In 8-bit prescaler + 8-bit PPG mode or in 16-bit PPG mode, ch.1 PPG operates in
response to a counter clock from ch.0. Therefore, the setting in these bits has no
effect.
bit7 to bit5
PCS2 to PCS0:
Count clock selection
bit
PCS2
PCS1
PCS0
Operation mode
0
0
0
Peripheral Clock (62.5 ns machine clock, 16 MHz)
0
0
1
Peripheral Clock/2 (125 ns machine clock, 16 MHz)
0
1
0
Peripheral Clock/4 (250 ns machine clock, 16 MHz)
0
1
1
Peripheral Clock/8 (500 ns machine clock, 16 MHz)
1
0
0
Peripheral Clock/16 (1 μs machine clock, 16 MHz)
1
1
1
Clock input from the time-base timer
(128 μs, 4 MHz source oscillation)
These bits select the operation clock for the down counter of Channel 0 as described
below.
bit4 to bit2
260
PCM2 to PCM0:
Count clock selection
bit
PCM2
PCM1
PCM0
Operation mode
0
0
0
Peripheral Clock (62.5 ns machine clock, 16 MHz)
0
0
1
Peripheral Clock/2 (125 ns machine clock, 16 MHz)
0
1
0
Peripheral Clock/4 (250 ns machine clock, 16 MHz)
0
1
1
Peripheral Clock/8 (500 ns machine clock, 16 MHz)
1
0
0
Peripheral Clock/16 (1 μs machine clock, 16 MHz)
1
1
1
Clock input from the time-base timer
(128 μs, 4 MHz source oscillation)
CHAPTER 16 8/16-BIT PPG
16.3.4
Reload Register (PRLL/PRLH)
The reload registers (PRLL and PRLH) are 8-bit registers that store reload values for the
PCNT down counters. The PRLL and PRLH registers are readable and writable.
■ Reload Register (PRLL/PRLH)
Reload register H
Address: ch.0 003501H
ch.1 003503H
ch.2 003505H
ch.3 003507H
ch.4 003509H
ch.5 00350BH
ch.6 00350DH
ch.7 00350F H
ch.8 003511 H
ch.9 003513 H
ch.A 003515H
ch.B 003517H
Reload register L
Address: ch.0 003500 H
ch.1 003502 H
ch.2 003504 H
ch.3 003506 H
ch.4 003508 H
ch.5 00350A H
ch.6 00350C H
ch.7 00350E H
ch.8 003510 H
ch.9 003512 H
ch.A 003514 H
ch.B 003516 H
bit
15
14
13
12
11
10
9
8
PRLHn
(R/W) (R/W) (R/W) (R/W) (R/W)
(X)
(X)
(X)
(X)
(X)
bit
7
6
5
4
3
(R/W) (R/W)
(X)
(X)
2
1
(R/W)
(X)
0
PRLLn
(R/W)
(X)
(R/W) (R/W) (R/W) (R/W)
(X)
(X)
(X)
(X)
(R/W) (R/W)
(X)
(X)
(R/W)
(X)
n = 0, 1, ... , 9, A, B
Table 16.3-4 Register Function of the Reload Registers
Register name
Function
PRLLn
Holds the "L" side reload value.
PRLHn
Holds the "H" side reload value.
Note:
In 8-bit prescaler + 8-bit PPG mode, different values in PRLL and PRLH of Channel 0 may cause the
PPG waveform of ch.1 to vary in each cycle. Write the same value to PRLL and PRLH of ch.0.
261
CHAPTER 16 8/16-BIT PPG
16.4
Operations of 8/16-bit PPG
One 8/16-bit PPG consists of two channels of 8-bit PPG units. These two channels can
be used in three modes: independent two-channel mode, 8-bit prescaler + 8-bit PPG
mode, and single-channel 16-bit PPG mode.
■ Operations of 8/16-bit PPG
Each of the 8-bit PPG units has two eight-bit reload registers. One reload register is for the "L" pulse width
(PRLL) and the other is for the "H" pulse width (PRLH). The values stored in these registers are reloaded
into the 8-bit down counter (PCNT), from the PRLL and PRLH in turn. The pin output value is inverted
upon a reload caused by counter borrow. This operation results in the pulses of the specified "L" pulse
width and "H" pulse width.
Table 16.4-1 lists the relationship between the reload operation and pulse outputs.
Table 16.4-1 Reload Operation and Pulse Output
Reload operation
Pin output change
PRLH → PCNT
PPG0/PPG1 [0 → 1]
Rise
PRLL → PCNT
PPG0/PPG1 [1 → 0]
Fall
When "1" is set in bit4 (PIE0) of PPGC0 or in bit12 (PIE1) of PPGC1, an interrupt request is output upon a
borrow from "00H" to "FFH" (from "0000H" to "FFFFH" in 16-bit PPG mode) of each counter.
■ Operation Modes of 8/16-bit PPG
This block can be used in three modes: independent two-channel mode, 8-bit prescaler + 8-bit PPG mode,
and single-channel 16-bit PPG mode.
● Independent two-channel mode
The two channels of 8-bit PPG units operate independently. The PPG00 pin is connected to the ch.0 PPG
output, while the PPG10 pin is connected to the ch.1 PPG output.
● 8-bit prescaler + 8-bit PPG mode
Ch.0 is used as an 8-bit prescaler while the count in ch.1 is based on borrow outputs from ch.0. Thus, 8-bit
PPG waveforms can be output with arbitrary length of cycle time. The PPG00 pin is connected to the ch.0
prescaler output, while the PPG10 pin is connected to the ch.1 PPG output.
● 16-bit PPG 1ch mode
Ch.0 and ch.1 are connected and used as a single 16-bit PPG. The PPG00 and PPG10 pins are connected to
the 16-bit PPG output.
262
CHAPTER 16 8/16-BIT PPG
■ 8/16-bit PPG Output Operation
In this block, the ch.0 PPG is activated to start counting when "1" is written to bit7 (PEN0) of the PPGC0
(PWM operation mode control) register. Similarly, the ch.1 PPG is activated to start counting when "1" is
written to bit15 (PEN1) of the PPGC1 register. Once the operation has started, counting is terminated by
writing "0" to bit7 (PEN0) of PPGC0 or in bit15 (PEN1) of PPGC1. Once the counting is terminated, the
output is maintained at the L level.
In 8-bit prescaler + 8-bit PPG mode, do not set ch.1 to be in operation while ch.0 operation is stopped.
In 16-bit PPG mode, ensure that bit7 (PEN0) of PPGC0 register and bit15 (PEN1) of PPGC1 register are
started or stopped simultaneously. The figure below is a diagram of PPG output operation. During PPG
operation, a pulse wave is continuously output at a frequency and duty ratio (the ratio of the "H" level
period of the pulse wave to the "L" level period). PPG continues operation until stop is specified explicitly.
Figure 16.4-1 PPG Output Operation, Output Waveform
PEN
Starts operation based on PEN (from "L" side).
Output pin
PPG
T
(L+1)
T
L : PRLL value
H : PRLH value
T : Input from peripheral clock (φ, φ/4, φ/16)
or time base counter (depending on th e
clock selection by PPG01)
(H+1)
(Start)
■ Relationship between 8/16-bit PPG Reload Value and Pulse Width
The width of the output pulse is determined by adding 1 to the reload register value and multiplying it by
the count clock cycle. Note that when the reload register value is "00H" during 8-bit PPG operation or
"0000H" during 16-bit PPG operation, the pulse width is equivalent to one count clock cycle. In addition,
note that when the reload register value is "FFH" during 8-PPG operation, the pulse width is equivalent to
256 count clock cycles. When the reload register value is "FFFFH" during 16-bit PPG operation, the pulse
width is equivalent to 65536 count clock cycles.
Pl =T
Ph=T
(L+1)
(H+1)
L
: PRLL value
H
T
: PRLH value
: Input clock cycle
Ph : "H" pulse width
Pl : "L" pulse width
263
CHAPTER 16 8/16-BIT PPG
16.5
Selecting a Count Clock for 8/16-bit PPG
The count clock used for the operation is supplied from the peripheral clock or the timebase timer. The count clock can be selected from six choices.
■ Selecting a Count Clock for 8/16-bit PPG
Select ch.0 clock at bit4 to bit2 (PCM2 to PCM0) of the PPG01 register, and ch.1 clock at bit7 to bit5
(PCS2 to PCS0) of the PPG01 register.
The clock is selected from a peripheral clock 1/16 to 1 times higher than a machine clock or an input clock
from the time-base timer. In 8-bit prescaler + 8-bit PPG mode or 16-bit PPG mode, however, the setting in
the PCS2 to PCS0 has no effect.
When the time-base timer input is used, the first count cycle after a trigger or a stop may be shifted. The
cycle may also be shifted if the time-base counter is cleared during operation of this module.
Note:
In 8-bit prescaler + 8-bit PPG mode, if ch.1 is activated while ch.0 is in operation and ch.1 is
stopped, the first count cycle may be shifted.
• ch.0: operation mode
• ch.1: stop mode
264
CHAPTER 16 8/16-BIT PPG
16.6
Controlling Pin Output of 8/16-bit PPG Pulses
The pulses generated by this module can be output from external pins PPG00 and
PPG10.
■ Controlling Pin Output of 8/16-bit PPG Pulses
To output the pulses from an external pin, write "1" to the bit corresponding to each pin (PPGC0: PE00,
PPGC1: PE10). When "0" is written to these bits (default), the pulses are not output from the corresponding
external pins; the pins work as general-purpose ports.
In 16-bit PPG mode, the same waveform is output from PPG00 and PPG10. Thus, the same output can be
obtained by enabling both external pin.
In 8-bit prescaler + 8-bit PPG mode, the 8-bit prescaler toggle output waveform is output from PPG00,
while the 8-bit PPG waveform is output from PPG10. Figure 16.6-1 is a diagram of output waveforms in
this mode.
Figure 16.6-1 8+8 PPG Output Operation Waveform
Ph0
Pl0
PPG0
PPG1
Ph1
Pl0 = T
Pl1
(L0+1)
Ph0 = T
(L0+1)
Pl1 = T
(L0+1)
(L1+1)
Ph1 = T
(L0+1)
(H1+1)
L0 :
L1 :
H1 :
T :
Ph0 :
Pl0 :
Ph1 :
ch.0 PRLL value and ch.0 PRLH value
ch.1 PRLL value
ch.1 PRLH value
Input clock cycle
PPG00 "H" pulse width
PPG00 "L" pulse width
PPG10 "H" pulse width
Pl1 :
PPG10 "L" pulse width
Note:
Set the same value in ch.0 PRLL and ch.0 PRLH.
265
CHAPTER 16 8/16-BIT PPG
16.7
8/16-bit PPG Interrupts
For the 8/16-bit PPG, an interrupt becomes active when the reload value counts out and
a borrow occurs.
■ 8/16-bit PPG Interrupts
In 8-bit PPG 2ch mode or 8-bit prescaler + 8-bit PPG mode, an interrupt is requested by a borrow in each
counter. In 16-bit PPG mode, PUF0 and PUF1 are simultaneously set by a borrow in the 16-bit counter.
Therefore, enable only PIE0 or PIE1 to unify the interrupt causes. In addition, simultaneously clear the
interrupt flags for PUF0 and PUF1.
266
CHAPTER 16 8/16-BIT PPG
16.8
Initial Values of 8/16-bit PPG Hardware
The hardware components of this block are initialized to the following values when
reset:
■ Initial Values of 8/16-bit PPG Hardware
● Registers
•
PPGC0 → 0X000XX1B
•
PPGC1 → 0X000001B
•
PPG01 → 000000XXB
● Pulse outputs
•
PPG00 → "L"
•
PPG10 → "L"
•
PE00
→
PPG00 output disabled
•
PE10
→
PPG10 output disabled
● Interrupt requests
•
IRQ0 → "L"
•
IRQ1 → "L"
Hardware components other than the above are not initialized.
Note:
In a mode other than 16-bit PPG mode, it is recommended to use a word transfer instruction to write
data in reload registers PRLL and PRLH.
If two byte transfer instructions are used to write a data item to these registers, a pulse of
unexpected cycle time may be output depending on the timing.
Figure 16.8-1 Write Timing for 8/16-bit PPG Reload Registers (PRLL and PRLH)
PPG0
B
A
B
C
A
B
C
C
D
D
(1)
267
CHAPTER 16 8/16-BIT PPG
Assume that PRLL is updated from A to C before (1) in the time chart above, and PRLH is updated from B
to D after (1). Since the PRL values at (1) are PRLL=C and PRLH=B, a pulse of "L" side count value C
and "H" side count value B is output only once.
Similarly, to write data in PRL of ch.0 and ch.1 in 16-bit PPG mode, use a long word transfer instruction,
or use word transfer instructions in the order of ch.0 and then ch.1. In this mode, the data is only
temporarily written to ch.0 PRL. Then, the data is actually written into ch.0 PRL when the ch.1 PRL is
written to.
In a mode other than 16-bit PPG mode, ch.0 and ch.1 PRL are written independently.
Figure 16.8-2 PRL Write Operation Block Diagram
ch.0 PRL write data
ch.1 PRL write data
Transferred in synchronization
with ch.1 write in 16-bit
PPG mode
Temporary latch
ch.0 write in a mode other
than 16-bit PPG mode
ch.1 write
ch.0 PRL
268
ch.1 PRL
CHAPTER 17
DTP/EXTERNAL
INTERRUPTS
This chapter explains the functions and operations of
the DTP/external interrupts.
17.1 Outline of DTP/External Interrupts
17.2 DTP/External Interrupt Registers
17.3 Operations of DTP/External Interrupts
17.4 Switching between External Interrupt and DTP Requests
17.5 Notes on Using DTP/External Interrupts
269
CHAPTER 17 DTP/EXTERNAL INTERRUPTS
17.1
Outline of DTP/External Interrupts
The data transfer peripheral (DTP) is located between an external peripheral and the
F2MC-16LX CPU. The DTP receives a DMA request or interrupt request from the external
peripheral, transfers the request to the F2MC-16LX CPU to activate the intelligent I/O
service or interrupt processing.
■ Outline of DTP/External Interrupts
For the intelligent I/O service, "H" and "L" request levels are available. For an external interrupt request,
four request levels are available: "H", "L", rising edge, and falling edge.
For the MB90390 Series, the external bus interface is not supported. Therefore the DTP/External Interrupt
can not serve as the data transfer peripheral. It can be only used as the External Interrupt.
■ Block Diagram of DTP/External Interrupts
Figure 17.1-1 Block Diagram of DTP/external Interrupts
8
Interrupt/DTP enable register
8
Gate
8
Edge detection circuit
Cause F/F
8
Request input
Interrupt/DTP cause register
16
Request level setting register
■ DTP/External Interrupts Registers
bit
Address : 000030H
bit
Address : 000031H
bit
Address : 000032H
bit
Address : 000033H
270
7
6
5
4
3
2
1
0
EN7
EN6
EN5
EN4
EN3
EN2
EN1
EN0
15
14
13
12
11
10
9
8
ER7
ER6
ER5
ER4
ER3
ER2
ER1
ER0
7
6
5
4
3
2
1
0
LB3
LA3
LB2
LA2
LB1
LA1
LB0
LA0
15
14
13
12
11
10
9
8
LB7
LA7
LB6
LA6
LB5
LB4
LA4
LA5
Interrupt/DTP enable register
(ENIR)
External interrupt request register
(EIRR)
Request level setting register
(ELVR)
Request level setting register
(ELVR)
CHAPTER 17 DTP/EXTERNAL INTERRUPTS
17.2
DTP/External Interrupt Registers
The DTP/external interrupts has the following three types of registers:
• Interrupt/DTP enable register (ENIR: Interrupt request enable register)
• Interrupt/DTP flag (EIRR: External interrupt request register)
• Request level setting register (ELVR: External level register)
■ Interrupt/DTP Enable Register (ENIR: Interrupt Request Enable Register)
bit
ENIR
Address : 000030 H
7
6
5
4
3
2
1
0
Initial value
EN7
EN6
EN5
EN4
EN3
EN2
EN1
EN0
00000000B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
ENIR enables the function to issue a request to the interrupt controller using a device pin as an external
interrupt/DTP request input. A pin corresponding to a "1" bit of this register is used as an external interrupt/
DTP request input. A pin corresponding to a "0" bit holds the external interrupt/DTP request input cause,
but does not issue a request to the interrupt controller.
Note:
Clear the corresponding DTP/external interrupt source bit (EIRR: ER) right before DTP/external
interrupt is allowed (ENIR: EN = 1).
■ Interrupt/DTP Flags (EIRR: External Interrupt Request Register)
bit
EIRR
Address : 000031H
15
14
13
12
11
10
9
8
ER7
ER6
ER5
ER4
ER3
ER2
ER1
ER0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W ........The objects differ
Initial value
XXXXXXXX B
for R/W.
The EIRR indicates the presence of external interrupt/DTP requests at the pins corresponding to the "1" bits
of this register. Writing "0" to a bit of this register clears the corresponding request flag. Writing "1" has no
effect. "1" is always read from this register by a read-modify-write (RMW) instruction.
271
CHAPTER 17 DTP/EXTERNAL INTERRUPTS
Note:
If multiple external interrupt request outputs are enabled (ENIR: EN3 to EN0=1), only the bits for
which the CPU accepts an interrupt (bits for which "1" was set in ER3 to ER0) are cleared. No other
bits must be cleared unconditionally.
• The value of DTP/external interrupt source bit (EIRR: ER) is valid only when the corresponding
DTP/external interrupt enable bit (ENIR: EN) is set to "1". In the case that DTP/external interrupt
isn’t allowed (ENIR: EN = 0), DTP/external interrupt source bit could be set regardless of the
possibility of DTP/external interrupt source.
• Clear the corresponding DTP/external interrupt source bit (EIRR: ER) right before DTP/external
interrupt is allowed (ENIR: EN = 1).
■ Request Level Setting Register (ELVR: External Level Register)
bit
Address : 000032 H
bit
Address : 000033 H
7
6
5
4
3
2
1
0
Initial value
LB3
LA3
LB2
LA2
LB1
LA1
LB0
LA0
00000000B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
15
14
13
12
11
10
9
8
Initial value
LB7
LA7
LB6
LA6
LB5
LB5
LB4
LA4
00000000B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
ELVR defines the request event at the external pin. Each pin is assigned two bits as described in Table
17.2-1. If a request is detected by the input level, the interrupt flag is set as long as the input is at the
specified level even after the flag is reset by software.
Table 17.2-1 Interrupt Request Detection Factor for External Pins
272
LBx
LAx
Interrupt request detection factor
0
0
"L" level pin input
0
1
"H" level pin input
1
0
Rising edge pin input
1
1
Falling edge pin input
CHAPTER 17 DTP/EXTERNAL INTERRUPTS
17.3
Operations of DTP/External Interrupts
When the interrupt flag is set, this block signals an interrupt to the interrupt controller.
The interrupt controller judges the priority levels of the simultaneous interrupts, and
issues an interrupt request to the F2MC-16LX CPU if the interrupt from this block has
the highest priority. The F2MC-16LX CPU compares the ILM bits of its internal CCR
register and the interrupt request. If the interrupt level of the request is higher than that
indicated by the ILM bits, the F2MC-16LX CPU activates the hardware interrupt
processing microprogram as soon as the currently executing instruction is terminated.
■ External Interrupt Operation
In the hardware interrupt processing microprogram, the CPU reads the ISE bit information from the
interrupt controller, identifies that the request is for interrupt processing based on that information, and
branches to the interrupt processing microprogram. The interrupt processing microprogram reads the
interrupt vector area and issues an interrupt acknowledgment signal for the interrupt controller. Then, the
microprogram transfers the jump destination address of the macro instruction generated from the vector to
the program counter, and executes the user interrupt processing program.
Figure 17.3-1 External Interrupt
External interrupt/DTP
Interrupt controller
F2MC-16LX CPU
ICRyy
IL
Other request
ELVR
EIRR
ENIR
Cause
CMP
ICRxx
CMP
ILM
INTA
273
CHAPTER 17 DTP/EXTERNAL INTERRUPTS
■ DTP Operation
To activate the intelligent I/O service, the user program initially sets the address of a register, assigned
between "000000H" and "0000FFH", in the I/O address pointer of the intelligent I/O service descriptor.
Then, the user program sets the start address of the memory buffer in the buffer address pointer.
The DTP operation sequence is almost the same as for external interrupts. The operation is identical until
the CPU activates the hardware interrupt processing microprogram. Then, for the DTP, control is
transferred to the intelligent I/O service processing microprogram, since the ISE bit read by the CPU within
the hardware interrupt processing microprogram indicates the DTP. Once the intelligent I/O service is
activated, a read or write signal is sent to the addresses external peripheral, and data is transferred between
the peripheral and the chip. The external peripheral must cancel the interrupt request to this chip within
three machine cycles after the transfer is made. When the transfer is completed, the descriptor is updated,
and the interrupt controller generates a signal that clears the transfer cause. Upon receiving the signal to
clear the transfer cause, this resource clears the flip-flop holding the cause and prepares for the next request
from the pin. For details of the intelligent I/O service processing, refer to the MB90500 Programming
Manual.
Figure 17.3-2 Timing to Cancel the External Interrupt at the End of DTP Operation
Edge request or "H" level request
Internal operation
Interrupt cause
* When data is transferred from the I/O register to memory
in the intelligent I/O service
Selecting and
reading
descriptor
Address bus pin
Read address
Data bus pin
Write address
Read data
Write data
Read signal
Write signal
Cancel within three machine cycles.
Data, address
bus
Internal bus
Register
External peripheral
Figure 17.3-3 Sample Interface to the External Peripheral
INT
IRQ
DTP
Cancel within three machine
cycles after transfer.
274
MB90390 series
CORE
MEMORY
CHAPTER 17 DTP/EXTERNAL INTERRUPTS
17.4
Switching between External Interrupt and DTP Requests
To switch between external interrupt and DTP requests, use the ISE bit in the ICR
register corresponding to this block, which is in the interrupt controller. Each pin is
individually assigned ICR. Thus, a pin is used for a DTP request if "1" is written to the
ISE bit of the corresponding ICR, and is used for an external interrupt request if "0" is
written to the bit.
■ Switching between External Interrupt and DTP Requests
Figure 17.4-1 Switching between External Interrupt and DTP Requests
Interrupt controller
0
ICR xx
ICR yy
1
F2MC-16LX CPU
Pin
External
interrupt/DTP
DTP
External interrupt
275
CHAPTER 17 DTP/EXTERNAL INTERRUPTS
17.5
Notes on Using DTP/External Interrupts
Note carefully the following items when using DTP/external interrupts:
• Conditions on the externally connected peripheral when DTP is used
• External interrupt/DTP operation procedure
• External interrupt request level
■ Notes on Using DTP/External Interrupts
● Conditions on the externally connected peripheral when DTP is used
DTP supports only external peripherals that automatically clear a request once a transfer is completed. The
system must be designed so that a transfer request is canceled within three machine cycles (provisional)
after transfer operation starts. Otherwise, this resource assumes that a transfer request is issued.
● External interrupt/DTP operation procedure
To set registers in the external interrupt/DTP, follow the steps below:
1. Set the general-purpose I/O pin shared with the pin for using the external interrupt input as the input port.
2. Disable the bits corresponding to the enable register.
3. Set the bits corresponding to the request level setting register.
4. Clear the bits corresponding to the cause register.
5. Enable the bits corresponding to the enable register.
(Steps 4. and 5. can be simultaneously performed by word specification.)
To set a register in this resource, ensure that the enable register is disabled. Before enabling the enable
register, ensure that the cause register is cleared. Clearing the cause register prevents a false interrupt cause
from being determined while registers are set or interrupts are enabled.
● External interrupt request level
To detect an edge for an edge request you need at least the minimum pulse width described in datasheet.
Please refer to it.
As shown in Figure 17.5-1, when the request input level is related to the level setting, a request that is input
from an external device to the interrupt controller is kept active even if the request is later canceled because
a cause hold circuit has been installed. To cancel the request to the interrupt controller, the cause hold
circuit must be cleared as shown in Figure 17.5-2.
Figure 17.5-1 Clearing the Cause Hold Circuit Upon Level Set
Level detection
Interrupt cause
Cause F/F (interrupt/DTP
cause register)
The cause is kept held unless cleared.
276
Enable gate
To interrupt
controller
CHAPTER 17 DTP/EXTERNAL INTERRUPTS
Figure 17.5-2 Interrupt Cause and Interrupt Request to the Interrupt Controller while Interrupts are
Enabled
Interrupt cause
"H" level
Interrupt request to
the interrupt controller
Set inactive when the cause F/F is cleared.
277
CHAPTER 17 DTP/EXTERNAL INTERRUPTS
278
CHAPTER 18
8/10-BIT A/D CONVERTER
This chapter describes the functions and operation of
the 8/10-bit A/D converter.
18.1 Outline of the 8/10-Bit A/D Converter
18.2 Configuration of the 8/10-Bit A/D Converter
18.3 8/10-Bit A/D Converter Pins
18.4 8/10-Bit A/D Converter Registers
18.5 8/10-Bit A/D Converter Interrupts
18.6 Operation of the 8/10-Bit A/D Converter
18.7 Notes on the 8/10-Bit A/D Converter
18.8 Sample Program 1 for the 8/10-Bit A/D Converter (Single
Conversion Mode Using EI2OS)
18.9 Sample Program 2 for the 8/10-Bit A/D Converter (Continuous
Conversion Mode Using EI2OS)
18.10 Sample Program 3 for the 8/10-Bit A/D Converter (Stop
Conversion Mode Using EI2OS)
279
CHAPTER 18 8/10-BIT A/D CONVERTER
18.1
Outline of the 8/10-Bit A/D Converter
Using the RC-type successive approximation conversion method, the 8/10-bit A/D
converter converts an analog input voltage into a 10-bit or 8-bit digital value. An input
signal is selected from fifteen channels for analog input pins. The conversion can be
activated by software, 16-bit reload timer 1 output, and external trigger.
■ Functions of the 8/10-bit A/D Converter
The converter converts the analog voltage input to an analog input pin (input voltage) to a digital value.
The converter has the following features:
• The minimum conversion time is 4.9 μs (only possible at certain machine clock frequencies; includes
the sampling time).
• The minimum sampling time is 1.6 μs (only possible at certain machine clock frequencies).
• The converter uses the RC-type successive approximation conversion method with a sample hold
circuit.
• A resolution of 10 bits or 8 bits can be selected.
• Up to 15 channels for analog input pins can be selected by a program.
• At the end of A/D conversion, an interrupt request can be generated and EI2OS can be activated.
• In the interrupt-enabled state, the conversion data protection function prevents any part of the data from
being lost through continuous conversion.
• The conversion can be activated by software, 16-bit reload timer 1 (rising edge), and external trigger
ADTG.
• The MB90390 series has 15 analog inputs, where from either channels 0 to 7 or channels 8 to 14 can be
selected as inputs for the A/D converter.
Table 18.1-1 8/10-bit A/D Converter Conversion Modes
Single conversion
Scan conversion
Single conversion mode
Converts the input of a specified
channel (single channel) just once.
Converts the inputs of two or more consecutive
channels (up to eight channels) just once. Either
channel 0 to channel 7 or channel 8 to channel 14
can be selected.
Continuous conversion
mode
Converts the input of a specified
channel (single channel) repeatedly.
Converts the inputs of two or more consecutive
channels (up to eight channels) repeatedly.Either
channel 0 to channel 7 or channel 8 to channel 14
can be selected.
Converts the input of a specified
channel (single channel), after which
it is on standby for the next activation.
Converts the inputs of two or more consecutive
channels (up to eight channels). Either channel 0 to
channel 7 or channel 8 to channel 14 can be
selected.
When a channel has been converted, the converter is
put on standby for the next activation.
Stop conversion mode
280
CHAPTER 18 8/10-BIT A/D CONVERTER
Table 18.1-2 8/10-bit A/D Converter Interrupts and EI2OS
Interrupt control register
Interrupt No.
#31 (1FH)
Vector table address
EI2OS
Register
name
Address
Lower
Upper
Bank
ICR10
0000BAH
FFFF80H
FFFF81H
FFFF82H
❍
❍: Available
281
CHAPTER 18 8/10-BIT A/D CONVERTER
18.2
Configuration of the 8/10-Bit A/D Converter
The 8/10-bit A/D converter has nine blocks:
• A/D control status register (ADCS0, ADCS1)
• A/D data register (ADCR0, ADCR1)
• Clock selector (Input clock selector for activating A/D conversion)
• Decoder
• Analog channel selector
• Sample hold circuit
• D/A converter
• Comparator
• Control circuit
■ Block Diagram of the 8/10-bit A/D Converter
Figure 18.2-1 Block Diagram of the 8/10-bit A/D Converter
Interrupt request signal #31 (1FH)
A/D control status register
(ADCS0/ADCS1)
BUSY INT INTE PAUS STS1 STS0 STRT Reserved MD1 MD0 ANS2 ANS1 ANS0 ANE2 ANE1 ANE0
6
PB6/AN14
PB5/AN13
PB4/AN12
PB3/AN11
PB2/AN10
PB1/AN9
PB0/AN8
P67/AN7
P66/AN6
P65/AN5
P64/AN4
P63/AN3
P62/AN2
P61/AN1
P60/AN0
ADSEL
A/D data register
(ADCR0/ADCS1)
φ : Machine clock
- : Undefined
282
2
Clock selector
Decoder
Internal data bus
16-bit reload timer 1 output
External trigger (ADTG)
φ
Analog
channel
selector
S10 ST1 ST0 CT1 CT0
Sample
holding circuit
AVRH/AVRL
AVcc
AVss
Comparator
Control circuit
2
D/A converter
2
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
CHAPTER 18 8/10-BIT A/D CONVERTER
● A/D control status register (ADCS0, ADCS1)
This register selects activation by software or another activation trigger, the conversion mode, and the A/D
conversion channel. It also enables or disables interrupt requests, checks the interrupt request status, and
indicates whether the conversion has halted or is in progress.
● A/D data register (ADCR0, ADCR1)
This register holds the result of A/D conversion and selects the resolution for A/D conversion.
● Clock selector
The clock selector selects the clock for activating A/D conversion. Either 16-bit reload timer channel 1
output or external trigger (ADTG) can be used as the activation clock.
● Decoder
This circuit selects the analog input pin to be used based on the settings of the ANE0 to ANE2 bits and
ANS0 to ANS2 bits of the A/D control status register (ADCS0).
● Analog channel selector
This circuit selects the pin to be used from fifteen analog input pins.
● Sample hold circuit
This circuit maintains the input voltage of the channel selected by the analog channel selector. It samples
and maintains the input voltage obtained immediately after the activation of A/D conversion. This circuit
protects the A/D conversion from any variations in the input voltage during approximation.
● D/A converter
This circuit generates a reference voltage for comparison with the input voltage maintained by the sample
hold circuit.
● Comparator
This circuit compares the input voltage maintained by the sample hold circuit with the output voltage of the
D/A converter to determine which is greater.
● Control circuit
This circuit determines the A/D conversion value based on the decision signal generated by the comparator.
When the A/D conversion has been completed, the circuit sets the conversion result in the A/D data register
(ADCR0, ADCR1) and generates an interrupt request.
283
CHAPTER 18 8/10-BIT A/D CONVERTER
18.3
8/10-Bit A/D Converter Pins
This section describes the 8/10-bit A/D converter pins and provides pin block diagrams.
■ 8/10-bit A/D Converter Pins
The A/D converter pins are also used as general ports.
Table 18.3-1 8/10-bit A/D Converter Pins
Function
Pin name
Ch.0
P60/AN0
Ch.1
P61/AN1
Ch.2
P62/AN2
Ch.3
P63/AN3
Ch.4
P64/AN4
Ch.5
P65/AN5
Ch.6
P66/AN6
Ch.7
P67/AN7
Ch.8
PB0/AN8
Ch.9
PB1/AN9
Ch.10
PB2/AN10
Ch.11
PB3/AN11
Ch.12
PB4/AN12
Ch.13
PB5/AN13
Ch.14
PB6/AN14
284
Pin function
Input-output signal type
Pull-up
option
Standby
control
CMOS output/CMOS or
Automotive Hysteresis input or
analog input
Not selectable
Not selectable
Port 6
I/O or analog
input
Port B
I/O or analog
input
CHAPTER 18 8/10-BIT A/D CONVERTER
■ Analog Input Enable Registers
Figure 18.3-1 shows the analog input enable registers (ADER1/ADER0).
Figure 18.3-1 Analog Input Enable Registers (ADER1/ADER0)
Address:
00000D H
00000C H
bit
Initial value:
15
14
13
12
11
10
9
8
ADSEL ADE14 ADE13 ADE12 ADE11 ADE10 ADE9 ADE8
7
6
5
4
3
2
1
0
ADE7 ADE6 ADE5 ADE4 ADE3 ADE2 ADE1 ADE0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
ADER1/ADER0
Note:
If bit15 (ADSEL) is set to "0" the pins AN0 to AN7 (Port P60 to P67) are selected as inputs for the A/D
Converter. If this bit is set to "1" the pins AN8 to AN14 (Port PB0 to PB6) are selected as inputs for
the A/D Converter.
■ Block Diagram of the 8/10-bit A/D Converter Pins
Figure 18.3-2 Block Diagram of the P60/AN0 to P67/AN7 and PB0/AN8 to PB6/AN14 Pins
Internal data bus
ADER
Analog input
PDR read
Output latch
PDR
(Port data register)
PDR write
P-ch
Pin
Direction latch
N-ch
DDR write
DDR read
DDR
(Port direction register)
standby control (SBL = 1)
Notes:
• To use a pin as an input port, set the corresponding bit of the DDR6 / DDRB register to "0", and
handle it as normal digital input. Set the corresponding bit of the ADER register to "0".
• To use the pin as an analog input pin, set the corresponding bit of the ADER register to "1". The
value read from the PDR6 / PDRB register is "0".
285
CHAPTER 18 8/10-BIT A/D CONVERTER
18.4
8/10-Bit A/D Converter Registers
This section lists the 8/10-bit A/D converter registers.
■ 8/10-bit A/D Converter Registers
Figure 18.4-1 8/10-bit A/D Converter Registers
Address:
286
bit
15
14
13
12
11 10
9
8
7
6
5
4
3
00000DH / 00000CH
ADER1
ADER0
000035H / 000034H
ADCS1
ADCS0
000037H / 000036H
ADCR1
ADCR0
2
1
0
CHAPTER 18 8/10-BIT A/D CONVERTER
18.4.1
Analog Input Enable / A/D Converter Select Register
The MB90390 series has 15 analog inputs but only one A/D converter with 8 inputs.
Therefore, the special bit ADSEL can be used to select the analog input channels.
■ Upper Bits of the Analog Input Enable / A/D Converter Select Register (ADER1)
Figure 18.4-2 Configuration of the Upper Bits of Analog Input Enable / A/D Converter Select Register
(ADER1)
bit15
Address
00000D H
bit14
bit13
bit12
bit11
bit10
bit9
ADSEL ADE14 ADE13 ADE12 ADE11 ADE10 ADE9
R/W
R/W
R/W
R/W
R/W
R/W
ADEx
0
1
R/W : Readable and writable
: Initial value
R/W
bit8
ADE8
Initial value
01111111B
R/W
Analog input enable bits
Port input mode (Port B).
Analog input mode (Initial value).
ADSEL
A/D converter input selection bit
0
1
AN0 to AN7 (Port 6) are selected as inputs.
AN8 to AN14 (Port B) are selected as inputs.
■ Lower Bits of the Analog Input Enable Register (ADER0)
Figure 18.4-3 Configuration of the Lower Bits of the Analog Input Enable Register (ADER0)
Address
00000C H
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
ADE7
ADE6
ADE5
ADE4
ADE3
ADE2
ADE1
ADE0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W : Readable and writable
ADEx
0
1
Initial value
11111111B
Analog input enable bits
Port input mode (Port 6).
Analog input mode (Initial value).
: Initial value
287
CHAPTER 18 8/10-BIT A/D CONVERTER
18.4.2
A/D Control Status Register 1 (ADCS1)
A/D control status register 1 (ADCS1) selects activation by software or activation
trigger, enables or disables interrupt requests, and indicates interrupt request status
and whether conversion is halted or in progress.
■ Upper Bits of the A/D Control Status Register 1 (ADCS1)
Figure 18.4-4 Configuration of the A/D Control Status Register 1 (ADCS1)
Address
000035H
bit
15
14
13
BUSY
INT
INTE
PAUS STS1 STS0 STRT Reserved
R/W
R/W
R/W
R/W
12
11
R/W
10
9
R/W
8
W
7
0
Initial value
(ADCS0)
00000000B
R/W
Reserved bit
Reserved
Always write "0" to this bit.
STRT
0
1
A/D conversion activation bit
(valid only when activated by software (ADC2: EXT= 0))
Does not activate the A/D conversion.
Activate the A/D conversion function.
A/D activation select bit
STS1 STS0
0
0
Activation by software.
0
1
1
0
1
1
Activation by external trigger or software.
Activation by 16-bit reload timer 1 output
or software.
Activation by external trigger, 16-bit
reload timer 1 output, or software.
Halt flag bit
(valid only when EI2OS is used)
PAUS
0
1
A/D conversion is not halted.
A/D conversion is halted.
INTE
1
Enables interrupt request output.
Reading
Writing
0
A/D conversion has not been completed.
Clears this bit.
1
A/D conversion has been completed.
No change, no effect on other bits.
BUSY
288
Disables interrupt request output.
Interrupt request flag bit
INT
R/W : Readable and writable
W : Write only
- : Undefined
: Initial value
Interrupt request enable bit
0
Busy bit
Reading
Writing
0
A/D conversion is halted.
Stops the A/D conversion.
1
A/D conversion is in progress.
No change, no effect on other bits.
CHAPTER 18 8/10-BIT A/D CONVERTER
Table 18.4-1 Function Description of Each Bit of Control Status Register 1 (ADCS1)
Bit name
Function
•
•
bit15
BUSY:
Busy bit
This bit indicates the operating status of the A/D converter.
If the value read from this bit is "0", A/D conversion has halted. If the read value is "1", A/D
conversion is in progress.
• Writing "0" to this bit forces the A/D conversion to stop. Writing "1" to this bit does not change
the bit value and has no effect on other bits.
Note:
Never select forced stop (BUSY = 0) and software activation (STRT = 1) simultaneously.
•
•
bit14
INT:
Interrupt request flag
bit
bit13
INTE:
Interrupt request
enable bit
When A/D conversion data is set in the A/D data register, this bit is set to "1".
When both this bit and the interrupt request enable bit (ADCS: INTE) are "1", an interrupt
request is generated. If EI2OS has been enabled, it is activated.
• Writing "0" to this bit clears the bit. Writing "1" to this bit does not change the bit value and has
no effect on other bits.
• When EI2OS is activated, this bit is cleared.
Note:
When clearing this bit by writing "0" it, do so only while the A/D converter is not operating.
•
•
•
This bit enables or disables interrupt output to the CPU.
When both this bit and the interrupt request flag bit (ADCS: INT) are set to "1", an interrupt
request is generated.
When EI2OS is used, set this bit to "1".
•
•
bit12
bit11
bit10
PAUS:
Halt flag bit
STS1, STS0:
A/D activation select
bit
When A/D conversion stops temporarily, this bit is set to "1".
This A/D converter has just one A/D data register. In continuous conversion mode, if a
conversion result were written before the previous conversion result was read by the CPU, the
previous result would be lost. When continuous conversion mode is selected, the program must
be written so that the conversion result is automatically transferred to memory by EI2OS each
time a conversion is completed. This bit also protects against multiple interrupts preventing the
completion of conversion data transfer before the next conversion. When a conversion is
completed, this bit is set to "1". This status is maintained until EI2OS finishes transferring the
contents of the data register. Meanwhile, the A/D conversion is halted so that no conversion data
can be stored. When EI2OS completes the transfer, the A/D converter automatically resumes the
conversion. Once this bit is set, it is not cleared by itself, write "0" to clear this bit.
Note:
This bit is valid only when EI2OS is used.
•
•
These bits select how A/D conversion is to be activated.
When two or more activation causes are shared, activation is the result of the cause that occurs
first.
Note:
Change the setting during A/D conversion only while there is no corresponding activation cause,
since the change becomes effective immediately.
bit9
STRT:
A/D conversion
activation bit
• This bit allows software to start A/D conversion.
• Writing "1" to this bit activates A/D conversion.
• Writing "0" to this bit doesn’t active A/D conversion.
• In stop conversion mode, conversion cannot be reactivated with this bit.
Note:
Never select forced stop (BUSY = 0) and software activation (STRT = 1) simultaneously.
bit8
Reserved:
Reserved bit
Note:
Always write "0" to this bit.
289
CHAPTER 18 8/10-BIT A/D CONVERTER
18.4.3
A/D control status register 0 (ADCS0)
A/D control status register 0 (ADCS0) selects the conversion mode and A/D conversion
channel.
■ A/D Control Status Register 0 (ADCS0)
Figure 18.4-5 Configuration of the A/D Control Status Register 0 (ADCS0)
bit15
Address
000034H
(ADCS: H)
bit6
bit8 bit7
bit5
bit4
bit3
bit2
bit1
bit0
MD1
MD0 ANS2 ANS1 ANS0 ANE2 ANE1 ANE0
R/W
R/W
R/W
R/W
ANE2 ANE1 ANE0
0
0
R/W
R/W
R/W
Initial value
00000000B
R/W
A/D conversion end channel select bit
0
AN0/AN8 pin
0
0
1
AN1/AN9 pin
0
1
0
AN2/AN10 pin
0
1
1
AN3/AN11 pin
1
0
0
AN4/AN12 pin
1
0
1
AN5/AN13 pin
1
1
0
AN6/AN14 pin
1
1
1
AN7 pin
A/D conversion start channel select bit
ANS2 ANS1 ANS0
Halt
0
0
0
AN0/AN8
0
0
1
AN1/AN9
0
1
0
AN2/AN10
0
1
1
AN3/AN11
1
0
0
AN4/AN12
1
0
1
AN5/AN13
1
1
0
AN6/AN14
1
1
1
AN7
MD1
R/W : Readable and writable
: Initial value
290
Read during
conversion
Read during a pause in
stop conversion mode
Number of
the current
conversion
channel
Number of the last
conversion channel
MD0
A/D conversion mode select bit
0
0
Single conversion mode 1 (reactivation allowed
during operation)
0
1
Single conversion mode 2 (reactivation not
allowed during operation)
1
0
1
1
Continuous conversion mode (reactivation not
allowed during operation)
Stop conversion mode (reactivation not allowed
during operation)
CHAPTER 18 8/10-BIT A/D CONVERTER
Table 18.4-2 Function Description of Each Bit of Control Status Register 0 (ADCS0)
Bit name
Function
MD1, MD0:
A/D conversion
mode select bit
• These bits select the conversion mode of the A/D conversion function.
• The two-bit value of the MD1 and MD0 bits determines the mode that is selected from
among four modes: single conversion mode 1, single conversion mode 2, continuous
conversion mode, and stop conversion mode.
• The operation in each mode is described below:
- Single conversion mode 1:
Just a single A/D conversion from the channel set by ANS2 to ANS0 to the channel
set by ANE2 to ANE0 is performed.
Reactivation during operation is allowed.
- Single conversion mode 2:
Just a single A/D conversion from the channel set by ANS2 to ANS0 to the channel
set by ANE2 to ANE0 is performed.
Reactivation during operation is not allowed.
- Continuous conversion mode:
A/D conversion from the channel set by ANS2 to ANS0 to the channel set by ANE2
to ANE0 is performed repeatedly. The repeated conversion continues until it is
stopped by the BUSY bit. Reactivation during operation is not allowed.
- Stop conversion mode:
A/D conversion from the channel set by ANS2 to ANS0 to the channel set by ANE2
to ANE0 is performed repeatedly with a pause after the conversion of each channel.
The repeated conversion continues until it is stopped by the BUSY bit.
Reactivation during operation is not allowed. In the pause state, the conversion is
reactivated when an activation cause selected by the STS1 and STS0 bits is
generated.
Note:
In the single conversion mode, continuous conversion mode, and stop conversion
mode, no reactivation by a timer, external trigger, or software is allowed.
bit5
bit4
bit3
ANS2, ANS1,
ANS0:
A/D conversion
start channel select
bit
• These bits set the A/D conversion start channel and indicate the number of the current
conversion channel.
• When activated, A/D conversion starts from the channel specified by these bits.
• During A/D conversion, the bits indicate the number of the current conversion channel.
During a pause in stop conversion mode, the bits indicate the number of the last
conversion channel.
Note:
Don’t set the bits in this resister using the read-modify-write instruction (RMW) after
the start channels are set for A/D conversion start channel select bits (ANS2, ANS1,
and ANS0).
For ANS2, ANS1, and ANS0 bits, their previous conversion channels are read until A/
D conversion operation starts, therefore, if you set the bits in this resister using the
read-modify-write instruction (RMW) after the start channels are set for ANS2, ANS1,
and ANS0 bits, the values of ANE2, ANE1, and ANE0 bits may be rewritten.
bit2
bit1
bit0
ANE2, ANE1,
ANE0:
A/D conversion
end channel select
bit
• These bits set the A/D conversion end channel.
• When activated, A/D conversion is performed up to the channel specified by these bits.
• When these bits specify the channel specified by ANS2 to ANS0, just that channel is
converted. In continuous or stop conversion mode, the start channel specified by ANS2
to ANS0 is converted after the channel specified by these bits. If the start channel is
greater than the end channel, the start channel to AN7 and AN0 to the end channel are
converted in that order in a single series of conversions.
bit7
bit6
291
CHAPTER 18 8/10-BIT A/D CONVERTER
18.4.4
A/D Data Register (ADCR0, ADCR1)
The A/D data register (ADCR0, ADCR1) holds the result of A/D conversion and selects
the resolution of A/D conversion.
■ A/D Data Register (ADCR0, ADCR1)
Figure 18.4-6 A/D Data Register (ADCR0, ADCR1)
bit15 bit14 bit13 bit12
Address
000037H S10 ST1 ST0 CT1
000036H
W
W
W
W
bit11 bit10 bit9
bit8
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
CT0
-
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
00000XXX B
W
-
R
R
R
R
R
R
R
R
R
R
XXXXXXXXB
AD data bit
D0 to D9
Conversion data
R :
Read only
W :
Write only
X :
Undefined value
-
Undefined
:
Comparison time setting bit
CT1
0
0
1
1
CT0
0
1
0
1
44 machine cycles (5.50µ[email protected])
66 machine cycles (3.3µ[email protected])
88 machine cycles (3.67µ[email protected])
176 machine cycles (7.33µ[email protected])
ST1
0
0
1
1
ST0
0
1
0
1
Sampling time setting bit
20 machine cycles (2.5µ[email protected])
32 machine cycles (1.6µ[email protected])
48 machine cycles (2.0µ[email protected])
128 machine cycles (5.33µ[email protected])
S10
0
1
AD data bit
10-bit resolution mode (D9 to D0)
8-bit resolution mode (D7 to D0)
Note:
When setting the Comparison and Sampling time, the minimal required value has to be respected.
For example, 44 machine cycles cannot be used with some frequencies. Please see the Data sheet
for the precise specification.
292
CHAPTER 18 8/10-BIT A/D CONVERTER
Table 18.4-3 Function Description of Each Bit of A/D Data Register 0 (ADCR0)
Bit name
Function
S10:
A/D conversion
resolution selection
bit
• This bit selects an A/D conversion resolution.
• Writing "0" to this bit selects a resolution of 10 bits, and writing "1" to this bit selects a
resolution of 8 bits.
Note:
The data bit to be used depends on the resolution.
ST1, ST0:
Sampling time
setting bit
• These bits select the sampling time for A/D conversion.
• When A/D conversion is activated, analog input is fetched during the time set in this
bit.
Note:
Setting these bits to "00B" during 16(20, 24)-MHz operation may disable normal
fetching of the analog voltage. The "00B" setting is proposed for up to 8 MHz.
bit12
bit11
CT1, CT0:
Comparison time
setting bit
• These bits select the comparison time for A/D conversion.
• After analog input is fetched (i.e., sampling time elapses), conversion result data is
defined and stored in bit9 to bit0 of this register after the time set in these bits.
Note:
Setting these bits to "00B" during 16(20, 24)-MHz operation may disable normal
acquisition of the analog conversion value. The "00B" setting is proposed for up to 8
MHz.
bit10
-:
Undefined
bit15
bit14
bit13
bit9 to
bit0
D9 to D0:
A/D conversion
end channel
selection bit
−
• The A/D conversion results are stored and the register is rewritten each time conversion
ends.
• Usually, the last conversion value is stored.
• The initial value of this register is undefined.
Note:
The conversion data protection function is provided. (See Section "18.6 Operation of
the 8/10-Bit A/D Converter") Do not write data to these bits during A/D conversion.
Notes:
• To rewrite the S10 bit, do so while the A/D is in a pause before conversion. If the bit is rewritten
after the conversion, the contents of ADCR0,ADCR1 become undefined.
• To read the contents of the ADCR0,ADCR1 register in 10-bit mode, use a word transfer
instruction (MOVW A, 002EH, etc.).
293
CHAPTER 18 8/10-BIT A/D CONVERTER
18.5
8/10-Bit A/D Converter Interrupts
The 8/10-bit A/D converter can generate an interrupt request when the data for the A/D
conversion is set in the A/D data register. This function supports the extended
intelligent I/O service (EI2OS).
■ 8/10-bit A/D Converter Interrupts
Table 18.5-1 Interrupt Control Bits of the 8/10-bit A/D Converter and the Interrupt Cause
8/10-bit A/D converter
Interrupt request flag bit
ADCS: INT
Interrupt request enable bit
ADCS: INTE
Interrupt cause
Writing the A/D conversion result to the A/D data register
When A/D conversion is performed and its result is set in the A/D data register (ADCR), the INT bit of the
A/D control status register (ADCS1) is set to "1". If the interrupt request is enabled (ADCS1: INTE = 1), an
interrupt request is output to the interrupt controller.
■ 8/10-bit A/D Converter Interrupts and EI2OS
Table 18.5-2 8/10-bit A/D Converter Interrupts and EI2OS
Interrupt control register
Interrupt No.
#31 (1FH)
Vector table address
EI2OS
Register
name
Address
Lower
Upper
Bank
ICR10
0000BAH
FFFF80H
FFFF81H
FFFF82H
❍
❍: Available
■ EI2OS Function of the 8/10-bit A/D Converter
Using the EI2OS function, the 10-bit A/D converter can transfer the A/D conversion result to memory.
When the transfer is performed, a conversion data protection function halts the A/D conversion until the A/D
conversion data is transferred to memory, and clears the INT bit. The function prevents any part of the data
from being lost.
294
CHAPTER 18 8/10-BIT A/D CONVERTER
18.6
Operation of the 8/10-Bit A/D Converter
The 8/10-bit A/D converter has three conversion modes: single conversion mode,
continuous conversion mode, and stop conversion mode. This section describes
operation in each mode.
■ Operation in Single Conversion Mode
In single conversion mode, the analog inputs from the channel specified by the ANS bits to the channel
specified by the ANE bits are sequentially converted. When the channels up to the end channel specified by the
ANE bits have been converted, A/D conversion stops. If the start and end channels are the same (ANS = ANE),
just the channel specified by the ANS bits is converted.
The figure below shows the settings required for operation in single conversion mode.
Figure 18.6-1 Settings for Single Conversion Mode
bit15
bit14
ADCS BUSY INT
ADCR
ADER
bit13
bit12
bit11
bit10
bit9
bit8
bit7
INTE PAUS STS1 STS0 STRT RESV MD1
✧
✧
✧
✧
✧
✧
S10
ST1
ST0
CT1
CT0
-
✧
✧
✧
✧
✧
✦
✦
✦
✦
✧
0
✧
bit6
bit5
bit4
bit3
bit2
bit1
bit0
MD0 ANS2 ANS1 ANS0 ANE2 ANE1 ANE0
✧
✧
✧
✧
✧
✧
✧
✦
✦
✦
Holds the conversion data.
ADSEL
✧
✦
✦
✦
✦
✦
✦
✦
✦
✧ : Used during conversion.
✦ : Set the bit that corresponds to the used pin to "1".
0 : Set to "0".
Reference:
The following are sample conversion sequences in single conversion mode:
(It is assumed that ADSEL = 0.)
ANS = 000B, ANE = 011B: AN0 → AN1 → AN2 → AN3 → End
ANS = 110B, ANE = 010B: AN6 → AN7 → AN0 → AN1 → AN2 → End
ANS = 011B, ANE = 011B: AN3 → End
295
CHAPTER 18 8/10-BIT A/D CONVERTER
■ Operation in Stop Conversion Mode
In stop conversion mode, the analog inputs from the channel specified by the ANS bits to the channel
specified by the ANE bits are sequentially converted with a pause after the conversion of each channel.
When the end channel specified by the ANE bits has been processed, A/D conversion, with pauses, starts
again with the channel specified by the ANS bits. If the start and end channels are the same (ANS = ANE),
the conversion of the channel specified by the ANS bits is repeated. To reactivate conversion during a
pause, generate the activation cause specified by the STS1 and STS0 bits.
The settings required for operation in stop conversion mod.
Figure 18.6-2 Settings for Stop Conversion Mode
bit15
bit14
ADCS BUSY INT
ADCR
ADER
bit13
bit12
bit11
bit10
bit9
bit8
bit7
INTE PAUS STS1 STS0 STRT RESV MD1
✧
✧
✧
✧
✧
✧
S10
ST1
ST0
CT1
CT0
-
✧
✧
✧
✧
✧
✦
✦
✦
✦
✧
0
1
bit6
bit5
bit4
bit3
bit2
bit1
bit0
MD0 ANS2 ANS1 ANS0 ANE2 ANE1 ANE0
1
✧
✧
✧
✧
✧
✧
✦
✦
✦
Holds the conversion data.
ADSEL
✧
✦
✦
✦
✦
✦
✦
✦
✦
✧ : Used during conversion.
✦ : Set the bit that corresponds to the used pin to "1".
0 : Set to "0".
1 : Set to "1".
Reference:
The following are sample conversion sequences in stop conversion mode:
(It is assumed that ADSEL = 0.)
ANS = 000B, ANE = 011B:
AN0 → Pause → AN1 → Pause → AN2 → Pause → AN3 → Pause → AN0 → Repeat
ANS = 110B, ANE = 011B:
AN6 → Pause → AN7 → Pause → AN0 → Pause → AN1 → Pause → AN2 → Pause → AN3
→ Pause→ AN6 → Repeat
ANS = 011B, ANE = 011B:
AN3 → Pause → AN3 → Pause → Repeat
296
CHAPTER 18 8/10-BIT A/D CONVERTER
18.6.1
Conversion using EI2OS
The 8/10-bit A/D converter can use EI2OS transfer the A/D conversion result to memory.
■ Conversion Using EI2OS
Figure 18.6-3 shows the sample operation flowchart when EI2OS is used.
Figure 18.6-3 Sample Operation Flowchart when EI2OS is Used.
Start A/D conversion
Sample and hold
EI2OS started
Conversion
Transfer dat a
End conversion
Has the
data transfer been
repeated for the specified
number of times?
(*)
Generate an interrupt
YES
Interrupt processing
NO
Interrupt cleared
*: The number of times is determined by an EI2OS setting.
When EI2OS is used, the conversion data protection function prevents any part of the data from being lost
even in continuous conversion. Multiple data items can be safely transferred to memory.
297
CHAPTER 18 8/10-BIT A/D CONVERTER
18.6.2
A/D conversion data protection function
When A/D conversion is performed in the interrupt enabled state, the conversion data
protection function operates.
■ A/D Conversion Data Protection Function
The A/D converter has just one data register that holds conversion data. When a single A/D conversion is
completed, the data in the data register is rewritten.
If the conversion data were not transferred to memory before the next conversion data was stored, part of
the conversion data would be lost. The data protection function operates in the interrupt enabled state
(INTE = 1), as described below, to prevent loss of data.
● Data protection function when EI2OS is not used
When conversion data is stored in the A/D data register (ADCR), the INT bit of the A/D control status
register1 (ADCS1) is set to "1".
While the INT bit is "1", A/D conversion is halted.
Halt status is released when the INT bit is cleared after data in the A/D data register (ADCR) has been
transferred to memory by the interrupt routine.
● Data protection function when EI2OS is used
In continuous conversion using EI2OS, the PAUS bit of the A/D control status register1 (ADCS1) is kept at
"1" when a conversion ends. This status continues until EI2OS finishes transferring the conversion data
from the data register to memory. In the meantime, the A/D conversion is halted, and the next conversion
data is not stored. When the data transfer to memory is completed, conversion resumes, but once PAUS bit
is set, it is not cleared by itself, write "0" to clear PAUS bit.
Figure 18.6-3 shows operation flowchart of the data protection function when EI2OS is used.
298
CHAPTER 18 8/10-BIT A/D CONVERTER
Figure 18.6-4 Operation Flowchart of the Data Protection Function when EI2OS is Used
Set EI2OS
Start continuous A/D
conversion
End first conversion
Store data in the data
register
Activate EI2OS
End second conversion
Has EI2OS
ended?
NO
Halt A/D
YES
Store data in the data
register
Third conversion
Activate EI2OS
Continue
Terminate all conversions
Continue
Store data in the data
register
Activate EI2OS
Interrupt processing routine
Initialize or stop A/D
End
Note: The steps while the A/D converter is halted are omitted.
Notes:
• The conversion data protection function operates only in the interrupt enabled state (ADCS1:
INTE = 1).
• If interrupts are disabled during a pause in A/D conversion while EI2OS is operating, A/D
conversion may start again. This will cause new data to be written before the old data is
transferred. Reactivation attempted during a pause will cause the old data to be destroyed.
• Reactivation attempted during a pause will destroy the standby data.
299
CHAPTER 18 8/10-BIT A/D CONVERTER
18.7
Notes on the 8/10-Bit A/D Converter
Notes on using the 8/10-bit A/D converter.
■ Usage Notes on the 8/10-bit A/D Converter
● Analog input pin
The A/D input pins are also used as the I/O pins of ports 6 and B. The corresponding Data Direction
Register (DDR6 and DDRB) and the Analog Input Enable Register (ADER) determine which pin is used
for which purpose.
To use a pin as analog input, write "0" to the corresponding bit of DDR6, resp. of DDRB, and thereby
change the port setting to input. Then, set the analog input mode (ADEx = 1) in the ADER register and
determine the input gate of the port.
If an intermediate-level signal is input in the port input mode (ADEx = 0), a leakage current flows through
the gate.
● Note on using an internal timer
To start the A/D converter with an internal timer, set the STS1 and STS0 bits of A/D control status register
1 (ADCS1) accordingly. Set the input value of the internal timer at the inactive level ("L" for the internal
timer). Otherwise, operation may start concurrently with writing to the ADCS register.
● Sequence of turning on the A/D converter and analog input
Do not turn on power to the A/D converter (AVCC, AVRH, AVRL) and to the analog inputs (AN0 to AN7)
before the digital power supply (VCC) has been turned on.
Do not turn off the digital power supply (VCC) before power to the A/D converter and the analog inputs has
been turned off.
● Supply voltage to the A/D converter
The supply voltage to the A/D converter (AVCC) must not exceed the digital power supply (VCC);
otherwise, latch-up may occur.
300
CHAPTER 18 8/10-BIT A/D CONVERTER
18.8
Sample Program 1 for the 8/10-Bit A/D Converter (Single
Conversion Mode Using EI2OS)
This section contains a sample program for A/D conversion in single conversion mode
using EI2OS.
■ Sample Program for Single Conversion Mode Using EI2OS
● Processing
• Analog inputs AN1 to AN3 are converted once.
• The conversion data is sequentially transferred to addresses "200H" to "205H".
• A resolution of 10 bits is selected.
• The conversion is activated by software.
Figure 18.8-1 Flowchart of Program Using EI2OS (Single Conversion Mode)
Start conversion
AN1
Interrupt
Transfer by EI 2OS
AN12
Interrupt
Transfer by EI 2OS
AN13
Interrupt
Transfer by EI 2OS
End
Interrupt sequence
Parallel processing
301
CHAPTER 18 8/10-BIT A/D CONVERTER
● Coding example
BAPL
EQU
000100H
;Lower buffer address pointer
BAPM
EQU
000101H
;Intermediate buffer address pointer
BAPH
EQU
000102H
;Upper buffer address pointer
ISCS
EQU
000103H
;EI2OS status register
IOAL
EQU
000104H
;Lower I/O address register
IOAH
EQU
000105H
;Upper I/O address register
DCTL
EQU
000106H
;Lower data counter
DCTH
EQU
000107H
;Upper data counter
DDR6
EQU
000016H
;Port 6 direction register
ADER0
EQU
00000CH
;Analog input enable register
ICR10
EQU
0000BAH
;Interrupt control register for A/D Converter
ADCS0
EQU
000034H
;A/D control status register
ADCS1
EQU
000035H
;
ADCR0
EQU
000036H
;A/D data register
ADCR1
EQU
000037H
;
;-----Main program--------------------------------------------------------------CODE
CSEG
START:
;Assumes that the stack pointer (SP) has already
;been initialized.
AND
CCR,#0BFH
;Disables interrupts.
MOV
ICR10,#00H
;Interrupt level: 0 (highest priority)
MOV
BAPL,#00H
;Sets the address to which the conversion data is
;transferred and stored.
MOV
BAPM,#02H
;(Uses 200H to 205H.)
MOV
BAPH,#00H
;
MOV
ISCS,#18H
;Transfers word data, adds 1 to the address,
; then transfers the data from I/O to memory.
MOV
IOAL,#36H
;Sets the address of the analog data register as
MOV
IOAH,#00H
;the transfer source address pointer.
MOV
DCTL,#03H
;Sets the EI2OS transfer count to three, which is
;the same value as the conversion count.
MOV
DDR6,#11110001B ;Sets P61 to P63 as input.
MOV
ADER0,#00001110B ;Sets P61/AN1 to P63/AN3 as analog inputs.
MOV
CTH,#00H
;
MOV
ADCS0,#0BH
;Single activation. Converts AN1 to AN3.
MOV
ADCS1,#0A2H
;Software activation. Begins A/D conversion.
;Enables interrupts.
MOV
ILM,#07H
;Sets ILM in PS to level 7.
OR
CCR,#40H
;Enables interrupts.
LOOP:
MOV
MOV
BRA
302
A,#00H
A,#01H
LOOP
;Endless loop
CHAPTER 18 8/10-BIT A/D CONVERTER
;-----Interrupt program---------------------------------------------------------ED_INT1:
MOV
I:ADCS1,#00H
;Stops A/D conversion. Clears and disables the
;interrupt flag.
RETI
;Returns from interrupt.
CODE
ENDS
;-----Vector setting------------------------------------------------------------VECT
CSEG
ABS=0FFH
ORG
0FFB4H
;Sets vector for interrupt #18 (12H)
DSL
ED_INT1
ORG
0FFDCH
; Sets reset vector.
DSL
START
DB
00H
; Sets single-chip mode.
VECT
ENDS
END
START
303
CHAPTER 18 8/10-BIT A/D CONVERTER
18.9
Sample Program 2 for the 8/10-Bit A/D Converter
(Continuous Conversion Mode Using EI2OS)
This section contains a sample program for A/D conversion in continuous conversion
mode using EI2OS.
■ Sample Program for Continuous Conversion Mode Using EI2OS
● Processing
• Analog inputs AN3 to AN5 are converted twice. Two conversion data items are obtained for each
channel.
• The conversion data is sequentially transferred to addresses "600H" to "60BH".
• A resolution of 10 bits is selected.
• The conversion is activated by 16-bit reload timer 1.
Figure 18.9-1 Flowchart of Program Using EI2OS (Continuous Conversion Mode)
Start conversion
AN3
Interrupt
Transfer by EI 2OS
AN4
Interrupt
Transfer by EI 2OS
AN5
Interrupt
Transfer by EI 2OS
After a total of
six transfers
Interrupt sequence
End
304
CHAPTER 18 8/10-BIT A/D CONVERTER
● Coding example
BAPL
BAPM
BAPH
ISCS
IOAL
IOAH
DCTL
DCTH
DDR6
ADER0
ICR10
ADCS0
ADCS1
ADCR0
ADCR1
TMCSR1L
TMCSR1H
TMRL1L
TMRL1H
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
000100H
000101H
000102H
000103H
000104H
000105H
000106H
000107H
000016H
00000CH
0000BAH
000034H
000035H
000036H
000037H
000068H
000069H
003902H
003903H
;Lower buffer address pointer
;Middle buffer address pointer
;Upper buffer address pointer
;EI2OS status register
;Lower I/O address register
;Upper I/O address register
;Lower data counter
;Upper data counter
;Port 6 direction register
;Analog input enable register
;Interrupt control register for A/D Converter
;A/D control status register
;
;A/D data register
;
;Lower control status register 1
;
;16-bit reload register 1
;
;-----Main program--------------------------------------------------------------CODE
START:
AND
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOVW
MOV
CSEG
;Assumes that the stack pointer (SP) has already
;been initialized.
CCR,#0BFH
;Disables interrupts.
ICR10,#08H
;Interrupt level: 0 (highest priority).Enables EI2OS when
;interrupt
BAPL,#00H
;Sets the address to which the conversion data is stored.
BAPM,#06H
;(Uses 600H to 60BH.)
BAPH,#00H
;
ISCS,#18H
;Transfers word data, adds 1 to the address, then
;transfers from I/O to memory.
IOAL,#36H
;Sets the address of the analog data register as the
IOAH,#00H
;transfer source address pointer.
DCTL,#06H
;Six transfer by EI2OS (two transfers each for three
;channels.)
DDR6,#00000000B ;Sets P60 to P67 as input.
ADER0,#00111000B ;Sets P63/AN3 to P65/AN5 as analog input.
DCTH,#00H
;
ADCS0,#9DH
;Continuous conversion mode. Converts AN3 to AN5.
ADCS1,#0A8H
;Activates the 16-bit timer, starts A/D conversion, and
;enables interrupts.
TMRL1L,#0320H
;Sets the timer value to 800(320H),100 s.
TMCSR1H,#00H
;Sets the clock source to 125 ns and disables
;external trigger.
MOV
TMCSR1L,#12H
MOV
MOV
OR
TMCSR1L,#13H
ILM,#07H
CCR,#40H
;Disables timer output, disables interrupts, and
;enables reload.
;Activates the 16-bit timer.
;Sets ILM in PS to level 7.
;Enables interrupts.
305
CHAPTER 18 8/10-BIT A/D CONVERTER
LOOP:
MOV
MOV
BRA
A,#00H
A,#01H
LOOP
;Endless loop
;-----Interrupt program---------------------------------------------------------ED_INT1:
MOV
I:ADCS1,#80H
;Does not stop A/D conversion. Clears and disables
;the interrupt flag.
RETI
;Returns from interrupt.
CODE
ENDS
;-----Vector setting------------------------------------------------------------VECT
CSEG
ABS=0FFH
ORG
0FFB4H
;Sets vector for interrupt #18 (12H).
DSL
ED_INT1
ORG
0FFDCH
;Sets reset vector.
DSL
START
DB
00H
;Sets single-chip mode.
VECT
ENDS
END
START
306
CHAPTER 18 8/10-BIT A/D CONVERTER
18.10
Sample Program 3 for the 8/10-Bit A/D Converter (Stop
Conversion Mode Using EI2OS)
This section contains a sample program for A/D conversion in stop conversion mode
using EI2OS.
■ Sample Program for Stop Conversion Mode Using EI2OS
● Processing
• Analog input AN3 is converted 12 times at regular intervals.
• The conversion data is sequentially transferred to addresses "600H" to "617H".
• A resolution of 10 bits is selected.
• The conversion is activated by 16-bit reload timer.
Figure 18.10-1 Flowchart of Program Using EI2OS (Stop Conversion Mode)
Start conversion
AN3
Interrupt
Transfer by EI 2OS
Stop
Activation by 16-bit reload timer 1
After 12 transfers
Interrupt sequence
End
307
CHAPTER 18 8/10-BIT A/D CONVERTER
● Coding example
BAPL
BAPM
BAPH
ISCS
IOAL
IOAH
DCTL
DCTH
DDR6
ADER0
ICR10
ADCS0
ADCS1
ADCR0
ADCR1
TMCSR1L
TMCSR1H
TMRL1L
TMRL1H
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
000100H
000101H
000102H
000103H
000104H
000105H
000106H
000107H
000016H
00000CH
0000BAH
000034H
000035H
000036H
000037H
000068H
000069H
003902H
003903H
;Lower buffer address pointer
;Middle buffer address pointer
;Upper buffer address pointer
;EI2OS status register
;Lower I/O address register
;Upper I/O address register
;Lower data counter
;Upper data counter
;Port 6 direction register
;Analog input enable register
;Interrupt control register for A/D Converter
;A/D control status register
;
;A/D data register
;
;Lower control status register 1
;
;16-bit reload register 1
;
;-----Main program--------------------------------------------------------------CODE
CSEG
START:
;Assumes that the stack pointer (SP) has already
;been initialized.
AND
CCR,#0BFH
;Disables interrupts.
MOV
ICR10,#08H
;Interrupt level: 0 (highest priority) + EI2OS.
MOV
BAPL,#00H
;Sets the address to which conversion data is stored.
MOV
BAPM,#06H
;(Uses 600H to 617H.)
MOV
BAPH,#00H
;
MOV
ISCS,#19H
;Transfers word data, adds 1 to the address,
;transfers from I/O to memory, then ends by a
;resource request.
MOV
IOAL,#36H
;Sets the address of the analog data register as the
MOV
IOAH,#00H
;transfer source address pointer.
MOV
DCTL,#0CH
;Transfers only channel 3 twelve times by EI2OS
MOV
DDR6,#00000000B ;Sets P60 to P67 as input.
MOV
ADER0,#00001000B ;Sets P63/AN3 as analog input.
MOV
ADCS0,#0DBH
;Stop conversion mode. Converts AN3 CH.
MOV
ADCS1,#0A8H
;Activates the 16-bit timer, starts A/D conversion,
;and enables interrupts.
MOVW
TMRL1L,#0320H
;Sets the timer value to 800 (320H), 100 ?s.
MOV
TMCSR1H,#00H
;Sets the clock source to 125 ns and disables
;external trigger.
MOV
TMCSR1L,#12H
;Disables timer output, disables interrupts, and
;enables reload.
MOV
TMCSR1L,#13H
;Activates the 16-bit timer.
MOV
ILM,#07H
;Sets ILM in PS to level 7.
OR
CCR,#40H
;Enables interrupts.
LOOP:
MOV
A,#00H
;Endless loop
MOV
A,#01H
BRA
LOOP
308
CHAPTER 18 8/10-BIT A/D CONVERTER
;-----Interrupt program---------------------------------------------------------ED_INT1:
MOV
I:ADCS1,#80H
;Does not stop A/D conversion. Clears and disables
;the interrupt flag.
RETI
;Returns from interrupt.
CODE
ENDS
;-----Vector setting------------------------------------------------------------VECT
CSEG
ABS=0FFH
ORG
0FFB4H
;Sets vector for interrupt #18 (12H).
DSL
ED_INT1
ORG
0FFDCH
;Sets reset vector.
DSL
START
DB
00H
;Sets single-chip mode.
VECT
ENDS
END
START
309
CHAPTER 18 8/10-BIT A/D CONVERTER
310
CHAPTER 19
UART0, UART1
This chapter explains the UART0, UART1 functions and
operations.
Note: UART2 is not specified in the MB90390 series. For
this reason Fujitsu recommends not to use this feature.
19.1 Features of UART0, UART1
19.2 UART0, UART1 Block Diagram
19.3 UART0, UART1 Registers
19.4 UART0, UART1 Operation
19.5 Baud Rate
19.6 Internal and External Clock
19.7 Transfer Data Format
19.8 Parity Bit
19.9 Interrupt Generation and Flag Set Timings
19.10 UART0, UART1 Application Example
311
CHAPTER 19 UART0, UART1
19.1
Features of UART0, UART1
The UART0, UART1 are serial I/O ports for asynchronous or CLK synchronous
communication. The MB90390 Series contains four UARTs. For UART2 and UART3 see
"CHAPTER 20 UART2, UART3".
■ Feature of UART0, UART1
UART0, UART1 have the following features each.
• Full duplex double buffer
• Supports CLK synchronous and CLK asynchronous start-stop data transfer.
• Multiprocessor mode support (mode 2)
• Internally dedicated baud rate generator (12 types)
• Supports flexible baud rate setting using an external clock input or internal timer.
• Variable data length (7 bit to 9 bit, [no parity]; 6 bit to 8 bit [with parity]).
• Error detect function (framing, overrun, and parity)
• Interrupt function (receive and transmit interrupts) Error detect function (framing, overrun, and parity)
• NRZ type transfer format
312
CHAPTER 19 UART0, UART1
19.2
UART0, UART1 Block Diagram
Figure 19.2-1 shows the UART0, UART1 block diagram.
■ UART0, UART1 Block Diagram
Figure 19.2-1 UART0, UART1 Block Diagram
CONTROL BUS
Receive interrupt
(to CPU)
Dedicated baud rate clock
SCK0
Tr ansmit clock
16-bit reload timer 0
Clock select
circuit
Tr ansmit interrupt
(to CPU)
Receive clock
SCK0
SIN0
Receive control circuit
Tr ansmit control circuit
Start bit detect
circuit
Tr ansmit start circuit
Receive bit counter
Tr ansmit bit counter
Receive parity
counter
Tr ansmit parity
counter
SOT0
Receive status
evaluation circuit
Tr ansmit shifter
Receive shifter
Receive
complete
Tr ansmit start
UIDR
UODR
Receive error
indication signal
for EI2OS (to CPU)
Data bus
UMC
register
PEN
SBL
MC1
MC0
SMDE
RFC
SCKE
SOE
USR
register
RDRF
ORFE
PE
TDRE
RIE
TIE
RBF
TBF
URD
register
BCH
RC3
RC2
RC1
RC0
BCH0
P
D8
CONTROL BUS
Note: this diagram is valid for UART0, UART1
313
CHAPTER 19 UART0, UART1
19.3
UART0, UART1 Registers
The UART0, UART1 have the following four registers each:
• Serial mode control register
• Status register
• Input data register/output data register
• Rate and data register
■ UART0, UART1 Registers
Serial mode control register
Address: ch.0 000020H
ch.1 000024H
7
6
PEN
SBL
(R/W)
(0)
(R/W)
(0)
bit
Read/write
Initial value
Status register
Address: ch.0 000021H
ch.1 000025H
bit
Read/write
Initial value
Input data register/
Output data register
Address: ch.0 000022H
ch.1 000026H
Read/write
Initial value
314
4
MC1
MC0
(R/W)
(0)
3
2
1
0
SMDE
RFC
SCKE
SOE
(R/W)
(0)
(W)
(1)
(R/W)
(0)
(R/W)
(0)
14
13
12
11
10
9
8
RDRF
ORFE
PE
TDRE
RIE
TIE
RBF
TBF
(R)
(0)
(R)
(0)
(R)
(1)
(R/W)
(0)
(R/W)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
USR0
USR1
7
6
5
4
3
2
1
0
D7
D6
D5
D4
D3
D2
D1
D0
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
bit
15
14
13
12
11
10
9
8
BCH
RC3
RC2
RC1
RC0
BCH0
P
D8
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
UMC0
UMC1
(R/W)
(0)
15
Read/write
Initial value
Rate and data register
bit
Address: ch.0 000023H
ch.1 000027H
5
(R/W)
(X)
UIDR0(read)
UODR0(write)
UIDR1(read)
UODR1(write)
URD0
URD1
CHAPTER 19 UART0, UART1
19.3.1
Serial Mode Control Register (UMC)
UMC specifies the operation mode of UART0, UART1. Set the operation mode while
operation is halted. However, the RFC bit can be accessed during operation.
■ Serial Mode Control Register (UMC)
Figure 19.3-1 Configuration of the Serial Mode Control Register (UMC)
Address: bit 7
ch.0 000020H
ch.1 000024H
6
5
4
3
2
1
0
R/W R/W R/W R/W R/W W R/W R/W
UMC0 UMC1
Initial value
00000100B
bit0
SOE
Serial Output enable
0
disable SOT0,SOT1 pin (hi-Z)
1
enable SOT0,SOT1 pin (TxData)
bit1
SCKE
Serial Clock Output enable
0
External Serial Clock Input
1
Internal Serial Clock Output
bit2
Receiver Flag Clear
RFC
write
read
0
clear RDRF , ORFE, PE
1
no effect
bit3
SMDE
0
1
bit5
always "1"
Synchro mode enable
Start-Stop-CLK synchronous transfer
Asynchronous Transfer
bit4
MC1
MC0
0
0
Mode 0: Asynchronous, 7(6) data bits
Operation Mode Setting
0
1
Mode 1: Asynchronous, 8(7) data bits
1
0
Mode 2: Async. Multiprocessor, 8+1 data bits
1
1
Mode 3: Asynchronous, (9)8 data bits
bit6
SBL
Stop bit length
0
1 bit
1
2 bit
bit7
PEN
R/W
:
Readable and writable
W
:
Write only (read returns always "0")
:
Initial value
Parity enable
0
Do not use parity
1
Use parity
315
CHAPTER 19 UART0, UART1
■ Serial Mode Control Register (UMC) Contents
Table 19.3-1 Function of Each Bit of the Serial Control Register
Bit name
Function
bit7
PEN:
Parity enable
Specifies whether to add (for transmit) or detect (for receive) a parity bit in serial data I/O. Set to "0"
in mode 2.
"0": Do not use parity
"1": Use parity
bit6
SBL:
stop bit length
Specifies the number of stop bits for transmit data. For receive data, the first stop bit only is
recognized and any second stop bit is ignored.
"0": 1 bit length
"1": 2 bits length
These bits control the length of the transferred data. Table 19.4-1 lists the four transfer modes (data
lengths) selectable by these bits.
bit5,
bit4
MC1, MC0:
Mode control bits
Mode
MC1
MC0
Data Length
0
0
0
7 (6)
1
0
1
8 (7)
2
1
0
8+1
3
1
1
9 (8)
The figures enclosed in parentheses indicate the data length with parity.
"+1" means Address/Data-Bit instead of parity
SMDE:
Synchro mode enable
This bit selects the transfer method.
"0": Start-stop CLK synchronous transfer (clocked synchronous transfer using start and stop bits.)
"1": Start-stop CLK asynchronous transfer
RFC:
Receiver flag clear
Writing "0" to this bit clears the RDRF, ORFE, and PE flags in the USR register. Writing "1" has no
effect. Reading always returns "1".
Note:
When receive interrupts are enabled during UART0, UART1 operation, only write "0" to RFC
when either RDRF, ORFE, or PE is "1".
bit1
SCKE:
SCLK enable
Writing "1" to this bit in CLK synchronous mode switches the port pin to the UART0, 1 serial clock
output pin and outputs the synchronizing clock. Set to "0" in CLK asynchronous mode or external
clock mode.
"0": The pin functions as a general purpose I/O port and does not output the serial clock. The pin
functions as the external clock input pin when the port is set to input mode (DDR=0) and RC3
to RC0 are set to "1111B".
"1": The pin functions as the UART0, UART1 serial clock output pin.
bit0
SOE:
Serial output enable
Writing "1" to this bit switches the port pin to the UART0, UART1 serial data output pin and
enables serial output.
"0": The pin functions as a port pin and does not output serial data.
"1": The pin functions as the UART0, UART1 serial data output pin (SOT).
bit3
bit2
316
CHAPTER 19 UART0, UART1
19.3.2
Status Register (USR)
USR indicates the current state of the UART0, UART1 port.
■ Status Register (USR)
Figure 19.3-2 Configuration of the Status Register (USR)
Address:
bit 15 14 13 12 11 10
ch.0 000021H
RDRF ORFE PE TDRE RIE TIE
ch.1 000025H
R
R
R
9
8
USR0 USR1
RBF
TBF
R R/W R/W R
R
Initial value
0 0 0 1 0 0 0 0B
bit8
TBF
Transmission busy flag bit
0
Transmitter idle
1
Transmitter busy
bit9
RBF
Receiver busy flag bit
0
Receiver idle
1
Receiver busy
bit10
TIE
Transmission interrupt enable bit
0
Disable interrupt
1
Enable interrupt
bit11
RIE
Reception interrupt enable bit
0
Disable interrupt
1
Enable interrupt
bit12
TDRE
Transmission data register empty bit
0
Data present in UODR0, UODR1
1
No data in UODR0, UODR1
bit13
PE
Parity error bit
0
No parity error occurred
1
Parity error occurred
bit14
ORFE
Overrun/Framing error bit
0
No overrun/framing error occurred
1
An overrun/framing error occurred during reception
bit15
RDRF
R/W
:
Readable and writable
R
:
Flag is read only, write to it has
no effect
:
Initial value
Reception data register full
0
No data in UIDR0, UIDR1
1
Data present in UIDR0, UIDR1
317
CHAPTER 19 UART0, UART1
■ Status Register (USR) Contents
Table 19.3-2 Function of Each Bit of the Status Register
Bit name
bit15
bit14
RDRF:
Receiver Data
Register full bit
ORFE:
Overrun/Framing
Error bit
Function
This flag indicates the state of the UIDR (input data register). The flag is set when the receive data is
loaded into UIDR. Reading UIDR or writing "0" to RFC in the UMC register clears the flag. If RIE
is active, a receive interrupt request is generated when RDRF is set.
"0": No data in UIDR
"1": Data present in UIDR
The flag is set when an overrun or framing error occurs in receiving. Writing "0" to RFC in the
UMC register clears the flag. When this flag is set, the data in UIDR is invalid and the load from the
receive shifter to UIDR is not performed. If RIE is active, a receive interrupt request is generated
when ORFE is set.
"0": No error
"1": Error (see table below)
RDRF
0
0
1
1
ORFE
0
1
0
1
UIDR0, UIDR1 State
Empty
Framing error
Vaild data
Overrun error
bit13
PE:
Parity error bit
The flag is set when a receive parity error occurs. Writing "0" to RFC in the UMC register clears the
flag. When this flag is set, the data in UIDR is invalid and the load from the receive shifter to UIDR
is not performed. If RIE is active, a receive interrupt request is generated when PE is set.
"0": No parity error
"1": Parity error
bit12
TDRE:
Transmission Data
Register empty bit
This flag indicates the state of the UODR (output data register). Writing transmit data to the UODR
register clears the flag. The flag is set when the data is loaded to the transmit shifter and the
transmission is started. If TIE is active, a transmit interrupt request is generated when TDRE is set.
"0": Data present in UODR
"1": No data in UODR
bit11
RIE:
Reception interrupt
enable bit
Enables receive interrupt requests.
"0": Disable interrupts.
"1": Enable interrupts.
bit10
TIE:
Transmission
interrupt enable bit
Enables transmit interrupt requests. A transmit interrupt is generated immediately if transmit
interrupts are enabled when TDRE is "1".
"0": Disable interrupts.
"1": Enable interrupts.
bit9
RBF:
Receiver Busy Flag
bit
This flag indicates that UART0, UART1 is receiving input data. The flag is set when the start bit is
detected and cleared when the stop bit is detected.
"0": Receiver idle
"1": Receiver busy
bit8
TBF:
Transmitter Busy
Flag bit
This flag indicates that UART0, UART1 is transmitting input data. The flag is set when transmit
data is written to the UODR register and cleared when transmission completes.
"0": Transmitter idle
"1": Transmitter busy
318
CHAPTER 19 UART0, UART1
19.3.3
Input Data Register (UIDR) and Output Data Register
(UODR)
UIDR (input data register) is the serial data input register. UODR (output data register) is
the serial data output register.
The most significant two bits (D7 and D6) are ignored if the data length is 6 bits and the
most significant bit (D7) is ignored if the data length is 7 bits. Write to UODR only when
TDRE = 1 in the USR register. Read UIDR only when RDRF = 1 in the USR register.
■ Input Data Register (UIDR) and Output Data Register (UODR)
Figure 19.3-3 Input Data Register (UIDR) and Output Data Register (UODR)
Address:
bit
ch.0 000022 H
ch.1 000026 H
7
6
5
4
3
2
1
0
R/W R/W R/W R/W R/W R/W R/W R/W
Initial value
X X X X X X X XB
bit 7 to bit 0
Read/Write
R/W
:
Readable and writable
Data Registers
Read
Read from Input Data Register
Write
Write to Output Data Register
319
CHAPTER 19 UART0, UART1
19.3.4
Rate and Data Register (URD)
URD selects the data transfer speed (baud rate) for UART0, UART1. The register also
holds the most significant bit (bit8) of the data when the transmit data length is 9 bits.
Set the baud rate and parity when UART0, UART1 is halted.
■ Rate and Data Register (URD)
Figure 19.3-4 Configuration of the Rate and Data Register (URD)
Address:
bit 15
ch.0 000023 H
ch.1 000027 H
14
13
12
11
10
9
8
R/W R/W R/W R/W R/W R/W R/W R/W
URD0 URD1
Initial value
0 0 0 0 0 0 0 XB
bit8
D8
X
UIDRn/UODRn Data bit 8
read/write
bit9
P
Parity bit
0
Even parity
1
Odd parity
bit10
BCH0
-
Baud Rate Clock Change 1
see description for details
bit14 to bit11
RC3 to RC0
-
Rate Control
see description for details
bit15
BCH
R/W
320
:
Readable and writable
:
Initial value
-
Baud Rate Cloc
see description for details
CHAPTER 19 UART0, UART1
■ Rate and Data Register (URD) Contents
Table 19.3-3 Function of Each Bit of the Rate and Data Register
Bit name
Function
Specifies the machine cycles for the baud rate clock (see Section "19.4 UART0,
UART1 Operation" for details).
bit15,
bit10
BCH, BCH0:
Baud rate clock
change bits
BCH
BCH0
0
0
1
0
1
0
Divider
ratio
6
4
3
1
1
5
Setting example for different Machine Cycles
For 24 MHz: 24/6 = 4 MHz
For 16 MHz: 16/4 = 4 MHz
For 12 MHz: 12/3 = 4 MHz
For 20 MHz: 20/5 = 4 MHz;
For 10 MHz: 10/5 = 2 MHz
Selects the clock input for the UART0, UART1 port (see Section "19.4 UART0,
UART1 Operation" for details).
bit14 to
bit11
RC3, RC2, RC1,
RC0
RC3 to
RC0
0000B
to
1011B
1101B
1111B
Clock Input
Dedicated baud rate generator
16-bit Reload Timer 0
External Clock
bit9
P:
Parity bit
Sets even or odd parity when parity is active (PEN = 1).
"0": Even parity
"1": Odd parity
bit8
D8:
UIDRn/UODRn
data bit 8
Holds the bit8 of the transfer data in mode 2 or 3 (9-bit data length) and no parity.
Treated as bit8 of the UIDR register for reading. Treated as bit8 of the UODR register
for writing. The bit has no meaning in the other modes. Write to D8 only when TDRE = 1
in the USR register.
321
CHAPTER 19 UART0, UART1
19.4
UART0, UART1 Operation
Table 19.4-1 lists the operating modes for UART0, UART1. Set the UMC register to
switch between modes.
■ UART0, UART1 Operation Modes
Table 19.4-1 UART0, UART1 Operating Modes
Mode
Parity
Data Length
ON
6
OFF
7
ON
7
OFF
8
OFF
8+1
ON
8
OFF
9
Clock Mode
Length of Stop Bits *
CLK asynchronous or
CLK synchronous
1 bit or 2 bits
0
1
2
3
*: The number of stop bits can only be set for transmission. The number of receive stop bits is always set to one. Do not
set modes other than those listed above. UART0, UART1 does not operate if an invalid mode is set.
Note:
UART0, UART1 uses start-stop clock synchronous transfer. Therefore, a start and stop bit are added
to the data even in clock synchronous transfer.
322
CHAPTER 19 UART0, UART1
19.5
Baud Rate
When the dedicated baud rate generator is used, the following two types of baud rates
are available:
• CLK synchronous baud rate
• CLK asynchronous baud rate
■ CLK Synchronous Baud Rate
The five URD register bits: BCH, BCH0 and RC3, RC2, RC1 select the baud rate for CLK synchronous
transfer.
First select the machine clock divider ratio using BCH and BCH0.
BCH BCH0
0
0
-->
Divide by 6 [For example, at 24 MHz: 24/6 = 4 MHz]
0
1
-->
Divide by 4 [For example, at 16 MHz: 16/4 = 4 MHz]
1
0
-->
Divide by 3 [For example, at 12 MHz: 12/3 = 4 MHz]
1
1
-->
Divide by 5 [For example, at 20 MHz: 20/5 = 4 MHz]
Then, set the division ratio for the clock selected above in RC3, RC2, RC1, and RC0. The following three
settings are available for CLK synchronous transfer. Other settings are prohibited.
RC3 RC2 RC1 RC0
0
1
0
1 -->
Divide by 2 [For example, at 4 MHz: 4/2 = 2.0 Mbps]
0
1
1
1 -->
Divide by 4 [For example, at 4 MHz: 4/4 = 1.0 Mbps]
1
0
0
1 -->
Divide by 8 [For example, at 4 MHz: 4/8 = 0.5 Mbps]
(At 2 MHz, the speed becomes half the above examples.)
323
CHAPTER 19 UART0, UART1
■ CLK Asynchronous Baud Rate
The six URD register bits: BCH, BCH0 and RC3, RC2, RC1, RC0 select the baud rate for CLK
asynchronous transfer.
First select the machine clock divider ratio using BCH and BCH0.
BCH BCH0
0
0
-->
Divide by 6 [For example, at 24 MHz: 24/6 = 4 MHz]
0
1
-->
Divide by 4 [For example, at 16 MHz: 16/4 = 4 MHz]
1
0
-->
Divide by 3 [For example, at 12 MHz: 12/3 = 4 MHz]
1
1
-->
Divide by 5 [For example, at 10 MHz: 10/5 = 2 MHz]
Then, set the asynchronous transfer clock division ratio for the clock selected above in RC3, RC2, RC1,
and RC0. The following settings are available.
Baud rate =
Baud rate =
Baud rate =
/6
2m-1
/4
2m-1
/3
2m-1
/5
Baud rate =
2
m-1
[bps] (machine cycle = 24 MHz)
[bps] (machine cycle = 16 MHz)
[bps] (machine cycle = 12 MHz)
[bps] (machine cycle = 20 (10) MHz)
The above 12 baud rates can be selected. The following formula shows how to calculate the CLK
synchronous baud rate.
Baud rate =
/6
2m-1
/4
Baud rate =
m-1
[bps] (machine cycle = 24 MHz)
[bps] (machine cycle = 16 MHz)
2
/3
Baud rate =
2
m-1
2
m-1
/5
Baud rate =
[bps] (machine cycle = 12 MHz)
[bps] (machine cycle = 20 (10) MHz)
where φ is a machine cycle and m is in decimal notation for RC3 to RC1.
Note:
The above formula for m=0 or m=1 cannot be calculated.
Data transfer is possible if the CLK asynchronous baud rate is in the range -1% to +1%. The baud
rate is the CLK synchronous baud rate divided by 8 × 13, 8 × 12, or 8.
Table 19.5-1 shows examples for 24 MHz, 20 MHz, 16 MHz, and 12 MHz machine cycles. However,
do not use the settings marked as "_" in the table.
324
CHAPTER 19 UART0, UART1
Table 19.5-1 Baud Rate
CLK asynchronous (μs/bps)
CLK synchronous (μs/bps)
24 MHz
20 MHz
16 MHz
12 MHz
CLK
asynchronous
divider ratio
24 MHz
20 MHz
16 MHz
12 MHz
BCH/
BCH0=
00B
BCH/
BCH0=
11B
BCH/
BCH0=
01B
BCH/
BCH0=
10B
R
C
3
R
C
2
R
C
1
R
C
0
BCH/
BCH0=
00B
BCH/
BCH0=
11B
BCH/
BCH0=
01B
BCH/
BCH0=
10B
0
0
0
0
-
-
-
-
8 × 12
-
-
-
-
0
0
0
1
26/
38460
26/
38460
26/
38460
26/
38460
8 × 13
-
-
-
-
0
0
1
0
-
-
8
-
-
-
-
0
0
1
1
2/
500000
2/
500000
2/
500000
2/
500000
8
-
-
-
-
0
1
0
0
48/
20833
48/
20833
48/
20833
48/
20833
8 × 12
-
-
-
-
0
1
0
1
52/
19230
52/
19230
52/
19230
52/
19230
8 × 13
0.5 / 2M
0.5 / 2M
0.5 / 2M
0.5 / 2M
0
1
1
0
96/
10417
96/
10417
96/
10417
96/
10417
8 × 12
-
-
-
-
0
1
1
1
104/
9615
104/
9615
104/
9615
104/
9615
8 × 13
1 / 1M
1 / 1M
1 / 1M
1 / 1M
1
0
0
0
192/
5208
192/
5208
192/
5208
192/
5208
8 × 12
-
-
-
-
1
0
0
1
208/
4808
208/
4808
208/
4808
208/
4808
8 × 13
2 / 500K
2 / 500K
2 / 500K
2 / 500K
1
0
1
0
-
-
-
-
8
-
-
-
-
1
0
1
1
16/
62500
16/
62500
16/
62500
16/
62500
8
-
-
-
-
1
1
0
0
-
-
-
-
-
-
-
-
-
1
1
0
1
-
-
-
-
-
-
-
-
-
1
1
1
0
-
-
-
-
-
-
-
-
-
1
1
1
1
-
-
-
-
-
-
-
-
-
325
CHAPTER 19 UART0, UART1
19.6
Internal and External Clock
Setting RC3 to RC0 to "1101B" selects the clock signal from the 16-bit Reload Timer.
Setting RC3 to RC0 to "1111B" selects the external clock.
The external clock frequency has a maximum value of 2 MHz.
■ Internal and External Clock
The CLK asynchronous baud rate is the CLK synchronous baud rate divided by 8. Also, data transfer is
possible if the CLK asynchronous baud rate is in the range -1% to +1% of the selected baud rate. Table
19.6-1 lists the baud rate and reload value. The values in this table are calculated for a machine cycle of
7.3728 MHz. However, do not use the settings marked as "-" in the table.
Baud rate=
φ/X
8 × 2 (n+1)
[bps]
⎛ φ: Machine cycle
⎜
⎜ X: Divider ratio for the count clock source for
⎜
the internal timer
⎜
⎝ n: Reload value (decimal)
⎞
⎟
⎟
⎟
⎟
⎠
Table 19.6-1 Baud Rate and Reload Value
Reload Value
Baud Rate (bps)
X = 21
(divide machine cycle by 2)
X = 23
(divide machine cycle by 8)
76800
2
-
38400
5
-
19200
11
2
9600
23
5
4800
47
11
2400
95
23
1200
191
47
600
383
95
300
767
191
The values in the table are the reload values (decimal) for reload count operation of the 16-bit Reload
Timer.
326
CHAPTER 19 UART0, UART1
19.7
Transfer Data Format
UART0, UART1 only handle NRZ (non-return-to-zero) type data. Figure 19.7-1 shows the
relationship between the transmit/receive clock and the data for CLK synchronous
mode.
■ Transfer Data Format
Figure 19.7-1 Transfer Data Format
SCK0
SIN0, SOT0
0
Start
1
LSB
0
1
1
0
0
1
0
MSB
1
1
⎫
Stop
Depends
D8 Stop ⎬ on the mode.
⎭
The transferred data is "01001101B" (mode 1) or "101001101B" (mode 3).
As shown in Figure 19.7-1, the transfer data always starts with the start bit ("L" level data), the specified
number of data bits are transmitted with the LSB first, then transmission ends with the stop bit ("H" level
data). Always input a clock if external clock operation is selected. When an internal clock (the dedicated
baud rate generator or 16-bit Reload Timer) is selected, the clock is output continuously. When using CLK
synchronous transfer, do not start data transfer until the selected baud rate clock has stabilized (for two
baud rate clock cycles).
When using CLK asynchronous transfer, set the SCKE bit in the UMC0, UMC1 register to "0" to disable
clock output. The transfer data format of SIN0, SIN1 and SOUT0, SOUT1 is the same as shown in Figure
19.7-1.
327
CHAPTER 19 UART0, UART1
19.8
Parity Bit
The P bit in the URD0, URD1 register specifies whether to use even or odd parity when
parity is enabled. The PEN bit in the UMC0, UMC1 register enables parity.
■ Parity Bit
Inputting the data shown in Figure 19.8-1 to SIN when even parity is set causes a receive parity error.
Figure 19.8-1 also shows the data transmitted when sending "001101B" with even parity and odd parity.
Figure 19.8-1 Serial Data with Parity Enabled
SIN0
(Receive parity error occurs P = 0)
0
Start
1
LSB
0
1
1
0
0
MSB
0
1
Stop
(Parity)
SOT0
(Even parity transmission P = 0)
0
Start
1
LSB
0
1
1
0
0
MSB
1
1
Stop
(Parity)
SOT0
(Odd parity transmission P = 1)
0
Start
1
LSB
0
1
1
0
0
MSB
0
(Parity)
328
1
Stop
CHAPTER 19 UART0, UART1
19.9
Interrupt Generation and Flag Set Timings
UART0, UART1 have two interrupt causes and six flags each. The two interrupt causes
are the receive and transmit interrupts. The six flags are RDRF, ORFE, PE, TDRE, RBF,
and TBF. For reception, the RDRF, ORFE, and PE flags request an interrupt. For
transmission, the TDRE flag requests an interrupt.
■ Set Timings of the Six Flags
● RDRF flag
The RDRF flag is set when receive data is loaded into the UIDR register. The flag is cleared by writing "0"
to RFC in the UMC register or by reading the UIDR register.
● ORFE flag
The ORFE flag is an overrun or framing error flag. The flag is set when a receive error occurs and is
cleared by writing "0" to RFC in the UMC register.
● PE flag
The PE flag is a reception parity error flag. The flag is set when a receive parity error occurs and is cleared
by writing "0" to RFC in the UMC register. Note that the parity detect function is not available in mode 2.
● TDRE flag
The TDRE flag is set when the UODR register becomes empty and is available for writing. The flag is
cleared by writing to the UODR register. The above four flags (RDRF, ORFE, PE, and TDRE) trigger
transmit or receive interrupts.
● RBF and TBF flags
The RBF and TBF flags indicate that reception or transmission is in progress. The RBF flag becomes active
during reception, and the TBF flag becomes active during transmission.
329
CHAPTER 19 UART0, UART1
19.9.1
Flag Set Timings for a Receive Operation
(Mode0, Mode1, Mode3)
The RDRF, ORFE, and PE flags are set and an interrupt request to the CPU generated
when the final stop bit is detected indicating the end of reception transfer. The data in
UIDR0, UIDR1 is invalid when either the ORFE or PE bit is active.
■ Flag Set Timings for a Receive Operation (in Mode0, Mode1, Mode3)
Figure 19.9-1 shows the RDRF set timing (mode0, mode1, mode3), Figure 19.9-2 shows the ORFE set
timing (mode0, mode1, mode3), and Figure 19.9-3 show the PE set timing (mode0, mode1, mode3).
Figure 19.9-1 RDRF Set Timing (Mode0, Mode1, Mode3)
Stop
Data
(Stop)
RDRF
Receive interrupt
Figure 19.9-2 ORFE Set Timing (Mode0, Mode1, Mode3)
Data
Stop
Data
RDRF = 1
RDRF = 0
ORFE
ORFE
Receive interrupt
Stop
Receive interrupt
(Overrun error)
(Framing error)
Figure 19.9-3 PE Set Timing (Mode0, Mode1, Mode3)
Data
PE
Receive interrupt
330
Stop
(Stop)
CHAPTER 19 UART0, UART1
19.9.2
Flag Set Timings for a Receive Operation (in Mode 2)
The RDRF flag is set when the final stop bit is detected and reception transfer ends with
the last data bit (D8) having the value "1".
The ORFE flag is set when the final stop bit is detected, irrespective of the value of the
last data bit (D8). The data in UIDR is invalid when the ORFE bit is active.
The interrupt request to the CPU is generated when either of the flags are set (see
Section "19.10 UART0, UART1 Application Example" for details on using mode 2).
■ Flag Set Timings for a Receive Operation (in Mode 2)
Figure 19.9-4 RDRF Set Timing (Mode 2)
Data
D6
D7
D8
Stop
(Stop)
RDRF
Receive interrupt
Figure 19.9-5 ORFE Set Timing (Mode 2)
Data
D7
D8
Stop
Data
RDRF = 1
RDRF = 0
ORFE
ORFE
Receive interrupt
D7
D8
Stop
Receive interrupt
(Overrun error)
(Framing error)
331
CHAPTER 19 UART0, UART1
19.9.3
Flag Set Timings for a Transmit Operation
TDRE is set and an interrupt request to the CPU is generated when the data written in
UODR register is transferred to the internal shift register and the next data can be
written to UODR.
■ Flag Set Timings for a Transmit Operation
Figure 19.9-6 TDRE Set Timing (Mode 0)
UODR write
TDRE
Interrupt request to the CPU
Tr ansmit interrupt
SOT0 output
ST D0 D1
ST: Start bit
332
D2 D3 D4
D5 D6 D7
D0 to D7: Data bits
SP
SP ST D0 D1
SP: Stop bit
D2 D3
CHAPTER 19 UART0, UART1
19.9.4
Status Flag During Transmit and Receive Operation
RBF is set when the start bit is detected and cleared when a stop bit is detected. The
receive data in UIDR at the RBF clear timing is not yet valid. The data in UIDR becomes
valid at the RDRF set timing.
■ Status Flag During Transmit and Receive Operation
Figure 19.9-7 shows the RBF set timing (Mode 0).
Figure 19.9-7 RBF Set Timing (Mode 0)
SIN0 input
ST D0 D1
D2 D3 D4
D5 D6 D7
SP
RBF
RDRF, PE, ORFE
ST: Start bit
D0 to D7: Data bits
SP: Stop bit
Writing the transmission data to UODR0 sets TBF. TBF is cleared when transmission completes.
Figure 19.9-8 TBF Set Timing (Mode 0)
UODR write
ST D0 D1
SOT0 output
D2 D3 D4
D5 D6 D7
SP
SP
TBF
ST: Start bit
D0 to D7: Data bits
SP: Stop bit
Note:
Receive operation starts after releasing a reset unless the SIN input pin is fixed at "1". Therefore,
before setting the mode, write "0" to RFC in the UMC register to clear any receive flags that have
been set.
Set the communication mode when the RBF and TBF flags in the USR register are "0". The data
transmitted and received during mode setting cannot be guaranteed.
■ EI2OS (Extended Intelligent I/O Service)
See the Section "3.7 Extended Intelligent I/O Service (EI2OS)" for details on EI2OS.
333
CHAPTER 19 UART0, UART1
19.10
UART0, UART1 Application Example
Mode 2 is used when a number of slave CPUs are connected to a host CPU (see Figure
19.10-1.)
■ Application Example
Figure 19.10-1 RBF Set Timing (Mode 0)
SIN0 input
ST D0 D1
D2 D3 D4
D5 D6 D7
SP
RBF
RDRF, PE, ORFE
ST: Start bit
D0 to D7: Data bits
SP: Stop bit
As shown in Figure 19.10-2, communication starts with the host CPU transmitting address data. The ninth
bit (D8) of the address data is set to "1". The address selects the slave CPU with which communication will
be established. The selected slave CPU communicates with the host CPU using a protocol determined by
the user. In normal data, D8 is set to "0". Unselected slave CPUs wait in standby until the next
communication session starts. Figure 19.10-3 shows the communication flowchart for mode 2 operation.
Because the parity check function is not available in this mode, set the PEN bit in the UMC register to "0".
Figure 19.10-2 Example System Configuration Using Mode 2
SOT0
SIN0
Host CPU
334
SOT0 SIN0
SOT0 SIN0
Slave CPU #0
Slave CPU #1
CHAPTER 19 UART0, UART1
Figure 19.10-3 Communication Flowchart for Mode 2 Operation
(Host CPU)
(Slave CPU)
Start
Start
Set the transfer mode to "3"
Set the transfer mode to "2"
Set the slave CPU selection
in D0 to D7. Set D8 to "1".
Transfer the byte.
Receive a byte
NO
Selected?
Set D8 to "0" and perform
communications
End
YES
Set the transfer mode to "3"
and enable SOT0 output
Perform communications
with the master CPU
Use the status flag to
confirm transfer completion,
then set the transfer mode to
"2" and disable SOT0 output
335
CHAPTER 19 UART0, UART1
336
CHAPTER 20
UART2, UART3
This chapter explains the functions and operation of
UART2, UART3.
Note: UART2 is only available on MB90V390HA/
MB90V390HB.
20.1 Overview of UART2, UART3
20.2 Configuration of UART2, UART3
20.3 UART2, UART3 Pins
20.4 UART2, UART3 Registers
20.5 UART2, UART3 Interrupts
20.6 UART2, UART3 Baud Rates
20.7 Operation of UART2, UART3
20.8 Notes on Using UART2, UART3
337
CHAPTER 20 UART2, UART3
20.1
Overview of UART2, UART3
The UART2, UART3 with LIN (Local Interconnect Network) - Function is a generalpurpose serial data communication interface for performing synchronous or
asynchronous communication with external devices. UART2, UART3 provides
bidirectional communication function (normal mode), master/slave communication
function (multiprocessor mode in master/slave systems), and special features for LINbus systems (working both as master or as slave device).
Please note that UART2, UART3 is not software compatible to the other UARTs.
■ UART2, UART3 Functions
● UART2, UART3 functions
UART2, UART3 is a general-purpose serial data communication interface for transmitting serial data to
and receiving data from another CPU and peripheral devices. It has the functions listed in Table 20.1-1.
Table 20.1-1 UART2, UART3 Functions (1/2)
Item
Data buffer
Full-duplex
Serial Input
The machine clock performs oversampling 5 times and the receive value is
determined by the majority decision of sampling value (asynchronous mode
only)
Transfer mode
• Clock synchronous (start-stop synchronization and start-stop-bit-option)
• Clock asynchronous (using start-, stop-bits)
Baud rate
• A dedicated baud rate generator is provided, which consists of a 15-bitreload counter
• An external clock can be input and also be adjusted by the reload counter
Data length
• 7 bits (not in synchronous or LIN mode)
• 8 bits
Signal mode
Non-return to zero (NRZ)
Start bit timing
Reception error detection
Interrupt request
338
Function
Clock synchronization to the falling edge of the start bit in asynchronous
mode
• Framing error
• Overrun error
• Parity error (Not supported in Mode 1)
• Reception interrupt (reception complete, reception error detect, LINSynch-break detect)
• Transmission interrupt (transmission data empty)
• Interrupt request to ICU (LIN synch field detection: LSYN)
• Both transmission and reception support for extended intelligent
I/O service (EI2OS) and DMA function.
CHAPTER 20 UART2, UART3
Table 20.1-1 UART2, UART3 Functions (2/2)
Item
Master/slave communication function
(multiprocessor mode)
Synchronous mode
Transceiving pins
LIN bus options
Synchronous serial clock
Clock delay option
Function
One-to-n communication (one master to n slaves)
(This function is supported both for master and slave system).
Function as Master- or Slave-UART
Direct access possible
•
•
•
•
•
Operation as master device
Operation as slave device
Generation of LIN-Synch-break
Detection of LIN-Synch-break
Detection of start/stop edges in LIN-Synch-field connected to ICU1 or
ICU5 (UART3) / ICU3 (UART2, MB90V390HA/MB90V390HB only)
The synchronous serial clock can be output continuously on the SCK pin
for synchronous communication with start & stop bits
Special synchronous Clock Mode for delaying clock (useful for SPI)
339
CHAPTER 20 UART2, UART3
■ UART2, UART3 Operation Modes
The UART2, UART3 operates in four different modes, which are determined by the MD0- and the MD1bit of the Serial mode register (SMR2/SMR3). Mode 0 and 2 are used for bidirectional serial
communication, mode 1 for master/slave communication and mode 3 for LIN master/slave communication.
Table 20.1-2 UART2, UART3 Operation Modes
Data length
Operation mode
parity disabled
0
normal mode
1
multiprocessor
2
normal mode
3
LIN mode
parity enabled
7 bits or 8 bits
7 bits or 8 bits
+ 1 *2
8 bits
8 bits
-
Synchronization of
mode
Length of
stop bit
data bit
direction *1
asynchronous
1 bit or 2 bits
L/M
asynchronous
1 bit or 2 bits
L/M
synchronous
0 bit, 1 bit or
2 bits
L/M
asynchronous
1 bit
L
*1: means the data bit transfer format: LBS first or MSB first.
*2: "+1" means the indicator bit of the address/data selection in the multiprocessor mode, instead of parity.
Note:
Mode 1 operation is supported both for master or slave operation of UART2, UART3 in a master/
slave connection system. In Mode 3 the UART2, UART3 function is locked to 8N1-Format, LSB first.
If the mode is changed, UART2, UART3 cuts off all possible transmission or reception and awaits then
new action.
The MD1 and MD0 bit of the Serial Mode Register (SMR2/SMR3) determine the operation mode of
UART2, UART3 as shown in the following table:
Table 20.1-3 Mode Bit Setting
340
MD1
MD0
Mode
Description
0
0
0
Asynchronous (normal mode)
0
1
1
Asynchronous (multiprocessor mode)
1
0
2
Synchronous (normal mode)
1
1
3
Asynchronous (LIN mode)
CHAPTER 20 UART2, UART3
■ UART2, UART3 Interrupt and EI2OS
Table 20.1-4 UART2, UART3 Interrupt and EI2OS
Interrupt control register
Interrupt cause
Interrupt
number
Vector table address
EI2OS
Register
name
Address
Lower
Upper
Bank
UART2 reception interrupt
#39(27H)
ICR14
0000BEH
FFFF60H
FFFF61H
FFFF62H
*1
UART2 transmission
interrupt
#40(28H)
ICR14
0000BEH
FFFF5CH
FFFF5DH
FFFF5EH
*2
UART3 reception interrupt
#39(27H)
ICR14
0000BEH
FFFF60H
FFFF61H
FFFF62H
*3
UART3
transmission interrupt
#40(28H)
ICR14
0000BEH
FFFF5CH
FFFF5DH
FFFF5EH
*4
*1: EI2OS service for UART2 reception is usable only if the UART2 transmission interrupt and both of transmission and
reception interrupt of UART3 are disabled. When detecting receive errors, stop request for EI2OS service is supported.
*2: EI2OS service for UART2 transmission is usable only if the UART2 reception interrupt and both of transmission and
reception interrupt of UART3 are disabled.
*3: EI2OS service for UART3 reception is usable only if the UART3 transmission interrupt and both of transmission and
reception interrupt of UART2 are disabled. When detecting receive errors, stop request for EI2OS service is supported.
*4: EI2OS service for UART3 transmission is usable only if the UART3 reception interrupt and both of transmission and
reception interrupt of UART2 are disabled.
341
CHAPTER 20 UART2, UART3
20.2
Configuration of UART2, UART3
This section provides a short overview on the building blocks of UART2, UART3.
■ Block Diagram of UART2, UART3
UART2, UART3 consists of the following blocks:
• Reload Counter
• Reception Control Circuit
• Reception Shift Register
• Reception Data Register (RDR2/RDR3)
• Transmission Control Circuit
• Transmission Shift Register
• Transmission Data Register (TDR2/TDR3)
• Error Detection Circuit
• Oversampling Unit
• Interrupt Generation Circuit
• LIN Synch Break/Synch Field Detection
• LIN Synch Break Generation Circuit
• Bus Idle Detection Circuit
• LIN-UART3 Serial Mode Register (SMR2/SMR3)
• Serial Control Register (SCR2/SCR3)
• Serial Status Register (SSR2/SSR3)
• Extended Communication Control Register. (ECCR2/ECCR3)
• Extended Status/Control Register. (ESCR2/ESCR3)
342
CHAPTER 20 UART2, UART3
Figure 20.2-1 Block Diagram of UART2, UART3
(OTO,
EXT,
REST)
Machine clock
PE
ORE
FRE
TIE
RIE
LBIE
LBD
transmission clock
Reload
Counter
SCK2/SCK3
TRANSMISSION
CONTROL
CIRCUIT
RECEPTION
CONTROL
CIRCUIT
Pin
Restart Reception
Reload Counter
SIN2/SIN3
Interrupt
Generation
circuit
reception clock
Pin
RBI
TBI
Start bit
Detection
circuit
Transmission
Start circuit
Received
Bit counter
Transmission
Bit counter
Received
Parity counter
Transmission
Parity counter
reception
IRQ
transmission
IRQ
TDRE
SOT2/3
Over sampling
Unit
Pin
RDRF
reception
complete
SOT3
SIN3
Signal
to ICU
LIN break
and Synch
Field
Detection
circuit
SIN3
Reception
shift register
Transmission
shift register
LIN
break
generation
circuit
transmission
start
Bus idle
Detection
circuit
Err or
Detection
RDR2/RDR3
PE
ORE
FRE
2
To EI OS
LBR
LBL1
LBL0
TDR2/TDR3
RBI
LBD
TBI
Internal data bu s
PE
ORE
FRE
RDRF
TDRE
BDS
RIE
TIE
SSR2/
SSR3
register
MD1
MD0
OTO
EXT
REST
UPCL
SCKE
SOE
SMR2/
SMR3
register
PEN
P
SBL
CL
A/D
CRE
RXE
TXE
SCR2/
SCR3
register
LBIE
LBD
LBL1
LBL0
SOPE
SIOP
CCO
SCES
LBR
ESCR2/
MS
ESCR3 SCDE
ECCR2/
ECCR3
register
register
SSM
RBI
TBI
343
CHAPTER 20 UART2, UART3
■ Explanation of the Different Blocks
● Reload Counter
The reload counter functions as the dedicated baud rate generator. It can select external input clock or
internal clock for the transmitting and receiving clocks. The reload counter has a 15 bit register for the
reload value. The actual count of the transmission reload counter can be read via the BGR02/BGR12, resp.
BGR03/BGR13.
● Reception Control Circuit
The reception control circuit consists of a received bit counter, start bit detection circuit, and received
parity counter. The received bit counter counts reception data bits. When reception of one data item for the
specified data length is complete, the received bit counter sets the reception data register full flag in the
serial status register. The start bit detection circuit detects start bits from the serial input signal and sends a
signal to the reload counter to synchronize it to the falling edge of these start bits. The reception parity
counter calculates the parity of the reception data.
● Reception Shift Register
The reception shift register fetches reception data input from the SIN2/SIN3 pin, shifting the data bit by bit.
When reception is complete, the reception shift register transfers receive data to the RDR2/RDR3 register.
● Reception Data Register
This register retains reception data. Serial input data is converted and stored in this register.
● Transmission Control Circuit
The transmission control circuit consists of a transmission bit counter, transmission start circuit, and
transmission parity counter. The transmission bit counter counts transmission data bits. The transmission of
one data item of the specified data length is transmitted. When the transmission bit counter indicates the
transmission start of written data, the transmission data register full flag in the serial status register is set.
At this time, if the transmission interrupt is enabled, the transmission interrupt request is generated. The
transmission start circuit starts transmission when data is written to TDR2/TDR3. The transmission parity
counter generates a parity bit for data to be transmitted if parity is enabled.
● Transmission Shift Register
The transmission shift register transfers data written to the TDR2/TDR3 register to itself and outputs the
data to the SOT2/SOT3 pin, shifting the data bit by bit.
● Transmission Data Register (TDR2/TDR3)
This register sets transmission data. Data written to this register is converted to serial data and output.
● Error Detection Circuit
The error detection circuit checks if there was any error during the last reception. If an error has occurred it
sets the corresponding error flags.
344
CHAPTER 20 UART2, UART3
● Oversampling Unit
The oversampling unit oversamples the incoming data at the SIN2/SIN3 pin for five times with the
machine clock. It is not operated in synchronous operation mode.
● Interrupt Generation Circuit
The interrupt generation circuit administers all cases of generating a reception or transmission interrupt. If a
corresponding enable flag is set and an interrupt case occurs the interrupt will be generated immediately.
● LIN synch Break and Synchronization Field Detection Circuit
The LIN break and LIN synchronization field detection circuit detects a LIN break, if a LIN master node is
sending a message header. If a LIN break is detected a special flag bit is generated. The first and the fifth
falling edge of the LIN synchronization field is recognized by this circuit by generating an internal signal
(LSYN) for the Input Capture Unit to measure the actual serial clock time of the transmitting master node.
● LIN Synch Break Generation Circuit
The LIN break generation circuit generates a LIN break of a determined length.
● Bus Idle Detection circuit
The bus idle detection circuit recognizes if neither reception nor transmission is going on. In this case, the
circuit generates the special flag bits TBI and RBI.
● LIN-UART2, LIN-UART3 Serial Mode Register (SMR2/SMR3)
This register performs the following operations:
• Selecting the LIN-UART2, LIN-UART3 operation mode
• Selecting a clock input source
• Selecting if an external clock is connected "one-to-one" or connected to the reload counter
• Resetting dedicated reload timer
• Resetting the LIN-UART2, LIN-UART3 (preserving the settings of the registers)
• Specifying whether to enable serial data output to the corresponding pin
• Specifying whether to enable clock output to the corresponding pin
● Serial Control Register (SCR2/SCR3)
This register performs the following operations:
• Specifying whether to provide parity bits
• Selecting parity bits
• Specifying a stop bit length
• Specifying a data length
• Selecting a frame data format in mode 1
• Clearing the error flags
• Specifying whether to enable transmission
• Specifying whether to enable reception
345
CHAPTER 20 UART2, UART3
● Serial Status Register (SSR2/SSR3)
This register performs the following functions
• Indicating status of receive/transmit operations and errors
• Specifying LSB first or MSB first
• Receive interrupt enable/disable
• Transmit interrupt enable/disable
● Extended Status/Control Register (ESCR2/ESCR3)
This register performs the following functions
• LIN synch break interrupt enable/disable
• Indicating LIN synch break detection
• Specifying LIN synch break length
• Directly accessing SIN2/SIN3 and SOT2/SOT3 pins
• Specifying continuous clock output operation
• Specifying sampling clock edge
● Extended Communication Control Register (ECCR2/ECCR3)
This register performs the following functions
• Indicating bus idle state
• Specifying synchronous clock
• Specifying LIN synch break generation
346
CHAPTER 20 UART2, UART3
20.3
UART2, UART3 Pins
This section describes the UART2, UART3 pins and provides a pin block diagram.
■ UART2, UART3 Pins
The UART2, UART3 pins also serve as general ports. Table 20.3-1 lists the UART2, UART3 pins.
Table 20.3-1 UART2, UART3 Pins
Pin name
P90/SIN2
P91/SCK2
Pin function
Pull-up
Standby
control
Port I/O or serial
data input
Port I/O or serial
data output
P93/SIN3
Port I/O or serial
data input
P95/SOT3
Port I/O or serial
data output
Port I/O or serial
clock input/output
Setting required to use pin
Set as an input port
(DDR9:bit0 = 0)
Set as an input port when a
clock is input
(DDR9:bit1 = 0)
Port I/O or serial
clock input/output
P92/SOT2
P94/SCK3
I/O format
Set to output enable mode
when a clock is output
(SMR2:SCKE = 1)
CMOS output
and selectable
Automotive/
CMOS
Hysteresis input
Set to output enable mode
(SMR2:SOE = 1)
Not selectable
Provided
Set as an input port
(DDR9: bit3 = 0)
Set to output enable mode
(SMR3: SOE = 1)
Set as an input port when a
clock is input
(DDR9: bit4 = 0)
Set to output enable mode
when a clock is output
(SMR3: SCKE = 1)
See "Electrical characteristics 3. Direct current standard" for the standard values.
347
CHAPTER 20 UART2, UART3
Figure 20.3-1 Block Diagram of UART2, UART3 Pins
Resource input *
Port data register (PDR)
Resource output
Internal data bus
Resource output enable
PDR read
Output latch
P-ch
PDR write
Pin
Port direction register (DDR)
Direction latch
N-ch
DDR write
general purpose I/O /SIN2/SIN3
general purpose I/O /SCK2/SCK3
general purpose I/O /SOT2/SOT3
Standby control (SPL=1)
DDR read
Standby control: Stop mode, watch mode, time-base timer mode, and SPL=1
*: Resources are input or output to or from pins having peripheral functions.
Note:
UART2 is functionally the same as UART3, except the registers and pin numbers
348
CHAPTER 20 UART2, UART3
20.4
UART2, UART3 Registers
The following figure shows the UART2, UART3 registers.
■ UART2, UART3 Registers
Figure 20.4-1 UART2, UART3 Registers
bit 15
bit 8
bit 7
bit 0
Address:
003519H, 003518H
SCR3 (Serial Control Register)
SMR3 (Serial Mode Register)
00351BH, 00351AH
SSR3 (Serial Status Register)
RDR3/TDR3 (Rx, Tx Data Register)
00351DH, 00351CH
ESCR3 (Extended Status/Control Reg.)
ECCR3 (Extended Comm. Contr. Reg.)
00351FH, 00351EH
BGR13 (Baud Rate Generator Reg. 13)
BGR03 (Baud Rate Generator Reg. 03)
0035D9H, 0035D8H
SCR2 (Serial Control Register)
SMR2 (Serial Mode Register)
0035DBH, 0035DAH
SSR2 (Serial Status Register)
RDR2/TDR2 (Rx, Tx Data Register)
0035DDH, 0035DCH
ESCR2 (Extended Status/Control Reg.)
ECCR2 (Extended Comm. Contr. Reg.)
0035DFH, 0035DEH
BGR12 (Baud Rate Generator Reg. 12)
BGR02 (Baud Rate Generator Reg. 02)
349
CHAPTER 20 UART2, UART3
20.4.1
Serial Control Register (SCR2/SCR3)
This register specifies parity bits, selects the stop bit and data lengths, selects a frame
data format in mode 1, clears the reception error flag, and specifies whether to enable
transmission and reception.
■ Serial Control Register (SCR2/SCR3)
Figure 20.4-2 Configuration of the Serial Control Register (SCR2/SCR3)
Address:
SCR3: 003519H
SCR2: 0035D9H
bit 15
PEN
14
P
13
12
SBL CL
11
10
9
Initial value
00000000B
8
A/D CRE RXE TXE
R/W R/W R/W R/W R/W W R/W R/W
bit8
TXE
Tr ansmission enable
0
Disable Tr ansmission
1
Enable Tr ansmission
bit9
RXE
Reception enable
0
Disable Reception
1
Enable Reception
bit10
Clear Reception errors
CRE
write
read
0
ignored
1
Clear all reception
errors (PE, FRE, ORE)
read always returns "0"
bit11
A/D
Address / Data bit
0
Data bit
1
Address bit
bit12
CL
Character (Data frame) Length
0
7 bits
1
8 bits
bit13
SBL
Stop bit length
0
1 stop bit
1
2 stop bits
bit14
P
Parity selection
0
Even Parity enabled
1
Odd Parity enabled
bit15
PEN
350
Parity Enable
R/W
:
Readable and writable
0
Parity disabled
W
:
Write only
1
Parity enabled
:
Initial value
CHAPTER 20 UART2, UART3
Table 20.4-1 Functions of Each Bit of Control Register (SCR2/SCR3)
Bit name
Function
bit15
PEN:
Parity enable bit
This bit selects whether to add a parity bit during transmission or detect it during
reception.
Parity is only provided in mode 0 and in mode 2 if SSM of the ECCR2/ECCR3 is
selected. This bit is fixed to "0" (no parity) in mode 1 and 3 (LIN).
bit14
P:
Parity selection bit
When parity is provided and enabled this bit selects even (0) or odd (1) parity
bit13
SBL:
Stop bit length
selection bit
This bit selects the length of the stop bit of an asynchronous data frame or a
synchronous frame if SSM of the ECCR2/ECCR3 is selected. This bit is fixed to "0" (1
stop bit) in mode 3 (LIN).
Note:
The bit length of the stop bit is detected whenever it is received.
bit12
CL:
Data length selection
bit
This bit specifies the length of transmission or reception data. This bit is fixed to "1" (8
bits) in mode 2 and 3.
A/D:
Address/Data
selection bit
This bit specifies the data format in multiprocessor mode 1. Writing to this bit is
provided for a master CPU, reading from it for slave CPU. A "1" indicates an address
frame, a "0" indicates a usual data frame.
Note:
Please read the hints about using this bit in Section "20.8 Notes on Using UART2,
UART3".
CRE:
Clear reception error
flags bit
This bit clears the FRE, ORE, and PE flag of the Serial Status Register (SSR2/SSR3).
Writing a "1" to it clears the error flag.
Writing a "0" has no effect.
Reading from it always returns "0".
Note:
Clear reception error flags after disabling the receive operation (RXE=0).
RXE:
Reception enable bit
This bit enables/disables LIN-UART2, UART3 reception.
If this bit is set to "0", UART2, UART3 disables the reception of data frames.
If this bit is set to "1", UART2, UART3 enables the reception of data frames.
The LIN synch break detection in mode 3 remains unaffected.
Note:
If reception is disabled (RXE=0) during receiving, it is stopped immediately. In this
case, data is not guaranteed.
TXE:
Transmission enable
bit
This bit enables/disables LIN-UART2, UART3 transmission.
If this bit is set to "0", UART2, UART3 disables the transmission of data frames.
If this bit is set to "1", UART2, UART3 enables the transmission of data frames.
Note:
If transmission is disabled (TXE=0) during transmitting, it is stopped immediately.
In this case, data is not guaranteed.
bit11
bit10
bit9
bit8
351
CHAPTER 20 UART2, UART3
20.4.2
Serial Mode Register (SMR2/SMR3)
This register selects an operation mode and baud rate clock and specifies whether to
enable output of serial data and clocks to the corresponding pin.
■ Serial Mode Register (SMR2/SMR3)
Figure 20.4-3 Configuration of the Serial Mode Register (SMR2/SMR3)
bit 7
Address:
SMR3: 003518H
SMR2: 0035D8H
6
5
4
3
R/W R/W R/W R/W W
2
1
0
W R/W R/W
Initial value
00000000B
bit0
SOE
Serial data output enable bit of LIN-UART
0
General purpose I/O port
1
LIN-UART serial data output pin
bit1
SCKE
Serial clock output enable bit of LIN-UART
0
General purpose I/O port or LIN-UART clock input pin
1
Serial clock output pin of LIN-UART
bit2
UPCL
LIN-UART programmable clear (Software Reset)
write
0
ignored
1
Reset UART
read
always "0"
bit3
Restart dedicated Reload Counter
REST
write
0
ignored
1
Restart Counter
read
always "0"
bit4
EXT
External Serial Clock Source enable
0
Use internal Baud Rate Generator (Reload Counter)
1
Use external Serial Clock Source
bit5
352
R/W
:
Readable and writable
W
:
Write only
:
Initial value
OTO
One-to-one external clock Input enable
0
Use ext. Clock with Baud Rate Generator (Reload C.)
1
Use external Clock as is
bit7
MD1
bit6
MD0
0
0
Mode 0: Asynchronous normal
0
1
Mode 1: Asynchronous Multiprocessor
1
0
Mode 2: Synchronous
1
1
Mode 3: Asynchronous LIN
Operation Mode Setting
CHAPTER 20 UART2, UART3
Table 20.4-2 Bit Function of the Serial Mode Register (SMR2/SMR3)
Bit name
Function
bit7
bit6
MD1 and MD0:
Operation mode
selection bits
These two bits set the UART2, UART3 operation mode.
bit5
OTO:
One-to-one external
clock selection bit
This bit sets an external clock directly to the LIN-UART2, LIN-UART3’s serial clock.
This function is used for operating mode 2 (synchronous) slave mode operation.
bit4
EXT:
External clock
selection bit
This bit executes internal or external clock source for the reload counter
bit3
REST:
Restart of
transmission reload
counter bit
If a "1" is written to this bit the reload counter is restarted. Writing "0" to it has no
effect. Reading from this bit always returns "0".
UPCL:
UART2, UART3
programmable clear
bit (Software reset)
Writing a "1" to this bit resets LIN-UART2, UART3 immediately. The register settings
are preserved. Possible reception or transmission will cut off.
All flags (TDRE, RDRF, LBD, PE, ORE, FRE) are cleared and the Reception Data
Register (RDR2/RDR3) contains "00H". Writing "0" to this bit has no effect. Reading
from it always returns "0".
LIN-UART2, UART3 reset should be performed after disabling the interrupt enable bits.
SCKE:
Serial clock output
enable
• This bit controls the serial clock I/O ports.
• When this bit is "0", SCK2/SCK3 pin operate as general purpose I/O port or serial
clock input pin. When this bit is "1", the pin operates as serial clock output pin and
outputs clock in operating mode 2 (synchronous). SCKE bit is fixed to "0" for
MS=1.
Note:
When using SCK2/SCK3 pin as serial clock input (SCKE=0) pin, set the
corresponding bit of DDR as input port. Also, select external clock (EXT = 1) using
the external clock selection bit.
Reference:
When the SCK2/SCK3 pin is assigned to serial clock output (SCKE=1), it functions
as the serial clock output pin regardless of the status of the general purpose I/O
ports.
SOE:
Serial data output
enable bit
• This bit enables or disables the output of serial data.
• When this bit is "0", SOT2/SOT3 pin operates as general purpose I/O pin. When this
bit is "1", SOT2/SOT3 pin operates as serial data output pins (SOT2/SOT3).
Reference:
When the output of serial data is enabled (SOE=1), SOT2/SOT3 pin functions as
serial data output pin (SOT2/SOT3) regardless of the status of general input-output
ports.
bit2
bit1
bit0
353
CHAPTER 20 UART2, UART3
20.4.3
Serial Status Register (SSR2/SSR3)
This register checks the transmission and reception status and error status, and
enables and disables the transmission and reception interrupts.
■ Serial Status Register (SSR2/SSR3)
Figure 20.4-4 Configuration of the Serial Status Register (SSR2/SSR3)
bit 15
Address:
SSR3: 00351BH
SSR2: 0035DBH
R
14
13
12
R
R
R
11
10
9
Initial value
00001000B
8
R R/W R/W R/W
bit8
TIE
Transmission Interrupt enable
0
Disables Tr ansmission Interrupt
1
Enables Tr ansmission Interrupt
bit9
RIE
Reception Interrupt enable
0
Disables Reception Interrupt
1
Enables Reception Interrupt
bit10
BDS
Bit direction setting
0
send / receive LSB Þrst
1
send / receive MSB Þrst
bit11
TDRE
Tr ansmission data register empty
0
Transmission data register is full
1
Transmission data register is empty
bit12
RDRF
Reception data register full
0
Reception data register is empty
1
Reception data register is full
bit13
FRE
Framing error
0
No framing error occurred
1
A framing error occurred during reception
bit14
ORE
Overrun error
0
No overrun error occurred
1
An overrun error occurred during reception
bit15
PE
354
Parity error
R/W
:
Readable and writable
0
No parity error occurred
R
:
Flag is read only, write to it has
no effect
1
A parity error occurred during reception
:
Initial value
CHAPTER 20 UART2, UART3
Table 20.4-3 Functions of Each Bit of Status Register (SSR2/SSR3) (1/2)
Bit name
bit15
bit14
bit13
bit12
bit11
bit10
Function
PE:
Parity error flag
bit
• This bit is set to "1" when a parity error occurs during reception at PEN=1 and is cleared
when "1" is written to the CRE bit of the serial mode register (SMR2/SMR3).
MB90V390H/MB90F394H(A): This bit is also cleared when a LIN break is detected
(LBD=1).
• A reception interrupt request is output when this bit and the RIE bit are "1".
• Data in the reception data register (RDR2/RDR3) is invalid when this flag is set.
ORE:
Overrun error
flag bit
• This bit is set to "1" when an overrun error occurs during reception and is cleared when
"0" is written to the CRE bit of the serial mode register (SMR2/SMR3).
MB90V390H/MB90F394H(A): This bit is also cleared when a LIN break is detected
(LBD=1).
• A reception interrupt request is output when this bit and the RIE bit are "1".
• Data in the reception data register (RDR2/RDR3) is invalid when this flag is set.
FRE:
Framing error
flag bit
• This bit is set to "1" when a framing error occurs during reception and is cleared when
"0" is written to the CRE bit of the serial mode register 1 (SMR2/SMR3).
MB90V390H/MB90F394H(A): This bit is also cleared when a LIN break is detected
(LBD=1).
• A reception interrupt request is output when this bit and the RIE bit are "1".
• Data in the reception data register (RDR2/RDR3) is invalid when this flag is set.
Note:
When framing error is detected by the first or the second bit of the stop bit at SBL=1,
this bit is set to "1" as for either stop bit.
Thus, it is necessary to determine whether the receive data is enabled by the second bit
of the stop bit.
RDRF:
Receive data full
flag bit
• This flag indicates the status of the reception data register (RDR2/RDR3).
• This bit is set to "1" when reception data is loaded into RDR2/RDR3 and can only be
cleared to "0" when the reception data register (RDR2/RDR3) is read.
MB90V390H/MB90F394H(A): This bit is also cleared when a LIN break is detected
(LBD=1).
• A reception interrupt request is output when this bit and the RIE bit are "1".
TDRE:
Transmission
data empty flag
bit
• This flag indicates the status of the transmission data register (TDR2/TDR3).
• This bit is cleared to "0" when transmission data is written to TDR2/TDR3 and is set to
"1" when data is loaded into the transmission shift register and transmission starts.
• A transmission interrupt request is generated if both this bit and the TIE bit are "1".
• If the LBR bit in the ECCR2/ECCR3 register is set to "1" while the TDRE bit is "1",
then this bit once changes to "0". When effective data to TDR2/TDR3 doesn't exist after
the completion of LIN synch break generator, the TDRE bit returns to "1".
Note:
This bit is set to "1" (TDR2/TDR3 empty) as its initial value.
BDS:
Transfer
direction
selection bit
• This bit selects whether to transfer serial data from the least significant bit (LSB first,
BDS=0) or the most significant bit (MSB first, BDS=1).
This bit is fixed to "0" at mode 3.
Note:
When the BDS bit is rewritten after the receive data writing to receive data register
(RDR2/RDR3) because an upper side and lower side are replaced at the time of writing
receive data to the receive data register (RDR2/RDR3), the data of RDR2/RDR3
becomes invalid.
355
CHAPTER 20 UART2, UART3
Table 20.4-3 Functions of Each Bit of Status Register (SSR2/SSR3) (2/2)
Bit name
Function
bit9
RIE:
Reception
interrupt request
enable bit
• This bit enables/disables the reception interrupt. If any of the RDRF, PE, ORE and FRE
bits is set and this bit is "1", then a reception interrupt is signaled to the interrupt
controller.
bit8
TIE:
Transmission
interrupt request
enable bit
• This bit enables or disables the transmission interrupt.
• A transmission interrupt request is output when this bit and the TDRE bit are "1".
356
CHAPTER 20 UART2, UART3
20.4.4
Reception and Transmission Data Register
(RDR2/RDR3 and TDR2/TDR3)
The reception data register (RDR2/RDR3) holds the received data. The transmission
data register (TDR2/TDR3) holds the transmission data. Both RDR2/RDR3 and TDR2/
TDR3 registers are located at the same address.
■ Bit Configuration of Reception and Transmission Data Registers (RDR2/RDR3 and
TDR2/TDR3)
Figure 20.4-5 Transmission and Reception Data Registers (RDR2/RDR3 and TDR2/TDR3)
bit 7
6
5
4
3
2
1
0
Address:
RDR3/TDR3: 00351AH
RDR2/TDR2: 0035DAH
Initial value
0 0 0 0 0 0 0 0B [RDR2/RDR3]
1 1 1 1 1 1 1 1B [TDR2/TDR3]
R/W R/W R/W R/W R/W R/W R/W R/W
bit 7 to 0
R/W
Data Registers
Read
Read from Reception Data Register
Write
Write to Tr ansmission Data Register
R/W: Readable and writable
■ Reception Data Register (RDR2/RDR3)
RDR2/RDR3 is the register that contains reception data. The serial data signal transmitted to the SIN2/
SIN3 pin is converted in the shift register and stored there. When the data length is 7 bits, the uppermost bit
(D7) contains "0". When reception is complete the data is stored in this register and the reception data full
flag bit (SSR2/SSR3: RDRF) is set to "1". If a reception interrupt request is enabled at this point, a
reception interrupt occurs.
Read RDR2/RDR3 when the RDRF bit of the status register (SSR2/SSR3) is "1". The RDRF bit is cleared
automatically to "0" when RDR2/RDR3 is read. Also the reception interrupt is cleared if it is enabled and no
error has occurred. For MB90V390H/MB90F394H(A), the RDRF bit is also cleared when a LIN break is
detected (LBD=1).
Data in RDR2/RDR3 is invalid when a reception error occurs (SSR2/SSR3: PE, ORE, or FRE = 1).
357
CHAPTER 20 UART2, UART3
■ Transmission Data Register (TDR2/TDR3)
When data to be transmitted is written to the transmission data register in transmission enable state, it is
transferred to the transmission shift register, then converted to serial data, and transmitted from the serial
data output terminal (SOT2/SOT3 pin). If the data length is 7 bits, the uppermost bit (D7) is not sent.
When transmission data is written to this register, the transmission data empty flag bit (SSR2/SSR3:
TDRE) is cleared to "0". When transfer to the transmission shift register is complete and starts, the bit is set
to "1". When the TDRE bit is "1", the next part of transmission data can be written. If output transmission
interrupt requests have been enabled, a transmission interrupt is generated. Write the next part of
transmission data when a transmission interrupt is generated or the TDRE bit is "1".
Note:
TDR2/TDR3 is a write-only register and RDR2/RDR3 is a read-only register. These registers are
located at the same address, so the read value is different from the write value. Therefore,
instructions that perform a read-modify-write (RMW) operation, such as the INC/DEC instruction,
cannot be used.
358
CHAPTER 20 UART2, UART3
20.4.5
Extended Status/Control Register (ESCR2/ESCR3)
The extended status control register (ESCR2/ESCR3) provides several functions, such
as LIN synch break interrupt enabling/disabling, LIN synch break length selection, LIN
synch break detection, direct access to the SIN2/SIN3 and SOT2/SOT3 pins, continuous
clock output in UART2, UART3 synchronous clock mode, and sampling clock edge
setting.
■ Extended Status/Control Register (ESCR2/ESCR3)
Figure 20.4-6 shows the bit configuration of the extended status control registers (ESCR2/ESCR3), and
Table 20.4-4 shows the functions of each bit in the resisters.
Figure 20.4-6 Configuration of the Extended Status/Control Register (ESCR2/ESCR3)
Initial value
0 0 0 0 0 X 0 0B
9
8
Address: 15 14 13 12 11 10
ESCR3: 00351DH
LBL0 SOPE SIOP CCO SCES
ESCR2: 0035DDH LBIE LBD LBL1
R/W R/W R/W R/W R/W R/W R/W R/W
bit8
SCES
Sampling Clock Edge Selection (Mode 2)
0
Sampling on rising clock edge (normal)
1
Sampling on falling clock edge (inverted clock)
bit9
CCO
Continuous Clock Output (Mode 2)
0
Continuous Clock Output disabled
1
Continuous Clock Output enabled
bit10
Serial Input / Output Pin Access
SIOP
write (if SOPE = 1 )
0
SOT is forced to "0"
1
SOT is forced to "1"
read
reading the actual value of
SIN
bit11
SOPE
Enable Serial Output pin direct Access
0
Serial Output pin direct access disable
1
Serial Output pin direct access enable
bit13
bit12
LBL1
LBL0
0
0
LIN break length 13 bit times
LIN synch break length select
0
1
LIN break length 14 bit times
1
0
LIN break length 15 bit times
1
1
LIN break length 16 bit times
bit14
LIN synch break detected flag
LBD
read *
write
0
Clear LIN synch break
detected flag
No LIN synch break detected
1
Ignored
LIN synch break detected
bit15
LBIE
R/W
X
*
:
:
:
:
Readable and writable
Undefined value
Initial value
See Table 20.4-4 for RMW access.
LIN synch break detection Interrupt enable
0
LIN synch break interrupt disable
1
LIN synch break interrupt enable
359
CHAPTER 20 UART2, UART3
Table 20.4-4 Function of Each Bit of the Extended Status/Control Register (ESCR2/ESCR3)
Bit name
bit15
bit14
LBIE:
LIN synch break
detection interrupt
enable bit
LBD:
LIN synch break
detected flag
Function
This bit enables/disables LIN synch break interrupt.
LIN synch break interrupt is connected to the reception interrupt. When the LBD bit is
set and this bit is "1", a reception interrupt is signaled to the interrupt controller. This bit
is fixed to "0" in operation mode 1 and 2.
MB90V390H/MB90F394H(A): This bit goes to "1" if a LIN synch break was detected
in operating mode 0 or 3. When this bit goes to "1", the reception error flags (SSR2/
SSR3:FRE, SSR2/SSR3:ORE, SSR2/SSR3:PE) and the reception register full flag
(SSR2/SSR3:RDRF) are cleared.
MB90V390HA/MB90V390HB/MB90394HA: This bit goes to "1" if a LIN synch
break was detected in operating mode 3.
Writing a "0" to it clears this bit and the corresponding interrupt, if it is enabled.
It is recommended to write "0" to the RXE bit in the SCR2/SCR3 register before using
this bit.
Read-modify-write instructions always return 1. Note that this does not indicate a LIN
synch break.
bit13
bit12
LBL1/LBL0:
LIN synch break
length selection
These two bits determine how many serial bit times the LIN synch break is generated by
UART2, UART3. Receiving a LIN synch break is always fixed to 11 bit times.
bit11
SOPE:
Serial Output pin
direct access enable*
Setting this bit to "1" enables the direct write to the SOT2/SOT3 pin, if SOE = 1 (SMR2/
SMR3). *
bit10
SIOP:
Serial Input/Output
Pin direct access *
Normal read instructions always return the actual value of the SIN2/SIN3 pin. Writing
to it sets the bit value to the SOT2/SOT3 pin, if SOPE = 1.
Notes:
• During a Read-Modify-Write instruction the bit returns the SOT2/SOT3 value in the
read cycle. *
• A set value of this bit is effective only for the TXE bit of serial control register
(SCR) is "0".
bit9
bit8
CCO:
Continuos Clock
Output enable bit
This bit enables a continuos serial clock at the SCK2/SCK3 pin if UART2, UART3
operates in master mode 2 (synchronous) and the SCK2/SCK3 pin is configured as a
clock output.
Note:
When CCO bit is "1", use SSM bit of ECCR2/ECCR3 as setting to "1".
SCES:
Sampling clock edge
selection bit
This bit inverts the serial clock signal in operation mode 2 (synchronous
communication). Receiving data is sampled at the falling edge of the internal clock. If
the MS bit of the ECCR2/ECCR3 register is "0" (master mode) and the SCKE bit of the
SMR2/SMR3 register is "1" (clock output enabled), the output clock signal is also
inverted.
MB90V390H/MB90F394H(A): During operation mode 0,1,3, this bit must be set to
"0".
MB90V390HA/MB90V390HB/MB90394HA: During operation mode 0,1,3, this bit is
fixed to "0".
*: See Table 20.4-5.
360
CHAPTER 20 UART2, UART3
Table 20.4-5 Description of the Interaction of SOPE and SIOP
SOPE
SIOP
Writing to SIOP
Reading from SIOP
1
R/W
write "0" or "1" to SOT2/SOT3
returns current value of SIN2/SIN3
-
RMW
reads current value of SOT2/SOT3 and write "0" or "1"
- : "0" or "1"
361
CHAPTER 20 UART2, UART3
20.4.6
Extended Communication Control Register (ECCR2/
ECCR3)
The extended communication control register provides bus idle recognition interrupt
settings, synchronous clock settings, and the LIN Synch break generation.
■ Extended Communication Control Register (ECCR2/ECCR3)
Figure 20.4-7 shows the bit configuration of the extended communication control registers (ECCR2/
ECCR3), and Table 20.4-6 shows the functions of each bit in the resisters.
Figure 20.4-7 Configuration of the Extended Communication Control Register (ECCR2/ECCR3)
Address:
ECCR3: 00351CH
ECCR2: 0035DCH
bit 7
-
6
2
1
0
MS SCDE SSM
-
RBI
TBI
W R/W R/W R/W
-
R
R
LBR
5
4
3
Initial value
X 0 0 0 0 X X XB
bit0
Tr ansmission bus idle
TBI *
0
Transmission is ongoing
1
no transmission activity
bit1
Reception bus idle
RBI *
0
Reception is ongoing
1
no reception activity
bit2
Unused bit
Reading value is undefined. Always write "0".
bit3
SSM
Synchronous start/stop bits in mode 2
0
No start/stop bits in synchronous mode 2
1
Enable start/stop bits in synchronous mode 2
bit4
SCDE
Serial Clock Delay enable bit in mode 2
0
disable clock delay
1
enable clock delay
bit5
MS
Master / Slave function in mode 2
0
Master mode (generating serial clock)
1
Slave mode (receiving external serial clock)
bit6
Generating LIN synch break bit
LBR
write
0
1
read
ignored
always read "0"
Generate LIN Synch break
bit7
Unused bit
R/W
:
Readable and writable
R
:
Read only
W
:
Write only
X
:
Undefined value
:
Undefined
:
Initial value
-
362
Reading value is undefined. Always write "0".
* : Not used in mode2 when SSM = 0
CHAPTER 20 UART2, UART3
Table 20.4-6 Function of Each Bit of the Extended Communication Control Register (ECCR2/ECCR3)
Bit name
bit7
-
Function
This bit is undefined. Always write "0".
LBR: Generating
LIN synch break bit
Writing a "1" to this bit generates a LIN synch break of the length selected by the LBL0/
LBL1 bits of the ESCR2/ESCR3, if operation mode 3 is selected. Setting to "0" in
operation mode 0.
MS:
Master/Slave mode
selection bit
This bit selects master or slave mode of UART2, UART3 in synchronous mode 2. If
master is selected UART2, UART3 generates the synchronous clock by itself. If slave
mode is selected,
UART2, UART3 receives external serial clock.
This bit is fixed to "0" in operation mode 0, 1 and 3.
Note:
If slave mode is selected, the clock source must be external and set to "One-to-One"
(SMR2/SMR3: SCKE = 0, EXT = 1, OTO = 1).
bit4
SCDE:
Serial clock delay
enable bit
If this bit is set the serial output clock is delayed as shown in Figure 20.7-5 if UART2, 3
operates in master mode 2.
Note:
Figure 20.7-5 shows the behavior of MB90V390HA/MB90V390HB/MB90394HA
(the delay is one half serial clock cycle). For MB90V390H/MB90F394H(A), the
delay is one machine clock cycle.
bit3
SSM:
Start/Stop bit mode
enable
This bit adds start and stop bits to the synchronous data format in operation mode 2. It is
ignored in mode 0, 1, and 3.
bit2
Undefined bit
Undefined bit. Reading value is undefined. Always write to "0".
bit1
RBI:
Reception bus idle
flag bit
This bit is "1" if there is no reception activity on the SIN2/SIN3 pin and it is kept at "1".
Do not use this bit in mode 2 when SSM=0.
bit0
TBI:
Transmission bus idle
flag bit
This bit is "1" if there is no transmission activity on the SOT2/SOT3 pin.
Do not use this bit in mode 2 when SSM=0.
bit6
bit5
363
CHAPTER 20 UART2, UART3
20.4.7
Baud Rate Generator Register 0 and 1 (BGR02/03 and
BGR12/13)
The baud rate generator registers 0 and 1 (BGR02/03 and BGR12/13) set the division
ratio for the serial clock. Also the actual count of the transmission reload counter can
be read.
■ Bit Configuration of Baud Rate Generator Register (BGR02/03 and BGR12/13)
Figure 20.4-8 shows the bit configuration of the baud rate generator register (BGR02/03 and BGR12/13).
Figure 20.4-8 Bit Configuration of Baud Rate Generator Register (BGR02/03 and BGR12/13)
Address: bit 15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
BGR03: 00351EH
BGR13: 00351FH
BGR02: 0035DEH
BGR12: 0035DFH
Initial value
00000000B
00000000B
R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
bit7 to bit0
BGR7 to BGR0
Baud rate Generator Register 02,03
write
Write bit 7 to 0 of reload value to counter
read
Read bit 7 to 0 of transmission reload counter
bit14 to bit8
BGR14 to BGR8
Baud rate Generator Register 12,13
write
Write bit 14 to 8 of reload value to counter
read
Read bit 14 to 8 of transmission reload counter
bit15
Undefined bit
read
R/W
:
Readable and writable
R
:
Read only
-
:
Undefined bit
"0" is read.
The baud rate generator register sets the division ratio of the serial clock. The BGR12/13 and BGR02/03
correspond to the upper byte and lower byte, respectively, and writing of counter reload value and reading
of transmission reload counter value is allowed.
Also, both registers can be read or written via byte or word access.
When writing reload value other than "0" to baud rate generator register, the reload counter starts counting.
364
CHAPTER 20 UART2, UART3
20.5
UART2, UART3 Interrupts
UART2, UART3 uses both reception and transmission interrupts. An interrupt request
can be generated for either of the following causes:
• Receive data is set in the Reception Data Register (RDR2/RDR3), or a reception error
occurs.
• Transmission data is transferred from the Transmission Data Register (TDR2/TDR3) to
the transmission shift register and started.
• A LIN synch break is detected
The extended intelligent I/O service (EI2OS) is available for these interrupts.
■ LIN-UART2, UART3 Interrupts
Table 20.5-1 lists the interrupt control bits and interrupt causes of LIN-UART2, UART3.
Table 20.5-1 Interrupt Control Bits and Interrupt Causes of LIN-UART2, UART3
Reception/ Interrupt
transmission/ request
ICU
flag bit
Reception
Transmission
Input Capture
Unit
Operation
mode
Flag
Register
0
1
2
Interrupt
cause
3
RDRF
SSR2/SSR3
receive data is
❍ ❍ ❍ ❍ written to
RDR2/RDR3
ORE
SSR2/SSR3
❍ ❍ ❍ ❍ Overrun error
FRE
SSR2/SSR3
❍ ❍ *
❍ Framing error
PE
SSR2/SSR3
❍ x
*
x
Parity error
LBD
ESCR2/
ESCR3
x
x
❍
LIN synch
break detected
TDRE
SSR2/SSR3
TDR2/TDR3
❍ ❍ ❍ ❍
empty
ICP1/
ICP3/
ICP5
ICS01/
ICS23/
ICS45
x
ICP1/
ICP3/
ICP5
ICS01/
ICS23/
ICS45
x
x
x
x
x
x
Interrupt
cause
enable bit
How to clear the Interrupt
Request
Receive data is read.
MB90V390H/MB90F394H(A):
LIN synch break is detected
(LBD = 1).
SSR2/
SSR3: RIE "1" is written to clear rec. error bit
(SCR2/3:CRE).
MB90V390H/MB90F394H(A):
LIN synch break is detected
(LBD = 1).
ESCR2/
ESCR3:
LBIE
"0" is written to ESCR2/ESCR3:
LBD
Writing transmission data and 1
SSR2/
writing in LIN Synch break
SSR3: TIE generation bit (ECCR2/ECCR3:
LBR)
1st falling edge ICS01/
❍ of LIN synch
ICS23/
field
ICS45:
5th falling edge ICE1/
ICE3/
❍ of LIN synch
ICE5
field
disable ICP1/ICP3/ICP5
❍: Used
x: Unused
*: Only available if ECCR2/ECCR3:SSM = 1
365
CHAPTER 20 UART2, UART3
● Reception Interrupt
If one of the following events occurs in reception mode, the corresponding flag bit of the Serial Status
Register (SSR2/SSR3) is set to "1":
• Data reception is complete, i. e. the received data was transferred from the received shift register to the
Reception Data Register (RDR2/RDR3): (RDRF=1)
• Overrun error, i. e. RDRF = 1 and RDR2/RDR3 was not read by the CPU and next received data was
transferred to received data register (RDR2/RDR3) from received shift register: (ORE=1)
• Framing error, i. e. a stop bit was expected, but a "0"-bit was received: FRE
• Parity error, i. e. a wrong parity bit was detected: PE
If at least one of these flag bits above go "1" and the reception interrupt is enabled (SSR2/SSR3:RIE = 1), a
reception interrupt request is generated.
If the Reception Data Register (RDR2/RDR3) is read, the RDRF flag is automatically cleared to "0". Note
that this is the only way to reset the RDRF flag (for MB90V390H/MB90F394H(A), the RDRF flag is also
cleared when a LIN break is detected). The error flags are cleared to "0", if a "1" is written to the Clear
Reception Error (CRE) flag bit of the Serial Control Register (SCR2/SCR3). For MB90V390H/
MB90F394H(A), the error flags are also cleared when a LIN break is detected. The RDR2/3 contains only
valid data if the RDRF flag is "1" and no error bits are set.
Note, that the CRE flag is "write only" and by writing a "1" to it, it is internally held to "1" for one machine
clock cycle.
● Transmission Interrupt
If transmission data is transferred from the Transmission Data Register (TDR2/TDR3) to the transfer shift
register and transfer is started, the Transmission Data Register Empty flag bit (TDRE) of the Serial Status
Register (SSR2/SSR3) is set to "1". In this case an interrupt request is generated, if the Transmission
Interrupt Enable (TIE) bit of the SSR2/SSR3 was set to "1" before.
Note, that the initial value of TDRE (after hardware or software reset) is "1". So an interrupt is generated
immediately then, if the TIE flag is set to "1". Also note, that the only way to reset the TDRE flag is writing
data to the Transmission Data Register (TDR2/TDR3).
● LIN Synchronization Break Interrupt
MB90V390H/MB90F394H(A): This paragraph is only relevant, if UART2, UART3 operates in modes 0
or 3.
If the bus (serial input) goes "0" (dominant) for more than 11 bit times, the LIN Break Detected (LBD) flag
bit of the Extended Status/Control Register (ESCR2/ESCR3) is set to "1", and the reception error flags
(SSR2/SSR3:FRE, SSR2/SSR3:ORE, SSR2/SSR3:PE) and the reception data register full flag (SSR2/
SSR3:RDRF) are cleared. Note, that in this case after 9 bit times the reception error flags are set to "1",
therefore the RXE flag has to be set to "0", if only a LIN synch break detect is desired.
The interrupt and the LBD flag are cleared after writing a "1" to the LBD flag. This has to be performed
before input capture interrupt for LIN synch field.
366
CHAPTER 20 UART2, UART3
MB90V390HA/MB90V390HB/MB90394HA: This paragraph is only relevant, if UART2, 3 operates in
mode 3 as a LIN slave.
If the bus (serial input) goes "0" (dominant) for more than 11 bit times, the LIN Break Detected (LBD) flag
bit of the Extended Status/Control Register (ESCR2/ESCR3) is set to "1". Note, that in this case after 9 bit
times the reception error flags are set to "1", therefore the RXE flag has to be set to "0", if only a LIN synch
break detect is desired.
The interrupt and the LBD flag are cleared after writing a "1" to the LBD flag. This has to be performed
before input capture interrupt for LIN synch field.
● LIN Synchronization Field Edge Detection Interrupts
This paragraph is only relevant, if UART2, UART3 operates in mode 3 as a LIN slave. After a LIN synch
break detection the next falling edge of the reception bus is indicated by UART2, UART3. Simultaneously
an internal signal connected to the ICU1/ICU3/ICU5 is set to "1". This signal is reset to "0" after the fifth
falling edge of the LIN Synchronization Field. In both cases the ICU1/ICU3/ICU5 generates an interrupt, if
"both edge detection" and the ICU1/ICU3/ICU5 interrupt are enabled. The difference of the ICU1/ICU3/
ICU5 counter values is the serial clock multiplied by 8. Dividing it by 8 results in the new detected and
calculated baud rate for the dedicated reload counter. This value - 1 has then to be written to the Baud Rate
Generator Registers (BGR02/BGR03 and BGR12/BGR13).There is no need to restart the reload counter,
because it is automatically reset if a falling edge of a start bit is detected.
■ LIN-UART2, UART3 Interrupts and EI2OS
Table 20.5-2 UART2, UART3 Interrupt and EI2OS
Interrupt cause
Interrupt
number
Interrupt control register
Vector table address
EI2OS
Register name
Address
Lower
Upper
Bank
UART2 reception
interrupt
#39(27H)
ICR14
0000BEH
FFFF60H
FFFF61H
FFFF62H
*1
UART2 transmission
interrupt
#40(28H)
ICR14
0000BEH
FFFF5CH
FFFF5DH
FFFF5EH
*2
UART3 reception
interrupt
#39(27H)
ICR14
0000BEH
FFFF60H
FFFF61H
FFFF62H
*3
UART3 transmission
interrupt
#40(28H)
ICR14
0000BEH
FFFF5CH
FFFF5DH
FFFF5EH
*4
*1: EI2OS service for UART2 reception is usable only if UART2 transmission interrupt and both of transmission and
reception interrupt of UART3 are disabled. When detecting receive errors, stop request for EI2OS service is supported.
*2: EI2OS service for UART2 transmission is usable only if UART2 reception interrupt and both of transmission and
reception interrupt of UART3 are disabled.
*3: EI2OS service for UART3 reception is usable only if UART3 transmission interrupt and both of transmission and
reception interrupt of UART2 are disabled. When detecting receive errors, stop request for EI2OS service is supported.
*4: EI2OS service for UART3 transmission is usable only if for UART3 reception interrupt and both of transmission and
reception interrupt of UART2 are disabled.
367
CHAPTER 20 UART2, UART3
■ UART2, UART3 EI2OS Functions
UART2, UART3 has a circuit for operating EI2OS, which can be started up for either reception or
transmission interrupts.
● For UART2 Reception
UART2 shares the interrupt registers with the UART2 transmission interrupts and with UART3 reception
and transmission interrupts. Therefore, EI2OS can be started up only when no UART2 transmission
interrupts and no UART3 reception or transmission interrupts are used.
● For UART2 Transmission
UART2 shares the interrupt registers with the UART2 reception interrupts and with UART3 reception and
transmission interrupts. Therefore, EI2OS can be started up only when no UART2 reception interrupts and
no UART3 reception or transmission interrupts are used.
● For UART3 Reception
UART3 shares the interrupt registers with the UART3 transmission interrupts and with UART2 reception
and transmission interrupts. Therefore, EI2OS can be started up only when no UART3 transmission
interrupts and no UART2 reception or transmission interrupts are used.
● For UART3 Transmission
UART3 shares the interrupt registers with the UART3 reception interrupts and with UART2 reception and
transmission interrupts. Therefore, EI2OS can be started up only when no UART3 reception interrupts and
no UART2 reception or transmission interrupts are used.
368
CHAPTER 20 UART2, UART3
20.5.1
Reception Interrupt Generation and Flag Set Timing
The following are the reception interrupt causes: completion of reception (SSR2/SSR3:
RDRF) and occurrence of a reception error (SSR2/SSR3:PE, ORE, or FRE).
■ Reception Interrupt Generation and Flag Set Timing
The first stop bit detection in mode 0, 1, 2 (SSM = 1), 3, or the last data bit detection in mode 2 (SSM = 0)
will store the reception data into the reception data resisters (RDR2/RDR3). Each flag is set when the data
reception is completed (SSR2/SSR3: RDRF = 1) or a reception error has occurred (SSR2/SSR3: PE, ORE,
FRE = 1). Then, if the reception interrupt is enabled (SSR2/SSR3: RIE = 1) a reception interrupt will be
generated.
Note:
If a reception error has occurred, the Reception Data Register (RDR2/RDR3) contains invalid data in
each mode.
Figure 20.5-1 shows the reception operation and flag set timing.
Figure 20.5-1 Reception Operation and Flag Set Timing
Receive data
(mode 0/3)
ST
D0
D1
D2
....
D5
D6
D7/P
SP
ST
Receive data
(mode 1)
ST
D0
D1
D2
....
D6
D7
AD
SP
ST
D2
....
D5
D6
D7
D0
Receive data
(mode 2)
D0
D1
D4
PE *1, FRE
RDRF
ORE *2
(if RDRF = 1)
reception interrupt occurs
*1: The PE flag will always remain "0" in mode 1 or 3.
*2: ORE only occurs, if the reception data is not read by the CPU (RDRF = 1) and
another data frame is read.
ST: Start bit
SP: Stop bit
AD: Mode 1 (multi processor) address/data selection bit
Note:
The example in Figure 20.5-1 does not show all possible reception options for mode 0 and 3. Here it
is: "7p1" and "8N1" (p = "E" [even] or "O" [odd]).
369
CHAPTER 20 UART2, UART3
Figure 20.5-2 ORE Set Timing
Receive
data
RDRF
ORE
370
CHAPTER 20 UART2, UART3
20.5.2
Transmission Interrupt Generation and Flag Set Timing
A transmission interrupt is generated when the transmission data is transferred from
transmission data register (TDR2/TDR3) to transmission shift register and started.
■ Transmission Interrupt Generation and Flag Set Timing
A transmission interrupt is generated, when the next data to be sent is ready to be written to the
Transmission Data Register (TDR2/TDR3), i. e. the TDR2/TDR3 is empty, and the transmission interrupt
is enabled by setting the Transmission Interrupt Enable (TIE) bit of the Serial Status Register (SSR2/SSR3)
to "1".
The Transmission Data Register Empty (TDRE) flag bit of the SSR2/SSR3 indicates an empty TDR2/
TDR3. Because the TDRE bit is "read only", it only can be cleared by writing data into TDR2/TDR3.
The following figure demonstrates the transmission operation and flag set timing for the four modes of
UART2, UART3.
Figure 20.5-3 Transmission Operation and Flag Set Timing
transmission interrupt occurs
transmission interrupt occurs
Mode 0, 1, 2 (SSM=1) or 3:
write to TDR2/TDR3
TDRE
serial output
ST D0 D1 D2 D3 D4 D5 D6 D7
transmission interrupt occurs
P SP ST D0 D1 D2 D3 D4 D5 D6 D7 P SP
AD
AD
transmission interrupt occurs
Mode 2 (SSM = 0):
write to TDR2/TDR3
TDRE
serial output
ST: Start bit
D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4
D0 ... D7: data bits
P: Parity
SP: Stop bit
AD: Address/data selection bit (mode1)
Note:
The example in Figure 20.5-3 does not show all possible transmission options for mode 0. Here it is:
"8p1" (p = "E" [even] or "O" [odd]). Parity is not provided in mode 3 or 2, if SSM = 0.
371
CHAPTER 20 UART2, UART3
■ Transmission Interrupt Request Generation Timing
If the TDRE flag is set to "1" when a transmission interrupt is enabled (SSR2/SSR3: TIE=1), transmission
interrupt request is generated.
Note:
A transmission completion interrupt is generated immediately after the transmission interrupt is
enabled (TIE=1) because the TDRE bit is set to "1" as its initial value. TDRE is a read-only bit that
can be cleared only by writing new data to the transmission data register (TDR2/TDR3). Carefully
specify the transmission interrupt enable timing.
372
CHAPTER 20 UART2, UART3
20.6
UART2, UART3 Baud Rates
One of the following can be selected for the UART2, UART3 serial clock source:
• Dedicated baud rate generator (Reload Counter)
• External clock as it is (clock input to the SCK2/SCK3 pin)
• External clock connected to the baud rate generator (Reload Counter)
■ UART2, UART3 Baud Rate Selection
Table 20.6-1 shows the select circuit of the baud rate. One of the following three types of baud rates can be
selected:
● Baud rates determined using the dedicated baud rate generator (reload counter)
UART2, UART3 has two independent internal reload counters for transmission and reception serial clock.
The baud rate can be selected via the 15-bit reload value determined by the Baud Rate Generator Register 0
and 1 (BGR02/BGR03 and BGR12/BGR13).
The reload counter divides the machine clock by the value set in the Baud Rate Generator Register 0 and 1.
These baud rates are used in asynchronous mode or synchronous mode (master). To set the clock source,
select the internal clock and the use of the baud rate generator clock (SMR2/SMR3:EXT=0, OTO=0).
● Baud rates determined using external clock (one-to-one mode)
The clock input from UART2, UART3 clock pulse input pins (SCK2/SCK3) is used as it is (synchronous).
Any baud rate less than the machine clock divided by 4 and is divisible can be set externally. These baud
rates are used in synchronous mode (slave). To set the clock source, select the external clock and its direct
use (SMR2/SMR3:EXT=1, OTO=1).
● Baud rates determined using the dedicated baud rate generator with external clock
An external clock source can also be connected internally to the reload counter. In this mode it is used
instead of the internal machine clock. Baud rates can be selected by setting baud rate generator registers 1
and 0 (BGR02/BGR03, BGR12/BGR13) to 15-bit reload values. The reload counter divides the external
clock frequency by the set value. These baud rates are used in asynchronous mode. To set the clock source,
select the external clock and the use of the baud rate generator clock (SMR2/SMR3:EXT=1, OTO=0). This
was designed to use quartz oscillators with special frequencies and having the possibility to divide them.
373
CHAPTER 20 UART2, UART3
Figure 20.6-1 Baud Rate Selection Circuit (Reload Counter)
REST
Start bit falling
edge detected
Reload Value: v
Rxc = 0?
Reception
15-bit Reload Counter
set
FF
Reload
Rxc = v/2?
0
Reception
Clock
reset
1
Reload Value: v
Machine clock
0
SCK2/SCK3
(external
clock
input)
EXT
Txc = 0?
Transmission
15-bit Reload Counter
1
Count Value: Txc
set
Txc = v/2?
OTO
FF
Reload
0
reset
1
Transmission
Clock
Internal data bus
EXT
REST
OTO
374
SMR2/
SMR3
register
BGR14
BGR13
BGR12
BGR11
BGR10
BGR9
BGR8
BGR12/
BGR13
register
BGR7
BGR6
BGR5
BGR4
BGR3
BGR2
BGR1
BGR0
BGR02/
BGR03
register
CHAPTER 20 UART2, UART3
20.6.1
Setting the Baud Rate
This section describes how the baud rates are set and the resulting serial clock
frequency is calculated.
■ Calculating the Baud Rate
Both 15-bit reload counters are programmed by the baud rate generator registers 0, 1 (BGR02/03 and
BGR12/13). The following formula shall be used to set the desired baud rate:
Reload Value:
v = [φ / b] - 1
where φ is the machine clock, b the baud rate and [] gaussian brackets (mathematical rounding function).
● Example of calculation
If the CPU clock is 16 MHz and the desired baud rate is 19200 bps baud then the reload value v is:
v = [16 × 106 / 19200] - 1 = 832
The exact baud rate can then be recalculated: bexact = φ / (v + 1), here it is: 16 × 106 / 833 = 19207.6831
Note:
Setting the reload value to "0" stops the reload counter. For this reason the minimum division ratio is
2. For asynchronous communication, the reload value must be greater than equal to 4 because 5
times over-sampling is performed internally.
375
CHAPTER 20 UART2, UART3
■ Suggested Division Ratios for Different Machine Speeds and Baud Rates
The following settings are suggested for different MCU clock speeds and baud rates:
Table 20.6-1 Suggested Baud Rates and Reload Values at Different Machine Speeds
Baud
rate
(bps)
8 MHz
10 MHz
16 MHz
20 MHz
24 MHz
value
dev.
value
dev.
value
dev.
value
dev.
value
dev.
4M
-
-
-
-
-
-
4
0
5
0
2M
-
-
4
0
7
0
9
0
11
0
1M
7
0
9
0
15
0
19
0
23
0
500000
15
0
19
0
31
0
39
0
47
0
460800
-
-
-
-
-
-
-
-
51
-0.16
250000
31
0
39
0
63
0
79
0
95
0
230400
-
-
-
-
-
-
-
-
103
-0.16
153600
51
-0.16
64
-0.16
103
-0.16
129
-0.16
155
-0.16
125000
63
0
79
0
127
0
159
0
191
0
115200
68
-0.64
86
0.22
138
0.08
173
0.22
207
-0.16
76800
103
-0.16
129
-0.16
207
-0.16
259
-0.16
311
-0.16
57600
138
0.08
173
0.22
277
0.08
346
-0.06
416
0.08
38400
207
-0.16
259
-0.16
416
0.08
520
0.03
624
0
28800
277
0.08
346
<0.01
554
-0.01
693
-0.06
832
-0.03
19200
416
0.08
520
0.03
832
-0.03
1041
0.03
1249
0
10417
767
<0.01
959
<0.01
1535
<0.01
1919
<0.01
2303
<0.01
9600
832
0.04
1041
0.03
1666
0.02
2083
0.03
2499
0
7200
1110
<0.01
1388
<0.01
2221
<0.01
2777
<0.01
3332
<0.01
4800
1666
0.02
2082
-0.02
3332
<0.01
4166
<0.01
4999
0
2400
3332
<0.01
4166
<0.01
6666
<0.01
8332
<0.01
9999
0
1200
6666
<0.01
8334
0.02
13332
<0.01
16666
<0.01
19999
0
600
13332
<0.01
16666
<0.01
26666
<0.01
-
-
-
-
300
26666
<0.01
-
-
-
-
-
-
-
-
Notes:
• Deviations (dev.) are given in %.
• Maximum Synchronous Baud Rate: MCU-Clock div. by 5.
376
CHAPTER 20 UART2, UART3
■ Using External Clock
If the EXT bit of the SMR2/SMR3 is set, an external clock is selected, which has to be connected to the
SCK2/SCK3 pin. The external clock is used in the same way as the machine clock to the baud rate reload
counter.
If One-to-one External Clock Input Mode (SMR2/SMR3:OTO) is selected the SCK2/SCK3 signal is
directly connected to the UART2, UART3 serial clock inputs. This is needed for the UART2, UART3
synchronous mode 2 operating as slave device.
Note, that in any case the resulting clock signal is synchronized to the machine clock in the UART2,
UART3 module. This means that indivisible clock rates will result in phase unstable signals.
■ Counting Example
Assume the reload value is 832. The Figure 20.6-2 demonstrates the behavior of both Reload Counters.
Figure 20.6-2 Counting Example of the Reload Counters
Transmission/
Reception Clock
Reload
Count
001
000
832
831
830
829
828
827
reload count value
Transmission/
Reception Clock
Reload
Count
418
417
416
415
414
413
412
411
Note:
The falling edge of the Serial Clock Signal always occurs | (v + 1) / 2 | machine clock cycles after the
rising edge.
377
CHAPTER 20 UART2, UART3
20.6.2
Reload Counter
This is the 15-bit reload counter that works as a dedicated baud rate generator, and
generates the transmission/reception clock through the external or internal clock.
In addition, it can read the value of the transmission reload counter from the baud rate
generator registers (BGR02/BGR03, BGR12/BGR13).
■ Function of the Reload Counter
The reload counter has a transmission and reception reload counters that works as the dedicated baud rate
generator. It consists of the 15-bit resister for the reload value, and generates the transmission/reception
clock through the external or internal clock. In addition, it can read the value of the transmission reload
counter from the baud rate generator registers (BGR02/BGR03, BGR12/ BGR13).
■ Start of the Count
When a reload value is written into the baud rate generator registers (BGR02/BGR03, BGR12/BGR13), the
reload counter starts counting.
■ Restarting the Reload Counter
The Reload Counters can be restarted of the following reasons:
Transmission and reception reload counter:
• Global MCU reset
• UART2, UART3 programmable clear (SMR2/SMR3:UPCL bit)
• User programmable restart (SMR2/SMR3:REST bit)
Reception reload counter:
• Automatic restart (Start bit falling edge detection in asynchronous mode)
● Programmable Restart
If the REST bit of the Serial Mode Register (SMR2/SMR3) is set by the user, both Reload Counters are
restarted at the next clock cycle. This feature is intended to use the Transmission Reload Counter as a small
timer.
The following figure illustrates a possible usage of this feature (assume that the reload value is 100.)
378
CHAPTER 20 UART2, UART3
Figure 20.6-3 Reload Counter Restart Example
MCU
Clock
Reload
Counter
Clock
Outputs
REST
Reload
Value
37
36
35
100
99
98
97
96
95
94
93
92
91
90
89
88
87
Read
BGR02/03, BGR12/BGR13
Data
Bus
90
: don’t care
In this example the number of MCU clock cycles (cyc) after REST is then:
cyc = v - c + 1 = 100 - 90 + 1 = 11
where v is the reload value and c is the read counter value.
Note:
If UART2, UART3 is reset by setting SMR2/SMR3:UPCL, the Reload Counters will restart too.
● Automatic restart (reception reload counter only)
In asynchronous UART2, UART3 mode if a falling edge of a start bit is detected the Reception Reload
Counter is restarted. This is intended to synchronize the serial input shifter to the incoming serial data
stream.
■ Clearing Reload Counters
The baud rate Generator register (BGR02/03 and BGR12/13) and the baud rate reload counters are cleared
to "0" by the MCU global reset and the counters stop. The reload counters are cleared to "0" by writing "1"
to the UPCL bit in the SMR2/SMR3 register. However the value stored in the reload register is kept
unchanged and the counters start from reload value immediately. Writing "1" to the REST bit does not clear
the counters and they restart from reload value immediately.
379
CHAPTER 20 UART2, UART3
20.7
Operation of UART2, UART3
UART2, UART3 operates in operation mode 0 for normal bidirectional serial
communication, in mode 2 and 3 in bidirectional communication as master or slave, and
in mode 1 as master or slave in multiprocessor communication.
■ Operation of UART2, UART3
● Operation modes
There are four UART2, UART3 operation modes: modes 0 to 3. As listed in Table 20.7-1, an operation
mode can be selected according to the communication method.
Table 20.7-1 UART2, UART3 Operation Mode
Data length
Operation mode
0
normal mode
1
multiprocessor
2
normal mode
3
LIN mode
parity
disabled
parity
enabled
7 bits or 8 bits
7 bits or 8 bits
+ 1*2
-
8 bits
8 bits
-
Length
of stop
bit
data bit
direction
asynchronous
1 or 2
L/M
asynchronous
1 or 2
L/M
synchronous
0, 1 or 2
L/M
asynchronous
1
L
Synchronization
of mode
*1
*1: means the data bit transfer format: LSB first or MSB first
*2: "+1" means the indicator bit of the address/data selection in the multiprocessor mode, instead of
parity.
Note:
Mode 1 operation is supported both for master or slave operation of UART2, UART3 in a master/
slave connection system. In Mode 3 the UART2, UART3 function is locked to 8N1-Format, LSB first.
If the mode is changed, UART2, UART3 cuts off all possible transmission or reception and awaits
then new action.
380
CHAPTER 20 UART2, UART3
■ Inter-CPU Connection Method
External Clock One-to-one connection (normal mode) and master/slave connection (multiprocessor mode)
can be selected. For either connection method, the data length, whether to enable parity, and the
synchronization method must be common to all CPUs. Select an operation mode as follows:
• In the one-to-one connection method, operation mode 0 or 2 must be used in the two CPUs. Select
operation mode 0 for asynchronous transfer mode and operation mode 2 for synchronous transfer mode.
Note, that one CPU has to set to the master and the other to the slave in synchronous mode 2.
• Select operation mode 1 for the master/slave connection method and use it either for the master or slave
system.
■ Synchronization Methods
In asynchronous operation UART2, UART3 reception clock is automatically synchronized to the falling
edge of a received start bit.
• MB90V390H/MB90F394H(A): Start bit detection is level sensitive. This means that a start bit is
detected immediately if SCR2/SCR3:RXE bit is set to "1" while the serial data input SIN2/SIN3 is "0".
A received start bit is memorized even when SCR2/SCR3:RXE bit is set to "0". This causes immediate
start of reception after SCR2/SCR3:RXE bit is set to "1" again. As a workaround, reset UART2,
UART3 by writing "1" to SMR2/SMR3:UPCL bit after setting SCR2/SCR3:RXE bit to "0".
• MB90V390HA/MB90V390HB/MB90394HA: Start bit detection is edge sensitive. This means that a
start bit is not detected before the next falling edge on the serial data input SIN2/SIN3 if SCR2/
SCR3:RXE bit is set to "1" while SIN2/SIN3 is "0". A received start bit is not memorized after SCR2/
SCR3:RXE bit is set to "0". This means that when SCR2/SCR3:RXE bit is set to "1" again, reception
starts when a start bit is detected.
In synchronous mode the synchronization is performed either by the clock signal of the master device or by
UART2, UART3 itself if operating as master.
■ Signal Mode
UART2, UART3 can treat data only in non-return to zero (NRZ) format.
■ Operation Enable Bit
UART2, UART3 controls both transmission and reception using the operation enable bit for transmission
(SCR2/SCR3:TXE) and reception (SCR2/SCR3:RXE).
• If reception operation is disabled during reception (data is input to the reception shift register), finish
frame reception and read the received data of the reception data register (RDR2/RDR3). Then stop the
reception operation.
• If the transmission operation is disabled during transmission (data is output from the transmission shift
register), wait until there is no data in the transmission data register (TDR2/TDR3) before stopping the
transmission operation.
381
CHAPTER 20 UART2, UART3
20.7.1
Operation in Asynchronous Mode (Op. Modes 0 and 1)
When UART2, UART3 is used in operation mode 0 (normal mode) or operation mode 1
(multiprocessor mode), the asynchronous transfer mode is selected.
■ Operation in Asynchronous Mode
● Transfer data format
Generally each data transfer in the asynchronous mode operation begins with the start bit ("L" level on bus)
and ends with at least one stop bit ("H" level). The direction of the bit stream (LSB first or MSB first) is
determined by the BDS bit of the Serial Status Register (SSR2/SSR3). The parity bit (if enabled) is always
placed between the last data bit and the (first) stop bit.
In operation mode 0 the length of the data frame can be 7 bits or 8 bits, with or without parity, and 1 or 2
stop bits.
In operation mode 1 the length of the data frame can be 7 bits or 8 bits with a following address-/dataselection bit instead of a parity bit. 1 or 2 stop bits can be selected.
The calculation formula for the bit length of a transfer frame is:
Length = 1 + d + p + s
(d = number of data bits [7 or 8], p = parity [0 or 1], s = number of stop bits [1 or 2]
Figure 20.7-1 shows the data format in asynchronous mode.
Figure 20.7-1 Transfer Data Format (Operation Modes 0 and 1)
*1
*2
Operation mode 0
ST
D0
D1
D2
D3
D4
D5
D6
D7/P
SP SP
Operation mode 1
ST
D0
D1
D2
D3
D4
D5
D6
D7 A/D
SP
*1: D7 (bit 7) if parity is not provided and data length is 8 bits
P (parity) if parity is provided and data length is 7 bits
*2: only if SBL-bit of SCR3 is set to "1"
ST: Start bit
SP: Stop bit
A/D: Address/data selection bit in mode 1 (multiprocessor mode)
Note:
If BDS bit of the Serial Status Register (SSR2/SSR3) is set to "1" (MSB first), the bit stream
processes as: D7, D6, ..., D1, D0, (P).
During Reception both stop bits are detected, if selected. But the Reception data register full (RDRF) flag
will go "1" at the first stop bit. The bus idle flag (RBI of ECCR2/3) goes "1" after the second stop bit if no
further start bit is detected. (The second stop bit belongs to "bus activity", although it is just mark level.)
382
CHAPTER 20 UART2, UART3
● Transmission operation
If the Transmission Data Register Empty (TDRE) flag bit of the Serial Status Register (SSR2/SSR3) is "1",
transmission data is allowed to be written to the Transmission Data Register (TDR2/TDR3). When data is
written, the TDRE flag goes "0". If the transmission operation is enabled by the TXE-Bit ("1") of the Serial
Control Register (SCR2/SCR3), the data is written next to the transmission shift register and the
transmission starts at the next clock cycle of the serial clock, beginning with the start bit. Thereby the
TDRE flag goes "1", so that new data can be written to the TDR2/TDR3.
If transmission interrupt is enabled (TIE = 1), the interrupt is generated by the TDRE flag. Note, that the
initial value of the TDRE flag is "1", so that in this case if TIE is set to "1" an interrupt will occur
immediately.
When the data length is set to 7 bits (CL=0), the unused bit of the TDR2/TDR3 is always the MSB,
independently from the transfer direction setting in the BDS bit (LSB first or MSB first).
Note:
Because the initial value of the transmission data empty flag bit (SSR2/SSR3:TDRE) is "1",
if the transmission interrupt is enabled (SSR2/SSR3:TIE=1), an interrupt generates immediately.
● Reception operation
Reception operation is performed when it is enabled by the Reception Enable (RXE) flag bit of the SCR2/
SCR3. If a start bit is detected, a data frame is received according to the format specified by the SCR2/
SCR3. In case of errors, the corresponding error flags are set (PE, ORE, FRE). After the reception of the
data frame the data is transferred from the reception shift register to the Reception Data Register (RDR2/
RDR3) and the Receive Data Register Full (RDRF) flag bit of the SSR2/SSR3 is set to "1". The data then
has to be read by the CPU. By doing so, the RDRF flag is cleared. If reception interrupt is enabled (RIE =
1), the interrupt is simply generated by the RDRF. To read received data, check the error flag status upon
completion of reception of one-frame data and, if the data has been received normally, read the received
data from the Reception Data Register (RDR2/RDR3). If a reception error has occurred, perform error
handling.
When the data length is set to 7 bits (CL=0), the unused bit of the RDR2/RDR3 is always the MSB,
independently from the transfer direction setting in the BDS bit (LSB first or MSB first).
Note:
Only when the RDRF flag bit is set and no errors have occurred the Reception Data Register (RDR2/
RDR3) contains valid data.
● Used clock
Use the internal clock or external clock. Select the baud rate generator (SMR2/SMR3: EXT = 0 or 1, OTO =
0) for desired baud rate.
● Stop bit
One or two stop bits can be selected at transmission. If two stop bits are selected, both of the stop bits are
detected at reception. Upon detection of the first stop bit, the reception data register full flag (SSR2/
SSR3:RDRF) is set to "1". If no start bit is detected subsequently, the reception bus idle flag (ECCR2/
ECCR3:RBI) is set to "1" to indicate no reception.
383
CHAPTER 20 UART2, UART3
● Error detection
In mode 0, parity, overrun, and frame errors can be detected. In mode 1, overrun and frame errors can be
detected; parity errors cannot be detected though.
● Parity
The addition and detection of a parity bit can be set (for transmission and reception, respectively). Use the
parity enable bit (SCR2/SCR3:PEN) to enable or disable parity and the parity selection bit (SCR2/SCR3:P)
to select even or odd parity. Parity cannot be used in operation mode 1.
Figure 20.7-2 Data Transmitted with Parity Enabled
SIN
SP
ST
Parity error during
reception with even parity
(SCR2/SCR3: P=0)
1 0 1 1 0 0 0 0 0
SOT
ST
SP
Transmission of even parity
(SCR2/SCR3: P=0)
SP
Transmission of odd parity
(SCR2/SCR3: P=1)
1 0 1 1 0 0 0 0 1
SOT
ST
1 0 1 1 0 0 0 0 0
Data
Parity
ST: Start bit SP: Stop bit Parity enabled (PEN=1)
Note: Parity cannot be used in operation mode 1.
● Data signaling method
NRZ data format.
● Data transfer method
LSB-first or MSB-first mode can be selected as the data bit transfer method.
384
CHAPTER 20 UART2, UART3
20.7.2
Operation in Synchronous Mode (Operation Mode 2)
The clock synchronous transfer method is used for UART2, 3 operation mode 2 (normal
mode).
■ Operation in Synchronous Mode (Operation Mode 2)
● Transfer data format
In the synchronous mode, 8-bit data is transferred without start or stop bits if the SSM bit of the Extended
Communication Control Register (ECCR2/ECCR3) is "0". When the start/stop bits are used (ECCR2/
ECCR3:SSM=1), in addition, it can be selected to enable or disable the parity bit (SCR2/SCR3:PEN).
The figure below illustrates the data format during a transmission in the synchronous operation mode.
Figure 20.7-3 Transfer Data Format (Operation Mode 2)
Reception or transfer data
(ECCR2/ECCR3:SSM=0, SCR2/SCR3:PEN=0)
D0
D1
D2
D3
D4
D5
D6
D7
Reception or transfer data
(ECCR2/ECCR3:SSM=1, SCR2/SCR3:PEN=0)
ST
D0
D1
D2
D3
D4
D5
D6
D7
SP SP
Reception or transfer data
(ECCR2/ECCR3:SSM=1, SCR2/SCR3:PEN=1)
ST
D0
D1
D2
D3
D4
D5
D6
D7
P
*
*
SP SP
* only if SBL bit of SCR2/SCR3 is set to "1"
ST: Start bit
SP: Stop bit
P : Parity bit
● Clock inversion and start/stop bits in mode 2
If the SCES bit of the Extended Status/Control Register (ESCR2/ESCR3) is set the serial clock is inverted.
Therefore in slave mode UART2, UART3 samples the data bits at the falling edge of the received serial
clock. Note, that in master mode if SCES is set the clock signal’s mark level is "0". If the SSM bit of the
Extended Communication Control Register (ECCR2/ECCR3) is set the data format gets additional start and
stop bits like in asynchronous mode.
Figure 20.7-4 Transfer Data Format with Clock Inversion
mark level
reception or transmission clock
(SCES = 0, CCO = 0):
reception or transmission clock
(SCES = 1, CCO = 0):
data stream (SSM = 1)
(here: no parity, 1 stop bit)
mark level
ST
SP
data frame
385
CHAPTER 20 UART2, UART3
● Clock supply
In clock synchronous mode (normal), the number of clock cycles for the clock signal must be the same as
the number of transmission and reception bits for the data including start and stop bits. If the MS bit of the
ECCR2/ECCR3 register is "0" (master mode) and the SCKE bit of the SMR2/SMR3 register is "1" (serial
clock output enabled), the consistent clock cycles are generated automatically. If the MS bit of the ECCR2/
ECCR3 register is "1" (slave mode), or if serial clock output is disabled (SMR2/SMR3: SCKE = 0), clocks
equivalent to each block of bits of transmit/receive data are required to be externally provided. While there
is no communication, the clock signal must be kept at "H" as the mark level.
If the SCDE bit of the ECCR2/ECCR3 register is "1", the clock output signal is delayed. The amount of
this delay is different between MB90V390H/MB90F394H(A) and MB90V390HA/MB90V390HB/
MB90394HA.
MB90V390H/MB90F394H(A): If the SCDE bit of the ECCR2/ECCR3 register is "1", the clock output
signal is delayed by one machine clock cycle.
MB90V390HA/MB90V390HB/MB90394HA: If the SCDE bit of the ECCR2/ECCR3 register is "1", the
clock output signal is delayed by the half of the serial clock cycle as shown in Figure 20.7-5.
The operation is prepared for communication devices which use the rising or falling edge of the serial clock
signal for the data sampling.
Figure 20.7-5 Delayed Transmitting Clock Signal (SCDE=1)
Transmission data
writing
Reception data sample edge (SCES = 0)
Transmitting or
receiving clock
(normal)
Mark level
Mark level
Transmitting
clock (SCDE = 1)
Transmission and
reception data
Mark level
0
1
1
0
LSB
1
0
Data
0
1
MSB
If the SCES bit of the ESCR2/ESCR3 register is "1", the serial clock signal is inverted. Receiving data is
sampled at the falling edge of the serial clock.
If the MS bit of the ECCR2/ECCR3 register is "0" (master mode) and the SCKE bit of the SMR2/SMR3
register is "1" (clock output enabled), the output clock signal is also inverted.
While there is no communication, the clock signal must be kept at "0" as the mark level.
If the CCO bit of the ESCR2/ESCR3 register is "1", the serial clock is signaled even while there is no data
communication. Therefore it is recommended to specify the start/stop bits as shown in Figure 20.7-6.
Figure 20.7-6 Continuous Clock Output in Mode 2
reception or transmission clock
(SCES = 0, CCO = 1):
reception or transmission clock
(SCES = 1, CCO = 1):
data stream (SSM = 1)
(here: no parity, 1 stop bit)
ST
SP
data frame
386
CHAPTER 20 UART2, UART3
● Error detection
If no start/stop bits are selected (ECCR2/ECCR3: SSM = 0) only overrun errors are detected.
● Communication
For initialization of the synchronous mode, following settings have to be done:
Baud rate generator registers (BGR02/BGR03 and BGR12/BGR13):
Set the desired reload value for the dedicated baud rate reload counter.
Serial mode control register (SMR2/SMR3):
MD1, MD0: "10B" (Mode 2)
SCKE:
"1" for the dedicated Baud Rate Reload Counter
"0" for external clock input
SOE:
"1" for transmission and reception
"0" for reception only
Serial control register (SCR2/SCR3):
RXE, TXE: set one or both of these flags to "1"
A/D:
no Address/Data selection - don’t care
CL:
automatically fixed to 8-bit data - don’t care
CRE:
"1" to clear error flags and suspend reception.
-- when SSM=0 (default):
PEN, P, SBL: don’t care
-- when SSM=1:
PEN: "1" if parity bit is added/detected, "0" if not
P:
"1" for even parity, "0" odd parity
SBL:
"1" for 2 stop bits, "0" for 1 stop bit.
Serial status register (SSR2/SSR3):
BDS:
"0" for LSB first, "1" for MSB first
RIE:
"1" if interrupts are used; "0" reception interrupts are disabled.
TIE:
"1" if interrupts are used; "0" transmission interrupts are disabled.
Extended communication control register (ECCR2/ECCR3):
SSM: "0" if no start/stop bits are desired (normal); "1" for adding start/stop bits (extended function)
MS:
"0" for master mode (UART2, UART3 generates the serial clock); "1" for slave mode (UART2,
UART3 receives serial clock from the master device)
Note:
To start the communication, write the data into the transmission data resister (TDR2/TDR3).
If you just want to receive the data, disable the serial output (SMR2/SMR3: SOE = 0) and write a
dummy data to TDR2/TDR3.
Allowing the continuous clock and start/stop bits will enable a bidirectional communication like the
asynchronous mode.
387
CHAPTER 20 UART2, UART3
20.7.3
Operation with LIN Function (Operation Mode 3)
UART2, UART3 can be used either as LIN-Master or LIN-Slave. For this LIN function a
special mode is provided. Setting the UART2, UART3 to mode 3 configures the data
format to 8N1-LSB-first format.
■ Operation in Asynchronous LIN Mode (Operation Mode 3)
● UART2, UART3 as LIN master
In LIN master mode the master determines the baud rate of the whole sub bus, therefore slave devices have
to synchronize to the master. Therefore the desired baud rate remains fixed in master operation after
initialization.
Writing a "1" into the LBR bit of the Extended Communication Control Register (ECCR2/ECCR3)
generates a 13 - 16 bit time low-level on the SOT2/SOT3 pin, which is the LIN synchronization break and
the start of a LIN message. Thereby the TDRE flag of the Serial Status Register (SSR2/SSR3) goes "0". If
valid data does not exist in the transmission data register (TDR2/TDR3), this bit is reset to "1" after the
break, and generates a transmission interrupt for the CPU (if TIE of SSR2/SSR3 is "1").
The length of the Synchronization break to be sent can be determined by the LBL1/LBL0 bits of the
ESCR2/ESCR3 as follows:
Table 20.7-2 LIN Break Length
LBL1
LBL0
Length of Break
0
0
13 Bit times
0
1
14 Bit times
1
0
15 Bit times
1
1
16 Bit times
The Synch Field is sent as byte data of 55H after the LIN break. The 55H can be written to the TDR2/TDR3
just after writing the "1" to the LBR bit, although the TDRE flag is "0".
388
CHAPTER 20 UART2, UART3
● UART2, UART3 as LIN slave
In LIN slave mode UART2, UART3 has to synchronize to the master’s baud rate. If Reception is disabled
(RXE = 0) but LIN break Interrupt is enabled (LBIE = 1) UART2, UART3 will generate a reception
interrupt, if a synchronization break from the LIN master is detected, and indicates it with the LBD flag of
the ESCR2/ESCR3. Writing "0" to this bit clears the reception interrupt request. The LIN slave may need
to calculate the baud rate from the synch field. In this case, the time between the first falling edge to the
fifth falling edge of the synch field is measured by the input capture module. For this purpose, the input
capture module is connected to the LIN-UART2, UART3 with an internal signal. This internal signal
changes from "0" to "1" at the first falling edge then "1" to "0" at the fifth falling edge. Therefore the input
capture module should be set to detect both rising and falling edge. Also the input signal from the LINUART2, UART3 should be selected. The time measured by the input capture module represents 8 times of
the baud rate clock cycle.
Therefore, baud rate setting value is summarized as follows:
without free run timer overflow : BGR value = {(b-a)×Fe/(8×φ)}-1
with free run timer overflow
: BGR value = {(max+b-a)×Fe/(8×φ)}-1
where max is the free run timer maximum value at the overflow occurs.
where a is the value of the ICU data register after the first Interrupt
where b is the value of the ICU data register after the second Interrupt
where φ is the machine clock frequency (MHz).
where Fe is the external clock frequency (MHz). When the internal baud rate generator is used
(EXT=0), it calculates as Fe=φ.
Note:
Do not set the baud rate if the BGR value newly calculated from the Synch field in LIN slave mode
as above has an error from the baud rate by ±15% or more.
For the correspondence between other UARTs and ICUs, see Section "13.3 16-bit Free-run Timer" and
Section "13.5 Input Capture".
389
CHAPTER 20 UART2, UART3
● LIN Synch Break Detection Interrupt and Flags
If a LIN Synch synchronization break is detected in the slave mode, the LIN Break Detected (LBD) Flag of
the ESCR2/ESCR3 is set to "1". This causes an interrupt, if the LIN Break Interrupt Enable (LBIE) bit is
set.
Figure 20.7-7 LIN Synch Break Detection and Flag Set Timing
Serial clock
0
cycle#
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Serial
clock
Serial
Input
(LIN bus)
MB90V390HA/
MB90V390HB/
MB90394HA
FRE
(RXE=1)
MB90V390H/
MB90F394H(A)
LBD
(RXE=0)
Reception interrupt occurs, if RXE=1
Reception interrupt occurs, if RXE=0
The figure above demonstrates the LIN synch break detection and flag set timing.
Note, that if reception is enabled (RXE = 1) and reception interrupt is enabled (RIE = 1) the Reception Data
Framing Error (FRE) flag bit of the SSR2/SSR3 will cause a reception interrupt 2 bit times ("8N1") earlier
than the LIN break interrupt, so it is recommended to turn off RXE, if a LIN break is expected.
MB90V390H/MB90F394H(A):
LBD is only supported in operation mode 0 and 3. Upon LIN break detection, the reception error flags
(SSR2/SSR3:FRE, SSR2/SSR3:ORE, SSR2/SSR3:PE) and the reception data register full flag (SSR2/
SSR3:RDRF) are cleared.
MB90V390HA/MB90V390HB/MB90394HA:
LBD is only supported in operation mode 3. Upon LIN break detection, the reception error flags (SSR2/
SSR3:FRE, SSR2/SSR3:ORE, SSR2/SSR3:PE) and the reception data register full flag (SSR2/
SSR3:RDRF) are not cleared.
Figure 20.7-8 shows a typical start of a LIN message frame and the behavior of the UART2, UART3.
Figure 20.7-8 UART2, UART3 Behavior as Slave in LIN Mode
Serial
clock
Serial
Input
(LIN bus)
LBR cleared
by CPU
LBD
Internal
ICU
Signal
390
Synch break (e. g. 14 bit)
Synch field
CHAPTER 20 UART2, UART3
● LIN bus timing
Figure 20.7-9 LIN Bus Timing and UART2, UART3 Signals
no clock used
(calibration frame)
old serial clock
new (calibrated) serial clock
ICU count
LIN
bus
(SIN2/SIN3)
RXE
LBD
(IRQ0)
LBIE
Internal
Signal
to ICU
IRQ from
ICU
RDRF
(IRQ0)
RIE
Read
RDR2/RDR3
by CPU
Reception Interrupt
enable
LIN break begins
LIN break detected and Interrupt
IRQ cleared by CPU (LBD -> 0)
LBIE disable
IRQ from ICU
IRQ cleared: Begin of Input Capture
IRQ from ICU
IRQ cleared: Calculate & set new baud rate
Reception enable
Edge of Start bit of Identifier byte
Byte read in RDR2/RDR3
RDR2/RDR3 read by CPU
391
CHAPTER 20 UART2, UART3
20.7.4
Direct Access to Serial Pins
UART2, UART3 allows the user to directly access to the transmission pin (SOT2, SOT3)
or the reception pin (SIN2, SIN3).
■ UART2, UART3 Direct Pin Access
The UART2, UART3 provides the ability for the software to access directly to serial input or output pin.
The states of serial input pins (SIN2/SIN3) can be read via the serial I/O pin direct access bits (ESCR2/
ESCR3:SIOP).
You can set the values of the serial output pins (SOT2/SOT3) arbitrarily by enabling direct write (ESCR2/
ESCR3:SOPE=1) to the serial output pins (SOT2/SOT3), writing "0" or "1" to the serial I/O pin direct
access bits (ESCR2/ESCR3:SIOP), and enabling serial output (SMR2/SMR3:SOE=1).
In LIN mode this function can be used for reading back the own transmission and is used for error handling
if something is physically wrong with the single-wire LIN-bus.
Notes:
• That this access is only possible, if the transmission shift register is empty (i. e. no transmission
activity).
• Write the desired value to the SIOP pin before enabling the output pin access to prevent
undesired output level because SIOP holds the last written value.
• During a Read-Modify-Write operation the SIOP bit returns the actual value of the SOT2/SOT3 pin
in the read cycle instead of the value of SIN2/SIN3 during a normal read instruction.
392
CHAPTER 20 UART2, UART3
20.7.5
Bidirectional Communication Function (Normal Mode)
In operation mode 0 or 2, normal serial bidirectional communication is available. Select
operation mode 0 for asynchronous communication and operation mode 2 for
synchronous communication.
■ Bidirectional Communication Function
The settings shown in Figure 20.7-10 are required to operate UART2, UART3 in normal mode (operation
mode 0 or 2).
Figure 20.7-10 Settings for UART2, UART3 Operation Mode 0 and 2
SCR2/SCR3 , SMR2/SMR3
SSR2/SSR3 , TDR2/TDR3 ,
RDR2/RDR3
ESCR2/ESCR3 ,
ECCR2/ECCR3
"1"
"0"
393
CHAPTER 20 UART2, UART3
● Inter-CPU connection
As shown in Figure 20.7-11, interconnect two CPUs in UART2, UART3 mode 2
Figure 20.7-11 Connection Example of UART2, UART3 Mode 2 Bidirectional Communication
SOT
SOT
SIN
SIN
SCK
Input
Output
CPU-1 (Master)
SCK
CPU-2 (Slave)
● Communication procedures
Communication will start at any timing from the transmission side when the transmission data is ready.
When the reception side received the data, ANS is returned regularly (every 1 byte in the following
example). Figure 20.7-12 shows one example bidirectional communication flowchart.
Figure 20.7-12 Example of Bidirectional Communication Flowchart
(Transmission side)
(Reception side)
Start
Start
Operating mode setting
(either 0 or 2)
Operating mode setting
(match the transmission side)
Set 1-byte data to TDR2/
TDR3 and communicate
Transmission of data
With reception data
NO
YES
With reception data
Read reception data
and process
NO
YES
Read reception data
and process
394
Transmission of data
1-byte data transmission
(ANS)
CHAPTER 20 UART2, UART3
20.7.6
Master/Slave Communication Function (Multiprocessor
Mode)
UART2, UART3 communication with multiple CPUs connected in master/slave mode is
available for both master or slave systems.
■ Master/Slave Communication Function
The settings shown in Figure 20.7-13 are required to operate UART2, UART3 in multiprocessor mode
(operation mode 1).
Figure 20.7-13 Settings for UART2, UART3 Operation Mode 1
SCR2/SCR3 , SMR2/SMR3
SSR2/SSR3 , TDR2/TDR3,
RDR2/RDR3
ESCR2/ESCR3 ,
ECCR2/ECCR3
"1"
"0"
395
CHAPTER 20 UART2, UART3
● Inter-CPU connection
As shown in Figure 20.7-14, a communication system consists of one master CPU and multiple slave CPUs
connected to two communication lines. UART2, UART3 can be used for the master or slave CPU.
Figure 20.7-14 Connection Example of UART2, UART3 Master/Slave Communication
SOT1
SIN1
Master CPU
SOT
SOT
SIN
Slave CPU #0
SIN
Slave CPU #1
● Function selection
Select the operation mode and data transfer mode for master/slave communication as shown in Table 20.73.
Table 20.7-3 Selection of the Master/Slave Communication Function
Operation mode
Data
Master CPU
Address
transmission
and
reception
Data
transmission
and
reception
Mode 1
(transmit/receive
A/D-bit)
Parity
Synchronization
method
None
Asynchronous
Slave CPU
Mode 1
(transmit/receive
A/D-bit)
Stop
bit
Bit
direction
1bit or
2 bits
LSB first
or
MSB first
A/D= 1 + 7bits or 8-bits
address
A/D= 0 + 7bits or 8-bits
data
Communication procedure
When the master CPU transmits address data, communication starts. The A/D bit in the address data is
set to "1", and the communication destination slave CPU is selected. Each slave CPU checks the
address data using a program. When the address data indicates the address assigned to a slave CPU, the
slave CPU communicates with the master CPU.
Figure 20.7-15 shows a flowchart of master/slave communication (multiprocessor mode).
396
CHAPTER 20 UART2, UART3
Figure 20.7-15 Master/Slave Communication Flowchart
(Master CPU)
(Slave CPU)
Start
Start
Set operation mode 1
Set operation mode 1
Set SIN2/SIN3 pin as the
serial data input pin.
Set SOT2/SOT3 pin as the
serial data output pin.
Set SIN2/SIN3 pin as the
serial data input pin.
Set SOT2/SOT3 pin as the
port input pin.
Set 7 or 8 data bits.
Set 1 or 2 stop bits.
Set 7 or 8 data bits.
Set 1 or 2 stop bits.
Set “1” in A/D bit
Set TXE = RXE = 1.
Set TXE = RXE = 1.
Receive Byte
Send Slave Address
Is
A/D bit = 1?
NO
YES
Does
Slave Address
match?
Set “0” in A/D bit.
NO
YES
Communicate with
slave CPU
Is
communication
complete?
Communicate with
master CPU
NO
YES
Communicate
with another
slave CPU?
Is
communication
complete?
NO
YES
NO
YES
Set TXE = RXE = 0.
End
397
CHAPTER 20 UART2, UART3
20.7.7
LIN Communication Function
UART2, UART3 communication with LIN devices is available for both LIN master or LIN
slave systems.
■ LIN-master/slave Communication Function
The settings shown in the figure below are required to operate UART2, UART3 in LIN communication
mode (operation mode 3).
Figure 20.7-16 Settings for UART2, UART3 in Operation Mode 3 (LIN)
SCR2/SCR3, SMR2/SMR3
SSR2/SSR3, TDR2/TDR3,
RDR2/RDR3
ESCR2/ESCR3,
ECCR2/ECCR3
"1"
"0"
● LIN device connection
As shown in the Figure below, a communication system of one LIN-Master device and a LIN-Slave device.
UART2, UART3 can operate both as LIN-Master or LIN-Slave.
Figure 20.7-17 Connection Example of a Small LIN-Bus System
SOT
SOT
LIN bus
SIN
LIN-Master
398
SIN
Single-WireTransceiver
Single-WireTransceiver
LIN-Slave
CHAPTER 20 UART2, UART3
20.7.8
Sample Flowcharts for UART2, UART3 in LIN
Communication (Operation Mode 3)
This section contains sample flowcharts for UART2, UART3 in LIN communication.
■ UART2, UART3 as Master Device
Figure 20.7-18 UART2, UART3 LIN Master Flow Chart
START
Initial setting :
Set operation mode 3
Serial data output enabled
Baud rate setting
Synch break length setting
TXE=1, TIE=0
RXE=1, RIE=1
NO
Send Message?
NO (transmission)
YES (reception)
YES
Wake up?
RDRF=1
NO
Data field reception?
(80H reception)
Reception interrupt
YES
*1
Data 1 reception
Transmission data 1 set :
TDR2/TDR3=Data 1
Transmission interrupt
enabled
RDRF=1
RXE=0
TDRE=1
Reception interrupt
Synch break interrupt enabled
Synch break transmission :
*1
Data N reception
Transmission interrupt
ECCR2/ECCR3 : LBR=1
Transmission data N set :
TDR2/TDR3=Data N
Transmission interrupt
disabled
Synch field transmission :
TDR2/TDR3=55H
LBD=1
RDRF=1
Synch break interrupt
Reception interrupt
Reception enabled
LBD=0
Synch break interrupt disabled
*1
Data 1 reception
Data 1 reading
RDRF=1
RDRF=1
Reception interrupt
Reception interrupt
*1
*1
Synch field reception
Data N reception
Data N reading
Identify field set : TDR2/TDR3=ID
RDRF=1
Reception interrupt
*1
*2
ID field reception
NO
Without error
Error processing
YES
*1: Perform an error processing when an error has occurred.
*2: • If FRE and ORE bits are "1", write "1" to the CRE bit in the SCR to clear the error flag.
• If LBD bit in the ESCR is "1", execute UART reset.
Note: Perform the error detection in each process and give proper care.
399
CHAPTER 20 UART2, UART3
■ UART2, UART3 as Slave Device
Figure 20.7-19 UART2, UART3 LIN Slave Flow Chart
START
Initial setting :
Set operation mode 3
Serial data output enabled
Baud rate setting
Synch break length setting
TXE=1, TIE=0
RXE=0, RIE=1
Connection with UART and ICU
Reception prohibited
ICU interrupt enabled
Synch break interrupt enabled
YES (reception)
LBD=1
RDRF=1
Synch break interrupt
NO (transmission)
Data field
reception?
Reception interrupt
Synch break detection clear
ECCR2/ECCR3 : LBD=0
Synch break interrupt prohibited
*1
Transmission data 1 set
TDR2/TDR3=Data 1
Transmission interrupt
enabled
Data 1 reception
RDRF=1
ICU interrupt
Reception interrupt
TDRE=1
*1
Data N reception
ICU data read
ICU interrupt flag clear
Transmission interrupt
Transmission data N set
TDR2/TDR3=Data N
Transmission interrupt
prohibited
ICU interrupt
Reception prohibited
RDRF=1
ICU data read
Baud rate regulation
Reception enabled
ICU interrupt flag clear
ICU interrupt prohibited
Reception interrupt
*1
Data 1 reception
Data 1 read
RDRF=1
LBD=1
Reception interrupt
Synch break interrupt
*1
*1
Data N reception
Data N read
Reception prohibited
Identify field reception
*2
NO
Error processing
Without error
YES
Sleep mode?
NO
YES
Wake up reception?
NO
YES
Wake up
transmission?
*1: Perform an error processing when an error has occurred.
*2: • If FRE and ORE bits are "1", write "1" to the CRE bit in the SCR to clear the error flag.
• If LBD bit in the ESCR is "1", execute UART reset.
Note: Perform the error detection in each process and give proper care.
400
NO
YES
Wake up code transmission
CHAPTER 20 UART2, UART3
20.8
Notes on Using UART2, UART3
Notes on using UART2, UART3 are given below.
■ Notes on Using UART2, UART3
● Enabling operations
In UART2, UART3, the serial control register (SCR2/SCR3) has TXE (transmission) and RXE (reception)
operation enable bits. Both, transmission and reception operations, must be enabled before the
communication starts because they have been disabled as the default value (initial value). The operation
can also be canceled by disabling these bits.
● Communication mode setting
Set the communication mode while the system is not operating. If the mode is changed during transmission
or reception, the transmission or reception is stopped and possible data will be lost.
● Transmission interrupt enabling timing
The default (initial value) of the transmission data empty flag bit (SSR2/SSR3: TDRE) is "1" (no
transmission data and transmission data write enable state). A transmission interrupt request is generated as
soon as the transmission interrupt request is enabled (SSR2/SSR3: TIE=1). Be sure to set the TIE flag to
"1" after setting the transmission data to avoid an immediate interrupt.
● Start bit synchronization
MB90V390H/MB90F394H(A):
In asynchronous mode, start bit detection is level sensitive. This means that a start bit is detected
immediately if SCR2/SCR3:RXE bit is set to "1" while the serial data input SIN2/SIN3 is "0".
In asynchronous mode, a received start bit is memorized even when SCR2/SCR3:RXE bit is set to "0". This
causes immediate start of reception after SCR2/SCR3:RXE bit is set to "1" again. As a workaround, reset
UART2, UART3 by writing "1" to SMR2/SMR3:UPCL bit after setting SCR2/SCR3:RXE bit to "0".
MB90V390HA/MB90V390HB/MB90394HA:
In asynchronous mode, start bit detection is edge sensitive. This means that a start bit is not detected before
the next falling edge on the serial data input SIN2/SIN3 if SCR2/SCR3:RXE bit is set to "1" while SIN2/
SIN3 is "0".
In asynchronous mode, a received start bit is not memorized after SCR2/SCR3:RXE bit is set to "0". This
means that when SCR2/SCR3:RXE bit is set to "1" again, reception starts when a start bit is detected.
401
CHAPTER 20 UART2, UART3
● Using LIN operation mode 3
The LIN features are available in mode 3 (transmitting, receiving synch break), but using mode 3 sets the
UART2, UART3 data format automatically to LIN format (8N1, LSB first). Note, that the length of the
synch break for transmission is variable but for reception it is fixed 11-bit times.
Note:
During LIN operation, please set SCES bit of ESCR2/ESCR3 register to "0".
● Changing operation settings
It is strongly recommended to reset UART2, UART3 after changing operation settings. Particularly if (for
example) start-/stop-bits added to or removed from the data format.
Note:
If settings in the Serial Mode Register (SMR2/SMR3) are desired, it is not useful to set the UPCL bit
at the same time to reset UART2, UART3. The correct operation settings are not guaranteed in this
case. Thus it is recommended to set the bits of the SMR2/SMR3 and then to set them again plus the
UPCL bit.
● LIN slave settings
Set the baud rate before receiving the first LIN synch break for the slave operation. Otherwise, duration of
the synch break can not be correctly checked against the minimum requirement of the LIN specification (13
master bit time and 11 slave bit time).
● Software compatibility
Although UART2, UART3 is similar to other UARTs in other microcontrollers it is not software
compatible to them. The programming models may be the same, but the structure of the registers differ.
Furthermore the setting of the baud rate is now determined by a reload value instead of selecting a
predefined value.
● Bus idle function
The Bus Idle Function cannot be used in synchronous mode 2 and SSM=0.
402
CHAPTER 20 UART2, UART3
● A/D bit (serial control register (SCR2/SCR3): address/data type select bit)
The behavior of this bit is different between MB90V390H/MB90F394H(A) and MB90V390HA/
MB90V390HB/MB90394HA.
MB90V390H/MB90F394H(A):
• Special care has to be taken when using the A/D bit (Address-Data-Bit for multiprocessor mode 1) of
the Serial Control Register. This bit is both a control and a flag bit, because writing to it sets the A/D bit
for transmission, whereas reading from it returns the last received A/D bit. Internally, the received and
the transmitted value are stored in different registers, but in Read-Modify-Write instructions, the
received value is read, modified and then written back for transmission. This can lead to a wrong value
in the A/D bit, when one of the other bits in the same register is accessed by an instruction of this kind.
Therefore, this bit should be written by the last register access before transmission. Alternatively, using
byte wise access and writing the correct values for all bits at once avoids this problem.
• Furthermore, the A/D bit is not buffered like the transmission data register.
Changing the bit during transmission will alter the A/D bit of the currently transmitted data.
MB90V390HA/MB90V390HB/MB90394HA:
• This bit is both a control and a flag bit, because writing to it sets the A/D bit for transmission, whereas
reading from it returns the last received A/D bit. Internally, the received and the transmitted A/D bit
values are stored in different registers.
The A/D bit of the transmission is read when the RMW system instruction is used, and the received A/D
data is read as for other reading.
• When the TDRE bit becomes "1" from "0" when the transmission operates, the A/D bit for the
transmission is loaded into the transmission shift register with the data of the transmission data register
(TDR2/TDR3). Therefore, set the A/D bit to the A/D bit for the transmission before writing in the
transmission data register (TDR2/TDR3).
● Software reset of UART2/UART3
Perform the software reset (SMR2/SMR3:UPCL=1), when the TXE bit of the SCR2/SCR3 register is "1".
● LIN Synch field wait state
MB90V390H/MB90F394H(A): In modes 0 and 3, the LBD bit in the ESCR2/ESCR3 register is set to "1"
if the serial input is kept at "0" for more than equal to 11-bit times. When LBD is set to "1", the reception
error flags (SSR2/SSR3:FRE, SSR2/SSR3:ORE, SSR2/SSR3:PE) and the reception data register full flag
(SSR2/SSR3:RDRF) are cleared. Then the UART2, UART3 waits for the following synch field to be
received. If the UART2, UART3 is set into this state for other reasons than the synch break, it should be
initialized by the software reset (SMR2/SMR3: UPCL=1).
MB90V390HA/MB90V390HB/MB90394HA: In mode 3 (LIN operation), the LBD bit in the ESCR2/
ESCR3 register is set to "1" if the serial input is kept at "0" for more than equal to 11-bit times. Then the
UART2, UART3 waits for the following synch field to be received. If the UART2, UART3 is set into this
state for other reasons than the synch break, it should be initialized by the software reset (SMR2/
SMR3:UPCL=1).
403
CHAPTER 20 UART2, UART3
404
CHAPTER 21
400 kHz I2C INTERFACE
This section describes the functions and operation of
the fast I2C interface.
Note: The I2C interface is not available in all MB90390
Series devices.
21.1 I2C Interface Overview
21.2 I2C Interface Registers
21.3 I2C Interface Operation
21.4 Programming Flow Charts
405
CHAPTER 21 400 kHz I2C INTERFACE
21.1
I2C Interface Overview
The I2C interface is a serial I/O port supporting the Inter IC bus, operating as a master/
slave device on the I2C bus.
■ Features
• Master/slave transmitting and receiving functions
• Arbitration function
• Clock synchronization function
• General call addressing support
• Transfer direction detection function
• Repeated start condition generation and detection function
• Bus error detection function
• 7 bit addressing as master and slave
• 10 bit addressing as master and slave
• Possibility to give the interface a seven and a ten bit slave address
• Acknowledging upon slave address reception can be disabled (Master-only operation)
• Address masking to give interface several slave addresses (in 7 and 10 bit mode)
• Up to 400 KBytes transfer rate
• Possibility to use built-in noise filters for SDA and SCL
• Can receive data at 400 KBytes if machine clock is higher than 6 MHz regardless of prescaler setting
• Can generate MCU interrupts on transmission and bus error events
• Supports being slowed down by a slave on bit and byte level
The I2C interface does not support SCL clock stretching on bit level since it can receive the full
400 KBytes data rate if the machine clock is higher than 6 MHz regardless of the prescaler setting.
However, clock stretching on byte level is performed since SCL is pulled low during an interrupt (INT = 1
in IBCR register).
406
CHAPTER 21 400 kHz I2C INTERFACE
■ Block Diagram of I2C Interface
Figure 21.1-1 shows the block diagram of the I2C interface.
Figure 21.1-1 Block Diagram of I2C Interface
ICCR
I2C enable
EN
ICCR
Clock Divider 1
2 3 4 5 ... 32
CS4
CS3
5
CS2
5
Clock Selector
Synch
CS1
CS0
Clock Divider 2 (by 12)
SCL Duty Cycle Generator
Shift Clock Generator
IBSR
BB
RSC
LRB
TRX
Bus busy
Repeated start
Bus Observer
Last Bit
Bus Error
Send/receive
ADT
Address Data
AL
Arbitration Loss Detector
ICCR
NSF
Internal data-bus
IBCR
enable
BER
BEIE
MCU
IRQ
Interrupt Request
INTE
INT
Noise
Filter
SCL
SDA
SCL
SDA
IBCR
SCC
MSS
ACK
GCAA
Start
Start-Stop Condition
Generator
Master
ACK enable
ACK Generator
GC-ACK enable
8
IBSR
AAS
GCA
ISMK
ENSB
ITMK
ENTB
RAL
IDAR
8
Slave
General call
enable 7 bit mode
Slave Address
Comparator
enable 10 bit mode
received ad. length
7
10
10
ITBA
ITMK
7
ISBA
ISMK
10
10
7
7
407
CHAPTER 21 400 kHz I2C INTERFACE
I2C Interface Registers
21.2
This section describes the function of the I2C interface registers in detail.
■ I2C Interface Registers
Bus Control Register (IBCR)
Address: bit 15
14
13
12
BER BEIE SCC MSS
0035A1H
11
10
9
ACK GCAA INTE
8
IBCR
INT
Initial value
00000000B
R/W R/W W R/W R/W R/W R/W R/W
Bus Status Register (IBSR)
bit 7
6
5
4
3
BB
RSC
AL
LRB
TRX AAS
R
R
R
R
R
Address:
0035A0H
2
1
0
GCA
ADT
R
R
R
9
8
IBSR
Initial value
0 0 0 0 0 0 0 0B
Ten Bit slave Address register (ITBA)
bit 15
14
13
12
11
10
-
-
-
-
-
-
TA9 TA8
-
-
-
-
-
-
R/W R/W
7
6
5
4
3
2
0035A3H
bit
0035A2 H
1
0
TA7 TA6 TA5 TA4 TA3 TA2 TA1 TA0
ITBAH (upper)
Initial value
00000000
B
ITBAL (lower)
Initial value
0 0 0 0 0 0 0 0B
R/W R/W R/W R/W R/W R/W R/W R/W
Ten bit slave address MasK register (ITMK)
bit 15
0035A5H
13
12
11
10
-
-
-
-
TM9 TM8
R/W R/W -
-
-
-
R/W R/W
4
3
2
ENTB RAL
bit 7
0035A4 H
14
6
5
9
1
8
0
TM7 TM6 TM5 TM4 TM3 TM2 TM1TM0
ITMKH (upper)
Initial value
00111111B
ITMKL (lower)
Initial value
1 1 1 1 1 1 1 1B
R/W R/W R/W R/W R/W R/W R/W R/W
Seven Bit slave Address register (ISBA)
bit 7
0035A6 H
R/W
R
W
-
408
:
:
:
:
Readable and writable
Read only
Write only
Undefined
6
5
4
3
2
1
0
-
SA6 SA5 SA4 SA3 SA2 SA1 SA0
-
R/W R/W R/W R/W R/W R/W R/W
ISBA
Initial value
0 0 0 0 0 0 0 0B
CHAPTER 21 400 kHz I2C INTERFACE
Seven bit slave address MasK register (ISMK)
bit 15
14
13
12
11
10
9
8
ENSB SM6 SM5 SM4 SM3 SM2 SM1SM0
0035A7 H
ISMK
Initial value
0 1 1 1 1 1 1 1B
R/W R/W R/W R/W R/W R/W R/W R/W
Data Register (IDAR)
bit
0035A8H
7
6
5
4
3
2
D7 D6 D5 D4 D3 D2
1
0
D1 D0
IDAR
Initial value
00000000
R/W R/W R/W R/W R/W R/W R/W R/W
B
Clock control register (ICCR)
bit 15
0035AB H
14
13
12
11
10
9
8
-
NSF EN CS4 CS3 CS2 CS1 CS0
-
R/W R/W R/W R/W R/W R/W R/W
ICCR
Initial value
0 0 0 1 1 1 1 1B
Noise filter configuration register (INFCR)
bit 15
0035A9 H
R/W
:
Readable and writable
-
:
Undefined
14
13
12
11
10
9
8
-
-
-
-
-
-
SEL1 SEL0
-
-
-
-
-
-
R/W R/W
INFCR
Initial value
X X X X X X 0 1B
409
CHAPTER 21 400 kHz I2C INTERFACE
21.2.1
Bus Status Register (IBSR)
The bus status register (IBSR) has the following functions:
• Bus busy detection
• Repeated start condition detection
• Arbitration loss detection
• Acknowledge detection
• Data transfer direction indication
• Addressing as slave detection
• General call address detection
• Address data transfer detection
■ Bus Status Register (IBSR)
This register is read-only, all bits are controlled by the hardware. All bits are cleared if the interface is not
enabled (EN = 0 in ICCR).
Figure 21.2-1 Configuration of the Bus Status Register (IBSR)
bit 7
6
5
4
3
BB
RSC
AL
LRB
TRX AAS
R
R
R
R
R
Address:
0035A0H
2
R
1
0
GCA
ADT
R
R
IBSR
Initial value
0 0 0 0 0 0 0 0B
bit 0
ADT
Address data transfer bit
0
Incoming data in not address data (bus not in use)
1
Incoming data is address data
bit 1
GCA
General Call Address bit
0
Generall call address not received as slave
1
General call address received as slave
bit 2
AAS
Addressed as slave bit
0
not addressed as slave
1
Addressed as slave
bit 3
TRX
Tr ansferring data bit
0
Not transmitting data
1
Transmitting data
bit 4
LRB
Last received bit
0
Receiver did not acknowledge
1
Receiver did acknowledge
bit 5
AL
Arbitration loss bit
0
No arbitration loss detected
1
Arbitration loss detected
bit 6
RSC
Repeated start condition bit
0
Repeated start condition not detected
1
Bus in use, repeated start condition detected
bit 7
BB
R
410
Bus busy bit
:
Read only
0
Stop condition detected (bus idle)
:
Initial value
1
Start condition detected (bus in use)
CHAPTER 21 400 kHz I2C INTERFACE
■ Bus Status Register (IBSR) Contents
Table 21.2-1 Function of Each Bit of the Bus Status Register (IBSR) (1/2)
Bit name
Function
bit7
BB:
Bus busy bit
This bit indicates the status of the I2C bus.
"0": Stop condition detected (bus idle)
"1": Start condition detected (bus in use)
This bit is set to "1" if a start condition is detected. It is reset upon a stop condition.
bit6
RSC:
Repeated start
condition bit
This bit indicates detection of a repeated start condition.
"0": Repeated start condition not detected.
"1": Start condition detected (bus in use).
This bit is cleared at the end of an address data transfer (ADT= 0) or detection of a stop
condition.
AL:
Arbitration loss
bit
This bit indicates an arbitration loss.
"0": No arbitration loss detected.
"1": Arbitration loss occurred during master sending.
This bit is cleared by writing "0" to the INT bit or by writing "1" to the MSS bit in the IBCR
register.
An arbitration loss occurs if:
- the data sent does not match the data read on the SDA line at the rising SCL edge
- a repeated start condition is generated by another master in the first bit of a data byte
- the interface could not generate a start or stop condition because another slave pulled the
SCL line low before
LRB:
Last received bit
This bit is used to store the acknowledge message from the receiving side.
"0": Receiver acknowledged.
"1": Receiver did not acknowledge.
It is changed by the hardware upon reception of bit9 (acknowledge bit) and is also cleared
by a start or stop condition.
bit3
TRX:
Transferring data
bit
This bit indicates data sending operation during data transfer.
"0": Not transmitting data.
"1": Transmitting data.
It is set to "1":
- if a start condition was generated in master mode
- at the end of a first byte transfer and read access as slave or sending data as master
It is set to "0" if:
- the bus is idle (BB= 0)
- an arbitration loss occurred
- a "1" is written to the SCC bit during master interrupt (MSS = 1 and INT = 1)
- the MSS bit being cleared during master interrupt (MSS = 1 and INT = 1)
- the interface is in slave mode and the last transferred byte was not acknowledged
- the interface is in slave mode and it is receiving data
- the interface is in master mode and is reading data from a slave
bit2
AAS:
Addressed as
slave bit
This bit indicates detection of a slave addressing.
"0": Not addressed as slave.
"1": Addressed as slave.
This bit is cleared by a (repeated-) start or stop condition. It is set if the interface detects its
seven and/or ten bit slave address.
bit5
bit4
411
CHAPTER 21 400 kHz I2C INTERFACE
Table 21.2-1 Function of Each Bit of the Bus Status Register (IBSR) (2/2)
Bit name
bit1
bit0
412
Function
GCA:
General call
address bit
This bit indicates detection of a general call address (00H).
"0": General call address not received as slave.
"1": General call address received as slave.
This bit is cleared by a (repeated-) start or stop condition.
ADT:
Address data
transfer bit
This bit indicates the detection of an address data transfer.
"0": Incoming data is not address data (or bus is not in use).
"1": Incoming data is address data.
This bit is set to "1" by a start condition. It is cleared after the second byte if a ten bit slave
address header with write access is detected, else it is cleared after the first byte.
"After" the first/second byte means:
- a "0" is written to the MSS bit during a master interrupt (MSS = 1 and INT = 1 in IBCR)
- a "1" is written to the SCC bit during a master interrupt (MSS = 1 and INT = 1 in IBCR)
- the INT bit is being cleared
- the beginning of every byte transfer if the interface is not involved in the current transfer
as master or slave
CHAPTER 21 400 kHz I2C INTERFACE
21.2.2
Bus Control Register (IBCR)
The bus control register (IBCR) has the following functions:
• Interrupt enabling flags
• Interrupt generation flag
• Bus error detection flag
• Repeated start condition generation
• Master / slave mode selection
• General call acknowledge generation enabling
• Data byte acknowledge generation enabling
■ Bus Control Register (IBCR)
Write access to this register should only occur while the INT = 1 or if a transfer is to be started. The user
should not write to this register during an ongoing transfer since changes to the ACK or GCAA bits could
result in bus errors. All bits in this register except the BER and the BEIE bit are cleared if the interface is
not enabled (EN= 0 in ICCR).
413
CHAPTER 21 400 kHz I2C INTERFACE
Figure 21.2-2 Configuration of the Bus Control Register
bit 15
Address:
0035A1H
14
13
12
BER BEIE SCC MSS
11
10
9
ACK GCAA INTE
8
IBCR
INT
Initial value
00000000B
R/W R/W W R/W R/W R/W R/W R/W
bit 8
INT
0
1
Interrupt bit
see table on next page for details
bit 9
INTE
Interrupt enable bit
0
Interrupt disabled
1
Interrupt enabled
bit 10
GCCA
Generall call address acknowledge bit
0
No acknowledge on general call address
1
Acknowledge on general call address
bit 11
ACK
Acknowledge bit
0
No Acknowledge on data byte reception
1
Acknowledge on data byte reception
bit 12
MSS
Master/slave select bit
0
Go to slave mode
1
Go to master mode (s. table below for details)
bit 13
SCC
Start condition continue bit
0
Write: No effect:
1
Write: Generate repeated start condition
bit 14
BEIE
414
R/W
:
Readable and writable
W
:
Write only
:
Initial value
Bus error interrupt enable bit
0
Bus error interrupt disabled
1
Bus error interrupt enabled
bit 15
Bus error bit
BER
write
read
0
Clear bus error int.
No error detected
1
No effect
Error detected
CHAPTER 21 400 kHz I2C INTERFACE
■ Bus Control Register (IBCR) Contents
Table 21.2-2 Function of Each Bit of the Bus Control Register (IBCR) (1/3)
Bit name
Function
bit15
BER:
Bus error bit
This bit is the bus error interrupt flag. It is set by the hardware and cleared by the user.
It always reads "1" in a Read-Modify-Write (RMW) instruction access.
Write access:
"0": Clear bus error interrupt flag
"1": No effect
Read access:
"0": No bus error detected
"1": One of the error conditions described below detected
When this bit is set, the EN bit in the ICCR register is cleared, the I2C interface goes to
pause status, data transfer is interrupted and all bits in the IBSR and the IBCR registers
except BER and BEIE are cleared. The BER bit must be cleared before the interface
may be reenabled.
This bit is set to "1" if:
- start or stop conditions are detected at wrong places: during an address data transfer or
during the transfer of the bits two to nine (acknowledge bit)
- a ten bit address header with read access is received before a ten bit write access
bit14
BEIE:
Bus error
interrupt enable
bit
This bit enables the bus error interrupt. It only can be changed by the user.
"0": Bus error interrupt disabled
"1": Bus error interrupt enabled
Setting this bit to "1" enables MCU interrupt generation when the BER bit is set to "1".
SCC
Start condition
continue bit
This bit is used to generate a repeated start condition. It is write only - it always reads
"0".
"0": No effect
"1": Generate repeated start condition during master transfer
A repeated start condition is generated if a "1" is written to this bit while an interrupt in
master mode (MSS = 1 and INT = 1) and the INT bit is cleared automatically.
bit13
415
CHAPTER 21 400 kHz I2C INTERFACE
Table 21.2-2 Function of Each Bit of the Bus Control Register (IBCR) (2/3)
Bit name
Function
This is the master/slave mode selection bit. It can only be set by the user, but it can be
cleared by the user and the hardware.
"0": Go to slave mode
"1": Go to master mode, generate start condition and send address data byte in IDAR
register. It is cleared if an arbitration loss event occurs during master sending.
bit12
416
MSS:
Master/slave
select bit
If a "0" is written to it during a master interrupt (MSS = 1 and INT = 1), the INT bit is
cleared automatically, a stop condition will be generated and the data transfer ends.
Note that the MSS bit is reset immediately, the generation of the stop condition can be
checked by polling the BB bit in the IBSR register.
If a "1" is written to it while the bus is idle (MSS= 0 and BB= 0), a start condition is
generated and the contents of the IDAR register (which should be address data) is sent.
If a "1" is written to the MSS bit while the bus is in use (BB = 1 and TRX= 0 in IBSR;
MSS= 0 in IBCR), the interface waits until the bus is free and then starts sending.
If the interface is addressed as slave with write access (data reception) in the meantime,
it will start sending after the transfer ended and the bus is free again. If the interface is
sending data as slave in the meantime (AAS = 1 and TRX = 1 in IBSR), it will not start
sending data if the bus of free again. It is important to check whether the interface was
addressed as slave (AAS = 1 in IBSR), sent the data byte successfully (MSS = 1 in
IBCR) or failed to send the data byte (AL = 1 in IBSR) at the next interrupt!
bit11
ACK:
Acknowledge bit
This is the acknowledge generation on data byte reception enable bit. It only can be
changed by the user.
"0": The interface will not acknowledge on data byte reception
"1": The interface will acknowledge on data byte reception
This bit is not valid when receiving address bytes in slave mode - if the interface detects
its 7 or 10 bit slave address, it will acknowledge if the corresponding enable bit (ENTB
in ITMK or ENSB in ISMK) is set.
Write access to this bit should occur during an interrupt (INT = 1) or if the bus is idle
(BB= 0 in the IBSR register) only.
bit10
GCAA:
General call
address
acknowledge bit
This bit enables acknowledge generation when a general call address is received. It only
can be changed by the user.
"0": The interface will not acknowledge on general call address byte reception.
"1": The interface will acknowledge on general call address byte reception.
Write access to this bit should occur during an interrupt (INT = 1) or if the bus is idle
(BB= 0 in IBSR register) or the interface is disabled (EN= 0 in ICCR register) only.
bit9
INTE:
Interrupt enable
bit
This bit enables the MCU interrupt generation. It only can be changed by the user.
"0": Interrupt disabled
"1": Interrupt enabled
Setting this bit to "1" enables MCU interrupt generation when the INT bit is set to "1"
(by the hardware).
CHAPTER 21 400 kHz I2C INTERFACE
Table 21.2-2 Function of Each Bit of the Bus Control Register (IBCR) (3/3)
Bit name
Function
This bit is the transfer end interrupt request flag. It is changed by the hardware and can
be cleared by the user. It always reads "1" in a Read-Modify-Write access.
Write access:
"0": Clear transfer end interrupt request flag
"1": No effect
Read access:
"0": Transfer not ended or not involved in current transfer or bus is idle
"1": Set at the end of a 1-byte data transfer or reception including the acknowledge bit
under the following conditions:
bit8
INT:
Interrupt flag bit
- Device is bus master.
- Device is addressed as slave.
- General call address received.
- Arbitration loss occurred.
Set at the end of an address data reception (after first byte if seven bit address received,
after second byte if ten bit address received) including the acknowledge bit if the device
is addressed as slave.
While this bit is "1" the SCL line will hold an "L" level signal. Writing "0" to this bit
clears the setting, releases the SCL line, and executes transfer of the next byte or a
repeated start or stop condition is generated. Additionally, this bit is cleared if a "1" is
written to the SCC bit or the MSS bit is being cleared.
417
CHAPTER 21 400 kHz I2C INTERFACE
■ SCC, MSS and INT Bit Competition
Simultaneously writing to the SCC, MSS and INT bits causes a competition to transfer the next byte, to
generate a repeated start condition or to generate a stop condition. In these cases the order of priority is as
follows:
• Next byte transfer and stop condition generation.
When "0" is written to the INT bit and "0" is written to the MSS bit, the MSS bit takes priority and a
stop condition is generated.
• Next byte transfer and start condition generation.
When "0" is written to the INT bit and "1" is written to the SCC bit, the SCC bit takes priority. A
repeated start condition is generated and the contents of the IDAR register is sent.
• Repeated start condition generation and stop condition generation.
When a "1" is written to the SCC bit and "0" to the MSS bit, the MSS bit clearing takes priority. A stop
condition is generated and the interface enters slave mode.
Notes:
• Note on using MB90F394H(A), MB90V390H only.
If there are some other master mode LSIs on the bus, the device can not be used as the master
mode.
- Example of usable configuration
I2C bus
MB90F394H
MB90V390H
Slave A
Slave B
Master
I2C bus
MB90F394H
MB90V390H
Slave A
Master A
Slave
- Example of unusable configuration
I2C bus
MB90F394H
MB90V390H
Master
418
Slave A
Master A
CHAPTER 21 400 kHz I2C INTERFACE
• Note on using the devices except MB90F394H(A) and MB90V390H.
If the device is used in the following condition, it cannot receive as slave. So, sending general call
address is prohibited.
- Condition that there is other master mode LSI on the bus without MB90390 series, and
MB90390 series transmit the general-call address as master, and the arbitration lost occurs
after second byte.
• When an instruction which generates a start condition is executed (the MSS bit is set to "1") at the
timing shown in Figure 21.2-3 and Figure 21.2-4, arbitration lost detection (AL bit = 1) prevents an
interrupt (INT bit = 1) from being generated.
- Condition 1 in which an interrupt (INT bit = 1) upon detection of " AL bit = 1 " does not occurs
When an instruction which generates a start condition is executed (setting the MSS bit in the
IBCR register to 1) with no start condition detected (BB bit = 0) and with the SDA or SCL pin at
the " L " level.
Figure 21.2-3 Diagram of Timing at which an Interrupt Upon Detection of " AL Bit = 1 " does not Occurs
SCL pin
SCL pin or SDA pin is Low level.
SDA pin
"L"
"L"
I2C operation enable state (EN bit =1)
Master mode setting (MSS bit = 1)
1
Arbitration lost detection (AL bit = 1)
Bus busy (BB bit)
0
Interruption (INT bit)
0
419
CHAPTER 21 400 kHz I2C INTERFACE
- Condition 2 in which an interrupt (INT bit = 1) upon detection of " AL bit = 1 " does not occurs
When an instruction which generates a start condition by enabling I2C operation (EN bit = 1) is
executed (setting the MSS bit in the IBCR register to "1") with the I2C bus occupied by another
master.
This is because, as shown in Figure 21.2-4, when the other master on the I2C bus starts
communication with I2C disabled (EN bit = 0), the I2C bus enters the occupied state with no start
condition detected (BB bit = 0).
Figure 21.2-4 Diagram of Timing at which an Interrupt Upon Detection of " AL Bit = 1 " does not Occur
Start Condition
INT bit interruption is not generated
in 9th clock.
Stop Condition
SCL pin
SDA pin
SLAVE ADDRESS
ACK
DAT
ACK
EN bit
MSS bit
AL bit
BB bit
INT bit
0
0
If a symptom as described above can occur, follow the procedure below for software
processing.
1) Execute the instruction that generates a start condition (set the MSS bit to "1").
2) Use, for example, the timer function to wait for the time × for three-bit data transmission at
the I2C transfer frequency set in the ICCR register.
Example: Time for three-bit data transmission at an I2C transfer frequency of 100 kHz
{1/(100 × 103)} × 3 = 30 μs
3) Check the AL and BB bits in the IBSR register and, if the AL and BB bits are "1" and "0",
respectively, set the EN bit in the ICCR register to "0" to initialize I2C. When the AL and BB
bits are not so, perform normal processing.
420
CHAPTER 21 400 kHz I2C INTERFACE
A sample flow is given below.
Master mode setting
Set the MSS bit in the bus control register (IBCR) to "1".
Wait * for the time of three-bit data transmission at the I2C
transfer frequency set in the clock control register (ICCR).
NO
BB bit = 0 and AL bit = 1 ?
YES
Set the EN bit to "0" to initialize I2C
to normal process
*: When "arbitration lost" is detected, the MSS bit is set to "1" and then the AL bit is set to
"1" without fail after the time for three-bit data transmission at the I2C transfer frequency.
- Example of occurrence for an interrupt (INT bit = 1) upon detection of "AL bit = 1"
When an instruction which generates a start condition is executed (setting the MSS bit to 1)
with "bus busy" detected (BB bit = 1) and arbitration is lost, the INT bit interrupt occurs upon
detection of "AL bit = 1".
Figure 21.2-5 Diagram of Timing at which an Interrupt Upon Detection of " AL Bit = 1 " Occurs
Start Condition
Interrupt in the ninth clock cycle
SCL pin
SDA pin
SLAVE ADDRESS
ACK
DAT
EN bit
MSS bit
AL bit
BB bit
Clearing the AL bit
by software
Releasing the SCL by clearing
the INT bit by software
INT bit
421
CHAPTER 21 400 kHz I2C INTERFACE
21.2.3
Ten Bit Slave Address Register (ITBA)
This register (ITBAH / ITBAL) designates the ten bit slave address.
■ Ten Bit Slave Address Register (ITBA)
Write access to this register is only possible if the interface is disabled (EN= 0 in ICCR).
Address:
0035A3H
bit 15
14
13
12
11
10
-
-
-
-
-
-
TA9 TA8
-
-
-
-
-
-
R/W R/W
7
6
5
4
3
2
bit
Address:
0035A2 H
9
1
8
0
TA7 TA6 TA5 TA4 TA3 TA2 TA1 TA0
ITBAH (upper)
Initial value
0 0 0 0 0 0 0 0B
ITBAL (lower)
Initial value
0 0 0 0 0 0 0 0B
R/W R/W R/W R/W R/W R/W R/W R/W
R/W
:
Readable and writable
-
:
Undefined
■ Ten Bit Slave Address Register (ITBA) Contents
Table 21.2-3 Function of Each Bit of the Ten Bit Slave Address Register (ITBA)
Bit name
bit15 to
bit10
bit9 to bit0
Function
Undefined
These bits always return "0".
TA9 to TA0:
Ten bit slave
address
When address data is received in slave mode, it is compared to the ITBA register if
the ten bit address is enabled (ENTB = 1 in the ITMK register). An acknowledge is
sent to the master after reception of a ten bit address header with write access1. Then,
the second incoming byte is compared to the TBAL register. If a match is detected,
an acknowledge signal is sent to the master device and the AAS bit is set.
Additionally, the interface acknowledges upon the reception of a ten bit header with
read access2 after a repeated start condition.
All bits of the slave address may be masked using the ITMK register. The received
ten bit slave address is written back to the ITBA register, it is only valid while the
AAS bit in the IBSR register is "1".
Notes:
• A ten bit header (write access) consists of the following bit sequence: 11110B, TA9, TA8, 0.
• A ten bit header (read access) consists of the following bit sequence: 11110B, TA9, TA8, 1.
422
CHAPTER 21 400 kHz I2C INTERFACE
21.2.4
Ten Bit Address Mask Register (ITMK)
This register contains the ten bit slave address mask and the ten bit slave address
enable bit.
■ Ten Bit Address Mask Register (ITMK)
Address:
0035A5H
bit 15
13
12
11
10
-
-
-
-
TM9 TM8
R/W R/W -
-
-
-
R/W R/W
4
3
2
ENTB RAL
bit 7
Address:
0035A4 H
14
6
5
9
1
8
0
TM7 TM6 TM5 TM4 TM3 TM2 TM1 TM0
ITMKH (upper)
Initial value
00111111B
ITMKL (lower)
Initial value
1 1 1 1 1 1 1 1B
R/W R/W R/W R/W R/W R/W R/W R/W
R/W
:
Readable and writable
-
:
Undefined
423
CHAPTER 21 400 kHz I2C INTERFACE
■ Ten Bit Address Mask Register (ITMK) Contents
Table 21.2-4 Function of Each Bit of the Ten Bit Address Mask Register (ITMK)
Bit name
bit15
bit14
bit13 to
bit10
bit9 to bit0
424
Function
ENTB:
Enable ten bit
slave address bit
This bit enables the ten bit slave address (and the acknowledging upon its reception).
Write access to this bit is only possible if the interface is disabled (EN= 0 in ICCR).
"0": Ten bit address disabled
"1": Ten bit address enabled
RAL:
Received slave
address length bit
This bit indicates whether the interface was addressed as a seven or ten bit slave. It is
read only.
"0": Addressed as seven bit slave
"1": Addressed as ten bit slave
This bit can be used to determine whether the interface was addressed as a seven or ten
bit slave if both slave addresses are enabled (ENTB = 1 and ENSB = 1). Its contents is
only valid if the AAS bit in the IBSR register is "1". This bit is also reset if the interface
is disabled (EN= 0 in ICCR).
Undefined
These bits always return "1" during reading.
TMK:
Ten bit slave
address mask bits
This register is used to mask the ten bit slave address of the interface. Write access to
these bits is only possible if the interface is disabled (EN= 0 in ICCR).
"0": Bit is not used in slave address comparison
"1": Bit is used in slave address comparison
This can be used to make the interface acknowledge on multiple ten bit slave addresses.
Only the bits set to "1" in this register are used in the ten bit slave address comparison.
The received slave address is written back to the ITBA register and thus may be
determined by reading the ITBA register if the AAS bit in
the IBSR register is "1".
Note:
If the address mask is changed after the interface had been enabled, the slave address
should also be set again since it could have been overwritten by a previously
received slave address.
CHAPTER 21 400 kHz I2C INTERFACE
I2C Seven Bit Slave Address Register (ISBA)
21.2.5
This register designates the seven bit slave address.
■ I2C Seven Bit Slave Address Register
Write access to this register is only possible if the interface is disabled (EN= 0 in ICCR).
bit 7
Address:
0035A6 H
R/W
:
Readable and writable
-
:
Undefined
6
5
4
3
2
1
0
ISBA
-
SA6 SA5 SA4 SA3 SA2 SA1 SA0
-
R/W R/W R/W R/W R/W R/W R/W
Initial value
0 0 0 0 0 0 0 0B
■ I2C Seven Bit Slave Address Register Contents
Table 21.2-5 Function of Each Bit of the I2C Seven Bit Slave Address Register
Bit name
bit7
bit6 to bit0
Function
Undefined
This bit always returns "0" during reading.
SA6 to SA0:
Seven bit slave
address bits
When address data is received in slave mode, it is compared to the ISBA register if the
seven bit address is enabled (ENSB = 1 in the ISMK register). If a match is detected, an
acknowledge signal is sent to the master device and the AAS bit is set.
All bits of the slave address may be masked using the ISMK register. The received
seven bit slave address is written back to the ISBA register, it is only valid while the
AAS bit in the IBSR register is "1".
The interface does not compare the contents of this register to the incoming data if a ten
bit header or a general call is received.
425
CHAPTER 21 400 kHz I2C INTERFACE
■ I2C Seven Bit Slave Address Mask Register (ISMK)
This register contains the seven bit slave address mask and the seven bit mode enable bit. Write access to
this register is only possible if the interface is disabled (EN= 0 in ICCR).
bit 15
Address:
0035A7 H
14
13
12
11
10
9
8
ISMK
ENSB SM6 SM5 SM4 SM3 SM2 SM1SM0
Initial value
0 1 1 1 1 1 1 1B
R/W R/W R/W R/W R/W R/W R/W R/W
R/W
:
Readable and writable
■ I2C Seven Bit Slave Address Mask Register Contents
Table 21.2-6 Function of Each Bit of the I2C Seven Bit Slave Address Mask Register
Bit name
bit15
bit14 to
bit8
426
Function
ENSB:
Enable seven bit
slave address bit
This bit enables the seven bit slave address (and the acknowledging upon its reception).
"0": Seven bit slave address disabled
"1": Seven bit slave address enabled
SM6 to SM0:
Seven bit slave
address mask bits
This register is used to mask the seven bit slave address of the interface.
"0": Bit is not used in slave address comparison.
"1": Bit is used in slave address comparison.
This can be used to make the interface acknowledge on multiple seven bit slave
addresses. Only the bits set to "1" in this register are used in the seven bit slave address
comparison. The received slave address is written back to the ISBA register and may
thus may be determined by reading the ISBA register if the AAS bit in the IBSR register
is "1".
Note:
If the address mask is changed after the interface had been enabled, the slave address
should also be set again since it could have been overwritten by a previously
received slave address.
CHAPTER 21 400 kHz I2C INTERFACE
I2C Data Register (IDAR)
21.2.6
Data Register for the 400 kHz I2C Interface.
■ I2C Data Register (IDAR)
bit 7
Address:
0035A8H
6
5
4
3
2
D7 D6 D5 D4 D3 D2
1
0
D1 D0
IDAR
Initial value
00000000
R/W R/W R/W R/W R/W R/W R/W R/W
R/W
:
B
Readable and writable
■ I2C Data Register Contents
Table 21.2-7 Function of Each Bit of the I2C Data Register
Bit name
bit7 to bit0
D7 to D0:
Data bits
Function
The data register is used in serial data transfer, and transfers data MSB first. This
register is double buffered on the write side, so that when the bus is in use (BB = 1),
write data can be loaded to the register for serial transfer. The data byte is loaded
into the internal transfer register if the INT bit in the IBCR register is being
cleared or the bus is idle (BB = 0 in IBSR). In a read access, the internal register is
read directly, therefore received data values in this register are only valid if INT=
1 in the IBCR register.
427
CHAPTER 21 400 kHz I2C INTERFACE
I2C Clock Control Register (ICCR)
21.2.7
The I2C clock control register (ICCR) has the following functions:
• Enable test mode
• Enable I/O pad noise filters
• Enable I2C interface operation
• Setting the serial clock frequency
■ I2C Clock Control Register (ICCR)
bit 15
Address:
0035AB H
428
R/W
:
Readable and writable
-
:
Undefined
14
13
12
11
10
9
8
-
NSF EN CS4 CS3 CS2 CS1 CS0
-
R/W R/W R/W R/W R/W R/W R/W
ICCR
Initial value
0 0 0 1 1 1 1 1B
CHAPTER 21 400 kHz I2C INTERFACE
■ I2C Clock Control Register (ICCR) Contents
Table 21.2-8 Function of Each Bit of the I2C Clock Control Register
Bit name
bit15
bit14
bit13
Function
Undefined
This bit always returns "0" during reading.
NSF:
IO pad noise filter
enable bit
This bit enables the noise filters built into the SDA and SCL I/O pads.
It should be set to "1" if the interface is transmitting or receiving at data rates above 100
kbit.
MB90V390H:
The noise filter will suppress single spikes with a pulse width of 0 ns (minimum) and
between 1 and 1.5 cycles of internal-bus (maximum). The maximum depends on the
phase relationship between I2C signals (SDA, SCL) and machine clock.
MB90394HA, MB90V390HA, MB90V390HB:
The noise filter will suppress single spikes with a pulse width between 0 ns (minimum)
and a maximum value according to the setting of the SEL1, SEL0 bits in the INFCR
register. Refer to Table 21.2-11. The maximum depends on the phase relationship
between I2C signals (SDA, SCL) and machine clock.
EN:
Enable bit
This bit enables the I2C interface operation. It can only be set by the user but may be
cleared by the user and the hardware.
"0": Interface disabled
"1": Interface enabled
When this bit is set to "0" all bits in the IBSR register and IBCR register (except the
BER and BEIE bits) are cleared and the module is disabled and the I2C lines are left
open. It is cleared by the hardware if a bus error occurs (BER = 1 in IBCR).
Notes:
• When the operation of the I2C interface is prohibited, sending and receiving is
stopped at once.
• Please prohibit operating after confirming the generation of the stop condition
(BB=0 of IBSR) when you prohibit the operation of the I2C interface after written
"0" to the MSS bit and the stop condition is generated (EN=0 of ICCR).
These bits select the serial bit rate. They can only be changed if the interface is disabled
(EN = 0) or the EN bit is being cleared in the same write access.
bit12 to
bit8
CS4 to CS0:
Clock prescaler
bits
n
CS4
CS3
CS2
CS1
CS0
1
0
0
0
0
1
Bit rate: φ / 28(+1)
2
0
0
0
1
0
Bit rate: φ / 40(+1)
3
0
0
0
1
1
Bit rate: φ / 52(+1)
4
0
0
1
0
0
Bit rate: φ / 64(+1)
1
1
1
Bit rate: φ / 400(+1)
...
31
1
1
(+1) means: Add 1 to divisor, if noise filter is enabled
429
CHAPTER 21 400 kHz I2C INTERFACE
■ Clock Prescaler Settings
The calculation formula for CS0 to CS4 is determined as follows:
Bit rate =
φ
n × 12 + 16
n>0
: machine clock, Noise filter disabled
Bit rate =
φ
n × 12 + 17
n>0
: machine clock, Noise filter enabled, INFCR:SEL[1:0] = 01B
Table 21.2-9 Prescaler Settings
n
CS4
CS3
CS2
CS1
CS0
1
0
0
0
0
1
2
0
0
0
1
0
3
0
0
0
1
1
1
1
1
...
31
1
1
Note:
Do not use n=0 prescaler setting, it violates SDA/SCL timings.
■ Common Machine Clock Frequencies
Table 21.2-10 lists the common machine clock frequencies.
Table 21.2-10 Common Machine Clock Frequencies
Machine Clock
[MHz]
430
100 kbit (Noise filter disabled)
n Bit rate [kbit]
400 kbit (Noise filter enabled,
INFCR:SEL[1:0]= 01B)
n Bit rate [kbit]
24
19
98
4
369
20
16
96
3
377
16
12
100
2
390
40/3 = 13.3
10
98
2
325
12
9
96
2
292
64/6 = 10.6
8
94
1
367
10
7
100
1
344
8
6
90
1
275
CHAPTER 21 400 kHz I2C INTERFACE
21.2.8
Noise Filter Configuration Register (INFCR)
The Noise Filter Configuration Register (INFCR) is used to configure the filter time of
the SDA and SCL noise filters as a function of the machine clock frequency.
It is only available in MB90394HA, MB90V390HA and MB90V390HB.
■ Noise Filter Configuration Register (INFCR)
0035A9 H
15
14
13
12
11
10
9
8
-
-
-
-
-
-
SEL1 SEL0
-
-
-
-
-
-
R/W R/W
INFCR
Initial value
XXXXXX 01B
R/W :Readable and writable
: Undefined
■ Noise Filter Configuration Register Contents
Table 21.2-11 Function of Each Bit of the Noise Filter Configuration Register
Bit name
bit15 to bit10
bit9, bit8
Function
Undefined
These bits return "X" during reading. Always write "0" to these bits
SEL1, SEL0
MB90394HA, MB90V390HA, MB90V390HB:
These bits select the filter time of noise filters built into the SDA and SCL I/O pads.
The noise filter will suppress single spikes with a pulse width between 0 ns (minimum)
and a maximum value according to the table below. The maximum depends on the
phase relationship between I2C signals (SDA, SCL) and machine clock.
SEL1
SEL0
maximum length of suppressed spikes
0
0
0.5 to 1 machine clock cycles
0
1
1 to 1.5 machine clock cycles (initial value)
1
0
1.5 to 2 machine clock cycles
1
1
2 to 2.5 machine clock cycles
431
CHAPTER 21 400 kHz I2C INTERFACE
21.3
I2C Interface Operation
The I2C bus executes communication using two bi-directional bus lines, the serial data
line (SDA) and serial clock line (SCL). The I2C interface has two open-drain I/O pins
(SDA/SCL) corresponding to these lines, enabling wired logic applications.
■ Start Conditions
When the bus is free (BB = 0 in IBSR, MSS = 0 in IBCR), writing "1" to the MSS bit places the I2C
interface in master mode and generates a start condition.
If a "1" is written to it while the bus is idle (MSS = 0 and BB = 0), a start condition is generated and the
contents of the IDAR register (which should be address data) is sent.
Repeated start conditions can be generated by writing "1" to the SCC bit when in bus master mode and
interrupt status (MSS = 1 and INT = 1 in IBCR).
If a "1" is written to the MSS bit while the bus is in use (BB = 1 and TRX = 0 in IBSR; MSS = 0 and INT = 0
in IBCR), the interface waits until the bus is free and then starts sending.
If the interface is addressed as slave with write access (data reception) in the meantime, it will start sending
after the transfer ended and the bus is free again. If the interface is sending data as slave in the meantime, it
will not start sending data if the bus of free again. It is important to check whether the interface was
addressed as slave (MSS = 0 in IBCR and AAS = 1 in IBSR), sent the data byte successfully (MSS = 1 in
IBCR) or failed to send the data byte (AL = 1 in IBSR) at the next interrupt.
Writing "1" to the MSS bit or SCC bit in any other situation has no significance.
■ Stop Conditions
Writing "0" to the MSS bit in master mode (MSS = 1 and INT = 1 in IBCR) generates a stop condition and
places the device in slave mode. Writing "0" to the MSS bit in any other situation has no significance.
After clearing the MSS bit, the interface tries to generate a stop condition which might fail if another
master pulls the SCL line low before the stop condition has been generated. This will generate an interrupt
after the next byte has been transferred!
432
CHAPTER 21 400 kHz I2C INTERFACE
■ Slave Address Detection
In slave mode, after a start condition is generated the BB is set to "1" and data sent from the master device
is received into the IDAR register.
After the reception of eight bits, the contents of the IDAR register is compared to the ISBA register using
the bit mask stored in ISMK if the ENSB bit in the ISMK register is "1". If a match results, the AAS bit is
set to "1" and an acknowledge signal is sent to the master. Then bit0 of the received data (bit0 of the IDAR
register) is inverted and stored in the TRX bit.
If the ENTB bit in the ITMK register is "1" and a ten bit address header (11110, TA1, TA0, write access) is
detected, the interface sends an acknowledge signal to the master and stores the inverted last data bit in the
TRX register. No interrupt is generated. Then, the next transferred byte is compared (using the bit mask
stored in ITMK) to the lower byte of the ITBA register. If a match is found, an acknowledge signal is sent
to the master, the AAS bit is set and an interrupt is generated.
If the interface was addressed as slave and detects a repeated start condition, the AAS bit is set after
reception of the ten bit address header (11110, TA1, TA0, read access) and an interrupt is generated.
Since there are separate registers for the ten and seven bit address and their bit masks, it is possible to make
the interface acknowledge on both addresses by setting the ENSB (in ISMK) and ENTB (in ITMK) bits.
The received slave address length (seven or ten bit) may be determined by reading the RAL bit in the
ITMK register (this bit is valid if the AAS bit is set only).
It is also possible to give the interface no slave address by setting both bits to "0" if it is only used as a
master.
All slave address bits may be masked with their corresponding mask register (ITMK or ISMK).
■ Slave Address Masking
Only the bits set to "1" in the mask registers (ITMK / ISMK) are used for address comparison, all other bits
are ignored. The received slave address can be read from the ITBA (if ten bit address received, RAL = 1) or
ISBA (if seven bit address received, RAL = 0) register if the AAS bit in the IBSR register is "1".
If the bit masks are cleared, the interface can be used as a bus monitor since it will always be addressed as
slave. Note that this is not a real bus monitor because it acknowledges upon any slave address reception,
even if there is no other slave listening.
433
CHAPTER 21 400 kHz I2C INTERFACE
■ Addressing Slaves
In master mode, after a start condition is generated the BB and TRX bits are set to "1" and the contents of
the IDAR register is sent in MSB first order. After address data is sent and an acknowledge signal was
received from the slave device, bit0 of the sent data (bit0 of the IDAR register after sending) is inverted and
stored in the TRX bit. Acknowledgement by the slave may be checked using the LRB bit in the IBSR
register. This procedure also applies to a repeated start condition.
In order to address a ten bit slave for write access, two bytes have to be sent. The first one is the ten bit
address header which consists of the bit sequence "1 1 1 1 0 A9 A8 0", it is followed by the second byte
containing the lower eight bits of the ten bit slave address (A7 - A0).
A ten bit slave is accessed for reading by sending the above byte sequence and generating a repeated start
condition (SCC bit in IBCR) followed by a ten bit address header with read access (1 1 1 1 0 A9 A8 1).
Summary of the address data bytes:
7 bit slave, write access: Start condition - A6 A5 A4 A3 A2 A1 A0 0.
7 bit slave, read access: Start condition - A6 A5 A4 A3 A2 A1 A0 1.
10 bit slave, write access: Start condition - 1 1 1 1 0 A9 A8 0 - A7 A6 A5 A4 A3 A2 A1 A0.
10 bit slave, read access: Start condition - 1 1 1 1 0 A9 A8 1 - A7 A6 A5 A4 A3 A2 A1 A0 - repeated start
- 1 1 1 1 0 A9 A8 1.
■ Arbitration
During sending in master mode, if another master device is sending data at the same time, arbitration is
performed. If a device is sending the data value "1" and the data on the SDA line has an "L" level value, the
device is considered to have lost arbitration, and the AL bit is set to "1". Also, the AL bit is set to "1" if a
start condition is detected at the first bit of a data byte but the interface did not want to generate one or the
generation of a start or stop condition failed by some reason.
Arbitration loss detection clears both the MSS and TRX bit and immediately places the device in slave
mode so it is able to acknowledge if its own slave address is being sent.
■ Acknowledgement
Acknowledge bits are sent from the receiver to the transmitter. The ACK bit in the IBCR register can be
used to select whether to send an acknowledgment when data bytes are received.
When data is send in slave mode (read access from another master), if no acknowledgement is received
from the master, the TRX bit is set to "0" and the device goes to receiving mode. This enables the master to
generate a stop condition as soon as the slave has released the SCL line.
In master mode, acknowledgement by the slave can be checked by reading the LRB bit in the IBSR
register.
434
CHAPTER 21 400 kHz I2C INTERFACE
21.4
Programming Flow Charts
Each programming flow charts for the 400 kHz I2C interface is shown below.
■ Programming Flow Charts
Figure 21.4-1 Example of Slave Addressing and Sending Data
Addressing a 7 bit slave
Sending data
Start
Start
Address slave for write
Clear BER bit (if set);
Enable Interface EN:=1;
IDAR := Data Byte;
INT := 0
IDAR := slave address<<1+RW;
MSS := 1; INT := 0
NO
INT=1?
NO
INT=1?
YES
YES
YES
BER=1?
YES
Bus error
BER=1?
NO
NO
AL=1?
YES
Restart
transfer
Check
if AAS
AL=1?
YES
Restart
transfer
Check
if AAS
NO
NO
ACK?
ACK?
(LRB=0?)
NO
(LRB=0?)
NO
YES
Yes
Ready to send data
Last byte
transferred?
YES
NO
Slave did not ACK
Generate
repeated start
or stop condition
Transfer End
Generate
repeated start or
stop condition
435
CHAPTER 21 400 kHz I2C INTERFACE
Figure 21.4-2 Example of Receiving Data
Start
Address slave for read
Clear ACK bit in IBCR if it’s the
last byte to read from slave;
INT := 0
NO
INT=1?
YES
BER=1?
YES Bus error
reenable IF
NO
NO
Last byte
transferred?
YES
Transfer End
Generate
repeated start or
stop condition
436
CHAPTER 22
SERIAL I/O
This chapter explains the functions and operations of
the serial I/O.
22.1 Outline of Serial I/O
22.2 Serial I/O Registers
22.3 Serial I/O Prescaler (CDCR)
22.4 Serial I/O Operation
437
CHAPTER 22 SERIAL I/O
22.1
Outline of Serial I/O
The serial I/O interface operates in two modes:
• Internal shift clock mode: Data is transferred in synchronization with the internal
clock.
• External shift clock mode: Data is transferred in synchronization with the clock
supplied via the external pin (SCK4). By manipulating the
general-purpose port sharing the external pin (SCK4), data
can also be transferred by a CPU instruction in this mode.
■ Serial I/O Block Diagram
This block is a serial I/O interface that allows data transfer using clock synchronization. The interface
consists of a single eight-bit channel. Data can be transferred from the LSB first or MSB first.
Figure 22.1-1 Extended Serial I/O Interface Block Diagram
Internal data bus
(MSB first) D7 to D0
D7 to D0 (LSB first)
Transfer direction selection
SIN3
SIN4
Read
SDR (Serial data register)
Write
SOT4
SOT3
SCK3
SCK4
Control circuit
Shift clock counter
Internal clock
2
SMD2
1
0
SMD1 SMD0
SIE
SIR
BUSY
STOP
STRT MODE
Interrupt
request
Internal data bus
438
BDS
SOE
SCOE
CHAPTER 22 SERIAL I/O
22.2
Serial I/O Registers
The serial I/O has the following two registers:
• Serial mode control status register (SMCS)
• Serial data register (SDR)
■ Serial I/O Registers
bit 15
14
13
Address : 00002DH SMD2 SMD1 SMD0
bit
7
6
5
12
11
10
SIE
SIR
BUSY
4
3
2
1
0
MODE
BDS
SOE
SCOE
0
Address : 00002CH
bit
Address : 00002EH
9
8
STOP STRT
7
6
5
4
3
2
1
D7
D6
D5
D4
D3
D2
D1
D0
Serial mode control
status register (SMCS)
Serial data register (SDR)
439
CHAPTER 22 SERIAL I/O
22.2.1
Serial Mode Control Status Register (SMCS)
The serial mode control status register (SMCS) controls the serial I/O transfer mode.
■ Upper Byte of Serial Mode Control Status Register (SMCS)
Figure 22.2-1 Configuration of the Serial Mode Control Status Register (Upper Byte)
bit15
Address
00002D H
bit14
SMD2 SMD1
R/W
R/W
bit13
bit12
bit11
bit10
bit9
bit8
SMD0
SIE
SIR
BUSY
STOP
STRT
R/W
R/W
R/W
R
R/W
R/W
STRT
0
1
Start bit
Writing "0" has no effect. "0" is always read
Writing "1" activates serial transfer, if MODE = 0
STOP
0
1
Normal operation
Transfer stopped
BUSY
: Initial value
440
Stop bit
1
Transfer Status bit
Transfer is stopped or standing by for serial data
register Read/Write
Serial transfer is active
SIR
0
1
Serial I/O Interrupt Request bit
No interrupt is requested
If SIE = 1, an interrupt request is issued to CPU
SIE
0
1
Serial I/O Interrupt Enable bit
Serial I/O interrupt disabled
Serial I/O interrupt enabled
0
R/W : Readable and writable
R
: Read only
Initial value
00000010 B
SMD2 to
SMD0
000B
001B
010B
011B
100B
101B
110B
111B
Shift Clock Mode selection bits
Prescaler output clock is divided by 2
Prescaler output clock is divided by 4
Prescaler output clock is divided by 16
Prescaler output clock is divided by 32
Prescaler output clock is divided by 64
External shift clock mode
Prescaler output clock is divided by 8
Prescaler output clock is divided by 128
CHAPTER 22 SERIAL I/O
■ Lower Byte of Serial Mode Control Status Register (SMCS)
Figure 22.2-2 Configuration of the Serial Mode Control Status Register (Lower Byte)
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
-
-
-
-
MODE
BDS
SOE
SCOE
-
-
-
-
R/W
R/W
R/W
R/W
Address
00002C H
SCOE
0
1
R/W : Readable and writable
X
: Undefined value
: Undefined
: Initial value
Initial value
XXXX0000 B
Shift Clock Output Enable bit
General-purpose port pin, transfer for each
instruction.
Shift Clock output pin.
SOE
0
1
Serial Output Enable bit
General-purpose port pin.
Serial data output.
BDS
0
1
LSB first.
MSB first.
MODE
0
1
Bit Direction Select bit
Serial Mode Selection bit
Transfer starts when STRT = 1.
Tr ansfer starts, when the serial data register is
read or written to.
441
CHAPTER 22 SERIAL I/O
■ Bit Functions of Serial Mode Control Status Register (SMCS)
Table 22.2-1 Bit Functions of Serial Mode Control Status Register
Bit name
Function
SMD2 to SMD0:
Shift clock mode
selection bits
Shift Clock Mode selection bits, see Table 22.2-2.
SIE:
Serial I/O interrupt
enable bit
Serial I/O interrupt enable bit.
This bit controls the serial I/O interrupt request as shown Figure 22.2-1. This bit is initialized to "0"
upon a reset. This bit is readable and writable.
bit11
SIR:
Serial I/O interrupt
request bit
Serial I/O interrupt request bit.
When serial data transfer is completed, "1" is set to this bit. If this bit is set while interrupts are
enabled (SIE=1), an interrupt request is issued to the CPU. The clear condition varies with the
MODE bit.
When "0" is written to the MODE bit, the SIR bit is cleared by writing "0". When "1" is written to
the MODE bit, the SIR bit is cleared by reading or writing to SDR. When the system is reset or "1"
is written to the STOP bit, the SIR bit is cleared regardless of the MODE bit value.
Writing "1" to the SIR bit has no effect. "1" is always read by a read operation of a read-modifywrite (RMW) instruction.
bit10
BUSY:
Transfer status bit
Transfer status bit.
The transfer status bit indicates whether serial transfer is being executed. This bit is initialized to "0"
upon a reset. This is a read-only bit.
bit9
STOP:
Stop bit
Stop bit.
The stop bit forcibly terminates serial transfer. When "1" is written to this bit, the transfer is stopped.
This bit is initialized to "1" upon a reset. This bit is readable and writable.
bit8
STRT:
Start bit
Start bit.
The start bit activates serial transfer. Writing "1" to this bit starts the data transfer when the MODE
bit is set to "0". When the MODE bit is set to "1" and the STRT bit is set to "1", writing the data into
serial data register starts the transfer.
Writing "1" is ignored while the system is performing serial transfer or standing by for a serial shift
register read or write. Writing "0" has no effect. "0" is always read.
bit3
MODE:
Serial mode selection
bit
Serial mode selection bit.
The serial mode selection bit is used to select the conditions to start the transfer operation from the
stop state. This bit must not be updated during operation.
This bit is initialized to "0" upon a reset and can be read or written to. To activate the intelligent I/O
service, ensure that "1" is written to this bit.
bit2
BDS:
Bit direction select
bit
Bit Direction Select bit.
When serial data is input or output, this bit determines from which bit data is to be transferred first,
the least significant bit (LSB first) or the most significant bit (MSB first), as shown Table 22.2-2.
Specify the bit ordering before any data is written to SDR.
bit1
SOE:
Serial output enable
bit
Serial Output Enable bit.
This bit controls the output from the serial I/O output external pins (SOT4).
This bit is initialized to "0" upon a reset. This bit is readable and writable.
bit0
SCOE:
Shift clock output
enable bit
Shift clock output enable bit.
This bit controls the output from the shift clock I/O output external pins (SCK4) as shown Table 22.2-2.
Ensure that "0" is written to this bit when data is transferred for each instruction in external shift
clock mode.
This bit is initialized to "0" upon a reset. This bit is readable and writable.
bit15 to
bit13
bit12
442
CHAPTER 22 SERIAL I/O
■ Shift Clock Selection
The Shift Clock Mode Selection bits are used to select the serial shift clock mode, as shown in Table 22.22. The second part is related to the Serial I/O prescaler register (CDCR). For details, see Section "22.3
Serial I/O Prescaler (CDCR)".
Table 22.2-2 Setting the Serial Shift Clock Mode
SMD2
SMD1
SMD0
φ=24MHz
div=6
φ=20MHz
div=4
φ=16MHz
div=4
φ=8MHz
div=4
φ=4MHz
div=4
0
0
0
2 MHz
2.5 MHz
2 MHz
1 MHz
500 kHz
0
0
1
1 MHz
1.25 MHz
1 MHz
500 kHz
250 kHz
0
1
0
250 kHz
312.5 kHz
250 kHz
125 kHz
62.5 kHz
0
1
1
125 kHz
156.25 kHz
125 kHz
62.5 kHz
31.25 kHz
1
0
0
62.5 kHz
78.125 kHz
62.5 kHz
31.25 kHz
15.625 kHz
1
0
1
1
1
0
500 kHz
625 kHz
500 kHz
250 kHz
125 kHz
1
1
1
31.25 kHz
39.1 kHz
31.25 kHz
15.625 kHz
7812.5 Hz
External shift clock mode
Table 22.2-3 Division Ratio for Serial I/O Prescaler Register
div
MD
DIV3
DIV2
DIV1
DIV0
Recommended
machine cycle
3
1
0
0
1
0
6 MHz
4
1
0
0
1
1
8 MHz
5
1
0
1
0
0
10 MHz
6
0
0
1
0
1
12 MHz
7
0
0
1
1
0
14 MHz
8
1
0
1
1
1
16 MHz
The SMD bits are initialized to "000B" upon a reset. These bits must not be updated during data transfer.
Shift operation can be performed for each instruction by specifying SCOE =0 during clock selection and by
using the ports that share the SCK4 pin.
443
CHAPTER 22 SERIAL I/O
22.2.2
Serial Shift Data Register (SDR)
This serial shift data register stores the serial I/O transfer data. During transfer, the SDR
must not be read or written to.
■ Serial Shift Data Register (SDR)
bit
SDR
Address : 00002E H
7
6
5
4
3
2
1
0
D7
D6
D5
D4
D3
D2
D1
D0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W : Readable and writable
X
: Undefined value
444
Initial value
XXXXXXXXB
CHAPTER 22 SERIAL I/O
22.3
Serial I/O Prescaler (CDCR)
The Serial I/O Prescaler provides the shift clock for the Serial I/O.
The operation clock for the Serial I/O is obtained by dividing the machine clock. The
Serial I/O is designed so that a constant baud rate can be obtained for a variety of
machine clocks by the use of the communication prescaler. The CDCR register controls
the machine clock division.
■ Serial I/O Prescaler (CDCR)
Figure 22.3-1 Configuration of the Serial I/O Prescaler (CDCR)
Address
00002FH
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
MD
-
NEG
-
DIV3
DIV2
DIV1
DIV0
R/W
-
R/W
-
R/W
R/W
R/W
R/W
DIV3 to
DIV0
0000B
0001B
0010B
0011B
0100B
0101B
0110B
0111B
1xxxB
NEG
0
1
R/W : Readable and writable
X
: Undefined value
: Undefined
MD
0
1
Initial value
0 X 0 X 0 0 0 0B
Machine Clock Division Ratio bits
Division ratio: div =
Division ratio: div =
Division ratio: div =
Division ratio: div =
Division ratio: div =
Division ratio: div =
Division ratio: div =
Division ratio: div =
reserved
1
2
3
4
5
6
7
8
Negative Clock Operation bit
Normal operation
The shift clock signal is inverted
Machine Clock Divide Mode Select bit
The Serial I/O Prescaler is disabled.
The Serial I/O Prescaler is enabled.
: Initial value
Note:
When the division ratio is changed, allow two cycles for the clock to stabilize before starting
communication.
445
CHAPTER 22 SERIAL I/O
22.4
Serial I/O Operation
The extended serial I/O consists of the serial mode control status register (SMCS) and
shift register (SDR), and is used for input and output of 8-bit serial data.
■ Serial I/O Operation
The bits in the shift register are serially output via the serial output pin (SOT4 pin) at the falling edge of the
serial shift clock (external clock or internal clock). The bits are serially input to the shift register (SDR) via
the serial input pin (SIN4 pin) at the rising edge of the serial shift clock. The shift direction (transfer from
MSB first or LSB first) is specified by the direction specification bit (BDS) of the serial mode control
status register (SMCS).
At the end of serial data transfer, this block is stopped or stands by for a read or write of the data register
according to the MODE bit of the serial mode control status register (SMCS). To start transfer from the
stop or standby state, follow the procedure below.
• To resume operation from the stop state, write "0" to the STOP bit and "1" to the STRT bit. (The STOP
and STRT bits can be set simultaneously.)
• To resume operation from the serial shift data register Read/Write standby state, read or write to the data
register.
446
CHAPTER 22 SERIAL I/O
22.4.1
Shift Clock
There are two modes of shift clock: internal or external shift clock. These two modes
are selected by setting the SMCS. To switch the modes, ensure that serial I/O transfer is
stopped. To check whether the serial I/O transfer is stopped, read the BUSY bit.
■ Internal Shift Clock Mode
In internal shift clock mode, data transfer is based on the internal clock. As a synchronization timing
output, a shift clock of 50% duty ratio can be output from the SCK4 pin. Data is transferred at one bit per
clock. The transfer frequency and speed is expressed as follows:
Transfer frequency [Hz] =
Transfer speed [s] =
A div
A div
"A" is the division ratio indicated by the SMD bits of SMCS. The value can be 21, 22, 23, 24, 25, 26 or 27.
φ is the machine frequency.
■ External Shift Clock Mode
In external shift clock mode, the data transfer is based on the external clock supplied via the SCK4 pin.
Data is transferred at one bit per clock.
The transfer speed can be between DC and 1/(5 machine cycles). For example, the transfer speed can be up
to 2 MHz when 1 machine cycle is equal to 0.1 μs. The external clock frequency has a maximum value of
2 MHz.
A data bit can also be transferred by software, which is enabled as described below.
Select external shift clock mode, and write "0" to the SCOE bit of SMCS. Then, write "1" to the direction
register for the port sharing the SCK4 pin, and place the port in output mode. Then, when "1" and "0" are
written to the data register (PDR) of the port, the port value output via the SCK4 pin is fetched as the
external clock and transfer starts. Ensure that the shift clock starts from "H".
Note:
The SMCS or SDR must not be written to during serial I/O operation.
447
CHAPTER 22 SERIAL I/O
22.4.2
Serial I/O Operation
There are four serial I/O operation statuses:
• STOP
• Halt
• SDR Read/Write standby
• Transfer
■ Serial I/O Operation
● STOP
The STOP state is initiated upon RESET or when "1" is written to the STOP bit of SMCS. The shift
counter is initialized, and "0" is written to SIR.
To resume operation from the STOP state, write "0" to STOP and "1" to STRT. (These two bits can be
written to simultaneously.) Since the STOP bit overrides the STRT bit, transfer cannot be started by writing
"1" to STRT while "1" is written to STOP.
● Halt
When transfer is completed while the MODE bit is "0", "0" is set to BUSY and "1" is set to SIR of the
SMCS, the counter is initialized, and the system stops. To resume operation from the stop state, write "1" to
STRT.
● Serial data register Read/Write standby
When transfer is completed while the MODE bit is "1", "0" is set to BUSY and "1" is set to SIR of the
SMCS, and the system enters the serial data register Read/Write standby state. If the interrupt enable flag is
set, an interrupt signal is output from this block.
To resume operation from Read/Write standby state, read or write to the serial data register. This sets the
BUSY bit to "1" and starts data transfer.
● Transfer
"1" is set to the BUSY bit and serial transfer is being performed. According to the MODE bit, the halt state
or Read/Write standby state comes next.
Figure 22.4-1 is a diagram of the operation transitions.
448
CHAPTER 22 SERIAL I/O
Figure 22.4-1 Extended I/O Serial Interface Operation Transitions
STOP
STRT=0, BUSY=0
MODE=0
STOP=0
&
STRT=1
Reset
STOP=0 & STRT=0
End of transfer
STRT=0, BUSY=0
STOP=1
MODE=0
&
STOP=0
&
END
STOP=1
STOP=1
STOP=0
&
STRT=1
Transfer
Serial data register Read/Write standby
MODE=1 & END & STOP=0
STRT=1, BUSY=1
STRT=1, BUSY=0
MODE=1
SDR R/W & MODE=1
Serial data
Figure 22.4-2 Serial Data Register Read/Write
Data bus
SOT4
SOT3
SIN4
SIN3
Data bus
Read
Write
Interrupt output
Extended I/O
serial interface
Read
Write
➁
CPU
➀
Interrupt input
Data bus Interrupt controller
1. If "1" is written to MODE, transfer ends according to the shift clock counter. The read/write standby
state starts when "1" is written to SIR. If "1" is written to the SIE bit, an interrupt signal is generated. No
interrupt signal is generated when SIE is inactive or transfer has been terminated by writing "1" to
STOP.
2. Reading or writing to the serial data register clears the interrupt request and starts serial transfer.
449
CHAPTER 22 SERIAL I/O
22.4.3
Shift Operation Start/Stop Timing
To start the shift operation, set the STOP bit to "0" and the STRT bit to "1" in SMCS.
The system may stop the shift operation at the end of transfer or when "1" is set in the
STOP bit.
• Stop by STOP=1 → The system stops with SIR=0 regardless of the MODE bit
• Stop by end of transfer → The system stops with SIR=1 regardless of the MODE bit
Regardless of the MODE bit, the BUSY bit becomes "1" during serial transfer and
becomes "0" during stop or Read/Write standby state. To check the transfer status,
read this bit.
■ Shift Operation Start/Stop Timing
● Internal shift clock mode (LSB first)
Figure 22.4-3 Shift Operation Start/Stop Timing (Internal Clock)
"1" output
SCK4
(Transfer start)
STRT
(Transfer end)
If MODE=0
BUSY
SOT4
DO0
DO7 (Data maintained)
● External shift clock mode (LSB first)
Figure 22.4-4 Shift Operation Start/Stop Timing (External Clock)
SCK4
(Transfer start)
STRT
(Transfer end)
If MODE=0
BUSY
SOT4
450
DO0
DO7 (Data maintained)
CHAPTER 22 SERIAL I/O
● External shift clock mode with instruction shift (LSB first)
Figure 22.4-5 Shift Operation Start/Stop Timing (External Shift Clock Mode with Instruction Shift)
SCK=0 in PDR
SCK4
STRT
SCK=0 in PDR
SCK=1 in PDR (Transfer end)
If MODE=0
BUSY
DO7 (Data maintained)
DO6
SOT4
* For an instruction shift, "H" is output when "1" is written to the bit corresponding to SCK of PDR,
and "L" is output when "0" is written. (When SCOE=0 in external shift clock mode)
● Stop by STOP=1 (LSB first, internal clock)
Figure 22.4-6 Stop Timing when "1" is Written to the STOP Bit
"1" output
SCK4
(Transfer start)
(Transfer stop)
If MODE=0
STRT
BUSY
STOP
SOT4
DO3
DO4
DO5 (Data maintained)
Note:
DO7 to DO0 indicate output data.
During serial data transfer, data is output from the serial output pin (SOT4) at the falling edge of the shift
clock, and input from the serial input pin (SIN4) at the rising edge.
451
CHAPTER 22 SERIAL I/O
Figure 22.4-7 Serial Data I/O Shift Timing
❍ LSB first (When the BDS bit is "0")
SCK4
SIN Input
SIN4
DI0
DI1
SOT4
DO0
DO1
DI2
DI3
SOT Output
DI4
DI5
DI6
DI7
DO2
DO4
DO5
DO6
DO7
DO3
❍ MSB first (When the BDS bit is "1")
SCK4
SIN4
SIN Input
DI7
DI6
DI5
DI4
DI3
DI2
DI1
DI0
DO4
DO3
DO2
DO1
DO0
SOT Output
SOT4
452
DO7
DO6
DO5
CHAPTER 22 SERIAL I/O
22.4.4
Interrupt Function of the Extended Serial I/O Interface
This block can issue an interrupt request to the CPU. At the end of data transfer, the SIR
bit is set as an interrupt flag. When "1" is written to the interrupt enable bit (SIE bit) of
SMCS, an interrupt request is issued to the CPU.
■ Interrupt Function of the Extended Serial I/O Interface
Figure 22.4-8 Interrupt Signal Output Timing of the Extended Serial I/O Interface
SCK4
(Transfer end)
BUSY
(Transfer start)
SIE=1
SIR
SDR RD/WR
SOT4
DO6
DO7 (Data is maintained.)
DO0
When MODE=1
SCK4
(Transfer end)
BUSY
SIE=1
SIR
SDR RD/WR
SOT4
DO6
DO7 (Data is maintained.)
When MODE=0
453
CHAPTER 22 SERIAL I/O
454
CHAPTER 23
CAN CONTROLLER
This chapter explains the functions and operations of
the CAN controller.
Note: CAN controller 2 to 4 are not specified in the
MB90390 series. For this reason Fujitsu
recommends not to use these features.
23.1 Features of CAN Controller
23.2 Block Diagram of CAN Controller
23.3 List of Overall Control Registers
23.4 List of Message Buffers (ID Registers)
23.5 List of Message Buffers (DLC Registers and Data Registers)
23.6 Classifying the CAN Controller Registers
23.7 Transmission of CAN Controller
23.8 Reception of CAN Controller
23.9 Reception Flowchart of CAN Controller
23.10 How to Use the CAN Controller
23.11 Procedure for Transmission by Message Buffer (x)
23.12 Procedure for Reception by Message Buffer (x)
23.13 Setting Configuration of Multi-level Message Buffer
23.14 Setting the redirection of CAN1 and CAN3 RX/TX pin
23.15 Setting the CAN Direct Mode Register
23.16 Precautions when Using CAN Controller
455
CHAPTER 23 CAN CONTROLLER
23.1
Features of CAN Controller
The CAN controller is a module built into a 16-bit microcontroller (F2MC-16LX). The CAN
(Controller Area Network) is the standard protocol for serial communication between
automobile controllers and is widely used in industrial applications.
■ Features of CAN Controller
The CAN controller has the following features:
● Conforms to CAN Specification Version 2.0 Part A and B
Supports transmission/reception in standard frame and extended frame formats
● Supports transmitting of data frames by receiving remote frames
● 16 transmitting/receiving message buffers
29-bit ID and 8-byte data
Multi-level message buffer configuration
● Supports full-bit comparison, full-bit mask and partial bit mask filtering.
Two acceptance mask registers in either standard frame format or extended frame formats
● Bit rate programmable from 10 kbps to 1 Mbps (A minimum 8 MHz machine clock is required if 1 Mbps
is used)
456
CHAPTER 23 CAN CONTROLLER
23.2
Block Diagram of CAN Controller
Figure 23.2-1 shows a block diagram of the CAN controller.
■ Block Diagram of CAN Controller
Figure 23.2-1 Block Diagram of CAN Controller
TQ (Operating clock)
F2MC-16LX bus
Prescaler
1 to 64 frequency division
Clock
Bit timing generation
SYNC, TSEG1, TSEG2
PSC
TS1
BTR
TS2
RSJ
TOE
TS
RS
CSR
HALT
NIE
NT
Node status change
interrupt generation
IDLE, INT, SUSPND,
transmit, receive,
ERR, OVRLD
Bus state
machine
Node status
change interrupt
NS1,NS0
Error
control
RTEC
Tr ansmitting/receiving
sequencer
BVALR
TREQR
TBFx, clear
Tr ansmitting
buffer x decision
TBFx
Data
counter
Error frame
generation
Acceptance
filter control
Overload
frame
generation
TDLC RDLC
TBFx
IDSEL
BITER, STFER,
CRCER, FRMER,
ACKER
TCANR
Output
driver
ARBLOST
TX
TRTRR
TCR
Stuffing
Tr ansmission
shift register
RFWTR
TBFx, set, clear
Tr ansmission
complete
interrupt
Tr ansmission complete
interrupt generation
TDLC
TIER
CRC
generation
ACK
generation
CRCER
RBFx, set
RDLC
RCR
Reception
complete
interrupt
Reception complete
interrupt generation
RIER
RBFx, TBFx, set, clear
CRC generation/error
check
Receive shift
register
STFER
Destuffing/stuffing
error check
RRTRR
RBFx, set
IDSEL
ROVRR
ARBLOST
AMSR
AMR0
0
1
Acceptance
filter
Receiving buffer x
decision
BITER
Bit error
check
ACKER
Acknowledgment
error check
AMR1
RBFx
IDR0 to IDR15
DLCR0 to DLCR15
DTR0 to DTR15
RAM
RAM address
generation
Arbitration
check
FRMER
Form error
check
PH1
Input
latch
RX
RBFx, TBFx, RDLC, TDLC, IDSEL
LEIR
LDER
457
CHAPTER 23 CAN CONTROLLER
23.3
List of Overall Control Registers
Table 23.3-1 lists overall control registers.
■ List of Overall Control Registers
Table 23.3-1 List of Overall Registers (1/2)
Address
Register
CAN0
CAN1
CAN2 *
CAN3 *
CAN4 *
000070H
000080H
003570H
003580H
003590H
000071H
000081H
003571H
003581H
003591H
000072H
000082H
003572H
003582H
003592H
000073H
000083H
003573H
003583H
003593H
000074H
000084H
003574H
003584H
003594H
000075H
000085H
003575H
003585H
003595H
000076H
000086H
003576H
003586H
003596H
000077H
000087H
003577H
003587H
003597H
000078H
000088H
003578H
003588H
003598H
000079H
000089H
003579H
003589H
003599H
00007AH
00008AH
00357AH
00358AH
00359AH
00007BH
00008BH
00357BH
00358BH
00359BH
00007CH
00008CH
00357CH
00358CH
00359CH
00007DH
00008DH
00357DH
00358DH
00359DH
00007EH
00008EH
00357EH
00358EH
00359EH
00007FH
00008FH
00357FH
00358FH
00359FH
003700H
003900H
003B00H
003D00H
003F00H
003701H
003901H
003B01H
003D01H
003F01H
003702H
003902H
003B02H
003D02H
003F02H
003703H
003903H
003B03H
003D03H
003F03H
003704H
003904H
003B04H
003D04H
003F04H
003705H
003905H
003B05H
003D05H
003F05H
003706H
003906H
003B06H
003D06H
003F06H
003707H
003907H
003B07H
003D07H
003F07H
003708H
003908H
003B08H
003D08H
003F08H
003709H
003909H
003B09H
003D09H
003F09H
00370AH
00390AH
003B0AH
003D0AH
003F0AH
00370BH
00390BH
003B0BH
003D0BH
003F0BH
458
Abbreviation Access
Initial Value
Message buffer
valid register
BVALR
R/W
00000000 00000000B
Transmit request
register
TREQR
R/W
00000000 00000000B
Transmit cancel
register
TCANR
W
00000000 00000000B
Transmit complete
register
TCR
R/W
00000000 00000000B
Receive complete
register
RCR
R/W
00000000 00000000B
Remote request
receiving register
RRTRR
R/W
00000000 00000000B
Receive overrun
register
ROVRR
R/W
00000000 00000000B
Receive interrupt
enable register
RIER
R/W
00000000 00000000B
Control status
register
CSR
R/W, R
00---000 0----0-1B
Last event
indicator register
LEIR
R/W
-------- 000-0000B
Receive/
transmit
error counter
RTEC
R
00000000 00000000B
Bit timing
register
BTR
R/W
-1111111 11111111B
IDE register
IDER
R/W
XXXXXXXX XXXXXXXXB
TRTRR
R/W
00000000 00000000B
Transmit RTR
register
CHAPTER 23 CAN CONTROLLER
Table 23.3-1 List of Overall Registers (2/2)
Address
Register
CAN0
CAN1
CAN2 *
CAN3 *
CAN4 *
00370CH
00390CH
003B0CH
003D0CH
003F0CH
00370DH
00390DH
003B0DH
003D0DH
003F0DH
00370EH
00390EH
003B0EH
003D0EH
003F0EH
00370FH
00390FH
003B0FH
003D0FH
003F0FH
003710H
003910H
003B10H
003D10H
003F10H
003711H
003911H
003B11H
003D11H
003F11H
003712H
003912H
003B12H
003D12H
003F12H
003713H
003913H
003B13H
003D13H
003F13H
003714H
003914H
003B14H
003D14H
003F14H
003715H
003915H
003B15H
003D15H
003F15H
003716H
003916H
003B16H
003D16H
003F16H
003717H
003917H
003B17H
003D17H
003F17H
003718H
003918H
003B18H
003D18H
003F18H
003719H
003919H
003B19H
003D19H
003F19H
00371AH
00391AH
003B1AH
003D1AH
003F1AH
00371BH
00391BH
003B1BH
003D1BH
003F1BH
Abbreviation Access
Initial Value
Remote frame
receive waiting
register
RFWTR
R/W
XXXXXXXX XXXXXXXXB
Transmit
interrupt enable
register
TIER
R/W
00000000 00000000B
Acceptance mask
select
register
XXXXXXXX XXXXXXXXB
AMSR
R/W
XXXXXXXX XXXXXXXXB
XXXXXXXX XXXXXXXXB
Acceptance mask
register 0
AMR0
R/W
XXXXX--- XXXXXXXXB
XXXXXXXX XXXXXXXXB
Acceptance mask
register 1
AMR1
R/W
XXXXX--- XXXXXXXXB
*: CAN2, CAN3, CAN4 are not supported in all devices of the MB90390 series
459
CHAPTER 23 CAN CONTROLLER
23.4
List of Message Buffers (ID Registers)
Table 23.4-1 lists message buffers (ID registers).
■ List of Message Buffers (ID Registers)
Table 23.4-1 List of Message Buffers (ID Registers) (1/3)
Address
Register
CAN0
CAN1
CAN2 *
CAN3 *
CAN4 *
003600H
to
00361FH
003800H
to
00381FH
003A00H
to
003A1FH
003C00H
to
003C1FH
003E00H
to
003E1FH
003620H
003820H
003A20H
003C20H
003E20H
003621H
003821H
003A21H
003C21H
003E21H
003622H
003822H
003A22H
003C22H
003E22H
003623H
003823H
003A23H
003C23H
003E23H
003624H
003824H
003A24H
003C24H
003E24H
003625H
003825H
003A25H
003C25H
003E25H
003626H
003826H
003A26H
003C26H
003E26H
003627H
003827H
003A27H
003C27H
003E27H
003628H
003828H
003A28H
003C28H
003E28H
003629H
003829H
003A29H
003C29H
003E29H
00362AH
00382AH
003A2AH
003C2AH
003E2AH
00362BH
00382BH
003A2BH
003C2BH
003E2BH
00362CH
00382CH
003A2CH
003C2CH
003E2CH
00362DH
00382DH
003A2DH
003C2DH
003E2DH
00362EH
00382EH
003A2EH
003C2EH
003E2EH
00362FH
00382FH
003A2FH
003C2FH
003E2FH
003630H
003830H
003A30H
003C30H
003E30H
003631H
003831H
003A31H
003C31H
003E31H
003632H
003832H
003A32H
003C32H
003E32H
003633H
003833H
003A33H
003C33H
003E33H
003634H
003834H
003A34H
003C34H
003E34H
003635H
003835H
003A35H
003C35H
003E35H
003636H
003836H
003A36H
003C36H
003E36H
003637H
003837H
003A37H
003C37H
003E37H
Generalpurpose RAM
Access
Initial Value
-
R/W
XXXXXXXXB
to
XXXXXXXXB
XXXXXXXX XXXXXXXXB
ID register 0
IDR0
R/W
XXXXX--- XXXXXXXXB
XXXXXXXX XXXXXXXXB
ID register 1
IDR1
R/W
XXXXX--- XXXXXXXXB
XXXXXXXX XXXXXXXXB
ID register 2
IDR2
R/W
XXXXX--- XXXXXXXXB
XXXXXXXX XXXXXXXXB
ID register 3
IDR3
R/W
XXXXX--- XXXXXXXXB
XXXXXXXX XXXXXXXXB
ID register 4
IDR4
R/W
XXXXX--- XXXXXXXXB
XXXXXXXX XXXXXXXXB
ID register 5
460
Abbreviation
IDR5
R/W
XXXXX--- XXXXXXXXB
CHAPTER 23 CAN CONTROLLER
Table 23.4-1 List of Message Buffers (ID Registers) (2/3)
Address
Register
CAN0
CAN1
CAN2 *
CAN3 *
CAN4 *
003638H
003838H
003A38H
003C38H
003E38H
003639H
003839H
003A39H
003C39H
003E39H
00363AH
00383AH
003A3AH
003C3AH
003E3AH
00363BH
00383BH
003A3BH
003C3BH
003E3BH
00363CH
00383CH
003A3CH
003C3CH
003E3CH
00363DH
00383DH
003A3DH
003C3DH
003E3DH
00363EH
00383EH
003A3EH
003C3EH
003E3EH
00363FH
00383FH
003A3FH
003C3FH
003E3FH
003640H
003840H
003A40H
003C40H
003E40H
003641H
003841H
003A41H
003C41H
003E41H
003642H
003842H
003A42H
003C42H
003E42H
003643H
003843H
003A43H
003C43H
003E43H
003644H
003844H
003A44H
003C44H
003E44H
003645H
003845H
003A45H
003C45H
003E45H
003646H
003846H
003A46H
003C46H
003E46H
003647H
003847H
003A47H
003C47H
003E47H
003648H
003848H
003A48H
003C48H
003E48H
003649H
003849H
003A49H
003C49H
003E49H
00364AH
00384AH
003A4AH
003C4AH
003E4AH
00364BH
00384BH
003A4BH
003C4BH
003E4BH
00364CH
00384CH
003A4CH
003C4CH
003E4CH
00364DH
00384DH
003A4DH
003C4DH
003E4DH
00364EH
00384EH
003A4EH
003C4EH
003E4EH
00364FH
00384FH
003A4FH
003C4FH
003E4FH
003650H
003850H
003A50H
003C50H
003E50H
003651H
003851H
003A51H
003C51H
003E51H
003652H
003852H
003A52H
003C52H
003E52H
003653H
003853H
003A53H
003C53H
003E53H
003654H
003854H
003A54H
003C54H
003E54H
003655H
003855H
003A55H
003C55H
003E55H
003656H
003856H
003A56H
003C56H
003E56H
003657H
003857H
003A57H
003C57H
003E57H
Abbreviation
Access
Initial Value
XXXXXXXX XXXXXXXXB
ID register 6
IDR6
R/W
XXXXX--- XXXXXXXXB
XXXXXXXX XXXXXXXXB
ID register 7
IDR7
R/W
XXXXX--- XXXXXXXXB
XXXXXXXX XXXXXXXXB
ID register 8
IDR8
R/W
XXXXX--- XXXXXXXXB
XXXXXXXX XXXXXXXXB
ID register 9
IDR9
R/W
XXXXX--- XXXXXXXXB
XXXXXXXX XXXXXXXXB
ID register 10
IDR10
R/W
XXXXX--- XXXXXXXXB
XXXXXXXX XXXXXXXXB
ID register 11
IDR11
R/W
XXXXX--- XXXXXXXXB
XXXXXXXX XXXXXXXXB
ID register 12
IDR12
R/W
XXXXX--- XXXXXXXXB
XXXXXXXX XXXXXXXXB
ID register 13
IDR13
R/W
XXXXX--- XXXXXXXXB
461
CHAPTER 23 CAN CONTROLLER
Table 23.4-1 List of Message Buffers (ID Registers) (3/3)
Address
Register
CAN0
CAN1
CAN2 *
CAN3 *
CAN4 *
003658H
003858H
003A58H
003C58H
003E58H
003659H
003859H
003A59H
003C59H
003E59H
00365AH
00385AH
003A5AH
003C5AH
003E5AH
00365BH
00385BH
003A5BH
003C5BH
003E5BH
00365CH
00385CH
003A5CH
003C5CH
003E5CH
00365DH
00385DH
003A5DH
003C5DH
003E5DH
00365EH
00385EH
003A5EH
003C5EH
003E5EH
00365FH
00385FH
003A5FH
003C5FH
003E5FH
Access
Initial Value
XXXXXXXX XXXXXXXXB
ID register 14
IDR14
R/W
XXXXX--- XXXXXXXXB
XXXXXXXX XXXXXXXXB
ID register 15
*: CAN2, CAN3, CAN4 are not supported in all devices of the MB90390 series
462
Abbreviation
IDR15
R/W
XXXXX--- XXXXXXXXB
CHAPTER 23 CAN CONTROLLER
23.5
List of Message Buffers (DLC Registers and Data
Registers)
Table 23.5-1 lists message buffers (DLC registers) and message buffers (data registers).
■ List of Message Buffers (DLC Registers and Data Registers)
Table 23.5-1 List of Message Buffers (DLC Registers and Data Register) (1/3)
Address
Register
CAN0
CAN1
CAN2 *
CAN3 *
CAN4 *
003660H
003860H
003A60H
003C60H
003E60H
003661H
003861H
003A61H
003C61H
003E61H
003662H
003862H
003A62H
003C62H
003E62H
003663H
003863H
003A63H
003C63H
003E63H
003664H
003864H
003A64H
003C64H
003E64H
003665H
003865H
003A65H
003C65H
003E65H
003666H
003866H
003A66H
003C66H
003E66H
003667H
003867H
003A67H
003C67H
003E67H
003668H
003868H
003A68H
003C68H
003E68H
003669H
003869H
003A69H
003C69H
003E69H
00366AH
00386AH
003A6AH
003C6AH
003E6AH
00366BH
00386BH
003A6BH
003C6BH
003E6BH
00366CH
00386CH
003A6CH
003C6CH
003E6CH
00366DH
00386DH
003A6DH
003C6DH
003E6DH
00366EH
00386EH
003A6EH
003C6EH
003E6EH
00366FH
00386FH
003A6FH
003C6FH
003E6FH
003670H
003870H
003A70H
003C70H
003E70H
003671H
003871H
003A71H
003C71H
003E71H
003672H
003872H
003A72H
003C72H
003E72H
003673H
003873H
003A73H
003C73H
003E73H
003674H
003874H
003A74H
003C74H
003E74H
003675H
003875H
003A75H
003C75H
003E75H
003676H
003876H
003A76H
003C76H
003E76H
003677H
003877H
003A77H
003C77H
003E77H
003678H
003878H
003A78H
003C78H
003E78H
003679H
003879H
003A79H
003C79H
003E79H
Abbreviation
Access
Initial Value
DLC register 0
DLCR0
R/W
----XXXXB
DLC register 1
DLCR1
R/W
----XXXXB
DLC register 2
DLCR2
R/W
----XXXXB
DLC register 3
DLCR3
R/W
----XXXXB
DLC register 4
DLCR4
R/W
----XXXXB
DLC register 5
DLCR5
R/W
----XXXXB
DLC register 6
DLCR6
R/W
----XXXXB
DLC register 7
DLCR7
R/W
----XXXXB
DLC register 8
DLCR8
R/W
----XXXXB
DLC register 9
DLCR9
R/W
----XXXXB
DLC register 10
DLCR10
R/W
----XXXXB
DLC register 11
DLCR11
R/W
----XXXXB
DLC register 12
DLCR12
R/W
----XXXXB
463
CHAPTER 23 CAN CONTROLLER
Table 23.5-1 List of Message Buffers (DLC Registers and Data Register) (2/3)
Address
Register
Abbreviation
Access
Initial Value
DLC register 13
DLCR13
R/W
----XXXXB
DLC register 14
DLCR14
R/W
----XXXXB
DLC register 15
DLCR15
R/W
----XXXXB
003E80H
to
003E87H
Data register 0 (8
bytes)
DTR0
R/W
XXXXXXXXB
to
XXXXXXXXB
003C88H
to
003C8FH
003E88H
to
003E8FH
Data register 1 (8
bytes)
DTR1
R/W
XXXXXXXXB
to
XXXXXXXXB
003A90H
to
003A97H
003C90H
to
003C97H
003E90H
to
003E97H
Data register 2 (8
bytes)
DTR2
R/W
XXXXXXXXB
to
XXXXXXXXB
003898H
to
00389FH
003A98H
to
003A9FH
003C98H
to
003C9FH
003E98H
to
003E9FH
Data register 3 (8
bytes)
DTR3
R/W
XXXXXXXXB
to
XXXXXXXXB
0036A0H
to
0036A7H
0038A0H
to
0038A7H
003AA0H
to
003AA7H
003CA0H
to
003CA7H
003EA0H
to
003EA7H
Data register 4 (8
bytes)
DTR4
R/W
XXXXXXXXB
to
XXXXXXXXB
0036A8H
to
0036AFH
0038A8H
to
0038AFH
003AA8H
to
003AAFH
003CA8H
to
003CAFH
003EA8H
to
003EAFH
Data register 5 (8
bytes)
DTR5
R/W
XXXXXXXXB
to
XXXXXXXXB
0036B0H
to
0036B7H
0038B0H
to
0038B7H
003AB0H
to
003AB7H
003CB0H
to
003CB7H
003EB0H
to
003EB7H
Data register 6 (8
bytes)
DTR6
R/W
XXXXXXXXB
to
XXXXXXXXB
0036B8H
to
0036BFH
0038B8H
to
0038BFH
003AB8H
to
003ABFH
003CB8H
to
003CBFH
003EB8H
to
003EBFH
Data register 7 (8
bytes)
DTR7
R/W
XXXXXXXXB
to
XXXXXXXXB
0036C0H
to
0036C7H
0038C0H
to
0038C7H
003AC0H
to
003AC7H
003CC0H
to
003CC7H
003EC0H
to
003EC7H
Data register 8 (8
bytes)
DTR8
R/W
XXXXXXXXB
to
XXXXXXXXB
0036C8H
to
0036CFH
0038C8H
to
0038CFH
003AC8H
to
003ACFH
003CC8H
to
003CCFH
003EC8H
to
003ECFH
Data register 9 (8
bytes)
DTR9
R/W
XXXXXXXXB
to
XXXXXXXXB
0036D0H
to
0036D7H
0038D0H
to
0038D7H
003AD0H
to
003AD7H
003CD0H
to
003CD7H
003ED0H
to
003ED7H
Data register 10 (8
bytes)
DTR10
R/W
XXXXXXXXB
to
XXXXXXXXB
0036D8H
to
0036DFH
0038D8H
to
0038DFH
003AD8H
to
003ADFH
003CD8H
to
003CDFH
003ED8H
to
003EDFH
Data register 11 (8
bytes)
DTR11
R/W
XXXXXXXXB
to
XXXXXXXXB
CAN0
CAN1
CAN2 *
CAN3 *
CAN4 *
00367AH
00387AH
003A7AH
003C7AH
003E7AH
00367BH
00387BH
003A7BH
003C7BH
003E7BH
00367CH
00387CH
003A7CH
003C7CH
003E7CH
00367DH
00387DH
003A7DH
003C7DH
003E7DH
00367EH
00387EH
003A7EH
003C7EH
003E7EH
00367FH
00387FH
003A7FH
003C7FH
003E7FH
003680H
to
003687H
003880H
to
003887H
003A80H
to
003A87H
003C80H
to
003C87H
003688H
to
00368FH
003888H
to
00388FH
003A88H
to
003A8FH
003690H
to
003697H
003890H
to
003897H
003698H
to
00369FH
464
CHAPTER 23 CAN CONTROLLER
Table 23.5-1 List of Message Buffers (DLC Registers and Data Register) (3/3)
Address
Register
Abbreviation
Access
Initial Value
Data register 12 (8
bytes)
DTR12
R/W
XXXXXXXXB
to
XXXXXXXXB
003EE8H
to
003EEFH
Data register 13 (8
bytes)
DTR13
R/W
XXXXXXXXB
to
XXXXXXXXB
003CF0H
to
003CF7H
003EF0H
to
003EF7H
Data register 14 (8
bytes)
DTR14
R/W
XXXXXXXXB
to
XXXXXXXXB
003CF8H
to
003CFFH
003EF8H
to
003EFFH
Data register 15 (8
bytes)
DTR15
R/W
XXXXXXXXB
to
XXXXXXXXB
CAN0
CAN1
CAN2 *
CAN3 *
CAN4 *
0036E0H
to
0036E7H
0038E0H
to
0038E7H
003AE0H
to
003AE7H
003CE0H
to
003CE7H
003EE0H
to
003EE7H
0036E8H
to
0036EFH
0038E8H
to
0038EFH
003AE8H
to
003AEFH
003CE8H
to
003CEFH
0036F0H
to
0036F7H
0038F0H
to
0038F7H
003AF0H
to
003AF7H
0036F8H
to
0036FFH
0038F8H
to
0038FFH
003AF8H
to
003AFFH
*: CAN2, CAN3, CAN4 are not supported in all devices of the MB90390 series
465
CHAPTER 23 CAN CONTROLLER
23.6
Classifying the CAN Controller Registers
There are three types of CAN controller registers:
• Overall control registers
• Message buffer control registers
• Message buffers
■ Overall Control Registers
The overall control registers are the following four registers:
• Control status register (CSR)
• Last event indicator register (LEIR)
• Receive and transmit error counter (RTEC)
• Bit timing register (BTR)
■ Message Buffer Control Registers
The message buffer control registers are the following 14 registers:
• Message buffer valid register (BVALR)
• IDE register (IDER)
• Transmission request register (TREQR)
• Transmission RTR register (TRTRR)
• Remote frame receiving wait register (RFWTR)
• Transmission cancel register (TCANR)
• Transmission complete register (TCR)
• Transmission interrupt enable register (TIER)
• Reception complete register (RCR)
• Remote request receiving register (RRTRR)
• Receive overrun register (ROVRR)
• Reception interrupt enable register (RIER)
• Acceptance mask select register (AMSR)
• Acceptance mask registers 0 and 1 (AMR0 and AMR1)
■ Message Buffers
The message buffers are the following three registers:
• ID register x (x = 0 to 15) (IDRx)
• DLC register x (x = 0 to 15) (DLCRx)
• Data register x (x = 0 to 15) (DTRx)
466
CHAPTER 23 CAN CONTROLLER
23.6.1
Control Status Register (CSR)
The lower 8 bits with the CAN control status register (CSR) is prohibited from executing
any bit manipulation instructions (Read-Modify-Write (RMW) instructions).
Only in the case of HALT bits unchanged, use any bit manipulation instructions without
problems (initialization of the macro instructions, etc.).
■ Control Status Register (CSR) (Lower)
Figure 23.6-1 Configuration of the Control Status Register (Lower Byte)
Address:
bit
7
CAN0: 003700 H
CAN1: 003900 H
CAN2: 003B00 H
CAN3: 003D00 H R/W
CAN4: 003F00 H
6
5
4
3
-
-
-
-
-
-
-
-
2
1
0
CSR0/CSR1/CSR2/CSR3/CSR4 (lower)
Initial value
0 X X X X 0 X 1B
R/W W R/W
bit 0
HALT
Bus Operation stop bit
0
Write: Cancels bus operation stop
Read: Bus operation not in stop mode
1
Write: Stops bus operation
Read: Bus operation in stop mode
bit 1
Reserved
0
bit 2
NIE
Reserved bit
Do not write "1" to this bit
Node status transition interrupt enable bit
0
Node status transition interrupt enabled
1
Node status transition interrupt disabled
bit 7
TOE
R/W
:
Readable and writable
W
:
Write only
X
:
Undefined value
-
:
Undefined
:
Initial value
Transmit output enable bit
0
General-purpose port pin
1
Transmit pin of CAN controller
467
CHAPTER 23 CAN CONTROLLER
■ Control Status Register (CSR-lower) Contents
Table 23.6-1 Function of Each Bit of the Control Status Register (Lower)
Bit name
bit7
bit6 to bit3
TOE:
Transmit output
enable bit
Function
Writing "1" to this bit switches from a general-purpose port pin to a transmit pin of the
CAN controller.
"0": General-purpose port pin
"1": Transmit pin of CAN controller
Undefined
bit2
NIE:
Node status
transition flag bit
This bit enables or disables a node status transition interrupt (when NT = 1).
"0": Node status transition interrupt disabled
"1": Node status transition interrupt enabled
bit1
Reserved bit
This is a reserved bit. Do not write "1" to this bit.
This bit controls the bus halt. The halt state of the bus can be checked by reading this bit.
Writing to this bit
"0": Cancels bus halt
"1": Halt bus
Reading this bit
"0": Bus operation not in stop state
"1": Bus operation in stop state
bit0
468
HALT:
Bus operation
stop bit
Note :
Before writing "0" to this bit while node status is "Bus Off", make sure that this bit is
"1".
Example program:
switch ( IO_CANCT0.CSR.bit.NS )
{
case 0 : /* error active */
break;
case 1 : /* warning */
break;
case 2 : /* error passive */
break;
default : /* bus off */
for ( i=0; ( i <= 500 ) && ( IO_CANCT0.CSR.bit.HALT == 0); i++);
IO_CANCT0.CSR.word = 0x0084; /* HALT = 0 */
break;
}
* The variable "i" is used for fail-safe.
CHAPTER 23 CAN CONTROLLER
■ Control Status Register (CSR) (Upper)
Figure 23.6-2 Configuration of the Control Status Register (Upper Byte)
Address:
bit 15
CAN0: 003701 H
CAN1: 003901 H
CAN2: 003B01 H
CAN3: 003D01 H
CAN4: 003F01 H
R
14
R
13
12
11
-
-
-
-
-
-
10
9
8
CSR0/CSR1/CSR2/CSR3/CSR4 (upper bit)
Initial value
00XXX000B
R/W R
R
bit 9
NS1
bit 8
NS0
Node Status bit
0
0
Error active
0
1
Warning (error active)
1
0
Error passive
1
1
Bus off
bit 10
NT
Node status transition flag bit
0
No change
1
Status changed
bit 14
RS
Receive status bit
0
Message not being received
1
Message being received
bit 15
TS
R/W
:
R
:
Read only
X
:
Undefined value
:
Undefined
:
Initial value
-
Readable and writable
Transmit status bit
0
Message not being transmitted
1
Message being transmitted
469
CHAPTER 23 CAN CONTROLLER
■ Control Status Register (CSR-upper) Contents
Table 23.6-2 Function of Each Bit of the Control Status Register (Upper)
Bit name
bit15
bit14
bit13 to
bit11
bit10
bit9, bit8
470
Function
TS:
Transmit status
bit
This bit indicates whether a message is being transmitted.
"0": Message not being transmitted
"1": Message being transmitted
This bit is "0" even while error and overload frames are transmitted.
RS:
Receive status bit
This bit indicates whether a message is being received.
"0": Message not being received
"1": Message being received
While a message is on the bus, this bit becomes "1". Therefore, this bit is also "1" while
a message is being transmitted. This bit does not necessarily indicates whether a
receiving message passes through the acceptance filter.
As a result, when this bit is "0", it implies that the bus operation is stopped (HALT = 0);
the bus is in the intermission/bus idle or a error/overload frame is on the bus.
−
Undefined
NT:
Node status
transition flag
If the node status is changed to increment, or from Bus Off to Error Active, this bit is set
to "1".
In other words, the NT bit is set to "1" if the node status is changed from Error Active
(00B) to Warning (01B), from Warning (01B) to Error Passive (10B), from Error Passive
(10B) to Bus Off (11B), and from Bus Off (11B) to Error Active (00B). Numbers in
parentheses indicate the values of NS1 and NS0 bits.
When the node status transition interrupt enable bit (NIE) is "1", an interrupt is
generated. Writing "0" sets the NT bit to "0". Writing 1 to the NT bit is ignored. "1" is
read when a Read Modify Write (RMW) instruction is performed.
NS1, NS0:
Node status bit 1
and 0
These bits indicate the current node status.
See Table 23.6-3 below for details.
CHAPTER 23 CAN CONTROLLER
Table 23.6-3 Correspondence between NS1 and NS0 and Node Status
NS1
NS0
Node Status
0
0
Error active
0
1
Warning (error active)
1
0
Error passive
1
1
Bus off
Note:
Warning (error active) is included in the error active in CAN Specification 2.0B for the node status,
however, indicates that the transmit error counter or receive error counter has exceeded 96. The
node status change diagram is shown in Figure 23.6-3.
Figure 23.6-3 Node Status Transition Diagram
Hardware reset
REC: Receive error counter
TEC: Tr ansmit error counter
Error active
After "0" has been written to the HALT bit of
the register(CSR), continuous 11-bit "H"
levels (recessive bits) a reinput 128 times
to the receive input pin (RX).
REC >= 96
or
TEC >= 96
REC < 96
and
TEC < 96
Warning
(Error active)
REC >= 128
or
TEC >= 128
REC < 128
and
TEC < 128
Error
passive
TEC >= 256
Bus off
(HALT =1)
471
CHAPTER 23 CAN CONTROLLER
23.6.2
Bus Operation Stop Bit (HALT = 1)
The bus operation stop bit sets or cancels stopping of bus operation, or indicates its
status.
■ Conditions for Setting Bus Operation Stop (HALT=1)
There are three conditions for setting bus operation stop (HALT = 1):
• After hardware reset
• When node status changed to bus off
• By writing "1" to HALT
Notes:
• The bus operation should be stopped by writing "1" to HALT before the F2MC-16LX is changed in
low-power consumption mode (stop mode and time-base timer mode).
If transmission is in progress when "1" is written to HALT, the bus operation is stopped (HALT =
1) after transmission is terminated. If reception is in progress when "1" is written to HALT, the bus
operation is stopped immediately (HALT = 1). If received messages are being stored in the
message buffer (x), stop the bus operation (HALT = 1) after storing the messages.
• To check whether the bus operation has stopped, always read the HALT bit.
■ Conditions for Canceling Bus Operation Stop (HALT = 0)
By writing "0" to HALT
Notes:
• Canceling the bus operation stop after hardware reset or by writing "1" to HALT as above
conditions is performed after "0" is written to HALT and continuous 11-bit "H" levels (recessive
bits) have been input to the receive input pin (RX) (HALT = 0).
• Canceling the bus operation stop when the node status is changed to bus off as above conditions
is performed after "0" is written to HALT and continuous 11-bit "H" levels (recessive bits) have
been input 128 times to the receive input pin (RX) (HALT = 0). Then, the values of both transmit
and receive error counters reach "0" and the node status is changed to error active.
• When write "0" to HALT during the node status is Bus Off, ensure that "1" is written to this bit.
472
CHAPTER 23 CAN CONTROLLER
■ State during Bus Operation Stop (HALT = 1)
• The bus does not perform any operation, such as transmission and reception.
• The transmit output pin (TX) outputs a "H" level (recessive bit).
• The values of other registers and error counters are not changed.
Note:
The bit timing register (BTR) should be set during bus operation stop (HALT = 1).
473
CHAPTER 23 CAN CONTROLLER
23.6.3
Last Event Indicator Register (LEIR)
This register indicates the last event.
The NTE, TCE, and RCE bits are exclusive. When the corresponding bit of the last event
is set to "1", other bits are set to 0s.
■ Last Event Indicator Register (LEIR)
Figure 23.6-4 Configuration of the Last Event Indicator Register (LEIR)
Address:
7
bit
CAN0: 003702 H
CAN1: 003902 H
CAN2: 003B02 H
CAN3: 003D02 H
CAN4: 003F02 H
6
5
4
3
2
1
0
R/W R/W R/W
-
LEIR0, LEIR1, LEIR2, LEIR3, LEIR4
Initial value
0 0 0 X 0 0 0 0B
R/W R/W R/W R/W
bit 3
MBP3
bit 2
bit 1
MBP2
MBP1
bit 0
Message buffer
pointer bits
MBP0
0 to 15 (initial value: "0000B")
bit 5
RCE
Receive completion event bit
read
write
0
-
clear bit
1
receive completion
ignored
bit 6
Transmit completion event bit
TCE
read
write
0
-
clear bit
1
transmit completion
ignored
bit 7
NTE
Node status transition event bit
read
474
R/W
:
Readable and writable
0
X
:
Undefined value
1
-
:
Undefined
:
Initial value
transition event
write
clear bit
ignored
CHAPTER 23 CAN CONTROLLER
■ Last Event Indicator Register (LEIR) Contents
Table 23.6-4 Function of Each Bit of the Last Event Indicator Register
Bit name
Function
NTE:
Node status
transition event
bit
When this bit is "1", node status transition is the last event.
This bit is set to "1" at the same time the NT bit of the control status register (CSR) is
set.
This bit is also set to "1" irrespective of the setting of the node status transition interrupt
enable bit (NIE) of CSR.
Writing "0" to this bit sets the NTE bit to "0". Writing "1" to this bit is ignored.
"1" is read when a Read Modify Write (RMW) instruction is executed.
TCE:
Transmit
completion event
bit
When this bit is "1", it indicates that transmit completion is the last event.
This bit is set to "1" at the same time as any one of the bits of the transmit completion
register (TCR). This bit is also set to "1", irrespective of the settings of the bits of the
transmit interrupt enable register (TIER).
Writing "0" sets this bit to "0". Writing "1" to this bit is ignored.
"1" is read when a Read Modify Write (RMW) instruction is performed.
When this bit is set to "1", the MBP3 to MBP0 bits are used to indicate the message
buffer number completing the transmit operation.
bit5
RCE:
Receive
completion event
bit
When this bit is "1", it indicates that receive completion is the last event.
This bit is set to "1" at the same time as any one of the bits of the receive complete
register (RCR). This bit is also set to "1" irrespective of the settings of the bits of the
receive interrupt enable register (RIER).
Writing "0" sets this bit to "0". Writing "1" to this bit is ignored.
"1" is read when a Read Modify Write (RMW) instruction is performed.
When this bit is set to "1", the MBP3 to MBP0 bits are used to indicate the message
buffer number completing the receive operation.
bit4
Undefined
bit7
bit6
bit3 to bit0
MBP3 to MBP0:
Message buffer
pointer bits
−
When the TCE or RCE bit is set to "1", these bits indicate the corresponding numbers of
the message buffers (0 to 15). If the NTE bit is set to 1, these bits have no meaning.
Writing "0" sets these bits to "0"s. Writing "1" to these bits is ignored.
"1"s are read when a Read Modify Write (RMW) instruction is performed.
If LEIR is accessed within an CAN interrupt handler, the event causing the interrupt is
not necessarily the same as indicated by LEIR. In the time from interrupt request to the
LEIR access by the interrupt handler there may occur other CAN events.
475
CHAPTER 23 CAN CONTROLLER
23.6.4
Receive and Transmit Error Counters (RTEC)
The receive and transmit error counters indicate the counts for transmission errors and
reception errors defined in the CAN specifications. These registers can only be read.
■ Receive and Transmit Error Counters (RTEC)
Figure 23.6-5 Configuration of the Receive and Transmit Error Counters
Address:
bit 15 14 13 12 11 10 9
8
CAN0: 003705 H
TEC7 TEC6 TEC5 TEC4 TEC3 TEC2 TEC1 TEC0
CAN1: 003905 H
CAN2: 003B05 H
CAN3: 003D05 H
R
R
R
R R
R
R
R
CAN4: 003F05 H
Address:
6
5
4
3
2
1
0
bit 7
CAN0: 003704 H
REC7 REC6 REC5 REC4 REC3 REC2 REC1 REC0
CAN1: 003904 H
CAN2: 003B04 H
R
R
R
R R
R
R
R
CAN3: 003D04 H
CAN4: 003F04 H
RTEC (upper)
Initial value
00000000B
RTEC (lower)
Initial value
00000000B
■ Receive and Transmit Error Counters (RTEC) Contents
Table 23.6-5 Function of Each Bit of the Receive and Transmit Error Counters (RTEC)
Bit name
Function
bit15 to
bit8
TEC7 to TEC0:
Transmit error
counter bits
These are transmit error counters.
TEC7 to TEC0 values indicate 0 to 7 when the counter value is more than 256, and the
subsequent increment is not counted for counter value. In this case, Bus Off is indicated
for the node status (NS1 and NS0 of control status register CSR = 11B).
bit7 to bit0
REC7 to REC0:
Receive error
counter bits
These are receive error counters.
REC7 to REC0 values indicate 0 to 7 when the counter value is more than 256, and the
subsequent increment is not counted for counter value. In this case, Error Passive is
indicated for the node status (NS1 and NS0 of control status register CSR = 10B).
476
CHAPTER 23 CAN CONTROLLER
23.6.5
Bit Timing Register (BTR)
Bit timing register (BTR) stores the prescaler and bit timing setting.
■ Bit Timing Register (BTR)
Figure 23.6-6 Configuration of the Bit Timing Register (BTR)
Address:
bit 15
CAN0: 003707 H
CAN1: 003907 H
CAN2: 003B07 H
CAN3: 003D07 H
CAN4: 003F07 H
Address:
R/W
bit
CAN0: 003706 H
CAN1: 003906 H
CAN2: 003B06 H
CAN3: 003D06 H
CAN4: 003F06 H
: Readable and writable
14
13
12
11
10
9
8
-
TS2.2 TS2.1 TS2.0 TS1.3 TS1.2 TS1.1 TS1.0
-
R/W R/W R/W R/W R/W R/W R/W
7
6
5
4
3
2
1
0
RSJ1 RSJ0 PSC5 PSC4 PSC3 REC2 PSC1 PSC0
R/W R/W R/W R/W R/W R/W R/W R/W
BTR (upper)
Initial value
X 1 1 1 1 1 1 1B
BTR (lower)
Initial value
11111111B
Note:
This register should be set during bus operation stop (HALT = 1).
■ Bit Timing Register (BTR) Contents
Table 23.6-6 Function of Each Bit of the Bit Timing Register (BTR)
Bit name
bit15
Function
Undefined
bit14 to
bit12
TS2.2 to TS2.0:
Time segment2
setting bits
These bits define the number of the time quanta (TQ’s) for the time segment 2 (TSEG2).
The time segment 2 is equal to the phase buffer segment 2 (PHASE_SEG2) in the CAN
specification.
bit11 to
bit8
TS1.3 to TS1.0:
Time segment1
setting bits
These bits define the number of the time quanta (TQ’s) for the time segment 1 (TSEG1).
The time segment 1 is equal to the propagation segment (PROP_SEG) + phase buffer
segment 1 (PHASE_SEG1) in the CAN specification.
bit7, bit6
RSJ1, RSJ0:
Resynchronization
jump width setting
bits
These bits define the number of the time quanta (TQ’s) for the resynchronization jump
width.
PSC5 to PSC0:
Prescaler setting
bits
These bits define the time quanta (TQ) of the CAN controller. (see below for details.)
bit5 to bit0
477
CHAPTER 23 CAN CONTROLLER
■ Prescaler Settings
Figure 23.6-7 shows the bit time segment in CAN specification, Figure 23.6-8 shows the bit time
segment in CAN controller.
Figure 23.6-7 Bit Time Segment in CAN Specification
Nominal bit time
SYNC_SEG
PROP_SEG
PHASE_SEG1 PHASE_SEG2
Sample point
Figure 23.6-8 Bit Time Segment in CAN Controller
Nominal bit time
SYNC_SEG
TSEG1
TSEG2
Sample point
The relationship between PSC = PSC5 to PSC0, TSI = TS1.3 to TS1.0, TS2 = TS2.2 to TS1.0, and RSJ =
RSJ1 and RSJ0 when the input clock (CLK), time quanta (TQ), bit time (BT), synchronous segment
(SYNC_SEG), time segment 1 and 2 (TSEG1 and TSEG2), and resynchronization jump width [(RSJ1 and
RSJ0) +1] frequency division is shown below.
The input clock is supplied with the machine clock.
TQ
BT
= (PSC + 1) x CLK
= SYNC_SEG + TSEG1 + TSEG2
= (1 + (TS1 + 1) + (TS2 +1)) x TQ
= (3 + TS1 +TS2) x TQ
RSJW = (RSJ + 1) x TQ
For correct operation, the following conditions should be met.
For 1
PSC
TSEG1
TSEG1
TSEG2
TSEG2
For PSC = 0:
TSEG1
TSEG2
TSEG2
63:
2TQ
RSJW
2TQ
RSJW
5TQ
2TQ
RSJW
In order to meet the bit timing requirements defined in the CAN specification, additions have to be met,
e.g. the propagation delay has to be considered.
478
CHAPTER 23 CAN CONTROLLER
23.6.6
Message Buffer Valid Register (BVALR)
Message buffer valid register (BVALR) stores the validity of the message buffers or
displays their state.
■ Message Buffer Valid Register (BVALR)
Figure 23.6-9 Configuration of the Message Buffer Valid Register (BVALR)
Address:
bit 15
CAN0: 000071 H
CAN1: 000081 H
CAN2: 003571 H
CAN3: 003581 H
CAN4: 003591 H
Address:
bit
CAN0: 000070 H
CAN1: 000080 H
CAN2: 003570 H
CAN3: 003580 H
CAN4: 003590 H
14
13
12
11
10
9
8
BVAL15 BVAL14 BVAL13 BVAL12 BVAL11 BVAL10 BVAL9 BVAL8
BVALRn (upper)
Initial value
00000000B
R/W R/W R/W R/W R/W R/W R/W R/W
7
6
5
4
3
2
1
0
BVAL7 BVAL6 BVAL5 BVAL4 BVAL3 BVAL2 BVAL1 BVAL0
R/W R/W R/W R/W R/W R/W R/W R/W
BVALRn (lower)
Initial value
00000000B
n = 0, 1, 2, 3, 4
[bit15 to bit0] BVAL15 to BVAL0:
"0": Message buffer (x) invalid
"1": Message buffer (x) valid
If the message buffer (x) is set to invalid, it will not transmit or receive messages.
If the buffer is set to invalid during transmission operating, it becomes invalid (BVALx = 0) after the
transmission is completed or terminated by an error.
If the buffer is set to invalid during reception operating, it immediately becomes invalid (BVALx = 0). If
received messages are stored in a message buffer (x), the message buffer (x) is invalid after storing the
messages.
Notes:
• x indicates a message buffer number (x = 0 to 15).
• When invaliding a message buffer (x) by writing "0" to a bit (BVALx), execution of a bit
manipulation instruction is prohibited until the bit is set to "0".
• To invalidate the message buffer (by setting the BVALR: BVAL bit to "0") while the CAN controller
is operating for CAN communication (the read value of the CSR: HALT bit is "0" and the CAN
controller is operating for CAN bus communication to enable transmission and reception), follow
the procedure in Section "23.16 Precautions when Using CAN Controller".
479
CHAPTER 23 CAN CONTROLLER
23.6.7
IDE register (IDER)
This register stores the frame format used by the message buffers (x) during
transmission/reception.
■ IDE Register (IDER)
Figure 23.6-10 Configuration of the IDE Register (IDER)
Address:
bit 15
CAN0: 003709 H
CAN1: 003909 H
CAN2: 003B09 H
CAN3: 003D09 H
CAN4: 003F09 H
Address:
bit
CAN0: 003708 H
CAN1: 003908 H
CAN2: 003B08 H
CAN3: 003D08 H
CAN4: 003F08 H
14
13
12
11
10
9
8
IDE15 IDE14 IDE13 IDE12 IDE11 IDE10 IDE9 IDE8
IDERn(upper)
Initial value
XXXXXXXXB
R/W R/W R/W R/W R/W R/W R/W R/W
7
6
5
4
3
2
IDE7 IDE6 IDE5 IDE4 IDE3 IDE2
1
0
IDE1 IDE0
R/W R/W R/W R/W R/W R/W R/W R/W
IDERn (lower)
Initial value
X X X X X X X XB
n = 0, 1, 2, 3, 4
[bit15 to bit0] IDE15 to IDE0:
"0": The standard frame format (ID11 bit) is used for the message buffer (x).
"1": The extended frame format (ID29 bit) is used for the message buffer (x).
Notes:
• This register should be set when the message buffer (x) is invalid (BVALx of the message buffer
valid register (BVALR) = 0). Setting when the buffer is valid (BVALx = 1) may cause unnecessary
received messages to be stored.
• To invalidate the message buffer (by setting the BVALR: BVAL bit to "0") while the CAN controller
is operating for CAN communication (the read value of the CSR: HALT bit is "0" and the CAN
controller is operating for CAN bus communication to enable transmission and reception), follow
the procedure in Section "23.16 Precautions when Using CAN Controller".
480
CHAPTER 23 CAN CONTROLLER
23.6.8
Transmission Request Register (TREQR)
Transmission request register (TREQR) stores transmission requests to the message
buffers (x) or displays their state.
■ Transmission Request Register (TREQR)
Figure 23.6-11 Configuration of the Transmission Request Register (TREQR)
Address:
bit 15
CAN0: 000073 H
CAN1: 000083 H
CAN2: 003573 H
CAN3: 003583 H
CAN4: 003593 H
14
13
12
11
10
9
8
TREQ15 TREQ14 TREQ13 TREQ12 TREQ11 TREQ10 TREQ9 TREQ8
TREQRn (upper)
Initial value
0 0 0 0 0 0 0 0B
R/W R/W R/W R/W R/W R/W R/W R/W
Address:
7
6
5
4
3
2
1
0
bit
CAN0: 000072 H TREQ7 TREQ6 TREQ5 TREQ4 TREQ3 TREQ2 TREQ1 TREQ0
CAN1: 000082 H
CAN2: 003572 H
CAN3: 003582 H R/W R/W R/W R/W R/W R/W R/W R/W
CAN4: 003592 H
TREQRn (lower)
Initial value
0 0 0 0 0 0 0 0B
n = 0, 1, 2, 3, 4
[bit15 to bit0] TREQ15 to TREQ0:
When "1" is written to TREQx, transmission to the message buffer (x) starts. If RFWTx of the remote
frame receiving wait register (RFWTR) *1 is "0", transmission starts immediately. However, if RFWTx = 1,
transmission starts after waiting until a remote frame is received (RRTRx of the remote request receiving
register (RRTRR)*1 becomes "1"). Transmission starts *2 immediately even when RFWTx = 1, if RRTRx
is already "1" when "1" is written to TREQx.
*1: For RFWTR and TRTRR, see Sections "23.6.9 Transmission RTR Register (TRTRR)" and "23.6.10
Remote Frame Receiving Wait Register (RFWTR)".
*2: For cancellation of transmission, see Sections "23.6.11 Transmission Cancel Register (TCANR)" and
"23.6.12 Transmission Complete Register (TCR)".
Writing "0" to TREQx is ignored.
"0" is read when a Read Modify Write (RMW) instruction is performed.
If clearing (to "0") at completion of the transmit operation and setting by writing "1" are concurrent,
clearing is preferred.
If "1" is written to more than one bit, transmission is performed, starting with the lower-numbered message
buffer (x).
TREQx is "1" while transmission is pending, and becomes "0" when transmission is completed or canceled.
481
CHAPTER 23 CAN CONTROLLER
23.6.9
Transmission RTR Register (TRTRR)
This register stores the RTR (Remote Transmission Request) bits for the message
buffers (x).
■ Transmission RTR Register (TRTRR)
Figure 23.6-12 Configuration of the Transmission RTR Register (TRTRR)
Address:
bit 15
CAN0: 00370B H
CAN1: 00390B H
CAN2: 003B0B H
CAN3: 003D0B H
CAN4: 003F0B H
Address:
bit
CAN0: 00370A H
CAN1: 00390A H
CAN2: 003B0AH
CAN3: 003D0AH
CAN4: 003F0A H
14
13
"1": Remote frame.
482
11
10
9
8
TRTR15 TRTR14 TRTR13 TRTR12 TRTR11 TRTR10 TRTR9 TRTR8
TRTRRn (upper)
Initial value
0 0 0 0 0 0 0 0B
R/W R/W R/W R/W R/W R/W R/W R/W
7
6
5
4
3
2
1
0
TRTR7 TRTR6 TRTR5 TRTR4 TRTR3 TRTR2 TRTR1 TRTR0
R/W R/W R/W R/W R/W R/W R/W R/W
[bit15 to bit0] TRTR15 to TRTR0:
"0": Data frame.
12
TRTRRn (lower)
Initial value
0 0 0 0 0 0 0 0B
n = 0, 1, 2, 3, 4
CHAPTER 23 CAN CONTROLLER
23.6.10
Remote Frame Receiving Wait Register (RFWTR)
Remote frame receiving wait register (RFWTR) stores the conditions for starting
transmission when a request for data frame transmission is set (TREQx of the
transmission request register (TREQR) is "1" and TRTRx of the transmitting RTR
register (TRTRR) is "0").
■ Remote Frame Receiving Wait Register (RFWTR)
Figure 23.6-13 Configuration of the Remote Frame Receiving Wait Register (RFWTR)
Address:
bit
CAN0: 00370DH
CAN1: 00390DH
CAN2: 003B0DH
CAN3: 003D0DH
CAN4: 003F0DH
Address:
bit
CAN0: 00370CH
CAN1: 00390CH
CAN2: 003B0CH
CAN3: 003D0CH
CAN4: 003F0CH
15
14
13
12
11
10
9
8
RFWT15 RFWT14 RFWT13 RFWT12 RFWT11 RFWT10 RFWT9 RFWT8
RFWTRn (upper)
Initial value
X X X X X X X XB
R/W R/W R/W R/W R/W R/W R/W R/W
7
6
5
4
3
2
1
0
RFWT7 RFWT6 RFWT5 RFWT4 RFWT3 RFWT2 RFWT1 RFWT0
R/W R/W R/W R/W R/W R/W R/W R/W
RFWTRn (lower)
Initial value
XXXXXXXXB
n = 0, 1, 2, 3, 4
[bit15 to bit0] RFWT15 to RFWT0:
"0": Transmission starts immediately
"1": Transmission starts after waiting until remote frame received (RRTRx of remote request receiving
register (RRTRR) becomes "1")
Notes:
• Transmission starts immediately if RRTRx is already "1" when a request for transmission is set.
• For remote frame transmission, do not set RFWTx to "1".
483
CHAPTER 23 CAN CONTROLLER
23.6.11
Transmission Cancel Register (TCANR)
When "1" is written to TCANx, this register cancels a pending request for transmission
to the message buffer (x).
At completion of cancellation, TREQx of the transmission request register (TREQR)
becomes "0". Writing "0" to TCANx is ignored.
This is a write only register and its read value is always "0".
■ Transmission Cancel Register (TCANR)
Figure 23.6-14 Configuration of the Transmission Cancel Register (TCANR)
Address:
bit 15
CAN0: 000075 H
CAN1: 000085 H
CAN2: 003575 H
CAN3: 003585 H
CAN4: 003595 H
Address:
bit
CAN0: 000074 H
CAN1: 000084 H
CAN2: 003574 H
CAN3: 003584 H
CAN4: 003594 H
14
13
11
10
9
8
TCAN15 TCAN14 TCAN13 TCAN12 TCAN11 TCAN10 TCAN9 TCAN8
W
W
W
W
W
W
W
W
7
6
5
4
3
2
1
0
TCAN7 TCAN6 TCAN5 TCAN4 TCAN3 TCAN2 TCAN1 TCAN0
W
W
W
[bit15 to bit0] TCAN15 to TCAN0:
484
12
W
W
W
W
W
TCANRn (upper)
Initial value
00000000B
TCANRn (lower)
Initial value
00000000B
n = 0, 1, 2, 3, 4
CHAPTER 23 CAN CONTROLLER
23.6.12
Transmission Complete Register (TCR)
At completion of transmission by the message buffer (x), the corresponding TCx
becomes "1".
If TIEx of the transmission complete interrupt enable register (TIER) is "1", an interrupt
occurs.
■ Transmission Complete Register (TCR)
Figure 23.6-15 Configuration of the Transmission Complete Register (TCR)
Address:
bit
CAN0: 000077 H
CAN1: 000087 H
CAN2: 003577 H
CAN3: 003587 H
CAN4: 003597 H
Address:
bit
CAN0: 000076 H
CAN1: 000086 H
CAN2: 003576 H
CAN3: 003586 H
CAN4: 003596 H
15
14
13
12
11
10
9
8
TC15 TC14 TC13 TC12 TC11 TC10 TC9 TC8
TCRn (upper)
Initial value
00000000B
R/W R/W R/W R/W R/W R/W R/W R/W
7
6
5
4
3
2
1
0
TC7 TC6 TC5 TC4 TC3 TC2 TC1 TC0
R/W R/W R/W R/W R/W R/W R/W R/W
TCRn (lower)
Initial value
00000000B
n = 0, 1, 2, 3, 4
[bit15 to bit0] TC15 to TC0:
● Conditions for TCx = 0
• Write "0" to TCx.
• Write "1" to TREQx of the transmission request register (TREQR).
After the completion of transmission, write "0" to TCx to set it to "0". Writing "1" to TCx is ignored.
"1" is read when a Read Modify Write (RMW) instruction is performed.
Note:
If setting to "1" by completion of the transmit operation and clearing to "0" by writing occur at the
same time, the bit is set to "1".
485
CHAPTER 23 CAN CONTROLLER
23.6.13
Transmission Interrupt Enable Register (TIER)
This register enables or disables the transmission interrupt by the message buffer (x).
The transmission interrupt is generated at transmission completion (when TCx of the
transmission complete register (TCR) is "1").
■ Transmission Interrupt Enable Register (TIER)
Figure 23.6-16 Configuration of the Transmission Interrupt Enable Register (TIER)
Address:
bit 15
CAN0: 00370F H
CAN1: 00390F H
CAN2: 003B0FH
CAN3: 003D0FH
CAN4: 003F0F H
Address:
bit
CAN0: 00370E H
CAN1: 00390E H
CAN2: 003B0EH
CAN3: 003D0EH
CAN4: 003F0E H
14
13
11
10
9
8
TIE15 TIE14 TIE13 TIE12 TIE11 TIE10 TIE9 TIE8
TIERn (upper)
Initial value
00000000B
R/W R/W R/W R/W R/W R/W R/W R/W
7
6
5
4
3
2
TIE7 TIE6 TIE5 TIE4 TIE3 TIE2
1
0
TIE1 TIE0
R/W R/W R/W R/W R/W R/W R/W R/W
[bit15 to bit0] TIER15 to TIER0:
"0": Transmission interrupt disabled.
"1": Transmission interrupt enabled.
486
12
TIERn (lower)
Initial value
00000000B
n = 0, 1, 2, 3, 4
CHAPTER 23 CAN CONTROLLER
23.6.14
Reception Complete Register (RCR)
At completion of storing received message in the message buffer (x), RCx becomes "1".
If RIEx of the reception complete interrupt enable register (RIER) is "1", an interrupt
occurs.
■ Reception Complete Register (RCR)
Figure 23.6-17 Configuration of the Reception Complete Register (RCR)
Address:
15
CAN0: 000079 H
CAN1: 000089 H
CAN2: 003579 H
CAN3: 003589 H
CAN4: 003599 H
Address:
bit
CAN0: 000078 H
CAN1: 000088 H
CAN2: 003578 H
CAN3: 003588 H
CAN4: 003598 H
14
13
12
11
10
9
8
RC15 RC14 RC13 RC12 RC11 RC10 RC9
RC8
RCRn (upper)
Initial value
00000000B
R/W R/W R/W R/W R/W R/W R/W R/W
7
RC7
6
5
4
3
2
1
0
RC6
RC5
RC4
RC3
RC2
RC1
RC0
R/W R/W R/W R/W R/W R/W R/W R/W
RCRn (lower)
Initial value
00000000B
n = 0, 1, 2, 3, 4
[bit15 to bit0] RC15 to RC0:
● Conditions for RCx = 0
Write "0" to RCx.
After completion of handling received message, write "0" to RCx to set it to "0". Writing "1" to RCx is
ignored.
"1" is read when a Read Modify Write (RMW) instruction is performed.
Note:
If setting to "1" by completion of the receive operation and clearing to "0" by writing occur at the
same time, the bit is set to "1".
487
CHAPTER 23 CAN CONTROLLER
23.6.15
Remote Request Receiving Register (RRTRR)
After a remote frame is stored in the message buffer (x), RRTRx becomes "1" (at the
same time as RCx setting to "1").
■ Remote Request Receiving Register (RRTRR)
Figure 23.6-18 Configuration of the Remote Request Receiving Register (RRTRR)
Address:
bit
CAN0: 00007B H
CAN1: 00008B H
CAN2: 00357B H
CAN3: 00358B H
CAN4: 00359B H
Address:
bit
CAN0: 00007A H
CAN1: 00008A H
CAN2: 00357A H
CAN3: 00358A H
CAN4: 00359A H
15
14
13
12
11
10
9
8
RRTR15 RRTR14 RRTR13 RRTR12 RRTR11 RRTR10 RRTR9 RRTR8
RRTRRn (upper)
Initial value
0 0 0 0 0 0 0 0B
R/W R/W R/W R/W R/W R/W R/W R/W
7
6
5
4
3
2
1
0
RRTR7 RRTR6 RRTR5 RRTR4 RRTR3 RRTR2 RRTR1 RRTR0
R/W R/W R/W R/W R/W R/W R/W R/W
RRTRRn (lower)
Initial value
0 0 0 0 0 0 0 0B
n = 0, 1, 2, 3, 4
[bit15 to bit0] RRTR15 to RRTR0:
● Conditions for RRTRx = 0
• Write "0" to RRTRx.
• After a received data frame is stored in the message buffer (x) (at the same time as RCx setting to "1").
• Transmission by the message buffer (x) is completed (TCx of the transmission complete register (TCR)
is "1").
Writing "1" to RRTRx is ignored.
"1" is read when a Read Modify Write (RMW) instruction is performed.
Note:
If setting to "1" by completion of the receive operation and clearing to "0" by writing occur at the
same time, the bit is set to "1".
488
CHAPTER 23 CAN CONTROLLER
23.6.16
Receive Overrun Register (ROVRR)
If RCx of the reception complete register (RCR) is "1" when completing storing of a
received message in the message buffer (x), ROVRx becomes "1", indicating that
reception has overrun.
■ Receive Overrun Register (ROVRR)
Figure 23.6-19 Configuration of the Receive Overrun Register (ROVRR)
Address:
bit 15
CAN0: 00007DH
CAN1: 00008DH
CAN2: 00357DH
CAN3: 00358D H
CAN4: 00359D H
Address:
bit
CAN0: 00007CH
CAN1: 00008CH
CAN2: 00357CH
CAN3: 00358C H
CAN4: 00359C H
14
13
12
11
10
9
8
ROVR15 ROVR14 ROVR13 ROVR12 ROVR11 ROVR10 ROVR9 ROVR8
ROVRRn (upper)
Initial value
0 0 0 0 0 0 0 0B
R/W R/W R/W R/W R/W R/W R/W R/W
7
6
5
4
3
2
1
0
ROVR7 ROVR6 ROVR5 ROVR4 ROVR3 ROVR2 ROVR1 ROVR0
R/W R/W R/W R/W R/W R/W R/W R/W
ROVRRn (lower)
Initial value
0 0 0 0 0 0 0 0B
n = 0, 1, 2, 3, 4
[bit15 to bit0] ROVR15 to ROVR0:
Writing "0" to ROVRx results in ROVRx = 0. Writing "1" to ROVRx is ignored. After checking that
reception has overrun, write "0" to ROVRx to set it to "0".
"1" is read when a Read Modify Write (RMW) instruction is performed.
Note:
If setting to "1" by completion of the receive operation and clearing to "0" by writing occur at the
same time, the bit is set to "1".
489
CHAPTER 23 CAN CONTROLLER
23.6.17
Reception Interrupt Enable Register (RIER)
Reception interrupt enable register (RIER) enables or disables the reception interrupt by
the message buffer (x).
The reception interrupt is generated at reception completion (when RCx of the reception
completion register (RCR) is "1").
■ Reception Interrupt Enable Register (RIER)
Figure 23.6-20 Configuration of the Reception Interrupt Enable Register (RIER)
Address:
bit 15
CAN0: 00007F H
CAN1: 0000BFH
CAN2: 00357F H
CAN3: 00358F H
CAN4: 00359F H
Address:
bit
CAN0: 00007E H
CAN1: 0000BEH
CAN2: 00357E H
CAN3: 00358E H
CAN4: 00359E H
14
13
11
10
9
8
RIE15 RIE14 RIE13 RIE12 RIE11 RIE10 RIE9 RIE8
RIERn (upper)
Initial value
00000000B
R/W R/W R/W R/W R/W R/W R/W R/W
7
6
5
4
3
2
1
0
RIE7 RIE6 RIE5 RIE4 RIE3 RIE2 RIE1 RIE0
R/W R/W R/W R/W R/W R/W R/W R/W
[bit15 to bit0] RIE15 to RIE0:
"0": Reception interrupt disabled.
"1": Reception interrupt enabled.
490
12
RIERn (lower)
Initial value
00000000B
n = 0, 1, 2, 3, 4
CHAPTER 23 CAN CONTROLLER
23.6.18
Acceptance Mask Select Register (AMSR)
This register selects masks (acceptance mask) for comparison between the received
message ID’s and the message buffer ID’s.
■ Acceptance Mask Select Register (AMSR)
Figure 23.6-21 Configuration of the Acceptance Mask Select Register (AMSR)
Address:
bit
CAN0: 003710 H
CAN1: 003910 H
CAN2: 003B10 H
CAN3: 003D10 H
CAN4: 003F10 H
Address:
bit
CAN0: 003712 H
CAN1: 003912 H
CAN2: 003B12 H
CAN3: 003D12 H
CAN4: 003F12 H
Address:
5
4
3
2
1
0
AMSRn Byte 0
Initial value
XXXXXXXXB
R/W R/W R/W R/W R/W R/W R/W R/W
14
13
12
11
10
9
8
AMS AMS AMS AMS AMS AMS AMS AMS
7.1 7.0 6.1 6.0 5.1 5.0 4.1 4.0
R/W R/W R/W R/W R/W R/W R/W R/W
7
6
5
4
3
2
1
0
AMS AMS AMS AMS AMS AMS AMS AMS
11.1 11.0 10.1 10.0 9.1 9.0 8.1 8.0
AMSRn Byte 1
Initial value
XXXXXXXXB
AMSRn Byte 2
Initial value
XXXXXXXXB
R/W R/W R/W R/W R/W R/W R/W R/W
bit 15
CAN0: 003713 H
CAN1: 003913 H
CAN2: 003B13 H
CAN3: 003D13 H
CAN4: 003F13 H
6
AMS AMS AMS AMS AMS AMS AMS AMS
3.1 3.0 2.1 2.0 1.1 1.0 0.1 0.0
bit 15
CAN0: 003711 H
CAN1: 003911 H
CAN2: 003B11 H
CAN3: 003D11 H
CAN4: 003F11 H
Address:
7
14
13
12
11
10
9
8
AMS AMS AMS AMS AMS AMS AMS AMS
15.1 15.0 14.1 14.0 13.1 13.0 12.1 12.0
R/W R/W R/W R/W R/W R/W R/W R/W
AMSRn Byte 3
Initial value
XXXXXXXXB
n = 0, 1, 2, 3, 4
491
CHAPTER 23 CAN CONTROLLER
Table 23.6-7 Selection of Acceptance Mask
AMSx.1
AMSx.0
Acceptance Mask
0
0
Full-bit comparison
0
1
Full-bit mask
1
0
Acceptance mask register 0 (AMR0)
1
1
Acceptance mask register 1 (AMR1)
Notes:
• AMSx.1 and AMSx.0 should be set when the message buffer (x) is invalid (BVALx of the message
buffer valid register (BVALR) is "0"). Setting when the buffer is valid (BVALx = 1) may cause
unnecessary received messages to be stored.
• To invalidate the message buffer (by setting the BVALR: BVAL bit to "0") while the CAN controller
is operating for CAN communication (the read value of the CSR: HALT bit is "0" and the CAN
controller is operating for CAN bus communication to enable transmission and reception), follow
the procedure in Section "23.16 Precautions when Using CAN Controller".
492
CHAPTER 23 CAN CONTROLLER
23.6.19
Acceptance Mask Registers 0 and 1 (AMR0 and AMR1)
There are two acceptance mask registers, AMR0 and AMR1, both of which are available
either in the standard frame format or extended frame format.
AM28 to AM18 (11 bits) are used for acceptance masks in the standard frame format and
AM28 to AM0 (29 bits) are used for acceptance masks in the extended format.
■ Acceptance Mask Registers 0 and 1 (AMR0 and AMR1)
Figure 23.6-22 Configuration of the Acceptance Mask Register 0 (AMR0)
Address:
bit 7
CAN0: 003714 H
CAN1: 003914 H
CAN2: 003B14 H
CAN3: 003D14 H
CAN4: 003F14 H
Address:
4
3
2
1
0
AMR0n Byte 0
Initial value
XXXXXXXXB
R/W R/W R/W R/W R/W R/W R/W R/W
bit 15
14
13
12
11
10
9
8
AM20 AM19 AM18 AM17 AM16 AM15 AM14 AM13
R/W R/W R/W R/W R/W R/W R/W R/W
bit 7
CAN0: 003716 H
CAN1: 003916 H
CAN2: 003B16 H
CAN3: 003D16 H
CAN4: 003F16 H
Address:
5
AM28 AM27 AM26 AM25 AM24 AM23 AM22 AM21
CAN0: 003715 H
CAN1: 003915 H
CAN2: 003B15 H
CAN3: 003D15 H
CAN4: 003F15 H
Address:
6
6
5
4
3
2
1
0
AM12 AM11 AM10 AM9 AM8 AM7 AM6 AM5
AMR0n Byte 1
Initial value
XXXXXXXXB
AMR0n Byte 2
Initial value
XXXXXXXXB
R/W R/W R/W R/W R/W R/W R/W R/W
bit 15
CAN0: 003717 H
CAN1: 003917 H
CAN2: 003B17 H
CAN3: 003D17 H
CAN4: 003F17 H
R/W
:
Readable and writable
X
-
:
:
Undefined value
Undefined
14
13
12
11
10
9
8
AM4 AM3 AM2 AM1 AM0
-
-
-
R/W R/W R/W R/W R/W
-
-
-
AMR0n Byte 3
Initial value
XXXXXXXX
B
n = 0, 1, 2, 3, 4
493
CHAPTER 23 CAN CONTROLLER
Figure 23.6-23 Configuration of the Acceptance Mask Register 1 (AMR1)
Address:
bit
CAN0: 003718 H
CAN1: 003918 H
CAN2: 003B18 H
CAN3: 003D18 H
CAN4: 003F18 H
Address:
bit 15
:
:
:
4
3
2
1
0
14
13
12
11
10
9
8
AM20 AM19 AM18 AM17 AM16 AM15 AM14 AM13
R/W R/W R/W R/W R/W R/W R/W R/W
bit
7
6
5
4
3
2
1
0
AM12 AM11 AM10 AM9 AM8 AM7 AM6 AM5
AMR1n Byte 0
Initial value
XXXXXXXXB
AMR1n Byte 1
Initial value
XXXXXXXXB
AMR1n Byte 2
Initial value
XXXXXXXXB
R/W R/W R/W R/W R/W R/W R/W R/W
bit 15
CAN0: 00371B H
CAN1: 00391B H
CAN2: 003B1BH
CAN3: 003D1BH
CAN4: 003F1B H
R/W
X
-
5
R/W R/W R/W R/W R/W R/W R/W R/W
CAN0: 00371A H
CAN1: 00391A H
CAN2: 003B1AH
CAN3: 003D1AH
CAN4: 003F1A H
Address:
6
AM28 AM27 AM26 AM25 AM24 AM23 AM22 AM21
CAN0: 003719 H
CAN1: 003919 H
CAN2: 003B19 H
CAN3: 003D19 H
CAN4: 003F19 H
Address:
7
14
13
12
11
10
9
8
AM4 AM3 AM2 AM1 AM0
-
-
-
R/W R/W R/W R/W R/W
-
-
-
AMR1n Byte 3
Initial value
X X X X X X X XB
n = 0, 1, 2, 3, 4
Readable and writable
Undefined value
Undefined
● 0: Compare
Compare the bit of the acceptance code (ID register IDRx for comparing with the received message ID)
corresponding to this bit with the bit of the received message ID. If there is no match, no message is
received.
● 1: Mask
Mask the bit of the acceptance code ID register (IDRx) corresponding to this bit. No comparison is made
with the bit of the received message ID.
Notes:
• AMR0 and AMR1 should be set when all the message buffers (x) selecting AMR0 and AMR1 are
invalid (BVALx of the message buffer valid register (BVALR) is "0"). Setting when the buffers are
valid (BVALx = 1) may cause unnecessary received messages to be stored.
• To invalidate the message buffer (by setting the BVALR: BVAL bit to "0") while the CAN controller
is operating for CAN communication (the read value of the CSR: HALT bit is "0" and the CAN
controller is operating for CAN bus communication to enable transmission and reception), follow
the procedure in Section "23.16 Precautions when Using CAN Controller".
494
CHAPTER 23 CAN CONTROLLER
23.6.20
Message Buffers
There are 16 message buffers. Message buffer x (x = 0 to 15) consists of an ID register
(IDRx), DLC register (DLCRx), and data register (DTRx).
■ Message Buffers
● The message buffer (x) is used both for transmission and reception.
● The lower-numbered message buffers are assigned higher priority.
• At transmission, when a request for transmission is made to more than one message buffer, transmission
is performed, starting with the lowest-numbered message buffer (See Section "23.7 Transmission of
CAN Controller").
• At reception, when the received message ID passes through the acceptance filter (mechanism for
comparing the acceptance-masked ID of received message and message buffer) of more than one
message buffer, the received message is stored in the lowest-numbered message buffer (See Section
"23.8 Reception of CAN Controller").
● When the same acceptance filter is set in more than one message buffer, the message buffers can be
used as a multi-level message buffer. This provides allowance for receiving time.
(See Section "23.12 Procedure for Reception by Message Buffer (x)").
Notes:
• A write operation to message buffers and general-purpose RAM areas should be performed in
words to even addresses only. A write operation in bytes causes undefined data to be written to
the upper byte at writing to the lower byte. Writing to the upper byte is ignored.
• When the BVALx bit of the message buffer valid register (BVALR) is "0" (Invalid), the message
buffers x (IDRx, DLCRx, and DTRx) can be used as general-purpose RAM.
During the receive/transmit operation of the CAN controller, the CAN Controller write/read to/from
the message buffers. If the CPU tries to write/read to/from the message buffers in this period, the
CPU has to wait a maximum time of 64 machine cycles.
This is also true for the general-purpose RAM.
495
CHAPTER 23 CAN CONTROLLER
23.6.21
ID Register x (x = 0 to 15) (IDRx)
ID Register x (x = 0 to 15) (IDRx) is the ID register for message buffer (x).
■ ID Register x (x = 0 to 15) (IDRx)
Figure 23.6-24 Configuration of the ID Registers (IDRx)
Address:
bit 7
CAN0: 003620 H + 4 × x
CAN1: 003820 H + 4 × x
CAN2: 003A20 H + 4 × x
CAN3: 003C20 H + 4 × x
CAN4: 003E20 H + 4 × x
Address:
Address:
Address:
14
13
12
3
2
1
0
11
10
9
8
ID20 ID19 ID18 ID17 ID16 ID15 ID14 ID13
R/W R/W R/W R/W R/W R/W R/W R/W
6
5
4
ID12 ID11 ID10 ID9
IDRxn Byte 0
Initial value
XXXXXXXXB
3
2
1
ID8 ID7 ID6
IDRxn Byte 1
Initial value
XXXXXXXXB
0
IDRxn Byte 2
ID5
Initial value
XXXXXXXXB
R/W R/W R/W R/W R/W R/W R/W R/W
bit 15
CAN0: 003623 H + 4 × x
CAN1: 003823 H + 4 × x
CAN2: 003A23 H + 4 × x
CAN3: 003C23 H + 4 × x
CAN4: 003E23 H + 4 × x
496
4
R/W R/W R/W R/W R/W R/W R/W R/W
bit 7
CAN0: 003622 H + 4 × x
CAN1: 003822 H + 4 × x
CAN2: 003A22 H + 4 × x
CAN3: 003C22 H + 4 × x
CAN4: 003E22 H + 4 × x
5
ID28 ID27 ID26 ID25 ID24 ID23 ID22 ID21
bit 15
CAN0: 003621 H + 4 × x
CAN1: 003821 H + 4 × x
CAN2: 003A21 H + 4 × x
CAN3: 003C21 H + 4 × x
CAN4: 003E21 H + 4 × x
6
14
13
12
11
10
9
8
IDRxn Byte 3
ID4 ID3
ID2
ID1
ID0
-
-
-
R/W R/W R/W R/W R/W
-
-
-
Initial value
XXXXX---
B
x = 0 to 15
n = 0, 1, 2, 3, 4
CHAPTER 23 CAN CONTROLLER
When using the message buffer (x) in the standard frame format (IDEx of the IDE register (IDER) = 0), use
11 bits of ID28 to ID18. When using the buffer in the extended frame format (IDEx = 1), use 29 bits of
ID28 to ID0.
ID28 to ID0 have the following functions:
• Set acceptance code (ID for comparing with the received message ID).
• Set transmitted message ID.
Note:
In the standard frame format, setting 1s to all bits of ID28 to ID22 is prohibited.
• Store the received message ID.
Notes:
• All received message ID bits are stored (even if bits are masked). In the standard frame format,
ID17 to ID0 stores image of old message left in the receive shift register.
• A write operation to this register should be performed in words. A write operation in bytes causes
undefined data to be written to the upper byte at writing to the lower byte. Writing to the upper
byte is ignored.
This register should be set when the message buffer (x) is invalid (BVALx of the message buffer
valid register (BVALR) is "0"). Setting when the buffer is valid (BVALx = 1) may cause
unnecessary received messages to be stored.
To invalidate the message buffer (by setting the BVALR: BVAL bit to "0") while the CAN controller
is operating for CAN communication (the read value of the CSR: HALT bit is "0" and the CAN
controller is operating for CAN bus communication to enable transmission and reception), follow
the procedure in Section "23.16 Precautions when Using CAN Controller".
497
CHAPTER 23 CAN CONTROLLER
23.6.22
DLC Register x (x = 0 to 15) (DLCRx)
DLC Register x (x = 0 to 15) (DLCRx) is the DLC register for message buffer x.
■ DLC Register x (x = 0 to 15) (DLCRx)
Figure 23.6-25 Configuration of the DLC Registers (DLCRx)
Address:
bit 7
CAN0: 003660 H + 2 × x
CAN1: 003860 H + 2 × x
CAN2: 003A60 H + 2 × x
CAN3: 003C60 H + 2 × x
CAN4: 003E60 H + 2 × x
6
5
4
3
2
1
0
-
-
-
-
DLC3 DLC2 DLC1 DLC0
-
-
-
- R/W R/W R/W R/W
DLCRnx (lower)
Initial value
----XXXXB
x = 0 to 15
n = 0, 1, 2, 3, 4
[bit15 to bit8] DLC3 to DLC0: DLC register x (x=0 to 15) (DLCRx)
● Transmission
• Set the data length (byte count) of a transmitted message when a data frame is transmitted (TRTRx of
the transmitting RTR register (TRTRR) is "0").
• Set the data length (byte count) of a requested message when a remote frame is transmitted (TRTRx =
1).
Note:
Setting other than 0000B to 1000B (0 to 8 bytes) is prohibited.
● Reception
• Store the data length (byte count) of a received message when a data frame is received (RRTRx of the
remote frame request receiving register (RRTRR) is "0").
• Store the data length (byte count) of a requested message when a remote frame is received (RRTRx =
1).
Note:
A write operation to this register should be performed in words. A write operation in bytes causes
undefined data to be written to the upper byte at writing to the lower byte. Writing to the upper byte is
ignored.
498
CHAPTER 23 CAN CONTROLLER
23.6.23
Data Register x (x = 0 to 15) (DTRx)
Data register x (x = 0 to 15) (DTRx) is the data register for message buffer (x).
This register is used only in transmitting and receiving a data frame but not in
transmitting and receiving a remote frame.
■ Data Register x (x = 0 to 15) (DTRx)
Figure 23.6-26 Configuration of the Data Registers (DTRx)
Address:
bit
Address:
CAN0: 003686 H + 8 × x
CAN1: 003886 H + 8 × x
CAN2: 003A86 H + 8 × x
CAN3: 003C86 H + 8 × x
CAN4: 003E86 H + 8 × x
Address:
CAN0: 003687 H + 8 × x
CAN1: 003887 H + 8 × x
CAN2: 003A87 H + 8 × x
CAN3: 003C87 H + 8 × x
CAN4: 003E87 H + 8 × x
2
1
0
D7
D6
D5
D4
D3
D2
D1
D0
12
11
10
9
8
D7
D6
D5
D4
D3
D2
D1
D0
R/W R/W R/W R/W R/W R/W R/W R/W
bit
Initial value
XXXXXXXXB
7
6
5
4
3
2
1
0
D7
D6
D5
D4
D3
D2
D1
D0
DTRxn Byte 1
Initial value
XXXXXXXXB
DTRxn Byte 2
Initial value
XXXXXXXXB
R/W R/W R/W R/W R/W R/W R/W R/W
bit 15
14
13
12
11
10
9
8
D7
D6
D5
D4
D3
D2
D1
D0
DTRxn Byte 3
R/W R/W R/W R/W R/W R/W R/W R/W
bit
7
6
5
4
3
2
1
0
D7
D6
D5
D4
D3
D2
D1
D0
Initial value
XXXXXXXXB
DTRxn Byte 4
Initial value
XXXXXXXXB
R/W R/W R/W R/W R/W R/W R/W R/W
bit 15
14
13
12
11
10
9
8
D7
D6
D5
D4
D3
D2
D1
D0
DTRxn Byte 5
CAN0: 003685 H + 8 × x
CAN1: 003885 H + 8 × x
CAN2: 003A85 H + 8 × x
CAN3: 003C85 H + 8 × x
CAN4: 003E85 H + 8 × x
Address:
3
13
CAN0: 003684 H + 8 × x
CAN1: 003884 H + 8 × x
CAN2: 003A84 H + 8 × x
CAN3: 003C84 H + 8 × x
CAN4: 003E84 H + 8 × x
Address:
4
14
CAN0: 003683 H + 8 × x
CAN1: 003883 H + 8 × x
CAN2: 003A83 H + 8 × x
CAN3: 003C83 H + 8 × x
CAN4: 003E83 H + 8 × x
Address:
5
bit 15
CAN0: 003682 H + 8 × x
CAN1: 003882 H + 8 × x
CAN2: 003A82 H + 8 × x
CAN3: 003C82 H + 8 × x
CAN4: 003E82 H + 8 × x
Address:
6
R/W R/W R/W R/W R/W R/W R/W R/W
CAN0: 003681 H + 8 × x
CAN1: 003881 H + 8 × x
CAN2: 003A81 H + 8 × x
CAN3: 003C81 H + 8 × x
CAN4: 003E81 H + 8 × x
Address:
7
DTRxn Byte 0
CAN0: 003680 H + 8 × x
CAN1: 003880 H + 8 × x
CAN2: 003A80 H + 8 × x
CAN3: 003C80 H + 8 × x
CAN4: 003E80 H + 8 × x
R/W R/W R/W R/W R/W R/W R/W R/W
bit
7
6
5
4
3
2
1
0
D7
D6
D5
D4
D3
D2
D1
D0
Initial value
XXXXXXXXB
DTRxn Byte 6
Initial value
XXXXXXXXB
R/W R/W R/W R/W R/W R/W R/W R/W
bit 15
14
13
12
11
10
9
8
D7
D6
D5
D4
D3
D2
D1
D0
DTRxn Byte 7
R/W R/W R/W R/W R/W R/W R/W R/W
Initial value
XXXXXXXXB
x = 0, 1, ... , 15
n = 0, 1, 2, 3, 4
499
CHAPTER 23 CAN CONTROLLER
● Sets transmitted message data (any of 0 to 8 bytes).
Data is transmitted in the order of BYTE0, BYTE1, ..., BYTE7, starting with the MSB first.
● Stores received message data.
Data is stored in the order of BYTE0, BYTE1, ..., BYTE7, starting with the MSB first.
Even if the received message data is less than 8 bytes, the remaining bytes of the data register (DTRx), to
which data are stored, are undefined.
Note:
A write operation to this register should be performed in words. A write operation in bytes causes
undefined data to be written to the upper byte at writing to the lower byte. Writing to the upper byte is
ignored.
500
CHAPTER 23 CAN CONTROLLER
23.7
Transmission of CAN Controller
When "1" is written to TREQx of the transmission request register (TREQR),
transmission by the message buffer (x) starts. At this time, TREQx becomes "1" and
TCx of the transmission complete register (TCR) becomes "0".
■ Starting Transmission of the CAN Controller
If RFWTx of the remote frame receiving wait register (RFWTR) is "0", transmission starts immediately. If
RFWTx is "1", transmission starts after waiting until a remote frame is received (RRTRx of the remote
request receiving register (RRTRR) becomes "1").
If a request for transmission is made to more than one message buffer (more than one TREQx is "1"),
transmission is performed, starting with the lowest-numbered message buffer.
Message transmission to the CAN bus (by the transmit output pin TX) starts when the bus is idle.
If TRTRx of the transmission RTR register (TRTRR) is "0", a data frame is transmitted. If TRTRx is "1", a
remote frame is transmitted.
If the message buffer competes with other CAN controllers on the CAN bus for transmission and
arbitration fails, or if an error occurs during transmission, the message buffer waits until the bus is idle and
repeats retransmission until it is successful.
■ Canceling a Transmission Request from the CAN Controller
● Canceling by transmission cancel register (TCANR)
A transmission request for message buffer (x) having not executed transmission during transmission
pending can be canceled by writing "1" to TCANx of the transmission cancel register (TCANR). At
completion of cancellation, TREQx becomes "0".
● Canceling by storing received message
The message buffer (x) having not executed transmission despite transmission request also performs
reception.
If the message buffer (x) has not executed transmission despite a request for transmission of a data frame
(TRTRx = 0 or TREQx = 1), the transmission request is canceled after storing received data frames passing
through the acceptance filter (TREQx = 0).
Note:
A transmission request is not canceled by storing remote frames (TREQx = 1 remains unchanged).
If the message buffer (x) has not executed transmission despite a request for transmission of a remote frame
(TRTRx = 1 or TREQx = 1), the transmission request is canceled after storing received remote frames
passing through the acceptance filter (TREQx = 0).
501
CHAPTER 23 CAN CONTROLLER
Note:
The transmission request is canceled by storing either data frames or remote frames.
■ Completing Transmission of the CAN Controller
When transmission is successful, RRTRx becomes "0", TREQx becomes "0", and TCx of the transmission
complete register (TCR) becomes "1".
If the transmission complete interrupt is enabled (TIEx of the transmission complete interrupt enable
register (TIER) is "1"), an interrupt occurs.
502
CHAPTER 23 CAN CONTROLLER
■ Transmission Flowchart of the CAN Controller
Figure 23.7-1 Transmission Flowchart of the CAN Controller
Transmission request
(TREQx := 1)
TCx := 0
0
TREQx?
1
0
RFWTx?
1
0
RRTRx?
1
If there are any other message buffers
meeting the above conditions, select
the lowest-numbered message buffer.
NO
Is the bus idle?
YES
0
1
TRTRx?
A data frame is transmitted.
A remote frame is transmitted.
NO
Is transmission
successful?
YES
TCANx?
1
RRTRx : = 0
TREQx := 0
TCx
:= 1
TREQx := 0
1
TIEx ?
0
0
A transmission complete
interrupt occurs.
End of transmission
503
CHAPTER 23 CAN CONTROLLER
23.8
Reception of CAN Controller
Reception starts when the start of data frame or remote frame (SOF) is detected on the
CAN bus.
■ Acceptance Filtering
The received message in the standard frame format is compared with the message buffer (x) set in the
standard frame format (IDEx of the IDE register (IDER) is "0"). The received message in the extended
frame format is compared with the message buffer (x) set (IDEx is "1") in the extended frame format.
If all the bits set to Compare by the acceptance mask agree after comparison between the received message
ID and acceptance code (ID register (IDRx) for comparing with the received message ID), the received
message passes to the acceptance filter of the message buffer (x).
■ Storing Received Message
When the receive operation is successful, received messages are stored in a message buffer x including IDs
passed through the acceptance filter.
When receiving data frames, received messages are stored in the ID register (IDRx), DLC register
(DLCRx), and data register (DTRx).
Even if received message data is less than 8 bytes, some data is stored in the remaining bytes of the DTRx
and its value is undefined.
When receiving remote frames, received messages are stored only in the IDRx and DLCRx, and the DTRx
remains unchanged.
If there is more than one message buffer including IDs passed through the acceptance filter, the message
buffer x in which received messages are to be stored is determined according to the following rules.
• The order of priority of the message buffer x (x = 0 to 15) rises as its number lower; in other words,
message buffer 0 is given the highest and the message buffer 15 is given the lowest priority.
• Basically, message buffers with the RCx bit of "0" in the receive completion register (RCR) are
preferred in storing received messages.
• If the bits of the acceptance mask select register (AMSR) are set to All Bits Compare (for message
buffers with the AMSx.1 and AMSx.0 bits set to "00B"), received messages are stored irrespective of the
value of the RCx bit of the RCR.
• If there are message buffers with the RCx bit of the RCR set to "0", or with the bits of the AMSR set to
All Bits Compare, received messages are stored in the lowest-number (highest-priority) message buffer
x.
• If there are no message buffers above-mentioned, received messages are stored in a lower-number
message buffer x.
• Message buffers should be arranged in ascending numeric order. The lowest message buffers should be
with All Bits Compare, then AMR0 or AMR1 masks. And The highest message buffers should be with
All Bits Mask.
504
CHAPTER 23 CAN CONTROLLER
Figure 23.8-1 shows the flowchart determining message buffer (x) where received messages stored. It is
recommended that message buffers be arranged in the following order: message buffers in which each
AMSR bit is set to All Bits Compare, message buffers using AMR0 or AMR1, and message buffers in
which each AMSR bit is set to All Bits Mask.
Figure 23.8-1 Flowchart Determining Message Buffer (x) where Received Messages Stored
Start
Are message buffers with RCx set to "0"
or with AMSx.1 and AMSx.0 set to "00B"
found?
NO
YES
Select the lowest-numbered
message buffer.
Select the lowest-numbered
message buffer.
End
■ Receive Overrun
When a message is stored in the message buffer with the corresponding RCx being already set to "1", it will
results in receive overrun. In this case, the corresponding ROVRx bit in the receive overrun register
ROVRR is set to "1".
■ Processing for Reception of Data Frame and Remote Frame
● Processing for reception of data frame
RRTRx of the remote request receiving register (RRTRR) becomes "0".
TREQx of the transmission request register (TREQR) becomes "0" (immediately before storing the
received message). A transmission request for message buffer (x) having not executed transmission will be
canceled.
Note:
A request for transmission of either a data frame or remote frame is canceled.
● Processing for reception of remote frame
RRTRx becomes "1".
If TRTRx of the transmitting RTR register (TRTRR) is "1", TREQx becomes "0". As a result, the request
for transmitting remote frame to message buffer having not executed transmission will be canceled.
Note:
A request for data frame transmission is not canceled.
For cancellation of a transmission request, see Section "23.7 Transmission of CAN Controller".
505
CHAPTER 23 CAN CONTROLLER
■ Completing Reception
RCx of the reception complete register (RCR) becomes "1" after storing the received message.
If a reception interrupt is enabled (RIEx of the reception interrupt enable register (RIER) is "1"), an
interrupt occurs.
Note:
This CAN controller will not receive any messages transmitted by itself.
506
CHAPTER 23 CAN CONTROLLER
23.9
Reception Flowchart of CAN Controller
Figure 23.9-1 shows a reception flowchart of the CAN controller.
■ Reception Flowchart of the CAN Controller
Figure 23.9-1 Reception Flowchart of the CAN Controller
Detection of start of data frame
or remote frame (SOF)
NO
Is any message buffer (x) passing to
the acceptance filter found?
YES
NO
Is reception
successful?
YES
Determine message buffer (x) where received messages to be stored.
Store the received message
in the message buffer (x).
1
RCx?
0
Data frame
ROVRx := 1
Remote frame
Received message?
RRTRx := 0
RRTRx := 1
1
TRTRx?
0
TREQx := 0
RCx := 1
RIEx ?
0
1
A reception interrupt
occurs.
End of reception
507
CHAPTER 23 CAN CONTROLLER
23.10
How to Use the CAN Controller
The following settings are required to use the CAN controller:
• Bit timing
• Frame format
• ID
• Acceptance filter
• Low-power consumption mode
■ Setting Bit Timing
The bit timing register (BTR) should be set during bus operation stop (when the bus operation stop bit
(HALT) of the control status register (CSR) is" 1").
After the setting completion, write "0" to HALT to cancel bus operation stop.
■ Setting Frame Format
Set the frame format used by the message buffer (x). When using the standard frame format, set IDEx of
the IDE register (IDER) to "0". When using the extended frame format, set IDEx to "1".
This setting should be made when the message buffer (x) is invalid (BVALx of the message buffer valid
register (BVALR) is "0"). Setting when the buffer is valid (BVALx = 1) may cause unnecessary received
messages to be stored.
■ Setting ID
Set the message buffer (x) ID to ID28 to ID0 of ID register (IDRx). The message buffer (x) ID need not be
set to ID17 to ID0 in the standard frame format. The message buffer (x) ID is used as a transmission
message at transmission and is used as an acceptance code at reception.
This setting should be made when the message buffer (x) is invalid (BVALx of the message buffer valid
register (BVALR) is "0"). Setting when the buffer is valid (BVALx = 1) may cause unnecessary received
messages to be stored.
■ Setting Acceptance Filter
The acceptance filter of the message buffer (x) is set by an acceptance code and acceptance mask set. It
should be set when the acceptance message buffer (x) is invalid (BVALx of the message buffer enable
register (BVALR) is "0"). Setting when the buffer is valid (BVALx = 1) may cause unnecessary received
messages to be stored.
Set the acceptance mask used in each message buffer (x) by the acceptance mask select register (AMSR).
The acceptance mask registers (AMR0 and AMR1) should also be set if used (For the setting details, see
Sections "23.6.18 Acceptance Mask Select Register (AMSR)" and "23.6.19 Acceptance Mask Registers 0
and 1 (AMR0 and AMR1)").
The acceptance mask should be set so that a transmission request may not be canceled when unnecessary
received messages are stored. For example, it should be set to a full-bit comparison if only one specific ID
is used for the transmission.
508
CHAPTER 23 CAN CONTROLLER
■ Setting Low-power Consumption Mode
To set the F2MC-16LX in a low-power consumption mode (Stop and Time-base timer), write "1" to the bus
operation stop bit (HALT) of the control status register (CSR), and then check that the bus operation has
stopped (HALT = 1).
509
CHAPTER 23 CAN CONTROLLER
23.11
Procedure for Transmission by Message Buffer (x)
After setting the bit timing, frame format, ID, and acceptance filter, set BVALx to "1" to
activate the message buffer (x).
■ Procedure for Transmission by Message Buffer (x)
● Setting transmit data length code
Set the transmit data length code (byte count) to DLC3 to DLC0 of the DLC register (DLCRx).
For data frame transmission (when TRTRx of the transmission RTR register (TRTRR) is "0"), set the data
length of the transmitted message.
For remote frame transmission (when TRTRx = 1), set the data length (byte count) of the requested
message.
Note:
Setting other than" 0000B" to "1000B" (0 to 8 bytes) is prohibited.
● Setting transmit data (only for transmission of data frame)
For data frame transmission (when TRTRx of the transmission register (TRTRR) is "0"), set data as the
count of byte transmitted in the data register (DTRx).
Note:
Transmit data should be rewritten while the TREQx bit of the transmission request register (TREQR)
set to "0". There is no need for setting the BVALx bit of the message buffer valid register (BVALR) to
"0". Setting the BVALx bit to "0" may cause incoming remote frame to be lost.
● Setting transmission RTR register
For data frame transmission, set TRTRx of the transmission RTR register (TRTRR) to "0".
For remote frame transmission, set TRTRx to "1".
510
CHAPTER 23 CAN CONTROLLER
● Setting conditions for starting transmission (only for transmission of data frame)
Set RFWTx of the remote frame receiving wait register (RFWTR) to "0" to start transmission immediately
after a request for data frame transmission is set (TREQx of the transmission request register (TREQR) is
"1" and TRTRx of the transmission RTR register (TRTRR) is "0").
Set RFWTx to "1" to start transmission after waiting until a remote frame is received (RRTRx of the
remote request receiving register (RRTRR) becomes "1") after a request for data frame transmission is set
(TREQx = 1 and TRTRx = 0).
Note:
Remote frame transmission can not be made, if RFWTx is set to "1".
● Setting transmission complete interrupt
When generating a transmission complete interrupt, set TIEx of the transmission complete interrupt enable
register (TIER) to "1".
When not generating a transmission complete interrupt, set TIEx to "0".
● Setting transmission request
For a transmission request, set TREQx of the transmission request register (TREQR) to "1".
● Canceling transmission request
When canceling a pending request for transmission to the message buffer (x), write "1" to TCANx of the
transmission cancel register (TCANR).
Check TREQx. For TREQx = 0, transmission cancellation is terminated or transmission is completed.
Check TCx of the transmission complete register (TCR). For TCx = 0, transmission cancellation is
terminated. For TCx = 1, transmission is completed.
● Processing for completion of transmission
If transmission is successful, TCx of the transmission complete register (TCR) becomes "1".
If the transmission complete interrupt is enabled (TIEx of the transmission complete interrupt enable
register (TIER) is "1"), an interrupt occurs.
After checking the transmission completion, write "0" to TCx to set it to "0". This cancels the transmission
complete interrupt.
In the following cases, the pending transmission request is canceled by receiving and storing a message.
• Request for data frame transmission by reception of data frame
• Request for remote frame transmission by reception of data frame
• Request for remote frame transmission by reception of remote frame
Request for data frame transmission is not canceled by receiving and storing a remote frame. ID and DLC,
however, are changed by the ID and DLC of the received remote frame. Note that the ID and DLC of data
frame to be transmitted become the value of received remote frame.
511
CHAPTER 23 CAN CONTROLLER
23.12
Procedure for Reception by Message Buffer (x)
After setting the bit timing, frame format, ID, and acceptance filter, make the settings
described below.
■ Procedure for Reception by Message Buffer (x)
● Setting reception interrupt
To enable reception interrupt, set RIEx of the reception interrupt enable register (RIER) to "1".
To disable reception interrupt, set RIEx to "0".
● Starting reception
When starting reception after setting, set BVALx of the message buffer valid register (BVALR) to "1" to
make the message buffer (x) valid.
● Processing for reception completion
If reception is successful after passing to the acceptance filter, the received message is stored in the
message buffer (x) and RCx of the reception complete register (RCR) becomes "1". For data frame
reception, RRTRx of the remote request receiving register (RRTRR) becomes "0". For remote frame
reception, RRTRx becomes "1".
If a reception interrupt is enabled (RIEx of the reception interrupt enable register (RIER) is "1"), an
interrupt occurs.
After checking the reception completion (RCx = 1), process the received message.
After completion of processing the received message, check ROVRx of the reception overrun register
(ROVRR).
If ROVRx = 0, the processed received message is valid. Write "0" to RCRx to set it to "0" (the reception
complete interrupt is also canceled) to terminate reception.
If ROVRx = 1, a reception overrun occurred and the next message may have overwritten the processed
message. In this case, received messages should be processed again after setting the ROVRx bit to "0" by
writing "0" to it.
Figure 23.12-1 shows an example of receive interrupt handling.
512
CHAPTER 23 CAN CONTROLLER
Figure 23.12-1 Example of Receive Interrupt Handling
Interrupt with RCx = 1
Read received messages.
A: = ROVRx
ROVRx := 0
A = 0?
NO
YES
RCx := 0
End
513
CHAPTER 23 CAN CONTROLLER
23.13
Setting Configuration of Multi-level Message Buffer
If the receptions are performed frequently, or if several different ID’s of messages are
received, in other words, if there is insufficient time for handling messages, more than
one message buffer can be combined into a multi-level message buffer to provide
allowance for processing time of the received message by CPU.
■ Setting Configuration of Multi-level Message Buffer
To provide a multi-level message buffer, the same acceptance filter must be set in the combined message
buffers.
If the bits of the acceptance mask select register (AMSR) are set to All Bits Compare ((AMSx.1, AMSx.0)
= (0, 0)), multi-level message configuration of message buffers is not allowed. This is because All Bits
Compare causes received messages to be stored irrespective of the value of the RCx bit of the receive
completion register (RCR), so received messages are always stored in lower-numbered (lower-priority)
message buffers even if All Bits Compare and identical acceptance code (ID register (IDRx)) are specified
for more than one message buffer. Therefore, All Bits Compare and identical acceptance code should not
be specified for more than one message buffer.
Figure 23.13-1 shows operational examples of multi-level message buffers.
514
CHAPTER 23 CAN CONTROLLER
Figure 23.13-1 Examples of Operation of Multi-level Message Buffer
Initialization
AMS15, AMS14, AMS13
AMSR 10 10 10
Select AMR0.
.. .
AM28 to AM18
AMS0
ID28 to ID18
Message buffer 13
Message buffer 14
Message buffer 15
0000 1111 111
0101 0000 000
0101 0000 000
0101 0000 000
RC15, RC14, RC13
IDE
.. .
0
.. .
RCR 0
0
0
.. .
0
.. .
ROVRR 0
0
0
.. .
0
.. .
ROVR15, ROVR14, ROVR13
Mask
Message receiving
"The received message is stored in message buffer 13.
IDE
ID28 to ID18
Message receiving
0101 1111 000
0
.. .
Message buffer 13
0101 1111 000
0
.. .
RCR 0
0
1
.. .
ROVRR 0
0
0
.. .
Message buffer 14
0101 0000 000
0
.. .
Message buffer 15
0101 0000 000
0
.. .
Message receiving
"The received message is stored in message buffer 14.
Message receiving
0101 1111 001
0
.. .
Message buffer 13
0101 1111 000
0
.. .
RCR 0
1
1
.. .
0
.. .
ROVRR 0
0
0
.. .
0
.. .
Message buffer 14
Message buffer 15
Message receiving
0101 1111 001
0101 0000 000
"The received message is stored in message buffer 15.
Message receiving
0101 1111 010
0
.. .
Message buffer 13
0101 1111 000
0
.. .
RCR 1
1
1
.. .
Message buffer 14
0101 1111 001
0
.. .
ROVRR 0
0
0
.. .
Message buffer 15
0101 1111 010
0
.. .
Message receiving "An overrun occurs (ROVR13 = 1) and the received message is stored in message buffer 13.
Message receiving
0101 1111 011
0
.. .
Message buffer 13
0101 1111 011
0
.. .
RCR 1
1
1
.. .
Message buffer 14
0101 1111 001
0
.. .
ROVRR 0
0
1
.. .
Message buffer 15
0101 1111 010
0
.. .
Note:
Four messages are received with the same acceptance filter set in message buffers 13, 14 and 15.
515
CHAPTER 23 CAN CONTROLLER
23.14
Setting the redirection of CAN1 and CAN3 RX/TX pin
CAN1 and CAN3 can be changed the redirection CAN1 RX/TX pin (RX1/TX1) to RX0/TX0
pin and CAN3 RX/TX pin (RX3/TX3) to RX2/TX2 pin by the CANSWR register.
■ CAN2 RX/TX Pin Switching Register (CANSWR)
Figure 23.14-1 CAN2 RX/TX Pin Switching Register (CANSWR)
Address:
bit 15 14
CAN0: 00356F H
R/W
X
-
:
:
:
13
12
11
10
9
8
CANSWR
-
-
-
-
RXS TXS RXS TXS
23 23 01 01
-
-
-
-
R/W R/W R/W R/W
Initial value
XXXX0000
B
Readable and writable
Undefined value
Undefined
■ CAN Switch Register (CANSWR) Contents
Table 23.14-1 Function of Each Bit of the CAN Switch Register
Bit name
bit15 to
bit12
Undefined
Function
−
bit11
RXS23:
Reception switch
2/3
If "0" is written to this bit, input of CAN3 is inputted from RX3 pin.
If "1" is written to this bit, input of CAN3 is inputted from RX2 pin.
bit10
TXS23:
Transmission
switch 2/3
If "0" is written to this bit, output of CAN3 is outputted from TX3 pin.
If "1" is written to this bit, output of CAN3 is outputted from TX2 pin.
bit9
RXS01:
Reception switch
0/1
If "0" is written to this bit, input of CAN1 is inputted from RX1 pin.
If "1" is written to this bit, input of CAN1 is inputted from RX0 pin.
bit8
TXS01:
Transmission
switch 0/1
If "0" is written to this bit, output of CAN1 is outputted from TX1 pin.
If "1" is written to this bit, output of CAN1 is outputted from TX0 pin.
CAN1 can be changed the redirection CAN1 RX/TX pin, and shared with CAN0, as shown in Figure
23.14-2. Therefore this feature allows the saving of one external CAN transceiver. This function is selected
by CANSWR register. The same function is provided for CAN2 and CAN3.
516
CHAPTER 23 CAN CONTROLLER
Figure 23.14-2 Redirection of CAN1 and CAN3 RX/TX
CAN0
TX
TX0
switched by TXS01
of CANSWR
RX0
RX
CAN0
switched by RXS01
of CANSWR
VCC
CAN1
TX
TX1
RX1
RX
CAN1
CAN2
TX
TX2
RX2
RX
CAN2
RX
CAN3
switched by TXS23
of CANSWR
switched by RXS23
of CANSWR
VCC
CAN3
TX
TX3
RX3
517
CHAPTER 23 CAN CONTROLLER
23.15
Setting the CAN Direct Mode Register
The MB90390 series provides a clock modulator for the system clock. Since the CAN
controller is not able to operate with a modulated clock, the unmodulated clock is
provided to the CAN controller independently from the clock modulator settings.
■ CAN Direct Mode Register (CDMR)
Figure 23.15-1 Configuration of the CAN Direct Mode Register (CDMR)
Address:
bit
CAN0: 00356E H
R/W
X
-
:
:
:
7
6
5
4
3
2
1
-
-
0
-
-
-
-
-
-
-
-
-
-
-
- R/W
DIRECT
CDMR
Initial value
XXXXXXX0
B
Readable and writable
Undefined value
Undefined
■ CAN Direct Mode Register Contents
Table 23.15-1 Function of the DIRECT Bit of the CAN Direct Mode Register
Bit name
bit7 to bit1
bit0
518
Function
Undefined
−
DIRECT
The value "1" should be written to this bit when the clock modulation is disabled.
Then, the CAN Controller skips synchronization to the modulated clock, making
the communication between CAN and CPU as fast as possible.
The value "0" must be written to this bit if the clock modulation is enabled in order
to synchronize modulated system clock and unmodulated CAN clock.
CHAPTER 23 CAN CONTROLLER
23.16
Precautions when Using CAN Controller
Use of the CAN Controller requires the following cautions.
■ For -H Devices, e.q. MB90F394H and MB90V390H: Caution for Disabling Message
Buffers by BVAL Bits
The use of BVAL bits may affect malfunction of CAN Controller when messages buffers are set disabled
while CAN Controller is participating in CAN communication (the read value of the CSR: HALT bit is "0"
and CAN Controller is ready to transmit messages). This section shows the work around of this
malfunction.
● Condition
When following two conditions occur at the same time, the CAN Controller will not perform to transmit
messages normally.
• CAN Controller is participating in the CAN communication. (i.e. The read value of the CSR: HALT bit
is" 0" and CAN Controller is ready to transmit messages)
• Message buffers are read when BVAL bits disable the message buffers.
● Work around
Operation for suppressing transmission request
Do not use BVAL bit for suppressing transmission request, use TCAN bit instead of it.
Operation for composing transmission message
For composing a transmission message, it is necessary to disable the message buffer by BVAL bit of
Message Buffer Valid Register to change contents of ID and IDE registers. In this case, BVAL bit
should reset (BVAL=0) after checking if TREQ bit is "0" or after completion of the previous message
transmission (TC=1).
In case a buffer needs to be disabled, ensure that no transmission request is pending (if it was requested
before). Therefore, do not reset BVALx-Bit before testing, if a transmission is ongoing:
a) Cancel the transmission request (TCANx=1;), if necessary
b) and wait for the transmission completion (while (TREQx=1);) by polling or interrupt.
Only after that the transmission buffer can be disabled (BVALx=0;).
Note for case a), if transmission of that buffer has already started, canceling the request is ignored and
disabling the buffer is delayed until the end of the transmission.
519
CHAPTER 23 CAN CONTROLLER
■ For Non-H Devices, e.q. MB90V390: Caution for Disabling Message Buffers by BVAL Bits
The use of BVAL bits may affect malfunction of CAN Controller when messages buffers are set disabled
while CAN Controller is participating in CAN communication (the read value of the CSR: HALT bit is "0"
and CAN Controller is ready to receive or transmit messages). This section shows the work around of this
malfunction.
● Condition
When following two conditions occur at the same time, the CAN Controller will not perform to receive or
transmit messages normally.
• CAN Controller is participating in the CAN communication. (i.e. the read value of the CSR: HALT bit
is "0" and CAN Controller is ready to receive or transmit messages)
• Message buffers are read or written when BVAL bits disable the message buffers.
● Work around
Operation for re-configuring receiving message buffers
While CAN Controller is participating in CAN communication (the read value of the CSR: HALT bit is
"0" and CAN Controller is ready to receive or transmit messages), it is necessary to follow one from the
two operations described below to re-configure message buffers by ID, AMS and AMR0/AMR1
register settings.
• Use of HALT bit
- Write "1" to HALT bit and read it back for checking the result is "1". Then change the settings for
ID/AMS/AMR0/AMR1 registers.
• No Use of Message Buffer 0
- Do not use the message buffer 0. In other words, disable message buffer (BVAL0=0), prohibit
receive interrupt (RIE0=0) and do not request transmission (TREQ0=0).
Operation for processing received message
Do not use the receiving prohibition by BVAL bit to avoid over-written of next message. Use the
ROVR bit for checking if over-write has been performed. For details, refer to Sections "23.6.16
Receive Overrun Register (ROVRR)" and "23.12 Procedure for Reception by Message Buffer (x)".
Operation for suppressing transmission request
Do not use BVAL bit for suppressing transmission request, use TCAN bit instead of it.
Operation for composing transmission message
For composing a transmission message, it is necessary to disable the message buffer by BVAL bit to
change contents of ID and IDE registers. In this case, BVAL bit should reset (BVAL=0) after checking
if TREQ bit is "0" or after completion of the previous message transmission (TC=1).
In case a buffer needs to be disabled, ensure that no transmission request is pending (if it was requested
before)! Therefore, do not reset BVALx-Bit before testing, if a transmission is ongoing:
a) Cancel the transmission request (TCANx=1;), if necessary
b) and wait for the transmission completion (while (TREQx==1);) by polling or interrupt.
Only after that the transmission buffer can be disabled (BVALx=0;).
Note for case a), if transmission of that buffer has already started, canceling the request is ignored and
disabling the buffer is delayed until the end of the transmission.
520
CHAPTER 24
STEPPING MOTOR
CONTROLLER
This chapter explains the functions and operations of
the stepping motor controller.
24.1 Outline of Stepping Motor Controller
24.2 Stepping Motor Controller Registers
24.3 Notes on Using the Stepping Motor Controller
521
CHAPTER 24 STEPPING MOTOR CONTROLLER
24.1
Outline of Stepping Motor Controller
The Stepping Motor Controller consists of two PWM Pulse Generators, four motor
drivers and the corresponding Selector Logic. The four motor drivers have high output
drive capabilities and they can be directly connected to the four ends of two motor
coils. The combination of the PWM Pulse Generators and Selector Logic is designed to
control the rotation of the motor. A Synchronization mechanism assures the
synchronous operations of the two PWMs. The MB90390 series provides 6 separate
Stepping Motor Controllers.
■ Block Diagram of Stepping Motor Controller
Figure 24.1-1 Block Diagram of Stepping Motor Controller
Machine Clock
OE1
Prescaler
CK
PWM1P0
PWM1 pulse generator
EN
P1
Output enable
Selector
PWM
PWM1M0
P0
PWM1 Compare register
PWM1 Select register
OE2
Output enable
CK
PWM2P0
PWM2 pulse generator
CE
EN
Selector
PWM2M0
PWM
Load
PWM2 Compare register
522
BS
PWM2 Select register
CHAPTER 24 STEPPING MOTOR CONTROLLER
24.2
Stepping Motor Controller Registers
The stepping motor controller "n" has the following five types of registers:
• PWM control n register (PWCn)
• PWM1 compare n register (PWC1n)
• PWM2 compare n register (PWC2n)
• PWM1 select register (PWS1n)
• PWM2 select register (PWS2n)
■ Stepping Motor Controller Registers
Figure 24.2-1 Overview of the Stepping Motor Controller Registers
Address:
bit
SMC0: 000062 H
SMC1: 000064 H
SMC2: 000066 H
SMC3: 000068 H
SMC4: 00006AH
SMC5: 00006CH
7
6
5
4
3
2
1
0
OE2
OE1
P1
P0
CE
-
-
Reserved
-
-
R/W
R/W R/W R/W R/W R/W
6
5
4
3
2
1
0
bit 7
SMC0: 003550 H
SMC1: 003554 H
D7 D6 D5 D4 D3 D2 D1 D0
SMC2: 003558 H
SMC3: 00355CH
SMC4: 003560 H R/W R/W R/W R/W R/W R/W R/W R/W
SMC5: 003564 H
bit 15
SMC0: 003551 H
SMC1: 003555 H
SMC2: 003559 H
SMC3: 00355DH
SMC4: 003561 H
SMC5: 003565 H
bit
SMC0: 003552 H
SMC1: 003556 H
SMC2: 00355AH
SMC3: 00355EH
SMC4: 003562 H
SMC5: 003566 H
14
13
12
11
10
D7 D6 D5 D4 D3 D2
9
8
D1
D0
PWCn
Initial value
0 0 0 0 0 X X 0B
PWC1n (lower)
Initial value
XXXXXXXX
B
PWC2n (upper)
Initial value
XXXXXXXXB
R/W R/W R/W R/W R/W R/W R/W R/W
7
6
5
-
-
P2
-
- R/W R/W R/W R/W R/W R/W
bit 15
4
3
2
1
0
P1 P0 M2 M1 M0
14
13
12
11
10
9
-
BS
P2
P1 P0 M2 M1 M0
-
R/W R/W R/W R/W R/W R/W R/W
PWS1n (lower)
Initial value
XX000000
B
8
PWS2n (upper)
SMC0: 003553 H
SMC1: 003557 H
SMC2: 00355BH
SMC3: 00355F H
SMC4: 003563 H
SMC5: 003567 H
Initial value
X0000000B
n = 0, 1, 2, 3, 4, 5
R/W
X
-
:
:
:
Readable and writable
Undefined value
Undefined
523
CHAPTER 24 STEPPING MOTOR CONTROLLER
24.2.1
PWM Control 0 register
The PWM control 0 register starts and stops the stepping motor controller, controls
interrupts, and sets the external output pins. Its function is equal to all other SMC
modules.
■ PWM Control 0 Register
Figure 24.2-2 Configuration of the PWM Control 0 Register
Address:
bit
SMC0: 000062 H
SMC1: 000064 H
SMC2: 000066 H
SMC3: 000068 H
SMC4: 00006AH
SMC5: 00006CH
7
6
5
4
3
2
1
0
OE2
OE1
P1
P0
CE
-
-
Reserved
-
-
R/W
R/W R/W R/W R/W R/W
PWCn
Initial value
00000XX0B
bit 0
Reserved
0
1
Reserved bit
This is a reserved bit. Always write "0" to it.
bit 4
CE
Count enable bit
0
PWM generator stopped
1
PWM generator operating
bit 5
P1
bit 4
0
P0
0
Operation Clock select bits
Machine clock
0
1
1/2 Machine clock
1
0
1/4 Machine clock
1
1
1/8 Machine clock
bit 6
OE1
Output enable 1 bit
0
Output is general Purpose Pin
1
PWM1Pn and PWM1Mn output enable
bit 7
OE2
524
R/W
:
Readable and writable
0
X
:
Undefined value
1
-
:
Undefined
:
Initial value
Output enable 2 bit
Output is general Purpose Pin
PWM2Pn and PWM2Mn output enable
n = 0, 1, 2, 3, 4, 5
CHAPTER 24 STEPPING MOTOR CONTROLLER
■ Pulse Width Control Register Contents
Table 24.2-1 Function of Each Bit of Pulse Width Control Register (PWCn)
Bit name
Function
bit7
OE2:
Output enable 2 bit
When this bit is set to "1", the external pins are assigned as PWM2Pn and PWM2Mn
outputs. Otherwise they can be used as general purpose I/O.
bit6
OE1:
Output enable 1 bit
When this bit is set to "1", the external pins are assigned as PWM1Pn and PWM1Mn
outputs. Otherwise they can be used as general purpose I/O.
These bits specify the clock input signal for the PWM pulse generators.
bit5, bit4
bit3
P1, P0:
Operation Clock
select bits
CE:
Count enable bit
bit2, bit1
Undefined
bit0
reserved bit
P1
P0
Clock Input
0
0
Machine clock
0
1
1/2 Machine clock
1
0
1/4 Machine clock
1
1
1/8 Machine clock
This bit enables the operation of the PWM pulse generators. When it is set to "1", the
PWM pulse generators start their operation. Note that the PWM2 pulse generator starts
the operation one machine clock cycle after the PWM1 pulse generators is started. This
is to help reduce the switching noise from the output drivers.
−
This is a reserved bit. Always write "0" to this bit.
525
CHAPTER 24 STEPPING MOTOR CONTROLLER
24.2.2
PWM1 and PWM2 Compare Registers
The contents of the two 8-bit compare registers determine the widths of PWM pulses.
The stored value of "00H" represents the PWM duty of 0% and "FFH" represents the
duty of 99.6%.
■ PWM1 and PWM2 Compare Registers
PWM1 and PWM2 compare registers are accessible at any time, however the modified values are reflected
to the pulse width at the end of the current PWM cycle after the BS bit of the PWM2 Select register is set to
"1".
Figure 24.2-3 PWM1 and PWM2 Compare Registers
Address:
bit
SMC0: 003550 H
SMC1: 003554 H
SMC2: 003558 H
SMC3: 00355CH
SMC4: 003560 H
SMC5: 003564 H
bit
7
6
5
4
3
2
1
0
D1
D0
PWC1n (lower)
D7 D6 D5 D4 D3 D2
R/W R/W R/W R/W R/W R/W R/W R/W
15
14
13
12
11
10
9
8
D1
D0
Initial value
XXXXXXXX
B
PWC2n (upper)
SMC0: 003551 H
SMC1: 003555 H
SMC2: 003559 H
SMC3: 00355DH
SMC4: 003561 H
SMC5: 003565 H
D7 D6 D5 D4 D3 D2
Initial value
XXXXXXXXB
R/W R/W R/W R/W R/W R/W R/W R/W
Figure 24.2-4 Examples for Duty Cycle Settings
One PWM Cycle
256 input clock cycles
Register value
00H
80H
128 input clock cycles
FFH
255 input clock cycles
526
CHAPTER 24 STEPPING MOTOR CONTROLLER
24.2.3
PWM1 and PWM2 Select Registers
The PWM1 and PWM2 select registers "0", "1", the PWM pulse, or high impedance for
the external pin output of the stepping motor controller.
■ PWM1 Select Registers
Figure 24.2-5 Configuration of the PWM1 Select Registers
Address:
SMC0: 003552 H
SMC1: 003556 H
SMC2: 00355AH
SMC3: 00355EH
SMC4: 003562 H
SMC5: 003566 H
bit
7
6
5
4
3
2
1
0
-
-
P2
-
- R/W R/W R/W R/W R/W R/W
P1 P0 M2 M1 M0
PWS1n
Initial value
X X 0 0 0 0 00 B
bit 2
bit 1
M1
M0
0
0
0
PWM1Mn = "L"
0
0
1
PWM1Mn = "H"
0
1
X
PWM pulses
1
X
X
High impedance
bit 5
R/W
:
Readable and writable
-
:
Undefined
:
Initial value
bit 0
M2
bit 4
M1 Output Select bits
bit 3
P2
P1
P0
0
0
0
P1 Output Select bits
0
0
1
PWM1Pn ="H"
0
1
X
PWM pulses
1
X
X
High impedance
PWM1Pn = "L"
n = 0, 1, 2, 3, 4, 5
527
CHAPTER 24 STEPPING MOTOR CONTROLLER
■ Pulse Width Modulator 1 Select Registers (PWS1n) Contents
Table 24.2-2 Function of Each Bit of the PWM1 Select Registers
Bit name
bit7, bit6
Function
−
Undefined
These bits selects the output signal at PWM1Pn
bit5 to bit3
P2 to P0:
Output P select
bits
P2
P1
P0
PWM1Pn
0
0
0
"L"
0
0
1
"H"
0
1
x
PWM pulses
1
x
x
High impedance
These bits selects the output signal at PWM1Mn
bit2 to bit0
528
M2 to M0:
Output M select
bits
M2
M1
M0
PWM1Mn
0
0
0
"L"
0
0
1
"H"
0
1
x
PWM pulses
1
x
x
High impedance
CHAPTER 24 STEPPING MOTOR CONTROLLER
■ PWM2 Select Registers
bit
Address:
SMC0: 003553 H
SMC1: 003557 H
SMC2: 00355BH
SMC3: 00355F H
SMC4: 003563 H
SMC5: 003567 H
15
14
13
12
11
10
9
8
-
BS
P2
P1 P0 M2 M1 M0
PWS2n
-
R/W R/W R/W R/W R/W R/W R/W
Initial value
X 0 0 0 0 0 0 0B
bit 10
bit 9
bit 8
M2
M1
M0
0
0
0
PWM2Mn = "L"
M2 Output Select bits
0
0
1
PWM2Mn = "H"
0
1
X
PWM pulses
1
X
X
High impedance
bit 13
bit 12
bit 11
P2
P1
P0
0
0
0
PWM2Pn = "L"
P2 Output Select bits
0
0
1
PWM2Pn = "H"
0
1
X
PWM pulses
1
X
X
High impedance
bit 14
BS
R/W
:
Readable and writable
-
:
Undefined
:
Initial value
Update bit
0
-
1
Pulse-Generator and Selector load register contents at end of PWM cycle
n = 0, 1, 2, 3, 4, 5
529
CHAPTER 24 STEPPING MOTOR CONTROLLER
■ Pulse Width Modulator 2 Select Registers (PWS2n) Contents
Table 24.2-3 Function of Each Bit of the PWM 2 Select Registers
Bit name
bit15
bit14
Function
Undefined
−
BS:
Update bit
This bit is prepared to synchronize the settings for the PWM outputs. Any modifications
in the two compare registers and two select registers are not reflected to the output
signals until this bit is set.
When this bit is set to "1", the PWM pulse generators and selectors load the register
contents at the end of the current PWM cycle. The BS bit is reset to "0" automatically at
the beginning of the next PWM cycle. If the BS bit is set to "1" by software at the same
time as this automatic reset, the BS bit is set to "1" (or remains unchanged) and the
automatic reset is cancelled.
These bits selects the output signal at PWM2Pn
bit13 to
bit11
P2 to P0:
Output P select
bits
P2
P1
P0
PWM2Pn
0
0
0
"L"
0
0
1
"H"
0
1
x
PWM pulses
1
x
x
High impedance
These bits selects the output signal at PWM2Mn
bit10 to
bit8
530
M2 to M0:
Output M select
bits
M2
M1
M0
PWM2Mn
0
0
0
"L"
0
0
1
"H"
0
1
x
PWM pulses
1
x
x
High impedance
CHAPTER 24 STEPPING MOTOR CONTROLLER
24.3
Notes on Using the Stepping Motor Controller
This section provides notes on using the stepping motor controller
■ Notes on Changing the PWM Setting Values
PWM Compare Register 1 (PWC1n), PWM Compare Register 2 (PWC2n), PWM Selection Register 1
(PWS1n), and PWM Selection Register 2 (PWS2n) can always be accessed. To change the setting of the
PWM’s "H" width or PWM output, write the setting values to these registers, then set the BS bit of PWM
Selection Register 2 to "1" (or do this simultaneously).
If the BS bit is set to "1", the new setting value will become effective at the end of the current PWM cycle,
and the BS bit is automatically cleared.
If setting the BS bit to "1" and resetting the BS bit at the end of the PWM cycle both occur at the same
time, writing "1" has priority and resetting the BS bit will be cancelled.
531
CHAPTER 24 STEPPING MOTOR CONTROLLER
532
CHAPTER 25
SOUND GENERATOR
This chapter explains the functions and operations of
the sound generator.
25.1 Outline of Sound Generator
25.2 Sound Generator Registers
533
CHAPTER 25 SOUND GENERATOR
25.1
Outline of Sound Generator
The Sound Generator consists of the Sound Control register, Frequency Data register,
Amplitude Data register, Decrement Grade register, Tone Count register, PWM pulse
generator, Frequency counter, Decrement counter and Tone Pulse counter.
■ Block Diagram of Sound Generator
Figure 25.1-1 shows a block diagram of the sound generator.
Figure 25.1-1 Block Diagram of Sound Generator
Clock input
Prescaler
S1
S0
8bit PWM pulse
Generator CO
EN
PWM
CI
Frequency
Counter
Toggle
Flip-flop
CO
EN
reload
Amplitude Data
register
reload
Q
1/d
Frequency Data
Register
DEC
DEC
Decrement
Counter
D
EN
CI
CO
EN
SGA
OE1
Decrement Grade
register
Tone Pulse
Counter
Tone Count
register
OE1
Mix
SGO
TONE OE2
OE2
CI
CO
EN
INTE
INT
ST
IRQ
534
CHAPTER 25 SOUND GENERATOR
25.2
Sound Generator Registers
The sound generator has the following five types of registers:
• Sound control register (SGCR)
• Frequency data register (SGFR)
• Amplitude data register (SGAR)
• Decrement grade register (SGDR)
• Tone count register (SGTR)
■ Sound Generator Registers
Figure 25.2-1 Overview on the Sound Generator Registers
Address: bit 7
S1
00005EH
6
S0
5
4
TONE OE2
3
2
OE1 INTE
1
0
SGCR (lower)
INT
ST
Initial value
0 0 0 0 0 0 0 0B
R/W R/W R/W R/W R/W R/W R/W R/W
bit 15
14
13
12
11
10
-
-
-
-
-
R/ W -
-
-
-
-
5
4
3
2
00005FH
Reserved
bit
7
6
D7 D6 D5 D4 D3 D2
003546 H
9
8
BUSY DEC
R R/W
1
0
D1 D0
SGCR (upper)
Initial value
0XXXXX00B
SGFR
Initial value
XXXXXXXXB
R/W R/W R/W R/W R/W R/W R/W R/W
bit 15
003547H
14
13
12
11
10
D7 D6 D5 D4 D3 D2
9
8
D1 D0
R/W R/W R/W R/W R/W R/W R/W R/W
bit
7
6
5
4
3
2
D7 D6 D5 D4 D3 D2
003548 H
1
0
D1 D0
SGAR
Initial value
XXXXXXXX
B
SGDR
Initial value
XXXXXXXXB
R/W R/W R/W R/W R/W R/W R/W R/W
bit 15
003549H
14
13
12
11
10
D7 D6 D5 D4 D3 D2
9
8
D1 D0
R/W R/W R/W R/W R/W R/W R/W R/W
R/W
X
-
:
:
:
SGTR
Initial value
XXXXXXXXB
Readable and writable
Undefined value
Undefined
535
CHAPTER 25 SOUND GENERATOR
25.2.1
Sound Generator Control Register
The sound control register controls the operation status of the sound generator by
controlling interrupts and setting the external output pins.
■ Sound Generator Control Register (Lower)
Figure 25.2-2 Configuration of the Sound Generator Control Register (Lower Byte)
Address: bit 7
00005EH
S1
6
S0
5
4
TONE OE2
3
2
OE1 INTE
1
0
SGCR (lower)
INT
ST
Initial value
0 0 0 0 0 0 0 0B
R/W R/W R/W R/W R/W R/W R/W R/W
bit 0
ST
Start bit
0
Stop operation
1
Start operation
bit 1
Interrupt bit
INT
read
write
0
no interrupt
clear interrupt
1
interrupt request
no effect
bit 2
INTE
Interrupt enable bit
0
Interrupt disabled
1
Interrupt enabled
bit 3
OE1
Amplitude output enable bit
0
General purpose pin
1
SGA Output enabled
bit 4
OE2
Sound output enable bit
0
General purpose pin
1
SGO Output enabled
bit 5
TONE
Tone and PWM mixed
1
SGO output
bit 7
R/W
536
Tone output bit
0
bit 6
S1
S0
0
0
Machine clock
Operation clock select bit
1/2 machine clock
0
1
:
Readable and writable
1
0
1/4 machine clock
:
Initial value
1
1
1/8 machine clock
CHAPTER 25 SOUND GENERATOR
■ Sound Generator Control Register (SGCR) (Lower) Contents
Table 25.2-1 Function of Each Bit of the Sound Control Register (Lower)
Bit name
Function
These bits specify the clock input signal for the Sound Generator.
bit7, bit6
S1, S0:
Operation clock
select bits
S1
S0
Clock input
0
0
Machine clock
0
1
1/2 Machine clock
1
0
1/4 Machine clock
1
1
1/8 Machine clock
bit5
TONE:
Tone output bit
When this bit is set to "1", the SGO signal becomes a simple square-waveform (tone
pulses) from the toggle flip-flop. Otherwise the SGO signal is the mixed (AND logic)
signal of the tone and PWM pulses.
bit4
OE2:
Sound output
enable bit
When this bit is set to "1", the external pin is assigned as the SGO output. Otherwise the
pin can be used as a general purpose I/O. To enable the SGO output, the corresponding
bit of the Port Direction register should also be set to "1".
bit3
OE1:
Amplitude output
enable bit
When this bit is set to "1", the external pin is assigned as the SGA output. Otherwise the
pin can be used as a general purpose I/O. To enable the SGA output, the corresponding
bit of the Port Direction register should also be set to "1".
The SGA signal is the PWM pulses from the PWM pulse generator representing the
amplitude of the sound.
bit2
INTE:
Interrupt enable
bit
This bit enables the interrupt signal of the Sound Generator. When this bit is "1" and the
INT bit is set to "1", the Sound Generator signals an interrupt.
bit1
INT:
Interrupt bit
This bit is set to "1" when the Tone Pulse counter counts the number of the tone pulses
specified by the Tone Count register and Decrement Grade register.
This bit is reset to "0" by writing "0". Writing "1" has no effect and Read-Modify-Write
(RMW) instructions always result in reading "1".
ST:
Start bit
This bit is for starting the operation of the Sound Generator. While this bit is "1", the
Sound Generator perform its operation.
When this bit is reset to "0", the Sound Generator stops its operation at the end of the
current tone cycle. The BUSY bit indicates whether the Sound Generator is fully
stopped.
When this bit is changed from "0" to "1", the value of Frequency Data register,
Amplitude Data register, Decrement Grade register, and Tone Count register is loaded
into each counter.
bit0
537
CHAPTER 25 SOUND GENERATOR
■ Sound Generator Control Register (Upper)
Figure 25.2-3 Configuration of the Sound Generator Control Register (Upper Byte)
bit 15
00005FH
14
13
12
11
10
Reserved
-
-
-
-
-
R/W
-
-
-
-
-
9
8
BUSY DEC
R R/W
SGCR (upper)
Initial value
0 X X X X X 0 0B
bit 8
DEC
Auto-decrement enable bit
0
Auto-decrement disabled
1
Auto-decrement enabled
bit 9
BUSY
Nusy bit
0
Operation completed
1
Generator is busy
bit 15
Reserved
R/W
:
Readable and writable
R
:
Read only
-
:
Undefined
:
Initial value
0
1
Reserved bit
always write "0" to this bit
■ Sound Generator Control Register (SGCR) (Upper) Contents
Table 25.2-2 Function of Each Bit of the Sound Generator Control Register (Upper)
Bit name
bit15
bit14 to
bit10
538
Reserved bit
Undefined
Function
This is a reserved bit. Always write "0" to this bit.
−
bit9
BUSY:
Busy bit
This bit indicates whether the Sound Generator is in operation. This bit is set to "1"
upon the ST bit is set to "1". It is reset to "0" when the ST bit is reset to "0" and the
operation is completed at the end of one tone cycle. Any write instructions performed
on this bit has no effect.
bit8
DEC:
Auto-decrement
enable bit
The DEC bit is prepared for an automatic de-gradation of the sound in conjunction
with the Decrement Grade register.
If this bit is set to "1", the stored value in the Amplitude Data register is decremented
by 1(one), every time when the Decrement counter counts the number of tone pulses
from the toggle flip-flop specified by the Decrement Grade register.
CHAPTER 25 SOUND GENERATOR
25.2.2
Frequency Data register
The Frequency Data register stores the reload value for the Frequency counter. The
stored value represents the frequency of the sound (or the tone signal from the toggle
flip-flop). The register value is reloaded into the counter at Frequency counter
underflow and PWM pulse generator underflow.
The following figure shows the relationship between the tone signal and the register
value.
■ Frequency Data Register
bit
Address:
003546 H
7
6
5
4
3
2
D7 D6 D5 D4 D3 D2
1
0
D1 D0
SGFR
Initial value
XXXXXXXXB
R/W R/W R/W R/W R/W R/W R/W R/W
Figure 25.2-4 shows the relationship between a tone signal and a register value.
Figure 25.2-4 Relationship between Tone Signal and Register Value
One Tone Cycle
Tone signal
(register value+1) x
One PWM cycle
(register value+1) x
One PWM cycle
It should be noted that modifications of the register value while operation may alter the duty cycle of 50%
depending on the timing of the modification.
539
CHAPTER 25 SOUND GENERATOR
25.2.3
Amplitude Data Register
The Amplitude Data register stores the reload value for the PWM pulse generator. The
register value represents the amplitude of the sound. The register value is reloaded into
the PWM pulse generator at falling edge of tone signal.
■ Amplitude Data Register
Address:
003547H
bit 15
14
13
12
11
10
D7 D6 D5 D4 D3 D2
9
8
D1 D0
R/W R/W R/W R/W R/W R/W R/W R/W
SGAR
Initial value
XXXXXXXX
B
When the DEC bit is "1" and the Decrement counter reaches its reload value, this register value is
decremented by 1(one). And when the register value reaches "00H", further decrements are not performed.
However the sound generator continues its operation until the ST bit is cleared.
Figure 25.2-5 shows the relationship between the register value and the PWM pulse.
Figure 25.2-5 Relationship between Register Value and PWM Pulse
One PWM Cycle
256 input clock cycles
Register value
00H
One input clock cycles
80H
129 input clock cycles
FEH
255 input clock cycles
FFH
256 input clock cycles
When the register value is set to "FFH", the PWM signal is always "1".
540
CHAPTER 25 SOUND GENERATOR
25.2.4
Decrement Grade Register
The Decrement Grade register stores the reload value for the Decrement counter. They
are prepared to automatically decrement the stored value in the Amplitude Data
register. The register value is reloaded into the counter at Decrement counter underflow
and falling edge of tone signal.
■ Decrement Grade Register
bit 7
Address:
003548 H
6
5
4
3
2
D7 D6 D5 D4 D3 D2
1
0
D1 D0
SGDR
Initial value
XXXXXXXXB
R/W R/W R/W R/W R/W R/W R/W R/W
When the DEC bit is "1" and the Decrement counter counts the number of tone pulses up to the reload
value, the stored value in the Amplitude Data register is decremented by 1(one) at the end of the tone cycle.
This operation realizes automatic de-gradation of the sound with fewer number of CPU interventions.
It should be noted that the number of the tone pulses specified by this register equals to "register value +1".
When the Decrement Grade register is set to "00H", the decrement operation is performed every tone cycle.
541
CHAPTER 25 SOUND GENERATOR
25.2.5
Tone Count Register
The Tone Count register stores the reload value for the Tone Pulse counter. The Tone
Pulse counter accumulate the number of tone pulses (or number of decrement
operations) and when it reaches the reload value it sets the INT bit. They are intended to
reduce the frequency of interrupts. The register value is reloaded into the counter at
Tone Pulse counter underflow, Decrement counter underflow, and falling edge of tone
signal.
■ Tone Count Register
Address:
003549H
bit 15
14
13
12
11
10
D7 D6 D5 D4 D3 D2
9
8
D1 D0
R/W R/W R/W R/W R/W R/W R/W R/W
SGTR
Initial value
XXXXXXXXB
The count input of the Tone Pulse counter is connected to the carry-out signal from the Decrement counter.
And when the Tone count register is set to "00H", the Tone Pulse counter sets the INT bit every carry-out
from the Decrement counter. Thus the number of accumulated tone pulses is;
((Decrement Grade register) +1) × ((Tone Count register) +1)
i.e. When the both registers are set to "00H", the INT bit is set every tone cycle.
542
CHAPTER 26
ADDRESS MATCH
DETECTION FUNCTION
This chapter explains the address match detection
function and operation.
26.1 Outline of the Address Match Detection Function
26.2 Registers of the Address Match Detection Function
26.3 Operation of the Address Match Detection Function
26.4 Example of the Address Match Detection Function
543
CHAPTER 26 ADDRESS MATCH DETECTION FUNCTION
26.1
Outline of the Address Match Detection Function
When an address matches the value set in the address detection register, the
instruction code to be read by the CPU is replaced with the INT9 instruction code (01H).
Consequently, the CPU executes the INT9 instruction when executing a specified
instruction. The address match detection function can be achieved using the INT9
interrupt routine for processing.
There are 5 address detection registers, each with an interrupt permission bit. When an
address matches the value set in the address detection register and the interrupt
permission bit is "1", the instruction code to be read by the CPU is replaced with the
INT9 instruction code.
■ Block Diagram of the Address Match Detection Function
Address latch
Address detection
register
Permission bit
F2MC-16LX bus
544
Comparison
Figure 26.1-1 Block Diagram of the Address Match Detection Function
INT9
instruction
F2MC-16LX
CPU core
CHAPTER 26 ADDRESS MATCH DETECTION FUNCTION
26.2
Registers of the Address Match Detection Function
The two types of registers for the address match detection function are as follows:
• Program address detection registers (PADR0, PADR1, PADR3 to PADR5)
• Program address detection control status register (PACSR0 and PACSR1)
■ Program Address Detection Registers (PADR0, PADR1, PADR3 to PADR5)
The program address detection registers compare the address with the value written in each register. If they
match when the interrupt permission bit corresponding to ADCSR is "1", the CPU is requested to issue the
INT9 instruction.
When the corresponding interrupt bit is "0", nothing occurs.
Figure 26.2-1 Program Address Detection Registers (PADR0, PADR1, PADR3 to PADR5)
Program address detection registers
PADR0
PADR1
PADR3
PADR4
PADR5
byte
0035E2H/0035E1H/0035E0H
0035E5H/0035E4H/0035E3H
0035F2H/0035F1H/0035F0H
0035F5H/0035F4H/0035F3H
0035F8H/0035F7H/0035F6H
byte
byte
Access
Initial value
R/W
R/W
R/W
R/W
R/W
Not defined
Not defined
Not defined
Not defined
Not defined
Table 26.2-1 lists the correspondence PADR0, PADR1, PADR3 to PADR5 registers and PACSR0 and
PACSR1 registers.
Table 26.2-1 Correspondence PADR0, PADR1, PADR3 to PADR5 Registers and PACSR0
and PACSR1 Registers
Address detection register
Interrupt permission bit
PADR0
AD0E (bit1)
PADR1
AD1E (bit3)
PADR3
AD3E (bit1)
PADR4
AD4E (bit3)
PADR5
AD5E (bit5)
545
CHAPTER 26 ADDRESS MATCH DETECTION FUNCTION
■ Program Address Detection Control Status Register (PACSR)
The program address detection control / status register (PACSR) controls the operation of the address
detection function.
Figure 26.2-2 Program Address Detection Control Status Registers (PACSR0/PACSR1)
Address: bit 7
00009E H
6
5
4
3
2
1
0
Reserved Reserved Reserved Reserved AD1E Reserved AD0E Reserved
R/W R/W R/W R/W R/W R/W R/W R/W
Address: bit 15
00003B H
14
13
12
11
10
9
8
Reserved Reserved AD5E Reserved AD4E Reserved AD3E Reserved
R/W R/W R/W R/W R/W R/W R/W R/W
R/W
PACSR0
Initial value
00000000
B
PACSR1
Initial value
0 0 0 0 0 0 0 0B
: Readable and writable
Table 26.2-2 Function of Each Bit of PACSR1 and PACSR0
Bit name
bit15, bit14
Function
Reserved bits
Bit15, bit14 are reserved. Set these bits to "0" before setting PACSR1.
bit13
AD5E:
Address detect
register 1 enable
The AD5E bit is the operation permission bit for PADR5.
When this bit is "1", the address is compared with the PADR5 register. If they match,
the INT9 instruction is issued.
bit12
Reserved bit
Bit12 is reserved. Set this bit to "0" before setting PACSR1.
bit11
AD4E:
Address detect
register 1 enable
The AD4E bit is the operation permission bit for PADR4.
When this bit is "1", the address is compared with the PADR4 register. If they match,
the INT9 instruction is issued.
bit10
Reserved bit
Bit10 is reserved. Set this bit to "0" before setting PACSR1.
bit9
AD3E:
Address detect
register 1 enable
The AD3E bit is the operation permission bit for PADR3.
When this bit is "1", the address is compared with the PADR3 register. If they match,
the INT9 instruction is issued.
bit8
Reserved bit
Bit8 is reserved. Set this bit to "0" before setting PACSR1.
bit7 to bit4
Reserved bits
Bit7 to bit4 are reserved. Set these bits to "0" before setting PACSR0.
bit3
AD1E:
Address detect
register 1 enable
The AD1E bit is the operation permission bit for PADR1.
When this bit is "1", the address is compared with the PADR1 register. If they match,
the INT9 instruction is issued.
bit2
Reserved bit
Bit2 is reserved. Set this bit to "0" before setting PACSR0.
bit1
AD0E:
Address detect
register 0 enable
The AD0E bit is the operation permission bit for PADR0.
When this bit is "1", the address is compared with the PADR0 register. If they match,
the INT9 instruction is issued.
bit0
Reserved bit
Bit0 is reserved. Set this bit to "0" before setting PACSR0.
546
CHAPTER 26 ADDRESS MATCH DETECTION FUNCTION
26.3
Operation of the Address Match Detection Function
If the program counter specifies the same address as the address match detection
register, the INT9 instruction is executed. The address match detection function can be
achieved by processing the INT9 instruction routine.
■ Operation of the Address Match Detection Function
There are 5 address detection registers with a compare enable bit. When the value set in the address
detection register and the value of the program counter match and the compare enable bit is set to "1", the
CPU executes the INT9 instruction.
Note:
If the value of the address detection register and the value of the program counter match, the
contents of internal data bus is changed to "01H". Consequently, the INT9 instruction is executed.
Before changing the contents of the address detection register, always set the compare enable bit to
"0". While the compare enable bit is set to "1", changing the contents of the address detection
register may result in a malfunction.
547
CHAPTER 26 ADDRESS MATCH DETECTION FUNCTION
26.4
Example of the Address Match Detection Function
Figure 26.4-1 shows a system configuration example of the address match detection
function. Table 26.4-1 lists the E2PROM memory map.
■ System Configuration Example of the Address Match Detection Function
Figure 26.4-1 System Configuration Example of the Address Match Detection Function
E2PROM
MCU
F2MC-16LX
SIN
Pull-up resistor
Connector (UART)
Table 26.4-1 E2PROM Memory Map
Address
0000H
Number of bytes of patch program No.0 (If "0", no program error exists.)
0001H
Program address No.0 (bit7 to bit0)
0002H
Program address No.0 (bit15 to bit8)
0003H
Program address No.0 (bit24 to bit16)
0004H
Number of bytes of patch program No.1 (If "0", no program error exists.)
0005H
Program address No.1 (bit7 to bit0)
0006H
Program address No.1 (bit15 to bit8)
0007H
Program address No.1 (bit24 to bit16)
0010H or higher
● Initial status
E2PROM is set to all 0s.
548
Description
Main body of patch program No. 0
CHAPTER 26 ADDRESS MATCH DETECTION FUNCTION
● When a program error occurs:
The main body of the patch program and program address are transferred to the MCU through the
connector (UART). The MCU writes the information to E2PROM.
● Reset sequence
The MCU reads the value of E2PROM after reset. If the number of bytes of the patch program is not 0, the
main body of the patch program is read from E2PROM and written to RAM. The MCU then uses either
PADR0 or PADR1 to set the patch address and sets the compare enable bit. If the relocatable patch
program is required, the first address of the patched program can be written to the RAM area. In this case,
the INT9 routine accesses this user-defined RAM area and jumps to the patched program.
● INT9 interrupt
The interrupt routine can know the address where the interrupt occurs by checking the value of the stack
program counter. The information that has been placed on the stack during the interrupt is discarded.
■ Example of Program Patch Processing
Figure 26.4-2 Example of Program Patch Processing
000000H
Correction program
RAM
Program address
detection register
E2PROM
Program address
detection setting
(reset sequence)
Correction program byte number
Interrupt generation address
Correction program
Abnormal program
ROM
FFFFFFH
Setting the program address detecting of reset sequence, executing normal program
Branch to the patch program that is expanded to RAM by INT9 interruption from address match detection.
Executing the patch program by branching of INT9 operation.
Executing the normal program that is branched by the patch program
549
CHAPTER 26 ADDRESS MATCH DETECTION FUNCTION
Figure 26.4-3 Flow of Program Patch Processing
Reset
Reads "00H" of E2PROM
INT9
YES
"0000H" (E2PROM)=0
To patch program
JMP 000400H
NO
Read address
"0001H" to "0003H" (E2PROM)
MOV
PADR0 (MCU)
Execute patch program
"000400H" to "000480H"
Read patch program
"0010H" to "0090H" (E2PROM)
MOV
"000400H" to "000480H" (MCU)
Terminate patch program
JMP FF0050H
Enable compare
MOV PACSR, #02H
Execute normal program
NO
PC=PADR0
YES
INT9
FFFFFFH
FF0050H
ROM
E2PROM
Abnormal program
FF0000H
FFFFH
FE0000H
0090H
Patch program
0010H
0003H
0002H
0001H
0000H
550
001100H
Program address
low-order:
Program address
middle-order:
Program address
high-order:
Number of bytes of
the patch program:
RAM area
00
00
Stack area
000480H
RAM
Patch program
000400H
RAM and register area
FF
000100H
I/O area
80
000000H
CHAPTER 27
ROM MIRRORING MODULE
This chapter explains the ROM mirroring module.
27.1 Outline of ROM Mirroring Module
27.2 ROM Mirroring Register (ROMM)
551
CHAPTER 27 ROM MIRRORING MODULE
27.1
Outline of ROM Mirroring Module
The ROM Mirroring module switches whether to mirror the image of the FF bank of the
ROM to the 00 bank.
■ Block Diagram of ROM Mirroring Module
Figure 27.1-1 Block Diagram of ROM Mirroring Module
F2MC-16LX BUS
ROM Mirrroring Register
Address Area
FF bank
00 bank
ROM
552
CHAPTER 27 ROM MIRRORING MODULE
27.2
ROM Mirroring Register (ROMM)
Do not access the ROM mirroring register (ROMM) when addresses "004000H" to
"00FFFFH" are being accessed.
■ ROM Mirroring Register (ROMM)
Figure 27.2-1 ROM Mirroring Register (ROMM)
Address:
00006FH
bit 15
14
13
12
11
10
-
-
-
-
-
-
MS MI
-
-
-
-
-
-
R/W W
(+)
R/W
W
:
:
Readable and writable
Write only
X
-
:
:
Undefined value
Undefined
9
8
ROMM
Initial value
X X X X X X + 1B
(+): MB90V390H: read only, fixed to "1"
MB90F394H: selectable; initial value "0"
Table 27.2-1 Function of Each Bit of ROM Mirroring Register
Bit name
bit15 to
bit10
Undefined
Function
−
bit9
MS:
Mirror size
"1": The ROM mirror size is 32K Bytes (008000H to 00FFFFH)
"0": The ROM mirror size is 48K Bytes (004000H to 00FFFFH)
Note:
This bit is fixed to "1" and read only in the MB90V390H, MB90V390HA, and
MB90F390HB.
In MB90394HA and MB90F394H(A) it is selectable.
bit8
MI:
Mirror bit
The image of the ROM data in the FF bank can also be found in the 00 bank when "1" is
written to this bit. However, this memory mapping will not be done when this bit is
written to "0". This bit is write only.
Note:
Only "FF4000H"/"FF8000H" to "FFFFFFH" is mirrored to "004000H"/"008000H" to "00FFFFH" when
the ROM mirroring function is activated. Therefore, addresses "FF0000H" to "FF3FFFH"/"FF7FFFH"
will not be mirrored to 00 bank.
553
CHAPTER 27 ROM MIRRORING MODULE
554
CHAPTER 28
3M-BIT FLASH MEMORY
This chapter explains the functions and operation of the
3M-bit flash memory.
The following three methods are available for writing
data to and erasing data from the flash memory:
• Parallel programmer
• Serial programmer
• Executing programs to write/erase data
This chapter explains "Executing programs to write/
erase data".
28.1 Overview of 3M-bit Flash Memory
28.2 Block Diagram of the Entire Flash Memory and Sector
Configuration of the Flash Memory
28.3 Write/Erase Modes
28.4 Flash Memory Control Status Register (FMCS)
28.5 Starting the Flash Memory Automatic Algorithm
28.6 Confirming the Automatic Algorithm Execution State
28.7 Detailed Explanation of Writing to and Erasing Flash Memory
28.8 Notes on using 3M-bit Flash Memory
28.9 Reset Vector Address in Flash Memory
28.10 Example of Programming 3M-bit Flash Memory
555
CHAPTER 28 3M-BIT FLASH MEMORY
28.1
Overview of 3M-bit Flash Memory
The 3M-bit flash memory is mapped to the F8/F9 to FF bank in the CPU memory map.
The functions of the flash memory interface circuit enable read-access and programaccess from the CPU in the same way as mask ROM. Instructions from the CPU can be
used via the flash memory interface circuit to write data to and erase data from the flash
memory. Internal CPU control therefore enables rewriting of the flash memory while it is
mounted. As a result, improvements in programs and data can be performed efficiently.
■ 3M-bit Flash Memory Features
•
Use of automatic program algorithm (Embedded AlgorithmTM*: Equivalent to MBM29LV200)
•
Erase pause/restart functions provided
•
Detection of completion of writing/erasing using data polling or toggle bit functions
•
Detection of completion of writing/erasing using CPU interrupts
•
Sector erase function (any combination of sectors)
•
Minimum of 10,000 write/erase operations
*: Embedded Algorithm is a trademark of Advanced Micro Device, Inc.
Note:
The manufacturer code and device code do not have the reading function. These codes cannot be
accessed by the command.
■ Writing to/Erasing Flash Memory
The flash memory cannot be written to and read at the same time. That is, when data is written to or erased
data from the flash memory, the program in the flash memory must first be copied to RAM. The entire
process is then executed in RAM so that data is simply written to the flash memory. This eliminates the
need for the program to access the flash memory from the flash memory itself.
■ Flash Memory Control Status Register (FMCS)
bit
Address: 0000AE H
556
7
6
5
4
3
INTE
RDYINT
WE
RDY
Reserved
(R/W)
(R/W)
(R/W)
(R)
(R/W)
2
1
Reserved Reserved
(R/W)
(R/W)
0
Reserved
(R/W)
Initial value
000X0000B
CHAPTER 28 3M-BIT FLASH MEMORY
28.2
Block Diagram of the Entire Flash Memory and Sector
Configuration of the Flash Memory
Figure 28.2-1 shows the block diagram of the entire flash memory. Figure 28.2-2 shows
the sector configuration of the 3M-bit flash memory.
■ Block Diagram of the Entire Flash Memory
Figure 28.2-1 Block Diagram of the Entire Flash Memory
Flash memory
interface circuit
Port 0
Port 1
Port 2
Port 3
Port 4
Port 5
F2MC-16LX
bus
3Mbit
2Mbit/3Mbit
Flash memory
BYTE
INT
BYTE
CE
CE
OE
OE
WE
WE
AQ0 to AQ18
AQ0 to AQ18
DQ0 to DQ15
DQ0 to DQ15
RY/BY
RY/BY
RESET
Write enable interrupt signal
(to CPU)
External reset signal
RY/BY write
enable signal
557
CHAPTER 28 3M-BIT FLASH MEMORY
■ Sector Configuration of the 3M-bit Flash Memory
Figure 28.2-2 shows the sector configuration of the 3M-bit flash memory. The addresses in the figure
indicate the high-order and low-order addresses of each sector.
Figure 28.2-2 Sector Configuration of the 3M-bit Flash Memory
Writer
address*
CPU address
SA8 (16 KByes)
7FFFFH
FFFFFFH
SA7 (8 KBytes)
7BFFFH
FFBFFFH
SA6 (8 KByes)
79FFFH
FF9FFFH
SA5 (32 KBytes)
77FFFH
FF7FFFH
SA4 (64 KByes)
6FFFFH
FEFFFFH
SA3 (64 KBytes)
5FFFFH
FDFFFFH
Unused
4FFFFH
FCFFFFH
SA2 (64 KBytes)
3FFFFH
FBFFFFH
SA1 (64 KByes)
2FFFFH
FAFFFF H
SA0 (64 KBytes)
1FFFFH
F9FFFFH
0FFFFH
00000H
F8FFFFH
F80000H
MB90F394H(A)
Unused
*: Always use the programmer address when writing/erasing the Flash memory using
a parallel programmer.
558
CHAPTER 28 3M-BIT FLASH MEMORY
28.3
Write/Erase Modes
The flash memory can be accessed in two different ways: Flash memory mode and
alternative mode. Flash memory mode enables data to be directly written to or erased
from the external pins. Alternative mode enables data to be written to or erased from
the CPU via the internal bus. Use the mode external pins to select the mode.
■ Flash Memory Mode
The CPU stops when the mode pins are set to "111B" while the reset signal is asserted. The flash memory
interface circuit is connected directly to ports 0, 1, 2, 3, 4 and 5, enabling direct control from the external
pins. This mode makes the MCU seem like a standard flash memory to the external pins, and write/erase
can be performed using a flash memory programmer.
In flash memory mode, all operations supported by the flash memory automatic algorithm can be used.
■ Alternative Mode
The flash memory is located in the F8/F9 to FF banks in the CPU memory space, and like ordinary mask
ROM, can be read-accessed and program-accessed from the CPU via the flash memory interface circuit.
Since writing/erasing the flash memory is performed by instructions from the CPU via the flash memory
interface circuit, this mode allows rewriting even when the MCU is soldered on the target board.
Sector protect operations cannot be performed in these modes.
Note:
Writing/erasing the flash memory is not specified at all machine clock frequencies. Refer to the AC
Characteristics section of the data sheet.
■ Flash Memory Control Signals
Table 28.3-1 lists the flash memory control signals.
There is almost a one-to-one correspondence between the flash memory control signals and the external
pins of the MBM29LV200. The VID (12 V) pins required by the sector protect operations are MD0, MD1,
and MD2 instead of A9, RESET, and OE for the MBM29LV200.
In flash memory mode, the external data bus signal width is limited to 8 bits, enabling only one-byte
access. The DQ15 to DQ8 pins are not supported. The BYTE pin should always be set to "0".
559
CHAPTER 28 3M-BIT FLASH MEMORY
Table 28.3-1 Flash Memory Control Signals
MB90F394H(A)
MBM29LV200
Pin number
Normal function
Flash memory mode
1
P30
AQ16
A15
2
P31
CE
CE
3
P32
OE
OE
4
P33
WE
WE
5
P34
AQ17
A16
6
P35
AQ18
-
7
P36
BYTE
BYTE
8
P37
RY/BY
RY/BY
9 to 12
P40 to P43
AQ8 to AQ11
A7 to A10
18, 19
P46, P47
AQ12, AQ13
A11, A12
20, 21
P50, P51
AQ14, AQ15
A13, A14
89
MD0
MD0
A9 (VID)
88
MD1
MD1
RESET (VID)
87
MD2
MD2
OE (VID)
93 to 100
P00 to P07
DQ0 to DQ7
DQ0 to DQ7
101 to 104
P10 to P13
DQ8 to DQ11
DQ8 to DQ11
90
RST
RESET
RESET
109 to 112
P14 to P17
DQ12 to DQ15
DQ12 to DQ15
113 to 120
P20 to P27
AQ0 to AQ7
A-1, A0 to A6
Note: All port pins not mentioned above should be connected to VCC via a pull-up resistor.
560
CHAPTER 28 3M-BIT FLASH MEMORY
28.4
Flash Memory Control Status Register (FMCS)
The flash memory control status register (FMCS), together with the flash memory
interface circuit, is used to write data to and erase data from the flash memory.
■ Flash Memory Control Status Register (FMCS)
Figure 28.4-1 Flash Memory Control Status Register (FMCS)
7
6
5
4
3
INTE
RDYINT
WE
RDY
Reserved
(R/W)
(R/W)
(R/W)
(R)
(R/W)
bit
Address: 0000AE H
2
1
Reserved Reserved
(R/W)
(R/W)
0
Reserved
Initial value
000X0000B
(R/W)
● Explanation of bits
[bit7] INTE (interrupt enable)
This bit generates an interrupt to the CPU when flash memory write/erase terminates.
An interrupt to the CPU is generated when the INTE and RDYINT bits are "1". No interrupt is
generated when the INTE bit is "0".
•
"0": Disables interrupts when write/erase terminates.
•
"1": Enables interrupts when write/erase terminates.
[bit6] RDYINT (ready interrupt)
This bit indicates the operating state of the flash memory.
This bit is set to "1" when flash memory write/erase terminates. Data cannot be written to or erased
from the flash memory while this bit is "0" after a flash memory write/erase. Flash memory write/erase
is enabled when write/erase terminates and this bit is set to "1".
Writing "0" clears this bit to "0". Writing "1" is ignored. This bit is set to "1" at the termination timing
of the flash memory automatic algorithm (see Section "28.5 Starting the Flash Memory Automatic
Algorithm"). When the read-modify-write (RMW) instruction is used, "1" is always read.
•
"0": Write/erase is being executed.
•
"1": Write/erase has terminated (interrupt request generated).
[bit5] WE (write enable)
This bit enables writing to the flash memory area.
When this bit is "1", writing after the command sequence (see Section "28.5 Starting the Flash Memory
Automatic Algorithm") is issued to the F8 (F9) to FF bank writes to the flash memory area. When this
bit is "0", the write/erase signal is not generated. This bit is used when the flash memory Write/Erase
command is started.
If write/erase is not performed, it is recommended that this bit be set to "0" to prevent data from being
mistakenly written to the flash memory.
•
"0": Disables flash memory write/erase.
•
"1": Enables flash memory write/erase.
561
CHAPTER 28 3M-BIT FLASH MEMORY
[bit4] RDY (ready)
This bit enables flash memory write/erase.
Flash memory write/erase is disabled while this bit is "0".
However, Suspend commands, such as the Read/Reset command and Sector Erase Suspend command,
can be accepted even if this bit is "0".
•
"0": Write/erase is being executed.
•
"1": Write/erase has terminated (next data write/erase enabled).
[bit3 to bit0] Reserved bits
These bits are reserved for testing. During regular use, they should always be set to "0".
Note:
The RDYINT and RDY bits cannot be changed at the same time. Create a program so that decisions
are made using one or the other of these bits.
Figure 28.4-2 Transitions of the RDYINT and RDY Bits
Automatic algorithm
Te rmination timing
RDYINT bit
RDY bit
1 machine cycle
562
CHAPTER 28 3M-BIT FLASH MEMORY
28.5
Starting the Flash Memory Automatic Algorithm
Four types of commands are available for starting the flash memory automatic
algorithm: Read/Reset, Write, and Chip Erase. Control of suspend and restart is enabled
for sector erase.
■ Command Sequence Table
Table 28.5-1 lists the command sequence table. All of the data written to the command register is in bytes,
but use word access to write. The data of the high-order bytes at this time is ignored.
Table 28.5-1 Command Sequence Table
Command
sequence
1st bus write
cycle
Bus
write
access
2nd bus write cycle
3rd bus write cycle
4th bus write cycle
5th bus write cycle
6th bus write cycle
Address
Data
Address
Data
Address
Data
Address
Data
Address
Data
Address
Data
Read/Reset *
1
FxXXXX
XXF0
-
-
-
-
-
-
-
-
-
-
Read/Reset *
4
FxAAAA
XXAA
Fx5554
XX55
FxAAAA
XXF0
RA
RD
-
-
-
-
Write program
4
FxAAAA
XXAA
Fx5554
XX55
FxAAAA
XXA0
PA
(even)
PD
(word)
-
-
-
-
Chip Erase
6
FxAAAA
XXAA
Fx5554
XX55
FxAAAA
XX80
FxAAAA
XXAA
Fx5554
XX55
FxAAAA
XX10
Sector Erase
6
FxAAAA
XXAA
Fx5554
XX55
FxAAAA
XX80
FxAAAA
XXAA
Fx5554
XX55
SA
(even)
XX30
-
-
Sector Erase Suspend
Entering address FxXXXX data (xxB0H) suspends erasing during sector erase.
Sector Erase Restart
Entering address FxXXXX data (xx30H) restarts erasing after erasing is suspended during sector erase.
Auto-select
3
FxAAAA
XXAA
Fx5554
XX55
FxAAAA
XX90
-
-
-
-
*: Both of the two types of Read/Reset commands can reset the flash memory to read mode.
Notes:
• The addresses Fx in the table mean FF, FE, FD, FB, FA and F9 for 3M-bit Flash Memory. Use
these addresses as the access target bank values for operations.
• The addresses in the table are the values in the CPU memory map. All addresses and data are
represented using hexadecimal notation. However, the letter "X" is an optional value.
• RA: Read address
• PA: Write address. Only even addresses can be specified.
• SA: Sector address. See Section "28.2 Block Diagram of the Entire Flash Memory and Sector
Configuration of the Flash Memory".
• RD: Read data
• PD: Write data. Only word data can be specified.
563
CHAPTER 28 3M-BIT FLASH MEMORY
The Auto-select command shown in Table 28.5-1 is used to know the state of sector protection. When
using the Auto-select command, set the address as follows.
Table 28.5-2 Address Setting at Auto-select
Sector protection
AQ13 to AQ18
AQ7
AQ2
AQ1
AQ0
DQ7 to DQ0
Sector Address
L
H
L
L
CODE*
*: When the sector address is protected, the output is "01H".
When the sector address is not protected, the output is "00H".
564
CHAPTER 28 3M-BIT FLASH MEMORY
28.6
Confirming the Automatic Algorithm Execution State
Because the write/erase flow of the flash memory is controlled using the automatic
algorithm, the flash memory has hardware for posting its internal operating state and
completion of operation. This automatic algorithm enables confirmation of the
operating state of the built-in flash memory using the following hardware sequences.
■ Hardware Sequence Flags
The hardware sequence flags are configured from the five-bit output of DQ7, DQ6, DQ5, DQ3 and DQ2.
The functions of these bits are those of the data polling flag (DQ7), toggle bit flag (DQ6), timing limit
exceeded flag (DQ5), sector erase timer flag (DQ3) and toggle bit-2 flag (DQ2). The hardware sequence
flags can therefore be used to confirm that writing or chip sector erase has been completed or that erase
code write is valid.
The hardware sequence flags can be accessed by read-accessing the addresses of the target sectors in the
flash memory after setting of the command sequence (see Table 28.5-1 in Section "28.5 Starting the Flash
Memory Automatic Algorithm".) Table 28.6-1 lists the bit assignments of the hardware sequence flags.
Table 28.6-1 Bit Assignments of Hardware Sequence Flags
Bit No.
7
6
5
4
3
2
1
0
Hardware sequence flag
DQ7
DQ6
DQ5
-
DQ3
DQ2
-
-
To determine whether automatic writing or chip sector erase is being executed, the hardware sequence flags
can be checked or the status can be determined from the RDY bit of the flash memory control status
register (FMCS) that indicates whether writing has been completed. After writing/erasing has terminated,
the state returns to the read/reset state. When creating a program, use one of the flags to confirm that
automatic writing/erasing has terminated. Then, perform the next processing operation, such as data read.
In addition, the hardware sequence flags can be used to confirm whether the second or subsequent sector
erase code write is valid. The following sections describe each hardware sequence flag separately. Table
28.6-2 lists the functions of the hardware sequence flags.
565
CHAPTER 28 3M-BIT FLASH MEMORY
Table 28.6-2 Hardware Sequence Flag Functions
State
DQ7
DQ6
DQ5
DQ3
DQ2
DQ7 →
DATA:7
Toggle →
DATA:6
0→
DATA:5
0→
DATA:3
1→
DATA:2
0→1
Toggle →
Stop
0→1
1
Toggle →
Stop
0
Toggle
0
0→1
Toggle
Erase → Sector erase suspended (sector
being erased)
0→1
Toggle → 1
0
1→0
Toggle
Sector erase suspend → Erase restarted
(sector being erased)
1→0
1 → Toggle
0
0→1
Toggle
DATA:7
DATA:6
DATA:5
DATA:3
DATA:2
DQ7
Toggle
1
0
1
0
Toggle
1
1
*
Write → Write completed (write
address specified)
Chip/sector erase → Erase completed
State
change for
normal
operation
Sector erase wait → Erase started
Sector erase suspended (sector not
being erased)
Abnormal
operation
Write
Chip/sector erase
*: If the DQ5 outputs "1" (exceed the timing limit), successive reads from a writing or erasing sector cause DQ2 to
toggle. DQ2 does not toggle when the successive reads are executed from other sectors.
566
CHAPTER 28 3M-BIT FLASH MEMORY
28.6.1
Data Polling Flag (DQ7)
The data polling flag (DQ7) uses the data polling function to post that the automatic
algorithm is being executed or has terminated
■ Data Polling Flag (DQ7)
Table 28.6-3 lists the data polling flag state transitions (state change for normal operation) and Table 28.6-4
lists the data polling flag state transitions (state change for abnormal operation).
Table 28.6-3 Data Polling Flag State Transitions (State Change for Normal Operation)
Operating
state
Write →
Completed
DQ7 →
DATA:7
DQ7
Chip/sector
erase →
Completed
Sector
erase wait
→ Started
0→1
0
Sector erase
→ Erase
suspend
(sector being
erased)
0→1
Sector erase
suspend →
Restarted
(sector being
erased)
1→0
Sector erase
suspended
(sector not
being erased)
DATA:7
Table 28.6-4 Data Polling Flag State Transitions (State Change for Abnormal Operation)
Operating state
Write
Chip/sector erase
DQ7
DQ7
0
● Write
Read-access during execution of the automatic write algorithm causes the flash memory to output the
opposite data of bit7 last written, regardless of the value at the address specified by the address signal.
Read-access at the end of the automatic write algorithm causes the flash memory to output bit7 of the read
value of the address specified by the address signal.
● Chip/sector erase
For a sector erase, read-access during execution of the chip erase/sector erase algorithm causes the flash
memory to output 0 from the sector currently being erased. For a chip erase, read-access causes the flash
memory to output 0 regardless of the value at the address specified by the address signal. Read-access at
the end of the automatic write algorithm causes the flash memory to output 1 in the same way.
567
CHAPTER 28 3M-BIT FLASH MEMORY
● Sector erase suspend
Read-access during a sector erase suspend causes the flash memory to output 1 if the address specified by
the address signal belongs to the sector being erased. The flash memory outputs bit7 (DATA: 7) of the read
value at the address specified by the address signal if the address specified by the address signal does not
belong to the sector being erased. Referencing this flag together with the toggle bit flag (DQ6) enables a
decision to be made on whether the flash memory is in the erase suspended state and which sector is being
erased.
Note:
When the automatic algorithm is being started, read-access to the specified address is ignored.
Since termination of the data polling flag (DQ7) can be accepted for a data read and other bits
output, data read after the automatic algorithm has terminated should be performed after readaccess has confirmed that data polling has terminated.
568
CHAPTER 28 3M-BIT FLASH MEMORY
28.6.2
Toggle Bit Flag (DQ6)
Like the data polling flag, the toggle bit flag (DQ6) uses the toggle bit function to post
that the automatic algorithm is being executed or has terminated.
■ Toggle Bit Flag (DQ6)
Table 28.6-5 lists the toggle bit flag state transitions (state change for normal operation) and Table 28.6-6
lists the toggle bit flag state transitions (state change for abnormal operation).
Table 28.6-5 Toggle Bit Flag State Transitions (State Change for Normal Operation)
Operating
state
Write →
Completed
Chip/sector
erase →
Completed
DQ6
Toggle →
DATA:6
Toggle →
Stop
Sector
erase wait
→ Started
Toggle
Sector erase
→ Erase
suspend
(sector being
erased)
Sector erase
suspend →
Restarted
(sector being
erased)
Toggle → 1
1 → Toggle
Sector erase
suspended
(sector not
being erased)
DATA:6
Table 28.6-6 Toggle Bit Flag State Transitions (State Change for Abnormal Operation)
Operating state
Write
Chip/sector erase
DQ6
Toggle
Toggle
● Write/chip sector erase
Continuous read-access during execution of the automatic write algorithm and chip/sector erase algorithm
causes the flash memory to toggle the "1" or "0" state for every read cycle, regardless of the value at the
address specified by the address signal. Continuous read-access at the end of the automatic write algorithm
and chip/sector erase algorithm causes the flash memory to stop toggling bit6 and output bit6 (DATA: 6) of
the read value of the address specified by the address signal.
● Sector erase suspend
Read-access during a sector erase suspend causes the flash memory to output "1" if the address specified by
the address signal belongs to the sector being erased. The flash memory outputs bit6 (DATA: 6) of the read
value at the address specified by the address signal if the address specified by the address signal does not
belong to the sector being erased.
Note:
For a write, if the sector where data is to be written is rewrite-protected, the toggle bit terminates the
toggle operation after approximately 2μs without any data being rewritten. For an erase, if all of the
selected sectors are write-protected, the toggle bit performs toggling for approximately 100μs and
then returns to the read/reset state without any data being rewritten.
569
CHAPTER 28 3M-BIT FLASH MEMORY
28.6.3
Timing Limit Exceeded Flag (DQ5)
The timing limit exceeded flag (DQ5) is used to post that execution of the automatic
algorithm has exceeded the time (internal pulse count) prescribed in the flash memory.
■ Timing Limit Exceeded Flag (DQ5)
Table 28.6-7 lists the timing limit exceeded flag state transitions (state change for normal operation) and
Table 28.6-8 lists the timing limit exceeded flag state transitions (state change for abnormal operation).
Table 28.6-7 Timing Limit Exceeded Flag State Transitions (State Change for Normal Operation)
Operating
state
Write →
Completed
Chip/sector
erase →
Completed
DQ5
0→
DATA:5
0→1
Sector
erase wait
→ Started
0
Sector erase
→ Erase
suspend
(sector being
erased)
0
Sector erase
suspend →
Restarted
(sector being
erased)
0
Sector erase
suspended
(sector not
being erased)
DATA:5
Table 28.6-8 Timing Limit Exceeded Bit Flag State Transitions (State Change for Abnormal
Operation)
Operating state
Write
Chip/sector erase
DQ5
1
1
● Write/chip sector erase
Read-access after write or chip/sector erase automatic algorithm activation causes the flash memory to
output "0" if the time is within the prescribed time (time required for write/erase) or to output "1" if the
prescribed time has been exceeded. Because this is done regardless of whether the automatic algorithm is
being executed or has terminated, it is possible to determine whether write/erase was successful or
unsuccessful. That is, when this flag outputs "1", writing can be determined to have been unsuccessful if
the automatic algorithm is still being executed by the data polling function or toggle bit function.
For example, writing "1" to a flash memory address where "0" has been written will cause the fail state to
occur. In this case, the flash memory will lock and execution of the automatic algorithm will not terminate.
As a result, valid data will not be output from the data polling flag (DQ7). In addition, the toggle bit flag
(DQ6) will exceed the time limit without stopping the toggle operation and the timing limit exceeded flag
(DQ5) will output "1". Note that this state indicates that the flash memory is not faulty, but has been used
correctly. When this state occurs, execute the Reset command.
570
CHAPTER 28 3M-BIT FLASH MEMORY
28.6.4
Sector Erase Timer Flag (DQ3)
The sector erase timer flag (DQ3) is used to post whether the automatic algorithm is
being executed during the sector erase wait period after the Sector Erase command has
been started.
■ Sector Erase Timer Flag (DQ3)
Table 28.6-9 lists the sector erase timer flag state transitions (state change for normal operation) and Table
28.6-10 lists the sector erase timer flag state transitions (state change for abnormal operation).
Table 28.6-9 Sector Erase Timer Flag State Transitions (State Change for Normal Operation)
Operating
state
Write →
Completed
Chip/sector
erase →
Completed
DQ3
0→
DATA:3
1
Sector
erase wait
→ Started
0→1
Sector erase
→ Erase
suspend
(sector being
erased)
1→0
Sector erase
suspend →
Restarted
(sector being
erased)
0→1
Sector erase
suspended
(sector not
being erased)
DATA:3
Table 28.6-10 Sector Erase Timer Flag State Transitions (State Change for Abnormal
Operation)
Operating state
Write
Chip/sector erase
DQ3
0
1
● Sector erase
Read-access after the Sector Erase command has been started causes the flash memory to output "0" if the
automatic algorithm is being executed during the sector erase wait period, regardless of the value at the
address specified by the address signal of the sector that issued the command. The flash memory outputs
"1" if the sector erase wait period has been exceeded.
If the data polling function or toggle bit function indicates that the erase algorithm is being executed,
internally controlled erase has already started if this flag is "1". Continuous write of the sector erase codes
or commands other than the Sector Erase Suspend command will be ignored until erase is terminated.
If this flag is "0", the flash memory will accept write of additional sector erase codes. To confirm this, it is
recommended that the state of this flag be checked before continuing to write sector erase codes. If this flag
is "1" after the second state check, it is possible that additional sector erase codes may not be accepted.
571
CHAPTER 28 3M-BIT FLASH MEMORY
● Read access during sector erase
Read-access during execution of sector erase suspend causes the flash memory to output "1" if the address
specified by the address signal belongs to the sector being erased. If this address does not belong to the
sector being erased, the flash memory outputs bit3 (DATA:3) of the corresponding memory value.
572
CHAPTER 28 3M-BIT FLASH MEMORY
28.6.5
Toggle Bit-2 Flag (DQ2)
The toggle bit-2 flag (DQ2) is a flag that uses the toggle bit function to indicate that the
sector is in the erase-suspended state.
■ Toggle Bit-2 Flag (DQ2)
Table 28.6-11 lists the toggle bit-2 flag state transitions (state change for normal operation) and Table 28.612 lists the toggle bit-2 flag state transitions (state change for abnormal operation).
Table 28.6-11 Toggle Bit-2 Flag State Transitions (State Change for Normal Operation)
Operating
state
Write →
Completed
Chip/sector
erase →
Completed
DQ2
1→
DATA:2
Toggle →
Stop
Sector
erase wait
→ Started
Toggle
Sector erase
→ Erase
suspend
(sector being
erased)
Toggle
Sector erase
suspend →
Restarted
(sector being
erased)
Toggle
Sector erase
suspended
(sector not
being erased)
DATA:2
Table 28.6-12 Toggle Bit-2 Flag State Transitions (State Change for Abnormal Operation)
Operating state
Write
Chip/sector erase
DQ2
1
*
*: If the DQ5 outputs "1" (exceed the timing limit), successive reads from a writing or erasing sector cause DQ2
to toggle. DQ2 does not toggle when the successive reads are executed from other sectors.
● During a sector erase operation
If successive reads are executed during the execution of the chip sector erase algorithm, a flash memory
toggles to output "1" and "0" to addresses alternately at every read access regardless of the location
indicated by the addresses. If successive reads are executed after the chip sector erase algorithm is
completed, the flash memory stops the toggle operation of the bit2 and outputs the read value of the bit2
(DATA: 2) to the location indicated by the address.
573
CHAPTER 28 3M-BIT FLASH MEMORY
● While a sector erase operation is suspended
If successive reads are executed while a sector erase operation is suspended, and if the address indicates the
sector to be erased, the flash memory toggles to alternately output "1" and "0". If the address indicates the
sector is not to be erased, the flash memory outputs the read value of the bit2 (DATA: 2) to the location
indicated by the address. In the erase-suspend-program mode, successive reads from the non-erase
suspended sector causes the flash memory to output "1".
Both DQ2 and DQ6 are used for detecting an erase-suspended sector (DQ2 toggles, but DQ6 does not).
DQ2 is also used for detecting an erasing sector. While erasing a sector, if a read access is executed from
the erasing sector, DQ2 toggles.
Reference:
If all sectors selected for erasing are write-protected, the toggle bit-2 toggles for about 100μs, and then
returns to the read/reset mode without writing the data.
574
CHAPTER 28 3M-BIT FLASH MEMORY
28.7
Detailed Explanation of Writing to and Erasing Flash
Memory
This section describes each operation procedure of flash memory Read/Reset, Write,
Chip Erase, Sector Erase, Sector Erase Suspend, and Sector Erase Restart when a
command that starts the automatic algorithm is issued.
■ Detailed Explanation of Flash Memory Write/Erase
The flash memory executes the automatic algorithm by issuing a command sequence (see Table 28.5-1 in
Section "28.5 Starting the Flash Memory Automatic Algorithm") for a write cycle to the bus to perform
Read/Reset, Write, Chip Erase, Sector Erase, Sector Erase Suspend, or Sector Erase Restart operations.
Each bus write cycle must be performed continuously. In addition, whether the automatic algorithm has
terminated can be determined using the data polling or other function. At normal termination, the flash
memory is returned to the read/reset state.
Each operation of the flash memory is described in the following order:
•
Setting the read/reset state
•
Writing data
•
Erasing all data (erasing chips)
•
Erasing optional data (erasing sectors)
•
Suspending sector erase
•
Restarting sector erase
575
CHAPTER 28 3M-BIT FLASH MEMORY
28.7.1
Setting The Read/Reset State
This section describes the procedure for issuing the Read/Reset command to set the
flash memory to the read/reset state.
■ Setting the Flash Memory to the Read/Reset State
The flash memory can be set to the read/reset state by sending the Read/Reset command in the command
sequence table (see Table 28.5-1 in Section "28.5 Starting the Flash Memory Automatic Algorithm")
continuously to the target sector in the flash memory.
The Read/Reset command has two types of command sequences that execute the first and third bus
operations. However, there are no essential differences between these command sequences.
The read/reset state is the initial state of the flash memory. When the power is turned on and when a
command terminates normally, the flash memory is set to the read/reset state. In the read/reset state, other
commands wait for input.
In the read/reset state, data is read by regular read-access. As with the mask ROM, program access from the
CPU is enabled. The Read/Reset command is not required to read data by a regular read. The Read/Reset
command is mainly used to initialize the automatic algorithm in such cases as when a command does not
terminate normally.
576
CHAPTER 28 3M-BIT FLASH MEMORY
28.7.2
Writing Data
This section describes the procedure for issuing the Write command to write data to the
flash memory.
■ Writing Data to the Flash Memory
The data write automatic algorithm of the flash memory can be started by sending the Write command in
the command sequence table (see Table 28.5-1 in Section "28.5 Starting the Flash Memory Automatic
Algorithm") continuously to the target sector in the flash memory. When data write to the target address is
completed in the fourth cycle, the automatic algorithm and automatic write are started.
● Specifying addresses
Only even addresses can be specified as the write addresses specified in a write data cycle. Odd addresses
cannot be written correctly. That is, writing to even addresses must be done in units of word data.
Writing can be done in any order of addresses or even if the sector boundary is exceeded. However, the
Write command writes only data of one word for each execution.
● Notes on writing data
Writing cannot return data "0" to data "1". When data "1" is written to data "0", the data polling algorithm
(DQ7) or toggle operation (DQ6) does not terminate and the flash memory elements are determined to be
faulty. If the time prescribed for writing is thus exceeded, the timing limit exceeded flag (DQ5) is
determined to be an error. Otherwise, the data is viewed as if dummy data "1" had been written. However,
when data is read in the read/reset state, the data remains "0". Data "0" can be set to data "1" only by erase
operations.
All commands are ignored during execution of the automatic write algorithm. If a hardware reset is started
during writing, the data of the written addresses will be unpredictable.
■ Writing to the Flash Memory
Figure 28.7-1 shows the example of the flash memory write procedure. The hardware sequence flags (see
Section "28.6 Confirming the Automatic Algorithm Execution State") can be used to determine the state of
the automatic algorithm in the flash memory. Here, the data polling flag (DQ7) is used to confirm that
writing has terminated.
The data read to check the flag is read from the address written to last.
The data polling flag (DQ7) changes at the same time that the timing limit exceeded flag (DQ5) changes.
For example, even if the timing limit exceeded flag (DQ5) is "1", the data polling flag bit (DQ7) must be
rechecked.
Also for the toggle bit flag (DQ6), the toggle operation stops at the same time that the timing limit
exceeded flag bit (DQ5) changes to "1". The toggle bit flag (DQ6) must therefore be rechecked.
577
CHAPTER 28 3M-BIT FLASH MEMORY
Figure 28.7-1 Example of the Flash Memory Write Procedure
Start writing
FMCS: WE (bit 5)
Enable flash memory write
Write command sequence
(1) FxAAAA <-- XXAA
(2) Fx5554 <-- XX55
(3) FxAAAA <-- XXA0
(4) Write address <-- Write data
Read internal address
Data polling (DQ7)
Next address
Data
Data
0
Timing limit (DQ5)
1
Read internal address
Data
Data polling (DQ7)
Data
Write error
Final address
FMCS: WE (bit 5)
Disable flash memory write
Complete writing
578
Confirm with the hardware
sequence flags.
CHAPTER 28 3M-BIT FLASH MEMORY
28.7.3
Erasing All Data (Erasing Chips)
This section describes the procedure for issuing the Chip Erase command to erase all
data in the flash memory.
■ Erasing All Data in the Flash Memory (Erasing Chips)
All data can be erased from the flash memory by sending the Chip Erase command in the command
sequence table (see Table 28.5-1 in Section "28.5 Starting the Flash Memory Automatic Algorithm")
continuously to the target sector in the flash memory.
The Chip Erase command is executed in six bus operations. When writing of the sixth cycle is completed,
the chip erase operation is started. For chip erase, the user need not write to the flash memory before
erasing. During execution of the automatic erase algorithm, the flash memory writes "0" for verification
before all of the cells are erased automatically.
579
CHAPTER 28 3M-BIT FLASH MEMORY
28.7.4
Erasing Optional Data (Erasing Sectors)
This section describes the procedure for issuing the Sector Erase command to erase
optional data (erase sector) in the flash memory. Individual sectors can be erased.
Multiple sectors can also be specified at one time.
■ Erasing Optional Data (Erasing Sectors) in the Flash Memory
Optional sectors in the flash memory can be erased by sending the Sector Erase command in the command
sequence table (see Table 28.5-1 in Section "28.5 Starting the Flash Memory Automatic Algorithm")
continuously to the target sector in the flash memory.
● Specifying sectors
The Sector Erase command is executed in six bus operations. Sector erase wait of 50μs is started by writing
the sector erase code (30H) to an accessible even-numbered address in the target sector in the sixth cycle.
To erase multiple sectors, write the erase code (30H) to the addresses in the target sectors after the above
processing operation.
● Notes on specifying multiple sectors
Erase is started when the sector erase wait period of 50μs terminates after the final sector erase code has
been written. That is, to erase multiple sectors at one time, an erase code (sixth cycle of the command
sequence) must be written within 50μs of writing of the address of a sector and the address of the next
sector must be written within 50μs of writing of the previous erase code. Otherwise, the address and erase
code may not be accepted. The sector erase timer (hardware sequence flag DQ3) can be used to check
whether writing of the subsequent sector erase code is valid. At this time, specify so that the address used
for reading the sector erase timer indicates the sector to be erased.
■ Erasing Sectors in the Flash Memory
The hardware sequence flags (see Section "28.6 Confirming the Automatic Algorithm Execution State")
can be used to determine the state of the automatic algorithm in the flash memory. Figure 28.7-2 shows the
example of the flash memory sector erase procedure. Here, the toggle bit flag (DQ6) is used to confirm that
erasing has terminated.
The data that is read to check the flag is read from the sector to be erased.
The toggle bit flag (DQ6) stops the toggle operation at the same time that the timing limit exceeded flag
(DQ5) is changed to "1". For example, even if the timing limit exceeded flag (DQ5) is "1", the toggle bit
flag (DQ6) must be rechecked.
The data polling flag (DQ7) also changes at the same time that the timing limit exceeded flag bit (DQ5)
changes. As a result, the data polling flag (DQ7) must be rechecked.
580
CHAPTER 28 3M-BIT FLASH MEMORY
Figure 28.7-2 Example of the Flash Memory Sector Erase Procedure
Start erasing
FMCS: WE (bit 5)
Enable flash memory erase
Erase command sequence
(1) FxAAAA <-- XXAA
(2) Fx5554 <-- XX55
(3) FxAAAA <-- XX80
(4) FxAAAA <-- XXAA
(5) Fx5554 <-- XX55
1
Sector erase timer (DQ3)
Read internal address
0
(6) Enter code to erase sector
(30H)
YES
Another erase sector
NO
Read internal address 1
Next sector
Read internal address 2
Toggle bit (DQ6)
data 1(DQ6) = data 2(DQ6)
YES
NO
0
Timing limit (DQ5)
1
Read internal address 1
Read internal address 2
NO
Toggle bit (DQ6)
data 1(DQ6) = data 2(DQ6)
YES
Erase error
Final sector
NO
YES
FMCS: WE (bit 5)
Disable flash memory erase
Confirm with the hardware
sequence flags.
Complete erasing
581
CHAPTER 28 3M-BIT FLASH MEMORY
28.7.5
Suspending Sector Erase
This section describes the procedure for issuing the Sector Erase Suspend command
to suspend erasing of flash memory sectors. Data can be read from sectors that are not
being erased.
■ Suspending Erasing of Flash Memory Sectors
Erasing of flash memory sectors can be suspended by sending the Sector Erase Suspend command in the
command sequence table (see Table 28.5-1 in Section "28.5 Starting the Flash Memory Automatic
Algorithm") continuously to the target sector in the flash memory.
The Sector Erase Suspend command suspends the sector erase operation being executed and enables data to
be read from sectors that are not being erased. In this state, only reading is enabled; data cannot be written.
This command is valid only during sector erase operations that include the erase wait time. The command
will be ignored during chip erase or write operations.
This command is implemented by writing the erase suspend code (B0H). At this time, specify an optional
address in the flash memory for the address. An Erase Suspend command issued again during erasing of
sectors will be ignored.
Entering the Sector Erase Suspend command during the sector erase wait period will immediately terminate
sector erase wait, cancel the erase operation, and set the erase stop state. Entering the Erase Suspend
command during the erase operation after the sector erase wait period has terminated will set the erase
suspend state after a maximum period of 20μs has elapsed. Sector Erase Suspend command should be
entered more than 20μs after Sector Erase command or Sector Erase Restart command is issued.
582
CHAPTER 28 3M-BIT FLASH MEMORY
28.7.6
Restarting Sector Erase
This section describes the procedure for issuing the Sector Erase Restart command to
restart suspended erasing of flash memory sectors.
■ Restarting Erasing of Flash Memory Sectors
Suspended erasing of flash memory sectors can be restarted by sending the Sector Erase Restart command
in the command sequence table (see Table 28.5-1 in Section "28.5 Starting the Flash Memory Automatic
Algorithm") continuously to the target sector in the flash memory.
The Sector Erase Restart command is used to restart erasing of sectors from the sector erase suspend state
set using the Sector Erase Suspend command. The Sector Erase Restart command is implemented by
writing the erase restart code (30H). At this time, specify an optional address in the flash memory area for
the address.
If a Sector Erase Restart command is issued during sector erase, the command will be ignored.
583
CHAPTER 28 3M-BIT FLASH MEMORY
28.8
Notes on using 3M-bit Flash Memory
This section contains notes on using 3M-bit flash memory.
■ Notes on Using Flash Memory
● Input of a hardware reset (RST)
To input a hardware reset when the automatic algorithm has not been started and reading is in progress, a
minimum low-level width of 500 ns must be maintained. In this case, a maximum of 500 ns is required
until data can be read from the flash memory after a hardware reset has been activated.
Similarly, to input a hardware reset when the automatic algorithm has been activated and writing or erasing
is in progress, a minimum low-level width of 500 ns must be maintained. In this case, 20 ns are required
until data can be read after the operation for initializing the flash memory has terminated.
A hardware reset during writing may cause the data being written to be undefined. A hardware reset during
erasing and, power supply cut-off may make the sector being erased unusable.
● Canceling of a software reset and watchdog timer reset
When the flash memory is being written to or erased with CPU access and if reset conditions occur while
the automatic algorithm is active, the CPU may run out of control. This occurs because these reset
conditions cause the automatic algorithm to continue without initializing the flash memory unit, possibly
preventing the flash memory unit from entering the read state when the CPU starts the sequence after the
reset has been deasserted. These reset conditions must be disabled during writing to or erasing of the flash
memory.
● Program access to flash memory
When the automatic algorithm is operating, read access to the flash memory is disabled. With the memory
access mode of the CPU set to built-in ROM mode, writing or erasing must be started after the program
area is switched to another area such as RAM.
In this case, when sectors (SA8/SA13) containing interrupt vectors are erased or written to, interrupt
processing cannot be executed. For the same reason, all interrupt sources other than the flash memory must
be disabled while the automatic algorithm is operating.
● Hold function
When the CPU accepts a hold request, the Write signal WE of the flash memory unit may be skewed,
causing erroneous writing or erasing due to an erroneous write. When the acceptance of a hold request is
enabled (HDE bit of EPCR set to "1"), ensure that the WE bit of the control status register (FMCS) is "0".
● Extended intelligent I/O service (EI2OS)
Because write and erase interrupts issued to the CPU from the flash memory interface circuit cannot be
accepted by the EI2OS, they should not be used.
584
CHAPTER 28 3M-BIT FLASH MEMORY
● Applying VID
Applying VID required for the sector protect operation should always be started and terminated when the
supply voltage is ON.
585
CHAPTER 28 3M-BIT FLASH MEMORY
28.9
Reset Vector Address in Flash Memory
The MB90F394H(A) support a hard-wired reset vector.
When the addresses "FFFFDCH" to "FFFFDFH" are accessed for reading data in internal
vector mode, the values that have been determined by the hard-wired logic in advance
are read. However, in flash memory mode, as mentioned in the previous chapter, all
addresses can be accessed.
Consequently, it is meaningless to write data to these addresses. Especially when
programming flash memory from the CPU (that is, not in flash memory mode), do not
read these addresses for software polling. Otherwise, the flash memory returns a fixed
reset vector instead of the hardware sequence flag value.
■ Reset Vector Address in Flash Memory
Table 28.9-1 lists the reset vector and mode data values.
Table 28.9-1 Reset Vector and Mode Data Values
Reset vector
FFA000H
Mode data
00H
Note:
Because of the hard-wired reset vector, it is not necessary to specify the reset vector in the software.
However it is recommended to specify the same vector and the same mode data in the program, this
will prevent the Mask ROM device to behave differently from the Flash device when the same
program is used.
586
CHAPTER 28 3M-BIT FLASH MEMORY
28.10
Example of Programming 3M-bit Flash Memory
This section presents a programming example of 3M-bit flash memory.
■ Programming Example of 3M-bit Flash Memory
Flash Memory Sample Program
NAME
FLASHWE
TITLE FLASHWE
;------------------------------------------------------------------------------;3M-bit-Flash test program
;
;1: Transmits the program (address: FF8000H, sector: SA6) from Flash to RAM
;
(address: 001500H).
;2: Executes the program on RAM.
;3: Writes the PDR1 value to Flash (address: F90000H, sector: SA1).
;4: Reads the written value (address: F90000H, sector: SA1) and outputs it to PDR2.
;5: Erases the written sector (SA1).
;6: Checks and outputs erase data.
;Conditions
; - Number of bytes transmitted to RAM: 100H (256B)
; - Write/erase termination judgment
;
Judgment according to DQ5 (timing limit excess flag)
;
Judgment according to DQ6 (toggle bit flag)
;
Judgment according to RDY (FMCS)
; - Error handling
;
“H” output to P00 to P07
;
Reset command issuance
;------------------------------------------------------------------;
RESOUS IOSEG
ABS=00
;"RESOUS" I/O segment definition
ORG
0000H
PDR0
RB
1
PDR1
RB
1
PDR2
RB
1
PDR3
RB
1
ORG
0010H
DDR0
RB
1
DDR1
RB
1
DDR2
RB
1
DDR3
RB
1
ORG
00A1H
CKSCR
RB
1
ORG
00AEH
FMCS
RB
1
ORG
006FH
ROMM
RB
1
RESOUS ENDS
;
SSTA
SSEG
RW
0127H
STA_T
RW
1
SSTA
ENDS
;
DATA
DSEG
ABS=0FFH
;Flash command address
ORG
5554H
COMADR2 RW
1
ORG
0AAAAH
COMADR1 RW
1
DATA
ENDS
587
CHAPTER 28 3M-BIT FLASH MEMORY
;/////////////////////////////////////////////////////////////
;Main program (FFA000H)
;/////////////////////////////////////////////////////////////
CODE
CSEG
START:
;
/////////////////////////////////////////////////////
;
Initialization
;
/////////////////////////////////////////////////////
MOV
CKSCR,#0BAH
;3-multiple setting
MOV
RP,#0
MOV
A,#!STA_T
MOV
SSB,A
MOVW
A,#STA_T
MOVW
SP,A
MOV
ROMM,#00H
;Mirror OFF
MOV
PDR0,#00H
;For error check
MOV
DDR0,#0FFH
MOV
PDR1,#00H
;Port for data input
MOV
DDR1,#00H
MOV
PDR2,#00H
;Port for data output
MOV
DDR2,#0FFH
;
//////////////////////////////////////////////////////////////
;
Transfer of "Flash write erase program (FF8000H)" to RAM (1500H address)
;
//////////////////////////////////////////////////////////////
MOVW
A,#1500H
;Transfer destination RAM area
MOVW
A,#08000H
;Transfer source address (program position)
MOVW
RW0,#100H
;Number of bytes to be transferred
MOVS
ADB,PCB
;Transfer of 100H from FF8000H to 001500H
CALLP
001500H
;Jump to the address containing the transferred
;
program
;
/////////////////////////////////////////////////////
;
Data output
;
/////////////////////////////////////////////////////
OUT
MOV
A,#0F9H
MOV
ADB,A
MOVW
RW2,#0000H
MOVW
A,@RW2+00
MOV
PDR2,A
END
JMP
*
CODE
ENDS
;////////////////////////////////////////////////////////////
;Flash write erase program (SA6)
;////////////////////////////////////////////////////////////
RAMPRG CSEG
ABS=0FFH
ORG
0BC00H
;
////////////////////////////////////////////
Initialization
;
////////////////////////////////////////////
MOVW
RW0,#0500H
;RW0:RAM space for input data acquisition
From 00:0500
MOVW
RW2,#0000H
;RW2:Flash memory write address
From F9:0000
MOV
A,#00H
;DTB modification
MOV
DTB,A
;Bank specification for @RW0
MOV
A,#0F9H
;ADB modification 1
MOV
ADB,A
;Bank specification for write mode specification
;
address
MOV
PDR3,#00H
;Switch initialization
MOV
DDR3,#00H
;
WAIT1
BBC
PDR3:0,WAIT1
;PDR3: 0(write start at high level)
;
588
CHAPTER 28 3M-BIT FLASH MEMORY
;////////////////////////////////////////////////
;Write (SA1)
;////////////////////////////////////////////////
MOV
A,PDR1
MOVW
@RW0+00,A
;PDR1 data allocation to RAM
MOV
FMCS,#20H
;Write mode setting
MOVW
ADB:COMADR1,#00AAH
;Flash write command 1
MOVW
ADB:COMADR2,#0055H
;Flash write command 2
MOVW
ADB:COMADR1,#00A0H
;Flash write command 3
;
MOVW
A,@RW0+00
;Input data (RW0) write to flash memory (RW2)
MOVW
@RW2+00,A
WRITE
;Wait time check
;
///////////////////////////////////////////////////////////////////
;
ERROR when the time limit excess check flag is set and toggle operation is
;
in progress
;
///////////////////////////////////////////////////////////////////
MOVW
A,@RW2+00
AND
A,#20H
;DQ5 time limit check
BZ
NTOW
;Time limit over
MOVW
A,@RW2+00
;AH
MOVW
A,@RW2+00
;AL
XORW
A
;XOR of AH and AL (1 when the values differ)
AND
A,#40H
;Is the DQ6 toggle bit different?
BNZ
ERROR
;To ERROR when the DQ6 toggle bit is different
;
///////////////////////////////////////
;
Write termination check (FMCS-RDY)
;
///////////////////////////////////////
;
///////////////////////////////////////
NTOW
MOVW
A,FMCS
AND
A,#10H
;Extraction of FMCS RDY bit (bit 4)
BZ
WRITE
;End of write?
MOV
FMCS,#00H
;Write mode release
;
/////////////////////////////////////////////////////
;
Write data output
;
/////////////////////////////////////////////////////
MOVW
RW2,#0000H
;Write data output
MOVW
A,@RW2+00
MOV
PDR2,A
;
WAIT2
BBC
PDR3:1,WAIT2
;PDR3: 1(sector erase start at “H” level)
;
;/////////////////////////////////////////////
;Sector erase (SA1)
;/////////////////////////////////////////////
MOV
@RW2+00,#0000H
;Address initialization
MOV
FMCS,#20H
;Erase mode setting
MOVW
ADB:COMADR1,#00AAH
;Flash erase command 1
MOVW
ADB:COMADR2,#0055H
;Flash erase command 2
MOVW
ADB:COMADR1,#0080H
;Flash erase command 3
MOVW
ADB:COMADR1,#00AAH
;Flash erase command 4
MOVW
ADB:COMADR2,#0055H
;Flash erase command 5
MOV
@RW2+00,#0030H
;Issuance of erase command 6 to the sector
to be erased
ELS
;Wait time check
;
///////////////////////////////////////////////////////////////////
;
ERROR when the time limit excess check flag is set and toggle operation is
;
in progress
;
///////////////////////////////////////////////////////////////////
MOVW
A,@RW2+00
AND
A,#20H
;DQ5 time limit check
BZ
NTOE
;Time limit over
MOVW
A,@RW2+00
;AH High and Low are alternately output from
MOVW
A,@RW2+00
;AL DQ6 per read during write operation.
XORW
A
;XOR of AH and AL (If the DQ6 value differs,
;
write operation is in progress (1)).
AND
A,#40H
;Is the DQ6 toggle bit High?
BNZ
ERROR
;ERROR when the DQ6 toggle bit is “H”
589
CHAPTER 28 3M-BIT FLASH MEMORY
;
;
;
NTOE
///////////////////////////////////////
Erase termination check (FMCS-RDY)
///////////////////////////////////////
MOVW
A,FMCS
;
AND
A,#10H
;Extraction of FMCS RDY bit (bit 4)
BZ
ELS
;End of sector erase?
MOV
FMCS,#00H
;Flash erase mode release
RETP
;Return to the main program
;//////////////////////////////////////////////
;Error
;//////////////////////////////////////////////
ERROR
MOV
FMCS,#00H
;Flash mode release
MOV
PDR0,#0FFH
;Error handling check
MOV
ADB:COMADR1,#0F0H
;Reset command (read is enabled)
RETP
;Return to the main program
RAMPRG ENDS
;/////////////////////////////////////////////
VECT
CSEG
ABS=0FFH
ORG
0FFDCH
DSL
START
DB
00H
VECT
ENDS
;
590
CHAPTER 29
EXAMPLES OF SERIAL
PROGRAMMING
CONNECTION
This chapter provides examples of F2MC-16LX
MB90F394H(A) serial programming connection.
29.1 Basic Configuration of MB90F394H(A) Serial Programming
Connection
29.2 Example of Serial Programming Connection
29.3 Example of Serial Programming Connection (Power Supplied From
the Programmer)
29.4 Example of Minimum Connection to the Flash Microcontroller
Programmer (User Power Supply Used)
29.5 Example of Minimum Connection to the Flash Microcontroller
Programmer (Power Supplied From the Programmer)
591
CHAPTER 29 EXAMPLES OF SERIAL PROGRAMMING CONNECTION
29.1
Basic Configuration of MB90F394H(A) Serial Programming
Connection
The MB90F394H(A) supports flash ROM serial onboard programming (Fujitsu standard).
This section describes the specifications.
■ Basic Configuration of MB90F394H(A) Serial Programming Connection
The AF220/AF210/AF120/AF110 flash microcontroller programmer from Yokogawa Digital Computer
Corporation is used for Fujitsu standard serial onboard programming.
Figure 29.1-1 Fujitsu Standard Serial Onboard Programming of MB90F394H(A)
Host interface cable (AZ201)
AF220/AF210/
AF120/AF110
flash
microcontroller
programmer
+
memory card
General-purpose
common cable (AZ210)
CLK synchronous serial
MB90F394H
Stand-alone operation enabled
Note:
Ask the company representative from Yokogawa Digital Computer Corporation for details about the
functions and operations of the AF220/AF210/AF120/AF110 flash microcontroller programmer,
general-purpose common cable for connection (AZ210), and connectors.
592
CHAPTER 29 EXAMPLES OF SERIAL PROGRAMMING CONNECTION
Table 29.1-1 Pins Used for Fujitsu Standard Serial Onboard Programming
Pin
Function
MD2, MD1
MD0
X0, X1
P00, P01
Additional information
Mode pins
Controls programming mode from the flash microcontroller
programmer.
Oscillation pins
In programming mode, the CPU internal operation clock signal is
one multiple of the PLL clock signal frequency. Therefore, because
the oscillation clock frequency becomes the internal operation clock
signal, the oscillator used for serial reprogramming is 3 MHz to 20
MHz.
programming activation pins
Input a low level to P00 and a High level to P01.
RST
Reset pin
SIN4
Serial data input pin
SOT4
Serial data output pin
SCK4
Serial clock signal input pin
-
Serial input-output is used.
C pin
This external capacitor pin is used to stabilize the power supply.
Connect a ceramic capacitor of approximately 0.1μF to the outside.
VCC
Power voltage supply pin
Programming voltage (5 V±10%)
VSS
GND pin
Common to the ground of the flash microcontroller programmer.
C
Even if the P00, P01, SIN4, SOT4, and SCK4 pins are used for the user system, the control circuit shown in
the figure below is required. The /TICS signal of the flash microcontroller programmer can be used to
disconnect the user circuit during serial programming.
Section "29.2 Example of Serial Programming Connection" present examples the following four types of
serial programming connection. See each Section as required.
•
Serial programming connection (user power supply used)
•
Serial programming connection (power supplied from the programmer)
•
Minimum connection to the flash microcontroller programmer (user power supply used)
•
Minimum connection to the flash microcontroller programmer (power supplied from the programmer)
593
CHAPTER 29 EXAMPLES OF SERIAL PROGRAMMING CONNECTION
Figure 29.1-2 Connecting User Circuitry for Serial Programming
AF220/AF210/
AF120/AF110
write control pin
MB90F394H
write control pin
10k
AF220/AF210/
AF120/AF110
/TICS pin
User circuit
Table 29.1-2 System Configuration of Flash Microcontroller Programmers (Manufactured by Yokogawa
Digital Computer Corporation)
Model
Main unit
Function
AF220/AC4P
Ethernet interface built-in model
100 to 220 V AC power adapter
AF210/AC4P
Standard model
100 to 220 V AC power adapter
AF120/AC4P
Single-key Ethernet interface built-in model
100 to 220 V AC power adapter
AF110/AC4P
Single-key model
100 to 220 V AC power adapter
AZ221
PC/AT RS232C cable for programmer
AZ210
Standard target probe (a) with a 1 m cable
FF201
Fujitsu F2MC-16LX flash microcontroller control module
AZ290
Remote controller
/P2
2 MBytes PC card (optional) for flash memory sizes up to 128 KBytes
/P4
4 MBytes PC card (optional) for flash memory sizes up to 512 KBytes
Inquiries: Yokogawa Digital Computer Corporation
Telephone number: (81)-42-333-6224
Note:
Although the AF200 flash microcontroller programmer is no longer manufactured, the programmer
still can be used in combination with the FF201 control module.
Examples of serial programming connection are given in Section "29.2
Programming Connection".
594
Example of Serial
CHAPTER 29 EXAMPLES OF SERIAL PROGRAMMING CONNECTION
■ Oscillating Clock Frequency and Serial Clock Input Frequency
The equation listed below can be used to calculate the serial clock frequencies that can be used for the
MB90F394H(A). Set an appropriate serial clock input frequency in the flash microcontroller programmer
according to the oscillating clock frequency in use.
fSC = 0.125 × fOSC
where fsc is the serial clock frequency and fosc is the oscillating clock frequency.
Table 29.1-3 Examples of Serial Clock Frequencies That can be Used
Oscillating clock
frequency
Maximum serial clock
frequency that can be
used for microcontroller
Maximum serial clock
frequency that can be
used for the AF220,
AF210, AF120, and
AF110
Maximum serial clock
frequency that can be
used for the AF200
4 MHz
500 kHz
500 kHz
500 kHz
8 MHz *
1 MHz
850 kHz
500 kHz
16 MHz *
2 MHz
1.25 MHz
500 kHz
*: External clock only.
595
CHAPTER 29 EXAMPLES OF SERIAL PROGRAMMING CONNECTION
29.2
Example of Serial Programming Connection
The value 1 and 0 are input to mode pins MD2 and MD0 from TAUX3 and TMODE of the
AF220/AF210/AF120/AF110 programmer.
Serial reprogramming mode: MD2, MD1, MD0 = 110B.
■ Example of Serial Programming Connection (User Power Supply Used)
Figure 29.2-1 shows the example of serial programming connection for MB90F394H(A) internal vector
modes (user power supply used).
Figure 29.2-1 Example of Serial Programming Connection for MB90F394H(A) Internal Vector Modes
(User Power Supply Used)
AF220/AF210/AF120/AF110
flash microcontroller
programmer
TAUX3
User system
MB90F394H
Connector
DX10-28S or DX20-28S
MD2
(19)
10k
10k
MD1
10k
TMODE
MD0
X0
(12)
X1
TAUX
P00
(23)
10k
/TICS
(10)
User circuit
10k
/TRES
RST
(5)
10k
User circuit
0.1 or more μF
TTXD
TRXD
TCK
TVcc
GND
(13)
(27)
(6)
SIN4
SOT4
SCK4
(2)
(7, 8,
14,15,
21, 22
1, 28)
P01
C
Vcc
User power
supply
Vss
Pin 14
Pins 3, 4, 9, 11, 16, 17, 18, 20,
24, 25, and 26 are open.
DX10-28S: Right-angle type
DX20-28S: Straight type
596
Pin 1
DX10-28S
DX20-28S
Pin 28
Pin 15
Connector (Hirose Electronics Ltd.)
pin arrangement
CHAPTER 29 EXAMPLES OF SERIAL PROGRAMMING CONNECTION
•
Even if the SIN4, SOT4, and SCK4 pins are used for the user system, the control circuit shown in the
figure below is required in the same way that it is for P00. The /TICS signal of the flash microcontroller
programmer can be used to disconnect the user circuit during serial programming.
•
Connect the AF220/AF210/AF120/AF110 while the user power is off.
Figure 29.2-2 Connecting User Circuitry (Detail)
AF220/AF210/
AF120/AF110
write control pin
MB90F394H
write control pin
10k
AF220/AF210/
AF120/AF110
/TICS pin
User circuit
597
CHAPTER 29 EXAMPLES OF SERIAL PROGRAMMING CONNECTION
29.3
Example of Serial Programming Connection
(Power Supplied From the Programmer)
The value 1 and 0 are input to mode pins MD2 and MD0 from TAUX3 and TMODE of the
AF220/AF210/AF120/AF110 programmer.
Serial reprogramming mode: MD2, MD1, MD0 = 110B.
■ Example of Serial Programming Connection (Power Supplied From the Programmer)
Figure 29.3-1 shows the example of serial programming connection for MB90F394H(A) internal vector
modes (power supplied from the programmer).
Figure 29.3-1 Example of Serial Programming Connection for MB90F394H(A) Internal Vector Modes
(Power Supplied From the Programmer)
AF220/AF210/AF120/AF110
flash microcontroller
programmer
TAUX3
User system
MB90F394H
Connector
DX10-28S or DX20-28S
MD2
(19)
10k
10k
MD1
10k
TMODE
MD0
X0
(12)
X1
TAUX
P00
(23)
10k
/TICS
(10)
User circuit
10k
/TRES
RST
(5)
10k
User circuit
0.1 or more μF
TTXD
TRXD
TCK
(13)
(27)
(6)
TVcc
(2)
GND
(7, 8,
14,15,
21, 22
1, 28)
P01
C
SIN4
SOT4
SCK4
User power
supply
Vcc
Vss
Pin 14
Pins 3, 4, 9, 11, 16, 17, 18, 20,
24, 25, and 26 are open.
DX10-28S: Right-angle type
DX20-28S: Straight type
598
Pin 1
DX10-28S
DX20-28S
Pin 28
Pin 15
Connector (Hirose Electronics Ltd.)
pin arrangement
CHAPTER 29 EXAMPLES OF SERIAL PROGRAMMING CONNECTION
•
Even if the SIN4, SOT4, and SCK4 pins are used for the user system, the control circuit shown in the
figure below is required in the same way that it is for P00. The /TICS signal of the flash microcontroller
programmer can be used to disconnect the user circuit during serial programming.
•
Connect the AF220/AF210/AF120/AF110 while the user power is off.
•
When the programming power is supplied from the AF220/AF210/AF120/AF110, be careful not to
short-circuit the user power supply.
Figure 29.3-2 Connecting User Circuitry (Detail)
AF220/AF210/
AF120/AF110
write control pin
MB90F394H
write control pin
10k
AF220/AF210/
AF120/AF110
/TICS pin
User circuit
599
CHAPTER 29 EXAMPLES OF SERIAL PROGRAMMING CONNECTION
29.4
Example of Minimum Connection to the Flash
Microcontroller Programmer (User Power Supply Used)
Figure 29.4-1 shows the example of minimum connection to the flash microcontroller
programmer (user power supply used).
Serial reprogramming mode: MD2, MD1, MD0 = 110B.
■ Example of Minimum Connection to the Flash Microcontroller Programmer
(User Power Supply Used)
For a flash memory write, the MD2, MD1, MD0, and P00 pins and flash microcontroller programmer need
not be connected if the pins are set as described below.
Figure 29.4-1 Example of Minimum Connection to the Flash Microcontroller Programmer
(User Power Supply Used)
AF220/AF210/AF120/AF110 User system
flash microcontroller
programmer
MB90F394H
1 for serial
reprogramming
10k
MD2
1 for serial
reprogramming
10k
10k
10k
10k
MD1
MD0
0 for serial
reprogramming
10k
X0
X1
P00
0 for serial 10k
reprogramming
10k
User circuit
P01
1 for serial reprogramming
User
circuit
C
Connector
DX10-28S or
DX20-28S
/TRES
TTXD
TRXD
TCK
TVcc
(5)
(13)
(27)
(6)
(2)
GND
(7, 8,
14,15,
21, 22,
1, 28)
10k
RST
SIN4
SOT4
SCK4
Vcc
User power supply
Pins 3, 4, 9, 10, 11, 12, 16, 17, 18, 19,
20, 23, 24, 25, and 26 are open.
DX10-28S: Right-angle type
DX20-28S: Straight type
600
Vss
Pin 14
Pin 1
Pin 28
Pin 15
DX10-28S
DX20-28S
Connector (Hirose Electronics Ltd.)
pin arrangement
CHAPTER 29 EXAMPLES OF SERIAL PROGRAMMING CONNECTION
•
Even if the SIN4, SOT4, and SCK4 pins are used for the user system, the control circuit shown in the
figure below is required. The /TICS signal of the flash microcontroller programmer can be used to
disconnect the user circuit during serial programming.
•
Connect the AF220/AF210/AF120/AF110 while the user power is off.
Figure 29.4-2 Connecting User Circuitry (Detail)
AF220/AF210/
AF120/AF110
write control pin
MB90F394H
write control pin
10k
AF220/AF210/
AF120/AF110
/TICS pin
User circuit
601
CHAPTER 29 EXAMPLES OF SERIAL PROGRAMMING CONNECTION
29.5
Example of Minimum Connection to the Flash
Microcontroller Programmer (Power Supplied From the
Programmer)
Figure 29.5-1 shows the example of minimum connection to the flash microcontroller
programmer (power supplied from the programmer).
Serial reprogramming mode: MD2, MD1, MD0 = 110B.
■ Example of Minimum Connection to the Flash Microcontroller Programmer (Power
Supplied From the Programmer)
For a flash memory write, the MD2, MD1, MD0, and P00 pins and flash microcontroller programmer need
not be connected if the pins are set as described below.
Figure 29.5-1 Example of Minimum Connection to the Flash Microcontroller Programmer
(Power Supplied From the Programmer)
AF220/AF210/AF120/AF110 User system
flash microcontroller
programmer
MB90F394H
1 for serial
reprogramming
MD2
1 for serial
reprogramming
MD1
MD0
0 for serial
reprogramming
X0
X1
P00
0 for serial
reprogramming
User circuit
P01
1 for serial reprogramming
User
circuit
C
Connector
DX10-28S or
DX20-28S
/TRES
TTXD
TRXD
TCK
(5)
(13)
(27)
(6)
(2)
(3)
(16)
RST
SIN4
SOT4
SCK4
Vcc
TVcc
GND
(7,8,
14,15,
21, 22,
1, 28)
Pins 4, 9, 10, 11, 12, 17, 18, 19,
20, 23, 24, 25, and 26 are open.
DX10-28S: Right-angle type
DX20-28S: Straight type
Vss
Pin 14
Pin 1
Pin 28
Pin 15
DX10-28S
DX20-28S
Connector (Hirose Electronics Ltd.)
pin arrangement
602
CHAPTER 29 EXAMPLES OF SERIAL PROGRAMMING CONNECTION
•
Even if the SIN4, SOT4, and SCK4 pins are used for the user system, the control circuit shown in the
figure below is required. The /TICS signal of the flash microcontroller programmer can be used to
disconnect the user circuit during serial programming.
•
Connect the AF220/AF210/AF120/AF110 while the user power is off.
•
When the programming power is supplied from the AF220/AF210/AF120/AF110, be careful not to
short-circuit the user power supply.
Figure 29.5-2 Connecting User Circuitry (Detail)
AF220/AF210/
AF120/AF110
write control pin
MB90F394H
write control pin
10k
AF220/AF210/
AF120/AF110
/TICS pin
User circuit
603
CHAPTER 29 EXAMPLES OF SERIAL PROGRAMMING CONNECTION
604
APPENDIX
The appendixes provide I/O maps, instructions, and
other information.
APPENDIX A I/O Maps
APPENDIX B Instructions
APPENDIX C Timing Diagrams in Flash Memory Mode
APPENDIX D List of Interrupt Vectors
605
APPENDIX
APPENDIX A I/O Maps
Table A-1 lists addresses to be assigned to the registers in the peripheral blocks.
■ I/O Maps
Table A-1 I/O Map (1/6)
Address
Register
Abbreviation
Access
Peripheral
Initial value
000000H
Port 0 data register
PDR0
R/W
Port 0
XXXXXXXXB
000001H
Port 1 data register
PDR1
R/W
Port 1
XXXXXXXXB
000002H
Port 2 data register
PDR2
R/W
Port 2
XXXXXXXXB
000003H
Port 3 data register
PDR3
R/W
Port 3
XXXXXXXXB
000004H
Port 4 data register
PDR4
R/W
Port 4
XXXXXXXXB
000005H
Port 5 data register
PDR5
R/W
Port 5
XXXXXXXXB
000006H
Port 6 data register
PDR6
R/W
Port 6
XXXXXXXXB
000007H
Port 7 data register
PDR7
R/W
Port 7
XXXXXXXXB
000008H
Port 8 data register
PDR8
R/W
Port 8
XXXXXXXXB
000009H
Port 9 data register
PDR9
R/W
Port 9
XXXXXXXXB
00000AH
Port A data register
PDRA
R/W
Port A
XXXXXXXXB
00000BH
Port B data register
PDRB
R/W
Port B
XXXXXXXXB
00000CH
Analog Input Enable 0
ADER0
R/W
Port 6, A/D
11111111B
00000DH
Analog Input Enable 1
ADER1
R/W
Port B, A/D
01111111B
00000EH
Input level select register
ILSR
R/W
Ports
00000000B
00000FH
Input level select register
ILSR
R/W
Ports
00000000B
000010H
Port 0 direction register
DDR0
R/W
Port 0
00000000B
000011H
Port 1 direction register
DDR1
R/W
Port 1
00000000B
000012H
Port 2 direction register
DDR2
R/W
Port 2
00000000B
000013H
Port 3 direction register
DDR3
R/W
Port 3
00000000B
000014H
Port 4 direction register
DDR4
R/W
Port 4
00000000B
000015H
Port 5 direction register
DDR5
R/W
Port 5
00000000B
000016H
Port 6 direction register
DDR6
R/W
Port 6
00000000B
606
APPENDIX A I/O Maps
Table A-1 I/O Map (2/6)
Address
Register
Abbreviation
Access
Peripheral
Initial value
000017H
Port 7 direction register
DDR7
R/W
Port 7
00000000B
000018H
Port 8 direction register
DDR8
R/W
Port 8
00000000B
000019H
Port 9 direction register
DDR9
R/W
Port 9
00000000B
00001AH
Port A direction register
DDRA
R/W
Port A
00000000B
00001BH
Port B direction register
DDRB
R/W
Port B
00000000B
00001CH to
00001FH
Reserved
000020H
Serial Mode Control 0
UMC0
R/W
00000100B
000021H
Status 0
USR0
R/W
00010000B
000022H
Input/Output Data 0
UIDR0/
UODR0
R/W
XXXXXXXXB
000023H
Rate and Data 0
URD0
R/W
0000000XB
000024H
Serial Mode Control 1
UMC1
R/W
00000100B
000025H
Status 1
USR1
R/W
00010000B
000026H
Input/Output Data 1
UIDR1/
UODR1
R/W
XXXXXXXXB
000027H
Rate and Data 1
URD1
R/W
0000000XB
000028H to
00002BH
UART0
UART1
Reserved
00002CH
Serial Mode Control
SMCS
R/W
00002DH
Serial Mode Control
SMCS
R/W
XXXX0000B
00000010B
Serial I/O
00002EH
Serial Data
00002FH
SDR
R/W
XXXXXXXXB
Serial I/O Prescaler
CDCR
R/W
0X0X0000B
000030H
External/DTP Enable Register
ENIR
R/W
00000000B
000031H
External Interrupt Request
EIRR
R/W
XXXXXXXXB
External Interrupt
000032H
External Interrupt Level
ELVR
R/W
00000000B
000033H
External Interrupt Level
ELVR
R/W
00000000B
607
APPENDIX
Table A-1 I/O Map (3/6)
Address
Register
Abbreviation
Access
000034H
A/D Control Status 0
ADCS0
R/W
000035H
A/D Control Status 1
ADCS1
R/W
Peripheral
Initial value
00000000B
00000000B
A/D Converter
000036H
A/D Data 0
ADCR0
R
XXXXXXXXB
000037H
A/D Data 1
ADCR1
R/W
00000XXXB
000038H
PPG0 operation mode control
register
PPGC0
R/W
0X000XX1B
000039H
PPG1 operation mode control
register
PPGC1
R/W
00003AH
PPG0 and PPG1 clock select
register
PPG01
R/W
00003BH
Program address detection control
status register 1
PACSR1
R/W
00003CH
PPG2 operation mode control
register
PPGC2
R/W
00003DH
PPG3 operation mode control
register
PPGC3
R/W
00003EH
PPG2/PPG3 clock control register
PPG23
R/W
00003FH
Clock Output Enable Register
CKOE
R/W
000040H
PPG4 operation mode control
register
PPGC4
R/W
000041H
PPG5 operation mode control
register
PPGC5
R/W
000042H
PPG4 and PPG5 clock select
register
PPG45
R/W
000043H
PPG6 operation mode control
register
PPGC6
R/W
000045H
PPG7 operation mode control
register
PPGC7
R/W
000046H
PPG6 and PPG7 clock select
register
PPG67
R/W
608
0X000001B
000000XXB
Program Address
Detection 1
00000000B
0X000XX1B
16-bit Programable
Pulse Generator 2/3
0X000001B
000000XXB
Clock Output
XXXXXX00B
0X000XX1B
16-bit Programable
Pulse Generator 4/5
0X000001B
000000XXB
Reserved
000044H
000047H
16-bit Programable
Pulse Generator 0/1
Reserved
0X000XX1B
16-bit Programable
Pulse Generator 6/7
0X000001B
000000XXB
APPENDIX A I/O Maps
Table A-1 I/O Map (4/6)
Address
Register
Abbreviation
Access
000048H
PPG8 operation mode control
register
PPGC8
R/W
000049H
PPG9 operation mode control
register
PPGC9
R/W
00004AH
PPG8 and PPG9 clock select
register
PPG89
R/W
00004BH
Initial value
0X000XX1B
16-bit Programable
Pulse Generator 8/9
0X000001B
000000XXB
Reserved
00004CH
PPGA operation mode control
register
PPGCA
R/W
00004DH
PPGB operation mode control
register
PPGCB
R/W
00004EH
PPGA and PPGB clock select
register
PPGAB
R/W
00004FH
000050H
Peripheral
0X000XX1B
16-bit Programable
Pulse Generator A/B
0X000001B
000000XXB
Reserved
Timer Control Status 0
TMCSR0
00000000B
R/W
16-bit Reload Timer 0
000051H
Timer Control Status 0
TMCSR0
R/W
000052H
Timer Control Status 1
TMCSR1
R/W
XXXX0000B
00000000B
16-bit Reload Timer 1
000053H
Timer Control Status 1
000054H
XXXX0000B
TMCSR1
R/W
Input Capture Control Status 0/1
ICS01
R/W
Input Capture 0/1
00000000B
000055H
Input Capture Control Status 2/3
ICS23
R/W
Input Capture 2/3
00000000B
000056H
Input Capture Control Status 4/5
ICS45
R/W
Input Capture 4/5
00000000B
000057H
000058H
Reserved
Output Compare Control Status 0
OCS0
0000XX00B
R/W
Output Compare 0/1
000059H
Output Compare Control Status 1
OCS1
R/W
00005AH
Output Compare Control Status 2
OCS2
R/W
0XX00000B
0000XX00B
Output Compare 2/3
00005BH
Output Compare Control Status 3
OCS3
R/W
00005CH
Output Compare Control Status 4
OCS4
R/W
0XX00000B
0000XX00B
Output Compare 4/5
00005DH
Output Compare Control Status 5
OCS5
R/W
00005EH
Sound Control
SGCR
R/W
0XX00000B
00000000B
Sound Generator
00005FH
Sound Control
SGCR
R/W
0XXXXX00B
609
APPENDIX
Table A-1 I/O Map (5/6)
Address
Register
000060H
Watch Timer Control
Abbreviation
Access
WTCR
R/W
Peripheral
Initial value
000XX000B
Watch Timer
000061H
Watch Timer Control
WTCR
R/W
000062H
PWM Control 0
PWC0
R/W
000063H
000064H
PWM Control 1
PWC1
PWM Control 2
PWC2
PWM Control 3
PWC3
PWM Control 4
PWC4
000070H to
00008FH
00000XX0B
R/W
Stepping Motor
Controller 2
00000XX0B
R/W
Stepping Motor
Controller 3
00000XX0B
R/W
Stepping Motor
Controller 4
00000XX0B
Stepping Motor
Controller 5
00000XX0B
ROM Mirror
XXXXXX+*1B
Reserved
PWM Control 5
PWC5
00006DH to
00006EH
00006FH
Stepping Motor
Controller 1
Reserved
00006BH
00006CH
R/W
Reserved
000069H
00006AH
00000XX0B
Reserved
000067H
000068H
Stepping Motor
Controller 0
Reserved
000065H
000066H
00000000B
R/W
Reserved
ROM Mirror
ROMM
W
Reserved for CAN Interface 0/1. Refer to section about CAN Controller
000090H to
00009DH
Reserved
00009EH
Program address detection control
status register 0
00009FH
Delayed Interrupt/release
0000A0H
Low-power Mode
PACSR0
R/W
Program Address
Detection 0
00000000B
DIRR
R/W
Delayed Interrupt
XXXXXXX0B
LPMCR
R/W
00011000B
Low Power Controller
0000A1H
Clock Selector
*: MB90V390H: Readable only. Fix to 1.
MB90F394H: Selectable. Initial value is 0.
610
CKSCR
R/W
11111100B
APPENDIX A I/O Maps
Table A-1 I/O Map (6/6)
Address
Register
Abbreviation
0000A2H to
0000A7H
Access
Peripheral
Initial value
Reserved
0000A8H
Watchdog Control
WDTC
R/W
Watchdog Timer
XXXXX111B
0000A9H
Time-Base Timer Control
TBTC
R/W
Time-Base Timer
1XX00100B
Flash Memory
000X0000B
0000AAH to
0000ADH
0000AEH
Reserved
Flash Control Status
(Flash devices only.
Otherwise reserved)
FMCS
0000AFH
R/W
Reserved
0000B0H
Interrupt control register 00
ICR00
R/W
00000111B
0000B1H
Interrupt control register 01
ICR01
R/W
00000111B
0000B2H
Interrupt control register 02
ICR02
R/W
00000111B
0000B3H
Interrupt control register 03
ICR03
R/W
00000111B
0000B4H
Interrupt control register 04
ICR04
R/W
00000111B
0000B5H
Interrupt control register 05
ICR05
R/W
00000111B
0000B6H
Interrupt control register 06
ICR06
R/W
00000111B
0000B7H
Interrupt control register 07
ICR07
R/W
00000111B
Interrupt controller
0000B8H
Interrupt control register 08
ICR08
R/W
00000111B
0000B9H
Interrupt control register 09
ICR09
R/W
00000111B
0000BAH
Interrupt control register 10
ICR10
R/W
00000111B
0000BBH
Interrupt control register 11
ICR11
R/W
00000111B
0000BCH
Interrupt control register 12
ICR12
R/W
00000111B
0000BDH
Interrupt control register 13
ICR13
R/W
00000111B
0000BEH
Interrupt control register 14
ICR14
R/W
00000111B
0000BFH
Interrupt control register 15
ICR15
R/W
00000111B
0000COH to
0000FFH
Reserved
611
APPENDIX
■ I/O Map (35XX Addresses)
Table A-2 I/O Map (35XX Addresses) (1/8)
Address
612
Register
Abbreviation
Access
Peripheral
Initial value
XXXXXXXXB
003500H
Reload L
PRLL0
R/W
003501H
Reload H
PRLH0
R/W
003502H
Reload L
PRLL1
R/W
003503H
Reload H
PRLH1
R/W
XXXXXXXXB
003504H
Reload L
PRLL2
R/W
XXXXXXXXB
003505H
Reload H
PRLH2
R/W
003506H
Reload L
PRLL3
R/W
003507H
Reload H
PRLH3
R/W
XXXXXXXXB
003508H
Reload L
PRLL4
R/W
XXXXXXXXB
003509H
Reload H
PRLH4
R/W
00350AH
Reload L
PRLL5
R/W
00350BH
Reload H
PRLH5
R/W
XXXXXXXXB
00350CH
Reload L
PRLL6
R/W
XXXXXXXXB
00350DH
Reload H
PRLH6
R/W
00350EH
Reload L
PRLL7
R/W
00350FH
Reload H
PRLH7
R/W
XXXXXXXXB
003510H
Reload L
PRLL8
R/W
XXXXXXXXB
003511H
Reload H
PRLH8
R/W
003512H
Reload L
PRLL9
R/W
003513H
Reload H
PRLH9
R/W
XXXXXXXXB
003514H
Reload L
PRLLA
R/W
XXXXXXXXB
003515H
Reload H
PRLHA
R/W
003516H
Reload L
PRLLB
R/W
003517H
Reload H
PRLHB
R/W
16-bit Programable
Pulse Generator 0/1
16-bit Programable
Pulse Generator 2/3
16-bit Programable
Pulse Generator 4/5
16-bit Programable
Pulse Generator 6/7
16-bit Programable
Pulse Generator 8/9
16-bit Programable
Pulse Generator A/B
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
APPENDIX A I/O Maps
Table A-2 I/O Map (35XX Addresses) (2/8)
Address
Register
Abbreviation
Access
Peripheral
Initial value
003518H
Serial Mode Register
SMR3
R/W
00000000B
003519H
Serial Control Register
SCR3
R/W
00000000B
00351AH
Reception/Transmission Data
Register
RDR3/TDR3
R/W
00000000B/
11111111B
00351BH
Serial Status Register
SSR3
R/W
00001000B
00351CH
Extended Communication
Control Reg.
ECCR3
R/W
00351DH
Extended Status/Control
Register
ESCR3
R/W
00000X00B
00351EH
Baud Rate Generator
Register 0
BGR03
R/W
00000000B
00351FH
Baud Rate Generator
Register 1
BGR13
R/W
00000000B
003520H
Input Capture 0
IPCP0
R
003521H
Input Capture 0
IPCP0
R
UART3
X0000XXXB
XXXXXXXXB
XXXXXXXXB
Input Capture 0/1
003522H
Input Capture 1
IPCP1
R
XXXXXXXXB
003523H
Input Capture 1
IPCP1
R
XXXXXXXXB
003524H
Input Capture 2
IPCP2
R
XXXXXXXXB
003525H
Input Capture 2
IPCP2
R
XXXXXXXXB
Input Capture 2/3
003526H
Input Capture 3
IPCP3
R
XXXXXXXXB
003527H
Input Capture 3
IPCP3
R
XXXXXXXXB
003528H
Input Capture 4
IPCP4
R
XXXXXXXXB
003529H
Input Capture 4
IPCP4
R
XXXXXXXXB
Input Capture 4/5
00352AH
Input Capture 5
IPCP5
R
XXXXXXXXB
00352BH
Input Capture 5
IPCP5
R
XXXXXXXXB
00352CH
Timer Data 0
TCDT0
R/W
00352DH
Timer Data 0
TCDT0
R/W
00000000B
00000000B
I/O Timer 0
00352EH
Timer Control 0
TCCSL0
R/W
00000000B
00352FH
Timer Control 0
TCCSH0
R/W
0XXXXXXXB
613
APPENDIX
Table A-2 I/O Map (35XX Addresses) (3/8)
Address
Register
Abbreviation
Access
003530H
Output Compare 0
OCCP0
R/W
003531H
Output Compare 0
OCCP0
R/W
Peripheral
Initial value
XXXXXXXXB
XXXXXXXXB
Output Compare 0/1
003532H
Output Compare 1
OCCP1
R/W
XXXXXXXXB
003533H
Output Compare 1
OCCP1
R/W
XXXXXXXXB
003534H
Output Compare 2
OCCP2
R/W
XXXXXXXXB
003535H
Output Compare 2
OCCP2
R/W
XXXXXXXXB
Output Compare 2/3
003536H
Output Compare 3
OCCP3
R/W
XXXXXXXXB
003537H
Output Compare 3
OCCP3
R/W
XXXXXXXXB
003538H
Output Compare 4
OCCP4
R/W
XXXXXXXXB
003539H
Output Compare 4
OCCP4
R/W
XXXXXXXXB
Output Compare 4/5
00353AH
Output Compare 5
OCCP5
R/W
XXXXXXXXB
00353BH
Output Compare 5
OCCP5
R/W
XXXXXXXXB
00353CH
Timer Data 1
TCDT1
R/W
00000000B
00353DH
Timer Data 1
TCDT1
R/W
00000000B
I/O Timer 1
00353EH
Timer Control 1
TCCSL1
R/W
00000000B
00353FH
Timer Control 1
TCCSH1
R/W
0XXXXXXXB
003540H
Timer 0/Reload 0
TMR0/
TMRLR0
R/W
XXXXXXXXB
003541H
Timer 0/Reload 0
TMR0/
TMRLR0
R/W
XXXXXXXXB
003542H
Timer 1/Reload 1
TMR1/
TMRLR1
R/W
XXXXXXXXB
Timer 1/Reload 1
TMR1/
TMRLR1
16-bit Reload Timer 0
16-bit Reload Timer 1
003543H
003544H,
003545H
XXXXXXXXB
R/W
Reserved
003546H
Frequency Data
SGFR
R/W
003547H
Amplitude Data
SGAR
R/W
XXXXXXXXB
XXXXXXXXB
Sound Generator
614
003548H
Decrement Grade
SGDR
R/W
XXXXXXXXB
003549H
Tone Count
SGTR
R/W
XXXXXXXXB
APPENDIX A I/O Maps
Table A-2 I/O Map (35XX Addresses) (4/8)
Address
Register
Abbreviation
Access
Peripheral
Initial value
00354AH
Sub-second Data
WTBR(0)
R/W
XXXXXXXXB
00354BH
Sub-second Data
WTBR(0)
R/W
XXXXXXXXB
00354CH
Sub-second Data
WTBR(1)
R/W
XXXXXXXXB
Watch Timer
00354DH
Second Data
WTSR
R/W
XXXXXXXXB
00354EH
Minute Data
WTMR
R/W
XXXXXXXXB
00354FH
Hour Data
WTHR
R/W
XXXXXXXXB
003550H
PWM1 Compare 0
PWC10
R/W
XXXXXXXXB
003551H
PWM2 Compare 0
PWC20
R/W
003552H
PWM1 Select 0
PWS10
R/W
003553H
PWM2 Select 0
PWS20
R/W
X0000000B
003554H
PWM1 Compare 1
PWC11
R/W
XXXXXXXXB
003555H
PWM2 Compare 1
PWC21
R/W
003556H
PWM1 Select 1
PWS11
R/W
003557H
PWM2 Select 1
PWS21
R/W
X0000000B
003558H
PWM1 Compare 2
PWC12
R/W
XXXXXXXXB
003559H
PWM2 Compare 2
PWC22
R/W
00355AH
PWM1 Select 2
PWS12
R/W
00355BH
PWM2 Select 2
PWS22
R/W
X0000000B
00355CH
PWM1 Compare 3
PWC13
R/W
XXXXXXXXB
00355DH
PWM2 Compare 3
PWC23
R/W
00355EH
PWM1 Select 3
PWS13
R/W
00355FH
PWM2 Select 3
PWS23
R/W
X0000000B
003560H
PWM1 Compare 4
PWC14
R/W
XXXXXXXXB
003561H
PWM2 Compare 4
PWC24
R/W
003562H
PWM1 Select 4
PWS14
R/W
003563H
PWM2 Select 4
PWS24
R/W
Stepping Motor
Controller 0
Stepping Motor
Controller 1
Stepping Motor
Controller 2
Stepping Motor
Controller 3
Stepping Motor
Controller 4
XXXXXXXXB
XX000000B
XXXXXXXXB
XX000000B
XXXXXXXXB
XX000000B
XXXXXXXXB
XX000000B
XXXXXXXXB
XX000000B
X0000000B
615
APPENDIX
Table A-2 I/O Map (35XX Addresses) (5/8)
Address
Abbreviation
Access
Peripheral
Initial value
003564H
PWM1 Compare 5
PWC15
R/W
003565H
PWM2 Compare 5
PWC25
R/W
003566H
PWM1 Select 5
PWS15
R/W
003567H
PWM2 Select 5
PWS25
R/W
X0000000B
003568H
Output Compare Control
Status 6
OCS6
R/W
0000XX00B
003569H
Output Compare Control
Status 7
OCS7
R/W
0XX00000B
00356AH
Output Compare 6
OCCP6
R/W
00356BH
Output Compare 6
OCCP6
R/W
XXXXXXXXB
00356CH
Output Compare 7
OCCP7
R/W
XXXXXXXXB
00356DH
Output Compare 7
OCCP7
R/W
XXXXXXXXB
00356EH
CAN Direct Mode Register
CDMR
R/W
CAN clock synch
XXXXXXX0B
00356FH
CAN2 RX/TX pin switching
register
CANSWR
R/W
CAN 0/1/2/3
XXXX0000B
003570H to
00359FH
XXXXXXXXB
Stepping Motor
Controller 5
Output Compare 6/7
XXXXXXXXB
XX000000B
XXXXXXXXB
Reserved for CAN Interface 2/3/4. Refer to section about CAN Controller
0035A0H
I2C bus status register
IBSR
R
00000000B
0035A1H
I2C bus control register
IBCR
R/W
00000000B
0035A2H
I2C ten bit slave address
register
ITBAL
R/W
00000000B
ITBAH
R/W
00000000B
ITMKL
R/W
11111111B
ITMKH
R/W
0035A3H
0035A4H
0035A5H
I2C ten bit address mask
register
I2C Interface
00111111B
0035A6H
I2C seven bit slave address
register
ISBA
R/W
00000000B
0035A7H
I2C seven bit address mask
register
ISMK
R/W
01111111B
0035A8H
I2C data register
IDAR
R/W
00000000B
0035A9H
I2C noise filter configuration
register *2
INFCR
R/W
XXXXXX01B
0035AAH
616
Register
Reserved
APPENDIX A I/O Maps
Table A-2 I/O Map (35XX Addresses) (6/8)
Address
0035ABH
Register
I2C clock control register
Abbreviation
ICCR
Access
R/W
0035ACH to
0035AFH
Reserved
0035B0H to
0035BFH
Reserved
0035C0H
Parameter Register Low Byte
CMPRL
R/W
0035C1H
Parameter Register High Byte
CMPRH
R/W
0035C2H
Clock Modulator Control
Register
CMCR
R/W
0035C3 to
0035C8H
Peripheral
I2C Interface
Initial value
00011111B
11111101B
Clock Modulator
XX000010B
0001X000B
Reserved
0035C9H
Input Capture Edge 0/1
ICE01
R/W
Input Capture 0/1
XXXXX0XXB
0035CAH
Input Capture Edge 2/3
ICE23
R
Input Capture 2/3
XXXXXXXXB
0035CBH
Input Capture Edge 4/5
ICE45
R/W
Input Capture 4/5
XXXXX0XXB
PLL
XXXX0000B
0035CCH to
0035CEH
0035CFH
Reserved
PLL and Special
Configuration Control
Register
PSCCR
0035D0H to
0035D7H
W
Reserved
0035D8H
Serial Mode Register
SMR2
R/W
00000000B
0035D9H
Serial Control Register
SCR2
R/W
00000000B
0035DAH
Reception/Transmission
Data Register
RDR2/TDR2
R/W
00000000B/
11111111B
0035DBH
Serial Status Register
SSR2
R/W
00001000B
0035DCH
Extended Communication
Control Register
ECCR2
R/W
0035DDH
Extended Status/Control
Register
ESCR2
R/W
00000X00B
0035DEH
Baud Rate Generator
Register 0
BGR02
R/W
00000000B
0035DFH
Baud Rate Generator
Register 1
BGR12
R/W
00000000B
UART2*1
X0000XXXB
617
APPENDIX
Table A-2 I/O Map (35XX Addresses) (7/8)
Address
Register
Abbreviation
Peripheral
Initial value
0035E0H
Program Address Detection
Register 0
PADR0
R/W
XXXXXXXXB
0035E1H
Program Address Detection
Register 0
PADR0
R/W
XXXXXXXXB
0035E2H
Program Address Detection
Register 0
PADR0
R/W
0035E3H
Program Address Detection
Register 1
PADR1
R/W
XXXXXXXXB
0035E4H
Program Address Detection
Register 1
PADR1
R/W
XXXXXXXXB
0035E5H
Program Address Detection
Register 1
PADR1
R/W
XXXXXXXXB
Address Match
Detection 0
0035E6H to
0035EFH
XXXXXXXXB
Reserved
0035F0H
Program Address Detection
Register 3
PADR3
R/W
XXXXXXXXB
0035F1H
Program Address Detection
Register 3
PADR3
R/W
XXXXXXXXB
0035F2H
Program Address Detection
Register 3
PADR3
R/W
XXXXXXXXB
0035F3H
Program Address Detection
Register 4
PADR4
R/W
XXXXXXXXB
0035F4H
Program Address Detection
Register 4
PADR4
R/W
0035F5H
Program Address Detection
Register 4
PADR4
R/W
XXXXXXXXB
0035F6H
Program Address Detection
Register 5
PADR5
R/W
XXXXXXXXB
0035F7H
Program Address Detection
Register 5
PADR5
R/W
XXXXXXXXB
0035F8H
Program Address Detection
Register 5
PADR5
R/W
XXXXXXXXB
0035F9H to
0035FFH
618
Access
Address Match
Detection 1
Reserved
003600H to
0036FFH
Reserved for CAN Interface 0. Refer to section about CAN Controller
003700H to
0037FFH
Reserved for CAN Interface 0. Refer to section about CAN Controller
XXXXXXXXB
APPENDIX A I/O Maps
Table A-2 I/O Map (35XX Addresses) (8/8)
Address
Register
Abbreviation
Access
Peripheral
003800H to
0038FFH
Reserved for CAN Interface 1. Refer to section about CAN Controller
003900H to
0039FFH
Reserved for CAN Interface 1. Refer to section about CAN Controller
003A00H to
003AFFH
Reserved for CAN Interface 2. Refer to section about CAN Controller
003B00H to
003BFFH
Reserved for CAN Interface 2. Refer to section about CAN Controller
003C00H to
003CFFH
Reserved for CAN Interface 3. Refer to section about CAN Controller
003D00H to
003DFFH
Reserved for CAN Interface 3. Refer to section about CAN Controller
003E00H to
003EFFH
Reserved for CAN Interface 4. Refer to section about CAN Controller
003F00H to
003FFFH
Reserved for CAN Interface 4. Refer to section about CAN Controller
Initial value
*1: UART2 is valid only in MB90V390HA and MB90V390HB.
*2: The I2C noise filter configuration register is valid only in MB90V390HA, MB90V390HB, and MB90394HA.
619
APPENDIX
• "X" indicates an undefined value.
• Any write access to reserved addresses in I/O map should not be performed.
A read access to reserved address results in reading "X".
● Explanation of write and read
R/W: Both read and write enabled
R:
Only read enabled
W:
Only write enabled
●Explanation of initial values
0: The initial value of this bit is "0".
1: The initial value of this bit is "1".
X: The initial value of this bit is undefined.
620
APPENDIX B Instructions
APPENDIX B Instructions
APPENDIX B describes the instructions used by the F2MC-16LX.
B.1 Instruction Types
B.2 Addressing
B.3 Direct Addressing
B.4 Indirect Addressing
B.5 Execution Cycle Count
B.6 Effective address field
B.7 How to Read the Instruction List
B.8 F2MC-16LX Instruction List
B.9 Instruction Map
Code: CM44-00202-1E
621
APPENDIX
B.1
Instruction Types
The F2MC-16LX supports 351 types of instructions. Addressing is enabled by using an
effective address field of each instruction or using the instruction code itself.
■ Instruction Types
The F2MC-16LX supports the following 351 types of instructions:
622
•
41 transfer instructions (byte)
•
38 transfer instructions (word or long word)
•
42 addition/subtraction instructions (byte, word, or long word)
•
12 increment/decrement instructions (byte, word, or long word)
•
11 comparison instructions (byte, word, or long word)
•
11 unsigned multiplication/division instructions (word or long word)
•
11 signed multiplication/division instructions (word or long word)
•
39 logic instructions (byte or word)
•
6 logic instructions (long word)
•
6 sign inversion instructions (byte or word)
•
1 normalization instruction (long word)
•
18 shift instructions (byte, word, or long word)
•
50 branch instructions
•
6 accumulator operation instructions (byte or word)
•
28 other control instructions (byte, word, or long word)
•
21 bit operation instructions
•
10 string instructions
APPENDIX B Instructions
B.2
Addressing
With the F2MC-16LX, the address format is determined by the instruction effective
address field or the instruction code itself (implied). When the address format is
determined by the instruction code itself, specify an address in accordance with the
instruction code used. Some instructions permit the user to select several types of
addressing.
■ Addressing
The F2MC-16LX supports the following 23 types of addressing:
•
Immediate (#imm)
•
Register direct
•
Direct branch address (addr16)
•
Physical direct branch address (addr24)
•
I/O direct (io)
•
Abbreviated direct address (dir)
•
Direct address (addr16)
•
I/O direct bit address (io:bp)
•
Abbreviated direct bit address (dir:bp)
•
Direct bit address (addr16:bp)
•
Vector address (#vct)
•
Register indirect (@RWj j = 0 to 3)
•
Register indirect with post increment (@RWj+ j = 0 to 3)
•
Register indirect with displacement (@RWi + disp8 i = 0 to 7, @RWj + disp16 j = 0 to 3)
•
Long register indirect with displacement (@RLi + disp8 i = 0 to 3)
•
Program counter indirect with displacement (@PC + disp16)
•
Register indirect with base index (@RW0 + RW7, @RW1 + RW7)
•
Program counter relative branch address (rel)
•
Register list (rlst)
•
Accumulator indirect (@A)
•
Accumulator indirect branch address (@A)
•
Indirectly-specified branch address (@ear)
•
Indirectly-specified branch address (@eam)
623
APPENDIX
■ Effective Address Field
Table B.2-1 lists the address formats specified by the effective address field.
Table B.2-1 Effective Address Field
Code
Representation
00
R0
RW0
RL0
01
R1
RW1
(RL0)
02
R2
RW2
RL1
03
R3
RW3
(RL1)
04
R4
RW4
RL2
05
R5
RW5
(RL2)
06
R6
RW6
RL3
07
R7
RW7
(RL3)
08
@RW0
09
@RW1
Address format
Default bank
Register direct: Individual parts correspond to the
byte, word, and long word types in order from the
left.
None
DTB
DTB
Register indirect
0A
@RW2
ADB
0B
@RW3
SPB
0C
@RW0+
DTB
0D
@RW1+
DTB
Register indirect with post increment
0E
@RW2+
ADB
0F
@RW3+
SPB
10
@RW0+disp8
DTB
11
@RW1+disp8
DTB
Register indirect with 8-bit displacement
12
@RW2+disp8
ADB
13
@RW3+disp8
SPB
14
@RW4+disp8
DTB
15
@RW5+disp8
DTB
Register indirect with 8-bit displacement
16
@RW6+disp8
ADB
17
@RW7+disp8
SPB
18
@RW0+disp16
DTB
19
@RW1+disp16
DTB
Register indirect with 16-bit displacement
624
1A
@RW2+disp16
ADB
1B
@RW3+disp16
SPB
1C
@RW0+RW7
Register indirect with index
DTB
1D
@RW1+RW7
Register indirect with index
DTB
1E
@PC+disp16
PC indirect with 16-bit displacement
PCB
1F
addr16
Direct address
DTB
APPENDIX B Instructions
B.3
Direct Addressing
An operand value, register, or address is specified explicitly in direct addressing mode.
■ Direct Addressing
● Immediate addressing (#imm)
Specify an operand value explicitly (#imm4/ #imm8/ #imm16/ #imm32).
Figure B.3-1 Example of Immediate Addressing (#imm)
MOVW A, #01212H (This instruction stores the operand value in A.)
Before execution
A 2233
4455
After execution
A 4455
1 2 1 2 (Some instructions transfer AL to AH.)
● Register direct addressing
Specify a register explicitly as an operand. Table B.3-1 lists the registers that can be specified. Figure B.3-2
shows an example of register direct addressing.
Table B.3-1 Direct Addressing Registers
General-purpose register
Special-purpose register
Byte
R0, R1, R2, R3, R4, R5, R6, R7
Word
RW0, RW1, RW2, RW3, RW4, RW5, RW6,
RW7
Long word
RL0, RL1, RL2, RL3
Accumulator
A, AL
Pointer
SP *
Bank
PCB, DTB, USB, SSB, ADB
Page
DPR
Control
PS, CCR, RP, ILM
*: One of the user stack pointer (USP) and system stack pointer (SSP) is selected and used depending on
the value of the S flag bit in the condition code register (CCR). For branch instructions, the program
counter (PC) is not specified in an instruction operand but is specified implicitly.
625
APPENDIX
Figure B.3-2 Example of Register Direct Addressing
MOV R0, A (This instruction transfers the eight low-order bits of A to the generalpurpose register R0.)
Before execution
A 0716
2534
Memory space
R0
After execution
A 0716
2564
??
Memory space
R0
34
● Direct branch addressing (addr16)
Specify an offset explicitly for the branch destination address. The size of the offset is 16 bits, which
indicates the branch destination in the logical address space. Direct branch addressing is used for an
unconditional branch, subroutine call, or software interrupt instruction. Bit23 to bit16 of the address are
specified by the program counter bank register (PCB).
Figure B.3-3 Example of Direct Branch Addressing (addr16)
JMP 3B20H (This instruction causes an unconditional branch by direct branch
addressing in a bank.)
Before execution
After execution
626
PC 3 C 2 0
PC 3 B 2 0
PCB 4 F
PCB 4 F
Memory space
4F3B20H
Next instruction
4F3C20H
62
4F3C21H
20
4F3C22H
3B
JMP 3B20H
APPENDIX B Instructions
● Physical direct branch addressing (addr24)
Specify an offset explicitly for the branch destination address. The size of the offset is 24 bits. Physical
direct branch addressing is used for unconditional branch, subroutine call, or software interrupt instruction.
Figure B.3-4 Example of Direct Branch Addressing (addr24)
JMPP 333B20H (This instruction causes an unconditional branch by direct branch 24-bit
addressing.)
Before execution
After execution
PC 3 C 2 0
PC 3 B 2 0
PCB 4 F
PCB 3 3
Memory space
333B20H
Next instruction
4F3C20H
63
4F3C21H
20
4F3C22H
3B
4F3C23H
33
JMPP 333B20H
● I/O direct addressing (io)
Specify an 8-bit offset explicitly for the memory address in an operand. The I/O address space in the
physical address space from 000000H to 0000FFH is accessed regardless of the data bank register (DTB)
and direct page register (DPR). A bank select prefix for bank addressing is invalid if specified before an
instruction using I/O direct addressing.
Figure B.3-5 Example of I/O Direct Addressing (io)
MOVW A, i : 0C0H (This instruction reads data by I/O direct addressing and stores it
in A.)
Before execution
After execution
A 0716
2534
Memory space
0000C0H
EE
0000C1H
FF
A 2534 FFEE
627
APPENDIX
● Abbreviated direct addressing (dir)
Specify the eight low-order bits of a memory address explicitly in an operand. Address bits 8 to 15 are
specified by the direct page register (DPR). Address bits 16 to 23 are specified by the data bank register
(DTB).
Figure B.3-6 Example of Abbreviated Direct Addressing (dir)
MOV S : 20H, A (This instruction writes the contents of the eight low-order bits of A in
abbreviated direct addressing mode.)
Before execution
A 4455
DPR 6 6
After execution
A 4455
DPR 6 6
1212
DTB 7 7
Memory space
776620H
1212
DTB 7 7
??
Memory space
776620H
12
● Direct addressing (addr16)
Specify the 16 low-order bits of a memory address explicitly in an operand. Address bits 16 to 23 are
specified by the data bank register (DTB). A prefix instruction for access space addressing is invalid for
this mode of addressing.
Figure B.3-7 Example of Direct Addressing (addr16)
MOVW A, 3B20H (This instruction reads data by direct addressing and stores it in A.)
Before execution
After execution
628
A 2020
A AABB
AABB
0123
DTB 5 5
DTB 5 5
Memory space
553B21H
01
553B20H
23
APPENDIX B Instructions
● I/O direct bit addressing (io:bp)
Specify bits in physical addresses 000000H to 0000FFH explicitly. Bit positions are indicated by ":bp",
where the larger number indicates the most significant bit (MSB) and the lower number indicates the least
significant bit (LSB).
Figure B.3-8 Example of I/O Direct Bit Addressing (io:bp)
SETB i : 0C1H : 0 (This instruction sets bits by I/O direct bit addressing.)
Memory space
Before execution
0000C1H
00
Memory space
After execution
0000C1H
01
● Abbreviated direct bit addressing (dir:bp)
Specify the eight low-order bits of a memory address explicitly in an operand. Address bits 8 to 15 are
specified by the direct page register (DPR). Address bits 16 to 23 are specified by the data bank register
(DTB). Bit positions are indicated by ":bp", where the larger number indicates the most significant bit
(MSB) and the lower number indicates the least significant bit (LSB).
Figure B.3-9 Example of Abbreviated Direct Bit Addressing (dir:bp)
SETB S : 10H : 0 (This instruction sets bits by abbreviated direct bit addressing.)
Memory space
Before execution
DTB 5 5
DPR 6 6
556610H
00
Memory space
After execution
DTB 5 5
DPR 6 6
556610H
01
● Direct bit addressing (addr16:bp)
Specify arbitrary bits in 64 kilobytes explicitly. Address bits 16 to 23 are specified by the data bank register
(DTB). Bit positions are indicated by ":bp", where the larger number indicates the most significant bit
(MSB) and the lower number indicates the least significant bit (LSB).
Figure B.3-10 Example of Direct Bit Addressing (addr16:bp)
SETB 2222H : 0 (This instruction sets bits by direct bit addressing.)
Memory space
Before execution
DTB 5 5
552222H
00
Memory space
After execution
DTB 5 5
552222H
01
629
APPENDIX
● Vector Addressing (#vct)
Specify vector data in an operand to indicate the branch destination address. There are two sizes for vector
numbers: 4 bits and 8 bits. Vector addressing is used for a subroutine call or software interrupt instruction.
Figure B.3-11 Example of Vector Addressing (#vct)
CALLV #15 (This instruction causes a branch to the address indicated by the interrupt
vector specified in an operand.)
Before execution
PC 0 0 0 0
Memory space
PCB F F
After execution
FFC000H
EF
FFFFE0H
00
FFFFE1H
D0
CALLV #15
PC D 0 0 0
PCB F F
Table B.3-2 CALLV Vector List
Instruction
Vector address L
Vector address H
CALLV #0
XXFFFEH
XXFFFFH
CALLV #1
XXFFFCH
XXFFFDH
CALLV #2
XXFFFAH
XXFFFBH
CALLV #3
XXFFF8H
XXFFF9H
CALLV #4
XXFFF6H
XXFFF7H
CALLV #5
XXFFF4H
XXFFF5H
CALLV #6
XXFFF2H
XXFFF3H
CALLV #7
XXFFF0H
XXFFF1H
CALLV #8
XXFFEEH
XXFFEFH
CALLV #9
XXFFECH
XXFFEDH
CALLV #10
XXFFEAH
XXFFEBH
CALLV #11
XXFFE8H
XXFFE9H
CALLV #12
XXFFE6H
XXFFE7H
CALLV #13
XXFFE4H
XXFFE5H
CALLV #14
XXFFE2H
XXFFE3H
CALLV #15
XXFFE0H
XXFFE1H
Note: A PCB register value is set in XX.
Note:
When the program counter bank register (PCB) is FFH, the vector area overlaps the vector area of
INT #vct8 (#0 to #7). Use vector addressing carefully (see Table B.3-2).
630
APPENDIX B Instructions
B.4
Indirect Addressing
In indirect addressing mode, an address is specified indirectly by the address data of an
operand.
■ Indirect Addressing
● Register indirect addressing (@RWj j = 0 to 3)
Memory is accessed using the contents of general-purpose register RWj as an address. Address bits 16 to
23 are indicated by the data bank register (DTB) when RW0 or RW1 is used, system stack bank register
(SSB) or user stack bank register (USB) when RW3 is used, or additional data bank register (ADB) when
RW2 is used.
Figure B.4-1 Example of Register Indirect Addressing (@RWj j = 0 to 3)
MOVW A, @RW1 (This instruction reads data by register indirect addressing and stores
it in A.)
Before execution
A 0716
2534
Memory space
RW1 D 3 0 F
After execution
DTB 7 8
78D30FH
EE
78D310H
FF
A 2534 FFEE
RW1 D 3 0 F
DTB 7 8
● Register indirect addressing with post increment (@RWj+ j = 0 to 3)
Memory is accessed using the contents of general-purpose register RWj as an address. After operand
operation, RWj is incremented by the operand size (1 for a byte, 2 for a word, or 4 for a long word).
Address bits 16 to 23 are indicated by the data bank register (DTB) when RW0 or RW1 is used, system
stack bank register (SSB) or user stack bank register (USB) when RW3 is used, or additional data bank
register (ADB) when RW2 is used.
If the post increment results in the address of the register that specifies the increment, the incremented
value is referenced after that. In this case, if the next instruction is a write instruction, priority is given to
writing by an instruction and, therefore, the register that would be incremented becomes write data.
631
APPENDIX
Figure B.4-2 Example of Register Indirect Addressing with Post Increment (@RWj+ j = 0 to 3)
MOVW A, @RW1+ (This instruction reads data by register indirect addressing with post
increment and stores it in A.)
Before execution
A 0716
2534
Memory space
RW1 D 3 0 F
After execution
DTB 7 8
78D30FH
EE
78D310H
FF
A 2534 FFEE
RW1 D 3 1 1
DTB 7 8
● Register indirect addressing with offset (@RWi + disp8 i = 0 to 7, @RWj + disp16 j = 0 to 3)
Memory is accessed using the address obtained by adding an offset to the contents of general-purpose
register RWj. Two types of offset, byte and word offsets, are used. They are added as signed numeric
values. Address bits 16 to 23 are indicated by the data bank register (DTB) when RW0, RW1, RW4, or
RW5 is used, system stack bank register (SSB) or user stack bank register (USB) when RW3 or RW7 is
used, or additional data bank register (ADB) when RW2 or RW6 is used.
Figure B.4-3 Example of Register Indirect Addressing with Offset
(@RWi + disp8 i = 0 to 7, @RWj + disp16 j = 0 to 3)
MOVW A, @RW1+10H (This instruction reads data by register indirect addressing with
an offset and stores it in A.)
Before execution
A 0716
2534
(+10H)
RW1 D 3 0 F
After execution
A 2534 FFEE
RW1 D 3 0 F
632
DTB 7 8
DTB 7 8
Memory space
78D31FH
EE
78D320H
FF
APPENDIX B Instructions
● Long register indirect addressing with offset (@RLi + disp8 i = 0 to 3)
Memory is accessed using the address that is the 24 low-order bits obtained by adding an offset to the
contents of general-purpose register RLi. The offset is 8-bits long and is added as a signed numeric value.
Figure B.4-4 Example of Long Register Indirect Addressing with Offset (@RLi + disp8 i = 0 to 3)
MOVW A, @RL2+25H (This instruction reads data by long register indirect addressing with
an offset and stores it in A.)
Before execution
A 0716
2534
(+25H)
RL2 F 3 8 2
After execution
4B02
Memory space
824B27H
EE
824B28H
FF
A 2534 FFEE
RL2 F 3 8 2
4B02
● Program counter indirect addressing with offset (@PC + disp16)
Memory is accessed using the address indicated by (instruction address + 4 + disp16). The offset is one
word long. Address bits 16 to 23 are specified by the program counter bank register (PCB). Note that the
operand address of each of the following instructions is not deemed to be (next instruction address +
disp16):
•
DBNZ eam, rel
•
DWBNZ eam, rel
•
CBNE eam, #imm8, rel
•
CWBNE eam, #imm16, rel
•
MOV eam, #imm8
•
MOVW eam, #imm16
Figure B.4-5 Example of Program Counter Indirect Addressing with Offset (@PC + disp16)
MOVW A, @PC+20H (This instruction reads data by program counter indirect
addressing with an offset and stores it in A.)
Before execution
A 0716
2534
Memory space
PCB C 5 PC 4 5 5 6
After execution
A 2534
FFEE
PCB C 5 PC 4 5 5 A
+4
C54556H
73
C54557H
9E
C54558H
20
C54559H
00
MOVW
A, @PC+20H
C5455AH
.
.
.
+20H
C5457AH
EE
C5457BH
FF
633
APPENDIX
● Register indirect addressing with base index (@RW0 + RW7, @RW1 + RW7)
Memory is accessed using the address determined by adding RW0 or RW1 to the contents of generalpurpose register RW7. Address bits 16 to 23 are indicated by the data bank register (DTB).
Figure B.4-6 Example of Register Indirect Addressing with Base Index (@RW0 + RW7, @RW1 + RW7)
MOVW A, @RW1+RW7 (This instruction reads data by register indirect addressing with
a base index and stores it in A.)
Before execution
A 0716
RW1 D 3 0 F
WR7 0 1 0 1
After execution
A 2534
RW1 D 3 0 F
WR7 0 1 0 1
634
2534
+
DTB 7 8
FFEE
DTB 7 8
Memory space
78D410H
EE
78D411H
FF
APPENDIX B Instructions
● Program counter relative branch addressing (rel)
The address of the branch destination is a value determined by adding an 8-bit offset to the program
counter (PC) value. If the result of addition exceeds 16 bits, bank register incrementing or decrementing is
not performed and the excess part is ignored, and therefore the address is contained within a 64-kilobyte
bank. This addressing is used for both conditional and unconditional branch instructions. Address bits 16 to
23 are indicated by the program counter bank register (PCB).
Figure B.4-7 Example of Program Counter Relative Branch Addressing (rel)
BRA 10H (This instruction causes an unconditional relative branch.)
Before execution
After execution
PC 3 C 2 0
PC 3 C 3 2
PCB 4 F
PCB 4 F
Memory space
4F3C32H
Next instruction
4F3C21H
10
4F3C20H
60
BRA 10H
● Register list (rlst)
Specify a register to be pushed onto or popped from a stack.
Figure B.4-8 Configuration of the Register List
MSB
LSB
RW7 RW6 RW5 RW4 RW3 RW2 RW1 RW0
A register is selected when the corresponding bit is 1 and deselected when the bit is 0.
635
APPENDIX
Figure B.4-9 Example of Register List (rlist)
POPW, RW0, RW4 (This instruction transfers memory data indicated by the SP to
multiple word registers indicated by the register list.)
SP
34FA
SP
34FE
RW0
×× ××
RW0
02 01
RW1
×× ××
RW1
×× ××
RW2
×× ××
RW2
×× ××
RW3
×× ××
RW3
×× ××
RW4
×× ××
RW4
04 03
RW5
×× ××
RW5
×× ××
RW6
×× ××
RW6
×× ××
RW7
×× ××
RW7
×× ××
Memory space
SP
Memory space
01
34FAH
01
34FAH
02
34FBH
02
34FBH
03
34FCH
03
34FCH
04
34FDH
04
34FDH
34FEH
SP
Before execution
34FEH
After execution
● Accumulator indirect addressing (@A)
Memory is accessed using the address indicated by the contents of the low-order bytes (16 bits) of the
accumulator (AL). Address bits 16 to 23 are specified by a mnemonic in the data bank register (DTB).
Figure B.4-10 Example of Accumulator Indirect Addressing (@A)
MOVW A, @A (This instruction reads data by accumulator indirect addressing and stores it in A.)
Before execution
A
0716
2534
DTB B B
After execution
A
0716
DTB B B
636
FFEE
Memory space
BB2534H
EE
BB2535H
FF
APPENDIX B Instructions
● Accumulator indirect branch addressing (@A)
The address of the branch destination is the content (16 bits) of the low-order bytes (AL) of the
accumulator. It indicates the branch destination in the bank address space. Address bits 16 to 23 are
specified by the program counter bank register (PCB). For the Jump Context (JCTX) instruction, however,
address bits 16 to 23 are specified by the data bank register (DTB). This addressing is used for
unconditional branch instructions.
Figure B.4-11 Example of Accumulator Indirect Branch Addressing (@A)
JMP @A (This instruction causes an unconditional branch by accumulator indirect
branch addressing.)
Before execution
PC 3 C 2 0
A 6677
After execution
PC 3 B 2 0
A 6677
PCB 4 F
3B20
Memory space
4F3B20H
Next instruction
4F3C20H
61
JMP @A
PCB 4 F
3B20
● Indirect specification branch addressing (@ear)
The address of the branch destination is the word data at the address indicated by ear.
Figure B.4-12 Example of Indirect Specification Branch Addressing (@ear)
JMP @@RW0 (This instruction causes an unconditional branch by register indirect
addressing.)
Before execution
After execution
PC 3 C 2 0
PCB 4 F
RW0 7 F 4 8
DTB 2 1
PC 3 B 2 0
PCB 4 F
RW0 7 F 4 8
DTB 2 1
Memory space
217F48H
20
217F49H
3B
4F3B20H
Next instruction
4F3C20H
73
4F3C21H
08
JMP @@RW0
637
APPENDIX
● Indirect specification branch addressing (@eam)
The address of the branch destination is the word data at the address indicated by eam.
Figure B.4-13 Example of Indirect Specification Branch Addressing (@eam)
JMP @RW0 (This instruction causes an unconditional branch by register indirect
addressing.)
Before execution
PC 3 C 2 0
PCB 4 F
RW0 3 B 2 0
After execution
PC 3 B 2 0
RW0 3 B 2 0
638
PCB 4 F
Memory space
4F3B20H
Next instruction
4F3C20H
73
4F3C21H
00
JMP @RW0
APPENDIX B Instructions
B.5
Execution Cycle Count
The number of cycles required for instruction execution (execution cycle count) is
obtained by adding the number of cycles required for each instruction, "correction
value" determined by the condition, and the number of cycles for instruction fetch.
■ Execution Cycle Count
The number of cycles required for instruction execution (execution cycle count) is obtained by adding the
number of cycles required for each instruction, "correction value" determined by the condition, and the
number of cycles for instruction fetch. In the mode of fetching an instruction from memory such as internal
ROM connected to a 16-bit bus, the program fetches the instruction being executed in word increments.
Therefore, intervening in data access increases the execution cycle count.
Similarly, in the mode of fetching an instruction from memory connected to an 8-bit external bus, the
program fetches every byte of an instruction being executed. Therefore, intervening in data access increases
the execution cycle count. In CPU intermittent operation mode, access to a general-purpose register,
internal ROM, internal RAM, internal I/O, or external data bus causes the clock to the CPU to halt for the
cycle count specified by the CG0 and CG1 bits of the low power consumption mode control register.
Therefore, for the cycle count required for instruction execution in CPU intermittent operation mode, add
the "access count x cycle count for the halt" as a correction value to the normal execution count.
639
APPENDIX
■ Calculating the Execution Cycle Count
Table B.5-1 lists execution cycle counts and Table B.5-2 and Table B.5-3 summarize correction value data.
Table B.5-1 Execution Cycle Counts in Each Addressing Mode
(a) *
Code
Operand
00
|
07
Ri
Rwi
RLi
08
|
0B
Execution cycle count in
each addressing mode
Register access count in
each addressing mode
See the instruction list.
See the instruction list.
@RWj
2
1
0C
|
0F
@RWj+
4
2
10
|
17
@RWi+disp8
2
1
18
|
1B
@RWi+disp16
2
1
1C
1D
1E
1F
@RW0+RW7
@RW1+RW7
@PC+disp16
addr16
4
4
2
1
2
2
0
0
*: (a) is used for ~ (cycle count) and B (correction value) in "B.8 F2MC-16LX Instruction List".
640
APPENDIX B Instructions
Table B.5-2 Cycle Count Correction Values for Counting Execution Cycles
(b) byte *
Operand
(c) word *
(d) long *
Cycle
count
Access
count
Cycle
count
Access
count
Cycle
count
Access
count
Internal register
+0
1
+0
1
+0
2
Internal memory
Even address
+0
1
+0
1
+0
2
Internal memory
Odd address
+0
1
+2
2
+4
4
External data bus
16-bit even address
+1
1
+1
1
+2
2
External data bus
16-bit odd address
+1
1
+4
2
+8
4
External data bus
8-bits
+1
1
+4
2
+8
4
*: (b), (c), and (d) are used for ~ (cycle count) and B (correction value) in "B.8 F2MC-16LX Instruction
List".
Note:
When an external data bus is used, the cycle counts during which an instruction is made to wait by
ready input or automatic ready must also be added.
Table B.5-3 Cycle Count Correction Values for Counting Instruction Fetch Cycles
Instruction
Byte boundary
Word boundary
Internal memory
-
+2
External data bus 16-bits
-
+3
External data bus 8-bits
+3
-
Notes:
• When an external data bus is used, the cycle counts during which an instruction is made to wait
by ready input or automatic ready must also be added.
• Actually, instruction execution is not delayed by every instruction fetch. Therefore, use the
correction values to calculate the worst case.
641
APPENDIX
B.6
Effective address field
Table B.6-1 shows the effective address field.
■ Effective Address Field
Table B.6-1 Effective Address Field
Code
Representation
00
01
02
03
04
05
06
07
08
09
0A
R0
R1
R2
R3
R4
R5
R6
R7
@RW0
@RW1
@RW2
RW0
RW1
RW2
RW3
RW4
RW5
RW6
RW7
0B
0C
0D
0E
0F
10
11
12
13
14
15
@RW3
@RW0+
@RW1+
@RW2+
@RW3+
@RW0+disp8
@RW1+disp8
@RW2+disp8
@RW3+disp8
@RW4+disp8
@RW5+disp8
RL0
(RL0)
RL1
(RL1)
RL2
(RL2)
RL3
(RL3)
Address format
Byte count of
extended
address part *
Register direct: Individual parts correspond to
the byte, word, and long word types in order
from the left.
-
Register indirect
0
Register indirect with post increment
0
Register indirect with 8-bit displacement
1
16
@RW6+disp8
17
@RW7+disp8
18
@RW0+disp16
19
@RW1+disp16
Register indirect with 16-bit displacement
2
1A
@RW2+disp16
1B
@RW3+disp16
1C
@RW0+RW7
Register indirect with index
0
1D
@RW1+RW7
Register indirect with index
0
1E
@PC+disp16
PC indirect with 16-bit displacement
2
1F
addr16
Direct address
2
*1: Each byte count of the extended address part applies to + in the # (byte count) column in "B.8 F2MC-16LX
Instruction List".
642
APPENDIX B Instructions
B.7
How to Read the Instruction List
Table B.7-1 describes the items used in "B.8 F2MC-16LX Instruction List", and Table
B.7-2 describes the symbols used in the same list.
■ Description of Instruction Presentation Items and Symbols
Table B.7-1 Description of Items in the Instruction List (1/2)
Item
Mnemonic
Description
Uppercase, symbol: Represented as is in the assembler.
Lowercase: Rewritten in the assembler.
Number of following lowercase: Indicates bit length in the instruction.
#
Indicates the number of bytes.
~
Indicates the number of cycles.
See Table B.2-1 for the alphabetical letters in items.
RG
B
Operation
Indicates the number of times a register access is performed during instruction
execution.
The number is used to calculate the correction value for CPU intermittent
operation.
Indicates the correction value used to calculate the actual number of cycles during
instruction execution.
The actual number of cycles during instruction execution can be determined by
adding the value in the ~ column to this value.
Indicates the instruction operation.
LH
Indicates the special operation for bit15 to bit08 of the accumulator.
Z: Transfers 0.
X: Transfers after sign extension.
-: No transfer
AH
Indicates the special operation for the 16 high-order bits of the accumulator.
*: Transfers from AL to AH.
-: No transfer
Z: Transfers 00 to AH.
X: Transfers 00H or FFH to AH after AL sign extension.
643
APPENDIX
Table B.7-1 Description of Items in the Instruction List (1/2)
Item
Description
I
Each indicates the state of each flag: I (interrupt enable), S (stack), T (sticky bit), N
(negative), Z (zero), V (overflow), C (carry).
*: Changes upon instruction execution.
-: No change
S: Set upon instruction execution.
R: Reset upon instruction execution.
S
T
N
Z
V
C
RMW
Indicates whether the instruction is a Read Modify Write instruction (reading data
from memory by the I instruction and writing the result to memory).
*: Read Modify Write instruction
-: Not Read Modify Write instruction
Note:
Cannot be used for an address that has different meanings between read and
write operations.
Table B.7-2 Explanation on Symbols in the Instruction List (1/2)
Symbol
A
644
Explanation
The bit length used varies depending on the 32-bit accumulator instruction.
Byte: Low-order 8 bits of byte AL
Word: 16 bits of word AL
Long word: 32 bits of AL and AH
AH
16 high-order bits of A
AL
16 low-order bits of A
SP
Stack pointer (USP or SSP)
PC
Program counter
PCB
program counter bank register
DTB
Data bank register
ADB
Additional data bank register
SSB
System stack bank register
USB
User stack bank register
SPB
Current stack bank register (SSB or USB)
DPR
Direct page register
brg1
DTB, ADB, SSB, USB, DPR, PCB, SPB
brg2
DTB, ADB, SSB, USB, DPR, SPB
APPENDIX B Instructions
Table B.7-2 Explanation on Symbols in the Instruction List (1/2)
Symbol
Ri
Explanation
R0, R1, R2, R3, R4, R5, R6, R7
RWi
RW0, RW1, RW2, RW3, RW4, RW5, RW6, RW7
RWj
RW0, RW1, RW2, RW3
RLi
RL0, RL1, RL2, RL3
dir
Abbreviated direct addressing
addr16
Direct addressing
addr24
Physical direct addressing
ad24 0-15
Bit0 to bit15 of addr24
ad24 16-23
Bit16 to bit23 of addr24
io
I/O area (000000H to 0000FFH)
#imm4
4-bit immediate data
#imm8
8-bit immediate data
#imm16
16-bit immediate data
#imm32
32-bit immediate data
ext (imm8)
16-bit data obtained by sign extension of 8-bit immediate data
disp8
8-bit displacement
disp16
16-bit displacement
bp
Bit offset
vct4
Vector number (0 to 15)
vct8
Vector number (0 to 255)
( )b
Bit address
rel
PC relative branch
ear
Effective addressing (code 00 to 07)
eam
Effective addressing (code 08 to 1F)
rlst
Register list
645
APPENDIX
B.8
F2MC-16LX Instruction List
Table B.8-1 to Table B.8-18 list the instructions used by the F2MC-16LX.
■ F2MC-16LX Instruction List
Table B.8-1 41 Transfer Instructions (Byte)
Mnemonic
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOVN
MOVX
MOVX
MOVX
MOVX
MOVX
MOVX
MOVX
MOVX
MOVX
MOVX
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
XCH
XCH
XCH
XCH
A,dir
A,addr16
A,Ri
A,ear
A,eam
A,io
A,#imm8
A,@A
A,@RLi+disp8
A,#imm4
A,dir
A,addr16
A,Ri
A,ear
A,eam
A,io
A,#imm8
A,@A
A,@RWi+disp8
A,@RLi+disp8
dir,A
addr16,A
Ri,A
ear,A
eam,A
io,A
@RLi+disp8,A
Ri,ear
Ri,eam
ear,Ri
eam,Ri
Ri,#imm8
io,#imm8
dir,#imm8
ear,#imm8
eam,#imm8
@AL,AH
A,ear
A,eam
Ri,ear
Ri,eam
#
~
RG
B
2
3
1
2
2+
2
2
2
3
1
2
3
2
2
2+
2
2
2
2
3
2
3
1
2
2+
2
3
2
2+
2
2+
2
3
3
3
3+
2
2
2+
2
2+
3
4
2
2
3 + (a)
3
2
3
10
1
3
4
2
2
3 + (a)
3
2
3
5
10
3
4
2
2
3 + (a)
3
10
3
4 + (a)
4
5 + (a)
2
5
5
2
4 + (a)
3
4
5 + (a)
7
9 + (a)
0
0
1
1
0
0
0
0
2
0
0
0
1
1
0
0
0
0
1
2
0
0
1
1
0
0
2
2
1
2
1
1
0
0
1
0
0
2
0
4
2
(b)
(b)
0
0
(b)
(b)
0
(b)
(b)
0
(b)
(b)
0
0
(b)
(b)
0
(b)
(b)
(b)
(b)
(b)
0
0
(b)
(b)
(b)
0
(b)
0
(b)
0
(b)
(b)
0
(b)
(b)
0
2 × (b)
0
2 × (b)
Operation
byte (A) ← (dir)
byte (A) ← (addr16)
byte (A) ← (Ri)
byte (A) ← (ear)
byte (A) ← (eam)
byte (A) ← (io)
byte (A) ← imm8
byte (A) ← ((A))
byte (A) ← ((RLi)+disp8)
byte (A) ← imm4
byte (A) ← (dir)
byte (A) ← (addr16)
byte (A) ← (Ri)
byte (A) ← (ear)
byte (A) ← (eam)
byte (A) ← (io)
byte (A) ← imm8
byte (A) ← ((A))
byte (A) ← ((RWi)+disp8)
byte (A) ← ((RLi)+disp8)
byte (dir) ← (A)
byte (addr16) ← (A)
byte (Ri) ← (A)
byte (ear) ← (A)
byte (eam) ← (A)
byte (io) ← (A)
byte ((RLi)+disp8) ← (A)
byte (Ri) ← (ear)
byte (Ri) ← (eam)
byte (ear) ← (Ri)
byte (eam) ← (Ri)
byte (Ri) ← imm8
byte (io) ← imm8
byte (dir) ← imm8
byte (ear) ← imm8
byte (eam) ← imm8
byte ((A)) ← (AH)
byte (A) ↔ (ear)
byte (A) ↔ (eam)
byte (Ri) ↔ (ear)
byte (Ri) ↔ (eam)
LH
AH
I
S
T
N
Z
V
C
RMW
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
X
X
X
X
X
X
X
X
X
X
Z
Z
-
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
-
-
-
-
*
*
*
*
*
*
*
*
*
R
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
-
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
-
-
-
-
Note:
See Table B.5-1 and Table B.5-2 for information on (a) and (b) in the table.
646
APPENDIX B Instructions
Table B.8-2 38 Transfer Instructions (Word, Long Word)
Mnemonic
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
XCHW
XCHW
XCHW
XCHW
MOVL
MOVL
MOVL
MOVL
MOVL
A,dir
A,addr16
A,SP
A,RWi
A,ear
A,eam
A,io
A,@A
A,#imm16
A,@RWi+disp8
A,@RLi+disp8
dir,A
addr16,A
SP,A
RWi,A
ear,A
eam,A
io,A
@RWi+disp8,A
@RLi+disp8,A
RWi,ear
RWi,eam
ear,RWi
eam,RWi
RWi,#imm16
io,#imm16
ear,#imm16
eam,#imm16
@AL,AH
A,ear
A,eam
RWi, ear
RWi, eam
A,ear
A,eam
A,#imm32
ear,A
eam,A
#
~
RG
B
2
3
1
1
2
2+
2
2
3
2
3
2
3
1
1
2
2+
2
2
3
2
2+
2
2+
3
4
4
4+
2
2
2+
2
2+
2
2+
5
2
2+
3
4
1
2
2
3 + (a)
3
3
2
5
10
3
4
1
2
2
3 + (a)
3
5
10
3
4 + (a)
4
5 + (a)
2
5
2
4 + (a)
3
4
5 + (a)
7
9 + (a)
4
5 + (a)
3
4
5 + (a)
0
0
0
1
1
0
0
0
0
1
2
0
0
0
1
1
0
0
1
2
2
1
2
1
1
0
1
0
0
2
0
4
2
2
0
0
2
0
(c)
(c)
0
0
0
(c)
(c)
(c)
0
(c)
(c)
(c)
(c)
0
0
0
(c)
(c)
(c)
(c)
0
(c)
0
(c)
0
(c)
0
(c)
(c)
0
2 × (c)
0
2 × (c)
0
(d)
0
0
(d)
Operation
word (A) ← (dir)
word (A) ← (addr16)
word (A) ← (SP)
word (A) ← (RWi)
word (A) ← (ear)
word (A) ← (eam)
word (A) ← (io)
word (A) ← ((A))
word (A) ← imm16
word (A) ← ((RWi)+disp8)
word (A) ← ((RLi)+disp8)
word (dir) ← (A)
word (addr16) ← (A)
word (SP) ← (A)
word (RWi) ← (A)
word (ear) ← (A)
word (eam) ← (A)
word (io) ← (A)
word ((RWi)+disp8) ← (A)
word ((RLi)+disp8) ← (A)
word (RWi) ← (ear)
word (RWi) ← (eam)
word (ear) ← (RWi)
word (eam) ← (RWi)
word (RWi) ← imm16
word (io) ← imm16
word (ear) ← imm16
word (eam) ← imm16
word ((A)) ← (AH)
word (A) ↔ (ear)
word (A) ↔ (eam)
word (RWi) ↔ (ear)
word (RWi) ↔ (eam)
long (A) ← (ear)
long (A) ← (eam)
long (A) ← imm32
long (ear) ← (A)
long(eam) ← (A)
LH
AH
I
S
T
N
Z
V
C
RMW
-
*
*
*
*
*
*
*
*
*
*
-
-
-
-
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
-
-
-
Note:
See Table B.5-1 and Table B.5-2 for information on (a), (c), and (d) in the table.
647
APPENDIX
Table B.8-3 42 Addition/Subtraction Instructions (Byte, Word, Long Word)
Mnemonic
#
~
RG
B
ADD
ADD
ADD
ADD
ADD
ADD
ADDC
ADDC
ADDC
ADDDC
A,#imm8
A,dir
A,ear
A,eam
ear,A
eam,A
A
A,ear
A,eam
A
2
2
2
2+
2
2+
1
2
2+
1
2
5
3
4 + (a)
3
5 + (a)
2
3
4 + (a)
3
0
0
1
0
2
0
0
1
0
0
0
(b)
0
(b)
0
2 × (b)
0
0
(b)
0
SUB
SUB
SUB
SUB
SUB
SUB
SUBC
SUBC
SUBC
SUBDC
A,#imm8
A,dir
A,ear
A,eam
ear,A
eam,A
A
A,ear
A,eam
A
2
2
2
2+
2
2+
1
2
2+
1
2
5
3
4 + (a)
3
5 + (a)
2
3
4 + (a)
3
0
0
1
0
2
0
0
1
0
0
0
(b)
0
(b)
0
2 × (b)
0
0
(b)
0
ADDW
ADDW
ADDW
ADDW
ADDW
ADDW
ADDCW
ADDCW
SUBW
SUBW
SUBW
SUBW
SUBW
SUBW
SUBCW
SUBCW
ADDL
ADDL
ADDL
SUBL
SUBL
SUBL
A
A,ear
A,eam
A,#imm16
ear,A
eam,A
A,ear
A,eam
A
A,ear
A,eam
A,#imm16
ear,A
eam,A
A,ear
A,eam
A,ear
A,eam
A,#imm32
A,ear
A,eam
A,#imm32
1
2
2+
3
2
2+
2
2+
1
2
2+
3
2
2+
2
2+
2
2+
5
2
2+
5
2
3
4+(a)
2
3
5+(a)
3
4+(a)
2
3
4+(a)
2
3
5+(a)
3
4+(a)
6
7+(a)
4
6
7+(a)
4
0
1
0
0
2
0
1
0
0
1
0
0
2
0
1
0
2
0
0
2
0
0
0
0
(c)
0
0
2 × (c)
0
(c)
0
0
(c)
0
0
2 × (c)
0
(c)
0
(d)
0
0
(d)
0
Operation
byte (A) ← (A) + imm8
byte (A) ← (A) + (dir)
byte (A) ← (A) + (ear)
byte (A) ← (A) + (eam)
byte (ear) ← (ear) + (A)
byte (eam) ← (eam) + (A)
byte (A) ← (AH) + (AL) + (C)
byte (A) ← (A) + (ear)+ (C)
byte (A) ← (A) + (eam)+ (C)
byte (A) ← (AH) + (AL) + (C)
(decimal)
byte (A) ← (A) - imm8
byte (A) ← (A) - (dir)
byte (A) ← (A) - (ear)
byte (A) ← (A) - (eam)
byte (ear) ← (ear) - (A)
byte (eam) ← (eam) - (A)
byte (A) ← (AH) - (AL) - (C)
byte (A) ← (A) - (ear) - (C)
byte (A) ← (A) - (eam) - (C)
byte (A) ← (AH) - (AL) - (C)
(decimal)
word (A) ← (AH) + (AL)
word (A) ← (A) + (ear)
word (A) ← (A) + (eam)
word (A) ← (A) + imm16
word (ear) ← (ear) + (A)
word (eam) ← (eam) + (A)
word (A) ← (A) + (ear) + (C)
word (A) ← (A) + (eam) + (C)
word (A) ← (AH) - (AL)
word (A) ← (A) - (ear)
word (A) ← (A) - (eam)
word (A) ← (A) - imm16
word (ear) ← (ear) - (A)
word (eam) ← (eam) - (A)
word (A) ← (A) - (ear) - (C)
word (A) ← (A) - (eam) - (C)
long (A) ← (A) + (ear)
long (A) ← (A) + (eam)
long (A) ← (A) + imm32
long (A) ← (A) - (ear)
long (A) ← (A) - (eam)
long (A) ← (A) - imm32
LH
AH
I
S
T
N
Z
V
C
RMW
Z
Z
Z
Z
Z
Z
Z
Z
Z
-
-
-
-
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
-
Z
Z
Z
Z
Z
Z
Z
Z
-
-
-
-
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
-
-
-
-
-
-
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
-
Note:
See Table B.5-1 and Table B.5-2 for information on (a) to (d) in the table.
648
APPENDIX B Instructions
Table B.8-4 12 Increment/decrement Instructions (Byte, Word, Long Word)
Mnemonic
#
~
RG
B
INC
ear
2
3
2
0
INC
eam
2+
5+(a)
0
2 × (b)
Operation
LH
AH
I
S
T
N
Z
V
C
RMW
byte (ear) ← (ear) + 1
-
-
-
-
-
*
*
*
-
-
byte (eam) ← (eam) + 1
-
-
-
-
-
*
*
*
-
*
DEC
ear
2
3
2
0
byte (ear) ← (ear) - 1
-
-
-
-
-
*
*
*
-
-
DEC
eam
2+
5+(a)
0
2 × (b)
byte (eam) ← (eam) - 1
-
-
-
-
-
*
*
*
-
*
INCW
ear
2
3
2
0
word (ear) ← (ear) + 1
-
-
-
-
-
*
*
*
-
-
INCW
eam
2+
5+(a)
0
2 × (c)
word (eam) ← (eam) + 1
-
-
-
-
-
*
*
*
-
*
DECW
ear
2
3
2
0
DECW
eam
2+
5+(a)
0
2 × (c)
INCL
ear
2
7
4
0
INCL
eam
2+
9+(a)
0
2 × (d)
DECL
ear
2
7
4
0
DECL
eam
2+
9+(a)
0
2 × (d)
word (ear) ← (ear) - 1
-
-
-
-
-
*
*
*
-
-
word (eam) ← (eam) - 1
-
-
-
-
-
*
*
*
-
*
long (ear) ← (ear) + 1
-
-
-
-
-
*
*
*
-
-
long (eam) ← (eam) + 1
-
-
-
-
-
*
*
*
-
*
long (ear) ← (ear) - 1
-
-
-
-
-
*
*
*
-
-
long (eam) ← (eam) - 1
-
-
-
-
-
*
*
*
-
*
Note:
See Table B.5-1 and Table B.5-2 for information on (a) to (d) in the table.
Table B.8-5 11 Compare Instructions (Byte, Word, Long Word)
#
~
RG
B
LH
AH
I
S
T
N
Z
V
C
RMW
CMP
Mnemonic
A
1
1
0
0
byte (AH) - (AL)
Operation
-
-
-
-
-
*
*
*
*
-
CMP
A,ear
2
2
1
0
byte (A) - (ear)
-
-
-
-
-
*
*
*
*
-
CMP
A,eam
2+
3+(a)
0
(b)
byte (A) - (eam)
-
-
-
-
-
*
*
*
*
-
CMP
A,#imm8
2
2
0
0
byte (A) - imm8
-
-
-
-
-
*
*
*
*
-
CMPW
A
1
1
0
0
word (AH) - (AL)
-
-
-
-
-
*
*
*
*
-
CMPW
A,ear
2
2
1
0
word (A) - (ear)
-
-
-
-
-
*
*
*
*
-
CMPW
A,eam
2+
3+(a)
0
(c)
word (A) - (eam)
-
-
-
-
-
*
*
*
*
-
CMPW
A,#imm16
3
2
0
0
word (A) - imm16
-
-
-
-
-
*
*
*
*
-
CMPL
A,ear
2
6
2
0
long (A) - (ear)
-
-
-
-
-
*
*
*
*
-
CMPL
A,eam
2+
7+(a)
0
(d)
long (A) - (eam)
-
-
-
-
-
*
*
*
*
-
CMPL
A,#imm32
5
3
0
0
long (A) - imm32
-
-
-
-
-
*
*
*
*
-
Note:
See Table B.5-1 and Table B.5-2 for information on (a) to (d) in the table.
649
APPENDIX
Table B.8-6 11 Unsigned Multiplication/Division Instructions (Word, Long Word)
Mnemonic
#
~
RG
B
Operation
LH
AH
I
S
T
N
Z
V
C
RMW
DIVU
A
1
*1
0
0
word (AH) / byte (AL)
quotient → byte (AL) remainder → byte (AH)
-
-
-
-
-
-
-
*
*
-
DIVU
A,ear
2
*2
1
0
word (A) / byte (ear)
quotient → byte (A) remainder → byte (ear)
-
-
-
-
-
-
-
*
*
-
DIVU
A,eam
2+
*3
0
*6
word (A) / byte (eam)
quotient → byte (A) remainder → byte (eam)
-
-
-
-
-
-
-
*
*
-
DIVUW
A,ear
2
*4
1
0
long (A) / word (ear)
quotient → word (A) remainder → word (ear)
-
-
-
-
-
-
-
*
*
-
DIVUW
A,eam
2+
*5
0
*7
long (A) / word (eam)
quotient → word (A) remainder → word (eam)
-
-
-
-
-
-
-
*
*
-
MULU
A
1
*8
0
0
byte (AH) * byte (AL) → word (A)
-
-
-
-
-
-
-
-
-
MULU
A,ear
2
*9
1
0
byte (A) * byte (ear) → word (A)
-
-
-
-
-
-
-
-
-
-
MULU
A,eam
2+
*10
0
(b)
byte (A) * byte (eam) → word (A)
-
-
-
-
-
-
-
-
-
-
MULUW
A
1
*11
0
0
word (AH) * word (AL) → Long (A)
-
-
-
-
-
-
-
-
-
MULUW
A,ear
2
*12
1
0
word (A) * word (ear) → Long (A)
-
-
-
-
-
-
-
-
-
-
MULUW
A,eam
2+
*13
0
(c)
word (A) * word (eam) → Long (A)
-
-
-
-
-
-
-
-
-
-
*1: 3: Division by 0 7: Overflow 15: Normal
*2: 4: Division by 0 8: Overflow 16: Normal
*3: 6+(a): Division by 0 9+(a): Overflow 19+(a): Normal
*4: 4: Division by 0 7: Overflow 22: Normal
*5: 6+(a): Division by 0 8+(a): Overflow 26+(a): Normal
*6: (b): Division by 0 or overflow 2 × (b): Normal
*7: (c): Division by 0 or overflow 2 × (c): Normal
*8: 3: Byte (AH) is 0. 7: Byte (AH) is not 0.
*9: 4: Byte (ear) is 0. 8: Byte (ear) is not 0.
*10: 5+(a): Byte (eam) is 0, 9+(a): Byte (eam) is not 0.
*11: 3: Word (AH) is 0. 11: Word (AH) is not 0.
*12: 4: Word (ear) is 0. 12: Word (ear) is not 0.
*13: 5+(a): Word (eam) is 0. 13+(a): Word (eam) is not 0.
Note:
See Table B.5-1 and Table B.5-2 for information on (a) to (c) in the table.
650
APPENDIX B Instructions
Table B.8-7 11 Signed Multiplication/Division Instructions (Word, Long Word)
Mnemonic
#
~
RG
B
Operation
LH
AH
I
S
T
N
Z
V
C
RMW
DIV
A
2
*1
0
0
word (AH) / byte (AL)
quotient → byte (AL) remainder → byte (AH)
Z
-
-
-
-
-
-
*
*
-
DIV
A,ear
2
*2
1
0
word (A) / byte (ear)
quotient → byte (A) remainder → byte (ear)
Z
-
-
-
-
-
-
*
*
-
DIV
A,eam
2+
*3
0
*6
word (A) / byte (eam)
quotient → byte (A) remainder → byte (eam)
Z
-
-
-
-
-
-
*
*
-
DIVW
A,ear
2
*4
1
0
long (A) / word (ear)
quotient → word (A) remainder → word (ear)
-
-
-
-
-
-
-
*
*
-
DIVW
A,eam
2+
*5
0
*7
long (A) / word (eam)
quotient → word (A) remainder → word (eam)
-
-
-
-
-
-
-
*
*
-
MUL
A
2
*8
0
0
byte (AH) * byte (AL) → word (A)
-
-
-
-
-
-
-
-
-
-
MUL
A,ear
2
*9
1
0
byte (A) * byte (ear) → word (A)
-
-
-
-
-
-
-
-
-
-
byte (A) * byte (eam) → word (A)
-
-
-
-
-
-
-
-
-
-
word (AH) * word (AL) → Long (A)
-
-
-
-
-
-
-
-
-
-
0
word (A) * word (ear) → Long (A)
-
-
-
-
-
-
-
-
-
-
(c)
word (A) * word (eam) → Long (A)
-
-
-
-
-
-
-
-
-
-
MUL
A,eam
2+
*10
0
(b)
MULW
A
2
*11
0
0
MULW
A,ear
2
*12
1
MULW
A,eam
2+
*13
0
*1:
*2:
*3:
*4:
3: Division by 0, 8 or 18: Overflow, 18: Normal
4: Division by 0, 11 or 22: Overflow, 23: Normal
5+(a): Division by 0, 12+(a) or 23+(a): Overflow, 24+(a): Normal
When dividend is positive; 4: Division by 0, 12 or 30: Overflow, 31: Normal
When dividend is negative; 4: Division by 0, 12 or 31: Overflow, 32: Normal
*5: When dividend is positive; 5+(a): Division by 0, 12+(a) or 31+(a): Overflow, 32+(a): Normal
When dividend is negative; 5+(a): Division by 0, 12+(a) or 32+(a): Overflow, 33+(a): Normal
*6: (b): Division by 0 or overflow, 2 × (b): Normal
*7: (c): Division by 0 or overflow, 2 × (c): Normal
*8: 3: Byte (AH) is 0, 12: result is positive, 13: result is negative
*9: 4: Byte (ear) is 0, 13: result is positive, 14: result is negative
*10: 5+(a): Byte (eam) is 0, 14+(a): result is positive, 15+(a): result is negative
*11: 3: Word (AH) is 0, 16: result is positive, 19: result is negative
*12: 4: Word (ear) is 0, 17: result is positive, 20: result is negative
*13: 5+(a): Word (eam) is 0, 18+(a): result is positive, 21+(a): result is negative
Notes:
• The execution cycle count found when an overflow occurs in a DIV or DIVW instruction may be a
pre-operation count or a post-operation count depending on the detection timing.
• When an overflow occurs with DIV or DIVW instruction, the contents of the AL are destroyed.
• See Table B.5-1 and Table B.5-2 for information on (a) to (c) in the table.
651
APPENDIX
Table B.8-8 39 Logic 1 Instructions (Byte, Word)
Mnemonic
#
~
RG
B
Operation
LH
AH
I
S
T
N
Z
V
C
RMW
-
AND
A,#imm8
2
2
0
0
byte (A) ← (A) and imm8
-
-
-
-
-
*
*
R
-
AND
A,ear
2
3
1
0
byte (A) ← (A) and (ear)
-
-
-
-
-
*
*
R
-
-
AND
A,eam
2+
4+(a)
0
(b)
byte (A) ← (A) and (eam)
-
-
-
-
-
*
*
R
-
-
byte (ear) ← (ear) and (A)
-
-
-
-
-
*
*
R
-
-
byte (eam) ← (eam) and (A)
-
-
-
-
-
*
*
R
-
*
AND
ear,A
2
3
2
0
AND
eam,A
2+
5+(a)
0
2 × (b)
OR
A,#imm8
2
2
0
0
byte (A) ← (A) or imm8
-
-
-
-
-
*
*
R
-
-
OR
A,ear
2
3
1
0
byte (A) ← (A) or (ear)
-
-
-
-
-
*
*
R
-
-
OR
A,eam
2+
4+(a)
0
(b)
byte (A) ← (A) or (eam)
-
-
-
-
-
*
*
R
-
-
OR
ear,A
2
3
2
0
byte (ear) ← (ear) or (A)
-
-
-
-
-
*
*
R
-
-
OR
eam,A
2+
5+(a)
0
2 × (b)
byte (eam) ← (eam) or (A)
-
-
-
-
-
*
*
R
-
*
XOR
A,#imm8
2
2
0
0
byte (A) ← (A) xor imm8
-
-
-
-
-
*
*
R
-
-
XOR
A,ear
2
3
1
0
byte (A) ← (A) xor (ear)
-
-
-
-
-
*
*
R
-
-
XOR
A,eam
2+
4+(a)
0
(b)
byte (A) ← (A) xor (eam)
-
-
-
-
-
*
*
R
-
-
XOR
ear,A
2
3
2
0
byte (ear) ← (ear) xor (A)
-
-
-
-
-
*
*
R
-
-
XOR
eam,A
2+
5+(a)
0
2 × (b)
byte (eam) ← (eam) xor (A)
-
-
-
-
-
*
*
R
-
*
NOT
A
1
2
0
0
byte (A) ← not (A)
-
-
-
-
-
*
*
R
-
-
NOT
ear
2
3
2
0
byte (ear) ← not (ear)
-
-
-
-
-
*
*
R
-
-
NOT
eam
2+
5+(a)
0
2 × (b)
byte (eam) ← not (eam)
-
-
-
-
-
*
*
R
-
*
ANDW
A
1
2
0
0
word (A) ← (AH) and (A)
-
-
-
-
-
*
*
R
-
-
ANDW
A,#imm16
3
2
0
0
word (A) ← (A) and imm16
-
-
-
-
-
*
*
R
-
-
ANDW
A,ear
2
3
1
0
word (A) ← (A) and (ear)
-
-
-
-
-
*
*
R
-
-
ANDW
A,eam
2+
4+(a)
0
(c)
word (A) ← (A) and (eam)
-
-
-
-
-
*
*
R
-
-
word (ear) ← (ear) and (A)
-
-
-
-
-
*
*
R
-
-
word (eam) ← (eam) and (A)
-
-
-
-
-
*
*
R
-
*
0
word (A) ← (AH) or (A)
-
-
-
-
-
*
*
R
-
-
0
word (A) ← (A) or imm16
-
-
-
-
-
*
*
R
-
-
1
0
word (A) ← (A) or (ear)
-
-
-
-
-
*
*
R
-
-
4+(a)
0
(c)
word (A) ← (A) or (eam)
-
-
-
-
-
*
*
R
-
-
2
3
2
0
word (ear) ← (ear) or (A)
-
-
-
-
-
*
*
R
-
-
eam,A
2+
5+(a)
0
2 × (c)
word (eam) ← (eam) or (A)
-
-
-
-
-
*
*
R
-
*
XORW
A
1
2
0
0
word (A) ← (AH) xor (A)
-
-
-
-
-
*
*
R
-
-
XORW
A,#imm16
3
2
0
0
word (A) ← (A) xor imm16
-
-
-
-
-
*
*
R
-
-
XORW
A,ear
2
3
1
0
word (A) ← (A) xor (ear)
-
-
-
-
-
*
*
R
-
-
ANDW
ear,A
2
3
2
0
ANDW
eam,A
2+
5+(a)
0
2 × (c)
ORW
A
1
2
0
ORW
A,#imm16
3
2
0
ORW
A,ear
2
3
ORW
A,eam
2+
ORW
ear,A
ORW
XORW
A,eam
2+
4+(a)
0
(c)
word (A) ← (A) xor (eam)
-
-
-
-
-
*
*
R
-
XORW
ear,A
2
3
2
0
word (ear) ← (ear) xor (A)
-
-
-
-
-
*
*
R
-
-
XORW
eam,A
2+
5+(a)
0
2 × (c)
word (eam) ← (eam) xor (A)
-
-
-
-
-
*
*
R
-
*
NOTW
A
1
2
0
0
word (A) ← not (A)
-
-
-
-
-
*
*
R
-
-
NOTW
ear
2
3
2
0
word (ear) ← not (ear)
-
-
-
-
-
*
*
R
-
-
NOTW
eam
2+
5+(a)
0
2 × (c)
word (eam) ← not (eam)
-
-
-
-
-
*
*
R
-
*
Note:
See Table B.5-1 and Table B.5-2 for information on (a) to (c) in the table.
652
APPENDIX B Instructions
Table B.8-9 6 Logic 2 Instructions (Long Word)
Mnemonic
#
~
RG
B
Operation
LH
AH
I
S
T
N
Z
V
C
RMW
ANDL
A,ear
2
6
2
0
long (A) ← (A) and (ear)
-
-
-
-
-
*
*
R
-
-
ANDL
A,eam
2+
7+(a)
0
(d)
long (A) ← (A) and (eam)
-
-
-
-
-
*
*
R
-
-
ORL
A,ear
2
6
2
0
long (A) ← (A) or (ear)
-
-
-
-
-
*
*
R
-
-
ORL
A,eam
2+
7+(a)
0
(d)
long (A) ← (A) or (eam)
-
-
-
-
-
*
*
R
-
-
XORL
A,ear
2
6
2
0
long (A) ← (A) xor (ear)
-
-
-
-
-
*
*
R
-
-
XORL
A,eam
2+
7+(a)
0
(d)
long (A) ← (A) xor (eam)
-
-
-
-
-
*
*
R
-
-
Note:
See Table B.5-1 and Table B.5-2 for information on (a) and (d) in the table.
Table B.8-10 6 Sign Inversion Instructions (Byte, Word)
Mnemonic
NEG
A
#
~
RG
B
1
2
0
0
byte (A) ← 0 - (A)
byte (ear) ← 0 - (ear)
-
-
-
-
-
*
*
*
*
-
byte (eam) ← 0 - (eam)
-
-
-
-
-
*
*
*
*
*
word (A) ← 0 - (A)
-
-
-
-
-
*
*
*
*
-
NEG
ear
2
3
2
0
NEG
eam
2+
5+(a)
0
2 × (b)
NEGW
A
1
2
0
0
NEGW
ear
2
3
2
0
NEGW
eam
2+
5+(a)
0
2 × (c)
Operation
LH
AH
I
S
T
N
Z
V
C
RMW
X
-
-
-
-
*
*
*
*
-
word (ear) ← 0 - (ear)
-
-
-
-
-
*
*
*
*
-
word (eam) ← 0 - (eam)
-
-
-
-
-
*
*
*
*
*
Note:
See Table B.5-1 and Table B.5-2 for information on (a) to (c) in the table.
Table B.8-11 1 Normalization Instruction (Long Word)
Mnemonic
NRML
A,R0
#
~
RG
B
2
*1
1
0
Operation
long (A) ← Shift left to the position where '1' is set
for the first time.
byte (R0) ← Shift count at that time
LH
AH
I
S
T
N
Z
V
C
RMW
-
-
-
-
-
-
*
-
-
-
*1: 4 when all accumulators have a value of 0; otherwise, 6+(R0)
653
APPENDIX
Table B.8-12 18 Shift Instructions (Byte, Word, Long Word)
Mnemonic
#
~
RG
B
Operation
LH
AH
I
S
T
N
Z
V
C
RMW
RORC
A
2
2
0
0
byte (A) ← Right rotation with carry
-
-
-
-
-
*
*
-
*
-
ROLC
A
2
2
0
0
byte (A) ← Right rotation with carry
-
-
-
-
-
*
*
-
*
-
RORC
ear
2
3
2
0
byte (ear) ← Right rotation with carry
-
-
-
-
-
*
*
-
*
-
RORC
eam
2+
5+(a)
0
2 × (b)
byte (eam) ← Right rotation with carry
-
-
-
-
-
*
*
-
*
*
ROLC
ear
2
3
2
0
byte (ear) ← Left rotation with carry
-
-
-
-
-
*
*
-
*
-
ROLC
eam
2+
5+(a)
0
2 × (b)
byte (eam) ← Left rotation with carry
-
-
-
-
-
*
*
-
*
*
ASR
A,R0
2
*1
1
0
byte (A) ← Arithmetic right shift (A, 1 bit)
-
-
-
-
*
*
*
-
*
-
LSR
A,R0
2
*1
1
0
byte (A) ← Logical right barrel shift (A, R0)
-
-
-
-
*
*
*
-
*
-
LSL
A,R0
2
*1
1
0
byte (A) ← Logical left barrel shift (A, R0)
-
-
-
-
-
*
*
-
*
-
ASRW
A
1
2
0
0
word (A) ← Arithmetic right shift (A, 1 bit)
-
-
-
-
*
*
*
-
*
-
LSRW
A/SHRW A
1
2
0
0
word (A) ← Logical right shift (A, 1 bit)
-
-
-
-
*
R
*
-
*
-
LSLW
A/SHLW A
1
2
0
0
word (A) ← Logical left shift (A, 1 bit)
-
-
-
-
-
*
*
-
*
-
ASRW
A,R0
2
*1
1
0
word (A) ← Arithmetic right barrel shift (A, R0)
-
-
-
-
*
*
*
-
*
-
LSRW
A,R0
2
*1
1
0
word (A) ← Logical right barrel shift (A, R0)
-
-
-
-
*
*
*
-
*
-
LSLW
A,R0
2
*1
1
0
word (A) ← Logical left barrel shift (A, R0)
-
-
-
-
-
*
*
-
*
-
ASRL
A,R0
2
*2
1
0
long (A) ← Arithmetic right barrel shift (A, R0)
-
-
-
-
*
*
*
-
*
-
LSRL
A,R0
2
*2
1
0
long (A) ← Logical right barrel shift (A, R0)
-
-
-
-
*
*
*
-
*
-
LSLL
A,R0
2
*2
1
0
long (A) ← Logical left barrel shift (A, R0)
-
-
-
-
-
*
*
-
*
-
*1: 6 when R0 is 0; otherwise, 5 + (R0)
*2: 6 when R0 is 0; otherwise, 6 + (R0)
Note:
See Table B.5-1 and Table B.5-2 for information on (a) and (b) in the table.
654
APPENDIX B Instructions
Table B.8-13 31 Branch 1 Instructions
Mnemonic
#
~
RG
B
Operation
LH
AH
I
S
T
N
Z
V
C
RMW
BZ/BEQ
rel
2
*1
0
0
Branch on (Z) = 1
-
-
-
-
-
-
-
-
-
-
BNZ/
BNE
rel
2
*1
0
0
Branch on (Z) = 0
-
-
-
-
-
-
-
-
-
-
BC/BLO
rel
2
*1
0
0
Branch on (C) = 1
-
-
-
-
-
-
-
-
-
-
BNC/
BHS
rel
2
*1
0
0
Branch on (C) = 0
-
-
-
-
-
-
-
-
-
-
BN
rel
2
*1
0
0
Branch on (N) = 1
-
-
-
-
-
-
-
-
-
-
BP
rel
2
*1
0
0
Branch on (N) = 0
-
-
-
-
-
-
-
-
-
-
BV
rel
2
*1
0
0
Branch on (V) = 1
-
-
-
-
-
-
-
-
-
-
BNV
rel
2
*1
0
0
Branch on (V) = 0
-
-
-
-
-
-
-
-
-
-
BT
rel
2
*1
0
0
Branch on (T) = 1
-
-
-
-
-
-
-
-
-
-
BNT
rel
2
*1
0
0
Branch on (T) = 0
-
-
-
-
-
-
-
-
-
-
BLT
rel
2
*1
0
0
Branch on (V) xor (N) = 1
-
-
-
-
-
-
-
-
-
-
BGE
rel
2
*1
0
0
Branch on (V) xor (N) = 0
-
-
-
-
-
-
-
-
-
-
BLE
rel
2
*1
0
0
Branch on ((V) xor (N)) or (Z) = 1
-
-
-
-
-
-
-
-
-
-
BGT
rel
2
*1
0
0
Branch on ((V) xor (N)) or (Z) = 0
-
-
-
-
-
-
-
-
-
-
BLS
rel
2
*1
0
0
Branch on (C) or (Z) = 1
-
-
-
-
-
-
-
-
-
-
BHI
rel
2
*1
0
0
Branch on (C) or (Z) = 0
-
-
-
-
-
-
-
-
-
-
BRA
rel
2
*1
0
0
Unconditional branch
-
-
-
-
-
-
-
-
-
-
JMP
@A
1
2
0
0
word (PC) ← (A)
-
-
-
-
-
-
-
-
-
-
JMP
addr16
3
3
0
0
word (PC) ← addr16
-
-
-
-
-
-
-
-
-
-
JMP
@ear
2
3
1
0
word (PC) ← (ear)
-
-
-
-
-
-
-
-
-
JMP
@eam
2+
4+(a)
0
(c)
word (PC) ← (eam)
-
-
-
-
-
-
-
-
-
-
JMPP
@ear *3
2
5
2
0
word (PC) ← (ear), (PCB) ← (ear+2)
-
-
-
-
-
-
-
-
-
-
JMPP
@eam *3
2+
6+(a)
0
(d)
JMPP
addr24
4
4
0
0
word (PC) ← (eam), (PCB) ← (eam+2)
-
-
-
-
-
-
-
-
-
-
word (PC) ← ad24 0-15, (PCB) ← ad24 16-23
-
-
-
-
-
-
-
-
-
-
CALL
@ear *4
2
6
1
(c)
word (PC) ← (ear)
-
-
-
-
-
-
-
-
-
-
CALL
@eam *4
2+
7+(a)
0
2 × (c)
word (PC) ← (eam)
-
-
-
-
-
-
-
-
-
-
CALL
addr16 *5
3
6
0
(c)
word (PC) ← addr16
-
-
-
-
-
-
-
-
-
-
CALLV
#vct4 *5
1
7
0
2 × (c)
Vector call instruction
-
-
-
-
-
-
-
-
-
-
CALLP
@ear *6
2
10
2
2 × (c)
word (PC) ← (ear), (PCB) ← (ear+2)
-
-
-
-
-
-
-
-
-
-
CALLP
@eam *6
2+
11+(a)
0
*2
CALLP
addr24 *7
4
10
0
2 × (c)
word (PC) ← (eam), (PCB) ← (eam+2)
-
-
-
-
-
-
-
-
-
-
word (PC) ← ad24 0-15, (PCB) ← ad24 16-23
-
-
-
-
-
-
-
-
-
-
*1: 4 when a branch is made; otherwise, 3
*2: 3 × (c) + (b)
*3: Read (word) of branch destination address
*4: W: Save to stack (word) R: Read (word) of branch destination address
*5: Save to stack (word)
*6: W: Save to stack (long word), R: Read (long word) of branch destination address
*7: Save to stack (long word)
Note:
See Table B.5-1 and Table B.5-2 for information on (a) to (d) in the table.
655
APPENDIX
Table B.8-14 19 Branch 2 Instructions
Mnemonic
#
~
RG
B
Operation
LH
AH
I
S T N Z V C
RMW
CBNE
A,#imm8,rel
3
*1
0
0
Branch on byte (A) not equal to imm8
-
-
-
-
-
*
*
*
*
-
CWBNE
A,#imm16,rel
4
*1
0
0
Branch on word (A) not equal to imm16
-
-
-
-
-
*
*
*
*
-
CBNE
ear,#imm8,rel
4
*2
1
0
Branch on byte (ear) not equal to imm8
-
-
-
-
-
*
*
*
*
-
CBNE
eam,#imm8,rel *9
4+
*3
0
(b)
Branch on byte (eam) not equal to imm8
-
-
-
-
-
*
*
*
*
-
CWBNE
ear,#imm16,rel
5
*4
1
0
Branch on word (ear) not equal to imm16
-
-
-
-
-
*
*
*
*
-
CWBNE
eam,#imm16,rel*9
5+
*3
0
(c)
Branch on word (eam) not equal to imm16
-
-
-
-
-
*
*
*
*
-
DBNZ
ear,rel
3
*5
2
0
byte (ear) ← (ear) - 1, Branch on (ear) not equal to 0
-
-
-
-
-
*
*
*
-
*
DBNZ
eam,rel
3+
*6
2
DWBNZ
ear,rel
3
*5
2
DWBNZ
eam,rel
3+
*6
2
2 × (b) byte (eam) ← (eam) - 1, Branch on (eam) not equal to 0
-
-
-
-
-
*
*
*
-
-
-
-
-
-
*
*
*
-
-
2 × (c) word (eam) ← (eam) - 1, Branch on (eam) not equal to 0
-
-
-
-
-
*
*
*
-
*
0
word (ear) ← (ear) - 1, Branch on (ear) not equal to 0
INT
#vct8
2
20
0
8 × (c) Software interrupt
-
-
R
S
-
-
-
-
-
-
INT
addr16
3
16
0
6 × (c) Software interrupt
-
-
R
S
-
-
-
-
-
-
INTP
addr24
4
17
0
6 × (c) Software interrupt
-
-
R
S
-
-
-
-
-
-
1
20
0
8 × (c) Software interrupt
-
-
R
S
-
-
-
-
-
-
INT9
RETI
LINK
#imm8
UNLINK
1
*8
0
*7
Return from interrupt
-
-
*
*
*
*
*
*
*
-
2
6
0
(c)
Saves the old frame pointer in the stack upon entering the
function, then sets the new frame pointer and reserves the
local pointer area.
-
-
-
-
-
-
-
-
-
-
1
5
0
(c)
Recovers the old frame pointer from the stack upon exiting
the function.
-
-
-
-
-
-
-
-
-
-
RET
*10
1
4
0
(c)
Return from subroutine
-
-
-
-
-
-
-
-
-
-
RETP
*11
1
6
0
(d)
Return from subroutine
-
-
-
-
-
-
-
-
-
-
*1: 5 when a branch is made; otherwise, 4
*2: 13 when a branch is made; otherwise, 12
*3: 7+(a) when a branch is made; otherwise, 6+(a)
*4: 8 when a branch is made; otherwise, 7
*5: 7 when a branch is made; otherwise, 6
*6: 8+(a) when a branch is made; otherwise, 7+(a)
*7: 3 × (b) + 2 × (c) when jumping to the next interruption request; 6 × (c) when returning from the current interruption
*8: 15 when jumping to the next interruption request; 17 when returning from the current interruption
*9: Do not use RWj+ addressing mode with a CBNE or CWBNE instruction.
*10: Return from stack (word)
*11: Return from stack (long word)
Note:
See Table B.5-1 and Table B.5-2 for information on (a) to (d) in the table.
656
APPENDIX B Instructions
Table B.8-15 28 Other Control Instructions (Byte, Word, Long Word)
Mnemonic
#
~
RG
B
Operation
LH
AH
I
S
T
N
Z
V
C
RMW
PUSHW
A
1
4
0
(c)
word (SP) ← (SP) - 2, ((SP)) ← (A)
-
-
-
-
-
-
-
-
-
-
PUSHW
AH
1
4
0
(c)
word (SP) ← (SP) - 2, ((SP)) ← (AH)
-
-
-
-
-
-
-
-
-
-
PUSHW
PS
1
4
0
(c)
word (SP) ← (SP) - 2, ((SP)) ← (PS)
-
-
-
-
-
-
-
-
-
-
PUSHW
rlst
2
*3
*5
*4
(SP) ← (SP) - 2n, ((SP)) ← (rlst)
-
-
-
-
-
-
-
-
-
-
POPW
A
1
3
0
(c)
word (A) ← ((SP)), (SP) ← (SP) + 2
-
*
-
-
-
-
-
-
-
-
POPW
AH
1
3
0
(c)
word (AH) ← ((SP)), (SP) ← (SP) + 2
-
-
-
-
-
-
-
-
-
-
POPW
PS
1
4
0
(c)
word (PS) ← ((SP)), (SP) ← (SP) + 2
-
-
*
*
*
*
*
*
*
-
POPW
rlst
2
*2
*5
*4
(rlst) ← ((SP)), (SP) ← (SP) + 2n
-
-
-
-
-
-
-
-
-
-
JCTX
@A
1
14
0
6 × (c)
Context switch instruction
-
-
*
*
*
*
*
*
*
-
AND
CCR,#imm8
2
3
0
0
byte (CCR) ← (CCR) and imm8
-
-
*
*
*
*
*
*
*
-
OR
CCR,#imm8
2
3
0
0
byte (CCR) ← (CCR) or imm8
-
-
*
*
*
*
*
*
*
-
MOV
RP,#imm8
2
2
0
0
byte (RP) ← imm8
-
-
-
-
-
-
-
-
-
-
MOV
ILM,#imm8
2
2
0
0
byte (ILM) ← imm8
-
-
-
-
-
-
-
-
-
-
MOVEA
RWi,ear
2
3
1
0
word (RWi) ← ear
-
-
-
-
-
-
-
-
-
-
MOVEA
RWi,eam
2+
2+(a)
1
0
word (RWi) ← eam
-
-
-
-
-
-
-
-
-
-
MOVEA
A,ear
2
1
0
0
word (A) ← ear
-
*
-
-
-
-
-
-
-
-
MOVEA
A,eam
2+
1+(a)
0
0
word (A) ← eam
-
*
-
-
-
-
-
-
-
-
ADDSP
#imm8
2
3
0
0
word (SP) ← (SP) + ext(imm8)
-
-
-
-
-
-
-
-
-
-
ADDSP
#imm16
3
3
0
0
word (SP) ← (SP) + imm16
-
-
-
-
-
-
-
-
-
-
MOV
A,brg1
2
*1
0
0
byte (A) ← (brg1)
Z
*
-
-
-
*
*
-
-
-
MOV
brg2,A
-
2
1
0
0
byte (brg2) ← (A)
-
-
-
-
-
*
*
-
-
NOP
1
1
0
0
No operation
-
-
-
-
-
-
-
-
-
-
ADB
1
1
0
0
Prefix code for AD space access
-
-
-
-
-
-
-
-
-
-
DTB
1
1
0
0
Prefix code for DT space access
-
-
-
-
-
-
-
-
-
-
PCB
1
1
0
0
Prefix code for PC space access
-
-
-
-
-
-
-
-
-
-
SPB
1
1
0
0
Prefix code for SP space access
-
-
-
-
-
-
-
-
-
-
NCC
1
1
0
0
Prefix code for flag no-change
-
-
-
-
-
-
-
-
-
-
CMR
1
1
0
0
Prefix code for common register bank
-
-
-
-
-
-
-
-
-
-
*1: PCB, ADB, SSB, USB, SPB: 1, DTB, DPR: 2
*2: 7 + 3 × (POP count) + 2 × (POP last register number), 7 when RLST = 0 (no transfer register)
*3: 29 + 3 × (PUSH count) - 3 × (PUSH last register number), 8 when RLST = 0 (no transfer register)
*4: (POP count) × (c) or (PUSH count) × (c)
*5: (POP count) or (PUSH count)
Note:
See Table B.5-1 and Table B.5-2 for information on (a) and (c) in the table.
657
APPENDIX
Table B.8-16 21 Bit Operand Instructions
Mnemonic
#
~
RG
B
Operation
LH
AH
I
S
T
N
Z
V
C
RMW
MOVB
A,dir:bp
3
5
0
(b)
byte (A) ← (dir:bp)b
Z
*
-
-
-
*
*
-
-
-
MOVB
A,addr16:bp
4
5
0
(b)
byte (A) ← (addr16:bp)b
Z
*
-
-
-
*
*
-
-
-
MOVB
A,io:bp
3
4
0
(b)
byte (A) ← (io:bp)b
Z
*
-
-
-
*
*
-
-
-
MOVB
dir:bp,A
3
7
0
2 × (b)
bit (dir:bp)b ← (A)
-
-
-
-
-
*
*
-
-
*
MOVB
addr16:bp,A
4
7
0
2 × (b)
bit (addr16:bp)b ← (A)
-
-
-
-
-
*
*
-
-
*
MOVB
io:bp,A
3
6
0
2 × (b)
bit (io:bp)b ← (A)
-
-
-
-
-
*
*
-
-
*
*
SETB
dir:bp
3
7
0
2 × (b)
bit (dir:bp)b ← 1
-
-
-
-
-
-
-
-
-
SETB
addr16:bp
4
7
0
2 × (b)
bit (addr16:bp)b ← 1
-
-
-
-
-
-
-
-
-
*
SETB
io:bp
3
7
0
2 × (b)
bit (io:bp)b ← 1
-
-
-
-
-
-
-
-
-
*
*
CLRB
dir:bp
3
7
0
2 × (b)
bit (dir:bp)b ← 0
-
-
-
-
-
-
-
-
-
CLRB
addr16:bp
4
7
0
2 × (b)
bit (addr16:bp)b ← 0
-
-
-
-
-
-
-
-
-
*
CLRB
io:bp
3
7
0
2 × (b)
bit (io:bp)b ← 0
-
-
-
-
-
-
-
-
-
*
BBC
dir:bp,rel
4
*1
0
(b)
Branch on (dir:bp) b = 0
-
-
-
-
-
-
*
-
-
-
BBC
addr16:bp,rel
5
*1
0
(b)
Branch on (addr16:bp) b = 0
-
-
-
-
-
-
*
-
-
-
BBC
io:bp,rel
4
*2
0
(b)
Branch on (io:bp) b = 0
-
-
-
-
-
-
*
-
-
-
BBS
dir:bp,rel
4
*1
0
(b)
Branch on (dir:bp) b = 1
-
-
-
-
-
-
*
-
-
-
BBS
addr16:bp,rel
5
*1
0
(b)
Branch on (addr16:bp) b = 1
-
-
-
-
-
-
*
-
-
-
BBS
io:bp,rel
4
*2
0
(b)
Branch on (io:bp) b = 1
-
-
-
-
-
-
*
-
-
-
SBBS
addr16:bp,rel
5
*3
0
2 × (b)
Branch on (addr16:bp) b = 1,
bit (addr16:bp) b ← 1
-
-
-
-
-
-
*
-
-
*
WBTS
io:bp
3
*4
0
*5
Waits until (io:bp) b = 1
-
-
-
-
-
-
-
-
-
-
WBTC
io:bp
3
*4
0
*5
Waits until (io:bp) b = 0
-
-
-
-
-
-
-
-
-
-
RMW
*1: 8 when a branch is made; otherwise, 7
*2: 7 when a branch is made; otherwise, 6
*3: 10 when the condition is met; otherwise, 9
*4: Undefined count
*5: Until the condition is met
Note:
See Table B.5-1 and Table B.5-2 for information on (b) in the table.
Table B.8-17 6 Accumulator Operation Instructions (Byte, Word)
#
~
RG
B
LH
AH
I
S
T
N
Z
V
C
SWAP
Mnemonic
1
3
0
0
byte (A)0-7 ↔ (A)8-15
-
-
-
-
-
-
-
-
-
-
SWAPW
1
2
0
0
word (AH) ↔ (AL)
-
*
-
-
-
-
-
-
-
-
EXT
1
1
0
0
Byte sign extension
X
-
-
-
-
*
*
-
-
-
EXTW
1
2
0
0
Word sign extension
-
X
-
-
-
*
*
-
-
-
ZEXT
1
1
0
0
Byte zero extension
Z
-
-
-
-
R
*
-
-
-
ZEXTW
1
1
0
0
Word zero extension
-
Z
-
-
-
R
*
-
-
-
658
Operation
APPENDIX B Instructions
Table B.8-18 10 String Instructions
Mnemonic
#
~
RG
B
Operation
LH
AH
I
S
T
N
Z
V
C
RMW
-
MOVS / MOVSI
2
*2
*5
*3
byte transfer @AH+ ← @AL+, counter = RW0
-
-
-
-
-
-
-
-
-
MOVSD
2
*2
*5
*3
byte transfer @AH- ← @AL-, counter = RW0
-
-
-
-
-
-
-
-
-
-
SCEQ / SCEQI
2
*1
*8
*4
byte search @AH+ ← AL, counter = RW0
-
-
-
-
-
*
*
*
*
-
SCEQD
2
*1
*8
*4
byte search @AH- ← AL, counter = RW0
-
-
-
-
-
*
*
*
*
FILS / FILSI
2
6m+6
*8
*3
byte fill @AH+ ← AL, counter = RW0
-
-
-
-
-
*
*
-
-
-
MOVSW / MOVSWI
2
*2
*5
*6
word transfer @AH+ ← @AL+, counter = RW0
-
-
-
-
-
-
-
-
-
-
MOVSWD
2
*2
*5
*6
word transfer @AH- ← @AL-, counter = RW0
-
-
-
-
-
-
-
-
-
-
SCWEQ / SCWEQI
2
*1
*8
*7
word search @AH+ - AL, counter = RW0
-
-
-
-
-
*
*
*
*
-
SCWEQD
2
*1
*8
*7
word search @AH- - AL, counter = RW0
-
-
-
-
-
*
*
*
*
-
FILSW / FILSWI
2
6m+6
*8
*6
word fill @AH+ ← AL, counter = RW0
-
-
-
-
-
*
*
-
-
-
*1: 5 when RW0 is 0, 4 + 7 × (RW0) when the counter expires, or 7n + 5 when a match occurs
*2: 5 when RW0 is 0; otherwise, 4 + 8 × (RW0)
*3: (b) × (RW0) + (b) × (RW0) When the source and destination access different areas, calculate the (b) item individually.
*4: (b) × n
*5: 2 × (b) × (RW0)
*6: (c) × (RW0) + (c) × (RW0) When the source and destination access different areas, calculate the (c) item individually.
*7: (c) × n
*8: (b) × (RW0)
Note:
m: RW0 value (counter value), n: Loop count
See Table B.5-1 and Table B.5-2 for information on (b) and (c) in the table.
659
APPENDIX
B.9
Instruction Map
Each F2MC-16LX instruction code consists of 1 or 2 bytes. Therefore, the instruction
map consists of multiple pages. Table B.9-2 to Table B.9-21 summarize the F2MC-16LX
instruction map.
■ Structure of Instruction Map
Figure B.9-1 Structure of Instruction Map
Basic page map
Bit operation
instructions
Character string
operation
instructions
2-byte
instructions
: Byte 1
ea instructions × 9 : Byte 2
An instruction such as the NOP instruction that ends in one byte is completed within the basic page. An
instruction such as the MOVS instruction that requires two bytes recognizes the existence of byte 2 when it
references byte 1, and can check the following one byte by referencing the map for byte 2. Figure B.9-2
shows the correspondence between an actual instruction code and instruction map.
660
APPENDIX B Instructions
Figure B.9-2 Correspondence between Actual Instruction Code and Instruction Map
Some instructions do
not contain byte 2.
Instruction
code
Length varies
depending on the
instruction.
Byte 1
Byte 2
Operand
Operand
...
[Basic page map]
XY
+Z
[Extended page map]*
UV
+W
*: The extended page map is a generic name of maps for bit operation instructions, character
string operation instructions, 2-byte instructions, and ea instructions. Actually, there are
multiple extended page maps for each type of instructions.
An example of an instruction code is shown in Table B.9-1.
Table B.9-1 Example of an Instruction Code
Byte 1
(from basic page map)
Byte 2
(from extended page map)
NOP
00 +0=00
-
AND A, #8
30 +4=34
-
MOV A, ADB
60 +F=6F
00 +0=00
@RW2+d8, #8, rel
70 +0=70
F0 +2=F2
Instruction
661
662
+F
+E
+D
+C
+B
+A
+9
+8
+7
+6
+5
+4
+3
+2
+1
+0
A
ZEXT
SWAP
ADDSP
DTB
ADB
SPB
#8
A, #8
dir, A
A, dir
io, A
A, io
JMP
BRA
60
MULU
DIVU
ea
@A instruction 2
A
MOVW
MOVX
RET
SP, A A, addr16
A0
B0
C0
ea
instruction 8
D0
E0
rel
rel
LSRW
ASRW
LSLW
SWAPW
ZEXTW
XORW
ORW
ANDW
ORW
PUSHW
POPW
A, #16
AH
AH
MOVW
ea, RWi
Bit operation MOV
A instruction
ea, Ri
MOVW
RWi, ea
PUSHW
POPW
2-byte
XCHW
A
rlst
rlst instruction
RWi, ea
Character
XORW
PUSHW
POPW
XCH
operation
A
A, #16
PS
PS string
Ri, ea
instruction
A
ANDW
PUSHW
POPW
A
A, #16
A
CMPW
MOVL
MOVW
RETI
A, #16
A, #32 addr16, A
ADDSP
MULUW
NOTW
A
#16
A
A
A
EXTW
A
BHI
BLS
BGT
BLE
rel
rel
rel
rel
rel
BGE
CMPL
CMPW
A, #32
NEGW
A
rel
rel
rel
rel
rel
rel
BLT
BT
BNV
BV
BP
BN
BNC/BHS
rel
BC/BLO
BNZ/BNE
rel
BZ/BEQ
MOV
MOV
CBNE A, CWBNE A, MOVW
MOVW
INTP
MOV
RP, #8
ILM, #8
#8, rel
#16, rel
A, #16 A,addr16
addr24
Ri, ea
#4
F0
rel
ADDW
MOVW
MOVW
INT
ea
MOVW
MOVW
MOVW
MOV A,
MOVW
A, #16
A, dir
A, io
#vct8 instruction 9
A, RWi
RWi, A RWi, #16 @RWi+d8 @RWi+d8, A
NOT
ea
instruction 7
MOVX
MOVX
CALLP
ea
A, dir
A, io
addr24 instruction 6
MOVW
MOVW
RETP
A, #8
A, SP
io, #16
A, #8
90
BNT
SUBL
SUBW
A, #32
A
A
A
XOR
OR
OR
CCR, #8
80
ea
MOV
MOV
MOV
MOV
MOVX A, MOV
CALL
rel instruction 1
A, Ri
Ri, A
Ri, #8
A, Ri @RWi+d8
A, #4
70
MOV
JMP
ea
A, addr16
addr16 instruction 3
MOV
MOV
50
MOVX
MOV
JMPP
ea
A, #8
A, #8 addr16, A
addr24 instruction 4
MOV
MOV
MOV
40
SUBW
MOVW
MOVW
INT
MOVEA
A
A, #16
dir, A
io, A
addr16
RWi, ea
UNLINK
A
CMP
A
A, #8
A, #8
SUBC
SUB
ADD
30
AND
AND
MOV
MOV
CALL
ea
CCR, #8
A, #8
dir, #8
io, #8
addr16 instruction 5
CMP
A
A, dir
A, dir
ADDC
SUB
ADD
20
LINK
ADDL
ADDW
#imm8
A, #32
EXT
@A
PCB
A
JCTX
SUBDC
ADDDC
NEG
NCC
INT9
A
CMR
10
NOP
00
APPENDIX
Table B.9-2 Basic Page Map
+F
+E
+D
+C
+B
+A
+9
+8
+7
+6
+5
+4
+3
+2
+1
+0
10
MOVB
io:bp, A
20
30
CLRB
io:bp
40
50
SETB
io:bp
60
70
BBC
io;bp, rel
80
90
BBS
io:bp, rel
A0
B0
MOVB
MOVB A, MOVB
MOVB
CLRB
CLRB
SETB
SETB
BBC
BBC
BBS
BBS
A, dir:bp addr16:bp
dir:bp, A addr16:bp,A
dir:bp addr16:bp
dir:bp addr16:bp dir:bp, rel addr16:bp,rel dir:bp, rel addr16:bp,rel
MOVB
A, io:bp
00
WBTS
io:bp
C0
D0
WBTC
io:bp
E0
SBBS
addr16:bp
F0
APPENDIX B Instructions
Table B.9-3 Bit Operation Instruction Map (First Byte = 6CH)
663
664
MOVSI
MOVSD
PCB, PCB
PCB, DTB
PCB, ADB
PCB, SPB
DTB, PCB
DTB, DTB
DTB, ADB
DTB, SPB
ADB, PCB
ADB, DTB
ADB, ADB
ADB, SPB
SPB, PCB
SPB, DTB
SPB, ADB
SPB, SPB
+1
+2
+3
+4
+5
+6
+7
+8
+9
+A
+B
+C
+D
+E
+F
10
+0
00
MOVSWI
20
MOVSWD
30
40
50
60
70
90
A0
B0
C0
SPB
ADB
DTB
SPB
ADB
DTB
SPB
ADB
DTB
SPB
ADB
DTB
SPB
ADB
DTB
SCEQI
SCEQD
SCWEQI SCWEQD FILSI
PCB
PCB
PCB
PCB
PCB
80
D0
FILSI
SPB
ADB
DTB
PCB
E0
F0
APPENDIX
Table B.9-4 Character String Operation Instruction Map (First Byte = 6EH)
LSLW
LSLL
LSL
MOVW
MOVW
A, R0
A, R0
A, R0 @RL2+d8, A A, @RL2+d8
MOVW
MOVW
NRML
A, @A @AL, AH
A, R0
ASRW
ASRL
ASR
MOVW
MOVW
A, R0
A, R0
A, R0 @RL3+d8, A A, @RL3+d8
LSRW
LSRL
LSR
A, R0
A, R0
A, R0
+D
+E
+F
MOVW
MOVW
@RL1+d8, A A, @RL1+d8
MOVW
MOVW
@RL0+d8, A A, @RL0+d8
+C
+B
+A
+9
+8
A
MOV
MOV
MOVX
MOV
MOV
A, PCB
A, @A A, @RL3+d8 @RL3+d8, A A, @RL3+d8
+6
ROLC
MOV
MOV
A, @A @AL, AH
+5
A
MOV
MOV
MOVX
MOV
MOV
A, DPR
DPR, A A, @RL2+d8 @RL2+d8, A A, @RL2+d8
+4
ROLC
MOV
MOV
A, USB
USB, A
+3
+7
MOV
MOV
MOVX
MOV
MOV
A, SSB
SSB, A A, @RL1+d8 @RL1+d8, A A, @RL1+d8
+2
40
MOV
MOV
A, ADB
ADB, A
30
+1
20
MOV
MOV
MOVX
MOV
MOV
A, DTB
DTB, A A, @RL0+d8 @RL0+d8, A A, @RL0+d8
10
+0
00
50
DIVU
MULW
MUL
60
A
A
A
70
80
90
A0
B0
C0
D0
E0
F0
APPENDIX B Instructions
Table B.9-5 2-byte Instruction Map (First Byte = 6FH)
665
666
50
90
B0
D0
@RW1, @RW1+d16 CMPL
CMPL A, ANDL
ANDL A, ORL
ORL A,
XORL
XORL A,
#16, rel
#16, rel A,@RW1 @RW1+d16 A,@RW1 @RW1+d16 A,@RW1 @RW1+d16 A,@RW1 @RW1+d16
@RW2, @RW2+d16 CMPL
CMPL A, ANDL
ANDL A, ORL
ORL A,
XORL
XORL A,
#16, rel
#16, rel A,@RW2 @RW2+d16 A,@RW2 @RW2+d16 A,@RW2 @RW2+d16 A,@RW2 @RW2+d16
@RW3, @RW3+d16 CMPL
CMPL A, ANDL
ANDL A, ORL
ORL A,
XORL
XORL A,
#16, rel
#16, rel A,@RW3 @RW3+d16 A,@RW3 @RW3+d16 A,@RW3 @RW3+d16 A,@RW3 @RW3+d16
SUBL
SUBL A,
A, RL2 @RW5+d8
SUBL
SUBL A,
A, RL3 @RW6+d8
SUBL
SUBL A,
A, RL3 @RW7+d8
ADDL
ADDL A,
A, RL2 @RW5+d8
ADDL
ADDL A,
A, RL3 @RW6+d8
ADDL
ADDL A,
A, RL3 @RW7+d8
ADDL
ADDL A, SUBL
SUBL A,
A,@RW0 @RW0+d16 A,@RW0 @RW0+d16
ADDL
ADDL A, SUBL
SUBL A,
A,@RW1 @RW1+d16 A,@RW1 @RW1+d16
ADDL
ADDL A, SUBL
SUBL A,
A,@RW2 @RW2+d16 A,@RW2 @RW2+d16
ADDL
ADDL A, SUBL
SUBL A,
A,@RW3 @RW3+d16 A,@RW3 @RW3+d16
ADDL
ADDL A, SUBL
SUBL A, Use
@RW0+RW7 CMPL
CMPL A, ANDL
ANDL A, ORL
ORL A,
XORL
XORL A, Use
@RW0+RW7
A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 prohibited
#16, rel A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 prohibited
,#8, rel
ADDL
ADDL A, SUBL
SUBL A, Use
@RW1+RW7 CMPL
CMPL A, ANDL
ANDL A, ORL
ORL A,
XORL
XORL A, Use
@RW1+RW7
A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 prohibited
#16, rel A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 prohibited
,#8, rel
ADDL
ADDL A,
A,@RW2+ @PC+d16
ADDL
ADDL A, SUBL
SUBL A, Use
A,@RW3+
addr16 A,@RW3+
addr16 prohibited
+5
+6
+7
+8
+9
+A
+B
+C
+D
+E
+F
SUBL
SUBL A,
A,@RW2+ @PC+d16
@RW0, @RW0+d16 CMPL
CMPL A, ANDL
ANDL A, ORL
ORL A,
XORL
XORL A,
#16, rel
#16, rel A,@RW0 @RW0+d16 A,@RW0 @RW0+d16 A,@RW0 @RW0+d16 A,@RW0 @RW0+d16
SUBL
SUBL A,
A, RL2 @RW4+d8
Use
prohibited
ANDL
ANDL A,
A,@RW2+ @PC+d16
ANDL
ANDL A,
A, RL3 @RW7+d8
ANDL
ANDL A,
A, RL3 @RW6+d8
ANDL
ANDL A,
A, RL2 @RW5+d8
ANDL
ANDL A,
A, RL2 @RW4+d8
ORL
ORL A,
A,@RW2+ @PC+d16
ORL
ORL A,
A, RL3 @RW7+d8
ORL
ORL A,
A, RL3 @RW6+d8
ORL
ORL A,
A, RL2 @RW5+d8
ORL
ORL A,
A, RL2 @RW4+d8
XORL
XORL A,
A,@RW2+ @PC+d16
XORL
XORL A,
A, RL3 @RW7+d8
XORL
XORL A,
A, RL3 @RW6+d8
XORL
XORL A,
A, RL2 @RW5+d8
XORL
XORL A,
A, RL2 @RW4+d8
XORL
XORL A,
A, RL1 @RW3+d8
addr16,
,#8, rel
Use
@PC+d16,
prohibited
,#8, rel
@RW3, @RW3+d16
#8, rel
,#8, rel
@RW2, @RW2+d16
#8, rel
,#8, rel
@RW1, @RW1+d16
#8, rel
,#8, rel
@RW0, @RW0+d16
#8, rel
,#8, rel
R7, @RW7+d8,
#8, rel
#8, rel
R6, @RW6+d8,
#8, rel
#8, rel
R5, @RW5+d8,
#8, rel
#8, rel
R4, @RW4+d8,
#8, rel
#8, rel
R3, @RW3+d8,
#8, rel
#8, rel
addr16, CMPL
CMPL A, ANDL
ANDL A, ORL
ORL A,
XORL
XORL A, Use
#16, rel A,@RW3+
addr16 A,@RW3+
addr16 A,@RW3+
addr16 A,@RW3+
addr16 prohibited
@PC+d16, CMPL
CMPL A,
#16, rel A,@RW2+ @PC+d16
RW7, @RW7+d8 CMPL
CMPL A,
#16, rel
#16, rel
A, RL3 @RW7+d8
RW6, @RW6+d8 CMPL
CMPL A,
#16, rel
#16, rel
A, RL3 @RW6+d8
RW5, @RW5+d8 CMPL
CMPL A,
#16, rel
#16, rel
A, RL2 @RW5+d8
RW4, @RW4+d8 CMPL
CMPL A,
#16, rel
#16, rel
A, RL2 @RW4+d8
ORL
ORL A,
A, RL1 @RW3+d8
R2, @RW2+d8,
#8, rel
#8, rel
R1, @RW1+d8,
#8, rel
#8, rel
ADDL
ADDL A,
A, RL2 @RW4+d8
ANDL
ANDL A,
A, RL1 @RW3+d8
XORL
XORL A,
A, RL1 @RW2+d8
XORL
XORL A,
A, RL0 @RW1+d8
+4
RW3, @RW3+d8 CMPL
CMPL A,
#16, rel
#16, rel
A, RL1 @RW3+d8
ORL
ORL A,
A, RL1 @RW2+d8
ORL
ORL A,
A, RL0 @RW1+d8
SUBL
SUBL A,
A, RL1 @RW3+d8
ANDL
ANDL A,
A, RL1 @RW2+d8
ANDL
ANDL A,
A, RL0 @RW1+d8
ADDL
ADDL A,
A, RL1 @RW3+d8
RW2, @RW2+d8 CMPL
CMPL A,
#16, rel
#16, rel
A, RL1 @RW2+d8
RW1, @RW1+d8 CMPL
CMPL A,
#16, rel
#16, rel
A, RL0 @RW1+d8
+3
CBNE ↓
F0
R0, @RW0+d8,
#8, rel
#8, rel
CBNE ↓
E0
SUBL
SUBL A,
A, RL1 @RW2+d8
XORL
XORL A,
A, RL0 @RW0+d8
C0
ADDL
ADDL A,
A, RL1 @RW2+d8
ORL
ORL A,
A, RL0 @RW0+d8
A0
+2
ANDL
ANDL A,
A, RL0 @RW0+d8
80
SUBL
SUBL A,
A, RL0 @RW1+d8
70
ADDL
ADDL A,
A, RL0 @RW1+d8
60
RW0, @RW0+d8 CMPL
CMPL A,
#16, rel
#16, rel
A, RL0 @RW0+d8
CWBNE ↓ CWBNE ↓
40
+1
30
+0
20
SUBL
SUBL A,
A, RL0 @RW0+d8
10
ADDL
ADDL A,
A, RL0 @RW0+d8
00
APPENDIX
Table B.9-6 ea Instruction 1 (First Byte = 70H)
JMPP
JMPP
CALLP
CALLP
INCL
INCL
DECL
DECL
MOVL
MOVL A, MOVL
MOVL
MOV
MOV
MOVEA
MOVEA A,
@RL3 @@RW7+d8
@RL3 @@RW7+d8
RL3 @RW7+d8
RL3 @RW7+d8
A, RL3 @RW7+d8
RL3, A @RW7+d8,A
R7, #8 @RW7+d8,#8
A, RW7 @RW7+d8
JMPP
JMPP @
CALLP
CALLP @
INCL
INCL
DECL
DECL
MOVL
MOVL A,
MOVL
MOVL
MOV
MOV
MOVEA
MOVEA A,
@@RW0 @RW0+d16 @@RW0 @RW0+d16
@RW0 @RW0+d16
@RW0 @RW0+d16 A,@RW0 @RW0+d16 @RW0,A @RW0+d16,A @RW0, #8 @RW0+d16,#8
A,@RW0 @RW0+d16
JMPP
JMPP @
CALLP
CALLP @
INCL
INCL
DECL
DECL
MOVL
MOVL A,
MOVL
MOVL
MOV
MOV
MOVEA
MOVEA A,
@@RW1 @RW1+d16 @@RW1 @RW1+d16
@RW1 @RW1+d16
@RW1 @RW1+d16 A,@RW1 @RW1+d16 @RW1,A @RW1+d16,A @RW1, #8 @RW1+d16,#8
A,@RW1 @RW1+d16
JMPP
JMPP @
CALLP
CALLP @
INCL
INCL
DECL
DECL
MOVL
MOVL A,
MOVL
MOVL
MOV
MOV
MOVEA
MOVEA A,
@@RW2 @RW2+d16 @@RW2 @RW2+d16
@RW2 @RW2+d16
@RW2 @RW2+d16 A,@RW2 @RW2+d16 @RW2,A @RW2+d16,A @RW2, #8 @RW2+d16,#8
A,@RW2 @RW2+d16
JMPP
JMPP @
CALLP
CALLP @
INCL
INCL
DECL
DECL
MOVL
MOVL A,
MOVL
MOVL
MOV
MOV
MOVEA
MOVEA A,
@@RW3 @RW3+d16 @@RW3 @RW3+d16
@RW3 @RW3+d16
@RW3 @RW3+d16 A,@RW3 @RW3+d16 @RW3,A @RW3+d16,A @RW3, #8 @RW3+d16,#8
A,@RW3 @RW3+d16
JMPP
JMPP @
CALLP
CALLP @
INCL
INCL
DECL
DECL
MOVL
MOVL A,
MOVL
MOVL
MOV
MOV
MOVEA
MOVEA A,
@@RW0+ @RW0+RW7 @@RW0+ @RW0+RW7 @RW0+ @RW0+RW7 @RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 @RW0+,A @RW0+RW7,A @RW0+, #8 @RW0+RW7,#8 A,@RW0+ @RW0+RW7
JMPP
JMPP @
CALLP
CALLP @
INCL
INCL
DECL
DECL
MOVL
MOVL A,
MOVL
MOVL
MOV
MOV
MOVEA
MOVEA A,
@@RW1+ @RW1+RW7 @@RW1+ @RW1+RW7 @RW1+ @RW1+RW7 @RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 @RW1+,A @RW1+RW7,A @RW1+, #8 @RW1+RW7,#8 A,@RW1+ @RW1+RW7
JMPP
JMPP
CALLP
CALLP
INCL
INCL
DECL
DECL
MOVL
MOVL A, MOVL
MOVL
MOV
MOV
MOVEA
MOVEA A,
@@RW2+ @@PC+d16 @@RW2+ @@PC+d16
@RW2+ @PC+d16
@RW2+ @PC+d16 A,@RW2+ @PC+d16 @RW2+,A @PC+d16, A @RW2+, #8 @PC+d16, #8 A,@RW2+ @PC+d16
JMPP
JMPP
CALLP
CALLP
INCL
INCL
DECL
DECL
MOVL
MOVL A, MOVL
MOVL
MOV
MOV
MOVEA
MOVEA A,
@@RW3+ @addr16 @@RW3+ @addr16 @RW3+
addr16 @RW3+
addr16 A,@RW3+
addr16 @RW3+,A
addr16, A @RW3+, #8
addr16, #8 A,@RW3+
addr16
+8
+9
+A
+B
+C
+D
+E
+F
F0
+7
E0
JMPP
JMPP
CALLP
CALLP
INCL
INCL
DECL
DECL
MOVL
MOVL A, MOVL
MOVL
MOV
MOV
MOVEA
MOVEA A,
@RL3 @@RW6+d8
@RL3 @@RW6+d8
RL3 @RW6+d8
RL3 @RW6+d8
A, RL3 @RW6+d8
RL3, A @RW6+d8,A
R6, #8 @RW6+d8,#8
A, RW6 @RW6+d8
D0
+6
C0
JMPP
JMPP
CALLP
CALLP
INCL
INCL
DECL
DECL
MOVL
MOVL A, MOVL
MOVL
MOV
MOV
MOVEA
MOVEA A,
@RL2 @@RW5+d8
@RL2 @@RW5+d8
RL2 @RW5+d8
RL2 @RW5+d8
A, RL2 @RW5+d8
RL2, A @RW5+d8,A
R5, #8 @RW5+d8,#8
A, RW5 @RW5+d8
B0
+5
A0
JMPP
JMPP
CALLP
CALLP
INCL
INCL
DECL
DECL
MOVL
MOVL A, MOVL
MOVL
MOV
MOV
MOVEA
MOVEA A,
@RL2 @@RW4+d8
@RL2 @@RW4+d8
RL2 @RW4+d8
RL2 @RW4+d8
A, RL2 @RW4+d8
RL2, A @RW4+d8,A
R4, #8 @RW4+d8,#8
A, RW4 @RW4+d8
90
+4
80
JMPP
JMPP
CALLP
CALLP
INCL
INCL
DECL
DECL
MOVL
MOVL A, MOVL
MOVL
MOV
MOV
MOVEA
MOVEA A,
@RL1 @@RW3+d8
@RL1 @@RW3+d8
RL1 @RW3+d8
RL1 @RW3+d8
A, RL1 @RW3+d8
RL1, A @RW3+d8,A
R3, #8 @RW3+d8,#8
A, RW3 @RW3+d8
70
+3
60
JMPP
JMPP
CALLP
CALLP
INCL
INCL
DECL
DECL
MOVL
MOVL A, MOVL
MOVL
MOV
MOV
MOVEA
MOVEA A,
@RL1 @@RW2+d8
@RL1 @@RW2+d8
RL1 @RW2+d8
RL1 @RW2+d8
A, RL1 @RW2+d8
RL1, A @RW2+d8,A
R2, #8 @RW2+d8,#8
A, RW2 @RW2+d8
50
+2
40
JMPP
JMPP
CALLP
CALLP
INCL
INCL
DECL
DECL
MOVL
MOVL A, MOVL
MOVL
MOV
MOV
MOVEA
MOVEA A,
@RL0 @@RW1+d8
@RL0 @@RW1+d8
RL0 @RW1+d8
RL0 @RW1+d8
A, RL0 @RW1+d8
RL0, A @RW1+d8,A
R1, #8 @RW1+d8,#8
A, RW1 @RW1+d8
30
+1
20
JMPP
JMPP
CALLP
CALLP
INCL
INCL
DECL
DECL
MOVL
MOVL A, MOVL
MOVL
MOV
MOV
MOVEA
MOVEA A,
@RL0 @@RW0+d8
@RL0 @@RW0+d8
RL0 @RW0+d8
RL0 @RW0+d8
A, RL0 @RW0+d8
RL0, A @RW0+d8,A
R0, #8 @RW0+d8,#8
A, RW0 @RW0+d8
10
+0
00
APPENDIX B Instructions
Table B.9-7 ea Instruction 2 (First Byte = 71H)
667
668
D0
E0
F0
ROLC
ROLC
RORC
RORC
INC
INC
DEC
DEC
MOV
MOV A,
MOV
MOV
MOVX
MOVX A,
XCH
XCH A,
@RW0+ @RW0+RW7
@RW0+ @RW0+RW7
@RW0+ @RW0+RW7
@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 @RW0+, A @RW0+RW7,A A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7
ROLC
ROLC
RORC
RORC
INC
INC
DEC
DEC
MOV
MOV A,
MOV
MOV
MOVX
MOVX A,
XCH
XCH A,
@RW1+ @RW1+RW7
@RW1+ @RW1+RW7
@RW1+ @RW1+RW7
@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 @RW1+, A @RW1+RW7,A A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7
ROLC
ROLC
RORC
RORC
INC
INC
DEC
DEC
MOV
MOV
A, MOV
MOV
MOVX
MOVX A, XCH
XCH
A,
@RW2+ @PC+d16
@RW2+ @PC+d16
@RW2+ @PC+d16
@RW2+ @PC+d16 A,@RW2+ @PC+d16 @RW2+, A @PC+d16, A A,@RW2+ @PC+d16 A,@RW2+ @PC+d16
ROLC
ROLC
RORC
RORC
INC
INC
DEC
DEC
MOV
MOV
A, MOV
MOV
MOVX
MOVX A, XCH
XCH
A,
@RW3+
addr16 @RW3+
addr16 @RW3+
addr16 @RW3+
addr16 A,@RW3+
addr16 @RW3+, A
addr16, A A,@RW3+
addr16 A,@RW3+
addr16
+D
+E
+F
DEC
MOV
MOV
A, MOV
MOV
MOVX
MOVX A, XCH
XCH
A,
R7 @RW7+d8
A, R7 @RW7+d8
R7, A @RW7+d8,A
A, R7 @RW7+d8
A, R7 @RW7+d8
DEC
MOV
MOV
A, MOV
MOV
MOVX
MOVX A, XCH
XCH
A,
R6 @RW6+d8
A, R6 @RW6+d8
R6, A @RW6+d8,A
A, R6 @RW6+d8
A, R6 @RW6+d8
DEC
MOV
MOV
A, MOV
MOV
MOVX
MOVX A, XCH
XCH
A,
R5 @RW5+d8
A, R5 @RW5+d8
R5, A @RW5+d8,A
A, R5 @RW5+d8
A, R5 @RW5+d8
DEC
MOV
MOV
A, MOV
MOV
MOVX
MOVX A, XCH
XCH
A,
R4 @RW4+d8
A, R4 @RW4+d8
R4, A @RW4+d8,A
A, R4 @RW4+d8
A, R4 @RW4+d8
DEC
MOV
MOV
A, MOV
MOV
MOVX
MOVX A, XCH
XCH
A,
R3 @RW3+d8
A, R3 @RW3+d8
R3, A @RW3+d8,A
A, R3 @RW3+d8
A, R3 @RW3+d8
DEC
MOV
MOV
A, MOV
MOV
MOVX
MOVX A, XCH
XCH
A,
R2 @RW2+d8
A, R2 @RW2+d8
R2, A @RW2+d8,A
A, R2 @RW2+d8
A, R2 @RW2+d8
DEC
MOV
MOV
A, MOV
MOV
MOVX
MOVX A, XCH
XCH
A,
R1 @RW1+d8
A, R1 @RW1+d8
R1, A @RW1+d8,A
A, R1 @RW1+d8
A, R1 @RW1+d8
+C
INC
DEC
R7 @RW7+d8
C0
ROLC
ROLC
RORC
RORC
INC
INC
DEC
DEC
MOV
MOV
A, MOV
MOV
MOVX
MOVX A, XCH
XCH
A,
@RW3 @RW3+d16
@RW3 @RW3+d16
@RW3 @RW3+d16
@RW3 @RW3+d16 A,@RW3 @RW3+d16 @RW3, A @RW3+d16,A
A,@RW3 @RW3+d16 A,@RW3 @RW3+d16
ROLC
RORC
RORC
INC
R7 @RW7+d8
R7 @RW7+d8
ROLC
INC
DEC
R6 @RW6+d8
B0
+B
ROLC
RORC
RORC
INC
R6 @RW6+d8
R6 @RW6+d8
ROLC
INC
DEC
R5 @RW5+d8
A0
ROLC
ROLC
RORC
RORC
INC
INC
DEC
DEC
MOV
MOV
A, MOV
MOV
MOVX
MOVX A, XCH
XCH
A,
@RW2 @RW2+d16
@RW2 @RW2+d16
@RW2 @RW2+d16
@RW2 @RW2+d16 A,@RW2 @RW2+d16 @RW2, A @RW2+d16,A
A,@RW2 @RW2+d16 A,@RW2 @RW2+d16
ROLC
RORC
RORC
INC
R5 @RW5+d8
R5 @RW5+d8
ROLC
INC
DEC
R4 @RW4+d8
90
+A
ROLC
RORC
RORC
INC
R4 @RW4+d8
R4 @RW4+d8
ROLC
INC
DEC
R3 @RW3+d8
INC
DEC
R2 @RW2+d8
INC
DEC
R1 @RW1+d8
80
DEC
MOV
MOV
A, MOV
MOV
MOVX
MOVX A, XCH
XCH
A,
R0 @RW0+d8
A, R0 @RW0+d8
R0, A @RW0+d8,A
A, R0 @RW0+d8
A, R0 @RW0+d8
70
ROLC
ROLC
RORC
RORC
INC
INC
DEC
DEC
MOV
MOV
A, MOV
MOV
MOVX
MOVX A, XCH
XCH
A,
@RW1 @RW1+d16
@RW1 @RW1+d16
@RW1 @RW1+d16
@RW1 @RW1+d16 A,@RW1 @RW1+d16 @RW1, A @RW1+d16,A
A,@RW1 @RW1+d16 A,@RW1 @RW1+d16
ROLC
RORC
RORC
INC
R3 @RW3+d8
R3 @RW3+d8
ROLC
60
INC
DEC
R0 @RW0+d8
50
+9
ROLC
RORC
RORC
INC
R2 @RW2+d8
R2 @RW2+d8
ROLC
40
ROLC
ROLC
RORC
RORC
INC
INC
DEC
DEC
MOV
MOV
A, MOV
MOV
MOVX
MOVX A, XCH
XCH
A,
@RW0 @RW0+d16
@RW0 @RW0+d16
@RW0 @RW0+d16
@RW0 @RW0+d16 A,@RW0 @RW0+d16 @RW0, A @RW0+d16,A
A,@RW0 @RW0+d16 A,@RW0 @RW0+d16
ROLC
RORC
RORC
INC
R1 @RW1+d8
R1 @RW1+d8
ROLC
30
ROLC
RORC
RORC
INC
R0 @RW0+d8
R0 @RW0+d8
20
ROLC
10
+8
+7
+6
+5
+4
+3
+2
+1
+0
00
APPENDIX
Table B.9-8 ea Instruction 3 (First Byte = 72H)
JMP
JMP @
CALL
CALL @
INCW
INCW @ DECW
DECW
MOVW
MOVW A, MOVW
MOVW
MOVW
MOVW
XCHW
XCHW A,
@@RW3 @RW3+d16 @@RW3 @RW3+d16 @RW3 @RW3+d16
@RW3 @RW3+d16 A,@RW3 @RW3+d16 @RW3, A @RW3+d16,A @RW3, #16 @RW3+d16,#16 A,@RW3 @RW3+d16
+B
JMP
JMP
CALL
CALL
INCW
INCW
DECW
DECW
MOVW
MOVW A, MOVW
MOVW
MOVW
MOVW
XCHW
XCHW A,
@@RW3+ @addr16 @@RW3+ @addr16 @RW3+
addr16 @RW3+
addr16 A,@RW3+
addr16 @RW3+, A
addr16, A @RW3+, #16
addr16, #16 A,@RW3+
addr16
INCW @
+F
INCW
JMP
JMP
CALL
CALL
INCW
INCW
DECW
DECW
MOVW
MOVW A, MOVW
MOVW
MOVW
MOVW
XCHW
XCHW A,
@@RW2+ @@PC+d16 @@RW2+ @@PC+d16 @RW2+ @@PC+d16
@RW2+ @PC+d16 A,@RW2+ @PC+d16 @RW2+, A @PC+d16, A @RW2+, #16 @PC+d16, #16 A,@RW2+ @PC+d16
CALL @
+E
CALL
DECW
DECW
MOVW
MOVW A,
MOVW
MOVW
MOVW
MOVW
XCHW
XCHW A,
@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 @RW1+, A @RW1+RW7,A @RW1+, #16 @RW1+RW7,#16 A,@RW1+ @RW1+RW7
XCHW
XCHW A,
A, RW7 @RW7+d8
XCHW
XCHW A,
A, RW6 @RW6+d8
XCHW
XCHW A,
A, RW5 @RW5+d8
+D @@RW1+ @RW1+RW7 @@RW1+ @RW1+RW7 @RW1+ @RW1+RW7
INCW @
MOVW
MOVW
RW7, #16 @RW7+d8,#16
MOVW
MOVW
RW6, #16 @RW6+d8,#16
MOVW
MOVW
RW5, #16 @RW5+d8,#16
XCHW
XCHW A,
A, RW4 @RW4+d8
DECW
DECW
MOVW
MOVW A,
MOVW
MOVW
MOVW
MOVW
XCHW
XCHW A,
@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 @RW0+, A @RW0+RW7,A @RW0+, #16 @RW0+RW7,#16 A,@RW0+ @RW0+RW7
INCW
INCW
INCW
DECW
DECW
MOVW
MOVW A, MOVW
MOVW
RW7 @RW7+d8
RW7 @RW7+d8
A, RW7 @RW7+d8
RW7, A @RW7+d8,A
INCW
INCW
DECW
DECW
MOVW
MOVW A, MOVW
MOVW
RW6 @RW6+d8
RW6 @RW6+d8
A, RW6 @RW6+d8
RW6, A @RW6+d8,A
INCW
INCW
DECW
DECW
MOVW
MOVW A, MOVW
MOVW
RW5 @RW5+d8
RW5 @RW5+d8
A, RW5 @RW5+d8
RW5, A @RW5+d8,A
MOVW
MOVW
RW4, #16 @RW4+d8,#16
+C @@RW0+ @RW0+RW7 @@RW0+ @RW0+RW7 @RW0+ @RW0+RW7
JMP @
JMP
JMP @
CALL
CALL @
INCW
INCW @ DECW
DECW
MOVW
MOVW A, MOVW
MOVW
MOVW
MOVW
XCHW
XCHW A,
@@RW2 @RW2+d16 @@RW2 @RW2+d16 @RW2 @RW2+d16
@RW2 @RW2+d16 A,@RW2 @RW2+d16 @RW2, A @RW2+d16,A @RW2, #16 @RW2+d16,#16 A,@RW2 @RW2+d16
+A
JMP
JMP
JMP @
CALL
CALL @
INCW
INCW @ DECW
DECW
MOVW
MOVW A, MOVW
MOVW
MOVW
MOVW
XCHW
XCHW A,
@@RW1 @RW1+d16 @@RW1 @RW1+d16 @RW1 @RW1+d16
@RW1 @RW1+d16 A,@RW1 @RW1+d16 @RW1, A @RW1+d16,A @RW1, #16 @RW1+d16,#16 A,@RW1 @RW1+d16
+9
CALL @
JMP
JMP @
CALL
CALL @
INCW
INCW @ DECW
DECW
MOVW
MOVW A, MOVW
MOVW
MOVW
MOVW
XCHW
XCHW A,
@@RW0 @RW0+d16 @@RW0 @RW0+d16 @RW0 @RW0+d16
@RW0 @RW0+d16 A,@RW0 @RW0+d16 @RW0,A @RW0+d16,A @RW0, #16 @RW0+d16,#16 A,@RW0 @RW0+d16
+8
CALL
CALL
CALL
RW7 @@RW7+d8
JMP
JMP
@RW7 @@RW7+d8
+7
JMP @
CALL
CALL
RW6 @@RW6+d8
JMP
JMP
@RW6 @@RW6+d8
+6
JMP
CALL
CALL
RW5 @@RW5+d8
JMP
JMP
@RW5 @@RW5+d8
+5
INCW
INCW
DECW
DECW
MOVW
MOVW A, MOVW
MOVW
RW4 @RW4+d8
RW4 @RW4+d8
A, RW4 @RW4+d8
RW4, A @RW4+d8,A
XCHW
XCHW A,
A, RW3 @RW3+d8
XCHW
XCHW A,
A, RW2 @RW2+d8
XCHW
XCHW A,
A, RW1 @RW1+d8
CALL
CALL
RW4 @@RW4+d8
MOVW
MOVW
RW3, #16 @RW3+d8,#16
MOVW
MOVW
RW2, #16 @RW2+d8,#16
MOVW
MOVW
RW1, #16 @RW1+d8,#16
JMP
JMP
@RW4 @@RW4+d8
INCW
INCW
DECW
DECW
MOVW
MOVW A, MOVW
MOVW
RW3 @RW3+d8
RW3 @RW3+d8
A, RW3 @RW3+d8
RW3, A @RW3+d8,A
INCW
INCW
DECW
DECW
MOVW
MOVW A, MOVW
MOVW
RW2 @RW2+d8
RW2 @RW2+d8
A, RW2 @RW2+d8
RW2, A @RW2+d8,A
INCW
INCW
DECW
DECW
MOVW
MOVW A, MOVW
MOVW
RW1 @RW1+d8
RW1 @RW1+d8
A, RW1 @RW1+d8
RW1, A @RW1+d8,A
+4
F0
XCHW
XCHW A,
A, RW0 @RW0+d8
E0
CALL
CALL
RW3 @@RW3+d8
D0
MOVW
MOVW
RW0, #16 @RW0+d8,#16
C0
JMP
JMP
@RW3 @@RW3+d8
B0
+3
A0
CALL
CALL
RW2 @@RW2+d8
90
JMP
JMP
@RW2 @@RW2+d8
80
+2
70
CALL
CALL
RW1 @@RW1+d8
60
JMP
JMP
@RW1 @@RW1+d8
50
INCW
INCW
DECW
DECW
MOVW
MOVW A, MOVW
MOVW
RW0 @RW0+d8
RW0 @RW0+d8
A, RW0 @RW0+d8
RW0, A @RW0+d8,A
40
+1
30
CALL
CALL
RW0 @@RW0+d8
20
JMP
JMP
@RW0 @@RW0+d8
10
+0
00
APPENDIX B Instructions
Table B.9-9 ea Instruction 4 (First Byte = 73H)
669
670
ADD
A, SUB
SUB
SUB
ADDC
A, ADDC
A,
ADDC
ADDC A,
A, CMP
CMP
CMP
CMP
A,
A,
A, AND
AND
AND
AND
AND
AND
A,
A,
A, OR
OR
A, XOR
XOR
A, DBNZ
DBNZ @
A,@RW2+ @PC+d16, A,@RW2+ @PC+d16 @RW2+, r PC+d16, r
+F A,@RW3+
ADD
ADD
SUB
SUB
ADDC
ADDC
CMP
CMP
AND
AND
OR
OR
XOR
XOR
DBNZ
DBNZ
A, addr16 A,@RW3+ A, addr16 A,@RW3+ A, addr16 A,@RW3+ A, addr16 A,@RW3+ A, addr16 A,@RW3+
A, addr16 A,@RW3+ A, addr16 @RW3+, r
addr16, r
+E A,@RW2+ @PC+d16 A,@RW2+ @PC+d16 A,@RW2+ @PC+d16 A,@RW2+ @PC+d16 A,@RW2+ @PC+d16
ADD
SUB
CMP
XOR
XOR A,
DBNZ
DBNZ @R
A,@RW1+ @RW1+RW7 @RW1+, r W1+RW7, r
A,
CMP
OR
OR
A,
A,@RW1+ @RW1+RW7
ADD
ADD
ADDC A,
+D A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7
ADDC
XOR
XOR A,
DBNZ
DBNZ @R
A,@RW0+ @RW0+RW7 @RW0+, r W0+RW7, r
A,
OR
OR
A,
A,@RW0+ @RW0+RW7
SUB
+C A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7
SUB
XOR
XOR
A, DBNZ
DBNZ @R
A,@RW3 @RW3+d16 @RW3, r W3+d16, r
ADD
ADD
A, SUB
SUB
A, ADDC
ADDC A, CMP
CMP
A, AND
AND
A, OR
OR
A,
A,@RW3 @RW3+d16 A,@RW3 @RW3+d16 A,@RW3 @RW3+d16 A,@RW3 @RW3+d16 A,@RW3 @RW3+d16 A,@RW3 @RW3+d16
+B
A,
XOR
XOR
A, DBNZ
DBNZ @R
A,@RW2 @RW2+d16 @RW2, r W2+d16, r
ADD
ADD
A, SUB
SUB
A, ADDC
ADDC A, CMP
CMP
A, AND
AND
A, OR
OR
A,
A,@RW2 @RW2+d16 A,@RW2 @RW2+d16 A,@RW2 @RW2+d16 A,@RW2 @RW2+d16 A,@RW2 @RW2+d16 A,@RW2 @RW2+d16
+A
ADD
XOR
XOR
A, DBNZ
DBNZ @R
A,@RW1 @RW1+d16 @RW1, r W1+d16, r
ADD
ADD
A, SUB
SUB
A, ADDC
ADDC A, CMP
CMP
A, AND
AND
A, OR
OR
A,
A,@RW1 @RW1+d16 A,@RW1 @RW1+d16 A,@RW1 @RW1+d16 A,@RW1 @RW1+d16 A,@RW1 @RW1+d16 A,@RW1 @RW1+d16
+9
ADD
XOR
XOR
A, DBNZ
DBNZ @R
A,@RW0 @RW0+d16 @RW0, r W0+d16, r
ADD
ADD
A, SUB
SUB
A, ADDC
ADDC A, CMP
CMP
A, AND
AND
A, OR
OR
A,
A,@RW0 @RW0+d16 A,@RW0 @RW0+d16 A,@RW0 @RW0+d16 A,@RW0 @RW0+d16 A,@RW0 @RW0+d16 A,@RW0 @RW0+d16
ADD
A, SUB
SUB
A, ADDC
ADDC A, CMP
CMP
A, AND
AND
A, OR
OR
A, XOR
XOR
A, DBNZ
DBNZ @
A, R7 @RW7+d8
A, R7 @RW7+d8
A, R7 @RW7+d8
A, R7 @RW7+d8
A, R7 @RW7+d8
A, R7 @RW7+d8
A, R7 @RW7+d8
R7, r RW7+d8, r
ADD
F0
ADD
A, SUB
SUB
A, ADDC
ADDC A, CMP
CMP
A, AND
AND
A, OR
OR
A, XOR
XOR
A, DBNZ
DBNZ @
A, R6 @RW6+d8
A, R6 @RW6+d8
A, R6 @RW6+d8
A, R6 @RW6+d8
A, R6 @RW6+d8
A, R6 @RW6+d8
A, R6 @RW6+d8
R6, r RW6+d8, r
E0
ADD
D0
ADD
A, SUB
SUB
A, ADDC
ADDC A, CMP
CMP
A, AND
AND
A, OR
OR
A, XOR
XOR
A, DBNZ
DBNZ @
A, R5 @RW5+d8
A, R5 @RW5+d8
A, R5 @RW5+d8
A, R5 @RW5+d8
A, R5 @RW5+d8
A, R5 @RW5+d8
A, R5 @RW5+d8
R5, r RW5+d8, r
C0
ADD
B0
ADD
A, SUB
SUB
A, ADDC
ADDC A, CMP
CMP
A, AND
AND
A, OR
OR
A, XOR
XOR
A, DBNZ
DBNZ @
A, R4 @RW4+d8
A, R4 @RW4+d8
A, R4 @RW4+d8
A, R4 @RW4+d8
A, R4 @RW4+d8
A, R4 @RW4+d8
A, R4 @RW4+d8
R4, r RW4+d8, r
A0
ADD
90
ADD
A, SUB
SUB
A, ADDC
ADDC A, CMP
CMP
A, AND
AND
A, OR
OR
A, XOR
XOR
A, DBNZ
DBNZ @
A, R3 @RW3+d8
A, R3 @RW3+d8
A, R3 @RW3+d8
A, R3 @RW3+d8
A, R3 @RW3+d8
A, R3 @RW3+d8
A, R3 @RW3+d8
R3, r RW3+d8, r
80
ADD
70
ADD
A, SUB
SUB
A, ADDC
ADDC A, CMP
CMP
A, AND
AND
A, OR
OR
A, XOR
XOR
A, DBNZ
DBNZ @
A, R2 @RW2+d8
A, R2 @RW2+d8
A, R2 @RW2+d8
A, R2 @RW2+d8
A, R2 @RW2+d8
A, R2 @RW2+d8
A, R2 @RW2+d8
R2, r RW2+d8, r
60
ADD
50
ADD
A, SUB
SUB
A, ADDC
ADDC A, CMP
CMP
A, AND
AND
A, OR
OR
A, XOR
XOR
A, DBNZ
DBNZ @
A, R1 @RW1+d8
A, R1 @RW1+d8
A, R1 @RW1+d8
A, R1 @RW1+d8
A, R1 @RW1+d8
A, R1 @RW1+d8
A, R1 @RW1+d8
R1, r RW1+d8, r
40
ADD
30
ADD
A, SUB
SUB
A, ADDC
ADDC A, CMP
CMP
A, AND
AND
A, OR
OR
A, XOR
XOR
A, DBNZ
DBNZ @
A, R0 @RW0+d8
A, R0 @RW0+d8
A, R0 @RW0+d8
A, R0 @RW0+d8
A, R0 @RW0+d8
A, R0 @RW0+d8
A, R0 @RW0+d8
R0, r RW0+d8, r
20
ADD
10
+8
+7
+6
+5
+4
+3
+2
+1
+0
00
APPENDIX
Table B.9-10 ea Instruction 5 (First Byte = 74H)
NOT
NOT
R2 @RW2+d8
SUB
SUB
SUB
SUB
ADD
SUB
SUB
@RW1+RW7,A @RW1+, A @RW1+RW7,A
ADD @R
@RW0+RW7,A @RW0+, A @RW0+RW7,A
ADD @R
+F
ADD
ADD
@RW3+, A addr16, A
SUB
SUB
@RW3+, A addr16, A
+E @RW2+, A @PC+d16,A @RW2+, A @PC+d16,A
ADD
+D @RW1+, A
ADD
+C @RW0+, A
ADD
NOT
NOT
@RW1+ @RW1+RW7
NOT
NOT
@RW0+ @RW0+RW7
SUBC
SUBC A, NEG
NEG A,
AND
AND
A,@RW3+
addr16 @RW3+
addr16 @RW3+, A addr16, A
OR
OR
@RW3+, A addr16, A
XOR
XOR
@RW3+, A addr16, A
NOT
NOT
@RW3+
addr16
SUBC
SUBC A, NEG
NEG A,
AND
AND
OR
OR
XOR
XOR
NOT
NOT
A,@RW2+ @PC+d16
@RW2+ @PC+d16 @RW2+, A @PC+d16,A @RW2+, A @PC+d16,A @RW2+, A @PC+d16,A @RW2+ @PC+d16
SUBC
SUBC A,
NEG
NEG A,
AND
AND
OR
OR
XOR
XOR
A,@RW1+ @RW1+RW7 @RW1+ @RW1+RW7 @RW1+, A @RW1+RW7,A @RW1+, A @RW1+RW7,A @RW1+, A @RW1+RW7,A
SUBC
SUBC A,
NEG
NEG A,
AND
AND
OR
OR
XOR
XOR
A,@RW0+ @RW0+RW7 @RW0+ @RW0+RW7 @RW0+, A @RW0+RW7,A @RW0+, A @RW0+RW7,A @RW0+, A @RW0+RW7,A
NOT
NOT
@RW3 @RW3+d16
ADD
ADD @R
SUB
SUB
SUBC
SUBC A, NEG
NEG A,
AND
AND
OR
OR
XOR
XOR
@RW3, A @RW3+d16,A @RW3, A @RW3+d16,A A, @RW3 @RW3+d16
@RW3 @RW3+d16 @RW3, A @RW3+d16,A @RW3, A @RW3+d16,A @RW3, A @RW3+d16,A
+B
XOR
NOT
NOT
R7, A @RW7+d8, A
R7 @RW7+d8
XOR
NOT
NOT
R6, A @RW6+d8, A
R6 @RW6+d8
XOR
NOT
NOT
R5, A @RW5+d8, A
R5 @RW5+d8
XOR
NOT
NOT
R4, A @RW4+d8, A
R4 @RW4+d8
XOR
NOT
NOT
R3, A @RW3+d8, A
R3 @RW3+d8
XOR
R2, A @RW2+d8,A
XOR
NOT
NOT
R1, A @RW1+d8, A
R1 @RW1+d8
NOT
NOT
@RW2 @RW2+d16
XOR
F0
ADD
ADD @R
SUB
SUB
SUBC
SUBC A, NEG
NEG A,
AND
AND
OR
OR
XOR
XOR
@RW2, A @RW2+d16,A @RW2, A @RW2+d16,A A, @RW2 @RW2+d16
@RW2 @RW2+d16 @RW2, A @RW2+d16,A @RW2, A @RW2+d16,A @RW2, A @RW2+d16,A
NEG A,
AND
AND
OR
OR
R7 @RW7+d8
R7, A @RW7+d8, A
R7, A @RW7+d8, A
XOR
XOR
XOR
XOR
XOR
XOR
E0
XOR
NOT
NOT
R0, A @RW0+d8, A
R0 @RW0+d8
D0
+A
ADD
SUB
SUB
SUBC
SUBC A, NEG
R7, A @RW7+d8, A
R7, A @RW7+d8, A
A, R7 @RW7+d8
ADD
NEG A,
AND
AND
OR
OR
R6 @RW6+d8
R6, A @RW6+d8, A
R6, A @RW6+d8, A
NEG A,
AND
AND
OR
OR
R5 @RW5+d8
R5, A @RW5+d8, A
R5, A @RW5+d8, A
NEG A,
AND
AND
OR
OR
R4 @RW4+d8
R4, A @RW4+d8, A
R4, A @RW4+d8, A
NEG A,
AND
AND
OR
OR
R3 @RW3+d8
R3, A @RW3+d8, A
R3, A @RW3+d8, A
NEG A,
AND
AND
OR
OR
R2 @RW2+d8
R2, A @RW2+d8,A
R2, A @RW2+d8,A
NEG A,
AND
AND
OR
OR
R1 @RW1+d8
R1, A @RW1+d8, A
R1, A @RW1+d8, A
XOR
C0
NOT
NOT
@RW1 @RW1+d16
ADD
SUB
SUB
SUBC
SUBC A, NEG
R6, A @RW6+d8, A
R6, A @RW6+d8, A
A, R6 @RW6+d8
ADD
B0
ADD
ADD @R
SUB
SUB
SUBC
SUBC A, NEG
NEG A,
AND
AND
OR
OR
XOR
XOR
@RW1, A @RW1+d16,A @RW1, A @RW1+d16,A A, @RW1 @RW1+d16
@RW1 @RW1+d16 @RW1, A @RW1+d16,A @RW1, A @RW1+d16,A @RW1, A @RW1+d16,A
ADD
SUB
SUB
SUBC
SUBC A, NEG
R5, A @RW5+d8, A
R5, A @RW5+d8, A
A, R5 @RW5+d8
ADD
A0
+9
ADD
SUB
SUB
SUBC
SUBC A, NEG
R4, A @RW4+d8, A
R4, A @RW4+d8, A
A, R4 @RW4+d8
ADD
90
NOT
NOT
@RW0 @RW0+d16
ADD
SUB
SUB
SUBC
SUBC A, NEG
R3, A @RW3+d8, A
R3, A @RW3+d8, A
A, R3 @RW3+d8
ADD
80
NEG A,
AND
AND
OR
OR
R0 @RW0+d8
R0, A @RW0+d8, A
R0, A @RW0+d8, A
70
ADD
ADD
SUB
SUB
SUBC
SUBC A, NEG
NEG A,
AND
AND
OR
OR
XOR
XOR
@RW0, A @RW0+d16,A @RW0, A @RW0+d16,A A, @RW0 @RW0+d16
@RW0 @RW0+d16 @RW0, A @RW0+d16,A @RW0, A @RW0+d16,A @RW0, A @RW0+d16,A
ADD
SUB
SUB
SUBC
SUBC A, NEG
R2, A @RW2+d8,A
R2, A @RW2+d8,A
A, R2 @RW2+d8
60
ADD
50
ADD
SUB
SUB
SUBC
SUBC A, NEG
R1, A @RW1+d8, A
R1, A @RW1+d8, A
A, R1 @RW1+d8
40
ADD
30
ADD
SUB
SUB
SUBC
SUBC A, NEG
R0, A @RW0+d8, A
R0, A @RW0+d8, A
A, R0 @RW0+d8
20
ADD
10
+8
+7
+6
+5
+4
+3
+2
+1
+0
00
APPENDIX B Instructions
Table B.9-11 ea Instruction 6 (First Byte = 75H)
671
672
ADDW A, SUBW
ADDW
ADDCW
CMPW
ADDCW A, CMPW
ADDCW A,
ANDW
CMPW A, ANDW
CMPW A,
ORW
ORW
ANDW A, ORW
ANDW A,
ANDW A,
ORW
ORW
ORW
A,
A,
A, XORW
XORW A, DWBNZ
DWBNZ
+F A,@RW3+
ADDW
ADDW A, SUBW
SUBW A, ADDCW
ADDCW A, CMPW
CMPW A, ANDW
ANDW A, ORW
ORW
A, XORW
XORW A, DWBNZ
DWBNZ
addr 16 A,@RW3+ addr 16
A,@RW3+
addr 16 A,@RW3+
addr 16 A,@RW3+
addr 16 A,@RW3+
addr16 A,@RW3+
addr 16 @RW3+, r
addr16, r
+E A,@RW2+ @PC+d16 A,@RW2+ @PC+d16 A,@RW2+ @PC+d16 A,@RW2+ @PC+d16 A,@RW2+ @PC+d16 A,@RW2+ @PC+d16, A,@RW2+ @PC+d16 @RW2+, r @PC+d16,r
SUBW A, ADDCW
SUBW A,
ANDW
XORW
XORW A,
DWBNZ
DWBNZ
A,@RW1+ @RW1+RW7 @RW1+, r @RW1+RW7,r
SUBW
ADDW A,
ADDW
CMPW A,
+D A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7
CMPW
XORW
XORW A,
DWBNZ
DWBNZ
A,@RW0+ @RW0+RW7 @RW0+, r @RW0+RW7,r
ADDCW A,
+C A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7
ADDCW
XORW
XORW A, DWBNZ
DWBNZ
A,@RW3 @RW3+d16 @RW3, r @RW3+d16,r
ADDW
ADDW A, SUBW
SUBW A, ADDCW
ADDCW A, CMPW
CMPW A, ANDW
ANDW A, ORW
ORW
A,
A,@RW3 @RW3+d16 A,@RW3 @RW3+d16 A,@RW3 @RW3+d16 A,@RW3 @RW3+d16 A,@RW3 @RW3+d16 A,@RW3 @RW3+d16
+B
SUBW A,
XORW
XORW A, DWBNZ
DWBNZ
A,@RW2 @RW2+d16 @RW2, r @RW2+d16,r
ADDW
ADDW A, SUBW
SUBW A, ADDCW
ADDCW A, CMPW
CMPW A, ANDW
ANDW A, ORW
ORW
A,
A,@RW2 @RW2+d16 A,@RW2 @RW2+d16 A,@RW2 @RW2+d16 A,@RW2 @RW2+d16 A,@RW2 @RW2+d16 A,@RW2 @RW2+d16
+A
SUBW
XORW
XORW A, DWBNZ
DWBNZ
A,@RW1 @RW1+d16 @RW1, r @RW1+d16,r
ADDW
ADDW A, SUBW
SUBW A, ADDCW
ADDCW A, CMPW
CMPW A, ANDW
ANDW A, ORW
ORW
A,
A,@RW1 @RW1+d16 A,@RW1 @RW1+d16 A,@RW1 @RW1+d16 A,@RW1 @RW1+d16 A,@RW1 @RW1+d16 A,@RW1 @RW1+d16
+9
ADDW A,
XORW
XORW A, DWBNZ
DWBNZ
A,@RW0 @RW0+d16 @RW0, r @RW0+d16,r
ADDW
ADDW A, SUBW
SUBW A, ADDCW
ADDCW A, CMPW
CMPW A, ANDW
ANDW A, ORW
ORW
A,
A,@RW0 @RW0+d16 A,@RW0 @RW0+d16 A,@RW0 @RW0+d16 A,@RW0 @RW0+d16 A,@RW0 @RW0+d16 A,@RW0 @RW0+d16
+8
ADDW
ADDW
ADDW A, SUBW
SUBW A, ADDCW
ADDCW A, CMPW
CMPW A, ANDW
ANDW A, ORW
ORW
A, XORW
XORW A, DWBNZ
DWBNZ
A, RW7 @RW7+d8
A, RW7 @RW7+d8
A, RW7 @RW7+d8
A, RW7 @RW7+d8
A, RW7 @RW7+d8
A, RW7 @RW7+d8
A, RW7 @RW7+d8
RW7, r @RW7+d8,r
F0
+7
E0
ADDW
ADDW A, SUBW
SUBW A, ADDCW
ADDCW A, CMPW
CMPW A, ANDW
ANDW A, ORW
ORW
A, XORW
XORW A, DWBNZ
DWBNZ
A, RW6 @RW6+d8
A, RW6 @RW6+d8
A, RW6 @RW6+d8
A, RW6 @RW6+d8
A, RW6 @RW6+d8
A, RW6 @RW6+d8
A, RW6 @RW6+d8
RW6, r @RW6+d8,r
D0
+6
C0
ADDW
ADDW A, SUBW
SUBW A, ADDCW
ADDCW A, CMPW
CMPW A, ANDW
ANDW A, ORW
ORW
A, XORW
XORW A, DWBNZ
DWBNZ
A, RW5 @RW5+d8
A, RW5 @RW5+d8
A, RW5 @RW5+d8
A, RW5 @RW5+d8
A, RW5 @RW5+d8
A, RW5 @RW5+d8
A, RW5 @RW5+d8
RW5, r @RW5+d8,r
B0
+5
A0
ADDW
ADDW A, SUBW
SUBW A, ADDCW
ADDCW A, CMPW
CMPW A, ANDW
ANDW A, ORW
ORW
A, XORW
XORW A, DWBNZ
DWBNZ
A, RW4 @RW4+d8
A, RW4 @RW4+d8
A, RW4 @RW4+d8
A, RW4 @RW4+d8
A, RW4 @RW4+d8
A, RW4 @RW4+d8
A, RW4 @RW4+d8
RW4, r @RW4+d8,r
90
+4
80
ADDW
ADDW A, SUBW
SUBW A, ADDCW
ADDCW A, CMPW
CMPW A, ANDW
ANDW A, ORW
ORW
A, XORW
XORW A, DWBNZ
DWBNZ
A, RW3 @RW3+d8
A, RW3 @RW3+d8
A, RW3 @RW3+d8
A, RW3 @RW3+d8
A, RW3 @RW3+d8
A, RW3 @RW3+d8
A, RW3 @RW3+d8
RW3, r @RW3+d8,r
70
+3
60
ADDW
ADDW A, SUBW
SUBW A, ADDCW
ADDCW A, CMPW
CMPW A, ANDW
ANDW A, ORW
ORW
A, XORW
XORW A, DWBNZ
DWBNZ
A, RW2 @RW2+d8
A, RW2 @RW2+d8
A, RW2 @RW2+d8
A, RW2 @RW2+d8
A, RW2 @RW2+d8
A, RW2 @RW2+d8
A, RW2 @RW2+d8
RW2, r @RW2+d8,r
50
+2
40
ADDW
ADDW A, SUBW
SUBW A, ADDCW
ADDCW A, CMPW
CMPW A, ANDW
ANDW A, ORW
ORW
A, XORW
XORW A, DWBNZ
DWBNZ
A, RW1 @RW1+d8
A, RW1 @RW1+d8
A, RW1 @RW1+d8
A, RW1 @RW1+d8
A, RW1 @RW1+d8
A, RW1 @RW1+d8
A, RW1 @RW1+d8
RW1, r @RW1+d8,r
30
+1
20
ADDW
ADDW A, SUBW
SUBW A, ADDCW
ADDCW A, CMPW
CMPW A, ANDW
ANDW A, ORW
ORW
A, XORW
XORW A, DWBNZ
DWBNZ
A, RW0 @RW0+d8
A, RW0 @RW0+d8
A, RW0 @RW0+d8
A, RW0 @RW0+d8
A, RW0 @RW0+d8
A, RW0 @RW0+d8
A, RW0 @RW0+d8
RW0, r @RW0+d8,r
10
+0
00
APPENDIX
Table B.9-12 ea Instruction 7 (First Byte = 76H)
NEGW
NEGW
ANDW
ANDW
ORW
ORW
XORW
XORW
NOTW
NOTW
@RW3 @RW3+d16 @RW3, A @RW3+d16,A @RW3, A @RW3+d16,A @RW3, A @RW3+d16,A
@RW3 @RW3+d16
SUBW
SUBW
@RW3+, A addr16, A
ADDW
ADDW
@RW3+, A addr16, A
+F
SUBCW
SUBCW A, NEGW
NEGW
ANDW
ANDW
A,@RW3+
addr16 @RW3+
addr16 @RW3+, A addr16, A
ORW
ORW
@RW3+, A addr16, A
XORW
XORW
@RW3+, A addr16, A
NOTW
NOTW
@RW3+
addr16
SUBCW
SUBCW A, NEGW
NEGW
ANDW
ANDW
ORW
ORW
XORW
XORW
NOTW
NOTW
A,@RW2+ @PC+d16
@RW2+ @PC+d16 @RW2+, A @PC+d16,A @RW2+, A @PC+d16,A @RW2+, A @PC+d16,A
@RW2+ @PC+d16
SUBW
SUBW
@RW2+, A @PC+d16,A
ADDW
ADDW
@RW2+, A @PC+d16,A
+E
SUBCW A,
ADDW
ADDW
SUBW
SUBW
SUBCW
SUBCW A,
NEGW
NEGW
ANDW
ANDW
ORW
ORW
XORW
XORW
NOTW
NOTW
@RW1+, A @RW1+RW7,A @RW1+, A @RW1+RW7,A A,@RW1+ @RW1+RW7 @RW1+ @RW1+RW7 @RW1+, A @RW1+RW7,A @RW1+, A @RW1+RW7,A @RW1+, A @RW1+RW7,A @RW1+ @RW1+RW7
SUBCW
+D
SUBW
SUBCW A,
ADDW
ADDW
SUBW
SUBW
SUBCW
SUBCW A,
NEGW
NEGW
ANDW
ANDW
ORW
ORW
XORW
XORW
NOTW
NOTW
@RW0+, A @RW0+RW7,A @RW0+, A @RW0+RW7,A A,@RW0+ @RW0+RW7 @RW0+ @RW0+RW7 @RW0+, A @RW0+RW7,A @RW0+, A @RW0+RW7,A @RW0+, A @RW0+RW7,A @RW0+ @RW0+RW7
SUBW
SUBCW
+C
ADDW
ADDW
SUBW
SUBCW A,
+B @RW3, A @RW3+d16,A @RW3, A @RW3+d16,A A, @RW3 @RW3+d16
SUBW
SUBCW
NEGW
NEGW
ANDW
ANDW
ORW
ORW
XORW
XORW
NOTW
NOTW
@RW2 @RW2+d16 @RW2, A @RW2+d16,A @RW2, A @RW2+d16,A @RW2, A @RW2+d16,A
@RW2 @RW2+d16
ADDW
ADDW
SUBW
+A @RW2, A @RW2+d16,A @RW2, A @RW2+d16,A A, @RW2 @RW2+d16
SUBW
NEGW
NEGW
ANDW
ANDW
ORW
ORW
XORW
XORW
NOTW
NOTW
@RW1 @RW1+d16 @RW1, A @RW1+d16,A @RW1, A @RW1+d16,A @RW1, A @RW1+d16,A
@RW1 @RW1+d16
ADDW
ADDW
SUBCW A,
+9 @RW1, A @RW1+d16,A @RW1, A @RW1+d16,A A, @RW1 @RW1+d16
SUBCW
NEGW
NEGW
ANDW
ANDW
ORW
ORW
XORW
XORW
NOTW
NOTW
@RW0 @RW0+d16 @RW0, A @RW0+d16,A @RW0, A @RW0+d16,A @RW0, A @RW0+d16,A
@RW0 @RW0+d16
SUBW
NOTW
NOTW
RW7 @RW7+d8
NOTW
NOTW
RW6 @RW6+d8
NOTW
NOTW
RW5 @RW5+d8
+8 @RW0, A @RW0+d16,A @RW0, A @RW0+d16,A A, @RW0 @RW0+d16
SUBW
XORW
XORW
RW7, A @RW7+d8, A
ADDW
ADDW
SUBW
SUBW
SUBCW SUBCW A, NEGW
NEGW
ANDW
ANDW
ORW
ORW
RW7, A @RW7+d8, A
RW7, A @RW7+d8, A
A, RW7 @RW7+d8
RW7 @RW7+d8
RW7, A @RW7+d8, A
RW7, A @RW7+d8, A
+7
ADDW
XORW
XORW
RW6, A @RW6+d8, A
ADDW
ADDW
SUBW
SUBW
SUBCW SUBCW A, NEGW
NEGW
ANDW
ANDW
ORW
ORW
RW6, A @RW6+d8, A
RW6, A @RW6+d8, A
A, RW6 @RW6+d8
RW6 @RW6+d8
RW6, A @RW6+d8, A
RW6, A @RW6+d8, A
+6
ADDW
XORW
XORW
RW5, A @RW5+d8, A
ADDW
ADDW
SUBW
SUBW
SUBCW SUBCW A, NEGW
NEGW
ANDW
ANDW
ORW
ORW
RW5, A @RW5+d8, A
RW5, A @RW5+d8, A
A, RW5 @RW5+d8
RW5 @RW5+d8
RW5, A @RW5+d8, A
RW5, A @RW5+d8, A
+5
NOTW
NOTW
RW4 @RW4+d8
XORW
XORW
RW4, A @RW4+d8, A
ADDW
ADDW
SUBW
SUBW
SUBCW SUBCW A, NEGW
NEGW
ANDW
ANDW
ORW
ORW
RW4, A @RW4+d8, A
RW4, A @RW4+d8, A
A, RW4 @RW4+d8
RW4 @RW4+d8
RW4, A @RW4+d8, A
RW4, A @RW4+d8, A
+4
F0
NOTW
NOTW
RW0 @RW0+d8
E0
NOTW
NOTW
RW3 @RW3+d8
D0
XORW
XORW
RW3, A @RW3+d8, A
C0
ADDW
ADDW
SUBW
SUBW
SUBCW SUBCW A, NEGW
NEGW
ANDW
ANDW
ORW
ORW
RW3, A @RW3+d8, A
RW3, A @RW3+d8, A
A, RW3 @RW3+d8
RW3 @RW3+d8
RW3, A @RW3+d8, A
RW3, A @RW3+d8, A
B0
+3
A0
NOTW
NOTW
RW2 @RW2+d8
90
ADDW
ADDW
SUBW
SUBW
SUBCW SUBCW A, NEGW
NEGW
ANDW
ANDW
ORW
ORW
XORW
XORW
RW2, A @RW2+d8,A
RW2, A @RW2+d8,A
A, RW2 @RW2+d8
RW2 @RW2+d8
RW2, A @RW2+d8,A
RW2, A @RW2+d8,A
RW2, A @RW2+d8,A
80
+2
70
NOTW
NOTW
RW1 @RW1+d8
60
XORW
XORW
RW1, A @RW1+d8, A
50
ADDW
ADDW
SUBW
SUBW
SUBCW SUBCW A, NEGW
NEGW
ANDW
ANDW
ORW
ORW
RW1, A @RW1+d8, A
RW1, A @RW1+d8, A
A, RW1 @RW1+d8
RW1 @RW1+d8
RW1, A @RW1+d8, A
RW1, A @RW1+d8, A
40
+1
30
XORW
XORW
RW0, A @RW0+d8, A
20
ADDW
ADDW
SUBW
SUBW
SUBCW SUBCW A, NEGW
NEGW
ANDW
ANDW
ORW
ORW
RW0, A @RW0+d8, A
RW0, A @RW0+d8, A
A, RW0 @RW0+d8
RW0 @RW0+d8
RW0, A @RW0+d8, A
RW0, A @RW0+d8, A
10
+0
00
APPENDIX B Instructions
Table B.9-13 ea Instruction 8 (First Byte = 77H)
673
674
DIV
DIV
A, DIVW
DIVW A,
A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7
DIV
DIV
A, DIVW
DIVW A,
A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7
MUL
MUL
A, MULW
MULW A, DIVU
DIVU
A, DIVUW
DIVUW A,
A, @RW1 @RW1+d16 A,@RW1 @RW1+d16 A,@RW1 @RW1+d16 A,@RW1 @RW1+d16
MUL
MUL
A, MULW
MULW A, DIVU
DIVU
A, DIVUW
DIVUW A,
A, @RW2 @RW2+d16 A,@RW2 @RW2+d16 A,@RW2 @RW2+d16 A,@RW2 @RW2+d16
MUL
MUL
A, MULW
MULW A, DIVU
DIVU
A, DIVUW
DIVUW A,
A, @RW3 @RW3+d16 A,@RW3 @RW3+d16 A,@RW3 @RW3+d16 A,@RW3 @RW3+d16
MULU
MULU A, MULUW MULUW A,
A,@RW1 @RW1+d16 A,@RW1 @RW1+d16
MULU
MULU A, MULUW MULUW A,
A,@RW2 @RW2+d16 A,@RW2 @RW2+d16
MULU
MULU A, MULUW MULUW A,
A,@RW3 @RW3+d16 A,@RW3 @RW3+d16
MULU
MULU A, MULUW
MULUW A, MUL
MUL A,
MULW
MULW A,
DIVU
DIVU A,
DIVUW
DIVUW A,
A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7
MULU
MULU A, MULUW
MULUW A, MUL
MUL A,
MULW
MULW A,
DIVU
DIVU A,
DIVUW
DIVUW A,
A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7
MULU
MULU A, MULUW
MULUW A, MUL
MUL
A, MULW
MULW A, DIVU
DIVU
A, DIVUW
DIVUW A, DIV
DIV
A, DIVW
DIVW A,
A,@RW2+ @PC+d16 A,@RW2+ @PC+d16 A,@RW2+ @PC+d16 A,@RW2+ @PC+d16 A,@RW2+ @PC+d16 A,@RW2+ @PC+d16
A,@RW2+ @PC+d16
A,@RW2+ @PC+d16
+9
+A
+B
+C
+D
+E
+F A, @RW3+
MULU
DIV
DIV
A, DIVW
DIVW A,
A,@RW3 @RW3+d16 A,@RW3 @RW3+d16
MUL
MUL
A, MULW
MULW A, DIVU
DIVU
A, DIVUW
DIVUW A,
A, @RW0 @RW0+d16 A,@RW0 @RW0+d16 A,@RW0 @RW0+d16 A,@RW0 @RW0+d16
MULU
MULU A, MULUW MULUW A,
A,@RW0 @RW0+d16 A,@RW0 @RW0+d16
+8
MULU A, MULUW
MULUW A, MUL
MUL
A, MULW
MULW A, DIVU
DIVU
A, DIVUW
DIVUW A, DIV
DIV
addr16 A,@RW3+ addr16
A,@RW3+
addr16 A,@RW3+
addr16 A,@RW3+
addr16 A,@RW3+
addr16 A,@RW3+
A, DIVW
DIVW A,
addr16 A,@RW3+
addr16
DIV
DIV
A, DIVW
DIVW A,
A,@RW2 @RW2+d16 A,@RW2 @RW2+d16
DIV
DIV
A, DIVW
DIVW A,
A,@RW1 @RW1+d16 A,@RW1 @RW1+d16
DIV
DIV
A, DIVW
DIVW A,
A,@RW0 @RW0+d16 A,@RW0 @RW0+d16
MULU
MULU A, MULUW MULUW A, MUL
MUL
A, MULW
MULW A, DIVU
DIVU
A, DIVUW
DIVUW A, DIV
DIV
A, DIVW
DIVW A,
A, R7 @RW7+d8
A, RW7 @RW7+d8
A, R7 @RW7+d8
A, RW7 @RW7+d8
A, R7 @RW7+d8
A, RW7 @RW7+d8
A, R7 @RW7+d8
A, RW7 @RW7+d8
F0
+7
E0
MULU
MULU A, MULUW MULUW A, MUL
MUL
A, MULW
MULW A, DIVU
DIVU
A, DIVUW
DIVUW A, DIV
DIV
A, DIVW
DIVW A,
A, R6 @RW6+d8
A, RW6 @RW6+d8
A, R6 @RW6+d8
A, RW6 @RW6+d8
A, R6 @RW6+d8
A, RW6 @RW6+d8
A, R6 @RW6+d8
A, RW6 @RW6+d8
D0
+6
C0
MULU
MULU A, MULUW MULUW A, MUL
MUL
A, MULW
MULW A, DIVU
DIVU
A, DIVUW
DIVUW A, DIV
DIV
A, DIVW
DIVW A,
A, R5 @RW5+d8
A, RW5 @RW5+d8
A, R5 @RW5+d8
A, RW5 @RW5+d8
A, R5 @RW5+d8
A, RW5 @RW5+d8
A, R5 @RW5+d8
A, RW5 @RW5+d8
B0
+5
A0
MULU
MULU A, MULUW MULUW A, MUL
MUL
A, MULW
MULW A, DIVU
DIVU
A, DIVUW
DIVUW A, DIV
DIV
A, DIVW
DIVW A,
A, R4 @RW4+d8
A, RW4 @RW4+d8
A, R4 @RW4+d8
A, RW4 @RW4+d8
A, R4 @RW4+d8
A, RW4 @RW4+d8
A, R4 @RW4+d8
A, RW4 @RW4+d8
90
+4
80
MULU
MULU A, MULUW MULUW A, MUL
MUL
A, MULW
MULW A, DIVU
DIVU
A, DIVUW
DIVUW A, DIV
DIV
A, DIVW
DIVW A,
A, R3 @RW3+d8
A, RW3 @RW3+d8
A, R3 @RW3+d8
A, RW3 @RW3+d8
A, R3 @RW3+d8
A, RW3 @RW3+d8
A, R3 @RW3+d8
A, RW3 @RW3+d8
70
+3
60
MULU
MULU A, MULUW MULUW A, MUL
MUL
A, MULW
MULW A, DIVU
DIVU
A, DIVUW
DIVUW A, DIV
DIV
A, DIVW
DIVW A,
A, R2 @RW2+d8
A, RW2 @RW2+d8
A, R2 @RW2+d8
A, RW2 @RW2+d8
A, R2 @RW2+d8
A, RW2 @RW2+d8
A, R2 @RW2+d8
A, RW2 @RW2+d8
50
+2
40
MULU
MULU A, MULUW MULUW A, MUL
MUL
A, MULW
MULW A, DIVU
DIVU
A, DIVUW
DIVUW A, DIV
DIV
A, DIVW
DIVW A,
A, R1 @RW1+d8
A, RW1 @RW1+d8
A, R1 @RW1+d8
A, RW1 @RW1+d8
A, R1 @RW1+d8
A, RW1 @RW1+d8
A, R1 @RW1+d8
A, RW1 @RW1+d8
30
+1
20
MULU
MULU A, MULUW MULUW A, MUL
MUL
A, MULW
MULW A, DIVU
DIVU
A, DIVUW
DIVUW A, DIV
DIV
A, DIVW
DIVW A,
A, R0 @RW0+d8
A, RW0 @RW0+d8
A, R0 @RW0+d8
A, RW0 @RW0+d8
A, R0 @RW0+d8
A, RW0 @RW0+d8
A, R0 @RW0+d8
A, RW0 @RW0+d8
10
+0
00
APPENDIX
Table B.9-14 ea Instruction 9 (First Byte = 78H)
MOVEA
MOVEA RW1
RW1,RW4 ,@RW4+d8
MOVEA
MOVEA RW1
RW1,RW5 ,@RW5+d8
MOVEA
MOVEA RW1
RW1,RW6 ,@RW6+d8
MOVEA
MOVEA RW1
RW1,RW7 ,@RW7+d8
MOVEA
MOVEA RW1
RW1,@RW0 ,@RW0+d16
MOVEA
MOVEA RW1
RW1,@RW1 ,@RW1+d16
MOVEA
MOVEA RW1
RW1,@RW2 ,@RW2+d16
MOVEA
MOVEA RW1
RW1,@RW3 ,@RW3+d16
MOVEA
MOVEA RW0
RW0,RW4 ,@RW4+d8
MOVEA
MOVEA RW0
RW0,RW5 ,@RW5+d8
MOVEA
MOVEA RW0
RW0,RW6 ,@RW6+d8
MOVEA
MOVEA RW0
RW0,RW7 ,@RW7+d8
MOVEA RW0
MOVEA RW0
MOVEA RW0
MOVEA RW0
MOVEA RW0
MOVEA RW0
MOVEA
MOVEA
MOVEA
MOVEA
MOVEA
MOVEA
+4
+5
+6
+7
50
70
90
B0
C0
D0
F0
MOVEA
MOVEA RW3
RW3,@RW2+ ,@PC+d16
MOVEA
MOVEA RW4
RW4,@RW2+ ,@PC+d16
MOVEA
MOVEA RW7
RW7,@RW2+ ,@PC+d16
MOVEA
MOVEA
MOVEA
MOVEA
RW6,@RW3+ RW6, addr16 [email protected]+ RW7, addr16
MOVEA
MOVEA RW5 MOVEA
MOVEA RW6
RW5,@RW2+ ,@PC+d16
RW6,@RW2+ ,@PC+d16
MOVEA
MOVEA
MOVEA
MOVEA
MOVEA
MOVEA
MOVEA
MOVEA
MOVEA
MOVEA
MOVEA
MOVEA
RW0,@RW3+ RW0, addr16 RW1,@RW3+ RW1, addr16 RW2,@RW3+ RW2, addr16 RW3,@RW3+ RW3, addr16 RW4,@RW3+ RW4, addr16 RW5,@RW3+ RW5, addr16
MOVEA
MOVEA RW2
RW2,@RW2+ ,@PC+d16
+F
MOVEA
MOVEA RW1
RW1,@RW2+ ,@PC+d16
MOVEA
MOVEA RW0
RW0,@RW2+ ,@PC+d16
MOVEA RW1
+E
MOVEA
MOVEA
MOVEA RW5 MOVEA
MOVEA RW6 MOVEA
MOVEA RW7
RW5,@RW1+ ,@RW1+RW7 RW6,@RW1+ ,@RW1+RW7 RW7,@RW1+ ,@RW1+RW7
MOVEA
MOVEA RW7
RW7,@RW3 ,@RW3+d16
MOVEA
MOVEA RW7
RW7,@RW2 ,@RW2+d16
MOVEA
MOVEA RW7
RW7,@RW1 ,@RW1+d16
MOVEA
MOVEA RW7
RW7,@RW0 ,@RW0+d16
MOVEA
MOVEA RW7
RW7,RW7 ,@RW7+d8
MOVEA
MOVEA RW7
RW7,RW6 ,@RW6+d8
MOVEA
MOVEA RW7
RW7,RW5 ,@RW5+d8
MOVEA
MOVEA RW7
RW7,RW4 ,@RW4+d8
MOVEA
MOVEA RW7
RW7,RW3 ,@RW3+d8
MOVEA
MOVEA RW7
RW7,RW2 ,@RW2+d8
MOVEA
MOVEA RW7
RW7,RW1 ,@RW1+d8
MOVEA
MOVEA RW7
RW7,RW0 ,@RW0+d8
E0
MOVEA
MOVEA RW2 MOVEA
MOVEA RW3 MOVEA
MOVEA RW4
RW2,@RW1+ ,@RW1+RW7 RW3,@RW1+ ,@RW1+RW7 RW4,@RW1+ ,@RW1+RW7
MOVEA
MOVEA RW5 MOVEA
MOVEA RW6
RW5,@RW3 ,@RW3+d16 RW6,@RW3 ,@RW3+d16
MOVEA
MOVEA RW5 MOVEA
MOVEA RW6
RW5,@RW2 ,@RW2+d16 RW6,@RW2 ,@RW2+d16
MOVEA
MOVEA RW5 MOVEA
MOVEA RW6
RW5,@RW1 ,@RW1+d16 RW6,@RW1 ,@RW1+d16
MOVEA
MOVEA RW5 MOVEA
MOVEA RW6
RW5,@RW0 ,@RW0+d16 RW6,@RW0 ,@RW0+d16
MOVEA
MOVEA RW5 MOVEA
MOVEA RW6
RW5,RW7 ,@RW7+d8
RW6,RW7 ,@RW7+d8
MOVEA
MOVEA RW5 MOVEA
MOVEA RW6
RW5,RW6 ,@RW6+d8
RW6,RW6 ,@RW6+d8
MOVEA
MOVEA RW5 MOVEA
MOVEA RW6
RW5,RW5 ,@RW5+d8
RW6,RW5 ,@RW5+d8
MOVEA
MOVEA RW5 MOVEA
MOVEA RW6
RW5,RW4 ,@RW4+d8
RW6,RW4 ,@RW4+d8
MOVEA
MOVEA RW5 MOVEA
MOVEA RW6
RW5,RW3 ,@RW3+d8
RW6,RW3 ,@RW3+d8
MOVEA
MOVEA RW5 MOVEA
MOVEA RW6
RW5,RW2 ,@RW2+d8
RW6,RW2 ,@RW2+d8
MOVEA
MOVEA RW5 MOVEA
MOVEA RW6
RW5,RW1 ,@RW1+d8
RW6,RW1 ,@RW1+d8
MOVEA
MOVEA RW5 MOVEA
MOVEA RW6
RW5,RW0 ,@RW0+d8
RW6,RW0 ,@RW0+d8
A0
+D RW0,@RW1+ ,@RW1+RW7 RW1,@RW1+ ,@RW1+RW7
MOVEA
MOVEA RW4
RW4,@RW3 ,@RW3+d16
MOVEA
MOVEA RW4
RW4,@RW2 ,@RW2+d16
MOVEA
MOVEA RW4
RW4,@RW1 ,@RW1+d16
MOVEA
MOVEA RW4
RW4,@RW0 ,@RW0+d16
MOVEA
MOVEA RW4
RW4,RW7 ,@RW7+d8
MOVEA
MOVEA RW4
RW4,RW6 ,@RW6+d8
MOVEA
MOVEA RW4
RW4,RW5 ,@RW5+d8
MOVEA
MOVEA RW4
RW4,RW4 ,@RW4+d8
MOVEA
MOVEA RW4
RW4,RW3 ,@RW3+d8
MOVEA
MOVEA RW4
RW4,RW2 ,@RW2+d8
MOVEA
MOVEA RW4
RW4,RW1 ,@RW1+d8
MOVEA
MOVEA RW4
RW4,RW0 ,@RW0+d8
80
MOVEA
MOVEA RW5 MOVEA
MOVEA RW6 MOVEA
MOVEA RW7
RW5,@RW0+ ,@RW0+RW7 RW6,@RW0+ ,@RW0+RW7 RW7,@RW0+ ,@RW0+RW7
MOVEA
MOVEA RW3
RW3,@RW3 ,@RW3+d16
MOVEA
MOVEA RW3
RW3,@RW2 ,@RW2+d16
MOVEA
MOVEA RW3
RW3,@RW1 ,@RW1+d16
MOVEA
MOVEA RW3
RW3,@RW0 ,@RW0+d16
MOVEA
MOVEA RW3
RW3,RW7 ,@RW7+d8
MOVEA
MOVEA RW3
RW3,RW6 ,@RW6+d8
MOVEA
MOVEA RW3
RW3,RW5 ,@RW5+d8
MOVEA
MOVEA RW3
RW3,RW4 ,@RW4+d8
MOVEA
MOVEA RW3
RW3,RW3 ,@RW3+d8
MOVEA
MOVEA RW3
RW3,RW2 ,@RW2+d8
MOVEA
MOVEA RW3
RW3,RW1 ,@RW1+d8
MOVEA
MOVEA RW3
RW3,RW0 ,@RW0+d8
60
MOVEA
MOVEA RW2 MOVEA
MOVEA RW3 MOVEA
MOVEA RW4
RW2,@RW0+ ,@RW0+RW7 RW3,@RW0+ ,@RW0+RW7 RW4,@RW0+ ,@RW0+RW7
MOVEA
MOVEA RW2
RW2,@RW3 ,@RW3+d16
MOVEA
MOVEA RW2
RW2,@RW2 ,@RW2+d16
MOVEA
MOVEA RW2
RW2,@RW1 ,@RW1+d16
MOVEA
MOVEA RW2
RW2,@RW0 ,@RW0+d16
MOVEA
MOVEA RW2
RW2,RW7 ,@RW7+d8
MOVEA
MOVEA RW2
RW2,RW6 ,@RW6+d8
MOVEA
MOVEA RW2
RW2,RW5 ,@RW5+d8
MOVEA
MOVEA RW2
RW2,RW4 ,@RW4+d8
MOVEA
MOVEA RW2
RW2,RW3 ,@RW3+d8
MOVEA
MOVEA RW2
RW2,RW2 ,@RW2+d8
MOVEA
MOVEA RW2
RW2,RW1 ,@RW1+d8
MOVEA
MOVEA RW2
RW2,RW0 ,@RW0+d8
40
+C RW0,@RW0+ ,@RW0+RW7 RW1,@RW0+ ,@RW0+RW7
+B RW0,@RW3 ,@RW3+d16
+A RW0,@RW2 ,@RW2+d16
+9 RW0,@RW1 ,@RW1+d16
MOVEA RW1
MOVEA
MOVEA RW1
RW1,RW3 ,@RW3+d8
MOVEA
MOVEA RW0
RW0,RW3 ,@RW3+d8
+3
MOVEA
MOVEA
MOVEA RW1
RW1,RW2 ,@RW2+d8
MOVEA
MOVEA RW0
RW0,RW2 ,@RW2+d8
+2
+8 RW0,@RW0 ,@RW0+d16
MOVEA
MOVEA RW1
RW1,RW1 ,@RW1+d8
MOVEA
MOVEA RW0
RW0,RW1 ,@RW1+d8
+1
30
MOVEA
MOVEA RW1
RW1,RW0 ,@RW0+d8
20
MOVEA
MOVEA RW0
RW0,RW0 ,@RW0+d8
10
+0
00
APPENDIX B Instructions
Table B.9-15 MOVEA RWi, ea Instruction (First Byte = 79H)
675
676
MOV
MOV R0, MOV
MOV R1, MOV
MOV R2, MOV
MOV R3, MOV
MOV R4, MOV
MOV R5, MOV
MOV R6, MOV
MOV R7,
R0, R7 @RW7+d8
R1, R7 @RW7+d8
R2, R7 @RW7+d8
R3, R7 @RW7+d8
R4, R7 @RW7+d8
R5, R7 @RW7+d8
R6, R7 @RW7+d8
R7, R7 @RW7+d8
MOV
MOV R0, MOV
MOV R1, MOV
MOV R2, MOV
MOV R3, MOV
MOV R4, MOV
MOV R5, MOV
MOV R6, MOV
MOV R7,
R0,@RW0 @RW0+d16 R1,@RW0 @RW0+d16 R2,@RW0 @RW0+d16 R3,@RW0 @RW0+d16 R4,@RW0 @RW0+d16 R5,@RW0 @RW0+d16 R6,@RW0 @RW0+d16 R7,@RW0 @RW0+d16
MOV
MOV R0, MOV
MOV R1, MOV
MOV R2, MOV
MOV R3, MOV
MOV R4, MOV
MOV R5, MOV
MOV R6, MOV
MOV R7,
R0,@RW1 @RW1+d16 R1,@RW1 @RW1+d16 R2,@RW1 @RW1+d16 R3,@RW1 @RW1+d16 R4,@RW1 @RW1+d16 R5,@RW1 @RW1+d16 R6,@RW1 @RW1+d16 R7,@RW1 @RW1+d16
MOV
MOV R0, MOV
MOV R1, MOV
MOV R2, MOV
MOV R3, MOV
MOV R4, MOV
MOV R5, MOV
MOV R6, MOV
MOV R7,
R0,@RW2 @RW2+d16 R1,@RW2 @RW2+d16 R2,@RW2 @RW2+d16 R3,@RW2 @RW2+d16 R4,@RW2 @RW2+d16 R5,@RW2 @RW2+d16 R6,@RW2 @RW2+d16 R7,@RW2 @RW2+d16
MOV
MOV R0, MOV
MOV R1, MOV
MOV R2, MOV
MOV R3, MOV
MOV R4, MOV
MOV R5, MOV
MOV R6, MOV
MOV R7,
R0,@RW3 @RW3+d16 R1,@RW3 @RW3+d16 R2,@RW3 @RW3+d16 R3,@RW3 @RW3+d16 R4,@RW3 @RW3+d16 R5,@RW3 @RW3+d16 R6,@RW3 @RW3+d16 R7,@RW3 @RW3+d16
MOV R0, MOV R0,
MOV R1, MOV R1,
MOV R2, MOV R2,
MOV R3, MOV R3,
MOV R4, MOV R4,
MOV R5, MOV R5,
MOV R6, MOV R6,
MOV R7, MOV R7,
@RW0+ @RW0+RW7
@RW0+ @RW0+RW7
@RW0+ @RW0+RW7
@RW0+ @RW0+RW7
@RW0+ @RW0+RW7
@RW0+ @RW0+RW7
@RW0+ @RW0+RW7
@RW0+ @RW0+RW7
MOV R0, MOV R0,
MOV R1, MOV R1,
MOV R2, MOV R2,
MOV R3, MOV R3,
MOV R4, MOV R4,
MOV R5, MOV R5,
MOV R6, MOV R6,
MOV R7, MOV R7,
@RW1+ @RW1+RW7
@RW1+ @RW1+RW7
@RW1+ @RW1+RW7
@RW1+ @RW1+RW7
@RW1+ @RW1+RW7
@RW1+ @RW1+RW7
@RW1+ @RW1+RW7
@RW1+ @RW1+RW7
MOV R0, MOV R0, MOV R1, MOV R1, MOV R2, MOV R2, MOV R3, MOV R3, MOV R4, MOV R4, MOV R5, MOV R5, MOV R6, MOV R6, MOV R7, MOV R7,
@RW2+ @PC+d16
@RW2+ @PC+d16
@RW2+ @PC+d16
@RW2+ @PC+d16
@RW2+ @PC+d16
@RW2+ @PC+d16
@RW2+ @PC+d16
@RW2+ @PC+d16
MOV R0, MOV R0, MOV R1, MOV R1, MOV R2, MOV R2, MOV R3, MOV R3, MOV R4, MOV R4, MOV R5, MOV R5, MOV R6, MOV R6, MOV R7, MOV R7,
@RW3+
addr16 @RW3+
addr16
@RW3+
addr16 @RW3+
addr16 @RW3+
addr16 @RW3+
addr16 @RW3+
addr16
@RW3+
addr16
+8
+9
+A
+B
+C
+D
+E
+F
F0
+7
E0
MOV
MOV R0, MOV
MOV R1, MOV
MOV R2, MOV
MOV R3, MOV
MOV R4, MOV
MOV R5, MOV
MOV R6, MOV
MOV R7,
R0, R6 @RW6+d8
R1, R6 @RW6+d8
R2, R6 @RW6+d8
R3, R6 @RW6+d8
R4, R6 @RW6+d8
R5, R6 @RW6+d8
R6, R6 @RW6+d8
R7, R6 @RW6+d8
D0
+6
C0
MOV
MOV R0, MOV
MOV R1, MOV
MOV R2, MOV
MOV R3, MOV
MOV R4, MOV
MOV R5, MOV
MOV R6, MOV
MOV R7,
R0, R5 @RW5+d8
R1, R5 @RW5+d8
R2, R5 @RW5+d8
R3, R5 @RW5+d8
R4, R5 @RW5+d8
R5, R5 @RW5+d8
R6, R5 @RW5+d8
R7, R5 @RW5+d8
B0
+5
A0
MOV
MOV R0, MOV
MOV R1, MOV
MOV R2, MOV
MOV R3, MOV
MOV R4, MOV
MOV R5, MOV
MOV R6, MOV
MOV R7,
R0, R4 @RW4+d8
R1, R4 @RW4+d8
R2, R4 @RW4+d8
R3, R4 @RW4+d8
R4, R4 @RW4+d8
R5, R4 @RW4+d8
R6, R4 @RW4+d8
R7, R4 @RW4+d8
90
+4
80
MOV
MOV R0, MOV
MOV R1, MOV
MOV R2, MOV
MOV R3, MOV
MOV R4, MOV
MOV R5, MOV
MOV R6, MOV
MOV R7,
R0, R3 @RW3+d8
R1, R3 @RW3+d8
R2, R3 @RW3+d8
R3, R3 @RW3+d8
R4, R3 @RW3+d8
R5, R3 @RW3+d8
R6, R3 @RW3+d8
R7, R3 @RW3+d8
70
+3
60
MOV
MOV R0, MOV
MOV R1, MOV
MOV R2, MOV
MOV R3, MOV
MOV R4, MOV
MOV R5, MOV
MOV R6, MOV
MOV R7,
R0, R2 @RW2+d8
R1, R2 @RW2+d8
R2, R2 @RW2+d8
R3, R2 @RW2+d8
R4, R2 @RW2+d8
R5, R2 @RW2+d8
R6, R2 @RW2+d8
R7, R2 @RW2+d8
50
+2
40
MOV
MOV R0, MOV
MOV R1, MOV
MOV R2, MOV
MOV R3, MOV
MOV R4, MOV
MOV R5, MOV
MOV R6, MOV
MOV R7,
R0, R1 @RW1+d8
R1, R1 @RW1+d8
R2, R1 @RW1+d8
R3, R1 @RW1+d8
R4, R1 @RW1+d8
R5, R1 @RW1+d8
R6, R1 @RW1+d8
R7, R1 @RW1+d8
30
+1
20
MOV
MOV R0, MOV
MOV R1, MOV
MOV R2, MOV
MOV R3, MOV
MOV R4, MOV
MOV R5, MOV
MOV R6, MOV
MOV R7,
R0, R0 @RW0+d8
R1, R0 @RW0+d8
R2, R0 @RW0+d8
R3, R0 @RW0+d8
R4, R0 @RW0+d8
R5, R0 @RW0+d8
R6, R0 @RW0+d8
R7, R0 @RW0+d8
10
+0
00
APPENDIX
Table B.9-16 MOV Ri, ea Instruction (First Byte = 7AH)
MOVW
MOVW RW5,
RW5,@RW3 @RW3+d16
MOVW
MOVW
MOVW
MOVW RW1, MOVW
MOVW RW2, MOVW
MOVW RW3, MOVW
MOVW RW4,
RW0,@RW1 @RW1+d16 RW1,@RW1 @RW1+d16 RW2,@RW1 @RW1+d16 RW3,@RW1 @RW1+d16 RW4,@RW1 @RW1+d16
MOVW
MOVW
MOVW
MOVW RW1, MOVW
MOVW RW2, MOVW
MOVW RW3, MOVW
MOVW RW4,
RW0,@RW2 @RW2+d16 RW1,@RW2 @RW2+d16 RW2,@RW2 @RW2+d16 RW3,@RW2 @RW2+d16 RW4,@RW2 @RW2+d16
MOVW
MOVW
MOVW
MOVW RW1, MOVW
MOVW RW2, MOVW
MOVW RW3, MOVW
MOVW RW4,
RW0,@RW3 @RW3+d16 RW1,@RW3 @RW3+d16 RW2,@RW3 @RW3+d16 RW3,@RW3 @RW3+d16 RW4,@RW3 @RW3+d16
MOVW
MOVW
MOVW
MOVW RW1, MOVW
MOVW RW2, MOVW
MOVW RW3, MOVW
MOVW RW4, MOVW
MOVW RW5, MOVW
MOVW RW6, MOVW
MOVW RW7,
RW0,@RW0+ @RW0+RW7 RW1,@RW0+ @RW0+RW7 RW2,@RW0+ @RW0+RW7 RW3,@RW0+ @RW0+RW7 RW4,@RW0+ @RW0+RW7 RW5,@RW0+ @RW0+RW7 RW6,@RW0+ @RW0+RW7 RW7,@RW0+ @RW0+RW7
MOVW
MOVW RW1, MOVW
MOVW RW2, MOVW
MOVW RW3, MOVW
MOVW RW4,
RW1, @RW2+ @PC+d16
RW2, @RW2+ @PC+d16
RW3, @RW2+ @PC+d16
RW4, @RW2+ @PC+d16
MOVW
MOVW
RW1, @RW3+ RW1, addr16
MOVW
RW0, @RW1+
MOVW
MOVW
RW0, @RW2+ @PC+d16
MOVW
MOVW
RW0, @RW3+ RW0, addr16
+9
+A
+B
+C
+D
+E
+F
MOVW
MOVW
RW2, @RW3+ RW2, addr16
MOVW
MOVW
RW3, @RW3+ RW3, addr16
MOVW
MOVW
RW5, @RW3+ RW5, addr16
MOVW
MOVW
RW5, @RW2+ @PC+d16
MOVW
MOVW
RW6, @RW3+ RW6, addr16
MOVW
MOVW RW6,
RW6, @RW2+ @PC+d16
MOVW
MOVW
RW7, @RW3+ RW7, addr16
MOVW
MOVW RW7,
RW7, @RW2+ @PC+d16
MOVW RW7,
@RW1+RW7
MOVW
MOVW RW7,
RW7,@RW3 @RW3+d16
MOVW
MOVW RW7,
RW7,@RW2 @RW2+d16
MOVW
MOVW RW7,
RW7,@RW1 @RW1+d16
MOVW
MOVW RW7,
RW7,@RW0 @RW0+d16
MOVW
MOVW RW7,
RW7, RW7 @RW7+d8
MOVW
MOVW RW7,
RW7, RW6 @RW6+d8
MOVW
MOVW RW7,
RW7, RW5 @RW5+d8
MOVW
MOVW RW7,
RW7, RW4 @RW4+d8
MOVW RW6, MOVW
@RW1+RW7 RW7, @RW1+
MOVW
MOVW RW6,
RW6,@RW3 @RW3+d16
MOVW
MOVW RW6,
RW6,@RW2 @RW2+d16
MOVW
MOVW RW6,
RW6,@RW1 @RW1+d16
MOVW
MOVW RW6,
RW6,@RW0 @RW0+d16
MOVW
MOVW RW6,
RW6, RW7 @RW7+d8
MOVW
MOVW RW6,
RW6, RW6 @RW6+d8
MOVW
MOVW RW6,
RW6, RW5 @RW5+d8
MOVW
MOVW RW6,
RW6, RW4 @RW4+d8
MOVW
MOVW
@RW1+RW7 RW6, @RW1+
MOVW
MOVW RW5,
RW5, RW6 @RW6+d8
MOVW
MOVW RW5,
RW5, RW5 @RW5+d8
MOVW RW4, MOVW
@RW1+RW7 RW5, @RW1+
MOVW
MOVW
RW4, @RW3+ RW4, addr16
MOVW RW3, MOVW
@RW1+RW7 RW4, @RW1+
MOVW
MOVW RW5,
RW5,@RW2 @RW2+d16
MOVW
MOVW
MOVW
MOVW RW1, MOVW
MOVW RW2, MOVW
MOVW RW3, MOVW
MOVW RW4,
RW0,@RW0 @RW0+d16 RW1,@RW0 @RW0+d16 RW2,@RW0 @RW0+d16 RW3,@RW0 @RW0+d16 RW4,@RW0 @RW0+d16
+8
MOVW RW2, MOVW
@RW1+RW7 RW3, @RW1+
MOVW
MOVW RW5,
RW5,@RW1 @RW1+d16
MOVW
MOVW RW1, MOVW
MOVW RW2, MOVW
MOVW RW3, MOVW
MOVW RW4,
RW1, RW7 @RW7+d8
RW2, RW7 @RW7+d8
RW3, RW7 @RW7+d8
RW4, RW7 @RW7+d8
MOVW
MOVW
RW0, RW7 @RW7+d8
+7
MOVW RW1, MOVW
@RW1+RW7 RW2, @RW1+
MOVW
MOVW RW5,
RW5,@RW0 @RW0+d16
MOVW
MOVW RW1, MOVW
MOVW RW2, MOVW
MOVW RW3, MOVW
MOVW RW4,
RW1, RW6 @RW6+d8
RW2, RW6 @RW6+d8
RW3, RW6 @RW6+d8
RW4, RW6 @RW6+d8
MOVW
MOVW
RW0, RW6 @RW6+d8
+6
MOVW
MOVW
@RW1+RW7 RW1, @RW1+
MOVW
MOVW RW5,
RW5, RW7 @RW7+d8
MOVW
MOVW RW1, MOVW
MOVW RW2, MOVW
MOVW RW3, MOVW
MOVW RW4,
RW1, RW5 @RW5+d8
RW2, RW5 @RW5+d8
RW3, RW5 @RW5+d8
RW4, RW5 @RW5+d8
MOVW
MOVW
RW0, RW5 @RW5+d8
+5
MOVW
MOVW RW5,
RW5, RW4 @RW4+d8
MOVW
MOVW RW7,
RW7, RW3 @RW3+d8
MOVW
MOVW RW7,
RW7, RW2 @RW2+d8
MOVW
MOVW RW7,
RW7, RW1 @RW1+d8
MOVW
MOVW RW1, MOVW
MOVW RW2, MOVW
MOVW RW3, MOVW
MOVW RW4,
RW1, RW4 @RW4+d8
RW2, RW4 @RW4+d8
RW3, RW4 @RW4+d8
RW4, RW4 @RW4+d8
MOVW
MOVW RW6,
RW6, RW3 @RW3+d8
MOVW
MOVW RW6,
RW6, RW2 @RW2+d8
MOVW
MOVW RW6,
RW6, RW1 @RW1+d8
MOVW
MOVW
RW0, RW4 @RW4+d8
MOVW
MOVW RW5,
RW5, RW3 @RW3+d8
MOVW
MOVW RW5,
RW5, RW2 @RW2+d8
MOVW
MOVW RW5,
RW5, RW1 @RW1+d8
+4
F0
MOVW
MOVW RW7,
RW7, RW0 @RW0+d8
E0
MOVW
MOVW RW1, MOVW
MOVW RW2, MOVW
MOVW RW3, MOVW
MOVW RW4,
RW1, RW3 @RW3+d8
RW2, RW3 @RW3+d8
RW3, RW3 @RW3+d8
RW4, RW3 @RW3+d8
D0
MOVW
MOVW RW6,
RW6, RW0 @RW0+d8
C0
MOVW
MOVW
RW0, RW3 @RW3+d8
B0
MOVW
MOVW RW5,
RW5, RW0 @RW0+d8
A0
+3
90
MOVW
MOVW RW1, MOVW
MOVW RW2, MOVW
MOVW RW3, MOVW
MOVW RW4,
RW1, RW2 @RW2+d8
RW2, RW2 @RW2+d8
RW3, RW2 @RW2+d8
RW4, RW2 @RW2+d8
80
MOVW
MOVW
RW0, RW2 @RW2+d8
70
+2
60
MOVW
MOVW RW1, MOVW
MOVW RW2, MOVW
MOVW RW3, MOVW
MOVW RW4,
RW1, RW1 @RW1+d8
RW2, RW1 @RW1+d8
RW3, RW1 @RW1+d8
RW4, RW1 @RW1+d8
50
MOVW
MOVW
RW0, RW1 @RW1+d8
40
+1
30
MOVW
MOVW RW1, MOVW
MOVW RW2, MOVW
MOVW RW3, MOVW
MOVW RW4,
RW1, RW0 @RW0+d8
RW2, RW0 @RW0+d8
RW3, RW0 @RW0+d8
RW4, RW0 @RW0+d8
20
MOVW
MOVW
RW0, RW0 @RW0+d8
10
+0
00
APPENDIX B Instructions
Table B.9-17 MOVW RWi, ea Instruction (First Byte = 7BH)
677
678
+F
+E
+D
+C
+B
+A
+9
+8
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
@RW3+, R1 addr16, R1
MOV
MOV
@RW3+, R0 addr16, R0
MOV
MOV
MOV
@RW2+, R1 @PC+d16, R1
@RW2+, R0 @PC+d16, R0
MOV
MOV
MOV
MOV
MOV
@RW0+, R1 @RW0+RW7, R1
MOV
@RW3, R1 @RW3+d16, R1
MOV
@RW2, R1 @RW2+d16, R1
MOV
@RW1, R1 @RW1+d16, R1
MOV
@RW1+, R1 @RW1+RW7, R1
MOV
MOV
@RW0, R1 @RW0+d16, R1
MOV
@RW1+, R0 @RW1+RW7, R0
MOV
@RW0+, R0 @RW0+RW7, R0
MOV
@RW3, R0 @RW3+d16, R0
MOV
@RW2, R0 @RW2+d16, R0
MOV
@RW1, R0 @RW1+d16, R0
MOV
@RW0, R0 @RW0+d16, R0
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
@RW3+, R2 addr16, R2
MOV
@RW2+, R2 @PC+d16, R2
MOV
@RW1+, R2 @RW1+RW7, R2
MOV
@RW0+, R2 @RW0+RW7, R2
MOV
@RW3, R2 @RW3+d16, R2
MOV
@RW2, R2 @RW2+d16, R2
MOV
@RW1, R2 @RW1+d16, R2
MOV
@RW0, R2 @RW0+d16, R2
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
@RW3+, R3 addr16, R3
MOV
@RW2+, R3 @PC+d16, R3
MOV
@RW1+, R3 @RW1+RW7, R3
MOV
@RW0+, R3 @RW0+RW7, R3
MOV
@RW3, R3 @RW3+d16, R3
MOV
@RW2, R3 @RW2+d16, R3
MOV
@RW1, R3 @RW1+d16, R3
MOV
@RW0, R3 @RW0+d16, R3
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
@RW3+, R4 addr16, R4
MOV
@RW2+, R4 @PC+d16, R4
MOV
@RW1+, R4 @RW1+RW7, R4
MOV
@RW0+, R4 @RW0+RW7, R4
MOV
@RW3, R4 @RW3+d16, R4
MOV
@RW2, R4 @RW2+d16, R4
MOV
@RW1, R4 @RW1+d16, R4
MOV
@RW0, R4 @RW0+d16, R4
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
@RW3+, R5 addr16, R5
MOV
@RW2+, R5 @PC+d16, R5
MOV
@RW1+, R5 @RW1+RW7, R5
MOV
@RW0+, R5 @RW0+RW7, R5
MOV
@RW3, R5 @RW3+d16, R5
MOV
@RW2, R5 @RW2+d16, R5
MOV
@RW1, R5 @RW1+d16, R5
MOV
@RW0, R5 @RW0+d16, R5
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
@RW3+, R6 addr16, R6
MOV
@RW2+, R6 @PC+d16, R6
MOV
@RW1+, R6 @RW1+RW7, R6
MOV
@RW0+, R6 @RW0+RW7, R6
MOV
@RW3, R6 @RW3+d16, R6
MOV
@RW2, R6 @RW2+d16, R6
MOV
@RW1, R6 @RW1+d16, R6
MOV
@RW0, R6 @RW0+d16,
R6
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
@RW3+, R7 addr16, R7
MOV
@RW2+, R7 @PC+d16, R7
MOV
@RW1+, R7 @RW1+RW7, R7
MOV
@RW0+, R7 @RW0+RW7, R7
MOV
@RW3, R7 @RW3+d16, R7
MOV
@RW2, R7 @RW2+d16, R7
MOV
@RW1, R7 @RW1+d16, R7
MOV
@RW0, R7 @RW0+d16, R7
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
R7, R0 @RW7+d8, R0
R7, R1 @RW7+d8, R1
R7, R2 @RW7+d8, R2
R7, R3 @RW7+d8, R3
R7, R4 @RW7+d8, R4
R7, R5 @RW7+d8, R5
R7, R6 @RW7+d8, R6
R7, R7 @RW7+d8, R7
F0
+7
E0
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
R6, R0 @RW6+d8, R0
R6, R1 @RW6+d8, R1
R6, R2 @RW6+d8, R2
R6, R3 @RW6+d8, R3
R6, R4 @RW6+d8, R4
R6, R5 @RW6+d8, R5
R6, R6 @RW6+d8, R6
R6, R7 @RW6+d8, R7
D0
+6
C0
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
R5, R0 @RW5+d8, R0
R5, R1 @RW5+d8, R1
R5, R2 @RW5+d8, R2
R5, R3 @RW5+d8, R3
R5, R4 @RW5+d8, R4
R5, R5 @RW5+d8, R5
R5, R6 @RW5+d8, R6
R5, R7 @RW5+d8, R7
B0
+5
A0
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
R4, R0 @RW4+d8, R0
R4, R1 @RW4+d8, R1
R4, R2 @RW4+d8, R2
R4, R3 @RW4+d8, R3
R4, R4 @RW4+d8, R4
R4, R5 @RW4+d8, R5
R4, R6 @RW4+d8, R6
R4, R7 @RW4+d8, R7
90
+4
80
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
R3, R0 @RW3+d8, R0
R3, R1 @RW3+d8, R1
R3, R2 @RW3+d8, R2
R3, R3 @RW3+d8, R3
R3, R4 @RW3+d8, R4
R3, R5 @RW3+d8, R5
R3, R6 @RW3+d8, R6
R3, R7 @RW3+d8, R7
70
+3
60
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
R2, R0 @RW2+d8, R0
R2, R1 @RW2+d8, R1
R2, R2 @RW2+d8, R2
R2, R3 @RW2+d8, R3
R2, R4 @RW2+d8, R4
R2, R5 @RW2+d8, R5
R2, R6 @RW2+d8, R6
R2, R7 @RW2+d8, R7
50
+2
40
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
R1, R0 @RW1+d8, R0
R1, R1 @RW1+d8, R1
R1, R2 @RW1+d8, R2
R1, R3 @RW1+d8, R3
R1, R4 @RW1+d8, R4
R1, R5 @RW1+d8, R5
R1, R6 @RW1+d8, R6
R1, R7 @RW1+d8, R7
30
+1
20
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
R0, R0 @RW0+d8, R0
R0, R1 @RW0+d8, R1
R0, R2 @RW0+d8, R2
R0, R3 @RW0+d8, R3
R0, R4 @RW0+d8, R4
R0, R5 @RW0+d8, R5
R0, R6 @RW0+d8, R6
R0, R7 @RW0+d8, R7
10
+0
00
APPENDIX
Table B.9-18 MOV ea, Ri Instruction (First Byte = 7CH)
MOVW
[email protected]
@RW2, RW1 +d16, RW1
MOVW
[email protected]
@RW3, RW1 +d16, RW1
MOVW
[email protected]
@RW0+, RW1 +RW7,RW1
MOVW
[email protected]
@RW1+,RW1 +RW7,RW1
MOVW
[email protected]
@RW2+,RW1 +d16, RW1
MOVW
MOVW
@RW3+,RW1 addr16, RW1
MOVW
[email protected]
@RW2, RW0 +d16, RW0
MOVW
[email protected]
@RW3, RW0 +d16, RW0
MOVW
[email protected]
@RW0+,RW0 +RW7,RW0
MOVW
[email protected]
@RW1+,RW0 +RW7,RW0
MOVW
[email protected]
@RW2+,RW0 +d16, RW0
MOVW
MOVW
@RW3+,RW0 addr16, RW0
+B
+C
+D
+E
+F
MOVW
MOVW
@RW3+,RW2 addr16, RW2
MOVW
[email protected]
@RW2+,RW2 +d16, RW2
MOVW
[email protected]
@RW1+,RW2 +RW7,RW2
MOVW
[email protected]
@RW0+,RW2 +RW7,RW2
MOVW
[email protected]
@RW3, RW2 +d16, RW2
MOVW
[email protected]
@RW2, RW2 +d16, RW2
MOVW
MOVW
@RW3+,RW3 addr16, RW3
MOVW
[email protected]
@RW2+,RW3 +d16, RW3
MOVW
[email protected]
@RW1+,RW3 -+RW7,RW3
MOVW
[email protected]
@RW0+,RW3 +RW7,RW3
MOVW
[email protected]
@RW3, RW3 +d16, RW3
MOVW
[email protected]
@RW2, RW3 +d16, RW3
MOVW
[email protected]
@RW1, RW3 +d16, RW3
MOVW
MOVW
@RW3+,RW4 addr16, RW4
MOVW
[email protected]
@RW2+,RW4 +d16, RW4
MOVW
[email protected]
@RW1+,RW4 +RW7,RW4
MOVW
[email protected]
@RW0+,RW4 +RW7,RW4
MOVW
[email protected]
@RW3, RW4 +d16, RW4
MOVW
[email protected]
@RW2, RW4 +d16, RW4
MOVW
[email protected]
@RW1, RW4 +d16, RW4
MOVW
MOVW
@RW3+,RW5 addr16, RW5
MOVW
[email protected]
@RW2+,RW5 +d16, RW5
MOVW
[email protected]
@RW1+,RW5 +RW7,RW5
MOVW
[email protected]
@RW0+,RW5 +RW7,RW5
MOVW
[email protected]
@RW3, RW5 +d16, RW5
MOVW
[email protected]
@RW2, RW5 +d16, RW5
MOVW
[email protected]
@RW1, RW5 +d16, RW5
MOVW
MOVW
@RW3+,RW6 addr16, RW6
MOVW
MOVW @PC
@RW2+,RW6 +d16, RW6
MOVW
[email protected]
@RW1+,RW6 +RW7,RW6
MOVW
[email protected]
@RW0+,RW6 +RW7,RW6
MOVW
[email protected]
@RW3, RW6 +d16, RW6
MOVW
[email protected]
@RW2, RW6 +d16, RW6
MOVW
[email protected]
@RW1, RW6 +d16, RW6
MOVW
MOVW
@RW3+,RW7 addr16, RW7
MOVW
[email protected]
@RW2+,RW7 +d16, RW7
MOVW
[email protected]
@RW1+,RW7 +RW7,RW7
MOVW
[email protected]
@RW0+,RW7 +RW7,RW7
MOVW
[email protected]
@RW3, RW7 +d16, RW7
MOVW
[email protected]
@RW2, RW7 +d16, RW7
MOVW
[email protected]
@RW1, RW7 +d16, RW7
MOVW
[email protected]
@RW0, RW7 +d16, RW7
+A
MOVW
[email protected]
@RW1, RW2 +d16, RW2
MOVW
[email protected]
@RW0, RW6 +d16, RW6
MOVW
[email protected]
@RW1, RW1 +d16, RW1
MOVW
[email protected]
@RW0, RW5 +d16, RW5
MOVW
[email protected]
@RW1, RW0 +d16, RW0
MOVW
[email protected]
@RW0, RW4 +d16, RW4
+9
MOVW
[email protected]
@RW0, RW3 +d16, RW3
MOVW
[email protected]
@RW0, RW1 +d16, RW1
MOVW
[email protected]
@RW0, RW0 +d16, RW0
+8
MOVW
[email protected]
@RW0, RW2 +d16, RW2
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
RW7, RW0 @RW7+d8, RW0
RW7, RW1 @RW7+d8, RW1 RW7, RW2 @RW7+d8, RW2 RW7, RW3 @RW7+d8, RW3 RW7, RW4 @RW7+d8, RW4 RW7, RW5 @RW7+d8, RW5 RW7, RW6 @RW7+d8, RW6 RW7, RW7 @RW7+d8, RW7
F0
+7
E0
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
RW6, RW0 @RW6+d8, RW0
RW6, RW1 @RW6+d8, RW1 RW6, RW2 @RW6+d8, RW2 RW6, RW3 @RW6+d8, RW3 RW6, RW4 @RW6+d8, RW4 RW6, RW5 @RW6+d8, RW5 RW6, RW6 @RW6+d8, RW6 RW6, RW7 @RW6+d8, RW7
D0
+6
C0
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
RW5, RW0 @RW5+d8, RW0
RW5, RW1 @RW5+d8, RW1 RW5, RW2 @RW5+d8, RW2 RW5, RW3 @RW5+d8, RW3 RW5, RW4 @RW5+d8, RW4 RW5, RW5 @RW5+d8, RW5 RW5, RW6 @RW5+d8, RW6 RW5, RW7 @RW5+d8, RW7
B0
+5
A0
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
RW4, RW0 @RW4+d8, RW0
RW4, RW1 @RW4+d8, RW1 RW4, RW2 @RW4+d8, RW2 RW4, RW3 @RW4+d8, RW3 RW4, RW4 @RW4+d8, RW4 RW4, RW5 @RW4+d8, RW5 RW4, RW6 @RW4+d8, RW6 RW4, RW7 @RW4+d8, RW7
90
+4
80
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
RW3, RW0 @RW3+d8, RW0
RW3, RW1 @RW3+d8, RW1 RW3, RW2 @RW3+d8, RW2 RW3, RW3 @RW3+d8, RW3 RW3, RW4 @RW3+d8, RW4 RW3, RW5 @RW3+d8, RW5 RW3, RW6 @RW3+d8, RW6 RW3, RW7 @RW3+d8, RW7
70
+3
60
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
RW2, RW0 @RW2+d8, RW0
RW2, RW1 @RW2+d8, RW1 RW2, RW2 @RW2+d8, RW2 RW2, RW3 @RW2+d8, RW3 RW2, RW4 @RW2+d8, RW4 RW2, RW5 @RW2+d8, RW5 RW2, RW6 @RW2+d8, RW6 RW2, RW7 @RW2+d8, RW7
50
+2
40
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
RW1, RW0 @RW1+d8, RW0
RW1, RW1 @RW1+d8, RW1 RW1, RW2 @RW1+d8, RW2 RW1, RW3 @RW1+d8, RW3 RW1, RW4 @RW1+d8, RW4 RW1, RW5 @RW1+d8, RW5 RW1, RW6 @RW1+d8, RW6 RW1, RW7 @RW1+d8, RW7
30
+1
20
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
RW0, RW0 @RW0+d8, RW0
RW0, RW1 @RW0+d8, RW1 RW0, RW2 @RW0+d8, RW2 RW0, RW3 @RW0+d8, RW3 RW0, RW4 @RW0+d8, RW4 RW0, RW5 @RW0+d8, RW5 RW0, RW6 @RW0+d8, RW6 RW0, RW7 @RW0+d8, RW7
10
+0
00
APPENDIX B Instructions
Table B.9-19 MOVW ea, Rwi Instruction (First Byte = 7DH)
679
680
XCH
XCH
XCH
XCH
R1,
XCH
XCH R1,
R1,@RW2 W2+d16, A
XCH
XCH
R2,
XCH
XCH R2,
R2,@RW2 W2+d16, A
XCH
XCH
R3,
XCH
XCH R3,
R3,@RW2 W2+d16, A
XCH
XCH
R4,
XCH
XCH R4,
R4,@RW2 W2+d16, A
XCH
XCH
R5,
XCH
XCH R5,
R5,@RW2 W2+d16, A
XCH
XCH
R6,
XCH
XCH R6,
R6,@RW2 W2+d16, A
XCH
XCH
R7,
XCH
XCH R7,
R7,@RW2 W2+d16, A
XCH
XCH
XCH
XCH
XCH
R1, XCH
XCH
R2, XCH
XCH
R3, XCH
XCH
R4, XCH
XCH
R5, XCH
XCH
R6, XCH
XCH
R7,
+F R0,@RW3+ R0, addr16
XCH
XCH
R1,@RW3+ R1, addr16
XCH
XCH
R2,@RW3+ R2, addr16
XCH
XCH
R3,@RW3+ R3, addr16
XCH
XCH
R4,@RW3+ R4, addr16
XCH
XCH
R5,@RW3+ R5, addr16
XCH
XCH
R6,@RW3+ R6, addr16
XCH
XCH
R7,@RW3+ R7, addr16
+E R0,@RW2+ @PC+d16 R1,@RW2+ @PC+d16 R2,@RW2+ @PC+d16 R3,@RW2+ @PC+d16 R4,@RW2+ @PC+d16 R5,@RW2+ @PC+d16 R6,@RW2+ @PC+d16 R7,@RW2+ @PC+d16
R0, XCH
XCH R0,
XCH
XCH R1,
XCH
XCH R2,
XCH
XCH R3,
XCH
XCH R4,
XCH
XCH R5,
XCH
XCH R6,
XCH
XCH R7,
@RW1+RW7 R1,@RW1+ @RW1+RW7 R2,@RW1+ @RW1+RW7 R3,@RW1+ @RW1+RW7 R4,@RW1+ @RW1+RW7 R5,@RW1+ @RW1+RW7 R6,@RW1+ @RW1+RW7 R7,@RW1+ @RW1+RW7
+D R0,@RW1+
XCH
XCH R0,
XCH
XCH R1,
XCH
XCH R2,
XCH
XCH R3,
XCH
XCH R4,
XCH
XCH R5,
XCH
XCH R6,
XCH
XCH R7,
@RW0+RW7 R1,@RW0+ @RW0+RW7 R2,@RW0+ @RW0+RW7 R3,@RW0+ @RW0+RW7 R4,@RW0+ @RW0+RW7 R5,@RW0+ @RW0+RW7 R6,@RW0+ @RW0+RW7 R7,@RW0+ @RW0+RW7
XCH
+C R0,@RW0+
+B R0,@RW3 @RW3+d16 R1,@RW3 @RW3+d16 R2,@RW3 @RW3+d16 R3,@RW3 @RW3+d16 R4,@RW3 @RW3+d16 R5,@RW3 @RW3+d16 R6,@RW3 @RW3+d16 R7,@RW3 @RW3+d16
R0,
+A R0,@RW2 W2+d16, A
R0,
XCH
XCH R0, XCH
XCH R1, XCH
XCH R2, XCH
XCH R3, XCH
XCH R4, XCH
XCH R5, XCH
XCH R6, XCH
XCH R7,
R0,@RW1 @RW1+d16 R1,@RW1 @RW1+d16 R2,@RW1 @RW1+d16 R3,@RW1 @RW1+d16 R4,@RW1 @RW1+d16 R5,@RW1 @RW1+d16 R6,@RW1 @RW1+d16 R7,@RW1 @RW1+d16
+9
XCH
XCH
XCH R0, XCH
XCH R1, XCH
XCH R2, XCH
XCH R3, XCH
XCH R4, XCH
XCH R5, XCH
XCH R6, XCH
XCH R7,
R0,@RW0 @RW0+d16 R1,@RW0 @RW0+d16 R2,@RW0 @RW0+d16 R3,@RW0 @RW0+d16 R4,@RW0 @RW0+d16 R5,@RW0 @RW0+d16 R6,@RW0 @RW0+d16 R7,@RW0 @RW0+d16
+8
XCH
XCH
XCH R0, XCH
XCH R1, XCH
XCH R2, XCH
XCH R3, XCH
XCH R4, XCH
XCH R5, XCH
XCH R6, XCH
XCH R7,
R0, R7 @RW7+d8
R1, R7 @RW7+d8
R2, R7 @RW7+d8
R3, R7 @RW7+d8
R4, R7 @RW7+d8
R5, R7 @RW7+d8
R6, R7 @RW7+d8
R7, R7 @RW7+d8
F0
+7
E0
XCH
XCH R0, XCH
XCH R1, XCH
XCH R2, XCH
XCH R3, XCH
XCH R4, XCH
XCH R5, XCH
XCH R6, XCH
XCH R7,
R0, R6 @RW6+d8
R1, R6 @RW6+d8
R2, R6 @RW6+d8
R3, R6 @RW6+d8
R4, R6 @RW6+d8
R5, R6 @RW6+d8
R6, R6 @RW6+d8
R7, R6 @RW6+d8
D0
+6
C0
XCH
XCH R0, XCH
XCH R1, XCH
XCH R2, XCH
XCH R3, XCH
XCH R4, XCH
XCH R5, XCH
XCH R6, XCH
XCH R7,
R0, R5 @RW5+d8
R1, R5 @RW5+d8
R2, R5 @RW5+d8
R3, R5 @RW5+d8
R4, R5 @RW5+d8
R5, R5 @RW5+d8
R6, R5 @RW5+d8
R7, R5 @RW5+d8
B0
+5
A
XCH
XCH R0, XCH
XCH R1, XCH
XCH R2, XCH
XCH R3, XCH
XCH R4, XCH
XCH R5, XCH
XCH R6, XCH
XCH R7,
R0, R4 @RW4+d8
R1, R4 @RW4+d8
R2, R4 @RW4+d8
R3, R4 @RW4+d8
R4, R4 @RW4+d8
R5, R4 @RW4+d8
R6, R4 @RW4+d8
R7, R4 @RW4+d8
90
+4
80
XCH
XCH R0, XCH
XCH R1, XCH
XCH R2, XCH
XCH R3, XCH
XCH R4, XCH
XCH R5, XCH
XCH R6, XCH
XCH R7,
R0, R3 @RW3+d8
R1, R3 @RW3+d8
R2, R3 @RW3+d8
R3, R3 @RW3+d8
R4, R3 @RW3+d8
R5, R3 @RW3+d8
R6, R3 @RW3+d8
R7, R3 @RW3+d8
70
+3
60
XCH
XCH R0, XCH
XCH R1, XCH
XCH R2, XCH
XCH R3, XCH
XCH R4, XCH
XCH R5, XCH
XCH R6, XCH
XCH R7,
R0, R2 @RW2+d8
R1, R2 @RW2+d8
R2, R2 @RW2+d8
R3, R2 @RW2+d8
R4, R2 @RW2+d8
R5, R2 @RW2+d8
R6, R2 @RW2+d8
R7, R2 @RW2+d8
50
+2
40
XCH
XCH R0, XCH
XCH R1, XCH
XCH R2, XCH
XCH R3, XCH
XCH R4, XCH
XCH R5, XCH
XCH R6, XCH
XCH R7,
R0, R1 @RW1+d8
R1, R1 @RW1+d8
R2, R1 @RW1+d8
R3, R1 @RW1+d8
R4, R1 @RW1+d8
R5, R1 @RW1+d8
R6, R1 @RW1+d8
R7, R1 @RW1+d8
30
+1
20
XCH
XCH R0, XCH
XCH R1, XCH
XCH R2, XCH
XCH R3, XCH
XCH R4, XCH
XCH R5, XCH
XCH R6, XCH
XCH R7,
R0, R0 @RW0+d8
R1, R0 @RW0+d8
R2, R0 @RW0+d8
R3, R0 @RW0+d8
R4, R0 @RW0+d8
R5, R0 @RW0+d8
R6, R0 @RW0+d8
R7, R0 @RW0+d8
10
+0
00
APPENDIX
Table B.9-20 XCH Ri, ea Instruction (First Byte = 7EH)
XCHW
XCHW RW0, XCHW
XCHW RW1, XCHW
XCHW RW2, XCHW
XCHW RW3, XCHW
XCHW RW4, XCHW
XCHW RW5, XCHW
XCHW RW6, XCHW
XCHW RW7,
RW0,@RW2+ @PC+d16
RW1,@RW2+ @PC+d16
RW2,@RW2+ @PC+d16
RW3,@RW2+ @PC+d16
RW4,@RW2+ @PC+d16
RW5,@RW2+ @PC+d16
RW6,@RW2+ @PC+d16
RW7,@RW2+ @PC+d16
XCHW
XCHW
RW0,@RW3+ RW0, addr16
+E
+F
XCHW
XCHW
RW7,@RW3+ RW7, addr16
XCHW
XCHW RW0, XCHW
XCHW RW1, XCHW
XCHW RW2, XCHW
XCHW RW3, XCHW
XCHW RW4, XCHW
XCHW RW5, XCHW
XCHW RW6, XCHW
XCHW R