The following document contains information on Cypress products. FUJITSU MICROELECTRONICS CONTROLLER MANUAL CM44-10148-4E F2MC-16LX 16-BIT MICROCONTROLLER MB90950 Series HARDWARE MANUAL F2MC-16LX 16-BIT MICROCONTROLLER MB90950 Series HARDWARE MANUAL For the information for microcontroller supports, see the following web site. http://edevice.fujitsu.com/micom/en-support/ FUJITSU MICROELECTRONICS LIMITED PREFACE ■ Objectives and Intended Reader Thank you very much for your continued patronage of FUJITSU MICROELECTRONICS products. The MB90950 series has been developed as one of the general-purpose products of the F2MC-16LX family, which is an original 16-bit single-chip microcontroller compatible with the Application Specific IC (ASIC). This manual describes the functions and operation of the MB90950 series for engineers who actually use this semiconductor to design products. Please read this manual first. Note: F2MC is the abbreviation of FUJITSU Flexible Microcontroller. ■ Trademark The company names and brand names herein are the trademarks or registered trademarks of their respective owners. i ■ Overall Structure of This Manual This manual consists of the following 29 chapters and an appendix. CHAPTER 1 OVERVIEW This chapter explains the features and basic specifications. CHAPTER 2 CPU This chapter explains the functions and operations of the CPU. CHAPTER 3 INTERRUPTS This chapter explains the functions and operations of the interrupts, the extended intelligent I/O service (EI2OS), and DMA. CHAPTER 4 DELAY INTERRUPT GENERATION MODULE This chapter explains the functions and operations of the delay interrupt generation module. CHAPTER 5 CLOCK This chapter explains the clock. CHAPTER 6 RESET This chapter explains the reset. CHAPTER 7 LOW-POWER CONSUMPTION MODE This chapter explains the low-power consumption mode. CHAPTER 8 MEMORY ACCESS MODE This chapter explains the functions and operations of the memory access mode. CHAPTER 9 I/O PORTS This chapter explains the functions of I/O ports. CHAPTER 10 TIME-BASE TIMER This chapter explains the function and operation of the time-base timer. CHAPTER 11 WATCHDOG TIMER This chapter explains the function and operation of the watchdog timer. CHAPTER 12 16-BIT I/O TIMER This chapter explains the functions and operations of the 16-bit I/O timer. CHAPTER 13 16-BIT RELOAD TIMERS This chapter describes the functions and operations of 16-bit reload timers. CHAPTER 14 WATCH TIMER This chapter explains the functions and operations of the watch timer. CHAPTER 15 8/16-BIT PPG TIMER This chapter explains the functions and operations of the 8/16-bit PPG timer. CHAPTER 16 DTP/EXTERNAL INTERRUPT This chapter explains the functions and operations of the DTP/external interrupt. CHAPTER 17 8/10-BIT A/D CONVERTER This chapter explains the functions and operations of the 8/10-bit A/D converter. CHAPTER 18 CLOCK MONITOR FUNCTION This chapter explains the functions and operations of the clock monitor. CHAPTER 19 LIN-UART This chapter explains the functions and operations of LIN-UART. ii CHAPTER 20 I2C INTERFACE (400 kHz) This chapter explains the functions and operations of the high-speed I2C interface. CHAPTER 21 CAN CONTROLLER This chapter explains the functions and overview of the CAN controller. CHAPTER 22 ADDRESS MATCH DETECTION FUNCTION This chapter explains the functions and operation of the address match detection function. CHAPTER 23 ROM MIRRORING FUNCTION SELECT MODULE This chapter explains the functions and operations of the ROM mirroring function select module. CHAPTER 24 FLASH MEMORY This chapter explains the functions and operation of the flash memory. CHAPTER 25 EXAMPLES OF SERIAL PROGRAMMING CONNECTION FOR FLASH MEMORY PRODUCTS This chapter shows examples of serial programming connection using the AF220/AF210/AF120/AF110 flash microcontroller programmers by Yokogawa Digital Computer Corporation. CHAPTER 26 LOW-VOLTAGE/CPU OPERATION DETECTION RESET CIRCUIT This chapter describes the functions and operations of the low-voltage/CPU operation detection reset circuit. This function can be used by only the products with J-suffix. MB90V950AJAS correspond to the cpu operation detection. CHAPTER 27 CLOCK SUPERVISOR This chapter describes the functions and operations of the clock supervisor. This function can be used by only the products with J-suffix. CHAPTER 28 CLOCK CALIBRATION UNIT This chapter outlines the clock calibration unit and describes its register configuration and functions. This function can be used by only the products with J-suffix. MB90V950AJAS doesn't correspond to the CR clock calibration. CHAPTER 29 D/A CONVERTER This chapter explains the functions and operation of the digital/analog (D/A) converter. APPENDIX The appendixes provide I/O maps, F2MC-16LX instructions, and other information. iii • • • • • • • The contents of this document are subject to change without notice. Customers are advised to consult with sales representatives before ordering. The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of FUJITSU MICROELECTRONICS device; FUJITSU MICROELECTRONICS does not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. FUJITSU MICROELECTRONICS assumes no liability for any damages whatsoever arising out of the use of the information. Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of FUJITSU MICROELECTRONICS or any third party or does FUJITSU MICROELECTRONICS warrant non-infringement of any thirdparty's intellectual property right or other right by using such information. FUJITSU MICROELECTRONICS assumes no liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use of information contained herein. The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). Please note that FUJITSU MICROELECTRONICS will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. Exportation/release of any products described in this document may require necessary procedures in accordance with the regulations of the Foreign Exchange and Foreign Trade Control Law of Japan and/or US export control laws. The company names and brand names herein are the trademarks or registered trademarks of their respective owners. Copyright ©2008-2009 FUJITSU MICROELECTRONICS LIMITED All rights reserved. iv CONTENTS CHAPTER 1 1.1 1.2 1.3 1.4 1.5 1.6 1.7 CHAPTER 2 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.7.1 2.7.2 2.7.3 2.7.4 2.8 2.9 2.10 OVERVIEW ................................................................................................... 1 Overview of the MB90950 Series ....................................................................................................... 2 Block Diagram of the MB90950 Series ............................................................................................... 8 Package Dimensions ........................................................................................................................ 10 Pin Assignment ................................................................................................................................. 12 Pin Function ...................................................................................................................................... 14 I/O Circuit Type ................................................................................................................................. 22 Precautions when Handling Devices ................................................................................................ 27 CPU ............................................................................................................ 31 Overview of the CPU ........................................................................................................................ Memory Space .................................................................................................................................. Memory Map ..................................................................................................................................... Linear Addressing ............................................................................................................................. Bank Addressing ............................................................................................................................... Multibyte Data in Memory Space ...................................................................................................... Registers ........................................................................................................................................... Accumulator (A) ........................................................................................................................... User Stack Pointer (USP) and System Stack Pointer (SSP) ....................................................... Processor Status (PS) ................................................................................................................. Program Counter (PC) ................................................................................................................. Register Bank ................................................................................................................................... Prefix Codes ..................................................................................................................................... Interrupt Disable Instructions ............................................................................................................ CHAPTER 3 32 33 36 37 38 40 41 44 45 46 49 50 52 54 INTERRUPTS ............................................................................................. 55 3.1 Overview of Interrupts ....................................................................................................................... 3.2 Interrupt Vector ................................................................................................................................. 3.3 Interrupt Control Registers (ICR00 to ICR15) ................................................................................... 3.4 Interrupt Flow .................................................................................................................................... 3.5 Hardware Interrupts .......................................................................................................................... 3.5.1 Hardware Interrupt Operation ...................................................................................................... 3.5.2 Occurrence and Release of Hardware Interrupt .......................................................................... 3.5.3 Multiple interrupts ........................................................................................................................ 3.6 Software Interrupts ........................................................................................................................... 3.7 Extended Intelligent I/O Service (EI2OS) .......................................................................................... 3.7.1 Extended Intelligent I/O Service Descriptor (ISD) ....................................................................... 3.8 Operation Flow of Extended Intelligent I/O Service (EI2OS) and its Application Procedure ............. 3.9 μDMAC ............................................................................................................................................. 3.9.1 Overview of μDMAC .................................................................................................................... 3.9.2 Registers of μDMAC .................................................................................................................... 3.9.2.1 DMA Descriptor Channel Specification Register (DCSR) ........................................................ 3.9.2.2 DMA Status Register (DSRL/DSRH) ........................................................................................ v 56 60 62 66 68 69 70 72 73 75 77 80 83 84 85 87 89 3.9.2.3 DMA Stop Status Register (DSSR) .......................................................................................... 90 3.9.2.4 DMA Enable Register (DERL/DERH) ....................................................................................... 92 3.9.3 DMA Descriptor Window Register (DDWR) ................................................................................. 93 3.9.3.1 Data Counter (DCTL/DCTH) .................................................................................................... 94 3.9.3.2 I/O Register Address Pointer (IOAL/IOAH) .............................................................................. 95 3.9.3.3 DMA Control Register (DMACS) .............................................................................................. 96 3.9.3.4 Buffer Address Pointer (BAPL/BAPM/BAPH) ........................................................................... 98 3.9.4 Operating Explanation of μDMAC ............................................................................................... 99 3.10 Exceptions ...................................................................................................................................... 103 CHAPTER 4 4.1 4.2 4.3 4.3.1 4.4 4.5 4.6 Overview of Delay Interrupt Generation Module ............................................................................. Block Diagram of Delay Interrupt Generation Module .................................................................... Configuration of Delay Interrupt Generation Module ...................................................................... Delay Interrupt Request Generation/Release Register (DIRR) ................................................. Operating Explanation of Delay Interrupt Generation Module ........................................................ Precautions when Using Delay Interrupt Generation Module ......................................................... Program Example of Delay Interrupt Generation Module ............................................................... CHAPTER 5 5.1 5.2 5.2.1 5.3 5.4 5.5 5.6 5.7 7.1 7.2 7.3 7.4 7.5 7.5.1 7.5.2 7.5.3 7.5.4 114 117 119 120 123 125 129 130 RESET ...................................................................................................... 131 Overview of Reset .......................................................................................................................... Reset Source and Oscillation Stabilization Wait Times .................................................................. External Reset Pin .......................................................................................................................... Reset Operation .............................................................................................................................. Reset Source Bits ........................................................................................................................... Status of Pins by Reset .................................................................................................................. CHAPTER 7 106 107 108 109 110 111 112 CLOCK ..................................................................................................... 113 Clock ............................................................................................................................................... Block Diagram of the Clock Generation Block ................................................................................ Register in the Clock Generation Block ..................................................................................... Clock Selection Register (CKSCR) ................................................................................................. PLL/Sub Clock Control Register (PSCCR) ..................................................................................... Clock Mode ..................................................................................................................................... Oscillation Stabilization Wait Time .................................................................................................. Connection of the Oscillator ............................................................................................................ CHAPTER 6 6.1 6.2 6.3 6.4 6.5 6.6 DELAY INTERRUPT GENERATION MODULE ....................................... 105 132 135 137 138 140 144 LOW-POWER CONSUMPTION MODE ................................................... 145 Overview of the Low-power Consumption Mode ............................................................................ Block Diagram of the Low-power Consumption Circuit .................................................................. Low-power Consumption Mode Control Register (LPMCR) ........................................................... CPU Intermittent Operation Mode .................................................................................................. Standby Mode ................................................................................................................................. Sleep Mode ............................................................................................................................... Watch Mode .............................................................................................................................. Time-base Timer Mode ............................................................................................................. Stop Mode ................................................................................................................................. vi 146 149 151 154 155 157 160 162 164 7.6 7.7 7.8 State Transition of the Standby Mode ............................................................................................ 167 Pin State in the Standby Mode and at the Time of Reset ............................................................... 168 Notes on Using the Low-power Consumption Mode ...................................................................... 173 CHAPTER 8 MEMORY ACCESS MODE ...................................................................... 177 8.1 Overview of the Memory Access Mode .......................................................................................... 8.1.1 Mode Pin ................................................................................................................................... 8.1.2 Mode Data ................................................................................................................................. 8.1.3 Memory Space by Bus Mode .................................................................................................... 8.2 External Memory Access (Bus Pin Control Circuit) ........................................................................ 8.2.1 Register for External Memory Access (External Bus Pin Control Circuit) .................................. 8.2.2 Auto Ready Selection Register (ARSR) .................................................................................... 8.2.3 External Address Output Control Register (HACR) ................................................................... 8.2.4 Bus Control Signal Selection Register (ECSR) ......................................................................... 8.3 External Memory Access Control Signal Operations ...................................................................... 8.3.1 Ready Function ......................................................................................................................... 8.3.2 Hold Function ............................................................................................................................ CHAPTER 9 178 179 180 181 183 184 185 187 188 191 193 195 I/O PORTS ................................................................................................ 197 9.1 I/O Ports .......................................................................................................................................... 9.2 Register List for I/O Ports ............................................................................................................... 9.2.1 Port Data Register (PDR0 to PDRA) ......................................................................................... 9.2.2 Port Data Direction Register (DDR0 to DDRA) ......................................................................... 9.2.3 Pull-up Control Register (PUCR0 to PUCR3) ............................................................................ 9.2.4 Analog Input Enabling Register (ADER5 to ADER7) ................................................................. 9.2.5 Input Level Selection Register (ILSR0, ILSR1, ILSR2) ............................................................. 198 199 200 202 205 206 207 CHAPTER 10 TIME-BASE TIMER .................................................................................. 211 10.1 Overview of the Time-base Timer ................................................................................................... 10.2 Block Diagram of the Time-base Timer .......................................................................................... 10.3 Configuration of the Time-base Timer ............................................................................................ 10.3.1 Time-base Timer Control Register (TBTC) ................................................................................ 10.4 Interrupt of the Time-base Timer .................................................................................................... 10.5 Operating Explanation of the Time-base Timer .............................................................................. 10.6 Notes on Using the Time-base Timer ............................................................................................. 10.7 Programming Example of the Time-base Timer ............................................................................. 212 214 216 217 219 220 224 225 CHAPTER 11 WATCHDOG TIMER ................................................................................ 227 11.1 Overview of the Watchdog Timer ................................................................................................... 11.2 Configuration of the Watchdog Timer ............................................................................................. 11.3 Register of the Watchdog Timer ..................................................................................................... 11.3.1 Watchdog Timer Control Register (WDTC) ............................................................................... 11.4 Operating Explanation of the Watchdog Timer ............................................................................... 11.5 Notes on Using the Watchdog Timer .............................................................................................. 11.6 Programming Example of the Watchdog Timer .............................................................................. vii 228 229 231 232 234 238 240 CHAPTER 12 16-BIT I/O TIMER ..................................................................................... 241 12.1 Overview of 16-bit I/O Timer ........................................................................................................... 12.2 Block Diagram of 16-bit I/O Timer .................................................................................................. 12.2.1 Block Diagram of 16-bit Free-run Timer .................................................................................... 12.2.2 Block Diagrams of Input Capture Units ..................................................................................... 12.2.3 Block Diagram of Output Compare Unit .................................................................................... 12.3 Configuration of 16-bit I/O Timer .................................................................................................... 12.3.1 Timer Control Status Registers (Upper) (TCCSH0, TCCSH1) .................................................. 12.3.2 Timer Control Status Registers (Lower) (TCCSL0, TCCSL1) ................................................... 12.3.3 Timer Data Registers (TCDT0, TCDT1) .................................................................................... 12.3.4 Input Capture Control Status Registers (ICS) ........................................................................... 12.3.5 Input Capture Registers (IPCP0 to IPCP7) ............................................................................... 12.3.6 Input Capture Edge Registers (ICE01, ICE23, ICE45, ICE67) .................................................. 12.3.7 Output Compare Control Status Register (OCS) (Upper) ......................................................... 12.3.8 Output Compare Control Status Register (OCS) (Lower) ......................................................... 12.3.9 Output Compare Registers (OCCP0 to OCCP7) ....................................................................... 12.4 Interrupts from 16-bit I/O Timer ...................................................................................................... 12.5 Operations of 16-bit Free-run Timer ............................................................................................... 12.6 Input Capture Operations ............................................................................................................... 12.7 Output Compare Operations ........................................................................................................... 12.8 Notes on Using the 16-bit I/O Timer ............................................................................................... 12.9 Sample Programs for 16-bit I/O Timer ............................................................................................ 242 244 246 247 250 252 254 255 258 259 261 263 267 270 272 274 276 279 281 284 285 CHAPTER 13 16-BIT RELOAD TIMERS ........................................................................ 289 13.1 Overview of 16-bit Reload Timers .................................................................................................. 13.2 Block Diagram of 16-bit Reload Timer ............................................................................................ 13.3 Configuration of 16-bit Reload Timers ............................................................................................ 13.3.1 Upper Byte of Timer Control Status Register (TMCSR:H) ......................................................... 13.3.2 Lower Byte of Timer Control Status Register (TMCSR:L) ......................................................... 13.3.3 16-bit Timer Register (TMR) ...................................................................................................... 13.3.4 16-bit Reload Register (TMRLR) ............................................................................................... 13.4 Interrupts of 16-bit Reload Timers .................................................................................................. 13.5 Operations of 16-bit Reload Timers ................................................................................................ 13.5.1 Operations in Internal Clock Mode ............................................................................................ 13.5.2 Operations in Event Count Mode .............................................................................................. 13.6 Notes on Using 16-bit Reload Timers ............................................................................................. 13.7 Sample Programs for 16-bit Reload Timers ................................................................................... 290 293 296 301 303 306 307 308 309 311 316 319 322 CHAPTER 14 WATCH TIMER ........................................................................................ 325 14.1 Overview of Watch Timer ............................................................................................................... 14.2 Block Diagram of Watch Timer ....................................................................................................... 14.3 Configuration of Watch Timer ......................................................................................................... 14.3.1 Watch Timer Control Register (WTC) ........................................................................................ 14.4 Interrupt of Watch Timer ................................................................................................................. 14.5 Operating Explanation of Watch Timer ........................................................................................... 14.6 Example Program of Watch Timer .................................................................................................. viii 326 328 330 331 333 334 336 CHAPTER 15 8/16-BIT PPG TIMER ............................................................................... 339 15.1 Overview of 8/16-bit PPG Timer ..................................................................................................... 15.2 Block Diagram of 8/16-bit PPG Timer ............................................................................................. 15.2.1 Block Diagram of 8/16-bit PPG Timer 0 .................................................................................... 15.2.2 Block Diagram of 8/16-bit PPG Timer 1 .................................................................................... 15.3 Configuration of 8/16-bit PPG Timer ............................................................................................... 15.3.1 PPG0 Operation Mode Control Register (PPGC0) .................................................................... 15.3.2 PPG1 Operation Mode Control Register (PPGC1) .................................................................... 15.3.3 PPG0/1 Count Clock Selection Register (PPG01) .................................................................... 15.3.4 PPG Reload Registers (PRLL0/PRLH0, PRLL1/PRLH1) .......................................................... 15.4 Interrupts of 8/16-bit PPG Timer ..................................................................................................... 15.5 Operating Explanation of 8/16-bit PPG Timer ................................................................................ 15.5.1 8-bit PPG Output 2-channel Independent Operation Mode ....................................................... 15.5.2 16-bit PPG Output Operation Mode .......................................................................................... 15.5.3 8+8-bit PPG Output Operation Mode ........................................................................................ 15.6 Notes on Using 8/16-bit PPG Timer ............................................................................................... 340 343 344 347 350 353 355 357 359 361 363 364 367 370 373 CHAPTER 16 DTP/EXTERNAL INTERRUPT ................................................................. 375 16.1 Overview of DTP/External Interrupt ................................................................................................ 16.2 Block Diagram of DTP/External Interrupt ........................................................................................ 16.3 Configuration of DTP/External Interrupt .......................................................................................... 16.3.1 DTP/External Interrupt Source Register (EIRR0/EIRR1) .......................................................... 16.3.2 DTP/External Interrupt Enable Register (ENIR0/ENIR1) ........................................................... 16.3.3 Detection Level Setting Register (ELVR0/ELVR1) .................................................................... 16.3.4 External Interrupt Source Select Register (EISSR) ................................................................... 16.4 Explanation of Operation of DTP/External Interrupt ....................................................................... 16.4.1 External Interrupt Function ........................................................................................................ 16.4.2 DTP Function ............................................................................................................................. 16.5 Notes on Using DTP/External Interrupt .......................................................................................... 16.6 Program Example of DTP/External Interrupt Circuit ....................................................................... 376 377 380 383 385 387 389 391 395 396 397 399 CHAPTER 17 8/10-BIT A/D CONVERTER ..................................................................... 403 17.1 Overview of 8/10-bit A/D Converter ................................................................................................ 17.2 Block Diagram of 8/10-bit A/D Converter ........................................................................................ 17.3 Configuration of 8/10-bit A/D Converter .......................................................................................... 17.3.1 A/D Control Status Register 1 (ADCS1) .................................................................................... 17.3.2 A/D Control Status Register 0 (ADCS0) .................................................................................... 17.3.3 A/D Data Registers 0/1 (ADCR0/ADCR1) ................................................................................. 17.3.4 A/D Setting Register (ADSR0/ADSR1) ...................................................................................... 17.3.5 Analog Input Enable Register (ADER5 to ADER7) ................................................................... 17.4 Interrupt of 8/10-bit A/D Converter .................................................................................................. 17.5 Operating Explanation of 8/10-bit A/D Converter ........................................................................... 17.5.1 Single Conversion Mode ........................................................................................................... 17.5.2 Continuous Conversion Mode ................................................................................................... 17.5.3 Stop Conversion Mode .............................................................................................................. 17.5.4 Conversion Operation with μDMAC or EI2OS Function ............................................................ 17.5.5 A/D Conversion Data Protection Function ................................................................................. ix 404 406 409 412 416 418 419 423 425 426 427 429 431 433 434 17.6 Notes on Using 8/10-bit A/D Converter .......................................................................................... 438 CHAPTER 18 CLOCK MONITOR FUNCTION ................................................................ 439 18.1 Overview of Clock Monitor Function ............................................................................................... 18.2 Block Diagram of Clock Monitor Function ....................................................................................... 18.3 Configuration of Clock Monitor Function ......................................................................................... 18.3.1 Clock Output Enable Register (CLKR) ...................................................................................... 18.4 Program Example of Clock Monitor Function ................................................................................. 440 441 442 443 444 CHAPTER 19 LIN-UART ................................................................................................. 445 19.1 Overview of LIN-UART ................................................................................................................... 19.2 Configuration of LIN-UART ............................................................................................................. 19.3 Pins of LIN-UART ........................................................................................................................... 19.4 Registers of LIN-UART ................................................................................................................... 19.4.1 Serial Control Register (SCR) ................................................................................................... 19.4.2 LIN-UART Serial Mode Register (SMR) .................................................................................... 19.4.3 Serial Status Register (SSR) ..................................................................................................... 19.4.4 Reception Data Register / Transmit Data Register (RDR/TDR) ................................................ 19.4.5 Extended Status Control Register (ESCR) ................................................................................ 19.4.6 Extended Communication Control Register (ECCR) ................................................................. 19.4.7 Baud Rate Generator Register 0, 1 (BGRn0/BGRn1) ............................................................... 19.5 Interrupts of LIN-UART ................................................................................................................... 19.5.1 Timing of Reception Interrupt Generation and Flag Set ............................................................ 19.5.2 Timing of Transmit Interrupt Generation and Flag Set .............................................................. 19.6 Baud Rate of LIN-UART ................................................................................................................. 19.6.1 Baud Rate Setting ..................................................................................................................... 19.6.2 Reload Counter ......................................................................................................................... 19.7 Operation of LIN-UART .................................................................................................................. 19.7.1 Operation of Asynchronous Modes (Operation Modes 0, 1) ..................................................... 19.7.2 Operation of Synchronous Mode (Operating Mode 2) ............................................................... 19.7.3 Operation of LIN Function (Operating Mode 3) ......................................................................... 19.7.4 Serial Pin Direct Access ............................................................................................................ 19.7.5 Bidirectional Communication Function (Normal Mode) ............................................................. 19.7.6 Master/Slave Mode Communication Function (Multiprocessor Mode) ...................................... 19.7.7 LIN Communication Function .................................................................................................... 19.7.8 Example Flowchart of LIN-UART LIN Communication (Operating Mode 3) .............................. 19.8 Notes on Using LIN-UART .............................................................................................................. 446 449 454 456 458 460 462 465 467 469 471 472 475 476 478 480 483 485 487 491 494 497 498 500 503 504 506 CHAPTER 20 I2C INTERFACE (400 kHz) ...................................................................... 509 20.1 Overview of I2C Interface (400 kHz) ............................................................................................... 20.2 Registers of I2C Interface ............................................................................................................... 20.2.1 Bus Status Register (IBSR0, IBSR1) ......................................................................................... 20.2.2 Bus Control Register (IBCR0, IBCR1) ....................................................................................... 20.2.3 10-bit Slave Address Register (ITBAH0/ITBAH1, ITBAL0/ITBAL1) .......................................... 20.2.4 10-bit Slave Address Mask Register (ITMK0, ITMK1) ............................................................... 20.2.5 7-bit Slave Address Register (ISBA0, ISBA1) ........................................................................... 20.2.6 7-bit Slave Address Mask Register (ISMK0, ISMK1) ................................................................ x 510 512 514 518 526 527 529 530 20.2.7 Data Register (IDAR0, IDAR1) .................................................................................................. 20.2.8 Clock Control Register (ICCR0, ICCR1) .................................................................................... 20.3 Operations of I2C Interface ............................................................................................................. 20.4 Programming Flowcharts ................................................................................................................ 531 532 535 538 CHAPTER 21 CAN CONTROLLER ................................................................................ 541 21.1 Features of CAN Controller ............................................................................................................ 21.2 Block Diagram of CAN Controller ................................................................................................... 21.3 List of Registers .............................................................................................................................. 21.4 Classifying the CAN Controller Registers ....................................................................................... 21.4.1 Configuration of Control Status Register (CSR) ........................................................................ 21.4.2 Function of Control Status Register (CSR) ................................................................................ 21.4.3 Correspondence between Node Status Bits and Node Status .................................................. 21.4.4 Notes on Using Bus Operation Stop Bit (HALT = 1) .................................................................. 21.4.5 Last Event Indicator Register (LEIR) ......................................................................................... 21.4.6 Receive and Transmit Error Counters (RTEC) .......................................................................... 21.4.7 Bit Timing Register (BTR) .......................................................................................................... 21.4.8 Prescaler Setting by Bit Timing Register (BTR) ........................................................................ 21.4.9 Message Buffer Valid Register (BVALR) ................................................................................... 21.4.10 IDE register (IDER) .................................................................................................................... 21.4.11 Transmission Request Register (TREQR) ................................................................................ 21.4.12 Transmission RTR Register (TRTRR) ....................................................................................... 21.4.13 Remote Frame Receiving Wait Register (RFWTR) ................................................................... 21.4.14 Transmission Cancel Register (TCANR) ................................................................................... 21.4.15 Transmission Complete Register (TCR) .................................................................................... 21.4.16 Transmission Interrupt Enable Register (TIER) ......................................................................... 21.4.17 Reception Complete Register (RCR) ........................................................................................ 21.4.18 Remote Request Receiving Register (RRTRR) ........................................................................ 21.4.19 Receive Overrun Register (ROVRR) ......................................................................................... 21.4.20 Reception Interrupt Enable Register (RIER) ............................................................................. 21.4.21 Acceptance Mask Select Register (AMSR) ............................................................................... 21.4.22 Acceptance Mask Registers 0, 1 (AMR0, AMR1) ...................................................................... 21.4.23 Message Buffers ........................................................................................................................ 21.4.24 ID Register x (x = 0 to 15) (IDR0 to IDR15) ............................................................................... 21.4.25 DLC Register x (x = 0 to 15) (DLCR0 to DLCR15) .................................................................... 21.4.26 Data Register x (x = 0 to 15) (DTR0 to DTR15) ........................................................................ 21.5 Transmission of CAN Controller ..................................................................................................... 21.6 Reception of CAN Controller .......................................................................................................... 21.7 Reception Flowchart of CAN Controller .......................................................................................... 21.8 How to Use the CAN Controller ...................................................................................................... 21.9 Procedure for Transmission by Message Buffer (x) ....................................................................... 21.10 Procedure for Reception by Message Buffer (x) ............................................................................. 21.11 Setting Configuration of Multi-level Message Buffer ....................................................................... 21.12 Setting the Redirection of CAN1 RX/TX pin ................................................................................... 21.13 CAN Direct Mode Register (CDMR) ............................................................................................... 21.14 Precautions when Using CAN Controller ........................................................................................ xi 542 543 544 552 553 555 558 559 560 563 564 565 567 568 569 570 571 572 573 574 575 576 577 578 579 581 583 585 587 588 590 592 595 596 598 600 602 604 605 606 CHAPTER 22 ADDRESS MATCH DETECTION FUNCTION ......................................... 609 22.1 Overview of Address Match Detection Function ............................................................................. 22.2 Block Diagram of Address Match Detection Function .................................................................... 22.3 Configuration of Address Match Detection Function ...................................................................... 22.3.1 Address Detection Control Register (PACSR0/PACSR1) ......................................................... 22.3.2 Detection Address Setting Registers (PADR0 to PADR5) ........................................................ 22.4 Explanation of Operation of Address Match Detection Function .................................................... 22.4.1 Example of Using Address Match Detection Function .............................................................. 22.5 Program Example of Address Match Detection Function ............................................................... 610 611 612 613 617 620 621 626 CHAPTER 23 ROM MIRRORING FUNCTION SELECT MODULE ................................ 629 23.1 23.2 Overview of ROM Mirroring Function Select Module ...................................................................... 630 ROM Mirroring Function Select Register (ROMM) ......................................................................... 632 CHAPTER 24 FLASH MEMORY ..................................................................................... 633 24.1 Outline of Flash Memory ................................................................................................................. 24.2 Block Diagram of the Entire Flash Memory .................................................................................... 24.3 Sector Configuration of the Flash Memory ..................................................................................... 24.4 Write/Erase Modes ......................................................................................................................... 24.5 Flash Memory Control Status Register (FMCS) ............................................................................. 24.6 Flash Memory Write Control Register (FWR0/FWR1) .................................................................... 24.7 Starting the Flash Memory Automatic Algorithm ............................................................................ 24.8 Confirming the Automatic Algorithm Execution State ..................................................................... 24.8.1 Data Polling Flag (DQ7) ............................................................................................................ 24.8.2 Toggle Bit Flag (DQ6) ................................................................................................................ 24.8.3 Timing Limit Exceeded Flag (DQ5) ........................................................................................... 24.8.4 Sector Erase Timer Flag (DQ3) ................................................................................................. 24.9 Detailed Explanation of Writing to and Erasing Flash Memory ....................................................... 24.9.1 Setting Flash Memory to the Read/Reset State ........................................................................ 24.9.2 Writing Data to Flash Memory ................................................................................................... 24.9.3 Erasing All Data from Flash Memory (Chip Erase) .................................................................... 24.9.4 Erasing Optional Data (Erasing Sectors) in the Flash Memory ................................................. 24.9.5 Suspending Sector Erase of Flash Memory .............................................................................. 24.9.6 Restarting Sector Erase of Flash Memory ................................................................................. 24.10 Notes on Using Flash Memory ....................................................................................................... 24.11 Flash Security Feature .................................................................................................................... 634 635 636 637 638 641 646 648 650 651 652 653 654 655 656 658 659 661 662 663 664 CHAPTER 25 EXAMPLES OF SERIAL PROGRAMMING CONNECTION FOR FLASH MEMORY PRODUCTS ............................................................................. 665 25.1 25.2 25.3 25.4 25.5 Basic Configuration of Serial Programming Connection for Flash Memory Products .................... 666 Example of Serial Programming Connection (User Power Supply Used) ...................................... 669 Example of Serial Programming Connection (Power Supplied from Programmer) ........................ 671 Example of Minimum Connection to Flash Microcontroller Programmer (User Power Supply Used) 673 Example of Minimum Connection to Flash Microcontroller Programmer (Power Supplied from Programmer) ............................................................................................... 675 xii CHAPTER 26 LOW-VOLTAGE/CPU OPERATION DETECTION RESET CIRCUIT ...... 677 26.1 26.2 26.3 26.4 26.5 26.6 Overview of the Low-voltage/CPU Operation Detection Reset Circuit ........................................... Configuration of the Low-Voltage/CPU Operation Detection Reset Circuit .................................... Register of the Low-voltage/CPU Operation Detection Reset Circuit ............................................. Operation of the Low-voltage/CPU Operation Detection Reset Circuit .......................................... Notes on Using the Low-voltage/CPU Operation Detection Reset Circuit ...................................... Sample Program for the Low-voltage/CPU Operation Detection Reset Circuit .............................. 678 680 682 686 687 689 CHAPTER 27 CLOCK SUPERVISOR ............................................................................. 691 27.1 Overview of Clock Supervisor ......................................................................................................... 27.2 Configuration of Clock Supervisor .................................................................................................. 27.3 Registers of Clock Supervisor ........................................................................................................ 27.3.1 Clock Supervisor Control Register (CSVCR) ............................................................................ 27.4 Operations of Clock Supervisor ...................................................................................................... 27.5 Precautions when Using Clock Supervisor ..................................................................................... 692 693 695 696 698 701 CHAPTER 28 CLOCK CALIBRATION UNIT .................................................................. 703 28.1 28.2 28.3 Overview of Clock Calibration Unit ................................................................................................. 704 Register of Clock Calibration Unit ................................................................................................... 707 Application Notes ............................................................................................................................ 715 CHAPTER 29 D/A CONVERTER .................................................................................... 717 29.1 Overview of D/A Converter ............................................................................................................. 29.2 Block Diagram of D/A Converter ..................................................................................................... 29.3 Configuration of D/A Converter ....................................................................................................... 29.4 D/A Converter Registers ................................................................................................................. 29.4.1 D/A Converter Register 1 (DAT1) .............................................................................................. 29.4.2 D/A Converter Register 0 (DAT0) .............................................................................................. 29.4.3 D/A Control Register 1 (DACR1) ............................................................................................... 29.4.4 D/A Control Register 0 (DACR0) ............................................................................................... 29.5 Sample Programs for the D/A Converter ........................................................................................ 718 719 720 721 722 723 724 725 726 APPENDIX ......................................................................................................................... 727 APPENDIX A I/O Maps .............................................................................................................................. APPENDIX B Instructions ........................................................................................................................... B.1 Instruction Types ............................................................................................................................ B.2 Addressing ..................................................................................................................................... B.3 Direct Addressing ........................................................................................................................... B.4 Indirect Addressing ........................................................................................................................ B.5 Execution Cycle Count ................................................................................................................... B.6 Effective address field .................................................................................................................... B.7 How to Read the Instruction List .................................................................................................... B.8 F2MC-16LX Instruction List ............................................................................................................ B.9 Instruction Map ............................................................................................................................... APPENDIX C List of MB90950 Interrupt Vectors ....................................................................................... 728 744 745 746 748 754 762 765 766 769 783 805 INDEX................................................................................................................................... 809 xiii xiv Main changes in this edition Page Changes (For details, refer to main body.) − − Changed product name MB90V950JAS → MB90V950AJAS MB90V950MAS → MB90V950AMAS 5 CHAPTER 1 OVERVIEW Changed "ROM size". 1.1 Overview of the MB90950 Added "(Satellite flash emulation memory:built-in 32 Kbytes)". Series ■ Product Lineup Table 1.1-1 7 ■ Features 30 1.7 Precautions when Deleted "· Satellite Flash". Handling Devices ■ Precautions when Handling Devices ● Notes when developing software using MB90V950 117 CHAPTER 5 CLOCK Changed a figure. 5.2 Block Diagram of the Changed the connect line. Clock Generation Block ■ Block Diagram of the Clock Generation Block Figure 5.2-1 128 5.5 Clock Mode ■ Machine Clock Figure 5.5-1 Changed an explanation. (7) CS1,CS0=11B CS2=1 → (7) End of PLL clock oscillation stabilization wait time &CS1, CS0 = 11B & CS2 = 1 (19) CS1,CS0=11B CS2=1 → (19) End of main clock oscillation stabilization wait time & CS1, CS0 = 11B & CS2 =1 137 CHAPTER 6 RESET 6.3 External Reset Pin ■ Block Diagram of the External Reset Pin Figure 6.3-1 Changed Figure. Deleted "(PLL multiplier circuit with an HCLK frequency divided by 2)". 6.5 Reset Source Bits ■ Reset Source Bits Figure 6.5-1 Changed Figure. Deleted the box of "RST pin". 140 Changed "Flash memory". Added "Evaluation product". Changed "Note:". Deleted "In particular, an operation with an external clock requires clock input together with reset input.". xv Page Changes (For details, refer to main body.) 149 CHAPTER 7 LOW-POWER CONSUMPTION MODE 7.2 Block Diagram of the Low-power Consumption Circuit ■ Block Diagram of the Low-power Consumption Circuit Figure 7.2-1 Changed a figure. Changed the connect line. 158 7.5 Standby Mode 7.5.1 Sleep Mode ■ Returning from the Sleep Mode Changed "Note:". Deleted "and for an external clock, the time is 0 ms.". 235 CHAPTER 11 WATCHDOG Deleted "Note:". TIMER 11.4 Operating Explanation of the Watchdog Timer ■ Watchdog Timer Operations ● Selection of a clock input source 239 11.5 Notes on Using the Changed all. Watchdog Timer ■ Notes on Using the Watchdog Timer ● Watchdog timer operations in hold state (external bus mode) 635 CHAPTER 24 FLASH MEMORY 24.2 Block Diagram of the Entire Flash Memory 636 24.3 Sector Configuration of the Flash Memory 635 24.2 Block Diagram of the Entire Flash Memory Changed summary. Figure 24.2-1 shows a block diagram of the entire flash memory with the flash memory interface circuit included. → This section shows a block diagram of the entire flash memory. Deleted "Figure 24.2-2 shows the sector configuration of the flash memory.". 636 24.3 Sector Configuration of the Flash Memory Added summary. 639 24.5 Flash Memory Control Changed "Note:". Status Register (FMCS) Deleted ". The RDYINT and RDY bits cannot be changed at the same time. Make a ■ Flash Memory Control Sta- program so that decisions are made using either of these bits. (See Figure 24.4-2).". tus Register (FMCS) 640 ■ Automatic Algorithm End Timing Separated a section. 24.2 Block Diagram of the Entire Flash Memory and Sector Configuration of the Flash Memory → 24.2 Block Diagram of the Entire Flash Memory, 24.3 Sector Configuration of the Flash Memory Added title and explanation. xvi Page Changes (For details, refer to main body.) 640 CHAPTER 24 FLASH MEMORY 24.5 Flash Memory Control Status Register (FMCS) ■ Automatic Algorithm End Timing Figure 24.5-2 Changed title. Change Timing of the RDYINT and RDY Bits → Relationship between Automatic Algorithm End Timing and RDYINT and RDY bits 648 24.8 Confirming the Automatic Algorithm Execution State ■ Hardware Sequence Flags Changed an explanation. Deleted descriptions about "DQ2". Table 24.8-1 Changed "Bit No. 2". DQ2 → −. 649 Table 24.8-2 Changed the table. Changed rows. Deleted "DQ2" column. Corrected values. Deleted remark "*". 653 24.8 Confirming the Automatic Algorithm Execution State Deleted "24.7.5 Toggle Bit-2 Flag (DQ2)". 655 24.9 Writing to and Erasing Flash Memory 24.9.1 Setting the Flash Memory to the Read/Reset State ■ Setting the Flash Memory to the Read/reset State Changed an explanation. first and third bus operations → first and fourth bus operations 659 24.9.4 Erasing Optional Data in the Flash Memory (Erasing Sectors) ■ Erasing Optional Data in the Flash Memory (Erasing Sectors) ● Specifying sectors Changed an explanation. 50 μs → minimum 50 μs ● Notes on specifying multi- Changed an explanation. ple sectors 50 μs → minimum 50 μs 660 Figure 24.9-2 Changed figure. 661 24.9.5 Suspending Sector Erase of Flash Memory ■ Suspending Sector Erase of Flash Memory Added an explanation. If Sector Erase Restart command will be issued less than 20 μs after Sector Erase Suspend command is issued, operations after restarting cannot be guaranteed. In the evaluation product, however, the restart command which is issued less than 20 μs is neglected. xvii Page Changes (For details, refer to main body.) 663 CHAPTER 24 FLASH MEMORY 24.10 Notes on Using Flash Memory ■ Notes on Using Flash Memory Added "● Transition during write/erase mode". 688 CHAPTER 26 LOW-VOLTAGE/CPU OPERATION DETECTION RESET CIRCUIT 26.5 Notes on Using the Low-voltage/CPU Operation Detection Reset Circuit ■ Notes on Using the CPU Operation Detection Reset Circuit Added Table 26.5-1. The vertical lines marked in the left side of the page show the changes. xviii CHAPTER 1 OVERVIEW This chapter explains the features and basic specifications. 1.1 Overview of the MB90950 Series 1.2 Block Diagram of the MB90950 Series 1.3 Package Dimensions 1.4 Pin Assignment 1.5 Pin Function 1.6 I/O Circuit Type 1.7 Precautions when Handling Devices CM44-10148-4E FUJITSU MICROELECTRONICS LIMITED 1 CHAPTER 1 OVERVIEW 1.1 1.1 MB90950 Series Overview of the MB90950 Series MB90950 series is the 16-bit microcontrollers designed for in-vehicle applications. Consisting of the CAN function, I2C, capture, compare timer, A/D converter, and others, it is equipped with functions that are suitable for personal computer peripheral devices such as displays and audio devices, and control of devices that support in-vehicle CAN communications. ■ Feature of the MB90950 Series MB90950 series has the following features: ● Clock • Built-in PLL clock multiplier circuit • Machine clock (PLL clock) selectable from divide-by-two of oscillation clock or multiply-by-one to multiply-by-eight of oscillation clocks (4 MHz to 32 MHz when oscillation clock is 4 MHz) • Minimum instruction execution time: 31.25 ns (when operating with 4 MHz of oscillation clock and multiply-by-eight of PLL clock) ● 16 MB CPU memory space Internal 24-bit addressing ● Instruction system optimized for controllers • Various data types (bit, byte, word, long word) • Various addressing modes (23 types) • Enhanced signed instructions of multiplication/division and RETI • High-accuracy operations enhanced by 32-bit accumulator ● Instruction system for high-level language (C language)/multitask • System stack pointer • Enhanced pointer indirect instructions • Barrel shift instructions ● Higher execution speed 4-byte instruction queue 2 FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 1 OVERVIEW 1.1 MB90950 Series ● Powerful interrupt function • Powerful interrupt function with 8 levels and 34 factors • Supports maximum 16 channels of external interrupt ● CPU-independent automatic data transfer function • Extended intelligent I/O service (EI2OS): Maximum 16 channels • DMA function: Maximum 16 channels ● Low-power consumption (standby) mode • Sleep mode (that stops CPU operating clock) • Time-base timer mode (that operates only the oscillation clock, sub clock, time-base timer, and watch timer) • Watch mode (that operates only sub clock and watch timer) • Stop mode (that stops the oscillation clock and sub clock) • CPU intermittent operation mode ● Process CMOS technology ● I/O port General-purpose I/O ports (CMOS output): - 82 ports ● Timers • Time-base timer, watch timer, watchdog timer: 1 channel • 8/16-bit PPG timer: 8-bit × 16 channels or 16-bit × 8 channels • 16-bit reload timer: 4 channels • 16-bit I/O timer - 16-bit free-run timer : 2 channels (FRT0: ICU0/ICU1/ICU2/ICU3, OCU0/OCU1/OCU2/ OCU3, FRT1: ICU4/ICU5/ICU6/ICU7, OCU4/OCU5/OCU6/ OCU7) - 16-bit input capture (ICU) : 8 channels - 16-bit output compare (OCU) : 8 channels ● Full-CAN Controller: 2 channels • Conforms to CAN Specification Ver.2.0A and Ver.2.0B. • Built-in 16 message buffers • CAN wake-up CM44-10148-4E FUJITSU MICROELECTRONICS LIMITED 3 CHAPTER 1 OVERVIEW 1.1 MB90950 Series ● UART (LIN/SCI): 7 channels • Full-duplex, double buffering • Available for clock asynchronous/clock synchronous serial transfer ● I2C interface: 2 channels Capable of maximum 400 kbps of communication ● DTP/External interrupt: 16 channels, CAN wake-up: 2 channels Starts EI2OS/DMA and generates an external interrupt by an external input ● Delayed interrupt generation module Generates an interrupt request for task switching ● 8/10-bit A/D converter: 24 channels • The resolution can be switched between 8 and 10 bits • Starts by an external trigger input • Conversion time: 3 μs (including sampling time when 32 MHz machine clock) ● Program patch function Detects address match for 6 address pointers ● Low-voltage/CPU operation detection reset function (products with J-suffix) • Detects low voltage (set program to 2.8V to 4.2V) and reset automatically • Automatically reset when program hangs up and counter is not cleared within interval time (set approx. 16.4ms to approx. 524ms@ 4MHz external) ● Clock supervisor (products with J-suffix) ● Clock calibration unit (products with J-suffix) Capable of improving precision of CR oscillation circuit by calculating calibration value from measurement and performing trimming. ● Variable port input voltage level • Automotive input level/CMOS schmitt input level (the initial value for the single chip mode is Automotive level) • TTL input level (supports pins for the external bus mode only; the initial values for these pins are TTL in the external bus mode) ● External bus interface ● Clock monitor function ● 8-bit D/A converter: 2 channels 4 FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 1 OVERVIEW 1.1 MB90950 Series ■ Product Lineup Table 1.1-1 shows the product lineup for the MB90950 series. Table 1.1-1 Product Lineup List for MB90950 Series MB90F952JDS, MB90F952MDS Features F2MC-16LX CPU CPU System clock MB90V950AJAS, MB90V950AMAS On-chip PLL clock multiplier method (x1, x2, x3, x4, x6, x8, 1/2 when PLL stops) Minimum instruction execution time of 31.25 ns (at original oscillation of 4 MHz, multiply-by-eight) Flash memory ROM size External Main: 256 Kbytes Satellite: 32 Kbytes (Satellite flash emulation memory: built-in 32 Kbytes) RAM size 16 Kbytes 30 Kbytes Package QFP-100, LQFP-100 PGA-299 Emulator-dedicated power supply*1 — Included FPGA data*2 — Rev. 050617 Adaptor board*2 — MB2147-20 Rev. 04C or later *1: It is a setting for the jumper switch (TOOL VCC) when the emulator (MB2147-01) is used. Refer to the Emulator hardware manual for details. *2: Customers considering the use of other FPGA data and the adaptor boards should consult with sales representatives. CM44-10148-4E FUJITSU MICROELECTRONICS LIMITED 5 CHAPTER 1 OVERVIEW 1.1 MB90950 Series ■ Features Table 1.1-2 Peripheral Functions of the MB90950 Series (1 / 2) Function MB90F952JDS MB90F952MDS MB90V950AJAS MB90V950AMAS 7 channels UART A wide-range communication speed can be set with the dedicated reload timer. LIN function can be used as a LIN master and LIN slave. I2C (400 kbps) 2 channels 24 channels A/D converter 10/8-bit resolution Conversion time: Minimum 3 μs including sampling time (per channel) 16-bit reload timer (4 channels) Operating clock frequency: fsys/21, fsys/23, fsys/25 (fsys=system clock frequency) Supports the external event count function 16-bit I/O timer (2 channels) Outputs an interrupt signal at overflowing Supports timer clear when a match with output compare (ch.0 and ch.4) Operating clock frequency: fsys/21, fsys/22, fsys/23, fsys/24, fsys/25, fsys/26, fsys/27 (fsys=system clock frequency) I/O timer 0 (clock input FRCK0) corresponds to ICU0/ICU1/ICU2/ICU3, OCU0/OCU1/OCU2/OCU3 I/O timer 1 (clock input FRCK1) corresponds to ICU4/ICU5/ICU6/ICU7, OCU4/OCU5/OCU6/OCU7 16-bit output compare (8 channels) Outputs an interrupt signal when a match with 16-bit I/O timer and 16-bit compare registers Up to 3 of compare registers can be used to generate an output signal 16-bit input capture (8 channels) Performs the retention of I/O timer value and the generation of interrupt by the pin input (rising edge, falling edge, or both edges) 8/16-bit PPG (8 channels) Supports 8-bit and 16-bit operating modes 8-bit reload counter × 16 Lower 8-bit reload register × 16 Upper 8-bit reload register × 16 A pair of 8-bit reload counters can be configured as one 16-bit reload counter or as 8-bit prescaler plus 8-bit reload counter Operating clock frequency: fsys, fsys/21, fsys/22, fsys/23, fsys/24 or 102.4 μs when fosc = 5 MHz (fsys=system clock frequency, fosc=oscillation clock frequency) 2 channels CAN Interface External interrupt (16 channels) 6 3 channels Conforms to CAN Specification Version 2.0 Part A and Version 2.0 Part B Automatic re-transmission in case of error Automatic transmission responding to Remote Frame 16 transmitting/receiving message buffers Supports multiple messages Flexible configuration of acceptance filtering: Full bit compare / Full bit mask / Two partial bit masks Supports 10kbps to 1Mbps (When using 1 Mbps, machine clock must operate at 8 MHz or higher. When using 10 kbps, it must operate at 16 MHz or less.) Edge detection or level detection can be configured Clock calibration unit Yes No No No Clock supervisor Yes No Yes No FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 1 OVERVIEW 1.1 MB90950 Series Table 1.1-2 Peripheral Functions of the MB90950 Series (2 / 2) Function MB90F952JDS MB90F952MDS MB90V950AJAS MB90V950AMAS Low-voltage detection reset Yes No No No CPU operation detection / reset Yes No Yes No No Clock modulation Yes D/A converter Sub clock Yes No Yes No General-purpose I/O ports (CMOS output): - 82 ports Input level setting: - Port0 to Port3: Selectable among CMOS/Automotive/TTL levels - Port4 to PortA: Selectable among CMOS/Automotive levels I/O port Flash memory 2 channels Product with FLASH Supports automatic programming, Embedded Algorithm, Write/Erase/ Erase-Suspend/Resume commands A flag indicating completion of the algorithm Boot sector configuration Erase can be performed on each sector Flash security function to protect the contents of the flash Evaluation product Built-in satellite flash emulation memory CM44-10148-4E FUJITSU MICROELECTRONICS LIMITED 7 CHAPTER 1 OVERVIEW 1.2 1.2 MB90950 Series Block Diagram of the MB90950 Series This section describes the block diagram of the MB90950 series. ■ Block Diagram of the Evaluation Products Figure 1.2-1 shows the block diagram of the evaluation products. Figure 1.2-1 Block Diagram of the Evaluation Products X0, X1 Clock control circuit RST F2MC-16LX core 16-bit I/O timer 0 Clock * calibration unit CR oscillation circuit * Input capture 8 ch IN7 to IN0 RAM 30K Output compare 8 ch OUT7 to OUT0 Prescaler (7 ch) 16-bit I/O timer 1 FRCK1 UART 7 ch CAN controller 3 ch RX2 to RX0 TX2 to TX0 SOT6 to SOT0 SCK6 to SCK0 SIN6 to SIN0 AVcc AVss AN23 to AN0 AVRH AVRL ADTG 10-bit A/D converter 24 ch DA1, DA0 8-bit D/A converter 2 ch SDA1, SDA0 SCL1, SCL0 Internal data bus CPU operation detection circuit * PPGF to PPG0 FRCK0 16-bit reload timer 4 ch External bus 8/16-bit PPG 16 ch I2C interface 2 ch DMA TIN3 to TIN0 TOT3 to TOT0 AD15 to AD00 A23 to A16 ALE RD WRL WRH HRQ HAK RDY CLK DTP/ External interrupt INT15 to INT8 (INT15R to INT8R) INT7 to INT0 Clock monitor CKOT *: Only for MB90V950AJAS 8 FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 1 OVERVIEW 1.2 MB90950 Series ■ Block Diagram of Flash Products Figure 1.2-2 shows the block diagram of flash products. Figure 1.2-2 Block Diagram of Flash Products X0, X1 Clock control/ monitor * RST F2MC-16LX core 16-bit I/O timer 0 Clock calibration unit * CR oscillation circuit * Input capture 8 ch IN7 to IN0 RAM Output compare 8 ch OUT7 to OUT0 ROM/Flash 16-bit I/O timer 1 FRCK1 CAN controller 2 ch RX0, RX1 TX0, TX1 Low-voltage detection circuit CPU operation detection circuit * Satellite Flash AVcc AVss AN15 to AN0 AN23 to AN16 AVRH AVRL ADTG DA1, DA0 PPGF to PPG0 SDA1, SDA0 SCL1, SCL0 UART 7 ch Internal data bus Prescaler (7 ch) SOT6 to SOT0 SCK6 to SCK0 SIN6 to SIN0 FRCK0 16-bit reload timer 4 ch TIN3 to TIN0 TOT3 to TOT0 External bus AD15 to AD00 A23 to A16 ALE RD WRL WRH HRQ HAK RDY CLK 10-bit A/D converter 24 ch DAC 8/16-bit PPG 16 ch I2C interface 2 ch DTP/ External interrupt DMA Clock monitor INT15 to INT8 (INT15R to INT8R) INT7 to INT0 CKOT *: Products with J-suffix CM44-10148-4E FUJITSU MICROELECTRONICS LIMITED 9 CHAPTER 1 OVERVIEW 1.3 1.3 MB90950 Series Package Dimensions Two types of the package are provided for the MB90950 series. These package dimensions are only a reference. Please ask us when you need the official version. ■ Package Dimension (LQFP-100) Figure 1.3-1 shows the LQFP-100 type package dimension. Figure 1.3-1 LQFP-100 Type Package Dimension 100-pin plastic LQFP Lead pitch 0.50 mm Package width × package length 14.0 mm × 14.0 mm Lead shape Gullwing Sealing method Plastic mold Mounting height 1.70 mm Max Weight 0.65 g Code (Reference) P-LFQFP100-14×14-0.50 (FPT-100P-M20) 100-pin plastic LQFP (FPT-100P-M20) Note 1) * : These dimensions do not include resin protrusion. Note 2) Pins width and pins thickness include plating thickness. Note 3) Pins width do not include tie bar cutting remainder. 16.00±0.20(.630±.008)SQ * 14.00±0.10(.551±.004)SQ 75 51 76 50 0.08(.003) Details of "A" part +0.20 26 100 1 (0.50(.020)) 0.08(.003) M ©2005-2008 FUJITSU MICROELECTRONICS LIMITED F100031S-c-2-2 C 2005 FUJITSU LIMITED F100031S-c-2-1 0.25(.010) 0.60±0.15 (.024±.006) 25 0.20±0.05 (.008±.002) 0.10±0.10 (.004±.004) (Stand off) 0˚~8˚ "A" 0.50(.020) +.008 1.50 –0.10 .059 –.004 (Mounting height) INDEX 0.145±0.055 (.0057±.0022) Dimensions in mm (inches). Note: The values in parentheses are reference values Please confirm the latest Package dimension by following URL. http://edevice.fujitsu.com/package/en-search/ 10 FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 1 OVERVIEW 1.3 MB90950 Series ■ Package Dimension (QFP-100) Figure 1.3-2 shows the QFP-100 type package dimension. Figure 1.3-2 QFP-100 Type Package Dimension 100-pin plastic QFP Lead pitch 0.65 mm Package width × package length 14.00 × 20.00 mm Lead shape Gullwing Sealing method Plastic mold Mounting height 3.35 mm MAX Code (Reference) P-QFP100-14×20-0.65 (FPT-100P-M06) 100-pin plastic QFP (FPT-100P-M06) Note 1) * : These dimensions do not include resin protrusion. Note 2) Pins width and pins thickness include plating thickness. Note 3) Pins width do not include tie bar cutting remainder. 23.90±0.40(.941±.016) * 20.00±0.20(.787±.008) 80 51 81 50 0.10(.004) 17.90±0.40 (.705±.016) *14.00±0.20 (.551±.008) INDEX Details of "A" part 100 0.25(.010) +0.35 3.00 –0.20 +.014 .118 –.008 (Mounting height) 0~8˚ 31 1 30 0.65(.026) 0.32±0.05 (.013±.002) 0.13(.005) M 0.17±0.06 (.007±.002) 0.80±0.20 (.031±.008) 0.88±0.15 (.035±.006) "A" ©2002-2008 FUJITSU MICROELECTRONICS LIMITED F100008S-c-5-6 C 2002 FUJITSU LIMITED F100008S-c-5-5 0.25±0.20 (.010±.008) (Stand off) Dimensions in mm (inches). Note: The values in parentheses are reference values. Please confirm the latest Package dimension by following URL. http://edevice.fujitsu.com/package/en-search/ CM44-10148-4E FUJITSU MICROELECTRONICS LIMITED 11 CHAPTER 1 OVERVIEW 1.4 1.4 MB90950 Series Pin Assignment This section describes the pin assignments of the MB90950 series, depending on two types of packages. ■ Pin Assignment (QFP-100) Figure 1.4-1 shows the QFP-100 type pin assignment. MD2 RST MD0 MD1 P76/INT6 P80/TIN0/ADT G/INT12R P77/INT7 P82/SIN0/TIN2/INT 14R P81/TOT0/CKOT /INT13R P83/SOT0/TOT2 P85/SIN1 P84/SCK0/INT15R P87/SCK1 P86/SOT1 Vcc Vss P90/PPG1(0) /SIN5 P91/PPG3(2) /SOT5 P92/PPG5(4) /SCK5 P93/PPG7(6) P94/OUT0 /SIN6 P95/OUT1 /SOT6 P96/OUT2 /SCK6 PA0/RX0/INT8R P97/OUT3 PA1/TX0 P00/AD00/INT8 P01/AD01/INT9 P02/AD02/INT10 P03/AD03/INT11 Figure 1.4-1 Pin Assignment (QFP-100) 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 P04/AD04/INT12 81 50 P75/AN21/INT5 P05/AD05/INT13 82 49 P74/AN20/INT4 P06/AD06/INT14 83 48 P73/AN19/INT3 P07/AD07/INT15 84 47 P72/AN18/INT2 P10/AD08/TIN1 85 46 P71/AN17/INT1 P11/AD09/TOT1 86 45 P70/AN16/INT0 P12/AD10/SIN3/INT11R 87 44 Vss P13/AD11/SOT3 88 43 P67/AN7/PPGE(F) P14/AD12/SCK3 89 42 P66/AN6/PPGC(D) Vcc 90 41 P65/AN5/PPGA(B) Vss 91 40 P64/AN4/PPG8(9) X1 92 39 P63/AN3/PPG6(7) X0 93 38 P62/AN2/PPG4(5) P15/AD13SIN4 94 37 P61/AN1/PPG2(3) P16/AD14/SOT4 95 36 P60/AN0/PPG0(1) P17/AD15/SCK4 96 35 AVss P20/A16/PPG9(8) 97 34 AVRL P21/A17/PPGB(A) 98 33 AVRH P22/A18/PPGD(C) 99 32 AVcc P23/A19/PPGF(E) 100 31 P57/AN15/DA1 QFP - 100 P55/AN13 P56/AN14/DA0 P54/AN12/TOT3 P53/AN11/TIN3 P52/AN10/SCK2 P50/AN8/SIN2 P33/WRH P34/HRQ/OUT4 P51/AN 9/SOT 2 P32/WRL/WR/INT10R P47/SCL1 P31/RD/IN5 P46/SDA1 P30/ALE/IN4 P45/SCL0/FRCK1 P27/A23/IN3 P43/IN7/TX1 P26/A22/IN2 P44/SDA0/FRCK0 P25/A21/IN1 P42/IN6/RX1/INT9R 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 C 8 Vss 7 Vcc 6 P41 5 P40 4 P37/CLK/OUT7 3 P36/RDY/OUT6 2 P35/HAK /OUT5 1 P24/A20/IN0 Package code (mold) FPT-100P-M06 (FPT-100P-M06) 12 FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 1 OVERVIEW 1.4 MB90950 Series ■ Pin Assignment (LQFP-100) Figure 1.4-2 shows the LQFP-100 type pin assignment. MD0 RST P76/AN22/INT6 P77/AN23/INT7 P80/TIN0/ADTG/INT12R P81/TOT0/CKOT/INT13R P82/SIN0/TIN2/INT14R P83/SOT0/TOT2 P84/SCK0/INT15R P85/SIN1 P86/SOT1 P87/SCK1 Vcc Vss P90/PPG1(0)/SIN5 P91/PPG3(2)/SOT5 P92/PPG5(4)/SCK5 P93/PPG7(6) P94/OUT0/SIN6 P95/OUT1/SOT6 P96/OUT2/SCK6 P97/OUT3 PA0/RX0/INT8R PA1/TX0 P00/AD00/INT8 Figure 1.4-2 Pin Assignment (LQFP-100) P01/AD01/INT9 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 P02/AD02/INT10 77 49 MD2 P03/AD03/INT11 78 48 P75/AN21/INT5 P04/AD04/INT12 79 47 P74/AN20/INT4 P05/AD05/INT13 80 46 P73/AN19/INT3 P06/AD06/INT14 81 45 P72/AN18/INT2 P07/AD07/INT15 82 44 P71/AN17/INT1 P10/AD08/TIN1 83 43 P70/AN16/INT0 P11/AD09/TOT1 84 42 Vss P12/AD10/SIN3/INT11R 85 41 P67/AN7/PPGE(F) P13/AD11/SOT3 86 40 P66/AN6/PPGC(D) P14/AD12/SCK3 87 39 P65/AN5/PPGA(B) Vcc 88 38 P64/AN4/PPG8(9) Vss 89 37 P63/AN3/PPG6(7) X1 90 36 P62/AN2/PPG4(5) X0 91 35 P61/AN1/PPG2(3) P15/AD13/SIN4 92 34 P60/AN0/PPG0(1) P16/AD14/SOT4 93 33 AVss P17/AD15/SCK4 94 32 AVRL P20/A16/PPG9(8) 95 31 AVRH P21/A17/PPGB(A) 96 30 AVcc P22/A18/PPGD(C) 97 29 P57/AN15/DA1 P23/A19/PPGF(E) 98 28 P56/AN14/DA0 P24/A20/IN0 99 27 P55/AN13 P25/A21/IN1 100 LQFP - 100 P54/AN12/TOT3 P53/AN11/TIN3 P52/AN10/SCK2 P51/AN9/SOT2 P50/AN8/SIN2 P47/SCL1 P46/SDA1 P45/SCL0/FRCK1 P44/SDA0/FRCK0 P43/IN7/TX1 P42/IN6/RX1/INT9R C Vss Vcc P41 P40 P37/CLK/OUT7 P36/RDY/OUT6 P35/HAK/OUT5 6 7 8 26 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 P33/WRH P34/HRQ/OUT4 P32/WRL/WR/INT10R P30/ALE/IN4 P31/RD/IN5 3 4 5 P27/A23/IN3 1 2 P26/A22/IN2 Package code (mold) FPT-100P-M20 MD1 (FPT-100P-M20) CM44-10148-4E FUJITSU MICROELECTRONICS LIMITED 13 CHAPTER 1 OVERVIEW 1.5 1.5 MB90950 Series Pin Function This section describes the pin function of the MB90950 series. ■ Pin Function Table 1.5-1 Pin Function of the MB90950 Series (1 / 8) Pin No. Pin name LQFP100*2 QFP100*1 90 92 I/O circuit type*3 X1 Function Oscillation output pin A 91 93 X0 52 54 RST Oscillation input pin E General-purpose I/O port. You can set a pull-up resistor On/Off by setting a register. This function is valid in the single chip mode. P00 to P07 75 to 82 77 to 84 AD00 to AD07 G INT8 to INT15 85 General-purpose I/O port. You can set a pull-up resistor On/Off by setting a register. This function is valid in the single chip mode. G AD08 I/O pin for the external address/data bus (AD08). This function is valid when the external bus is enabled. TIN1 Event input pin for the reload timer 1 General-purpose I/O port. You can set a pull-up resistor On/Off by setting a register. This function is valid in the single chip mode. P11 84 86 G AD09 I/O pin for the external address/data bus (AD09). This function is valid when the external bus is enabled. TOT1 Output pin for the reload timer 1 General-purpose I/O port. You can set a pull-up resistor On/Off by setting a register. This function is valid in the single chip mode. P12 85 87 AD10 SIN3 INT11R 14 I/O pin for the external address/data bus lower 8-bit. This function is valid when the external bus is enabled. External interrupt request input pin for INT8 to INT15 P10 83 Reset input N I/O pin for the external address/data bus (AD10). This function is valid when the external bus is enabled. Serial data input pin for UART3 External interrupt request input pin for INT11R FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 1 OVERVIEW 1.5 MB90950 Series Table 1.5-1 Pin Function of the MB90950 Series (2 / 8) Pin No. Pin name LQFP100 *2 QFP100 *1 I/O circuit type*3 General-purpose I/O port. You can set a pull-up resistor On/Off by setting a register. This function is valid in the single chip mode. P13 86 88 G AD11 I/O pin for the external address/data bus (AD11). This function is valid when the external bus is enabled. SOT3 Serial data output pin for UART3 General-purpose I/O port. You can set a pull-up resistor On/Off by setting a register. This function is valid in the single chip mode. P14 87 89 G AD12 I/O pin for the external address/data bus (AD12). This function is valid when the external bus is enabled. SCK3 Clock I/O pin for UART3 General-purpose I/O port. You can set a pull-up resistor On/Off by setting a register. This function is valid in the single chip mode. P15 92 94 N AD13 I/O pin for the external address/data bus (AD13). This function is valid when the external bus is enabled. SCK3 Serial data input pin for UART4 General-purpose I/O port. You can set a pull-up resistor On/Off by setting a register. This function is valid in the single chip mode. P16 93 95 G AD14 I/O pin for the external address/data bus (AD14). This function is valid when the external bus is enabled. SOT4 Serial data output pin for UART4 P17 G 94 CM44-10148-4E Function 96 General-purpose I/O port. You can set a pull-up resistor On/Off by setting a register. This function is valid in the single chip mode. AD15 I/O pin for the external address/data bus (AD15). This function is valid when the external bus is enabled. SCK4 Clock I/O pin for UART4 FUJITSU MICROELECTRONICS LIMITED 15 CHAPTER 1 OVERVIEW 1.5 MB90950 Series Table 1.5-1 Pin Function of the MB90950 Series (3 / 8) Pin No. Pin name LQFP100 *2 QFP100 *1 I/O circuit type*3 General-purpose I/O port. You can set a pull-up resistor On/Off by setting the register. In the external bus mode, it is enabled as a general-purpose I/O port when the corresponding bit of the external address output control register (HACR) is set to "1". P20 to P23 95 to 98 99, 100, 1, 2 3 4 16 97 to 100 Function G A16 to A19 Output pins for the external address/data bus A16 to A19. It is enabled as the upper address output pins (A16 to A19) when the corresponding bit of the external address output control register (HACR) is set to "0". PPG9, PPGB, PPGD, PPGF Output pins for PPG P24 to P27 General-purpose I/O port. You can set a pull-up resistor On/Off by setting the register. In the external bus mode, it is enabled as a general-purpose I/O port when the corresponding bit of the external address output control register (HACR) is set to "1". 1 to 4 G A20 to A23 Output pins for the external address/data bus A20 to A23. It is enabled as the upper address output pins (A20 to A23) when the corresponding bit of the external address output control register (HACR) is set to "0". IN0 to IN3 Data sample input pins for the input capture ICU0 to ICU3 P30 General-purpose I/O port. You can set a pull-up resistor On/Off by setting a register. This function becomes valid in the single chip mode. 5 G ALE Address latch enable output pin. This function becomes valid when the external bus mode is enabled. IN4 Data sample input pin for the input capture ICU4 P31 General-purpose I/O port. You can set a pull-up resistor On/Off by setting a register. This function becomes valid in the single chip mode. 6 G RD Read strobe output pin for the data bus. This function becomes valid when the external bus is enabled. IN5 Data sample input pin for the input capture ICU5 FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 1 OVERVIEW 1.5 MB90950 Series Table 1.5-1 Pin Function of the MB90950 Series (4 / 8) Pin No. Pin name LQFP100 *2 QFP100 *1 I/O circuit type*3 General-purpose I/O port. You can set a pull-up resistor On/Off by setting a register. This function becomes valid when the single chip mode or the WR/WRL pin output is disabled. P32 5 7 G WRL/ WR INT10R 7 8 G WRH P34 General-purpose I/O port. You can set a pull-up resistor On/Off by setting a register. This function becomes valid when the single chip mode or the hold function is disabled. 9 G HRQ Hold request input pin. This function is valid when the external bus and the hold function are enabled. OUT4 Wave form output pin for the output compare OCU4 10 G CM44-10148-4E General-purpose I/O port. You can set a pull-up resistor On/Off by setting a register. This function becomes valid when the single chip mode or the hold function is disabled. HAK Hold acknowledgment output pin. This function is valid when the external bus and the hold function are enabled. OUT5 Wave form output pin for the output compare OCU5 P36 9 General-purpose I/O port. You can set a pull-up resistor On/Off by setting a register. This function becomes valid when the single chip mode, external bus 8-bit mode or the WRH pin output is disabled. Write strobe output pin for the data bus upper 8-bit. This function becomes valid when the external bus is enabled and in the external bus 16-bit mode, and WRH pin output is enabled. P35 8 Write strobe output pin for the data bus. This function becomes valid when the external bus or the WR/WRL pin output is enabled. WRL is the write strobe output pin for the data bus lower 8-bit on 16-bit access. WR is the write strobe output pin for the data bus 8-bit on 8-bit access. External interrupt request input pin for INT10R P33 6 Function 11 G General-purpose I/O port. You can set a pull-up resistor On/Off by setting a register. This function becomes valid when the single chip mode or the external ready function is disabled. RDY Ready input pin. This function becomes valid when the external bus and external ready function are enabled. OUT6 Wave form output pin for the output compare OCU6 FUJITSU MICROELECTRONICS LIMITED 17 CHAPTER 1 OVERVIEW 1.5 MB90950 Series Table 1.5-1 Pin Function of the MB90950 Series (5 / 8) Pin No. Pin name LQFP100 *2 QFP100 *1 I/O circuit type*3 P37 10 11, 12 12 13, 14 G CLK output pin. This function becomes valid when the external bus and CLK output are enabled. OUT7 Wave form output pin for the output compare OCU7 P40, P41 F 18 Data sample input pin for the input capture ICU6 F RX1 RX input pin for CAN1 interface INT9R External interrupt request input pin for INT9R P43 18 19 20 IN7 General-purpose I/O port F TX output pin for CAN1 interface P44 General-purpose I/O port SDA0 H SCL0 General-purpose I/O port H FRCK1 22 General-purpose I/O port H SDA1 P47 21 23 P50 23 24 25 AN8 O Serial data input pin for UART2 P51 General-purpose I/O port AN9 AN10 SCK2 18 Analog input pin for A/D converter SIN2 I Analog input pin for A/D converter Serial data output pin for UART2 P52 26 Serial clock I/O pin for I2C1 General-purpose I/O port SOT2 24 Serial data I/O pin for I2C1 General-purpose I/O port H SCL1 22 Serial clock I/O pin for I2C0 Input for 16-bit I/O timer 1 P46 20 Serial data I/O pin for I2C0 Input for 16-bit I/O timer 0 P45 21 Data sample input pin for the input capture ICU7 TX1 FRCK0 19 General-purpose I/O port General-purpose I/O port IN6 17 General-purpose I/O port. You can set a pull-up resistor On/Off by setting a register. This function becomes valid when the single chip mode or the CLK output is disabled. CLK P42 16 Function General-purpose I/O port I Analog input pin for A/D converter Clock I/O pin for UART2 FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 1 OVERVIEW 1.5 MB90950 Series Table 1.5-1 Pin Function of the MB90950 Series (6 / 8) Pin No. Pin name LQFP100 *2 QFP100 *1 I/O circuit type*3 P53 25 27 AN11 General-purpose I/O port I TIN3 28 AN12 General-purpose I/O port I TOT3 29 General-purpose I/O port I AN13 Analog input pin for A/D converter P56, P57 28, 29 30, 31 AN14, AN15 General-purpose I/O port J 36 to 43 Analog output pin for D/A converter P60 to P67 General-purpose I/O port PPG0, PPG2, PPG4, PPG6, PPG8, PPGA, PPGC, PPGE Analog input pin for A/D converter I Output pins for PPG P70 to P77 43 to 48, 53, 54 45 to 50, 55, 56 AN16 to AN23 General-purpose I/O port I INT0 to INT7 General-purpose I/O port TIN0 57 Event input pin for the reload timer 0 F ADTG Trigger input pin for A/D converter INT12R External interrupt request input pin for INT12R P81 General-purpose I/O port TOT0 56 58 Output pin for the reload timer 0 F CKOT INT13R CM44-10148-4E Analog input pin for A/D converter External interrupt request input pin for INT0 to INT7 P80 55 Analog input pin for A/D converter DA0, DA1 AN0 to AN7 34 to 41 Analog input pin for A/D converter Output pin for the reload timer 3 P55 27 Analog input pin for A/D converter Event input pin for the reload timer 3 P54 26 Function Output pin for the clock monitor External interrupt request input pin for INT13R FUJITSU MICROELECTRONICS LIMITED 19 CHAPTER 1 OVERVIEW 1.5 MB90950 Series Table 1.5-1 Pin Function of the MB90950 Series (7 / 8) Pin No. Pin name LQFP100 *2 QFP100 *1 I/O circuit type*3 P82 General-purpose I/O port SIN0 57 59 Serial data input for UART0 M TIN2 Event input pin for the reload timer 2 INT14R External interrupt request input pin for INT14R P83 58 60 SOT0 General-purpose I/O port F TOT2 61 SCK0 General-purpose I/O port F INT15R 62 General-purpose I/O port M SIN1 Serial data input pin for UART1 P86 61 63 General-purpose I/O port F SOT1 Serial data output pin for UART1 P87 62 65 66 64 67 68 General-purpose I/O port F SCK1 Clock I/O pin for UART1 P90 General-purpose I/O port PPG1 M Serial data input pin for UART5 P91 General-purpose I/O port PPG3 F PPG5 General-purpose I/O port F SCK5 General-purpose I/O port F 70 PPG7 Output pins for PPG P94 69 71 OUT0 SIN6 20 Output pins for PPG Clock I/O pin for UART5 P93 68 Output pins for PPG Serial data output pin for UART5 P92 69 Output pins for PPG SIN5 SOT5 67 Clock I/O pin for UART0 External interrupt request input pin for INT15R P85 60 Serial data output pin for UART0 Output pin for the reload timer 2 P84 59 Function General-purpose I/O port M Wave form output pins for the output compare OCU0. This function becomes valid when the wave form output is enabled. Serial data input pin for UART6 FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 1 OVERVIEW 1.5 MB90950 Series Table 1.5-1 Pin Function of the MB90950 Series (8 / 8) Pin No. Pin name LQFP100 *2 QFP100 *1 I/O circuit type*3 P95 70 72 OUT1 General-purpose I/O port F SOT6 72 73 OUT2 General-purpose I/O port F Clock I/O pin for UART6 P97 General-purpose I/O port 74 F PA0 75 RX0 F RX input pin for CAN0 interface. When the CAN function is used, output from the other functions must be stopped. External interrupt request input pin for INT8R PA1 76 Wave form output pins for the output compare OCU3. This function becomes valid when the wave form output is enabled. General-purpose I/O port INT8R 74 Wave form output pins for the output compare OCU2. This function becomes valid when the wave form output is enabled. SCK6 OUT3 73 Wave form output pins for the output compare OCU1. This function becomes valid when the wave form output is enabled. Serial data output pin for UART6 P96 71 Function General-purpose I/O port F TX0 TX output pin for CAN0 interface 30 32 AVCC K VCC power supply input pin for the analog circuit 31 33 AVRH L Reference voltage input for A/D converter. Make sure that AVCC is applied greater voltage than AVRH when turning on and off the power supply. 32 34 AVRL K Lower reference voltage input for A/D converter 33 35 AVSS K VSS power supply input pin for the analog circuit 50, 51 52, 53 MD1, MD0 C Input pins for operating mode selection 49 51 MD2 D Input pin for operating mode selection 13, 63, 88 15, 65, 90 VCC — Power supply input pins (3.5V to 5.5 V) 14, 42, 64, 89 16, 44, 66, 91 VSS — Power supply input pin (0 V) 15 17 C K Power supply stabilization capacitor pin. Connects a ceramic capacitor of over 0.1 μF. *1:FPT-100P-M06 *2:FPT-100P-M20 *3: See Section "1.6 I/O Circuit Type" for the I/O circuit type. CM44-10148-4E FUJITSU MICROELECTRONICS LIMITED 21 CHAPTER 1 OVERVIEW 1.6 1.6 MB90950 Series I/O Circuit Type This section describes the I/O circuit types for each pin of the MB90950 series. ■ I/O Circuit Type Table 1.6-1 I/O Circuit Type (1 / 5) Classification Circuit Remarks A Xout X1 Oscillation circuit • High-speed oscillation feedback resistor = Approximately 1 MΩ (Flash memory product) X0 Standby control signal X1 Oscillation circuit High-speed oscillation feedback resistor = Approximately 1 MΩ (Evaluation product) Xout X0 Standby control signal B X1A Oscillation circuit • Low speed oscillation feedback resistor = Approximately 10 MΩ Xout X0A Standby control signal C R 22 CMOS hysteresis input Evaluation products • CMOS hysteresis input Flash memory products • CMOS input FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 1 OVERVIEW 1.6 MB90950 Series Table 1.6-1 I/O Circuit Type (2 / 5) Classification Circuit D R Remarks CMOS hysteresis input Pull-down resistor Evaluation products • CMOS hysteresis input • Pull-down resistor value = Approximately 50 kΩ Flash memory products • CMOS input • No pull-down E • CMOS hysteresis input • Pull-up resistor value = Approximately 50 kΩ Pull-up resistor CMOS hysteresis input R F P-ch Pout N-ch Nout R CMOS hysteresis input Automotive input • CMOS level output (IOL = 4 mA, IOH = - 4 mA) • CMOS hysteresis input (VIH 0.8Vcc VIL0.2Vcc) (with the input cut-off function on standby) • Automotive input (with the input cut-off function on standby) Input cut-off standby control G Pull-up control P-ch Pout N-ch Nout R CMOS hysteresis input Automotive input TTL input • CMOS level output (IOL = 4 mA, IOH = - 4 mA) • CMOS hysteresis input (VIH 0.8Vcc VIL0.2Vcc) (with the input cut-off function on standby) • Automotive input (with the input cut-off function on standby) • TTL (with the input cut-off function on standby) • Pull-up resistor configurable resistor: Approximately 50 kΩ Input cut-off standby control CM44-10148-4E FUJITSU MICROELECTRONICS LIMITED 23 CHAPTER 1 OVERVIEW 1.6 MB90950 Series Table 1.6-1 I/O Circuit Type (3 / 5) Classification Circuit H P-ch Pout N-ch Nout R CMOS hysteresis input Automotive input CMOS hysteresis input Remarks • CMOS level output (IOL = 3 mA, IOH = - 3 mA) • CMOS hysteresis input (VIH 0.8Vcc VIL0.2Vcc) (with the input cut-off function on standby) • Automotive input (with the input cut-off function on standby) • CMOS hysteresis input (VIH 0.7Vcc VIL0.3Vcc) (with the input cut-off function on standby) Input cut-off standby control I P-ch Pout N-ch Nout R CMOS hysteresis input Automotive input • CMOS level output (IOL = 4 mA, IOH = - 4 mA) • CMOS hysteresis input (VIH 0.8Vcc VIL0.2Vcc) (with the input cut-off function on standby) • Automotive input (with the input cut-off function on standby) • A/D analog input Input cut-off standby control Analog input J P-ch Pout N-ch Nout R CMOS hysteresis input Automotive input Input cut-off standby control • CMOS level output (IOL = 4 mA, IOH = - 4 mA) • CMOS hysteresis input (VIH 0.8Vcc VIL0.2Vcc) (with the input cut-off function on standby) • Automotive input (with the input cut-off function on standby) • A/D analog input • D/A analog output Analog input Analog output 24 FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 1 OVERVIEW 1.6 MB90950 Series Table 1.6-1 I/O Circuit Type (4 / 5) Classification Circuit Remarks K Power supply input protection circuit P-ch N-ch L ANE P-ch AVR P-ch N-ch ANE N-ch M P-ch Pout N-ch Nout R CMOS hysteresis input Automotive input CMOS hysteresis input With A/D converter reference voltage input pin power supply protection circuit. AVRH pin in the flash memory products does not have the protection circuit for VCC. • CMOS level output (IOL = 4 mA, IOH = - 4 mA) • CMOS input (VIH 0.8Vcc VIL0.2Vcc) (with the input cut-off function on standby) • Automotive input (with the input cut-off function on standby) • CMOS hysteresis input (VIH 0.7Vcc VIL0.3Vcc) (with the input cut-off function on standby) Input cut-off standby control N Pull-up control P-ch Pout N-ch Nout R CMOS hysteresis input Automotive input CMOS hysteresis input TTL input Input cut-off standby control CM44-10148-4E • CMOS level output (IOL = 4 mA, IOH = - 4 mA) • CMOS hysteresis input (VIH 0.8Vcc VIL0.2Vcc) (with the input cut-off function on standby) • Automotive input (with the input cut-off function on standby) • CMOS hysteresis input (VIH 0.7Vcc VIL0.3Vcc) (with the input cut-off function on standby) • TTL input (with the input cut-off function on standby) • Pull-up resistor configurable resistor: Approximately 50 kΩ FUJITSU MICROELECTRONICS LIMITED 25 CHAPTER 1 OVERVIEW 1.6 MB90950 Series Table 1.6-1 I/O Circuit Type (5 / 5) Classification Circuit O P-ch Pout N-ch Nout R CMOS hysteresis input Automotive input CMOS hysteresis input Input cut-off standby control Remarks • CMOS level output (IOL = 4 mA, IOH = - 4 mA) • CMOS hysteresis input (VIH 0.8Vcc VIL0.2Vcc) (with the input cut-off function on standby) • Automotive input (with the input cut-off function on standby) • CMOS hysteresis input (VIH 0.7Vcc VIL0.3Vcc) (with the input cut-off function on standby) • A/D analog input Analog input 26 FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 1 OVERVIEW 1.7 MB90950 Series 1.7 Precautions when Handling Devices This section describes the precautions when handling the MB90950 series. ■ Precautions when Handling Devices ● Preventing latch-up For a CMOS IC, a latch-up phenomenon may occur when: • A voltage higher than VCC or a voltage lower than VSS is applied to the I/O pin • A voltage that exceeds the rated voltage is applied between VCC and VSS • Power supply for AVCC is supplied prior to the VCC voltage Latch-up may cause a sudden increase in supply current, resulting in thermal damage to the device. Therefore, the maximum voltage ratings must not be exceeded. By the same token, make sure that the analog supply voltage (AVCC and AVRH) should not exceed the digital supply voltage. ● Handling unused pins If unused input pins remain open, a malfunction or latch-up may cause permanent damage, so take countermeasures such as pull-up or pull-down using a 2 kΩ or larger resistor. Leave unused I/O pins open in the output state or, if left in the input state, treat them in the same manner as for input pins in use. ● Precautions when using external clock The high-speed oscillator pins (X0, X1) can not be used for external clock inputs. ● Precautions while operating PLL clock mode If the PLL clock mode is selected on this microcontroller, it may attempt to be working with the free run frequency of self-oscillating circuit in the PLL when the resonator is disconnected or clock input is stopped. Performance of this operation, however, cannot be guaranteed. CM44-10148-4E FUJITSU MICROELECTRONICS LIMITED 27 CHAPTER 1 OVERVIEW 1.7 MB90950 Series ● Power supply pins (VCC/VSS) When the device is provided with multiple VCC pins and VSS pins, the pins designed to have equal potential are internally connected to them to prevent malfunctions such as latch-up. However, be sure to connect all of the potentially equal pins to the power supply and ground outside the device to reduce unwanted radiation, prevent the strobe signal from malfunctioning due to a rise of ground level, and follow the standards of total output current (See Figure 1.7-1). The power pins should be connected to VCC and VSS of this device at the lowest possible impedance from the current supply source. We also recommend to connect an approximately 0.1 μF capacitor between VCC and VSS as a bypass capacitor near the pins of this device. Figure 1.7-1 Power Supply Pins (VCC/VSS) Vcc Vss Vcc Vss Vss Vcc MB90950 series Vcc Vss Vss Vcc ● Pull-up/pull-down resistors The MB90950 series does not support internal pull-up/pull-down resistors (However, only port0 to port3 have built-in pull-up resistors). Make pull-up/pull-down pin process when needed. ● Crystal oscillation circuit Noise near the X0 and X1 pins may cause this device to malfunction. Place the X0 and X1 pins, the crystal (or ceramic) oscillator, and the bypass capacitor leading to the ground as close to one another as possible and prevent the wiring patterns for the crystal oscillator from crossing other wiring as much as possible. For stable operation, the printed circuit board is strongly recommended to have the artwork with the X0 and X1 pins enclosed by a ground line. Please ask the crystal maker to evaluate the oscillational characteristics of the crystal and this device. 28 FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 1 OVERVIEW 1.7 MB90950 Series ● Procedure of A/D converter/analog input power-on Always apply the A/D converter power (AVCC, AVRH and AVRL) and the analog input (AN0 to AN23) after the digital power (VCC) is turned on. Always turn off the A/D converter power and the analog input before the digital power is turned down. Make sure that AVRH should not exceed AVCC at turn on or off. ● Unused pin processing of A/D converter When not using the A/D converter, the pins should be connected so that AVCC = VCC, AVSS = AVRH = AVRL = VSS. ● Precautions at power on To prevent a malfunction of the internal step-down circuit, the voltage rising time at power-on should be 50 μs or more (0.2V to 2.7 V). ● Stabilization of supplied voltage A sudden change in the supply voltage may cause the device to malfunction even within the specified VCC supply voltage operating range. Therefore, the VCC supply voltage should be stabilized. For stabilization reference, the supply voltage should be controlled so that VCC ripple variations (peak-topeak values) at commercial frequencies (50Hz to 60Hz) fall below 10% of the standard VCC supply voltage and the transient fluctuation rate does not exceed 0.1 V/ms in the momentary fluctuation, such as switching the power supply. ● Output of port0 to port3 when turning on the power supply (external bus mode) Note that the output signals of port0 to port3 may become unstable when turning on the power supply in the external bus mode (See Figure 1.7-2). Figure 1.7-2 Output Between Port0 and Port3 When Power is On VCC Internal power supply Port 0 to Port 3 Output between port0 and port3 can be unstable CM44-10148-4E Output between port0 and port3 = Hi-Z FUJITSU MICROELECTRONICS LIMITED 29 CHAPTER 1 OVERVIEW 1.7 MB90950 Series ● Note on using CAN Function When using CAN, the DIRECT bit of the CAN direct mode register (CDMR) must be set "1". (See Table 1.7-1). If the DIRECT bit is not set correctly, the device does not operate normally. Table 1.7-1 Setting of the CAN Direct Mode Setting of CAN direct mode (CDMR: DIRECT bit) Required setting 1: Enabled the CAN direct mode Setting disabled 0: Disabled the CAN direct mode (Initial state) Note: For details on the CAN direct mode, see Section "21.13 CAN Direct Mode Register (CDMR)". ● Flash security function Security bit is placed in the flash memory area. When you write the protecting code "01H" into the security bit, the security function is enabled. If you do not use this function, do not write "01H" into the address. Refer to the following table for the security bit address. MB90F952 Flash memory size Security bit address Embedded 2 Mbit Flash Memory FC0001H ● Notes when developing software using MB90V950 MB90V950 does not contain the following functions. • Low-voltage detection reset circuit • CR Clock calibration (Clock calibration unit) ● Notes for serial communication At serial communication, incorrect data may be received by noise, etc. To prevent such incorrectly receiving, the board should be designed to reduce the noise. For occuring of incorrect-data receiving by noise, etc., execute the retransmission (Example: adding the finally checksum data, etc.). 30 FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 2 CPU This chapter explains the functions and operations of the CPU. 2.1 Overview of the CPU 2.2 Memory Space 2.3 Memory Map 2.4 Linear Addressing 2.5 Bank Addressing 2.6 Multibyte Data in Memory Space 2.7 Registers 2.8 Register Bank 2.9 Prefix Codes 2.10 Interrupt Disable Instructions CM44-10148-4E FUJITSU MICROELECTRONICS LIMITED 31 CHAPTER 2 CPU 2.1 2.1 MB90950 Series Overview of the CPU The F2MC-16LX CPU core is a 16-bit CPU designed for applications that require highspeed real-time processing, such as consumer or vehicle-mounted equipment. The F2MC-16LX instruction set is designed for controller applications, and is capable of high-speed, highly efficient control processing. ■ Overview of the CPU In addition to 16-bit data, the F2MC-16LX CPU core can process 32-bit data using an internal 32-bit accumulator. Up to 16 Mbytes of memory space (expandable) can be used, which can be accessed by either the linear pointer or bank method. The instruction set, based on the F2MC-8L A-T architecture, has been reinforced by adding instructions compatible with high-level languages, expanding addressing modes, reinforcing multiplication and division instructions, and enhancing bit processing. The features of the F2MC-16LX CPU are explained below: ● Minimum instruction execution time 31.25 ns (at 4 MHz oscillation, multiply-by-eight) ● Maximum memory space 16 Mbytes, accessed in linear or bank method ● Instruction set optimized for controller applications • Rich data types: Bit, byte, word, long word • Extended addressing modes: 23 types • Reinforced high-precision operation (32-bit length) with 32-bit accumulator ● Powerful interrupt function 8 of priority levels (programmable) ● CPU-independent automatic transfer function Up to 16 channels of the extended intelligent I/O service Up to 16 channels of the DMA transfer ● Instruction set for high-level language (C language)/multitask System stack pointer/instruction set symmetry/barrel-shift instructions ● Higher execution speed 4-byte queue 32 FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 2 CPU 2.2 MB90950 Series 2.2 Memory Space The F2MC-16LX CPU has a 16 Mbytes memory space where all data program I/O managed by the F2MC-16LX CPU are located. The CPU accesses the resources by indicating their addresses using a 24-bit address bus. ■ Overview of CPU Memory Space Figure 2.2-1 shows a sample relationship between the F2MC-16LX system and memory map. Figure 2.2-1 Sample Relationship between F2MC-16LX System and Memory Map F2MC-16LX device FFFFFFH FFFC00H Programs FF0000H *1 Vector table area ROM area Program area 100000H External area*3 010000H F2MC-16LX CPU Internal data bus Peripheral circuits 008000H 007900H 001900H*2 Data EI2OS 000380H 000180H 000100H ROM area (FF bank image) Peripheral function control register area I/O area Data area General-purpose register RAM area EI2OS descriptor area External area*3 Peripheral circuits Interrupts 0000F0H 0000C0H 0000B0H Peripheral circuits 000020H General-purpose ports 000000H Peripheral function control register area Interrupt control register area Peripheral function control register area I/O port control register area I/O area *1: The size of the built-in ROM varies depending on the model. *2: The size of the built-in RAM varies depending on the model. *3: Access is not possible in single chip mode. CM44-10148-4E FUJITSU MICROELECTRONICS LIMITED 33 CHAPTER 2 CPU 2.2 MB90950 Series ■ ROM Area ● Vector table area (address: FFFC00H to FFFFFFH) • This area is used as a vector table for the reset, interrupt, and CALLV vectors. • This area is allocated at the highest addresses of the ROM area. The start address of the corresponding processing routine is set as data in each vector table address. ● Program area (address: Up to FFFBFFH) • ROM is built in as an internal program area. • The size of internal ROM varies depending on the model. ■ RAM Area ● Data area (address: 000100H to 0018FFH) • The static RAM is built in as an internal data area. • The size of internal RAM varies depending on the model. ● General-purpose register area (address: 000180H to 00037FH) • Auxiliary registers, used for 8-bit, 16-bit, and 32-bit arithmetic operations and transfer, are allocated in this area. • Since this area is allocated to a part of the RAM area, it can be used as ordinary RAM. • When this area is used as a general-purpose register, general-purpose register addressing enables high speed access with short instructions. ● Extended intelligent I/O service (EI2OS) descriptor area (address: 000100H to 00017FH) • This area retains the transfer modes, I/O addresses, transfer count, and buffer addresses. • Since this area is allocated to a part of the RAM area, it can be used as ordinary RAM. ■ I/O Area ● Interrupt control register area (address: 0000B0H to 0000BFH) The interrupt control registers (ICR00 to ICR15) support all peripheral functions that have an interrupt function, and perform the interrupt levels setting and the control of the extended intelligent I/O service (EI2OS). ● Peripheral function control register area (address: 000020H to 0000AFH, 0000C0H to 0000EFH, and 007900H to 007FFFH) This register controls the peripheral functions and inputs/outputs of data. ● I/O port control register area (address: 000000H to 00001FH) This register controls I/O ports, and inputs/outputs data. 34 FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 2 CPU 2.2 MB90950 Series ■ Address Generation Methods The F2MC-16LX has the following two addressing methods: ● Linear addressing An entire 24-bit address is specified by an instruction. ● Bank addressing Upper 8-bit of address are specified by an appropriate bank register, and the remaining lower 16-bit of address are specified by an instruction. CM44-10148-4E FUJITSU MICROELECTRONICS LIMITED 35 CHAPTER 2 CPU 2.3 2.3 MB90950 Series Memory Map Figure 2.3-1 shows the memory map of the MB90950 series. ■ Memory Map As shown in Figure 2.3-1, the upper part of the bank 00 is an image of the ROM data in the FF bank and enables the small model C compiler. Since the same is true on the lower 16-bit, the table in the ROM can be referenced without using the far specification in the pointer declaration. For example, when you try to access to 00C000H, you actually access to the value of FFC000H in the ROM. The ROM area in the bank FF cannot display the entire image into the bank 00, exceeding 32 Kbytes. The image between FF8000H and FFFFFFH is visible in bank 00, whereas the image between FF0000H and FF7FFFH is only visible in bank FF. Figure 2.3-1 Memory Map MB90F952JDS, MB90F952MDS MB90V950AJAS, MB90V950AMAS FFFFFF H ROM(FF bank) FFFFFF H ROM(FF bank) FF0000 H FEFFFFH FF0000 H FEFFFFH ROM(FE bank) ROM(FE bank) FE0000 H FDFFFFH FE0000 H FDFFFFH ROM(FD bank) FD0000 H FCFFFFH FC0000 H FBFFFFH FB0000 H FAFFFF H ROM(FC bank) ROM(FB bank) ROM(FA bank) FA0000 H F9FFFFH F90000 H F8FFFFH ROM(FD bank) FD0000 H FCFFFFH ROM(FC bank) FC0000 H FBFFFFH F78000 H F77FFF H ROM (satellite) F70000 H ROM(F9 bank) F6FFFFH ROM(F8 bank) F80000 H 00FFFFH 008000 H 007FFFH ROM (image of FF bank) Peripheral 007900 H 0078FF H 00FFFFH 008000 H 007FFFH ROM (image of FF bank) Peripheral 007900 H RAM 30K bytes 003FFF H RAM 16K bytes 000100 H 000100 H 0000EFH 000000 H Peripheral 0000EFH 000000 H Peripheral Access prohibited 36 FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 2 CPU 2.4 MB90950 Series 2.4 Linear Addressing There are two types of linear addressing: • 24-bit operand specification: Directly specifies a 24-bit address using operands. • 32-bit register indirect specification: Cites the lower 24-bit of a 32-bit general-purpose register contents as the address. ■ 24-bit Operand Specification Figure 2.4-1 and Figure 2.4-2 show examples of 24-bit operand specification and 32-bit register indirect specification respectively. Figure 2.4-1 Example of Linear Method (24-bit Operand Specification) JMPP 123456H Old program counter + program bank 17452DH 17 452D JMPP 123456H 123456 New program counter + program bank 12 Next instruction 3456 Figure 2.4-2 Example of Linear Method (32-bit Register Indirect Specification) MOV A, @RL1+7 Old AL 090700H XXXX 3A 7 RL1 240906F9 (The upper 8-bit are ignored) New AL CM44-10148-4E 003A FUJITSU MICROELECTRONICS LIMITED 37 CHAPTER 2 CPU 2.5 2.5 MB90950 Series Bank Addressing In the bank method, the 16 M byte space is divided into 256 of 64 K bytes banks. The following five bank registers are used to specify the banks corresponding to each space: • Program counter bank register (PCB) • Data bank register (DTB) • User stack bank register (USB) • System stack bank register (SSB) • Additional data bank register (ADB) ■ Bank Addressing ● Program counter bank register (PCB) The 64 Kbytes bank specified by the program counter bank register (PCB) is called a program (PC) space. The PC space typically contains instruction codes, vector tables, and immediate data. ● Data bank register (DTB) The 64 Kbytes bank specified by the data bank register (DTB) is called a data (DT) space. The DT space typically contains readable/ writable data, and control/data registers for internal and external resources. ● User stack bank register (USB) and System stack bank register (SSB) The 64 Kbytes bank specified by the user stack bank register (USB) or system stack bank register (SSB) is called a stack (SP) space. The SP space is accessed when a stack access occurs during a push/pop instruction or interrupt register saving. The S flag in the condition code register determines which stack space to be accessed. ● Additional data bank register (ADB) The 64 Kbytes bank specified by the additional data bank register (ADB) is called an additional (AD) space. The AD space typically contains data that cannot fit into the DT space. Table 2.5-1 lists the default spaces used in each addressing mode, which are pre-determined to improve instruction coding efficiency. To use a non-default space for an addressing mode, specify a prefix code corresponding to a bank before the instruction does. This enables access to the bank space corresponding to the specified prefix code. By resetting, the DTB, USB, SSB, and ADB are initialized to 00H. The PCB is initialized to a value specified by the reset vector. After reset, the DT, SP, and AD spaces are allocated in bank 00H (000000H to 00FFFFH), and the PC space is allocated in the bank specified by the reset vector. 38 FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 2 CPU 2.5 MB90950 Series Table 2.5-1 Default Space Default space Addressing Program space PC indirect, program access, branch Data space Addressing using @RW0, @RW1, @RW4, or @RW5, @A, addr16, and dir Stack space Addressing using PUSHW, POPW, @RW3, or @RW7 Additional space Addressing using @RW2 or @RW6 Figure 2.5-1 shows an example of a memory space divided into register banks. Figure 2.5-1 Physical Addresses of Each Space FFFFFFH Program space FF0000H FFH : PCB (Program counter bank register) B3H : ADB (Additional data bank register) 92H : USB (User stack bank register) B3FFFFH Additional space B30000H 92FFFFH Physical address User stack space 920000H 68FFFFH Data space 680000H 68H : DTB (Data bank register) 4BFFFFH System stack space 4B0000H 4BH : SSB (System stack bank register) 000000H CM44-10148-4E FUJITSU MICROELECTRONICS LIMITED 39 CHAPTER 2 CPU 2.6 2.6 MB90950 Series Multibyte Data in Memory Space Data is written to memory from the low-order addresses. Therefore, for a 32-bit data item, the lower 16 bits are transferred before the upper 16 bits. If a reset signal is input immediately after the lower data are written, the upper data might not be written. ■ Multibyte Data Allocation in Memory Space Figure 2.6-1 shows a sample allocation of multibyte data in memory. The lower 8 bits of a data item are stored at address n, then address n+1, address n+2, address n+3, etc. Figure 2.6-1 Sample Allocation of Multibyte Data in Memory MSB H LSB 01010101 11001100 11111111 00010100 01010101 11001100 11111111 Address n 00010100 L ■ Accessing Multibyte Data Basically, all accesses are made within a bank. For an instruction accessing a multibyte data item, the address FFFFH is followed by address 0000H of the same bank. Figure 2.6-2 shows an example of an instruction accessing multibyte data. Figure 2.6-2 Execution of MOVW A, FFFFH H AL before execution 80FFFFH ???? 01H . . . 800000H 23H AL after execution 23H 01H L 40 FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 2 CPU 2.7 MB90950 Series 2.7 Registers The F2MC-16LX registers are largely classified into two types: dedicated registers and general-purpose registers. The dedicated registers are dedicated internal hardware of the CPU, and they have specific use defined by the CPU architecture. The applications of the general-purpose registers can be specified by the user, as is ordinary memory space. Sharing the CPU address space with RAM, the generalpurpose registers are the same as the dedicated registers in that they can be accessed without using an address. ■ Dedicated Registers The F2MC-16LX CPU core has the following 11 dedicated registers: • Accumulator (A=AH: AL): 2 × 16-bit accumulators (Can be used as a single 32-bit accumulator.) • User stack pointer (USP): 16-bit pointer indicating the user stack area • System stack pointer (SSP): 16-bit pointer indicating the system stack area • Processor status (PS): 16-bit register indicating the system status • Program counter (PC): 16-bit register containing the address where the program is stored • Program counter bank register (PCB): 8-bit register indicating the PC space • Data bank register (DTB): 8-bit register indicating the DT space • User stack bank register (USB): 8-bit register indicating the user stack space • System stack bank register (SSB): 8-bit register indicating the system stack space • Additional data bank register (ADB): 8-bit register indicating the AD space • Direct page register (DPR): 8-bit register indicating a direct page Figure 2.7-1 shows the configuration of the dedicated registers. CM44-10148-4E FUJITSU MICROELECTRONICS LIMITED 41 CHAPTER 2 CPU 2.7 MB90950 Series Figure 2.7-1 Dedicated Registers AH AL Accumulator USP User stack pointer SSP System stack pointer PS Processor status PC Program counter DPR Direct page register PCB Program counter bank register DTB Data bank register USB User stack bank register SSB System stack bank register ADB Additional data bank register 8 bits 16 bits 32 bits 42 FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 2 CPU 2.7 MB90950 Series ■ General-purpose Registers As described in Figure 2.7-2, the F2MC-16LX general-purpose registers are located from 000180H to 00037FH (maximum configuration) of main storage. The register bank pointer (RP) indicates which of the above addresses is currently being used as a register bank. Each bank has the following three types of registers. These registers are mutually dependent and have a relationship below: • R0 to R7 : 8-bit general-purpose registers • RW0 to RW7 : 16-bit general-purpose registers • RL0 to RL3 : 32-bit general-purpose registers Figure 2.7-2 General-purpose Registers MSB LSB 16 bits 000180H + RP x 10H RW0 Lower RL0 First address of general-purpose register RW1 RW2 RL1 RW3 R1 R0 RW4 R3 R2 RW5 R5 R4 RW6 R7 R6 RW7 RL2 RL3 Upper The relationship between the upper/lower bytes of a byte or word register is expressed as follows: RW(i+4) = R(i × 2+1) × 256 + R(i × 2) [i = 0 to 3] The relationship between the upper/lower bytes of RLi and RW is expressed as follows: RL(i) = RW(i × 2+1) × 65536 + RW(i × 2) [i = 0 to 3] CM44-10148-4E FUJITSU MICROELECTRONICS LIMITED 43 CHAPTER 2 CPU 2.7 2.7.1 MB90950 Series Accumulator (A) The accumulator (A) register consists of 2 of 16-bit arithmetic operation registers (AH and AL), and is used as a temporary storage for operation results and transfer data. ■ Accumulator (A) During 32-bit data processing, AH and AL are used together (see Figure 2.7-3). Only AL is used for word processing in 16-bit data processing mode or for byte processing in 8-bit data processing mode (see Figure 2.7-4). The data stored in the accumulator (A) register can be operated upon with the data in memory or registers (Ri, RWi, and RLi). In the same manner as with the F2MC-8L, when a word or shorter data item is transferred to AL, the previous data item in AL is automatically sent to AH (data preservation function). The data preservation function and operation between AL and AH help improve processing efficiency. When a byte or shorter data item is transferred to AL, the data is sign-extended or zero-extended and stored as a 16-bit data item in AL. The data in AL can be handled either as word or byte long. When a byteprocessing arithmetic operation instruction is executed on AL, the upper 8 bits of AL before operation are ignored. The upper 8 bits of the operation result all become "0". The A register is not initialized by a reset and holds an undefined value right after the reset. Figure 2.7-3 Example of 32-bit Data Transfer MOVL A,@RW1+6 A before execution XXXXH MSB XXXXH A61540H 8FH 74H A6153EH 2BH 52H 15H 38H A6H DTB A after execution LSB +6 8F74H 2B52H AH AL RW1 Figure 2.7-4 Example of AL-AH Transfer MSB MOVW A,@RW1+6 A before execution XXXXH 1234H 44 A61540H 8FH 74H A6153EH 2BH 52H 15H 38H A6H DTB A after execution LSB +6 1234H 1234H AH AL RW1 FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 2 CPU 2.7 MB90950 Series 2.7.2 User Stack Pointer (USP) and System Stack Pointer (SSP) User stack pointer (USP) and system stack pointer (SSP) are 16-bit registers that indicate the memory addresses for saving/restoring data when a push/pop instruction or subroutine is executed. ■ User Stack Pointer (USP) and System Stack Pointer (SSP) User stack pointer (USP) and system stack pointer (SSP) registers are used by the stack instructions however, the USP register is enabled when the S flag in the processor status register is "0", and the SSP register is enabled when the S flag is "1" (see Figure 2.7-5). Since the S flag is set when an interrupt is accepted, register values are always saved in the memory area indicated by SSP during interrupt processing. SSP is used for stack processing in an interrupt routine, while USP is used for stack processing outside an interrupt routine. If you do not need to divide the stack space, use only the SSP. During stack processing, the upper 8 bits of an address are indicated by SSB (for SSP) or USB (for USP). USP and SSP are not initialized by a reset. Instead, they hold undefined values. Figure 2.7-5 Stack Manipulation Instruction and Stack Pointer Example of PUSHW A when the S flag is "0" Before execution AL S flag After execution AL S flag MSB C6F326H LSB A624H USB C6H USP F328H 0 SSB 56H SSP 1234H A624H USB C6H USP F326H 0 SSB 56H SSP 1234H C6F326H A6H 24H 561232H XX XX 561232H A6H 24H XX XX System stack is used because the S flag is "0". Example of PUSHW A when the S flag is "1" AL S flag AL S flag A624H USB C6H USP F328H 1 SSB 56H SSP 1234H A624H USB C6H USP F328H 1 SSB 56H SSP 1232H System stack is used because the S flag is "1". Note: When you specify a value to be set in the stack pointer, use an even-numbered address whenever possible. CM44-10148-4E FUJITSU MICROELECTRONICS LIMITED 45 CHAPTER 2 CPU 2.7 2.7.3 MB90950 Series Processor Status (PS) The processor status (PS) register consists of the bits controlling the CPU operation and the bits indicating the CPU status. ■ Processor Status (PS) As shown in Figure 2.7-6, the upper bytes of the PS register consist of the register bank pointer (RP) and the interrupt level mask register (ILM) that indicate the start address of a register bank. The lower bytes of the PS register consist of the condition code register (CCR), containing the flags to be set or reset depending on the results of instruction execution or interrupt occurrences. Figure 2.7-6 Structure of Processor Status (PS) bit 15 PS 13 12 ILM 8 7 0 RP CCR ■ Condition Code Register (CCR) Figure 2.7-7 shows the structure of the condition code register. Figure 2.7-7 Structure of Condition Code Register (CCR) bit Initial value 7 6 5 4 3 2 1 0 - I S T N Z V C - 0 1 X X X X X : CCR X : Undefined value ● Interrupt enable flag (I) Interrupt requests other than software interrupts are enabled when the I flag is "1", and are disabled when the I flag is "0". The I flag is cleared to "0" by a reset. ● Stack flag (S) When the S flag is "0", USP is enabled as the stack manipulation pointer. When the S flag is "1", SSP is enabled as the stack manipulation pointer. The S flag is set to "1" by an interrupt reception or a reset. ● Sticky bit flag (T) "1" is set in the T flag when there is at least one "1" in the data shifted out from the carry after execution of a logical right/arithmetic right shift instruction. Otherwise, "0" is set in the T flag. In addition, "0" is set in the T flag when the shift amount is zero. ● Negative flag (N) "1" is set in the N flag when the MSB of the operation result is "1". Otherwise, N flag is cleared to"0". 46 FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 2 CPU 2.7 MB90950 Series ● Zero flag (Z) The Z flag is set to "1" when the operation result is all "0". Otherwise, Z flag is cleared to "0". ● Overflow flag (V) The V flag is set when an overflow of a signed value occurs as a result of operation execution. In other cases, V flag is cleared. ● Carry flag (C) The C flag is set when a carry-up or carry-down from the MSB occurs as a result of operation execution. In other cases, C flag is cleared. ■ Register Bank Pointer (RP) As shown in Figure 2.7-8, the register bank pointer (RP) register indicates the relationship between the general-purpose registers of the F2MC-16LX and the internal RAM addresses where the general-purpose registers exist. Specifically, the RP register indicates the first memory address of the currently used register bank in the following conversion expression: [000180H + (RP) × 10H]. The RP register that consists of five bits can take a value between 00H and 1FH and allocate the register banks at addresses from 000180H to 00037FH in the memory. Even within that range, however, the register banks cannot be used as general-purpose registers if the banks are not in internal RAM. All RP register is initialized to "0" by a reset. An instruction may transfer an 8-bit immediate value to the RP register, but only the lower 5 bits of that data are used. Figure 2.7-8 Register Bank Pointer (RP) Initial value B4 B3 B2 B1 B0 0 0 0 0 0 : RP ■ Interrupt Level Mask Register (ILM) As described in Figure 2.7-9, the interrupt level mask register (ILM) consists of 3 bits, indicating the CPU interrupt masking level. Only an interrupt request of which interrupt level is higher than that indicated by these 3 bits will be accepted. Level 0 is the highest priority interrupt, and level 7 is the lowest priority interrupt (see Table 2.7-1). Therefore, for an interrupt to be accepted, its level value must be smaller than the current ILM value. When an interrupt is accepted, the level value of that interrupt is set in ILM. Thus, a subsequent interrupt of the same or lower level cannot be accepted. ILM is initialized to all "0" by a reset. An instruction may transfer an 8-bit immediate value to the ILM register, but only the lower 3 bits of that data are used. Figure 2.7-9 Interrupt Level Mask Register (ILM) Initial value CM44-10148-4E ILM2 ILM1 ILM0 0 0 0 : ILM FUJITSU MICROELECTRONICS LIMITED 47 CHAPTER 2 CPU 2.7 MB90950 Series Table 2.7-1 Levels Indicated by the Interrupt Level Mask Register (ILM) 48 ILM2 ILM1 ILM0 Level value Acceptable interrupt level 0 0 0 0 Interrupt disabled 0 0 1 1 Level value less than 1 (0 only) 0 1 0 2 Level value less than 2 (0 and 1) 0 1 1 3 Level value less than 3 (0, 1 and 2) 1 0 0 4 Level value less than 4 (0, 1, 2 and 3) 1 0 1 5 Level value less than 5 (0, 1, 2, 3 and 4) 1 1 0 6 Level value less than 6 (0, 1, 2, 3, 4 and 5) 1 1 1 7 Level value less than 7 (0, 1, 2, 3, 4, 5 and 6) FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 2 CPU 2.7 MB90950 Series 2.7.4 Program Counter (PC) The program counter (PC) register is a 16-bit counter that indicates the lower 16 bits of the memory address of an instruction code to be executed by the CPU. The upper 8 bits of the address are indicated by the PCB. The PC register is updated by a conditional branch instruction, subroutine call instruction, interrupt, or reset. The PC register can also be used as a base pointer for operand access. ■ Program Counter (PC) Figure 2.7-10 shows the program counter. Figure 2.7-10 Program Counter PCB FEH PC ABCDH Next instruction to be executed FEABCDH CM44-10148-4E FUJITSU MICROELECTRONICS LIMITED 49 CHAPTER 2 CPU 2.8 2.8 MB90950 Series Register Bank A register bank that consists of 8 words can be used as the general-purpose registers for the arithmetic operations or as the pointers for the instructions, such as byte registers R0 to R7, word registers RW0 to RW7, and long word registers RL0 to RL3. In addition, RL0 to RL3 can also be used as the linear pointers to access directly to the entire space. ■ Register Bank Table 2.8-1 lists the register functions. Table 2.8-2 shows the relationship between each register. In the same manner as for an ordinary RAM area, the register bank values are not initialized by a reset. The status before a reset is maintained. When the power is turned-on, however, the register bank will have an undefined value. Table 2.8-1 Register Functions R0 to R7 Used as operands of instructions. Note: R0 is also used as a counter for barrel shift or normalization instruction RW0 to RW7 Used as pointers and operands of instructions. Note: RW0 is used as a counter for string instructions. RL0 to RL3 Used as long pointers and operands of instructions. Table 2.8-2 Relationship between Registers RW0 RL0 RW1 RW2 RL1 RW3 R0 RW4 R1 RL2 R2 RW5 R3 R4 RW6 R5 RL3 R6 RW7 R7 50 FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 2 CPU 2.8 MB90950 Series ● Direct page register (DPR) <Initial value: 01H> Direct page register (DPR) specifies addr8 to addr15 of the instruction operands in direct addressing mode. As shown in Figure 2.8-1, DPR is 8-bit length, and is initialized to 01H by a reset. Figure 2.8-1 Generating a Physical Address by Direct Addressing DTB register DPR register Direct address during instruction MSB LSB 24-bit physical address ● Program counter bank register (PCB) <Initial value: Value in reset vector> ● Data bank register (DTB) <Initial value: 00H> ● User stack bank register (USB) <Initial value: 00H> ● System stack bank register (SSB) <Initial value: 00H> ● Additional data bank register (ADB) <Initial value: 00H> Each bank register indicates the memory bank where the PC, DT, SP (user), SP (system), or AD space is allocated. All bank registers are one byte long. PCB is initialized to 00H by a reset. Bank registers other than PCB are readable/writable. PCB is readable but not writable. PCB is updated when the JMPP, CALLP, RETP, RETIQ, or RETF instruction branching to the entire 16 M bytes space is executed or when an interrupt occurs. See Section "2.2 Memory Space" for operation of each register. CM44-10148-4E FUJITSU MICROELECTRONICS LIMITED 51 CHAPTER 2 CPU 2.9 2.9 MB90950 Series Prefix Codes Placing a prefix code before an instruction can partially change the operation of the instruction. 3 types of prefix codes can be used: bank select prefix, common register bank prefix, and flag change disable prefix. ■ Bank Select Prefix The memory space used for accessing data depends on each addressing mode. When a bank select prefix is placed before an instruction, the memory space used for accessing data by that instruction can be selected regardless of the addressing mode. Table 2.9-1 lists the bank select prefixes and the corresponding memory spaces. Table 2.9-1 Bank Select Prefix Bank select prefix Selected space PCB PC space DTB Data space ADB AD space SPB Either the SSP or USP space is used according to the stack flag value. Use the following instructions with care: ● String instructions (MOVS, MOVSW, SCEQ, SCWEQ, FILS, FILSW) The bank register specified by an operand is used regardless of the prefix. ● Stack manipulation instructions (PUSHW, POPW) SSB or USB is used according to the S flag regardless of the prefix. ● I/O access instructions MOV A,io/MOV io,A/MOVX A,io/MOVW A,io/MOVW io,A/MOV io,#imm8 MOVW io,#imm16/MOVB A,io:bp/MOVB io:bp,A/SETB io:bp/CLRB io:bp BBC io:bp,rel/BBS io:bp,rel/WBTC,WBTS I/O space in bank is used regardless of the prefix. ● Flag change instructions (AND CCR,#imm8, OR CCR,#imm8) The instruction is executed normally, but the prefix affects the next instruction. ● POPW PS Either SSB or USB is used according to the S flag regardless of the prefix. The prefix affects the next instruction. 52 FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 2 CPU 2.9 MB90950 Series ● MOV ILM,#imm8 The instruction is executed normally, but the prefix affects the next instruction. ● RETI SSB is used regardless of the prefix. ■ Common Register Bank Prefix (CMR) To simplify data exchange between multiple tasks, the same register bank must be accessed relatively easily regardless of the RP value. When the common register bank prefix (CMR) is placed before an instruction that accesses the register bank, that instruction accesses the common bank (the register bank selected when RP=0) at addresses from 000180H to 00018FH regardless of the current RP value. Use the following instructions with care: ● String instructions (MOVS, MOVSW, SCEQ, SCWEQ, FILS, FILSW) If an interrupt request occurs during execution of a string instruction with a prefix code, the string instruction is executed falsely because the prefix becomes invalid for the string instruction after the interrupt is returned. Do not attach CMR prefix to any of the above string instructions. ● Flag change instructions (AND CCR,#imm8, OR CCR,#imm8, POPW PS) The instruction is executed normally, but the prefix affects the next instruction. ● MOV ILM,#imm8 The instruction is executed normally, but the prefix affects the next instruction. ■ Flag Change Disable Prefix (NCC) To disable a flag change, use the flag change disable prefix code (NCC). Placing NCC before an instruction that disables an unwanted flag change can disable flag changes associated with that instruction. Use the following instructions with care: ● String instructions (MOVS, MOVSW, SCEQ, SCWEQ, FILS, FILSW) If an interrupt request occurs during execution of a string instruction with a prefix code, the string instruction is executed falsely because the prefix becomes invalid for the string instruction after the interrupt is returned. Do not attach NCC prefix to any of the above string instructions. ● Flag change instructions (AND CCR,#imm8, OR CCR,#imm8, POPW PS) The instruction is executed normally, but the prefix affects the next instruction. ● Interrupt instructions (INT #vct8, INT9, INTaddr16, INTPaddr24, RETI) CCR changes according to the instruction specifications regardless of the prefix. ● JCTX@A CCR changes according to the instruction specifications regardless of the prefix. ● MOV ILM,imm8 The instruction is executed normally, but the prefix affects the next instruction. CM44-10148-4E FUJITSU MICROELECTRONICS LIMITED 53 CHAPTER 2 CPU 2.10 2.10 MB90950 Series Interrupt Disable Instructions Interrupt requests are not sampled for the following 10 instructions: - MOV ILM,#imm8 - PCB - SPB - OR CCR,#imm8 - NCC - AND CCR,#imm8 - ADB - CMR - POPW PS - DTB ■ Interrupt Disable Instructions As shown in Figure 2.10-1, if a valid hardware interrupt request occurs during execution of any of the above instructions, the interrupt can be processed only when an instruction other than the above is executed. Figure 2.10-1 Interrupt Disable Instructions Interrupt disable instructions • • • • • • • • • • • (a) (a) Ordinary instruction Interrupt request occurs Interrupt accepted ■ Restrictions on Interrupt Disable Instructions and Prefix Instructions As shown in Figure 2.10-2, when a prefix code is placed before an interrupt disable instruction, the prefix code affects the first instruction other than the interrupt disable instruction after the code. Figure 2.10-2 Interrupt Disable Instructions and Prefix Codes Interrupt disable instructions MOV A, FFH NCC • • • • MOV ILM,#imm8 ADD A,01H CCR:XXX10XX CCR:XXX10XXB CCR does not change with NCC. ■ Consecutive Prefix Codes As shown in Figure 2.10-3, when competitive prefix codes are placed consecutively, the latter one becomes valid. Competitive prefix codes herein are PCB, ADB, DTB, and SPB. Figure 2.10-3 Consecutive Prefix Codes Prefix codes • • • • • ADB DTB PCB ADD A,01H • • • • • PCB becomes valid as the prefix code 54 FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 3 INTERRUPTS This chapter explains the functions and operations of the interrupts, the extended intelligent I/O service (EI2OS), and DMA. 3.1 Overview of Interrupts 3.2 Interrupt Vector 3.3 Interrupt Control Registers (ICR00 to ICR15) 3.4 Interrupt Flow 3.5 Hardware Interrupts 3.6 Software Interrupts 3.7 Extended Intelligent I/O Service (EI2OS) 3.8 Operation Flow of Extended Intelligent I/O Service (EI2OS) and its Application Procedure 3.9 μDMAC 3.10 Exceptions CM44-10148-4E FUJITSU MICROELECTRONICS LIMITED 55 CHAPTER 3 INTERRUPTS 3.1 3.1 MB90950 Series Overview of Interrupts The F2MC-16LX has interrupt functions that suspend the currently executing processing and transfer control to another specified program when a specified event occurs. There are 5 types of interrupt functions: • Hardware interrupt: Interrupt processing due to an internal peripheral event • Software interrupt: Interrupt processing due to a software event occurrence instruction • Extended intelligent I/O service (EI2OS): Transfer processing due to an internal peripheral event • μDMAC: Data transfer processing due to an internal peripheral event • Exception: Suspension due to an operation exception ■ Hardware Interrupts A hardware interrupt is activated by an interrupt request from an internal peripheral. A hardware interrupt request occurs when both the interrupt request flag and the interrupt enable flag in an internal peripheral are set. Therefore, an internal peripheral must have an interrupt request flag and interrupt enable flag to issue a hardware interrupt request. ● Specifying an interrupt level An interrupt level can be specified for the hardware interrupt. To specify an interrupt level, use the level setting bits (IL0, IL1, and IL2) of the interrupt controller. ● Masking a hardware interrupt request A hardware interrupt request can be masked by using the I flag of the processor status register (PS) in the CPU and the ILM bits (ILM2,ILM1,ILM0). When an unmasked interrupt request occurs, the CPU saves 12 bytes of data that consists of registers PS, PC, PCB, DTB, ADB, DPR, and A in the memory area indicated by the SSB and SSP registers. Figure 3.1-1 Overview of Hardware Interrupt Register file PS 2 F MC-16LX bus IR Microcode Check Comparator (5) (6) PS I ILM IR : Processor status : Interrupt enable flag : Interrupt level mask register : Instruction register (4) F2MC-16LX CPU (3) (7) (1) (2) Interrupt level (IL) AND Source FF Level comparator Peripheral Enabling FF 56 ILM I Interrupt controller FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 3 INTERRUPTS 3.1 MB90950 Series ■ Software Interrupts The software interrupt function transfers control from the program that is currently being executed by the CPU to another interrupt processing program that is defined by the user. Software interrupts are requested by executing the INT instruction. An interrupt request by the INT instruction does not have an interrupt request or enable flag. An interrupt request is issued always by executing the INT instruction. No interrupt level is assigned to the INT instruction. Therefore, ILM is not updated when the INT instruction is used. Instead, the I flag is cleared and the continuing interrupt requests are suspended. Figure 3.1-2 Overview of Software Interrupt (1) PS (2) Microcode I IR S B unit Queue Fetch PS I S IR B unit : Processor status : Interrupt enable flag : Stack flag : Instruction register : Bus interface unit F2MC-16LX CPU Save Instruction bus 2 F MC-16LX BUS Register file RAM CM44-10148-4E FUJITSU MICROELECTRONICS LIMITED 57 CHAPTER 3 INTERRUPTS 3.1 MB90950 Series ■ Extended Intelligent I/O Service (EI2OS) The extended intelligent I/O service automatically transfers data between an internal peripheral and memory. This processing is traditionally performed by an interrupt processing program, but the EI2OS enables data to be transferred in a manner similar to a DMA (direct memory access) operation. To activate the extended intelligent I/O service function from an internal peripheral, the interrupt control register (ICR) of the interrupt controller must have an extended intelligent I/O service enable bit (ISE). The extended intelligent I/O service is activated when an interrupt request occurs with "1" specified in the ISE flag. To generate a normal interrupt using a hardware interrupt request, clear the ISE flag to "0". Figure 3.1-3 Overview of Extended Intelligent I/O Service (EI2OS) Memory space IOA I/O register I/O register Peripheral Interrupt request CPU 3) ISD 3) 1) ICS 2) Interrupt control register Interrupt controller BAP 1) I/O requests transfer. 2) Interrupt controller selects a descriptor. 4) Buffer DCT 3) Transfer source/destination is read from the descriptor. 4) Data is transferred between I/O and memory. 58 FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 3 INTERRUPTS 3.1 MB90950 Series ■ Direct Memory Access (DMA) μDMA is an automatic data transfer function used between a peripheral function and memory. μDMA enables the data that is traditionally transferred by an interrupt processing program to be transferred in a manner similar to a direct memory access (DMA) operation. The interrupt processing program is automatically executed once a specified number of data transfers are completed. μDMA interrupt is one of the hardware interrupts. Figure 3.1-4 Overview of Direct Memory Access (DMA) Memory space Descriptor RAM IOA I/O register Peripheral function (I/O) I/O register (4) (a) (1) (2) (3) DMA controller (2) DMA descriptor (4) (b) BAP Buffer CPU Interrupt controller DCT IOA : I/O address pointer DER : DMA enable register BAP : Buffer address pointer DCT : Data counter (1) A peripheral (I/O) requests DMA transfer. (2) When the corresponding bit of the DMA enable register (DER) is set to "1", the DMAC controller reads transfer data (transfer source address, transfer destination address and transfer channel) from the descriptor. (3) DMA data transfer starts between I/O and memory. (4) After one item (either byte data or word data) is transferred: (a) If the transfer is not completed (DCT is not "0"), it will request the peripheral to clear the DMA transfer request. (b) If the transfer is completed (DCT=0), a transfer end flag will be set in the DMA status register upon the completion of the DMA transfer, and an interrupt request will be output to the interrupt controller. Note: To write to an internal register (DSRH, DSRL, DSSR, DERH, or DERL), use a read-modify-write (RMW) instruction. ■ Exception Processing Exception processing is basically the same as interrupt processing. When an exception is detected between instructions, the normal processing is suspended and exception processing is performed instead. In general, exception processing occurs as a result of an unexpected operation. Therefore, it is recommended to use exception processing only for debugging programs or for activating recovery software in an emergency. CM44-10148-4E FUJITSU MICROELECTRONICS LIMITED 59 CHAPTER 3 INTERRUPTS 3.2 3.2 MB90950 Series Interrupt Vector An interrupt vector uses the same area for both hardware and software interrupts. For example, interrupt request number INT42 is used for a delayed hardware interrupt and for software interrupt INT #42. Therefore, the delayed interrupt and INT #42 call the same interrupt processing routine. Interrupt vectors are allocated between addresses FFFC00H and FFFFFFH as shown in Table 3.2-1. ■ Interrupt Vector Table 3.2-1 Interrupt Vector (1 / 2) Interrupt request Interrupt control register Interrupt source No. Address Vector address: Lower Vector address: Middle Vector address: Upper Mode register INT 0 * -- -- -- FFFFFCH FFFFFDH FFFFFEH Unused INT 1 * -- -- -- FFFFF8H FFFFF9H FFFFFAH Unused . . . -- -- -- . . . . . . . . . . . . INT 7 * -- -- -- FFFFE0H FFFFE1H FFFFE2H Unused INT 8 Reset -- -- FFFFDCH FFFFDDH FFFFDEH FFFFDFH INT 9 INT9 instruction -- -- FFFFD8H FFFFD9H FFFFDAH Unused INT 10 Exception processing -- -- FFFFD4H FFFFD5H FFFFD6H Unused INT 11 CAN0 reception FFFFD0H FFFFD1H FFFFD2H Unused ICR00 0000B0H FFFFCCH FFFFCDH FFFFCEH Unused FFFFC8H FFFFC9H FFFFCAH Unused FFFFC4H FFFFC5H FFFFC6H Unused FFFFC0H FFFFC1H FFFFC2H Unused FFFFBCH FFFFBDH FFFFBEH Unused FFFFB8H FFFFB9H FFFFBAH Unused FFFFB4H FFFFB5H FFFFB6H Unused FFFFB0H FFFFB1H FFFFB2H Unused FFFFACH FFFFADH FFFFAEH Unused INT 12 CAN0 transmission/ Node status INT 13 CAN1 reception/ Input capture 6 INT 14 CAN1 transmission/ Node status/ Input capture 7 INT 15 CAN2 reception/I2C0 INT 16 CAN2 transmission/ Node status / Clock calibration unit INT 17 16-bit reload timer 0 INT 18 16-bit reload timer 1 INT 19 16-bit reload timer 2 INT 20 16-bit reload timer 3 60 ICR01 ICR02 0000B1H 0000B2H ICR03 0000B3H ICR04 0000B4H FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 3 INTERRUPTS 3.2 MB90950 Series Table 3.2-1 Interrupt Vector (2 / 2) Interrupt request Interrupt control register Interrupt source INT 21 PPG 0/1/4/5 INT 22 PPG 2/3/6/7 INT 23 PPG 8/9/C/D INT 24 PPG A/B/E/F INT 25 Time-base timer INT 26 External interrupt 0-3/8-11 INT 27 Watch timer INT 28 External interrupt 4-7/12-15 INT 29 A/D converter INT 30 I/O timer 0/1 No. Address ICR05 0000B5H ICR06 0000B6H ICR07 0000B7H ICR08 0000B8H ICR09 0000B9H ICR10 0000BAH ICR11 0000BBH ICR12 0000BCH I2C1 INT 31 Input capture 4/5 / INT 32 Output compare 0/1/4/5 INT 33 Input capture 0-3 INT 34 Output compare 2/3/6/7 INT 35 UART 0 RX INT 36 UART 0 TX INT 37 UART 1 RX / UART 3 RX / UART 5 RX INT 38 UART 1 TX / UART 3 TX / UART 5 TX INT 39 UART 2 RX / UART 4 RX / UART 6 RX INT 40 UART 2 TX / UART 4 TX / UART 6 TX INT 41 Flash memory INT 42 Delayed interrupt generation module ICR13 ICR14 Vector address: Lower Vector address: Middle Vector address: Upper Mode register FFFFA8H FFFFA9H FFFFAAH Unused FFFFA4H FFFFA5H FFFFA6H Unused FFFFA0H FFFFA1H FFFFA2H Unused FFFF9CH FFFF9DH FFFF9EH Unused FFFF98H FFFF99H FFFF9AH Unused FFFF94H FFFF95H FFFF96H Unused FFFF90H FFFF91H FFFF92H Unused FFFF8CH FFFF8DH FFFF8EH Unused FFFF88H FFFF89H FFFF8AH Unused FFFF84H FFFF85H FFFF86H Unused FFFF80H FFFF81H FFFF82H Unused FFFF7CH FFFF7DH FFFF7EH Unused FFFF78H FFFF79H FFFF7AH Unused FFFF74H FFFF75H FFFF76H Unused FFFF70H FFFF71H FFFF72H Unused FFFF6CH FFFF6DH FFFF6EH Unused FFFF68H FFFF69H FFFF6AH Unused FFFF64H FFFF65H FFFF66H Unused FFFF60H FFFF61H FFFF62H Unused FFFF5CH FFFF5DH FFFF5EH Unused FFFF58H FFFF59H FFFF5AH Unused FFFF54H FFFF55H FFFF56H Unused 0000BDH 0000BEH ICR15 0000BFH INT 43 -- -- -- FFFF50H FFFF51H FFFF52H Unused . . . -- -- -- . . . . . . . . . . . . INT 254 -- -- -- FFFC04H FFFC05H FFFC06H Unused INT 255 -- -- -- FFFC00H FFFC01H FFFC02H Unused *: When PCB is FFH, the vector area for the CALLV instruction overlaps that for INT #vct8 (#0 to #7). Care must be taken when using the vector for the CALLV instruction. CM44-10148-4E FUJITSU MICROELECTRONICS LIMITED 61 CHAPTER 3 INTERRUPTS 3.3 3.3 MB90950 Series Interrupt Control Registers (ICR00 to ICR15) The interrupt control registers are in the interrupt controller. Each interrupt control register has a corresponding I/O that has an interrupt function. The interrupt control registers have the following three functions: • Setting an interrupt level for corresponding peripherals • Selecting whether to use an ordinary interrupt or extended intelligent I/O service for the corresponding peripherals • Selecting the extended intelligent I/O service channel Do not access an interrupt control register by using a read-modify-write instruction, as doing so causes a malfunction. ■ Interrupt Control Registers (ICR00 to ICR15) Figure 3.3-1 shows the bit configuration of an interrupt control registers. Figure 3.3-1 Interrupt Control Registers (ICR00 to ICR15) bit 15/7 14/6 13/5 12/4 11/3 10/2 9/1 8/0 ICS3 ICS2 ICS1 or S1 ICS0 or S0 ISE IL2 IL1 IL0 W W * * R/W R/W R/W R/W When interrupt control registers are reset: 00000111B *: ICS1 and ICS0 are valid for write only. S1 and S0 are valid for read only. Additional information The extended intelligent I/O service channel select bits (ICR:ICS3 to ICS0) are valid for write only. The extended intelligent I/O service status bits (ICR:S1, S0) are valid for read only. In read operation, "1" is read from bit6, bit7/bit14, and bit15 (ICS2, ICS3). Note: ICS3 to ICS0 are valid only when EI2OS is activated. Set "1" in ISE to activate EI2OS, and set "0" in ISE not to activate it. When EI2OS is not to be activated, any value can be set in ICS3 to ICS0. [bit10 to bit8, bit2 to bit0] IL0, IL1, IL2 (interrupt level setting bits) These bits specify the interrupt level of the corresponding internal peripherals, and they are readable and writable. Upon a reset, these bits are initialized to level 7 (no interrupt). Table 3.3-1 describes the relationship between the interrupt level setting bits and interrupt levels. 62 FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 3 INTERRUPTS 3.3 MB90950 Series Table 3.3-1 Interrupt Level Setting Bits and Interrupt Levels IL2 IL1 IL0 Interrupt level 0 0 0 0 (Highest interrupt) 0 0 1 1 0 1 0 2 0 1 1 3 1 0 0 4 1 0 1 5 1 1 0 6 (Lowest interrupt) 1 1 1 7 (No interrupt) [bit11, bit3] ISE (extended intelligent I/O service enable bits) These bits are used to enable EI2OS. In response to an interrupt request, EI2OS is activated when "1" is set in the ISE bit and an interrupt sequence is activated when "0" is set in the ISE bit. Upon completion of EI2OS (either due to completion of a count, or a request from an internal peripheral), the ISE bit is cleared to "0". If the corresponding peripheral does not have the EI2OS function, the ISE bit must be set to "0" on the software side. These bits are readable and writable. The ISE bit is initialized to "0" by a reset. CM44-10148-4E FUJITSU MICROELECTRONICS LIMITED 63 CHAPTER 3 INTERRUPTS 3.3 MB90950 Series [bit15 to bit12, bit7 to bit4] ICS3 to ICS0 (extended intelligent I/O service channel select bits) These bits are used for write operation only. These bits specify the EI2OS channel. The values set in these bits determine the extended intelligent I/O service descriptor addresses in memory. ICS3 to ICS0 are initialized to "0000B" by a reset. Table 3.3-2 shows the correspondence between the ICS bits, channel numbers, and descriptor addresses. Table 3.3-2 ICS Bits, Channel Numbers, and Descriptor Addresses 64 ICS3 ICS2 ICS1 ICS0 Channel to be selected Descriptor address 0 0 0 0 0 000100H 0 0 0 1 1 000108H 0 0 1 0 2 000110H 0 0 1 1 3 000118H 0 1 0 0 4 000120H 0 1 0 1 5 000128H 0 1 1 0 6 000130H 0 1 1 1 7 000138H 1 0 0 0 8 000140H 1 0 0 1 9 000148H 1 0 1 0 10 000150H 1 0 1 1 11 000158H 1 1 0 0 12 000160H 1 1 0 1 13 000168H 1 1 1 0 14 000170H 1 1 1 1 15 000178H FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 3 INTERRUPTS 3.3 MB90950 Series [bit13, bit12, bit5, bit4] S0, S1 (extended intelligent I/O service status bits) These are EI2OS end status bits and used for read operation only. The values set in these bits indicate the end condition of EI2OS. They are initialized to "00B" by a reset. Table 3.3-3 shows the relationship between the S bits and the end conditions. Table 3.3-3 S bits and End Conditions CM44-10148-4E S1 S0 End condition 0 0 EI2OS running or not activated 0 1 Stop status by completion of count 1 0 Reserved 1 1 Stop status by request from internal peripheral FUJITSU MICROELECTRONICS LIMITED 65 CHAPTER 3 INTERRUPTS 3.4 3.4 MB90950 Series Interrupt Flow Figure 3.4-1 shows the interrupt flow. ■ Interrupt Flow Figure 3.4-1 Interrupt Flow I : Flag in CCR ILM : CPU register level IF : Internal peripheral interrupt request IE : Internal peripheral interrupt enable flag ENx: DMA activation request flag in DMA enable register ISE : EI2OS enable flag IL : Internal peripheral interrupt request level S : Flag in CCR START NO ENx = 1 YES DMA processing Specified number of transfers ended? Or, any end request from peripheral function? YES I & IF & IE = 1 AND ILM > IL NO YES YES ISE = 1 NO Fetching and decoding the next instruction INT instruction YES NO Executing an ordinary instruction NO Processing the extended intelligent I/O service Saving PS, PC, PCB, DTB, ADB, DPR, and A into the stack of SSP, and setting I=0, ILM=IL Completion of string instruction repetition YES Updating PC 66 NO Saving PS, PC, PCB, DTB, DPR, and A into the stack of SSP, and setting ILM=IL S ←1 Fetching the interrupt vector FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 3 INTERRUPTS 3.4 MB90950 Series Figure 3.4-2 Register Saving During Interrupt Processing Word (16 bits) H MSB LSB SSP (SSP value before interrupt) AH AL DPR ADB DTB PCB PC PS SSP (SSP value after interrupt) L CM44-10148-4E FUJITSU MICROELECTRONICS LIMITED 67 CHAPTER 3 INTERRUPTS 3.5 3.5 MB90950 Series Hardware Interrupts In response to an interrupt request signal from an internal peripheral, the CPU temporarily suspends the current program execution and transfers control to the interrupt processing program defined by the user. ■ Hardware Interrupt A hardware interrupt occurs when the relevant conditions are satisfied as a result of two operations: comparison between the interrupt request level and the value in the interrupt level mask register (ILM) of PS in the CPU, and hardware reference to the I flag value of PS. The CPU performs the following processing when a hardware interrupt occurs: • Saves the values in the PC, PS, AH, AL, PCB, DTB, ADB, and DPR registers of the CPU to the system stack. • Sets ILM in the PS register. The currently requested interrupt level is automatically set. • Fetches the corresponding interrupt vector value and branches to the processing indicated by that value. ■ Structure of Hardware Interrupt Hardware interrupts are handled by the following three sections: ● Internal peripherals Interrupt enable and request bits: Used to control interrupt requests from peripherals. ● Interrupt controller ICR: Assigns interrupt levels and determines the priority levels of simultaneously requested interrupts. ● CPU I and ILM: Used to compare the requested and current interrupt levels and to identify the interrupt enable status. Microcode: Interrupt processing step The status of these sections is indicated by the peripheral control registers for internal peripherals, the ICR for the interrupt controller, and the CCR value for the CPU. To use a hardware interrupt, set the three sections beforehand by using software. The interrupt vector table referenced during interrupt processing is assigned to addresses FFFC00H to FFFFFFH in memory. These addresses are shared with software interrupts. Table C-2 in "APPENDIX C List of MB90950 Interrupt Vectors" shows such assignment for the MB90950 series. 68 FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 3 INTERRUPTS 3.5 MB90950 Series 3.5.1 Hardware Interrupt Operation An internal peripheral with the hardware interrupt request function has 2 types of flags: the "interrupt request flag", which indicates whether an interrupt request exists; and the "interrupt enable flag", which determines whether it requests an interrupt to the CPU. An interrupt request flag is set when an event specific to that internal peripheral is generated. When the interrupt enable flag is set to "Enable", the peripheral outputs an interrupt request to the interrupt controller. ■ Hardware Interrupt Operation When more than one request is received at the same time, the interrupt controller compares the interrupt levels (IL) in ICR, selects the request with the highest level (the smallest IL value), then reports that request to the CPU. If multiple requests are at the same level, the interrupt controller selects the request with the lowest interrupt number. The relationship between the interrupt requests and ICRs is determined by the hardware. The CPU compares the received interrupt level (IL) with the ILM in the PS register. If the IL is smaller than the ILM value and the I bit in the PS register is set to "1", the CPU activates the interrupt processing microcode after completing the currently executing instruction. The CPU references the ISE bit of the ICR in the interrupt controller at the beginning of the interrupt processing microcode to check that the ISE bit is "0" (i.e. interrupt). If the ISE bit is "0", the CPU activates the interrupt processing body. The interrupt processing body saves 12 bytes (PS, PC, PCB, DTB, ADB, DPR, and A) to the memory area indicated by SSB and SSP, fetches three bytes of interrupt vector, loads them onto PC and PCB, updates the ILM of PS to a level value of the received interrupt request, sets the S flag to "1", and then performs branch processing. As a result, the interrupt processing program defined by the user is executed next. CM44-10148-4E FUJITSU MICROELECTRONICS LIMITED 69 CHAPTER 3 INTERRUPTS 3.5 MB90950 Series Occurrence and Release of Hardware Interrupt 3.5.2 Figure 3.5-1 illustrates the flow from the occurrence of a hardware interrupt until there is no interrupt request in the interrupt processing program. ■ Occurrence and Release of Hardware Interrupt Figure 3.5-1 Flow from Occurrence to Release of Hardware Interrupt F MC-16LX bus Register file Microcode PS IR (6) PS I ILM IR ILM I Check : Processor status : Interrupt enable flag : Interrupt level mask register : Instruction register Comparator (5) (4) F MC-16LX • CPU 2 · · · Enabling FF (7) AND Source FF (1) (2) Interrupt level (IL) 2 Peripheral Level comparator (3) Interrupt controller (1) An interrupt source is generated in a peripheral. (2) The interrupt enable bit in the peripheral is referenced. If an interrupt is enabled, the peripheral issues an interrupt request to the interrupt controller. (3) Upon reception of the interrupt request, the interrupt controller determines the priority levels of simultaneously requested interrupts. Then, the interrupt controller transfers the interrupt level of the corresponding interrupt to the CPU. (4) The CPU compares the interrupt level requested by the interrupt controller with the ILM bit of the processor status register. (5) If the comparison shows that the requested level is higher than the current interrupt processing level, the I flag value of the same processor status register is checked. (6) If the check in step (5) shows that the I flag indicates interrupt enable status, the requested level is written to the ILM bit. Interrupt processing is performed as soon as the currently executing instruction is completed, then control is transferred to the interrupt processing routine. (7) When the interrupt source of step (1) is cleared by software in the user interrupt processing routine, the interrupt request is completed. The time required for the CPU to execute the interrupt processing in steps (6) and (7) is shown below. For the cycle count correction values, see Table 3.5-1. Interrupt start : 24 + 6 × cycle count correction value Interrupt return : 15 + 6 × cycle count correction value (RETI instruction) 70 FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 3 INTERRUPTS 3.5 MB90950 Series Table 3.5-1 Correction Values for Interrupt Processing Cycle Count Address indicated by the stack pointer CM44-10148-4E Correction value [cycle] External, 8-bit +4 External, even-numbered address +1 External, odd-numbered address +4 Internal, even-numbered address 0 Internal, odd-numbered address +2 FUJITSU MICROELECTRONICS LIMITED 71 CHAPTER 3 INTERRUPTS 3.5 3.5.3 MB90950 Series Multiple interrupts As a special case, no hardware interrupt request can be accepted while data is being written to the I/O area. This is intended to prevent the CPU from causing an interruptrelated malfunction due to an interrupt request issued while an interrupt control register for a peripheral is being updated. If an interrupt occurs during interrupt processing, a higher level interrupt is processed first. ■ Multiple Interrupts The F2MC-16LX CPU supports multiple interrupts. If an interrupt of a higher level occurs while another interrupt is being processed, control is transferred to the high-level interrupt after the currently executing instruction is completed. After processing of the high-level interrupt is completed, the original interrupt processing is resumed. An interrupt of the same or lower level may be generated while another interrupt is being processed. If this happens, the new interrupt request is suspended until the current interrupt processing is completed, unless the ILM value or I flag is changed by an instruction. The extended intelligent I/O service cannot be activated from multiple sources; while an extended intelligent I/O service is being processed, all other interrupt requests or extended intelligent I/O service requests are suspended. Figure 3.5-2 shows the order of the registers saved in the stack. Figure 3.5-2 Registers Saved in Stack Word (16 bits) MSB LSB H SSP (SSP value before interrupt) AH AL DPR ADB DTB PCB PC PS SSP (SSP value after interrupt) L 72 FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 3 INTERRUPTS 3.6 MB90950 Series 3.6 Software Interrupts In response to execution of a special instruction, control is transferred from the program currently executed by the CPU to the interrupt processing program defined by the user. A software interrupt occurs whenever the software interrupt instruction is executed. ■ Software Interrupts The CPU performs the following processing when a software interrupt occurs: • Saves the values in the PC, PS, AH, AL, PCB, DTB, ADB, and DPR registers of the CPU to the system stack. • Sets the I flag in the PS register to "0". Interrupts are automatically disabled. • Fetches the corresponding interrupt vector value, then branches to the processing indicated by that value. A software interrupt request issued by the INT instruction has no interrupt request or enable flag. A software interrupt request is always issued by executing the INT instruction. The INT instruction does not have an interrupt level. Therefore, the INT instruction does not update ILM. The INT instruction sets the I flag to "0" to suspend subsequent interrupt requests. ■ Structure of Software Interrupts Software interrupts are handled within the CPU: CPU: Microcode: Interrupt processing step ■ List of Interrupt Vectors Table C-1 lists the interrupt vectors of the MB90950 series. As shown in Table C-1, software interrupts share the same interrupt vector area with hardware interrupts. For example, interrupt request number INT 12 is used for external hardware interrupt as well as for INT #12 of a software interrupt. Therefore, the external interrupt and INT #12 call the same interrupt processing routine. ■ Software Interrupt Operation When the CPU fetches and executes the software interrupt instruction, the software interrupt processing microcode is activated. The software interrupt processing microcode saves 12 bytes (PS, PC, PCB, DTB, ADB, DPR, and A) to the memory area indicated by SSB and SSP. The microcode fetches three bytes of interrupt vector, loads them onto PC and PCB, resets the I flag, and sets the S flag. Then, the microcode performs branch processing. As a result, the interrupt processing program defined by the user application program is executed next. Figure 3.6-1 illustrates the flow from the occurrence of a software interrupt until there is no interrupt request in the interrupt processing program. CM44-10148-4E FUJITSU MICROELECTRONICS LIMITED 73 CHAPTER 3 INTERRUPTS 3.6 MB90950 Series Figure 3.6-1 Flow from Occurrence to Release of Software Interrupt (1) F 2 MC-16LX bus I PS Register file IR (2) B unit Microcode Queue F 2MC-16LX CPU S Fetch PS I S IR : : : : Processor status Interrupt enable flag Stack flag Instruction register B unit : Bus interface unit Save Instruction bus RAM (1) The software interrupt instruction is executed. (2) Dedicated CPU registers in the register file are saved according to the microcode corresponding to the software interrupt instruction. (3) The interrupt processing is completed with the RETI instruction in the user interrupt processing routine. ■ Others When the program counter bank register (PCB) is FFH, the CALLV instruction vector area overlaps the table of the INT #vct8 instruction. When designing software, ensure that the CALLV instruction does not use the same address as that of the #vct8 instruction. Table C-2 shows the relationship of interrupt source, interrupt vector, and interrupt control register in the MB90950 series. 74 FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 3 INTERRUPTS 3.7 MB90950 Series 3.7 Extended Intelligent I/O Service (EI2OS) The extended intelligent I/O service (EI2OS) is a type of hardware interrupt operations and automatically transfers data between I/O and memory. An interrupt processing program was conventionally used for such processing, but EI2OS enables data transfer to be performed like DMA (direct memory access). ■ Extended Intelligent I/O Service (EI2OS) EI2OS has the following advantages over the conventional method: • The program size can be reduced because it is not necessary to write a transfer program. • High transfer speed is enabled by eliminating the need for saving register as no internal register is used for transfer. • Transfer can be terminated by I/O, when required, preventing unnecessary data from being transferred. • The buffer address may either be incremented or left unupdated. • The I/O register address may either be incremented or left unupdated (when update is available for the buffer address). At the end of EI2OS, processing automatically branches to an interrupt processing routine after the end condition is set. Thus, the user can identify the type of the end condition. To implement EI2OS, the hardware is distributed in two blocks. Each block has the following registers and descriptors. ● Interrupt control register Exists in the interrupt controller and indicates the ISD address. ● Extended intelligent I/O service descriptor Exists in RAM and holds the transfer mode, I/O address, number of transfers, and buffer address. Note: When REALOS is used, the extended intelligent I/O service (EI2OS) cannot be used. Figure 3.7-1 illustrates the overview of the EI2OS. CM44-10148-4E FUJITSU MICROELECTRONICS LIMITED 75 CHAPTER 3 INTERRUPTS 3.7 MB90950 Series Figure 3.7-1 Overview of Extended Intelligent I/O Service (EI2OS) Memory space by IOA I/O register I/O register Peripheral CPU Interrupt request (1) (3) ISD (3) by ICS (2) Interrupt control register Interrupt controller by BAP (1) I/O requests transfer. (4) Buffer by DCT (2) The interrupt controller selects the descriptor. (3) The transfer source and destination are read from the descriptor. (4) Data is transferred between I/O and memory. Notes: • The area that can be specified by IOA is between 000000H and 00FFFFH. • The area that can be specified by BAP is between 000000H and FFFFFFH. • The maximum transfer count that can be specified by DCT is 65,536. ■ Structure of Extended Intelligent I/O Service (EI2OS) EI2OS is handled by the following four sections: • Internal peripherals: Interrupt enable and request bits: Controls interrupt requests from peripherals. • Interrupt controller: ICR: Assigns interrupt levels, determines the priority levels of simultaneously requested interrupts, and selects the EI2OS operation. • CPU: I and ILM: Compares the requested and current interrupt levels and identifies the interrupt enable status Microcode: EI2OS processing step • RAM: Descriptor: Describes the EI2OS transfer information. 76 FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 3 INTERRUPTS 3.7 MB90950 Series 3.7.1 Extended Intelligent I/O Service Descriptor (ISD) The extended intelligent I/O service descriptor exists between 000100H and 00017FH in internal RAM, and consists of the following items: • Data counter • I/O address pointer • Status data • Buffer address pointer ■ Extended Intelligent I/O Service Descriptor (ISD) Figure 3.7-2 shows the configuration of the extended intelligent I/O service descriptor. Figure 3.7-2 Configuration of Extended Intelligent I/O Service Descriptor H Upper 8 bits of data counter (DCTH) Lower 8 bits of data counter (DCTL) Upper 8 bits of I/O address pointer (IOAH) Lower 8 bits of I/O address pointer (IOAL) EI 2OS status (ISCS) Upper 8 bits of buffer address pointer (BAPH) 000100 H + 8 × ICS Middle 8 bits of buffer address pointer (BAPM) ISD start address Lower 8 bits of buffer address pointer (BAPL) L ■ Data Counter (DCT) This is a 16-bit register that works as a counter corresponding to the number of data items transferred. This counter is decremented by 1 after data transfer. EI2OS is terminated when this counter reaches "0". Figure 3.7-3 shows the configuration of the data counter. Figure 3.7-3 Configuration of Data Counter bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DCT B15 B14 B13 B12 B11 B10 B09 B08 B07 B06 B05 B04 B03 B02 B01 B00 (Undefined at reset) CM44-10148-4E FUJITSU MICROELECTRONICS LIMITED 77 CHAPTER 3 INTERRUPTS 3.7 MB90950 Series ■ I/O Register Address Pointer (IOA) This is a 16-bit register that indicates the lower address (A15 to A00) of the buffer and I/O register used for data transfer. All of upper addresses (A23 to A16) are "0", and any I/O between addresses 000000H and 00FFFFH can be specified. Figure 3.7-4 shows the configuration of the IOA. Figure 3.7-4 Configuration of the I/O Register Address Pointer bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 IOA (Undefined at reset) A15 A14 A13 A12 A11 A10 A09 A08 A07 A06 A05 A04 A03 A02 A01 A00 ■ Buffer Address Pointer (BAP) This 24-bit register holds the address used for the next EI2OS transfer. BAP exists for each EI2OS channel independently. Therefore, each EI2OS channel can be used for transfer with anywhere in the 16-Mbyte space. If the BF bit of ISCS is set to "0" (update enabled), only the lower 16 bits of BAP changes and BAPH does not change. ■ EI2OS Status Register (ISCS) This 8-bit register indicates whether the buffer address pointer or I/O register address pointer is updated or fixed. It also indicates the transfer data length (byte/word) and transfer direction of the buffer address pointer and the I/O register address pointer. Figure 3.7-5 shows the configuration of the ISCS. Always write "0" to bit7 to bit5 of ISCS. Figure 3.7-5 Configuration of ISCS bit 7 6 5 Reserved Reserved Reserved 4 3 2 1 0 IF BW BF DIR SE ISCS (Undefined at a reset) Each bit is explained as follows. [bit4] IF This bit determines whether the I/O register address pointer is to be updated or fixed. 0: The I/O register address pointer is updated (incremented) after data transfer. 1: The I/O register address pointer is fixed after data transfer. Note: Only increment is allowed. [bit3] BW This bit specifies the transfer data length. 0: Byte 1: Word 78 FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 3 INTERRUPTS 3.7 MB90950 Series [bit2] BF This bit specifies whether the buffer address pointer is updated or fixed. 0: The buffer address pointer is updated (incremented) after data transfer. 1: The buffer address pointer is fixed after data transfer. Note: Only the lower 16 bits of the buffer address pointer are updated. [bit1] DIR This bit specifies the data transfer direction. 0: I/O address pointer → Buffer address pointer 1: Buffer address pointer → I/O address pointer [bit0] SE This bit controls the termination of the extended intelligent I/O service based on requests from internal peripherals. 0: The service is not terminated by a peripheral request. 1: The service is terminated by a peripheral request. CM44-10148-4E FUJITSU MICROELECTRONICS LIMITED 79 CHAPTER 3 INTERRUPTS 3.8 3.8 MB90950 Series Operation Flow of Extended Intelligent I/O Service (EI2OS) and its Application Procedure Figure 3.8-1 illustrates the operation flow of the extended intelligent I/O service (EI2OS) and Figure 3.8-2 shows its application procedure. ■ Operation Flow of Extended Intelligent I/O Service (EI2OS) Figure 3.8-1 Operation Flow of Extended Intelligent I/O Service (EI2OS) BAP : : : ISCS : DCT : ISE : S1 and S0 : IOA ISD Interrupt request issued from internal peripheral ISE = 1 Buffer address pointer I/O address pointer EI 2OS descriptor EI 2OS status Data counter EI 2OS enable bit EI 2OS end status NO YES Interrupt sequence Reading ISD/ISCS End request from peripheral YES SE = 1 NO DIR = 1 YES NO Data indicated by IOA ⇓ (Data transfer) Memory indicated by BAP Data transferred by BAP ⇓ (Data transfer) Memory indicated by IOA YES IF = 0 NO Update value depending on BW Updating IOA Update value depending on BW Updating BAP YES BF = 0 NO Decrementing DCT DCT = 00 NO YES Setting S1 and S0 to "01B" Setting S1 and S0 to "11B" Setting S1 and S0 to "00B" 80 Clearing peripheral interrupt request Clearing ISE to "0" CPU operation return Interrupt sequence FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 3 INTERRUPTS 3.8 MB90950 Series Figure 3.8-2 Application Procedure Flow of Extended Intelligent I/O Service (EI2OS) Processing by EI2OS Processing by CPU EI 2OS initialization Normal termination (Interrupt request) JOB execution AND(ISE=1) Data transfer Interrupt occurs due to count out or termination request from peripheral Setting extended intelligent I/O service (Switching channels) Processing data in buffer The extended EI2OS execution time for each flow is described below. ● When data transfer continues (when the stop condition is not satisfied) (Table 3.8-1 + Table 3.8-2) machine cycles ● When a stop request is issued from a peripheral (36 + 6 × Table 3.8-3) machine cycles ● When the counting is completed (Table 3.8-1 + Table 3.8-2 + (21 + 6 × Table 3.8-3)) machine cycles Table 3.8-1 Execution Time when EI2OS Continues ISCS: SE bit Set to "0" I/O address pointer Set to "1" Fixed Updated Fixed Updated Fixed 32 34 33 35 Updated 34 36 35 37 Buffer address pointer Table 3.8-2 Data Transfer Correction Values for EI2OS Execution Time Internal access I/O address pointer Buffer address pointer Internal access B/E O B/E 0 +2 O +2 +4 B: Byte data transfer E: Even-numbered address, word transfer O: Odd-numbered address, word transfer CM44-10148-4E FUJITSU MICROELECTRONICS LIMITED 81 CHAPTER 3 INTERRUPTS 3.8 MB90950 Series Table 3.8-3 Correction Values for Interrupt Handling Times Address indicated by the stack pointer 82 Correction value [cycle] External, 8-bit +4 External, even-numbered address +1 External, odd-numbered address +4 Internal, even-numbered address 0 Internal, odd-numbered address +2 FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 3 INTERRUPTS 3.9 MB90950 Series 3.9 μDMAC μDMAC is a simplified DMA with a function equivalent to the EI2OS. Notes: • μDMAC cannot be used to access the message buffer of the CAN controller through read or write operation, if the controller is in the operable state (CSR:HALT=0, and any of the BVALR:BVAL bits are set to "1" or any of the TREQR:TREQx bits are set to "1"). • Make sure that the CAN controller is stopped (all of BVALR:BVAL and TREQR:TREQ bits are set to "0", or CSR:HALT=1) before accessing the message buffer of the controller through read or write operation using μDMAC. CM44-10148-4E FUJITSU MICROELECTRONICS LIMITED 83 CHAPTER 3 INTERRUPTS 3.9 3.9.1 MB90950 Series Overview of μDMAC Provided with a descriptor register, μDMAC can transfer data faster than EI2OS. ■ Overview of μDMAC μDMAC has the following functions: • Data is automatically transferred between a peripheral (I/O) and memory. • The execution of a program by the CPU is stopped while DMA is running. • The watchdog timer operates during DMA transfer. • There are 16 DMA transfer channels available (The channel with the smallest channel number has the highest priority for DMA transfer.) • Increment or no increment option can be selected for the transfer source and transfer destination addresses. • DMA transfer is activated by an interrupt source from a peripheral (I/O). • DMA transfer is controlled by (a) DMA enable register (DER), (b) DMA stop status register (DSSR), (c) DMA status register (DSR), (d) DMA descriptor channel specification register (DCSR), and (e) DMA control register (DMACS). • STOP request can be used as a method for stopping DMA transfer from a peripheral. • Upon completion of DMA transfer, a flag is set in the corresponding bit of the DMA status register (DSR) and an interrupt is output to the interrupt controller. 84 FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 3 INTERRUPTS 3.9 MB90950 Series 3.9.2 Registers of μDMAC μDMAC has 4 registers: DCSR, DSR, DSSR, and DER. The DMA descriptors used for DMA transfer setting are explained in Section "3.9.3 DMA Descriptor Window Register (DDWR)". ■ List of Registers • DMA descriptor channel specification register (DCSR) Address: 00009BH bit 15 14 13 12 11 10 9 8 STPctrl reserved reserved reserved DCSR3 DCSR2 DCSR1 DCSR0 DCSR R/W R/W R/W R/W R/W R/W R/W R/W Initial value 00000000B • DMA status register (DSRL/DSRH) Address: 00009DH Address 00009CH bit 15 14 13 12 11 10 9 8 DTE15 DTE14 DTE13 DTE12 DTE11 DTE10 DTE9 DTE8 DSRH R/W R/W R/W R/W R/W R/W R/W R/W Initial value 00000000B 6 5 4 3 2 1 0 DTE7 DTE6 DTE5 DTE4 DTE3 DTE2 DTE1 DTE0 DSRL R/W R/W R/W R/W R/W R/W R/W R/W Initial value 00000000B bit 7 • DMA stop status register (DSSR) Address: 0000A4H Address 0000A4H bit 7 6 5 4 3 2 1 0 STP15 STP14 STP13 STP12 STP11 STP10 STP9 STP8 DSSR R/W R/W R/W R/W R/W R/W R/W R/W Initial value 00000000B 6 5 4 3 2 1 0 STP7 STP6 STP5 STP4 STP3 STP2 STP1 STP0 DSSR R/W R/W R/W R/W R/W R/W R/W R/W Initial value 00000000B bit 7 (DSSR uses bit15 to bit8 when the STPctrl bit in DCSR is set to "0", and uses bit7 to bit0 when it is set to "1".) CM44-10148-4E FUJITSU MICROELECTRONICS LIMITED 85 CHAPTER 3 INTERRUPTS 3.9 MB90950 Series • DMA enable register (DERL/DERH) Address: bit 15 0000ADH Address 0000ACH 86 bit 14 13 12 11 10 9 8 EN15 EN14 EN13 EN12 EN11 EN10 EN9 EN8 DERH R/W R/W R/W R/W R/W R/W R/W R/W Initial value 00000000B 6 5 4 3 2 1 0 EN7 EN6 EN5 EN4 EN3 EN2 EN1 EN0 DERL R/W R/W R/W R/W R/W R/W R/W R/W Initial value 00000000B 7 FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 3 INTERRUPTS 3.9 MB90950 Series 3.9.2.1 DMA Descriptor Channel Specification Register (DCSR) The DMA descriptor channel specification register (DCSR) switches the descriptor between channels. Use this register to specify a channel and then set the descriptor. ■ DMA Descriptor Channel Specification Register (DCSR) Address: 00009BH bit 15 14 13 12 11 10 9 8 STPctrl reserved reserved reserved DCSR3 DCSR2 DCSR1 DCSR0 DCSR R/W R/W R/W R/W R/W R/W R/W R/W Initial value 00000000B [bit15] STPctrl: STP control bit STPctrl bit Function 0 [Initial value] Selects STP8 to STP15 as DSSR. 1 Selects STP0 to STP7 as DSSR. [bit14 to bit12] Reserved: reserved bits These 3 bits are reserved. Reading the bits always returns "0". Always write "0" to these bits. CM44-10148-4E FUJITSU MICROELECTRONICS LIMITED 87 CHAPTER 3 INTERRUPTS 3.9 MB90950 Series [bit11 to bit8] DCSR3 to DCSR0: DMA descriptor channel specification Table 3.9-1 Relationship between DCSR and Selected Channel DCSR3 to DCSR0 Selected channel Peripheral interrupt request 0000B 0 16-bit reload timer 0 0001B 1 16-bit reload timer 1 0010B 2 16-bit reload timer 2 0011B 3 External interrupt 0 to 3, 8 to 11 0100B 4 External interrupt 4 to 7, 12 to 15 0101B 5 A/D converter 0110B 6 Input capture 4/5, I2C1 0111B 7 Output compare 0/1/4/5 1000B 8 Input capture 0 to 3 1001B 9 Output compare 2/3/6/7 1010B 10 UART0 RX 1011B 11 UART0 TX 1100B 12 UART1 RX, UART3 RX, UART5 RX 1101B 13 UART1 TX, UART3 TX, UART5 TX 1110B 14 UART2 RX, UART4 RX, UART6 RX 1111B 15 UART2 TX, UART4 TX, UART6 TX Based on the DCSR setting, the descriptor channel is selected from the 16 channels. For details, see Section "3.9.3 DMA Descriptor Window Register (DDWR)". 88 FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 3 INTERRUPTS 3.9 MB90950 Series 3.9.2.2 DMA Status Register (DSRL/DSRH) The DMA status register (DSRL/DSRH) indicates that DMA transfer is completed. As soon as "1" is set in this register, an interrupt occurs. ■ DMA Status Register (DSRL/DSRH) Address: 00009DH Address: 00009CH bit 15 14 13 12 11 10 9 8 DTE15 DTE14 DTE13 DTE12 DTE11 DTE10 DTE9 DTE8 DSRH R/W R/W R/W R/W R/W R/W R/W R/W Initial value 00000000B 6 5 4 3 2 1 0 DTE7 DTE6 DTE5 DTE4 DTE3 DTE2 DTE1 DTE0 DSRL R/W R/W R/W R/W R/W R/W R/W R/W Initial value 00000000B bit 7 [bit15 to bit0] DTE15 to DTE0: DMA status DTE15 to DTE0 bits 0 [Initial value] 1 Function No interrupt has occurred due to completion of DMA transfer. When DTE15 to DTE0 are "0", always write "0" to these bits. This indicates that DMA transfer is completed and an interrupt is being requested. The bits cannot be set to "1" when DMA transfer is stopped by a STOP request, except for the final transfer. When DTE15 to DTE0 are "1", writing "0" to these bits clears them to "0", and writing "1" retains the previous data. Note: To write to DSRL/DSRH, use a read-modify-write (RMW) instruction. CM44-10148-4E FUJITSU MICROELECTRONICS LIMITED 89 CHAPTER 3 INTERRUPTS 3.9 3.9.2.3 MB90950 Series DMA Stop Status Register (DSSR) The DMA stop status register (DSSR) indicates that DMA transfer has been stopped by a STOP request. The meaning of the bit indicated in this register varies depending on the STPctrl bit in the DMA descriptor channel specification register (DCSR). ■ DMA Stop Status Register (DSSR) When DCSR.STPctrl = 0 Address: 0000A4H bit 7 6 5 4 3 2 1 0 STP15 STP14 STP13 STP12 STP11 STP10 STP9 STP8 DSSR R/W R/W R/W R/W R/W R/W R/W R/W Initial value 00000000B 6 5 4 3 2 1 0 STP7 STP6 STP5 STP4 STP3 STP2 STP1 STP0 DSSR R/W R/W R/W R/W R/W R/W R/W R/W Initial value 00000000B When DCSR.STPctrl = 1 Address: 0000A4H bit 7 [bit15 to bit0] STP15 to STP0: DMA stop status STP15 to STP0 bits Function 0 [Initial value] A STOP request has not been accepted from a peripheral during DMA transfer. When STP15 to STP0 are "0", always write "0". 1 This indicates that DMA transfer has stopped upon reception of a STOP request from a peripheral during the DMA transfer. Note however that when a STOP request is accepted at the final transfer, STP15 to STP0 are not set to "1". When the SE bit in the DMA control register is set to "1" and a STOP request is accepted for the corresponding channel, the corresponding bit of the DMA enable register is cleared to "0". When STP15 to STP0 are "1", writing "0" clears them to "0" and writing "1" retains the previous data. Note: To write to DSSR, use a read-modify-write (RMW) instruction. 90 FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 3 INTERRUPTS 3.9 MB90950 Series The following 3 channels support the STOP request. Channel Corresponding STPx bit Peripheral ch.10 STP10 UART0 RX ch.12 STP12 UART1 RX, UART3 RX, UART5 RX ch.14 STP14 UART2 RX, UART4 RX, UART6 RX Bits other than STP10, STP12 and STP14 have no meaning. Note: DSSR is controlled by the highest bit (STPctrl) of DCSR. When STPctrl is "0", bit15 to bit8 are selected as DSSR. When STPctrl is "1", bit7 to bit0 are selected as DSSR. As the initial value of STPctrl is "0", bit15 to bit8 are originally selected. CM44-10148-4E FUJITSU MICROELECTRONICS LIMITED 91 CHAPTER 3 INTERRUPTS 3.9 3.9.2.4 MB90950 Series DMA Enable Register (DERL/DERH) The DMA enable register (DERL/DERH) enables DMA transfer. When "1" is set in this register and an interrupt request occurs at the corresponding channel, it is regarded as a DMA transfer request and DMA transfer starts. ■ DMA Enable Register (DERL/DERH) Address: bit 15 0000ADH Address: 14 13 12 11 10 9 8 EN15 EN14 EN13 EN12 EN11 EN10 EN9 EN8 DERH R/W R/W R/W R/W R/W R/W R/W R/W Initial value 00000000B 6 5 4 3 2 1 0 EN7 EN6 EN5 EN4 EN3 EN2 EN1 EN0 DERL R/W R/W R/W R/W R/W R/W R/W R/W Initial value 00000000B bit 0000ACH 7 [bit15 to bit0] EN15 to EN0: DMA enable EN15 to EN0 bits 0 [Initial value] 1 Function DMA transfer is not executed. An interrupt request from a peripheral is handled as a DMA start request and the interrupt request is output to the interrupt controller upon completion of the DMA transfer. Cleared to "0" when there is no more DMA transfer, or when DMA transfer is stopped by a STOP request from the peripheral. Notes: • To write to DERL/DERH, use a read-modify-write (RMW) instruction. • Always set EN15 to EN0 to "0", before changing the mode to a standby mode (sleep mode, stop mode, watch mode, or time-base timer mode) or a CPU clock intermittent operating mode (main clock intermittent operating mode, PLL clock intermittent operating mode, or sub clock intermittent operating mode). 92 FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 3 INTERRUPTS 3.9 MB90950 Series 3.9.3 DMA Descriptor Window Register (DDWR) The DMA descriptor consists of 16 channels of 8 bytes and is used to set DMA transfer. Out of the 16 channels, one specified channel is mapped to the DMA descriptor window register (DDWR) and can be accessed. The DDWR addresses are 0000D0H to 0000D7H. ■ Configuration of DMA Descriptor Window Register (DDWR) The DMA descriptor consists of 16 channels of 8 bytes, and each channel is structured as illustrated in Figure 3.9-1. The descriptor of the channel selected by the DMA descriptor channel specification register (DCSR) or the interrupt request channel number is mapped to the DMA descriptor window register (DDWR). For the relationship between the DMA descriptor channel specification register (DCSR) and the selected channel, see Table 3.9-1. Figure 3.9-1 Configuration of DMA Descriptor Window Register (DDWR) Address 0000D7H Upper 8 bits of data counter (DCTH) 0000D6H Lower 8 bits of data counter (DCTL) 0000D5H Upper 8 bits of I/O register address pointer (IOAH) 0000D4H Lower 8 bits of I/O register address pointer (IOAL) 0000D3H DMA control register (DMACS) 0000D2H Upper 8 bits of buffer address pointer (BAPH) 0000D1H Middle 8 bits of buffer address pointer (BAPM) 0000D0H Lower 8 bits of buffer address pointer (BAPL) ■ Registers of DMA Descriptor The registers that form the DMA descriptor are explained on the following pages. The initial value of each register is undefined at a reset. Therefore, always initialize it before setting EN15 to EN0 to "1". Note: When the channel descriptor is switched by the DMA descriptor channel specification register (DCSR), the DMA descriptor window register (DDWR) is not allowed to be accessed during 2 machine cycles. CM44-10148-4E FUJITSU MICROELECTRONICS LIMITED 93 CHAPTER 3 INTERRUPTS 3.9 3.9.3.1 MB90950 Series Data Counter (DCTL/DCTH) The data counter (DCTL/DCTH) is a register that sets the number of data transfers. When the data counter (DCTL/DCTH) is set to "0", the DMA transfer is completed. ■ Data Counter (DCTL/DCTH) The data counter (DCTL/DCTH) is a 16-bit register that corresponds to the number of transfers. After the transfer of each data item, the counter decrements (decreases) the value by 1, regardless of whether it is a word or byte transfer. The DMA transfer is completed when the counter is set to "0". Figure 3.9-2 shows the configuration of DCTL/DCTH. Setting "0" in DCT sets the maximum number of data transfers (65536). Figure 3.9-2 Data Counter (DCTL/DCTH) Address 0000D7H /0000D6H DCTL DCTH bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 DCTL/ B15 B14 B13 B12 B11 B10 B09 B08 B07 B06 B05 B04 B03 B02 B01 B00 DCTH Initial value XXXXXXXXXXXXXXXXB R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W : Readable/Writable X : Undefined ■ Setting Value of Data Counter (DCTL/DCTH) The relationship between the number of transfer bytes and the data counter (DCTL/DCTH) is as follows. DMACS DCTL/DCTH BW bit BYTEL bit 0 — N 1 0 N/2 1 1 (N+1)/2 N: Number of transfer bytes 94 FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 3 INTERRUPTS 3.9 MB90950 Series 3.9.3.2 I/O Register Address Pointer (IOAL/IOAH) The I/O register address pointer (IOAL/IOAH) sets the I/O address pointer. The upper bits of the address (A23 to A16) are fixed to "00H". ■ I/O Register Address Pointer (IOAL/IOAH) The I/O register address pointer (IOAL/IOAH) is a 16-bit register that indicates the lower 16 bits (A15 to A00) of the I/O register address. The upper bits of the address (A23 to A16) are all "0", and any address from "000000H" to "00FFFFH" can be specified in the I/O address space. When the IF bit (IOAL/IOAH update/fixing selection bit) in the DMA control register (DMACS) is set to "perform update", IOAL/IOAH is updated by "+1" for a byte transfer, and by "+2" for a word transfer. When the IF bit is set to "perform no update", IOAL/IOAH is fixed. Figure 3.9-3 shows the configuration of IOAL/IOAH. Figure 3.9-3 Configuration of I/O Register Address Pointer (IOAL/IOAH) Address: 0000D5H/0000D4H IOAL IOAH bit15 bit14 bit13 bit12 bit11 bit10 IOA bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 A15 A14 A13 A12 A11 A10 A09 A08 A07 A06 A05 A04 A03 A02 A01 A00 Initial value XXXXXXXXXXXXXXXXB R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W : Readable/Writable X : Undefined CM44-10148-4E FUJITSU MICROELECTRONICS LIMITED 95 CHAPTER 3 INTERRUPTS 3.9 3.9.3.3 MB90950 Series DMA Control Register (DMACS) The DMA control register (DMACS) controls DMA transfers. The DMA control register (DMACS) can be used to control the following: • Direction control (IOA → BAP, BAP → IOA) • Transfer bit length (byte, word) • Address update (enabled, disabled) • Transfer interval • Odd-numbered byte control during word transfer ■ DMA Control Register (DMACS) The DMA control register (DMACS) is an 8-bit register that updates or fixes the buffer address pointer and the I/O register address pointer, specifies the transfer data format (byte/word), transfer direction and byte transfer option, and gives a wait indication. Figure 3.9-4 shows the configuration of DMACS. Figure 3.9-4 Configuration of DMA Control Register (DMACS) bit7 bit6 bit5 Address: BYTEL RDY2 RDY1 0000D3H R/W R/W R/W bit4 bit2 bit1 bit0 IF BW BF DIR SE R/W R/W R/W bit3 SE R/W Initial value XXXXXXXXB R/W DMA transfer end control bit 0 Does not end transfer by request from peripheral function 1 Ends transfer by request from peripheral function Data transfer direction specification bit DIR 0 I/O register address pointer → Buffer address pointer 1 Buffer address pointer → I/O register address pointer BAP update/fixing selection bit BF 0 Updates buffer address pointer after data transfer 1 Does not update buffer address pointer after data transfer Transfer data length specification bit BW 0 Byte 1 Word IF IOA update/fixing selection bit 0 Updates I/O register address pointer after data transfer 1 Does not update I/O register address pointer after data transfer BYTEL Byte transfer specification bit (Only valid for word transfer) 0 Even-numbered byte 1 Odd-numbered byte (RDY2,RDY1) R/W: Readable/Writable X: Undefined 96 Wait indication bits (See Figure 3.9-5) (0 ,0 ) Does not place a wait between transfers (0 ,1 ) Place 1 cycle of wait between transfers (1 ,0 ) Place 2 cycles of wait between transfers (1 ,1 ) Place 3 cycles of wait between transfers FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 3 INTERRUPTS 3.9 MB90950 Series Figure 3.9-5 Explanation of Wait Indication Bits Reading transfer source Writing transfer destination Wait Reading transfer source Writing transfer destination RDY2 and RDY1 are used to define the length of the waiting part of transfer as shown in the above figure. Note: When writing transmission data to LIN-UART using DMACS register to (0, 0). CM44-10148-4E μDMAC, do not set RDY2 and RDY1 bits in the FUJITSU MICROELECTRONICS LIMITED 97 CHAPTER 3 INTERRUPTS 3.9 MB90950 Series Buffer Address Pointer (BAPL/BAPM/BAPH) 3.9.3.4 The buffer address pointer (BAPL/BAPM/BAPH) is a register that sets the buffer address pointer. A23 to A00 can be set to the buffer address pointer (BAPL/BAPM/BAPH). ■ Buffer Address Pointer (BAPL/BAPM/BAPH) The buffer address pointer (BAPL/BAPM/BAPH) is a 24-bit register that stores the address used for DMA transfer. As BAPL, BAPM, and BAPH exist independently, corresponding to separate channels, each channel of DMA can transfer data between any 16-Mbyte address and I/O. When the BF bit (BAPL/ BAPM/BAPH update/fixing selection bit) in the DMA control register (DMACS) is set to "perform update", the lower 16 bits (BAPM, BAPL) are updated by "+1" for a byte transfer, and by "+2" for a word transfer. The upper 8 bits (BAPH) remain unchanged. Figure 3.9-6 shows the configuration of the buffer address pointer (BAPL/BAPM/BAPH). Figure 3.9-6 Configuration of Buffer Address Pointer (BAPL/BAPM/BAPH) Address: 0000D2H /0000D1H /0000D0 H BAP bit23 to bit16 BAPH bit15 to bit8 BAPM bit7 to bit0 BAPL R/W R/W R/W Initial value XXXXXXXX XXXXXXXX XXXXXXXXB R/W : Readable/Writable X : Undefined Notes: • The I/O register address pointer (IOA) can specify the area from "000000H" to "00FFFFH". • The buffer address pointer (BAP) can specify the area from "000000H" to "FFFFFFH". • It is prohibited to set IOA and BAP to the addresses of μDMAC internal registers DCSR, DSRH, DSRL, DSSR, DERH and DERL, and the address of the DMA descriptor window register (DDWR). 98 FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 3 INTERRUPTS 3.9 MB90950 Series 3.9.4 Operating Explanation of μDMAC This section explains the operation of μDMAC. ■ Operation of μDMAC Figure 3.9-7 shows a block diagram for explaining the operation of μDMAC. DMAC data transfer is performed in the following sequence: (1) A peripheral (I/O) requests DMA transfer. (2) When the DMA enable register (DER) is "1", DMAC reads from the descriptor the transfer source and destination addresses of the specified channel as well as transfer data such as the number of transfers. (3) DMA data transfer starts between I/O and memory. (4) After 1 byte or 1 word is transferred: (a) If the transfer is not completed (data counter DCT ≠ 0), the peripheral will be requested to clear the DMA transfer request. (b) If the transfer is completed (data counter DCT = 0), a transfer end flag is set in the DMA status register upon completion of the DMA transfer, and an interrupt request is output to the interrupt controller. Note: To write to an internal register DSRH, DSRL, DSSR, DERH, or DERL, use a read-modify-write (RMW) instruction. Figure 3.9-7 Operation of μDMAC Memory space IOA I/O register Peripheral function I/O register (4) (a) Descriptor RAM ( I/O ) (1) (2) (3) DMA controller (2) (4) (b) BAP Buffer CPU DMA descriptor Interrupt controller DCT IOA : I/O address pointer DER: DMA enable register BAP: Buffer address pointer DCT: Data counter CM44-10148-4E FUJITSU MICROELECTRONICS LIMITED 99 CHAPTER 3 INTERRUPTS 3.9 MB90950 Series ■ DMAC Application Procedure Figure 3.9-8 shows the application procedure for DMAC. Figure 3.9-8 DMAC Application Procedure Hardware processing Software processing (Interrupt occurs) Start NO Relevant channel: ENx=1 Setting of system stack area YES YES Initial settings Initial setting of peripheral function STOP request and SE=1 NO DMA transfer Setting of interrupt control register (BAP) Initial setting of μDMAC (IOA) Parallel processing BF = 0 NO NO IF = 0 YES Execution of user program BW = 1 YES NO BW = 1 YES BYTEL = 0 NO YES BAP = BAP+2 NO YES NO BYTEL = 0 NO DCT = 0 YES DCT = 0 YES YES IOA = IOA+2 BAP = BAP+1 STPx = 1 NO IOA = IOA+1 NO DCT = 0 YES DTEx = 1 ENx = 0 (Jump to Interrupt routine) * Interrupt processing NO Another interrupt occurs YES Interrupt occurs YES NO Completion of processing ENx DTEx STPx * 100 : Relevant bit of DMA enable register : Relevant bit of DMA status register : Relevant bit of DMA stop status register : Outputting interrupt request to interrupt controller FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 3 INTERRUPTS 3.9 MB90950 Series ■ Number of Data Transfer Cycles (Internal Transfer) When μDMAC obtains the bus right and data is transferred within the LSI, the number of transfer cycles is as follows. Table 3.9-2 Cycles from Obtaining Bus Right until Transfer Start Match between DCSR3 to DCSR0 in DCSR and interrupt request channels Mismatch between DCSR3 to DCSR0 in DCSR and interrupt request channels 1 machine cycle 2 machine cycles Table 3.9-3 Transfer Cycles Address pointer DMACS Number of cycles BAP IOA BW BYTEL ⎯ ⎯ 0 ⎯ 4 + (RDY2, RDY1)*1 machine cycles O E 1 ⎯ 6 + (RDY2, RDY1)*2 machine cycles E O O O 1 ⎯ 8 + (RDY2, RDY1)*2 machine cycles E E 1 ⎯ 4 + (RDY2, RDY1)*1 machine cycles *1: (RDY2, RDY1) becomes "0" during the final transfer. *2: When BYTEL is "1", the number of cycles is 4, and (RDY2, RDY1) becomes "0". When BYTEL is "0", (RDY2, RDY1) becomes "0". O: Odd-numbered address E: Even-numbered address ■ Watchdog Timer Figure 3.9-9 shows the operation of the watchdog timer during DMA transfer. A reset occurs during transfer, when the transfer exceeds the interval time of the watchdog timer set by the WT1/WT0 bits in the watchdog timer control register (WDTC). CM44-10148-4E FUJITSU MICROELECTRONICS LIMITED 101 CHAPTER 3 INTERRUPTS 3.9 MB90950 Series Figure 3.9-9 Watchdog Timer during DMAC Transfer Count continues Count starts Count starts Reset (1) Reset released WTEbit=0 (2) (3) (4) (5) (6) μDMAC activated 1st transfer starts Interrupt source generated μDMAC register settings (1) 1st 1 byte transfer in progress DCSR: Channel selected (2) 2nd 1 byte transfer in progress DER: DMA enabled (3) 3rd 1 byte transfer in progress DDWR: (4) 4th 1 byte transfer in progress DCT=10 the number of (5) 5th 1 byte transfer in progress transfers: 10 (6) 6th 1 byte transfer in progress BW=0 byte transfer (7) 7th 1 byte transfer in progress WTEbit=0 (7) (8) (9) (10) Time Jump to interrupt routine Interrupt processing executed μDMAC transfer completed To interrupt controller Interrupt request generated (8) 8th 1 byte transfer in progress (9) 9th 1 byte transfer in progress (10) 10th 1 byte transfer in progress 102 FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 3 INTERRUPTS 3.10 MB90950 Series 3.10 Exceptions The F2MC-16LX performs exception processing when the following events occur. ■ Execution of an Undefined Instruction Exception processing is fundamentally the same as interrupt processing. When an exception is detected between instructions, exception processing is performed separately from ordinary processing. In general, exception processing is performed as a result of an unexpected operation. Therefore, it is recommended to use exception processing only for debugging or for activating emergency recovery software. ■ Exception due to Execution of an Undefined Instruction The F2MC-16LX handles all codes that are not defined in the instruction map as undefined instructions. When an undefined instruction is executed, processing equivalent to the INT10 software interrupt instruction is performed. Specifically, the AL, AH, DPR, DTB, ADB, PCB, PC, and PS values are saved into the system stack first, then the I flag is set to "0", the S flag is set to "1", and processing branches to the routine indicated by the vector with the interrupt number 10. The PC value saved in the stack is the address at which the undefined instruction is stored. For an instruction code of 2 bytes or more, the saved value is the address at which the code identified as undefined is stored. Processing can be restored by the RETI instruction, but is of no use, however, because the same exception occurs again. CM44-10148-4E FUJITSU MICROELECTRONICS LIMITED 103 CHAPTER 3 INTERRUPTS 3.10 104 MB90950 Series FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 4 DELAY INTERRUPT GENERATION MODULE This chapter explains the functions and operations of the delay interrupt generation module. 4.1 Overview of Delay Interrupt Generation Module 4.2 Block Diagram of Delay Interrupt Generation Module 4.3 Configuration of Delay Interrupt Generation Module 4.4 Operating Explanation of Delay Interrupt Generation Module 4.5 Precautions when Using Delay Interrupt Generation Module 4.6 Program Example of Delay Interrupt Generation Module CM44-10148-4E FUJITSU MICROELECTRONICS LIMITED 105 CHAPTER 4 DELAY INTERRUPT GENERATION MODULE 4.1 4.1 MB90950 Series Overview of Delay Interrupt Generation Module The delay interrupt generation module generates the interrupt for task switching. Software can generate a hardware interrupt request. ■ Overview of Delay Interrupt Generation Module By using the delay interrupt generation module, a hardware interrupt request can be generated or released by the software. Table 4.1-1 shows the overview of delay interrupt generation module. Table 4.1-1 Overview of Delay Interrupt Generation Module Function and Control 106 Interrupt source An interrupt request is generated by setting the R0 bit in the delay interrupt request generation/ release register to "1" (DIRR: R0 = 1). An interrupt request is released by setting the R0 bit in the delay interrupt request generation/ release register to "0" (DIRR: R0 = 0). Interrupt number #42 (2AH) Interrupt control Register does not set to enable. Interrupt flag The interrupt flag is held in the R0 bit in the DIRR register. EI2OS/DMA It does not support the extended intelligent I/O service and DMA transfer. FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 4 DELAY INTERRUPT GENERATION MODULE 4.2 MB90950 Series 4.2 Block Diagram of Delay Interrupt Generation Module The delay interrupt generation module consists of the following blocks: • Interrupt request latch • Delay interrupt request generation/release register (DIRR) ■ Block Diagram of Delay Interrupt Generation Module Figure 4.2-1 Block Diagram of Delay Interrupt Generation Module Internal data bus − − − − − − − R0 Delay interrupt request generation/release register (DIRR) S R Interrupt request Latch Interrupt request signal − : Undefined ● Interrupt request latch This latch keeps the settings (delay interrupt request generation or release) of the delay interrupt request generation/release register (DIRR). ● Delay interrupt request generation/release register (DIRR) This register generates or releases a delay interrupt request. ■ Interrupt Number The interrupt number used in the delay interrupt generation module is as follows: Interrupt number #42 (2AH) CM44-10148-4E FUJITSU MICROELECTRONICS LIMITED 107 CHAPTER 4 DELAY INTERRUPT GENERATION MODULE 4.3 4.3 MB90950 Series Configuration of Delay Interrupt Generation Module This section lists registers for the delay interrupt generation module and its details. ■ List of Registers and Reset Values Figure 4.3-1 List of Registers for Delay Interrupt Generation Module and Its Reset Values Delay interrupt request generation/release register (DIRR) Address: 00009FH 108 bit 15 14 13 12 11 10 9 8 1 1 1 1 1 1 1 0 FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 4 DELAY INTERRUPT GENERATION MODULE 4.3 MB90950 Series 4.3.1 Delay Interrupt Request Generation/Release Register (DIRR) The delay interrupt request generation/release register (DIRR) generates or releases a delay interrupt request. ■ Delay Interrupt Request Generation/Release Register (DIRR) Figure 4.3-2 Delay Interrupt Request Generation/Release Register (DIRR) Address 15 14 13 12 11 10 9 8 Initial value 00009FH − − − − − − − R0 11111110B − − − − − − − R/W R/W − : Readable/Writable bit8 : Undefined R0 0 Releases the delay interrupt request : Initial value 1 Generates the delay interrupt request Delay interrupt request generation bit Table 4.3-1 Functions of Delay Interrupt Request Generation/Release Register (DIRR) Bit name CM44-10148-4E Function bit15 to bit9 Undefined bits Read : The value is undefined. Write : No effect bit8 R0: Delay interrupt request generation bit Generates or releases a delay interrupt request. When set to "0": Releases the delay interrupt request When set to "1": Generates a delayed interrupt request FUJITSU MICROELECTRONICS LIMITED 109 CHAPTER 4 DELAY INTERRUPT GENERATION MODULE 4.4 MB90950 Series Operating Explanation of Delay Interrupt Generation Module 4.4 The delay interrupt generation module has a function for generating or releasing an interrupt request by software. ■ Operating Explanation of Delay Interrupt Generation Module The setting shown in Figure 4.4-1 is required to use the delay interrupt generation module. Figure 4.4-1 Setting for Delay Interrupt Generation Module DIRR − bit15 14 13 12 11 10 9 bit8 − − − − − − − R0 : Undefined bits : Used bit When the R0 bit in the delay interrupt request generation/release register (DIRR) is set to "1" (DIRR: R0 = 1), an interrupt request is generated. There is no enable bit for an interrupt request. ● Operation of delay interrupt generation module • When the R0 bit in the delay interrupt request generation/release register (DIRR) is set to "1", the interrupt request latch is set to "1" and an interrupt request is generated to the interrupt controller. • An interrupt request is generated to the CPU when the interrupt controller prioritizes the interrupt request over other requests. • On the CPU side, the level of an interrupt request (ICR: IL) and the interrupt level mask bit (CCR: ILM) in the condition code register are compared, and if the interrupt request level is higher than the ILM, the delay interrupt is processed after the current instruction has completed. • Within the interrupt processing, the user program sets the R0 bit to "0" to release the interrupt request and switch the task. Figure 4.4-2 shows the operation of the delay interrupt generation module. Figure 4.4-2 Operation of Delay Interrupt Generation Module Delay interrupt generation module Other requests DIRR Interrupt controller ICR YY CPU IL CMP CMP ICR XX 110 ILM FUJITSU MICROELECTRONICS LIMITED Interrupt processing CM44-10148-4E MB90950 Series 4.5 CHAPTER 4 DELAY INTERRUPT GENERATION MODULE 4.5 Precautions when Using Delay Interrupt Generation Module When using the delay interrupt generation module, take the following precautions: ■ Precautions When Using Delay Interrupt Generation Module • Restart the interrupt processing when returned from interrupt processing without setting the R0 bit in the delay interrupt request generation/release register (DIRR) to "0" within an interrupt processing routine. • Unlike software interrupts, interrupts in the delay interrupt generation module are accompanied by delays. CM44-10148-4E FUJITSU MICROELECTRONICS LIMITED 111 CHAPTER 4 DELAY INTERRUPT GENERATION MODULE 4.6 4.6 MB90950 Series Program Example of Delay Interrupt Generation Module This section gives a program example of the delay interrupt generation module. ■ Program Example of Delay Interrupt Generation Module ● Processing specification The main program writes "1" to the R0 bit in the delay interrupt request generation/release register (DIRR) to generate a delay interrupt request and performs task switching. ● Coding example ICR15 DIRR ;Interrupt control register ;Delay interrupt source ;generation/release register DIRR_R0 EQU DIRR:0 ;Delay interrupt request generation ;bit ;---------Main program--------------------------------------------CODE CSEG START: ;Stack pointer (SP) and others ;should be initialized AND CCR,#0BFH ;Interrupt disabled MOV I:ICR15,#00H ;Interrupt level 0 (highest) MOV ILM,#07H ;Sets ILM in PS to level 7 OR CCR,#40H ;Interrupt enabled SETB I:DIRR_R0 ;Delay interrupt request generated LOOP MOV A,#00H ;Infinite loop MOV A,#01H BRA LOOP ;---------Interrupt program---------------------------------------WARI: CLRB I:DIRR_R0 ;Clears the interrupt request flag : ; User processing ; : RETI ;Returns from the interrupt CODE ENDS ;---------Vector setting------------------------------------------VECT CSEG ABS=0FFH ORG 0FF54H ;Sets a vector for the interrupt #42 ;(2AH) DSL WARI ORG 0FFDCH ;Reset vector setting DSL START DB 00H ;Sets to the single chip mode VECT ENDS END START 112 EQU EQU 0000BFH 00009FH FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 5 CLOCK This chapter explains the clock. 5.1 Clock 5.2 Block Diagram of the Clock Generation Block 5.3 Clock Selection Register (CKSCR) 5.4 PLL/Sub Clock Control Register (PSCCR) 5.5 Clock Mode 5.6 Oscillation Stabilization Wait Time 5.7 Connection of the Oscillator CM44-10148-4E FUJITSU MICROELECTRONICS LIMITED 113 CHAPTER 5 CLOCK 5.1 5.1 MB90950 Series Clock The clock generation block controls the internal clock that controls operation of the CPU and peripheral functions. The clock generated in the clock generation block is referred to as machine clock and its one cycle as machine cycle. In addition, the clock provided from a high-speed oscillator is referred to as oscillation clock and the divideby-two frequency of the oscillation clock is referred to as main clock. The divide-by-four or divide-by-eight frequency of the CR oscillation clock is referred to as sub clock, and a clock generated by the PLL oscillation as PLL clock. ■ Clock The clock generation block contains the oscillation circuit that generates the oscillation clock by connecting the oscillator to the oscillation pin. The clock generation block also contains the PLL clock multiplier circuit and it can generate 6 clocks of which frequencies are multiples of the oscillation clock frequency. The clock generation block controls the oscillation stabilization wait time and PLL clock multiplication and switching operation of the internal clock by the clock selector. ● Oscillation clock (HCLK) The oscillation clock is generated by connecting an oscillator to the high-speed oscillation pins (X0, X1) . ● Main clock (MCLK) The clock that has the divided-by-two frequency of the oscillation clock supplies the input clock to the time-base timer and the clock selector. ● Sub clock (SCLK) The clock that has the divided-by-four or divided-by-eight frequency of the CR oscillation clock. The division ratio of the sub clock is set with SCDS bit in the PPL/sub clock control register (PSCCR). This clock can be used as the operating clock in the watch timer or the low-speed machine clock. ● PLL clock (PCLK) The PLL clock is obtained by multiplying the oscillation clock with the PLL clock multiplier circuit (PLL oscillation circuit). You can select among 6 types of clocks, depending on the setting of the multiplication rate select bits (CKSCR: CS1, CS0, PSCCR: CS2). 114 FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 5 CLOCK 5.1 MB90950 Series ● Machine clock This is the operation clock for the CPU and peripheral functions. One cycle of the machine clock is defined as a machine cycle (1/φ). A machine clock can be selected among any of the main clock, sub clock or 6 types of PLL clocks. Note: When the operating voltage is 5 V, an oscillation clock of 3 MHz to 16 MHz can be generated. As the maximum operating frequency of CPU and peripheral functions is 32 MHz, setting the multiplication rate that results in exceeding the maximum operating frequency prevents the device from normal operation. Although the PLL oscillation can generate from 4 MHz to 32 MHz, the oscillation range of PLL depends on the operating voltage and multiplication rate. Refer to "Data sheet" for details. CM44-10148-4E FUJITSU MICROELECTRONICS LIMITED 115 CHAPTER 5 CLOCK 5.1 MB90950 Series ■ Clock Supply Map Machine clock generated in the clock generation block is supplied as the operating clock for the CPU and peripheral functions. The operation of the CPU and the peripheral functions are affected by switching between main clock and sub clock, switching the PLL clock (clock mode) and by a change in the PLL clock multiplication rate. Since some peripheral functions receive divided output from the time-base timer, a peripheral unit can select the clock best suited for this operation. Figure 5.1-1 shows the clock supply map. Figure 5.1-1 Clock Supply Map Peripheral function 4 Watch timer 4 Watchdog timer Time-base timer 1 Clock generation block 2 3 X0 Pin X1 Pin Clock selector Clock selector Divide-by four/two φc SCLK (Sub clock) Clock generation circuit Pin PPG0 to PPGF 16-bit reload timer 0 to 3 Pin TIN0 to TIN3 4 6 8 PLL multiplier circuit PCLK (PLL clock) Divide-by-two 8/16-bit PPG timer 0 to F Clock selector Divide-by-two Clock selector HCLK MCLK φ (Oscillation clock) (Main clock) (Machine clock) CAN0, CAN1 Pin RX0, RX1 Pin TX0, TX1 A/D converter (24ch) Pin AN0 to AN23 UART0 to 6+ serial I/O Pin SCK0 to SCK6 Pin SIN0 to SIN6 Pin SOT0 to SOT6 I/O timer Internal oscillation clock μDMA Clock monitor function Output compare 0 to 7 CPU Pin OUT0 to OUT7 Free-run timer 0 and 1 Input capture 0 to 7 I2CO, 1 HCLK : Oscillation clock MCLK : Main clock PCLK : PLL clock SCLK : Sub clock φ : Machine clock φC : CAN0, CAN1 clock 116 Pin TOT0 to TOT3 Clock monitor 4 Pin IN0 to IN7 Pin SDA0, SDA1 Pin SCL0, SCL1 Pin CKOT Oscillation stabilization wait control FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 5 CLOCK 5.2 MB90950 Series 5.2 Block Diagram of the Clock Generation Block The clock generation block consists of the following blocks: • Oscillation clock generation circuit/sub clock generation circuit • PLL multiplier circuit • Clock selector • Clock selection register (CKSCR) • PLL/sub clock control register (PSCCR) • Oscillation stabilization wait time selector ■ Block Diagram of the Clock Generation Block Figure 5.2-1 shows a block diagram of the clock generation block, including the standby control circuit and the time-base timer circuit. Figure 5.2-1 Block Diagram of the Clock Generation Block Low-power consumption mode control register (LPMCR) STP SLP SPL RST TMD CG1 CG0 Reserved RST Pin CPU intermittent operation cycle selector Pin high impedance control circuit Pin Hi-Z control Internal reset generation circuit Internal reset Intermittent cycle select CPU clock control circuit Reset (release) Watch, sleep and stop signals Standby control circuit 2 CPU operating clock Watch and stop signals Peripheral Peripheral functions clock control operating clock circuit Interrupt (release) Sub clock oscillation stabilization wait release Main clock oscillation stabilization wait release Clock generation block Operating clock selector Machine clock 2 CS2 PLL/Sub clock control register (PSCCR):bit8 Oscillation stabilization wait time selector 2 PLL multiplier circuit SCM MCM WS1 WS0 SCS MCS CS1 CS0 Clock selection register (CKSCR) Clock Selector X0 Pin Divideby-two Oscillation clock (HCLK) X1 Pin Oscillation clock oscillation circuit Clock Selector Sub clock (SCLK) Divide-byfour/divideby-two Divide- Divide- by-four Main by-512 clock Time-base timer Divideby-1024 Divideby-two Divideby-two Divideby-two Divideby-two Divideby-two Divideby-four To watchdog timer Divideby-eight Divideby-two Divideby-two Watch timer SCDS Internal CR oscillation clock Divideby-two PLL/sub clock control register (PSCCR):bit10 Clock monitor function CM44-10148-4E FUJITSU MICROELECTRONICS LIMITED 117 CHAPTER 5 CLOCK 5.2 MB90950 Series ● Oscillation clock generation circuit The oscillation clock (HCLK) is generated by connecting the oscillator to the high-speed oscillation pins. ● PLL multiplier circuit The PLL multiplier circuit multiplies the oscillation clock with the PLL oscillation and supplies the clock as a PLL clock (PCLK) to the clock selector. ● Clock selector It selects the clock to supply to the CPU and peripheral functions among the main clock, sub clock and 6 types of PLL clocks. ● Clock selection register (CKSCR) The clock selection register switches the oscillation clock/PLL clock and main clock/sub clock, and selects an oscillation stabilization wait time and a PLL clock multiplication rate. ● PLL/sub clock control register (PSCCR) This register selects the PLL clock multiplication rate (selects by the setting of CS0 and CS1 bits in the clock selection register, and setting of CS2 bit in this register) and sets the sub clock division ratio (divideby-two/divide-by-four). ● Oscillation stabilization wait time selector This selector selects an oscillation stabilization wait time of the oscillation clock. Selection is made from among 4 types of time-base timer outputs. 118 FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 5 CLOCK 5.2 MB90950 Series 5.2.1 Register in the Clock Generation Block This section explains the register in the clock generation block. ■ List of the Register in the Clock Generation Block and Its Initial Value Figure 5.2-2 List of Clock Selection Register and Its Initial Value bit Clock selection register (CKSCR) bit PLL/sub clock control register (PSCCR) CM44-10148-4E 15 14 13 12 11 10 9 8 1 1 1 1 1 1 0 0 15 14 13 12 11 10 9 8 1 1 1 1 0 0 0 0 FUJITSU MICROELECTRONICS LIMITED 119 CHAPTER 5 CLOCK 5.3 5.3 MB90950 Series Clock Selection Register (CKSCR) The clock selection register (CKSCR) switches the PLL clock, main clock and sub clock, and selects an oscillation stabilization wait time and the PLL clock multiplication rate. ■ Clock Selection Register (CKSCR) Figure 5.3-1 Clock Selection Register (CKSCR) Address bit15 bit14 bit13 bit12 bit11 bit10 bit9 0000A1H SCM MCM WS1 WS0 SCS MCS CS1 CS0 11111100B R R bit8 Initial value R/W R/W R/W R/W R/W R/W CS2 (PSCCR register: bit8) bit9 bit8 CS0 Multiplication rate selection bits The results when the oscillation clock (HCLK) frequency is 4 MHz is shown in parentheses CS2 CS1 0 0 0 1 × HCLK (4 MHz) 0 0 1 2 × HCLK (8 MHz) 0 1 0 3 × HCLK (12 MHz) 0 1 1 4 × HCLK (16 MHz) 1 1 0 6 × HCLK (24 MHz) 1 1 1 8 × HCLK (32 MHz) bit10 MCS PLL clock selection bit 0 Selects PLL clock 1 Selects main clock bit11 SCS Sub clock selection bit 0 Selects sub clock 1 Selects main clock bit13 bit12 Oscillation stabilization wait time selection bits WS1 WS0 The results when the oscillation clock (HCLK) frequency is 4 MHz is shown in parentheses 0 0 210/HCLK (approx. 256 μs) 0 1 213/HCLK (approx. 2.05 ms) 1 0 217/HCLK (approx. 32.77 ms) 1 1 216/HCLK (approx. 16.38 ms; except power-on reset) 212/HCLK + 216/HCLK (approx. 17.4 ms; power-on reset only) bit14 MCM HCLK R/W R 120 : Oscillation clock : Readable/Writable PLL clock operation flag bit 0 Operating with PLL clock 1 Operating with main clock or sub clock bit15 SCM Sub clock operating flag bit : Read only 0 Operating with sub clock : Initial value 1 Operating with PLL clock or main clock FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 5 CLOCK 5.3 MB90950 Series Table 5.3-1 Functions of Clock Selection Register (CKSCR) (1 / 2) Bit name Function Indicates whether the main clock or sub clock has been selected as the machine clock. • When the sub clock operating flag bit (CKSCR: SCM) is "0" and the sub clock selection bit (CKSCR: SCS) is "1", it indicates that it is in the transition period from the sub clock to the main clock. On the other hand, when SCM is "1" and SCS is "0", it indicates that it is in the transition period from the main clock to the sub clock. • Writing to this bit has no effect on operation. bit15 SCM: Sub clock operation flag bit bit14 Indicates whether the main clock or PLL clock has been selected as the machine clock. MCM: • When the PLL clock operating flag bit (CKSCR: MCM) is "1" and the PLL clock selection bit PLL clock operating flag (CKSCR: MCS) is "0", it indicates that it is during the PLL clock oscillation stabilization wait bit time. • Writing to this bit has no effect on operation. Selects the oscillation stabilization wait time of the oscillation clock when releasing the stop mode, transiting from sub clock to main clock mode, and transiting from sub clock to PLL clock mode. • Selects from among 4 types of time-base timer outputs. Returns to the initial value by resetting all. Note: An appropriate value must be set for the oscillation stabilization wait time according to the oscillator. Refer to Section "6.2 Reset Source and Oscillation Stabilization Wait Times" for details. The oscillation stabilization wait time is fixed to 214/HCLK when switching from the main clock to the PLL clock mode (when the oscillation clock frequency is 4 MHz: approx. 4.1 ms). The oscillation stabilization wait time depends on the value set in the bits when switching from the sub clock to the PLL clock mode or returning from PLL stop to PLL clock mode. Since the PLL clock oscillation stabilization wait time requires 214/HCLK or more, when switching from sub clock to PLL clock mode or transiting to PLL stop mode, set "10B" or "11B" for these bits. bit13, bit12 WS1, WS0: Oscillation stabilization wait time selection bits bit11 Specifies whether the main clock or sub clock to be selected as the machine clock. • When switching from the main clock to sub clock (CKSCR: SCS=1→ 0), it is switched to 1/ SCLK (when the oscillation clock frequency is 100 kHz and divide-by-eight setting: approx. 80 μs) sub clock mode, synchronizing with the sub clock. • When switching from the sub clock to main clock (CKSCR: SCS=0→ 1), it is switched to the main clock mode after the main clock oscillation stabilization wait time is generated. The timebase timer will be cleared automatically. Returns to the initial value by resetting all. Notes: SCS: 1) When both MCS and SCS bits are "0", SCS is preferred, and the sub clock is selected. 2) When both sub clock selection bit (CKSCR: SCS) and PLL clock selection bit (CKSCR: Sub clock selection bit MCS) are "0", the sub clock is preferred. 3) Write after switching from the main clock to sub clock (CKSCR: SCS=1→ 0), disables the time-base timer interrupt through the interrupt enable bit (TBTC: TBIE) in the time-base timer or the interrupt level mask registers (ILM: ILM2 to ILM0). 4) When turning on the power or releasing form the stop mode, a sub clock oscillation stabilization wait time 214/SCLK (when the oscillation clock frequency is 100 kHz and divide-by-eight setting: approx. 1.3 s) is generated. Therefore, if switching from the main clock to the sub clock mode during that period, an oscillation stabilization wait time will be generated. CM44-10148-4E FUJITSU MICROELECTRONICS LIMITED 121 CHAPTER 5 CLOCK 5.3 MB90950 Series Table 5.3-1 Functions of Clock Selection Register (CKSCR) (2 / 2) Bit name bit10 MCS: PLL clock selection bit Function Specifies whether the main clock or PLL clock to be selected as the machine clock. When switched from the main clock to the PLL clock (CKSCR: MCS=1→0), the PLL clock oscillation stabilization wait time is generated, and then the transition to the PLL clock mode is made. The time-base timer is cleared automatically. The oscillation stabilization wait time is fixed to 214/HCLK (when the oscillation clock frequency is 4 MHz: approx. 4.1ms) when switching from the main clock to the PLL clock mode. The oscillation stabilization wait time when switching from the sub clock to the PLL clock mode depends on the value set in the oscillation stabilization wait time selection bits (CKSCR: WS1, WS0). Returns to the initial value by resetting all. Notes: 1) When both MCS and SCS bits are "0", SCS is preferred, and the sub clock is selected. 2) Write after switching from the main clock to PLL clock (CKSCR: MCS=1→0), disables the time-base timer interrupt through the interrupt enable bit (TBTC: TBIE) in the time-base timer or the interrupt level mask registers (ILM: ILM2 to ILM0). • • • bit9, bit8 CS1, CS0: Multiplication rate selection bits These bits and CS2 bit in the PLL/sub clock control register (PSCCR) select a multiplication rate for the PLL clock. Select from among 6 types of multiplication rates for the PLL clock. Returns to the initial value by resetting all. Settings for CS0, CS1 and CS2: CS2 CS1 CS0 PLL clock multiplication rate 0 0 0 x1 0 0 1 x2 0 1 0 x3 0 1 1 x4 1 1 0 x6 1 1 1 x8 Note: When the PLL clock is selected (CKSCR: MCS=0), writing is controlled. When rewriting the multiplication rate, first write "1" into the PLL clock selection bit (CKSCR: MCS) temporarily, then rewrite the multiplication rate selection bits (CKSCR: CS1, CS0) and return the PLL clock selection bit (CKSCR: MCS) to "0". 122 FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 5 CLOCK 5.4 MB90950 Series 5.4 PLL/Sub Clock Control Register (PSCCR) PLL/sub clock control register selects the PLL multiplication rate and the sub clock division ratio. This register is write only. The value read from this bit is always "1". ■ PLL/Sub Clock Control Register (PSCCR) Figure 5.4-1 shows the configuration of the PLL/sub clock control register (PSCCR). Table 5.4-1 describes the function of each bit in the PLL/sub clock control register (PSCCR). Figure 5.4-1 Configuration of PLL/Sub Clock Control Register (PSCCR) Address bit 0000CFH 15 14 13 12 11 10 9 8 Initial value SCDS Reserved CS2 11110000B W W W − − − − Reserved − − − − W bit8 CS2 0 1 Multiplication rate selection bits See the clock selection registers (CKSCR) bit9 Reserved bit Reserved 0 Always write "0" to this bit The value read from this bit is always "1" bit10 W − : Write only SCDS : Undefined 0 Divide-by-eight 1 Divide-by-four : Initial value Sub clock division selection bit bit11 Reserved bit Reserved 0 CM44-10148-4E Always write "0" to this bit The value read from this bit is always "1" FUJITSU MICROELECTRONICS LIMITED 123 CHAPTER 5 CLOCK 5.4 MB90950 Series Table 5.4-1 Function of Each Bit in PLL/Sub Clock Control Register (PSCCR) Bit name Function bit15 to bit12 Undefined bits These bits are not used. • Writing to these bits has no effect. • The value read from this bit is always "1". bit11 Reserved bit • • bit10 SCDS: Sub clock division selection bit Selects a division ratio for the sub clock. • When you write "0", divide-by-eight is selected. • When you write "1", divide-by-four is selected. • The value read from this bit is always "1". Initialized to "0" by all reset sources. Note: Do not rewrite this bit when in the sub clock operation. bit9 Reserved bit • • Always write "0" to this bit. The value read from this bit is always "1". • This bit determines the multiplication rate for PLL, together with CS1 and CS0 bits in the clock selection register (CKSCR). bit8 CS2: Multiplication rate selection bit Always write "0" to this bit. The value read from this bit is always "1". CS2 CS1 CS0 PLL clock multiplication rate 0 0 0 x1 0 0 1 x2 0 1 0 x3 0 1 1 x4 1 1 0 x6 1 1 1 x8 • The value read from this bit is always "1". • Initialized to "0" by all reset sources. Note: When the MCS or MCM bit is "0", changing the setting of this bit is not allowed. Change this bit when in the main clock mode. Note: 124 The PSCCR register is a write-only register, so the read value is different from the write value. Therefore, do not use RMW instructions, such as SETB/CLRB. FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 5 CLOCK 5.5 MB90950 Series 5.5 Clock Mode There are 3 clock modes: main clock, sub clock, and PLL clock modes. ■ Clock Mode ● Main clock mode The main clock mode uses the divided-by-two oscillation clock, generated by connecting an oscillator to the high-speed oscillation pins (X0, X1), as the operating clock for the CPU and peripheral functions. ● Sub clock mode The sub clock mode uses the divided-by-eight or divided-by-four CR oscillation clock as the operating clock for the CPU and peripheral functions. The division ratio for the sub clock can be set with SCDS bit in the PLL/sub clock control register (PSCCR). ● PLL clock mode The PLL clock mode uses the oscillation clock, multiplied by the PLL clock multiplier circuit (PLL oscillation circuit), as operating clock for the CPU and peripheral functions. The multiplication rate for PLL clock can be set with the clock selection register (CKSCR: CS1, CS0) and PLL/sub clock control register (PSCCR: CS2). ■ Transition of the Clock Mode Clock mode can make the transition to the main clock, sub clock, and PLL clock modes by setting the PLL clock selection bit (CKSCR: MCS) and the sub clock selection bit (CKSCR: SCS). ● Transition from main clock mode to PLL clock mode When rewriting the PLL clock selection bit (CKSCR: MCS) from "1" to "0", main clock is switched to PLL clock after the PLL oscillation stabilization wait time (214/HCLK) has elapsed. ● Transition from PLL clock mode to main clock mode When rewriting the PLL clock selection bit (CKSCR: MCS) from "0" to "1", PLL clock is switched to main clock at the timing (after 1 to 16 PLL clocks) the PLL and main clock edges match. ● Transition from main clock mode to sub clock mode When rewriting the sub clock selection bit (CKSCR: SCS) from "1" to "0", main clock is switched to sub clock when the sub clock edge is detected. CM44-10148-4E FUJITSU MICROELECTRONICS LIMITED 125 CHAPTER 5 CLOCK 5.5 MB90950 Series ● Transition from sub clock mode to main clock mode When rewriting the sub clock selection bit (CKSCR: SCS) from "0" to "1", sub clock is switched to main clock after the main clock oscillation stabilization wait time has elapsed. ● Transition from PLL clock mode to sub clock mode When rewriting the sub clock selection bit (CKSCR: SCS) from "1" to "0", PLL clock is switched to sub clock. ● Transition from sub clock mode to PLL clock mode When rewriting the sub clock selection bit (CKSCR: SCS) from "0" to "1", sub clock is switched to PLL clock after the main clock oscillation stabilization wait time has elapsed. ■ Selection of PLL Clock Multiplication Rate One of 6 types of PLL clock multiplication rates (1 to 4, 6 and 8 multiplications) can be selected by writing "000B" to "111B" in the multiplication rate selection bits (CKSCR: CS1, CS0, PSCCR: CS2). ■ Machine Clock The PLL clock, main clock or sub clock output from the PLL multiplication circuit will be the machine clock. This machine clock is supplied to the CPU and peripheral functions. One of main clock, PLL clock, and sub clock can be selected by writing to the sub clock selection bit (CKSCR: SCS) and the PLL clock selection bit (CKSCR: MCS). Notes: • When you rewrite the PLL clock selection bit (CKSCR: MCS) and sub clock selection bit (CKSCR: SCS), the machine clock is not switched immediately. If you want to operate a machine clockdependent peripheral function, refer to the values on the PLL clock operating flag bit (CKSCR: MCM) or on the sub clock operating flag bit (CKSCR: SCM) and make sure that the machine clock has been switched before the operation. • When the PLL clock selection bit (CKSCR: MCS) is "0" (PLL clock mode) and the sub clock selection bit (CKSCR: SCS) is "0" (sub clock mode), SCS bit is preferred, and the sub clock mode begins. • When switching the clock mode, do not switch to other clock mode or the low-power consumption mode until the switch is completed. You can refer to MCM and SCM bits in the clock selection register (CKSCR) for the completion of switching. If the switch is not completed, switching to other clock mode or the low-power consumption mode may not take effect. 126 FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 5 CLOCK 5.5 MB90950 Series Figure 5.5-1 shows the state transition diagram by machine clock switching. Figure 5.5-1 State Transition Diagram by Machine Clock Selection Main MCS = 1 MCM = 1 SCS = 1 SCM = 1 CS1, CS0 = XXB CS2 = X (10) (12) (1) (11) (20) (13) (8) (2) Main → PLLx (3) MCS = 0 (4) MCM = 1 (5) SCS = 1 SCM = 1 (6) CS1, CS0 = XXB (7) CS2 = X CM44-10148-4E Main → Sub MCS = 1 MCM = 1 SCKS = 1 SCS = 0 SCM = 1 CS1, CS0 = XXB CS2 = X Sub → Main MCS = 1 MCM = 1 SCKS = 1 SCS = 1 SCM = 0 CS1, CS0 = XXB CS2 = X PLL1 → Main (9) MCS = 1 MCM = 0 SCS = 1 SCM = 1 CS1, CS0 = 00B CS2 = 0 PLL1 : Multiplied MCS = 0 MCM = 0 SCS = 1 SCM = 1 (8) CS1, CS0 = 00 B CS2 = 0 PLL2 → Main (9) MCS = 1 MCM = 0 SCS = 1 SCM = 1 CS1, CS0 = 01B CS2 = 0 PLL2 : Multiplied MCS = 0 MCM = 0 SCS = 1 (8) SCM = 1 CS1, CS0 = 01B CS2 = 0 PLL3 → Main (9) MCS = 1 MCM = 0 SCS = 1 SCM = 1 CS1, CS0 = 10B CS2 = 0 PLL3 : Multiplied MCS = 0 MCM = 0 SCS = 1 SCM = 1 (8) CS1, CS0 = 10B CS2 = 0 PLL4 → Main (9) MCS = 1 MCM = 0 SCS = 1 SCM = 1 CS1, CS0 = 11B CS2 = 0 PLL4 : Multiplied MCS = 0 MCM = 0 SCS = 1 SCM = 1 (8) CS1, CS0 = 11 B CS2 = 0 PLL6 → Main (9) MCS = 1 MCM = 0 SCS = 1 SCM = 1 CS1, CS0 = 10B CS2 = 1 PLL6 : Multiplied MCS = 0 MCM = 0 SCS = 1 SCM = 1 (8) CS1, CS0 = 10B CS2 = 1 PLL8 → Main MCS = 1 (9) MCM = 0 SCS = 1 SCM = 1 CS1, CS0 = 11B CS2 = 1 PLL8 : Multiplied MCS = 0 (8) MCM = 0 SCS = 1 SCM = 1 CS1, CS0 = 11B CS2 = 1 (12) (11) (14) (15) (16) (17) (18) (19) (10) (10) (10) (10) (10) (10) Sub MCS = X MCM = 1 SCKS = 1 SCS = 0 SCM = 0 CS1, CS0 = XXB CS2 = X (10) Sub → PLL MCS = 0 MCM = 1 SCKS = 1 SCS = 1 SCM = 0 CS1, CS0 = XXB CS2 = 0 PLL1 → Sub MCS = 1 MCM = 0 SCKS = 1 SCS = 0 SCM = 1 CS1, CS = 00B CS2 = 0 (21) PLL2 → Sub (21) MCS = 1 MCM = 0 SCKS = 1 SCS = 0 SCM = 1 CS1, CS0 = 01B CS2 = 0 PLL3 → Sub (21) MCS = 1 MCM = 0 SCKS = 1 SCS = 0 SCM = 1 CS1, CS0 = 10B CS2 = 0 PLL4 → Sub (21) MCS = 1 MCM = 0 SCKS = 1 SCS = 0 SCM = 1 CS1, CS0 = 11B CS2 = 0 PLL6 → Sub (21) MCS = 1 MCM = 0 SCKS = 1 SCS = 0 SCM = 1 CS1, CS0 = 10B CS2 = 1 (21) PLL8 → Sub MCS = 1 MCM = 0 SCKS = 1 SCS = 0 SCM = 1 CS1, CS0 = 11B CS2 = 1 FUJITSU MICROELECTRONICS LIMITED 127 CHAPTER 5 CLOCK 5.5 MB90950 Series (1) Write "0" to MCS bit (2) End of PLL clock oscillation stabilization wait time &CS1, CS0 = 00B & CS2 = 0 (3) End of PLL clock oscillation stabilization wait time &CS1, CS0 = 01B & CS2 = 0 (4) End of PLL clock oscillation stabilization wait time &CS1, CS0 = 10B & CS2 = 0 (5) End of PLL clock oscillation stabilization wait time &CS1, CS0 = 11B & CS2 = 0 (6) End of PLL clock oscillation stabilization wait time &CS1, CS0 = 10B & CS2 = 1 (7) End of PLL clock oscillation stabilization wait time &CS1, CS0 = 11B & CS2 = 1 (8) Write "1" to MCS bit (including the resets) (9) Synchronous timing of PLL clock and main clock (10) Write "0" to SCS bit (11) Synchronous timing of main clock and sub clock (12) Write "1" to SCS bit (MCS=1) (13) End of main clock oscillation stabilization wait time (14) End of main clock oscillation stabilization wait time & CS1, CS0 = 00B & CS2 = 0 (15) End of main clock oscillation stabilization wait time & CS1, CS0 = 01B & CS2 = 0 (16) End of main clock oscillation stabilization wait time & CS1, CS0 = 10B & CS2 = 0 (17) End of main clock oscillation stabilization wait time & CS1, CS0 = 11B & CS2 = 0 (18) End of main clock oscillation stabilization wait time & CS1, CS0 = 10B & CS2 = 1 (19) End of main clock oscillation stabilization wait time & CS1, CS0 = 11B & CS2 = 1 (20) Write "1" to SCS bit (MCS=0) (21) Synchronous timing of PLL clock and sub clock MCS : PLL clock selection bit in the clock selection register (CKSCR) MCM : PLL clock operation flag bit in the clock selection register (CKSCR) SCS : Sub clock selection bit in the clock selection register (CKSCR) SCM : Sub clock operation flag bit in the clock selection register (CKSCR) CS1, CS0 : Multiplication rate selection bit in the clock selection register (CKSCR) CS2 : Multiplication rate selection bit in the PLL/sub clock control register (PSCCR) SCKS : Sub clock selection bit in the clock supervisor control register (CSVCR) Notes: • Initial value of the machine clock is the main clock (CKSCR: MCS=1, SCS=1). • When both MCS and SCS bits are "0", SCS is preferred, and the sub clock is selected. • When switching from the sub clock to PLL clock mode, set CKSCR: WS1, WS0 to "10B" or "11B". 128 FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 5 CLOCK 5.6 MB90950 Series 5.6 Oscillation Stabilization Wait Time When the power is turned on where the oscillation clock is suspended or when stop mode is released, the oscillation clock requires some time to stabilize (oscillation stabilization wait time) after oscillation begins. When switching the clock mode, such as from the main to PLL, main to sub, sub to main, or sub to PLL, an oscillation stabilization wait time is also required. ■ Operation During Oscillation Stabilization Wait Time Generally, ceramic or crystal oscillator requires time of several to several dozen of milliseconds until the oscillation is stabilized at the natural frequency (oscillation frequency) after starting the oscillation. Accordingly, CPU operation should be disabled immediately after the oscillation starts and the machine clock supply to the CPU is not enabled until the oscillation stabilization wait time has elapsed and the oscillation becomes stable. Since the oscillation stabilization wait time depends on the type of oscillator (such as crystal, ceramic), the proper oscillation stabilization wait time must be selected for the oscillator to be used. The oscillation stabilization wait time can be set with the clock selection register (CKSCR). When switching the clock mode from the main clock to PLL clock, main clock to sub clock, sub clock to main clock, or sub clock to PLL clock, the CPU continues to operate on the original clock during the oscillation stabilization wait time. After the wait time has elapsed, the operating clock switches to the desire clock. Figure 5.6-1 shows the operation right after the oscillation starts. Figure 5.6-1 Operation Immediately after the Oscillation Stabilization Wait Time Oscillation time of oscillator Oscillation stabilization wait time Starting normal operation or switching to PLL clock/sub clock X1 Oscillation starts CM44-10148-4E Oscillation stabilized FUJITSU MICROELECTRONICS LIMITED 129 CHAPTER 5 CLOCK 5.7 5.7 MB90950 Series Connection of the Oscillator The MB90950 series contains a system clock generation circuit. Connecting the oscillator to the oscillation pin generates an internal clock. ■ Connection of the Oscillator ● Example of connection of crystal oscillator or ceramic resonator Figure 5.7-1 Example of Connection of Crystal Oscillator or Ceramic Resonator X0 MB90950 series X1 C1 130 C2 FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 6 RESET This chapter explains the reset. 6.1 Overview of Reset 6.2 Reset Source and Oscillation Stabilization Wait Times 6.3 External Reset Pin 6.4 Reset Operation 6.5 Reset Source Bits 6.6 Status of Pins by Reset CM44-10148-4E FUJITSU MICROELECTRONICS LIMITED 131 CHAPTER 6 RESET 6.1 6.1 MB90950 Series Overview of Reset When a reset source is generated, the CPU immediately stops the current execution process and assumes the reset release wait state. Once the reset is released, the CPU then begins processing with the address indicated by the reset vector. The reset has the following 7 sources: • Power-on reset • External reset request via the RST pin • Software reset request • Watchdog timer overflow • Low-voltage detection reset request • CPU operation detection reset request • Clock supervisor reset request ■ Reset Source Table 6.1-1 lists the sources of a reset. Table 6.1-1 Reset Sources Reset Source Machine clock Watchdog timer Oscillation stabilization wait Power-on When the power is turned on Main clock (MCLK) Stop Yes External pin "L" level input to the RST pin Main clock (MCLK) Stop No "0" is written to the internal reset signal generation bit (RST) in the low-power consumption mode control register (LPMCR). Main clock (MCLK) Stop No Watchdog timer overflow Main clock (MCLK) Stop No Low-voltage detection reset When low voltage * is detected Main clock (MCLK) Stop No CPU operation detection reset When CPU operation detection counter overflows Main clock (MCLK) Stop No Clock supervisor reset When some trouble of main clock is detected Internal CR oscillation clock Stop No Software Watchdog timer MCLK: Main clock (divide-by-two clock of the oscillation clock) *: For details, see "CHAPTER 26 LOW-VOLTAGE/CPU OPERATION DETECTION RESET CIRCUIT". 132 FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 6 RESET 6.1 MB90950 Series ● Power-on reset A power-on reset is generated when the power is turned-on. The oscillation stabilization wait time is fixed to 212 + 216 oscillation clock cycles (212/HCLK + 216/HCLK) (about 17.4 ms: at 4 MHz oscillation). When the oscillation stabilization wait time has elapsed, the reset is executed. ● External reset An external reset is generated by inputting the "L" level to an external reset pin (RST pin). The "L" level input time to the RST pin should be 500 ns or longer. The oscillation stabilization wait time is not required for the external resets. Notes: • Only for the reset requests via the RST pin, if the reset source is generated during a write operation, the CPU assumes the reset release wait state after completion of the instruction. Therefore, even though a reset is input while writing, the writing process will be completed successfully. However, beware of the following: • For the string instructions, a reset is accepted before a specified number of counter are transferred, so that all data will never be transferred completely. • A reset is forcibly accepted without waiting for the completion of the instruction, if the cycle is extended to a certain level by the RDY input during access to the external bus. A reset is forcibly accepted with 16 machine cycles. • When returning from the stop mode, sub clock mode, sub clock sleep mode, and watch mode to the main clock mode via the external reset pin (RST pin), input "L" level for at least oscillation time of the oscillator* + 100 μs. *: Oscillation time of the oscillator is the time when the amplitude reaches to 90%. Several to several dozen ms for the crystal oscillator, several hundred μs to several ms for the ceramic resonator. • When returning from the time-base timer mode to the main clock mode via the external reset pin (RST pin), input "L" level for at least 100 μs. ● Software reset A software reset is an internal reset generated by writing "0" to the RST bit of the low-power consumption mode control register (LPMCR). The oscillation stabilization wait time is not required for the software reset. ● Watchdog reset A watchdog reset is generated by a watchdog timer overflow that occurs when "0" is not written to the watchdog control bit (WTE) in the watchdog timer control register (WDTC) within a given time after the watchdog timer is activated. This reset does not take the oscillation stabilization wait time. ● Low-voltage detection reset The low-voltage detection reset is generated when the low voltage * is detected. The oscillation stabilization wait time is not required for the low-voltage detection reset. *: For details, see "CHAPTER 26 LOW-VOLTAGE/CPU OPERATION DETECTION RESET CIRCUIT". CM44-10148-4E FUJITSU MICROELECTRONICS LIMITED 133 CHAPTER 6 RESET 6.1 MB90950 Series ● CPU operation detection reset CPU operation detection reset is a counter that counts the source clock. If the CL bit of the low-voltage/ CPU operation detection reset control register (LVRC) is not cleared within a specified time after activation, the reset is generated. The oscillation stabilization wait time is not required for the CPU operation detection reset. ● Clock supervisor reset Generates a reset when a main clock failure is detected. Clock supervisor reset does not wait for the oscillation stabilization wait time to elapse. Definition of clocks HCLK: Oscillation clock frequency MCLK: Main clock frequency SCLK: Sub clock frequency φ: Machine clock (CPU operating clock) frequency 1/ φ: Machine cycle (CPU operating clock period) See Section "5.1 Clock", for details. Note: When a reset is generated in stop or sub clock mode, 216/HCLK oscillation stabilization wait time is required (approximately 16.28 ms, using HCLK=4 MHz oscillation). Refer to Section "5.6 Oscillation Stabilization Wait Time" for details. 134 FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 6 RESET 6.2 MB90950 Series 6.2 Reset Source and Oscillation Stabilization Wait Times The MB90950 series has 7 types of reset sources. The oscillation stabilization wait time when resetting varies, depending on the reset source. ■ Reset Source and Oscillation Stabilization Wait Times Table 6.2-1 lists the reset sources and oscillation stabilization wait times. Table 6.2-1 Reset Sources and Oscillation Stabilization Wait Times Reset Oscillation stabilization wait time The oscillation clock frequency at 4 MHz is given in parentheses. Reset source Power-on When the power is turned on 212/HCLK + 216/HCLK (approx. 17.4 ms) Watchdog Watchdog timer overflow None Note: WS1 and WS0 bits are initialized to "11B", however. External "L" input from the RST pin None Note: WS1 and WS0 bits are initialized to "11B", however. Software Writing "0" to the RST bit in the low-power consumption mode control register (LPMCR). None Note: WS1 and WS0 bits are initialized to "11B", however. When low voltage is detected None Note: WS1 and WS0 bits are initialized to "11B", however. Low-voltage detection CPU operation detection When CPU overflows Clock supervisor reset operation detection counter When some trouble of main clock is detected None Note: WS1 and WS0 bits are initialized to "11B", however. None Note: WS1 and WS0 bits are initialized to "11B", however. HCLK : Oscillation clock frequency WS1, WS0 : Oscillation stabilization wait time selection bits in the clock select register (CKSCR) Figure 6.2-1 shows the oscillation stabilization wait times at a power-on reset. Figure 6.2-1 Oscillation Stabilization Wait Times at a Power-on Reset VCC 212/HCLK 216/HCLK CLK CPU Operation Voltage step-down Oscillation circuit stabilization stabilization wait time wait time CM44-10148-4E FUJITSU MICROELECTRONICS LIMITED 135 CHAPTER 6 RESET 6.2 MB90950 Series Note: Ceramic and crystal oscillators generally require several to several dozen ms of oscillation stabilization wait time, until the oscillation is stabilized at a specific frequency from the start of the oscillation. A proper oscillation stabilization wait time must be set for the particular oscillator to be used. See Section "5.6 Oscillation Stabilization Wait Time", for details. ■ Oscillation Stabilization Wait Reset State The reset operations in response to a reset at power-on, or during the stop mode and sub clock mode are performed after the oscillation stabilization wait time, created by the time-base timer, has elapsed. If the external reset input has not been released after the wait time, the reset operation is performed after the external reset is released. 136 FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 6 RESET 6.3 MB90950 Series 6.3 External Reset Pin The external reset pin (RST pin) is a dedicated reset input pin that generates an internal reset by inputting an "L" level. For the MB90950 series, resets are generated in synchronization with the CPU operating clock however, only the external pin generates a reset in asynchronous manner. ■ Block Diagram of the External Reset Pin Figure 6.3-1 Block Diagram of External Reset Pin CPU operating clock RST P-ch Synchronization circuit Pin CPU peripheral functions N-ch Input buffer HCLK: Oscillation clock Note: Inputs to the RST pin are accepted during cycles in which memory is not affected in order to prevent memory from being destroyed by a reset during a write operation. A clock is required to initialize the internal circuit. CM44-10148-4E FUJITSU MICROELECTRONICS LIMITED 137 CHAPTER 6 RESET 6.4 6.4 MB90950 Series Reset Operation When a reset is released, the memory locations from which the mode data and the reset vectors are read are selected according to the setting of the mode pins, and a mode fetch is performed. The mode fetch determines the CPU operating mode and the execution start address after a reset operation ends. When returning by a reset at power-on or a reset from sub clock and stop mode, a mode fetch is performed when the oscillation stabilization wait time elapses. ■ Overview of Reset Operation Figure 6.4-1 shows the reset operation flow. Figure 6.4-1 Reset Operation Flow Power-on reset Stop mode Sub clock mode During a reset Oscillation stabilization wait reset state External reset Software reset Watchdog timer reset Low-voltage detection reset CPU operation detection reset Clock supervisor reset Fetching the reset vector Mode fetch (Reset operation) Fetching the mode data Normal operation (RUN state) CPU executes an instruction, fetching the instruction codes from the address indicated by the reset vector. ■ Mode Pins Setting the mode pins (MD0 to MD2) specifies how to fetch the reset vector and the mode data. Fetching the reset vector and the mode data is performed in the reset sequence. See Section "8.1.1 Mode Pin", for details on mode pins. ■ Mode Fetch When the reset is released, the CPU transfers the reset vector and the mode data to the appropriate registers in the CPU core by hardware. The reset vector and mode data are allocated to the 4 bytes from "FFFFDCH" to "FFFFDFH". The CPU outputs these addresses to the bus immediately after the reset is released and then fetches the reset vector and mode data. Using the mode fetch, the CPU can begin processing at the address indicated by the reset vector. Figure 6.4-2 shows the transfer of the reset vector and mode data. 138 FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 6 RESET 6.4 MB90950 Series Figure 6.4-2 Transfer of Reset Vector and Mode Data F2MC-16LX CPU core Memory Space Mode register FFFFDFH Mode data FFFFDEH Reset vector bits (23 to 16) Micro-ROM Reset sequence FFFFDDH Reset vector bits (15 to 8) FFFFDCH Reset vector bits (7 to 0) PCB PC ● Mode data (address: FFFFDFH) Only a reset operation can change the contents of the mode register. The mode register setting becomes valid after a reset operation. See Section "8.1.2 Mode Data", for details on mode data. ● Reset vector (address: FFFFDCH to FFFFDEH) The execution start address after the reset operation ends is written as the reset vector. Execution starts with the address contained in the reset vector. CM44-10148-4E FUJITSU MICROELECTRONICS LIMITED 139 CHAPTER 6 RESET 6.5 6.5 MB90950 Series Reset Source Bits A reset source can be identified by reading the watchdog timer control register (WDTC). ■ Reset Source Bits As shown in Figure 6.5-1, each reset source has a corresponding flip-flop. The contents of the flip-flops can be obtained by reading the watchdog timer control register (WDTC). If the source of a reset must be identified after the reset has been released, the value read from the WDTC should be processed by the software and branched to the appropriate program. Figure 6.5-1 Block Diagram of Reset Source Bits No periodic clear RST pin Drop power supply voltage C P U o p e r a t i o n Low-voltage d e t e c t i o n r e s e t detection r e q u e s t d e t e c t i o n circuit c i r c u i t Power-on RST="L" External reset Clock request supervisor detection circuit circuit Power-on detection circuit No periodic clear RST bit set Watchdog timer reset generation detection circuit LPMCR:RST bit write detection circuit Clear Watchdog timer control register (WDTC) S R S F/F Q R S S F/F F/F Q R Q R F/F Q Delay circuit Reading of watchdog timer control register (WDTC) Internal data bus S : Set R : Reset Q : Output F/F : Flip Flop ■ Correspondence Between Reset Source Bits and Reset Sources Figure 6.5-2 shows the configuration of the reset source bits of the watchdog timer control register (WDTC). Table 6.5-1 maps the correspondence between the reset source bits and reset sources. See Section "11.3.1 Watchdog Timer Control Register (WDTC)", for details. 140 FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 6 RESET 6.5 MB90950 Series Figure 6.5-2 Configuration of the Reset Source Bits (Watchdog Timer Control Register) Watchdog timer control register (WDTC) Address bit15 0000A8H ........ bit8 (TBTC) R : Read only W : Write only X : Undefined bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 PONR Reserved WRST ERST SRST WTE WT1 WT0 Initial value R R R R R W W W X1XXX111B Table 6.5-1 Correspondence between Reset Source Bits and Reset Sources LVRC Reset source PONR WRST ERST LVRF Power-on reset request generated 1 Watchdog timer overflow reset request generated X X CPUF X MM 0 1 External reset request via the RST pin 1 0 Low-voltage detection reset 1 1 CPU operation detection reset 1 Clock supervisor (main oscillation halt) 1 Software reset request generated CSVCR SRST 0 0 0 1 1 1 : Previous state retained X : Undefined CM44-10148-4E FUJITSU MICROELECTRONICS LIMITED 141 CHAPTER 6 RESET 6.5 MB90950 Series ■ Status of Reset Source Bit and Low-voltage Detection Bit Figure 6.5-3 Status of Reset Source Bit and Low-voltage Detection Bit Flag status at power-on Bit clear (1) (2) Flag status at Bit low voltage detection (4V) clear VCC=4 V VCC (3) (4) PONR bit (power-on) 1 → 0 → 0 → 0 ERST bit (external reset input, CPU operation detection, or LVRF = 1) 1 or 0 → 0 → 1 → 0 LVRF bit* (low voltage detection 4 V ± 0.2 V) 1 or 0 → 0 → 1 → 0 *: The LVRF bit exists in the low-voltage/CPU operation detection reset control register (LVRC). (1)At power-on Power-on reset bit (PONR), ERST, and LVRF are set to "1" at power on. However, ERST and LVRF are set to "0" when there is a steep rise at power-on. (2)Bit clear Bit is cleared by reading the WDTC register and by writing "0" to LVRF. (3)At low voltage detection (4.0 V ± 0.2 V)* The LVRF and ERST bits are set to "1" at low voltage detection of VCC = 4.0 V ± 0.2 V. *: See "CHAPTER 26 LOW-VOLTAGE/CPU OPERATION DETECTION RESET CIRCUIT" for setting value of low-voltage detection voltage. (4)Bit clear Bit is cleared by reading the WDTC register and by writing "0" to LVRF. 142 FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 6 RESET 6.5 MB90950 Series ■ Notes on Reset Source Bits ● When multiple reset sources are generated When multiple reset sources are generated at the same time, the corresponding reset source bits of the watchdog timer control register (WDTC) are set to "1". For example, an external reset request via the RST pin and the watchdog timer overflow occur at the same time, both ERST and the WRST bits are set to "1". ● Power-on reset For a power-on reset, the PONR bit is set to "1" but all other reset source bits are undefined. Because of it, the software should be programmed so that it will ignore all reset source bits except the PONR when it is "1". ● Clearing the reset source bits The reset source bits are cleared only when the watchdog timer control register (WDTC) is read. Any flag generated in the bit corresponding to a reset source is not cleared even though another reset is generated and remains to "1". Note: If the power is turned-on under conditions where no power-on reset occurs, the value in this register may not be guaranteed. CM44-10148-4E FUJITSU MICROELECTRONICS LIMITED 143 CHAPTER 6 RESET 6.6 6.6 MB90950 Series Status of Pins by Reset This section describes the status of pins when a reset occurs. ■ Status of Pins During a Reset The status of pins during a reset depends on the settings of mode pins (MD2 to MD0). Refer to Section "7.7 Pin State in the Standby Mode and at the Time of Reset" for the status of pins during a reset. ● When internal vector mode has been set (MD2 to MD0 = 011B) All I/O pins (peripheral function pins) are high impedance, and mode data is read from the internal ROM. ■ Status of Pins after Mode Data is Read The status of pins after mode data has been read depends on the mode data (M1 and M0). ● When single chip mode has been selected (M1 and M0 = 00B) All I/O pins (peripheral function pins) are high impedance, and mode data is read from the internal ROM. Note: For those pins that change to high impedance when a reset source is generated, confirm that devices connected to those pins do not malfunction. 144 FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 7 LOW-POWER CONSUMPTION MODE This chapter explains the low-power consumption mode. 7.1 Overview of the Low-power Consumption Mode 7.2 Block Diagram of the Low-power Consumption Circuit 7.3 Low-power Consumption Mode Control Register (LPMCR) 7.4 CPU Intermittent Operation Mode 7.5 Standby Mode 7.6 State Transition of the Standby Mode 7.7 Pin State in the Standby Mode and at the Time of Reset 7.8 Notes on Using the Low-power Consumption Mode CM44-10148-4E FUJITSU MICROELECTRONICS LIMITED 145 CHAPTER 7 LOW-POWER CONSUMPTION MODE 7.1 7.1 MB90950 Series Overview of the Low-power Consumption Mode CPU operation modes can be classified into the following operation modes based on the operation clock selection and the clock oscillation control. Operation modes except for the PLL clock mode belong to the low-power consumption mode. • Clock modes (main clock mode, PLL clock mode, and sub clock mode) • CPU intermittent operation modes (main clock intermittent operation mode, PLL clock intermittent operation mode, and sub clock intermittent operation mode) • Standby modes (sleep mode, stop mode, watch mode, and time-base timer mode) ■ CPU Operation Modes and Current Dissipation Figure 7.1-1 shows the relationship between CPU operation modes and their current dissipation. Figure 7.1-1 CPU Operation Modes and Current Dissipation Current dissipation Tens of mA CPU operation mode PLL clock mode Multiply-by-eight clock Multiply-by-six clock Multiply-by-four clock Multiply-by-three clock Multiply-by-two clock Multiply-by-one clock PLL clock intermittent operation mode Multiply-by-eight clock Multiply-by-six clock Multiply-by-four clock Multiply-by-three clock Multiply-by-two clock Multiply-by-one clock Main clock mode (1/2HCLK) Main clock intermittent operation mode Sub clock mode (divide-by-eight or divide-by-four of CR oscillation frequency) Some mA Sub clock intermittent operation mode Standby mode Sleep mode Time-base timer mode Watch mode Low-power consumption mode Stop mode This figure shows the image of operation modes, and actual current dissipation may differ. 146 FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 7 LOW-POWER CONSUMPTION MODE 7.1 MB90950 Series ■ Clock Modes ● PLL clock mode This is a mode that uses PLL multiplier clocks of the oscillation clock (HCLK) to operate CPU and peripheral functions. ● Main clock mode This is a mode that uses the divide-by-two clock of the oscillation clock (HCLK) to operate CPU and peripheral functions. During the main clock mode, the PLL multiplier circuit stops. ● Sub clock mode This is a mode that uses the sub clock (SCLK) to operate CPU and peripheral functions. Either divide-byeight or divide-by-four of the CR oscillation clock can be selected for the sub clock. During the sub clock mode, the main clock and PLL multiplier circuit stop. When power is turned on or the stop mode is canceled, a sub clock oscillation stabilization wait time 214/SCLK occurs (in the case oscillation clock frequency is 100 kHz with divide-by-eight setting: about 1.3 s). Therefore, if the main clock mode is switched to the sub clock mode therein, an oscillation stabilization wait time occurs. Reference: See "CHAPTER 5 CLOCK" for details on the clock mode. ■ CPU Intermittent Operation Mode This is a mode that reduces power dissipation by operating a CPU intermittently while providing highspeed clock to peripheral functions. The CPU intermittent operation mode provides intermittent clock only to a CPU when registers, internal memory peripheral functions, and external accesses are being used. ■ Standby Mode The standby mode reduces power dissipation by stopping providing operation clock to a CPU and peripheral functions using a standby control circuit or stopping the oscillation clock (HCLK). ● Sleep mode The sleep mode is a mode that stops providing operation clock to a CPU while a clock mode is operating. The CPU stops, and peripheral functions operate at the clock before switching to the sleep mode. Depending on the clock mode when transiting to the sleep mode, it is classified into the main sleep mode, PLL sleep mode, or sub sleep mode. ● Watch mode The watch mode is a mode that operates the sub clock (SCLK) and watch timer only. The main clock and PLL clock stop. Peripheral functions except the watch timer also stop. If the WDCS bit in WTC register is "0", the watchdog timer continues to operate. CM44-10148-4E FUJITSU MICROELECTRONICS LIMITED 147 CHAPTER 7 LOW-POWER CONSUMPTION MODE 7.1 MB90950 Series ● Time-base timer mode The time-base timer mode is a mode that operates the oscillation clock (HCLK), sub clock (SCLK), watchdog timer, time-base timer and watch timer only. Peripheral functions except the time-base timer, watchdog timer and watch timer stop. ● Stop mode The stop mode is a mode that stops the oscillation clock (HCLK) and sub clock (SCLK) while a clock mode is operating. Data can be kept with lowest power dissipation. Note: When a clock mode is being switched, do not again switch to other clock modes or the low-power consumption mode before the switching completes. The completion of switching can be checked by referring to the MCM bit and SCM bit in the clock selection register (CKSCR). If a mode is switched again to other clock modes or the low-power consumption mode before the first switching is finished, the second switching may not complete. 148 FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 7 LOW-POWER CONSUMPTION MODE 7.2 MB90950 Series 7.2 Block Diagram of the Low-power Consumption Circuit This section shows the block diagram of the low-power consumption circuit. ■ Block Diagram of the Low-power Consumption Circuit Figure 7.2-1 Block Diagram of the Low-power Consumption Circuit Low-power consumption mode control register (LPMCR) STP SLP SPL RST TMD CG1 CG0 Reserved RST Pin CPU intermittent operation cycle selector Pin high impedance control circuit Pin Hi-Z control Internal reset generation circuit Internal reset Intermittent cycle selected CPU operation clock CPU clock control circuit Reset (cancel) Watch, sleep, and stop signals Standby control circuit 2 Watch and stop signals Peripheral Peripheral functions clock control operation clock circuit Sub clock oscillation stabilization wait canceled Main clock oscillation stabilization wait canceled Interrupt (cancel) Clock generation block Operation clock selector Machine clock 2 CS2 PLL/Sub clock control register (PSCCR):bit8 Oscillation stabilization wait time selector 2 PLL multiplier circuit SCM MCM WS1 WS0 SCS MCS CS1 CS0 Clock selection register (CKSCR) Clock Selector X0 Pin Divideby-two Oscillation clock (HCLK) X1 Pin Oscillation clock oscillation circuit Clock Selector Sub clock (SCLK) Divide-byfour/divideby-two SCDS Internal CR oscillation clock CM44-10148-4E Divideby-two Divide- Divide- by-four Main by-512 clock Time-base timer Divideby-1024 Divideby-two Divideby-two Divideby-two Divideby-two Divideby-two Divideby-four To watchdog timer Divideby-eight Divideby-two Divideby-two Watch timer PLL/sub clock control register (PSCCR):bit10 Clock monitor function FUJITSU MICROELECTRONICS LIMITED 149 CHAPTER 7 LOW-POWER CONSUMPTION MODE 7.2 MB90950 Series ● CPU intermittent operation selector Selects the pause cycle count for CPU clock in the CPU intermittent operation mode. ● Standby control circuit Switches to and cancels the standby mode by switching CPU operation clock and peripheral function operation clock using the CPU clock control circuit and peripheral clock control circuit. ● CPU clock control circuit This is a circuit that provides operation clock to a CPU. ● Pin high impedance control circuit Switches an I/O pin to high impedance state when the mode is the watch mode, time-base timer mode, or stop mode. ● Internal reset generation circuit Generates internal reset signals. ● Low-power consumption mode control register (LPMCR) Switches to and cancels the standby mode, or configures the CPU intermittent operation mode. 150 FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 7 LOW-POWER CONSUMPTION MODE 7.3 MB90950 Series 7.3 Low-power Consumption Mode Control Register (LPMCR) The low-power consumption mode control register (LPMCR) switches to and cancels the low-power consumption mode, generates internal reset signals, and sets the pause cycle count of the CPU intermittent operation mode. ■ Low-power Consumption Mode Control Register (LPMCR) Figure 7.3-1 Low-power Consumption Mode Control Register (LPMCR) bit 7 6 5 4 3 2 1 STP SLP SPL RST TMD CG1 CG0 W W R/W W W 0 Initial value Reserved 00011000B R/W R/W R/W bit0 Reserved bit Reserved 0 Always set to "0" bit2 bit1 CG1 CG0 CPU pause cycle count selection bits 0 0 0 cycle (CPU clock = peripheral clock) 0 1 8 cycles (CPU clock : peripheral clock = 1: approx. 3 to 4) 1 0 16 cycles (CPU clock : peripheral clock = 1: approx. 5 to 6) 1 1 32 cycles (CPU clock : peripheral clock = 1: approx. 9 to 10) bit3 TMD 0 1 bit4 RST 0 1 bit5 SPL 0 1 Watch mode bit Transits to the watch mode or time-base timer mode No effect Internal reset signal generation bit Generates internal reset signals at 3 machine cycles No effect Pin state setting bit Keeps an input/output pin state High impedance Enabled only in the time-base timer, watch, and stop modes bit6 Sleep mode bit SLP No effect 0 1 Transits to the sleep mode bit7 STP R/W : Readable/writable : Write only W : Initial value CM44-10148-4E Stop mode bit 0 No effect 1 Transits to the stop mode FUJITSU MICROELECTRONICS LIMITED 151 CHAPTER 7 LOW-POWER CONSUMPTION MODE 7.3 MB90950 Series Table 7.3-1 Functions of Low-power Consumption Mode Control Register (LPMCR) Bit name Function STP: Stop mode bit Switches to the stop mode. When set to "0": No effect. When set to "1": Switches to the stop mode. When reading: "0" is consistently read. • Initialized to "0" by a reset or an external interrupt. SLP: Sleep mode bit Switches to the sleep mode. When set to "0": No effect. When set to "1": Switches to the sleep mode. When reading : "0" is consistently read. • Initialized to "0" by a reset or an external interrupt. • If "1" is set to the STP bit and SLP bit concurrently, the STP bit has priority, switching to the stop mode. bit5 SPL: Pin state setting bit Sets the state of an input/output pin when switching to the stop mode, watch mode, and time-base timer mode. When set to "0": Keeps the current level of an input/output pin. When set to "1": Switches the input/output pin to high impedance state. • Initialized to "0" by a reset. bit4 RST: Internal reset signal generation bit Generates a software reset. When set to "0": Generates internal reset signals at 3 machine cycles. When set to "1": No effect. When reading : "1" is consistently read. bit7 bit6 bit3 TMD: Watch mode bit Switches to the watch mode or time-base timer mode. When set to "0": Switches to the time-base timer mode if the mode is the main clock mode or PLL clock mode. Switches to the watch mode if the mode is the sub clock mode. When set to "1": No effect. • "1" is set by a reset or interrupt. When reading : "1" is consistently read. 152 bit2, bit1 CG1, CG0: CPU pause cycle count selection bits Sets the pause cycle count for CPU clock in the CPU intermittent operation mode. bit0 Reserved: Reserved bit Always set to "0". • Returns to initial values by all kinds of reset. FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 7 LOW-POWER CONSUMPTION MODE 7.3 MB90950 Series Notes: • Use the instructions in Table 7.3-2 to configure the settings for switching to the low-power consumption mode in the low-power consumption mode control register (LPMCR). Operations cannot be assured if instructions other than shown in the list below are used to switch to the lowpower consumption mode. • Immediately after using the standby mode transition instructions in Table 7.3-2, be sure to add the instructions shown in the dotted square below. MOV LPMCR, #H’xx ; Low-power consumption mode transition instruction in Table 7.3-2 NOP NOP JMP $+3 ; Jump to next instruction MOV A, #H’10 ; Any instruction If instruction lines other than shown in the dotted square are added, operations after canceling the standby mode will not be assured. • If the C language is used to access the low-power consumption mode control register, see "■Notes on Accessing the Low-power Consumption Mode Control Register (LPMCR) for Switching to the Standby Mode" in Section "7.8 Notes on Using the Low-power Consumption Mode". • Use even number addresses to write in the low-power consumption mode control register (LPMCR) in units of words. If an odd number address is used to write, it may cause malfunction. • During the stop mode, watch mode, or time-base timer mode, in order to set the pin sharing a port with peripheral functions to high impedance state, after prohibiting the output by peripheral functions, set the STP bit to "1" or TMD bit to "0" in the low-power consumption mode control register (LPMCR). Table 7.3-2 List of Instructions Used When Transiting to the Low-power Consumption Mode CM44-10148-4E MOV io,#imm8 MOV dir,#imm8 MOV eam,#imm8 MOV eam,Ri MOV io,A MOV dir,A MOV addr16,A MOV eam,A MOV @RLi+disp8,A MOVW io,#imm16 MOVW dir,#imm16 MOVW eam,#imm16 MOVW eam,RWi MOVW io,A MOVW dir,A MOVW addr16,A MOVW eam,A MOVW @RLi+disp8,A SETB io:bp SETB dir:bp SETB addr16:bp CLRB io:bp CLRB dir:bp CLRB addr16:bp FUJITSU MICROELECTRONICS LIMITED 153 CHAPTER 7 LOW-POWER CONSUMPTION MODE 7.4 7.4 MB90950 Series CPU Intermittent Operation Mode The CPU intermittent operation mode is a mode that reduces power dissipation by operating a CPU intermittently while providing operation clock to the CPU and peripheral functions. ■ Operation of CPU Intermittent Operation Mode When the CPU accesses the register, internal memory, I/O, peripheral functions, and external buses, the CPU intermittent operation mode temporarily holds the clock provided to CPU every time an instruction is executed to delay the activation of internal buses. It can reduce power dissipation by lowering the CPU execution speed while providing high-speed clock to peripheral functions. • The machine cycle count to temporarily stop providing clock to CPU is set at the CG1 and CG0 bits in the low-power consumption mode control register (LPMCR). • The instruction execution time of the CPU intermittent operation mode can be calculated by adding the normal execution time to the adjusted value that is the number of accesses to the register, internal memory, peripheral functions, and external buses multiplied by the number of pause cycle count. Figure 7.4-1 shows the clock operation of the CPU intermittent operation mode. Figure 7.4-1 Clock Operation of the CPU Intermittent Operation Mode Peripheral clock CPU clock One instruction execution cycle Pause cycle Internal bus activated 154 FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 7 LOW-POWER CONSUMPTION MODE 7.5 MB90950 Series 7.5 Standby Mode The standby mode can reduce power dissipation by stopping providing operation clock to a CPU and peripheral functions using a standby control circuit or stopping the oscillation clock. ■ Types and Operation States of the Standby Mode Table 7.5-1 shows the types and operation states of the standby mode. Table 7.5-1 Types and Operation States of the Standby Mode (1 / 2) Mode name Transition conditions Oscillation clock (HCLK) Sub clock (SCLK) Machine clock CPU Watchdog timer Peripheral functions Pin Release method Main sleep mode MCS=1 SCS=1 SLP=1 ❍ ❍ ❍ × ❍*7 ❍ ❍ External reset or interrupt Sub sleep mode SCKS=1 MCS=X SCS=0 SLP=1 WDCS=0 × ❍ ❍ × ❍*7 ❍ ❍ External reset or interrupt Sub sleep mode SCKS=1 MCS=X SCS=0 SLP=1 WDCS=1 × ❍ ❍ × − *8 ❍ ❍ External reset or interrupt PLL sleep mode MCS=0 SCS=1 SLP=1 ❍ ❍ ❍ × ❍*7 ❍ ❍ External reset or interrupt SPL=0 MCS=X SCS=1 TMD=0 ❍ ❍ × × ❍*7 ×*1 ◊ External reset or interrupt*4 SPL=1 MCS=X SCS=1 TMD=0 ❍ ❍ × × ❍*7 ×*1 Hi-Z*3 External reset or interrupt*4 Sleep mode Time-base timer mode CM44-10148-4E FUJITSU MICROELECTRONICS LIMITED 155 CHAPTER 7 LOW-POWER CONSUMPTION MODE 7.5 MB90950 Series Table 7.5-1 Types and Operation States of the Standby Mode (2 / 2) Oscillation clock (HCLK) Sub clock (SCLK) Machine clock CPU Watchdog timer Peripheral functions Pin Release method SPL=0 SCKS=1 MCS=X SCS=0 TMD=0 WDCS=0 × ❍ × × ❍*7 ×*2 ◊ External reset or interrupt*5 SPL=1 SCKS=1 MCS=X SCS=0 TMD=0 WDCS=0 × ❍ × × ❍*7 ×*2 Hi-Z*3 External reset or interrupt*5 SPL=0 SCKS=1 MCS=X SCS=0 TMD=0 WDCS=1 × ❍ × × − *8 ×*2 ◊ External reset or interrupt*5 SPL=1 SCKS=1 MCS=X SCS=0 TMD=0 WDCS=1 × ❍ × × − *8 ×*2 Hi-Z*3 External reset or interrupt*5 SPL=0 STP=1 × × × × × × ◊ External reset or interrupt*6 SPL=1 STP=1 × × × × × × Hi-Z*3 External reset or interrupt*6 Mode name Watch mode Transition conditions Stop mode ❍: Operating ×: Stopped ◊ : Keeps the state before transition Hi-Z : High impedance *1 : The time-base timer and watch timer operate. *2 : The watch timer operates. *3 : The input pin for DTP/external interrupt operates. *4 : Watch timer, time-base timer, and external interrupt *5 : Watch timer and external interrupt *6 : External interrupt *7 : The watchdog timer will be cleared when transiting to a different mode. *8 : The watchdog timer is not available. MCS: PLL clock selection bit of the clock selection register (CKSCR) SCS: Sub clock selection bit of the clock selection register (CKSCR) SPL: Pin state setting bit of the low-power consumption mode control register (LPMCR) SLP: Sleep mode bit of the low-power consumption mode control register (LPMCR) STP: Stop mode bit of the low-power consumption mode control register (LPMCR) TMD: Watch mode bit of the low-power consumption mode control register (LPMCR) SCKS: Sub clock selection bit of the clock supervisor control register (CSVCR) Note: During the stop mode, watch mode, or time-base timer mode, in order to set the pin sharing a port with peripheral functions to high impedance state, after prohibiting the output by peripheral functions, set the STP bit to "1" or TMD bit to "0" in the low-power consumption mode control register (LPMCR). 156 FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 7 LOW-POWER CONSUMPTION MODE 7.5 MB90950 Series 7.5.1 Sleep Mode The sleep mode is an operation mode that stops providing operation clock to a CPU while a clock mode is operating. The CPU stops, but peripheral functions continue to operate. ■ Switching to the Sleep Mode When the mode is switched to the sleep mode by the low-power consumption mode control register settings (LPMCR: SLP=1, STP=0), the transition to the sleep mode bases on the settings in the MCS bit and SCS bit of the clock selection register (CKSCR). Table 7.5-2 shows the correspondence between the sleep mode and the settings of the MCS bit and SCS bit in the clock selection register (CKSCR). Table 7.5-2 Clock Selection Register (CKSCR) Settings and Their Sleep Modes Clock selection register (CKSCR) Sleep mode to switch to MCS SCS 1 1 Main sleep mode 0 1 PLL sleep mode 1 0 0 0 Sub sleep mode Note: If "1" is concurrently set to the STP bit and SLP bit in the low-power consumption mode control register (LPMCR), the STP bit has priority, switching to the stop mode. Also, if "1" is set to the SLP bit and "0" to the TMD bit concurrently, the TMD bit has priority, switching to the time-base timer mode or watch mode. ● Data retaining function During the sleep mode, data stored in internal RAMs and dedicated registers such as an accumulator will be retained. ● External bus hold function During the sleep mode, the external bus hold function operates. If a hold request is generated to CPU, the state transits to hold state. ● Operations while an interrupt request exists While "1" is set to the SLP bit in the low-power consumption mode control register (LPMCR), if an interrupt request exists, the mode does not switch to the sleep mode. If the CPU cannot accept an interrupt request, the next instruction of the current one will be executed. On the other hand, if the CPU can accept an interrupt request, it will immediately branch to the interrupt processing routine. CM44-10148-4E FUJITSU MICROELECTRONICS LIMITED 157 CHAPTER 7 LOW-POWER CONSUMPTION MODE 7.5 MB90950 Series ● Pin state During the sleep mode, pins except ones that are used for bus input/output or bus control will keep the state before switching to the sleep mode. ■ Returning from the Sleep Mode Generation of a reset source or interrupt will cancel the sleep mode. ● Returning by a reset source If the sleep mode is canceled by a reset source, after canceling the sleep mode, the mode switches to the main clock mode and then to a reset sequence. Note: To return from sub sleep mode to main clock mode by external reset pin (RST pin), input "L" level for the following period: Oscillation time of oscillator* + 100μs + 16 machine cycles , or more *: The oscillation time of the oscillator is the time it takes for the amplitude of the oscillations to reach 90%. For crystal oscillators, this time is between several ms and several tens of ms, for ceramic oscillators the time is between several hundred μs and several ms. ● Returning by an interrupt During the sleep mode, if an interrupt request with interrupt level (IL) higher than seven is generated by peripheral functions or the like, the sleep mode will be canceled. And after canceling the sleep mode, generated interrupt requests will be judged based on the I flag in the condition code register (CCR) and the settings in the interrupt level mask register (ILM) and interrupt control register (ICR) as in the case with normal interrupt processing. • If the CPU cannot accept an interrupt request, the next instruction of the current one will be executed. • If the CPU can accept an interrupt request, it will immediately branch to the interrupt processing routine. 158 FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 7 LOW-POWER CONSUMPTION MODE 7.5 MB90950 Series Figure 7.5-1 shows the canceling of the sleep mode by an interrupt. Figure 7.5-1 Canceling of the Sleep Mode by an Interrupt Interrupt flag settings of peripheral functions INT occurs (IL < 7) YES NO Does not cancel sleep Does not cancel sleep Cancels sleep YES I=0 Executes the next instruction NO ILM < IL YES NO Executes interrupt processing Note: When executing an interrupt processing, it will be normally done after executing the next instruction of the instruction having a sleep mode specification. However, if the switching to sleep mode and the reception of external bus hold request are done simultaneously, the transition to interrupt processing may occur before executing the next instruction. CM44-10148-4E FUJITSU MICROELECTRONICS LIMITED 159 CHAPTER 7 LOW-POWER CONSUMPTION MODE 7.5 7.5.2 MB90950 Series Watch Mode The watch mode is a mode that operates the sub clock (SCLK) and watch timer only. The main clock and PLL clock stop. If the WDCS bit in WTC register is "0", the watchdog timer continues to operate. ■ Switching to the Watch Mode If "0" is written in the TMD bit of LPMCR because of the setting of low-power consumption mode control register (LPMCR) during the sub clock mode, the mode switches to the watch mode. ● Data retaining function During the watch mode, data stored in internal RAMs and dedicated registers such as an accumulator will be retained. ● External bus hold function During the watch mode, the external bus hold function stops. Although a hold request to CPU is input, it will not be accepted. If a hold request is input during the transition to watch mode, the HAK signal may not change to "L" level while keeping buses in high impedance state. ● Operations while an interrupt request exists While "0" is set to the TMD bit in the low-power consumption mode control register (LPMCR), if an interrupt request exists, the mode does not switch to the watch mode. If the CPU cannot accept an interrupt request, the next instruction of the current one will be executed. On the other hand, if the CPU can accept an interrupt request, it will immediately branch to the interrupt processing routine. ● Pin state The state of input/output pins during the watch mode can be specified either to change to high impedance state or to keep the state before transiting to the watch mode, by setting the SPL bit in the low-power consumption mode control register (LPMCR). Note: During the watch mode, in order to set the pin sharing a port with peripheral functions to high impedance state, after prohibiting the output by peripheral functions, set the TMD bit in the lowpower consumption mode control register (LPMCR) to "0". 160 FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 7 LOW-POWER CONSUMPTION MODE 7.5 MB90950 Series ■ Returning from the Watch Mode Generation of a reset source or interrupt will cancel the watch mode. ● Returning by a reset source If the watch mode is canceled by a reset source, after canceling the watch mode, the mode switches to the main clock mode and then to a reset sequence. ● Returning by an interrupt During the watch mode, if an interrupt request with interrupt level (IL) higher than seven is generated by the watch timer and an external interrupt, the watch mode will be canceled. And after canceling the watch mode, the interrupt requests will be judged based on the I flag in the condition code register (CCR) and the settings in the interrupt level mask register (ILM) and interrupt control register (ICR) as in the case with normal interrupt processing. In the case of sub watch mode, because it does not have oscillation stabilization wait time, the interrupt request will be judged immediately after returning to the watch mode. • If the CPU cannot accept an interrupt request, the next instruction of the current one will be executed. • If the CPU can accept an interrupt request, it will immediately branch to the interrupt processing routine. Note: When executing an interrupt processing, it will be normally done after executing the next instruction of the instruction having a watch mode specification. However, if the switching to watch mode and the reception of external bus hold request are done simultaneously, the transition to interrupt processing may occur before executing the next instruction. CM44-10148-4E FUJITSU MICROELECTRONICS LIMITED 161 CHAPTER 7 LOW-POWER CONSUMPTION MODE 7.5 7.5.3 MB90950 Series Time-base Timer Mode The time-base timer mode is a mode that operates the oscillation clock (HCLK), sub clock (SCLK), time-base timer and watch timer only. Peripheral functions except the time-base timer, watchdog timer and watch timer stop. ■ Switching to the Time-base Timer Mode If "0" is written in the TMD bit of low-power consumption mode control register (LPMCR) while the PLL clock mode or main clock mode is operating (CKSCR: SCM=1), the mode switches to the time-base timer mode. ● Data retaining function During the time-base timer mode, data stored in internal RAMs and dedicated registers such as an accumulator will be retained. ● External bus hold function During the time-base timer mode, the external bus hold function stops. Although a hold request to CPU is input, it will not be accepted. If a hold request is input during the transition to time-base timer mode, the HAK signal may not change to "L" level while keeping buses in high impedance state. ● Operations while an interrupt request exists While "0" is set to the TMD bit in the low-power consumption mode control register (LPMCR), if an interrupt request exists, the mode does not switch to the time-base timer mode. If the CPU cannot accept an interrupt request, the next instruction of the current one will be executed. On the other hand, if the CPU can accept an interrupt request, it will immediately branch to the interrupt processing routine. ● Pin state The state of input/output pins during the time-base timer mode can be specified either to change to high impedance state or to keep the state before transiting to the time-base timer mode, by setting the SPL bit in the low-power consumption mode control register (LPMCR). Note: During the time-base timer mode, in order to set the pin sharing a port with peripheral functions to high impedance state, after prohibiting the output by peripheral functions, set the TMD bit in the lowpower consumption mode control register (LPMCR) to "0". 162 FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 7 LOW-POWER CONSUMPTION MODE 7.5 MB90950 Series ■ Returning from the Time-base Timer Mode Generation of a reset source or interrupt will cancel the time-base timer mode. ● Returning by a reset source If the time-base timer mode is canceled by a reset source, after canceling the time-base timer mode, the mode switches to the main clock mode and then to a reset sequence. ● Returning by an interrupt During the time-base timer mode, if an interrupt request with interrupt level (IL) higher than seven is generated by the watch timer, time-base timer and an external interrupt, the time-base timer mode will be canceled. And after canceling the time-base timer mode, generated interrupt requests will be judged based on the I flag in the condition code register (CCR) and the settings in the interrupt level mask register (ILM) and interrupt control register (ICR) as in the case with normal interrupt processing. • If the CPU cannot accept an interrupt request, the next instruction of the current one will be executed. • If the CPU can accept an interrupt request, it will immediately branch to the interrupt processing routine. • The time-base timer mode has the following two types: - Main clock to/from time-base timer mode - PLL clock to/from time-base timer mode Note: When executing an interrupt processing, it will be normally done after executing the next instruction of the instruction having a time-base timer mode specification. However, if the switching to time-base timer mode and the reception of external bus hold request are done simultaneously, the transition to interrupt processing may occur before executing the next instruction. CM44-10148-4E FUJITSU MICROELECTRONICS LIMITED 163 CHAPTER 7 LOW-POWER CONSUMPTION MODE 7.5 7.5.4 MB90950 Series Stop Mode The stop mode is a mode that stops the oscillation clock (HCLK) and sub clock (SCLK) while a clock mode is operating. Data can be kept with lowest power dissipation. ■ Stop Mode If "1" is written in the STP bit of low-power consumption mode control register (LPMCR) while the PLL clock mode is operating (CKSCR: MCS=1, SCS=0), the mode switches to the stop mode based on the settings of MCS bit and SCS bit in the clock selection register (CKSCR). Table 7.5-3 shows the correspondence between the stop mode and the settings of the MCS bit and SCS bit in the clock selection register (CKSCR). Table 7.5-3 Clock Selection Register (CKSCR) Settings and Their Stop Modes Clock selection register (CKSCR) Stop mode to switch to MCS SCS 1 1 Main stop mode 0 1 PLL stop mode 1 0 0 0 Sub stop mode Note: If "1" is concurrently set to the STP bit and SLP bit in the low-power consumption mode control register (LPMCR), the STP bit has priority, switching to the stop mode. ● Data retaining function During the stop mode, data stored in internal RAMs and dedicated registers such as an accumulator will be retained. ● External bus hold function During the stop mode, the external bus hold function stops. Although a hold request to CPU is input, it will not be accepted. If a hold request is input during the transition to stop mode, the HAK signal may not change to "L" level while keeping buses in high impedance state. ● Operations while an interrupt request exists While "1" is set to the STP bit in the low-power consumption mode control register (LPMCR), if an interrupt request exists, the mode does not switch to the stop mode. If the CPU cannot accept an interrupt request, the next instruction of the current one will be executed. On the other hand, if the CPU can accept an interrupt request, it will immediately branch to the interrupt processing routine. 164 FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 7 LOW-POWER CONSUMPTION MODE 7.5 MB90950 Series ● Pin state The state of input/output pins during the stop mode can be specified either to change to high impedance state or to keep the state before transiting to the stop mode, by setting the SPL bit in the low-power consumption mode control register (LPMCR). Note: During the stop mode, in order to set the pin sharing a port with peripheral functions to high impedance state, after prohibiting the output by peripheral functions, set the STP bit in the low-power consumption mode control register (LPMCR) to "1". ■ Returning from the Stop Mode Generation of a reset source or interrupt will cancel the stop mode. When returning from the stop mode, because the oscillation clock (HCLK) and sub clock (SCLK) are suspended, the stop mode will be canceled after the main clock or sub clock oscillation stabilization wait time having elapsed. ● Returning by a reset source If the stop mode is canceled by a reset source, the main clock oscillation stabilization wait time will be necessary. After the main clock oscillation stabilization wait time elapses, the stop mode is canceled and transits to the reset sequence. Figure 7.5-2 shows the returning process from the sub stop mode caused by an external reset. Figure 7.5-2 Returning Process from the Sub Stop Mode Caused by an External Reset RST pin Stop mode Main clock Oscillation stabilization waiting Oscillating Sub clock Oscillation stabilization waiting Oscillating Oscillation stabilization waiting PLL clock CPU operation clock CPU operation Main clock Stopped Reset sequence Oscillating PLL clock Normal process Stop mode canceled Reset canceled CM44-10148-4E FUJITSU MICROELECTRONICS LIMITED 165 CHAPTER 7 LOW-POWER CONSUMPTION MODE 7.5 MB90950 Series ● Returning by an interrupt During the stop mode, if an interrupt request with interrupt level (IL) higher than seven is generated by an external interrupt, the stop mode will be canceled. In the case of stop mode, a main clock oscillation stabilization wait time or sub clock oscillation time will be required after canceling the stop mode. And after finishing the main clock oscillation stabilization wait time or sub clock oscillation wait time, generated interrupt requests will be judged based on the I flag in the condition code register (CCR) and the settings in the interrupt level mask register (ILM) and interrupt control register (ICR) as in the case with normal interrupt processing. • If the CPU cannot accept an interrupt request, the next instruction of the current one will be executed. • If the CPU can accept an interrupt request, it will immediately branch to the interrupt processing routine. Notes: • When executing an interrupt processing, it will be normally done after executing the next instruction of the instruction having a stop mode specification. However, if the switching to stop mode and the reception of external bus hold request are done simultaneously, the transition to interrupt processing may occur before executing the next instruction. When switching to the PLL stop mode, set "10B" or "11B" to the oscillation stabilization wait time selection bits in the clock selection register (CKSCR: WS1, WS0). • During the PLL stop mode, a main clock oscillation stabilization wait time and PLL clock oscillation stabilization wait time have to be secured when returning from the PLL stop mode because the main clock and PLL multiplier circuits are stopped. The oscillation stabilization wait time in this case bases upon the values set in the oscillation stabilization wait time selection bits in the clock selection register (CKSCR:WS1, WS0), and the main clock oscillation stabilization wait time and PLL clock oscillation stabilization wait time will be counted together. Therefore, set a value to the "CKSCR:WS1, WS0" bits in line with the longest one of the oscillation stabilization wait times. However, because 214/HCLK or more is needed for the PLL clock oscillation stabilization wait time, set "10B" or "11B" to the "CKSCR: WS1, WS0" bits. 166 FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 7 LOW-POWER CONSUMPTION MODE 7.6 MB90950 Series 7.6 State Transition of the Standby Mode Operation states and transitions of the clock mode and standby mode in MB90950 series are shown in a chart. ■ State Transition Chart Figure 7.6-1 State Transition Chart Power turned on External reset, watchdog timer reset, software reset, Low-voltage detection reset, CPU operation detection reset, Clock supervisor reset Power-on reset Reset SCKS=1 SCS=0 SCS=1 Oscillation stabilization wait end Main clock mode MCS=0 SCKS=1 PLL clock mode MCS=1 SLP=1 Interrupt Main sleep mode TMD=0 Interrupt Main time-base timer mode STP=1 Main stop mode SCS=0 Sub clock mode SCS=1 SLP=1 Interrupt PLL sleep mode TMD=0 Interrupt PLL time-base timer mode STP=1 PLL stop mode SLP=1 Interrupt Sub sleep mode TMD=0 Interrupt Watch mode STP =1 Sub stop mode Interrupt Oscillation stabili- Interrupt Oscillation stabili- Interrupt Oscillation stabilization wait end zation wait end zation wait end Main clock oscillation stabilization waiting CM44-10148-4E PLL clock oscillation stabilization waiting FUJITSU MICROELECTRONICS LIMITED Sub clock oscillation stabilization waiting 167 CHAPTER 7 LOW-POWER CONSUMPTION MODE 7.7 MB90950 Series Pin State in the Standby Mode and at the Time of Reset 7.7 This section shows the input/output pin states in the standby mode and at the time of reset, for each access mode. ■ Input/Output Pin State (Single Chip Mode) Table 7.7-1 Input/Output Pin State (Single Chip Mode) During stop/watch/time-base timer*6 Pin name During sleep At the time of reset SPL=0 P17 to P10, P27 to P20, P37 to P30, P47 to P40, P57 to P50, P67 to P60, P87 to P80, P97 to P90, PA1,PA0 Shuts off input*4/ Keeps the previous state*2 SPL=1 Shuts off input*4/ Outputs Hi-Z*5 Input unavailable*3/ Outputs Hi-Z*5 Keeps the previous state*2 P07 to P00*7 P77 to P70 Input available*1 PA0, P42, P32, P12, P80 to P82, P84*8 *1: "Input available" means that input functions can be used. If the pin is set as an input port, apply pull-up/pull-down processing or input external signals. If the pin is set as an output port, it transits to the same state as other pins. *2: If the state immediately before transiting to a standby mode is output or input as is, this means "Input unavailable". This means that if an outputting peripheral function is operating, output is obtained according to the state of the peripheral function, and if output is obtained from an output pin, the output will be retained. *3: "Input unavailable" means that the pin data cannot be accepted internally because the internal circuit is stopped while the operation of input gate at the pin is allowed. *4: During shut-off state, input is masked, and the "L" level will be sent inwardly if CMOS/Automotive is selected and the "H" level will be sent inwardly if TTL is selected. *5: "Outputs Hi-Z" means that the pin-driving transistor is prohibited from driving, and the pin is switched to high impedance state. *6: The pull-up function in port 0 to 3 will be disabled in these modes. *7: Can be input in the stop mode when the INTxR bit in external interrupt source selection register EISSR is "0". If the bit is "1", the state transits to the same one as other pins. *8: Can be input in the stop mode when the INTxR bit in external interrupt source selection register EISSR is "1". If the bit is "0", the state transits to the same one as other pins. Note: During the stop mode, watch mode, or time-base timer mode, in order to set the pin sharing a port with peripheral functions to high impedance state, after prohibiting the output by peripheral functions, set the STP bit to "1" or TMD bit to "0" in the low-power consumption mode control register (LPMCR). 168 FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 7 LOW-POWER CONSUMPTION MODE 7.7 MB90950 Series ■ Input/Output Pin State (16-bit Access Mode) Table 7.7-2 Input/output Pin State (16-bit access Mode) During stop/watch/ time-base timer Pin name During sleep During hold SPL=0 P07 to P00 (AD07 to AD00) Input unavailable/ P17 to P10 (AD15 to AD08) Outputs Hi-Z Shuts off input/ Outputs Hi-Z P27 to P20 (A23 to A16) Output state Output state *1, *3 *1,*3 SPL=1 At the time of internal ROM At the time of access after reset canceling reset At the time of internal ROM access after accessing external ROM Input unavailable/ Outputs Hi-Z Outputs Hi-Z/ Outputs Hi-Z/ Input available Input available Input unavailable/ Outputs Hi-Z Output state*1 Keeps the previous address *3 P37(CLK) P36(RDY) P35(HAK) Input unavailable/ Output available*2,*3 Keeps the previous state*4 Input unavailable/ Output state Input unavailable/ Output available*2,*3 *1, *3 Shuts off input/ Keeps the previous state*4 Shuts off input/ Outputs Hi-Z *5 Input unavailable/ Outputs Hi-Z*3 Inputs "1"*3 P33(WRH) Input unavailable/ Outputs Hi-Z Outputs "H"*3 Outputs "H"*3 *3 P31(RD) Outputs "H" Outputs "H" P30(ALE) Outputs "L" Outputs "L" P47 to P40, P57 to P50, P67 to P60, P87 to P80, P97 to P90, PA1, PA0 P77 to P70 PA0, P42, P32, P12, P82 to P80, P84*6 CM44-10148-4E Outputs Hi-Z/ Outputs Hi-Z/ Input available Input available Outputs "L"*3 P34(HRQ) P32(WRL) Input unavailable/ Output Hi-Z/ Keeps the previous state*4 Keeps the previous state*4 Input unavailable/ Outputs Hi-Z Outputs "H" Outputs "H" Outputs "H" Outputs "L" Outputs "L" Outputs "L" Keeps the previous state*4 Input unavailable/ Outputs Hi-Z Outputs Hi-Z/ Outputs Hi-Z/ Input available Input available Input available FUJITSU MICROELECTRONICS LIMITED 169 CHAPTER 7 LOW-POWER CONSUMPTION MODE 7.7 MB90950 Series *1: "Output state" means that the fixed value of "H" level or "L" level will be output because the internal circuit stops operating while the pin-driving transistor is allowed to drive. If the output function is being used while internal peripheral circuits are operating, the output fluctuates except at the time of reset. (There is no output fluctuation at the time of reset.) *2: "Output available" means that operation data will be output to pins because the internal circuit operation is allowed and the pindriving transistor is driving. *3: If it is used as an output port, the value just previously output will be kept. *4: If the state immediately before transiting to a standby mode is output or input as is, this means "Input unavailable". This means that if an outputting peripheral function is operating, output is obtained according to the state of the peripheral function, and if output is obtained from an output pin, the output will be retained. "Input unavailable" means that the pin data cannot be accepted internally because the internal circuit is stopped while the operation of input gate at the pin is allowed. *5: During shut-off state, input is masked, and the "L" level will be sent inwardly if CMOS/Automotive is selected and the "H" level will be sent inwardly if TTL is selected. "Outputs Hi-Z" means that the pin-driving transistor is prohibited from driving, and the pin is switched to high impedance state. *6:Can be input in the stop mode when the INTxR bit in external interrupt source selection register EISSR is "1". If the bit is "0", the state transits to the same one as other pins. Note: During the stop mode, watch mode, or time-base timer mode, in order to set the pin sharing a port with peripheral functions to high impedance state, after prohibiting the output by peripheral functions, set the STP bit to "1" or TMD bit to "0" in the low-power consumption mode control register (LPMCR). 170 FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 7 LOW-POWER CONSUMPTION MODE 7.7 MB90950 Series ■ Input/Output Pin State (8-bit Access Mode) Table 7.7-3 Input/output Pin State (8-bit Access Mode) During stop/watch/ time-base timer Pin name During sleep During hold SPL=0 P07 to P00 (AD07 to AD00) P17 to P10 (AD15 to AD08) P27 to P20 (A23 to A16) SPL=1 Shuts off input/Outputs Hi-Z Input unavailable/ Outputs Hi-Z Output state Output state *1, *3 *1, *3 Input unavailable/ Outputs Hi-Z Input unavailable/ Outputs Hi-Z At the time of internal ROM At the time of access after reset canceling reset At the time of internal ROM access after accessing external ROM Outputs Hi-Z/ Outputs Hi-Z/ Input available Input available Output state*1 Keeps the previous address *3 P37(CLK) Input unavailable/ Output available *2,*3 Input unavailable/ Output state Input unavailable/ Output available*2, *3 *1, *3 Input unavailable/ Outputs Hi-Z P36(RDY) P35(HAK) P34(HRQ) Keeps the previous state*4 Shuts off input/Keeps the previous state*4 *5 *3 Outputs Hi-Z/ Outputs Hi-Z/ Input available Input available Outputs "L"*3 Inputs "1"*3 Keeps the previous state*4 P33 (WRH) P32 (WR) Shuts off input/ Outputs Hi-Z Input unavailable/ Outputs Hi-Z Outputs "H"*3 Outputs "H"*3 Input unavailable/ Outputs Hi-Z *3 P31 (RD) Outputs "H" Outputs "H" P30 (ALE) Outputs "L" Outputs "L" P47 to P40, P57 to P50, P67 to P60, P87 to P80, P97 to P90, PA1, PA0 P77 to P70 PA0, P42, P32, P12, P82 to P80, P84*6 CM44-10148-4E Keeps the previous state*4 Shuts off input/ Keeps the previous state*4 Input unavailable/ Outputs Hi-Z Outputs "H" Outputs "H" Outputs "H" Outputs "L" Outputs "L" Outputs "L" Keeps the previous state*4 Input unavailable/ Outputs Hi-Z Outputs Hi-Z/ Outputs Hi-Z/ Input available Input available Input available FUJITSU MICROELECTRONICS LIMITED 171 CHAPTER 7 LOW-POWER CONSUMPTION MODE 7.7 MB90950 Series *1: "Output state" means that the fixed value of "H" level or "L" level will be output because the internal circuit stops operating while the pin-driving transistor is allowed to drive. If the output function is being used while internal peripheral circuits are operating, the output fluctuates except at the time of reset. (There is no output fluctuation at the time of reset.) *2: "Output available" means that operation data will be output to pins because the internal circuit operation is allowed and the pindriving transistor is driving. *3: If it is used as an output port, the value just previously output will be kept. *4: If the state immediately before transiting to a standby mode is output or input as is, this means "Input unavailable". This means that if an outputting peripheral function is operating, output is obtained according to the state of the peripheral function, and if output is obtained from an output pin, the output will be retained. "Input unavailable" means that the pin data cannot be accepted internally because the internal circuit is stopped while the operation of input gate at the pin is allowed. *5: During shut-off state, input is masked, and the "L" level will be sent inwardly if CMOS/Automotive is selected and the "H" level will be sent inwardly if TTL is selected. "Outputs Hi-Z" means that the pin-driving transistor is prohibited from driving, and the pin is switched to high impedance state. *6: Can be input in the stop mode when the INTxR bit in external interrupt source selection register EISSR is "1". If the bit is "0", the state transits to the same one as other pins. Note: During the stop mode, watch mode, or time-base timer mode, in order to set the pin sharing a port with peripheral functions to high impedance state, after prohibiting the output by peripheral functions, set the STP bit to "1" or TMD bit to "0" in the low-power consumption mode control register (LPMCR). 172 FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 7 LOW-POWER CONSUMPTION MODE 7.8 MB90950 Series 7.8 Notes on Using the Low-power Consumption Mode Take notice of the following points when using the low-power consumption mode. ■ Switching to the Standby Mode Even if "0" is set to the TMD bit or "1" is set to the STP and SLP bits of the low-power consumption mode control register (LPMCR) while peripheral functions generate interrupt requests to the CPU, the modes do not switch to their standby modes (do not switch even after finishing interrupt processing). While the CPU is processing interrupts, the interrupt request flags being processed will be cleared, and the mode is ready to switch to the standby mode unless other interrupt requests exist. ■ Notes on Switching to the Standby Mode Follow the procedure below to change the pin that shares a port with other peripheral functions to high impedance state during the stop mode, watch mode, or time-base timer mode. 1) Prohibit output by peripheral functions. 2) Set the SPL bit to "1", STP bit to "1", or TMD bit to "0" in the low-power consumption mode control register (LPMCR). ■ Canceling by the Interrupt of Standby Mode During the sleep mode, watch mode, time-base timer mode, or stop mode, if an interrupt request with interrupt level (IL) higher than seven is generated by the operating peripheral functions and an external interrupt, the standby mode will be canceled. Canceling of the standby mode by an interrupt is independent of whether the CPU accepts the interrupt or not. Note: If you do not want to branch to interrupt processing after the returning from the standby mode, take measures such as prohibiting an interrupt before setting the standby mode. ■ Notes on Canceling the Standby Mode Before entering into the stop mode, the standby mode can be canceled by inputting according to the settings of input source of external interrupt. "H" level, "L" level, rising edge, and falling edge are available for the input source. ■ Oscillation Stabilization Wait Time ● Main clock oscillation stabilization wait time Because the main clock oscillation is stopped during the sub clock mode, watch mode, and stop mode, a main clock oscillation stabilization wait time has to be secured. The WS1 and WS0 bits in the clock selection register (CKSCR) set the oscillation stabilization wait time. CM44-10148-4E FUJITSU MICROELECTRONICS LIMITED 173 CHAPTER 7 LOW-POWER CONSUMPTION MODE 7.8 MB90950 Series ● Sub clock oscillation stabilization wait time Because the sub clock (SCLK) oscillation is stopped during the sub stop mode, a sub clock oscillation stabilization wait time has to be secured. The oscillation stabilization wait time is fixed at 214/SCLK (SCLK: Sub clock). ● PLL clock oscillation stabilization wait time During the main clock mode, because the PLL multiplier circuit is stopped, a PLL clock oscillation stabilization wait time has to be secured when switching to the PLL clock mode. During the PLL clock oscillation stabilization wait time, the main clock operates. At the time the mode is switched from the main clock mode to PLL clock mode, the PLL clock oscillation stabilization wait time is fixed at 214/HCLK (HCLK: oscillation clock). During the sub clock mode, a main clock oscillation stabilization wait time and PLL clock oscillation stabilization wait time have to be secured when switching to the PLL clock mode because the main clock and PLL multiplier circuits are stopped. The oscillation stabilization wait time in this case bases upon the values set in the oscillation stabilization wait time selection bits in the clock selection register (CKSCR:WS1, WS0), and the main clock oscillation stabilization wait time and PLL clock oscillation stabilization wait time will be counted together. Therefore, set a value to the "CKSCR:WS1, WS0" bits in line with the longest one of the oscillation stabilization wait times. However, because 214/HCLK or more is needed for the PLL clock oscillation stabilization wait time, set "10B" or "11B" to the "CKSCR: WS1, WS0" bits. During the PLL stop mode, a main clock oscillation stabilization wait time and PLL clock oscillation stabilization wait time have to be secured when returning from the PLL stop mode because the main clock and PLL multiplier circuits are stopped. The oscillation stabilization wait time in this case bases upon the values set in the oscillation stabilization wait time selection bits in the clock selection register (CKSCR:WS1, WS0), and the main clock oscillation stabilization wait time and PLL clock oscillation stabilization wait time will be counted together. Therefore, set a value to the "CKSCR:WS1, WS0" bits in line with the longest one of the oscillation stabilization wait times. However, because 214/HCLK or more is needed for the PLL clock oscillation stabilization wait time, set "10B" or "11B" to the "CKSCR: WS1, WS0" bits. ■ Clock Mode Switch When the clock mode has been switched, do not again switch to the low-power consumption mode or other clock modes before the switching completes. The completion of switching can be checked by referring to the MCM bit and SCM bit in the clock selection register (CKSCR). If a mode is switched again to other clock modes or the low-power consumption mode before the first switching is finished, the second switching may not complete. ■ Notes on Accessing the Low-power Consumption Mode Control Register (LPMCR) for Switching to the Standby Mode ● When accessing the low-power consumption mode control register (LPMCR) using an assemble language Use the instructions in Table 7.3-2 to configure the settings for switching to the standby mode in the lowpower consumption mode control register (LPMCR). 174 FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E MB90950 Series CHAPTER 7 LOW-POWER CONSUMPTION MODE 7.8 Immediately after using the standby mode transition instructions in Table 7.3-2, be sure to add the instructions shown in the dotted square below. MOV LPMCR, #H’xx ; Low-power consumption mode transition instruction in Table 7.3-2 NOP NOP JMP $+3 ; Jump to next instruction MOV A, #H’10 ; Any instruction If instruction lines other than shown in the dotted square are added, operations after canceling the standby mode will not be assured. ● When accessing the low-power consumption mode control register (LPMCR) using C language Use one of the following instructions 1 to 3 to configure the settings for switching to the standby mode in the low-power consumption mode control register (LPMCR). 1. Prepare a function for the instruction to be switched to the standby mode, and insert two "__wait_nop()" built-in functions behind the standby mode transition instruction. If there is a possibility that an interrupt except a standby returning interrupt may occur within the function, optimize the program while compiling to prevent the occurrence of LINK/UNLINK instructions. Example (Transition function to the watch mode or time-base timer mode) void enter_watch(){ IO_LPMCR.byte = 0x10; /* Set the TMD bit of LPMCR to 0 */ __wait_nop(); __wait_nop(); } 2. Write an instruction to switch to the standby mode using the "__asm" statement, and insert two NOP and a JMP instructions behind the standby mode transition instruction. Example (Transition to the sleep mode) __asm( " MOV I:_IO_LPMCR, #H’58); /* Set 1 to the SLP bit of LPMCR */ __asm( " NOP"); __asm( " NOP"); __asm( " JMP $+3"); /* Jump to next instruction */ 3. Write an instruction to switch to the standby mode between "#pragma asm" and "#pragma endasm", and insert two NOP and a JMP instructions behind the standby mode transition instruction. Example (Transition to the stop mode) #pragma asm MOV I:_IO_LPMCR, #H’98 /* Set 1 to the STP bit of LPMCR */ NOP NOP JMP $+3 /* Jump to next instruction */ #pragma endasm CM44-10148-4E FUJITSU MICROELECTRONICS LIMITED 175 CHAPTER 7 LOW-POWER CONSUMPTION MODE 7.8 176 FUJITSU MICROELECTRONICS LIMITED MB90950 Series CM44-10148-4E CHAPTER 8 MEMORY ACCESS MODE This chapter explains the functions and operations of the memory access mode. 8.1 Overview of the Memory Access Mode 8.2 External Memory Access (Bus Pin Control Circuit) 8.3 External Memory Access Control Signal Operations CM44-10148-4E FUJITSU MICROELECTRONICS LIMITED 177 CHAPTER 8 MEMORY ACCESS MODE 8.1 8.1 MB90950 Series Overview of the Memory Access Mode F2MC-16LX has several modes for access methods and access areas. ■ Overview of the Memory Access Mode Table 8.1-1 Mode Pins and Their Modes Operation mode Bus mode Access mode − Single chip 8-bit Internal ROM external bus RUN 16-bit 8-bit External ROM external bus 16-bit Flash programming − − ● Operation mode Operation mode refers to a mode that controls the operation states of devices. It is specified by the MD2 to MD0 mode setting pin and the Mx bit in mode data. Selecting an operation mode allows to start a normal operations or write to a flash memory. ● Bus mode Bus mode refers to a mode that controls the operations of internal ROM and external access functions. It is specified by the mode setting pins (MD2 to MD0) and the Mx bit in mode data. The mode setting pins (MD2 to MD0) specifies the bus mode when it reads reset vectors and mode data, and the Mx bit in mode data specifies the bus mode in normal operations. ● Access mode Access mode refers to a mode that controls external data bus widths. It is specified by the MD2 to MD0 mode setting pin and the S0 bit in mode data. Selecting an access mode specifies the length of external data bus, either 8-bit or 16-bit. 178 FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 8 MEMORY ACCESS MODE 8.1 MB90950 Series 8.1.1 Mode Pin By combining the three external pins MD2 to MD0, the operations shown in Table 8.1-2 can be specified. ■ Mode Pin Table 8.1-2 Mode Pins and Their Modes Mode pin setting Mode name Reset vector access area External data bus width MD2 MD1 MD0 0 0 0 External vector mode 0 External 8-bit 0 0 1 External vector mode 1 External 16-bit 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 Flash serial writing* − − 1 1 1 Flash memory − − Remarks Reset vector 16-bit bus width access Specification not allowed Internal vector mode Internal (Mode data) Mode data will control after reset sequence Specification not allowed Mode when using parallel writer *: Serial writing to a flash memory cannot be done by the mode pin settings alone. Other pin settings are required. See "CHAPTER 25 EXAMPLES OF SERIAL PROGRAMMING CONNECTION FOR FLASH MEMORY PRODUCTS" for details. CM44-10148-4E FUJITSU MICROELECTRONICS LIMITED 179 CHAPTER 8 MEMORY ACCESS MODE 8.1 8.1.2 MB90950 Series Mode Data Mode data is stored in FFFFDFH of the main memory and used to control CPU operations. During the reset sequence, this data is fetched in the mode register in the device. It is the reset sequence only that can change the mode register values. The settings by this register will be enabled after the reset sequence. Be sure to set "0" to the reserved bit. ■ Mode Data Figure 8.1-1 Configuration of Mode Data bit Address: FFFFDFH 7 M1 6 5 4 M0 Reserved Reserved 3 2 1 0 S0 Reserved Reserved Reserved [bit7, bit6] M1, M0 (Bus mode setting bits) M1 and M0 are the bits that specify the operation mode after the reset sequence. The relationship between the M1 and M0 bits and their functions is shown in Table 8.1-3. Table 8.1-3 Functions of M1 and M0 (Bus Mode Setting Bits) M1 M0 Function 0 0 Single chip mode 0 1 Internal ROM - external bus mode 1 0 External ROM - external bus mode 1 1 Setting not allowed Remarks [bit3] S0 (Mode setting bit) S0 is the bit to specify the bus mode and access mode after the reset sequence. The relationship between the S0 bit and its functions is shown in Table 8.1-4. Table 8.1-4 Functions of S0 (Mode Setting Bit) S0 180 Function 0 External data bus 8-bit mode 1 External data bus 16-bit mode FUJITSU MICROELECTRONICS LIMITED Remarks CM44-10148-4E CHAPTER 8 MEMORY ACCESS MODE 8.1 MB90950 Series 8.1.3 Memory Space by Bus Mode Figure 8.1-2 shows the correspondence between access areas and their physical addresses specified by bus modes. ■ Memory Space by Bus Mode Figure 8.1-2 Relationship between Access Areas and their Physical Addresses Specified by Bus Modes FFFFFFH ROM area ROM area main main Address#1 F78000H ROM area satellite ROM area satellite ROM mirror area ROM mirror area Extended I/O area Extended I/O area F70000H 010000H 008000H Extended I/O area 007900H Address#2 RAM 000100H 0000F0H 000000H Generalpurpose register RAM Generalpurpose register RAM Generalpurpose register I/O I/O I/O Single chip Internal ROM external bus External ROM internal bus Product type : Internal : External : Access not allowed Address #1 Address #2 MB90F952 FC0000H 004000H MB90V950AJAS, MB90V950AMAS F80000H 007900H CM44-10148-4E FUJITSU MICROELECTRONICS LIMITED 181 CHAPTER 8 MEMORY ACCESS MODE 8.1 MB90950 Series ■ Recommended Settings Table 8.1-5 shows the recommended setting examples for mode pins and mode data. Table 8.1-5 Recommended Setting Examples for Mode Pins and Mode Data Setting example MD2 MD1 MD0 M1 M0 S0 Single chip 0 1 1 0 0 × Internal ROM external bus mode - 16-bit bus 0 1 1 0 1 1 Internal ROM external bus mode - 8-bit bus 0 1 1 0 1 0 External ROM external bus mode - 16-bit bus - Vector 16-bit bus width 0 0 1 1 0 1 External ROM external bus mode - 8-bit bus 0 0 0 1 0 0 External pins have different signal functions for each mode. Table 8.1-6 External Pin Functions for Each Mode Function Pin name External bus expansion Single chip Flash programming 8-bit P07 to P00 16-bit AD07 to AD00 P17 to P10 A15 to A08 AD15 to AD08 DQ07 to DQ00 AQ15 to AQ08 P27 to P20 A23 to A16* AQ07 to AQ00 P30 ALE AQ16 P31 RD CE P32 P33 Port WR* WRL* OE Port WRH* WE P34 HRQ* AQ17 P35 HAK* AQ18 P36 RDY* BYTE P37 CLK* RY/BY *: The output pins placed in a high address, WRL/WR, WRH, HRQ, HAK, RDY, and CLK pins can be used as a port by specifying a function. See Section "8.2 External Memory Access (Bus Pin Control Circuit)" for details. 182 FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 8 MEMORY ACCESS MODE 8.2 MB90950 Series 8.2 External Memory Access (Bus Pin Control Circuit) The external bus pin control circuit controls the external bus pin to expand the CPU address and data bus outward. ■ External Memory Access (External Bus Pin Control Circuit) Use the address, data, and control signal as shown below to access the external memory / peripherals of this device. • CLK(P37): Machine cycle clock (KBP) output pin • RDY(P36): External ready input pin • WRH(P33): Write strobe signal for the upper 8-bit of data bus. It operates only in the 16-bit bus mode. • WRL/WR(P32): In 16-bit bus mode, it functions as a write strobe signal for the lower 8-bit of data bus. In 8-bit bus mode, it functions as a write strobe signal. • RD(P31): Read strobe signal • ALE(P30): Address latch enable signal The external bus pin control circuit controls the external bus pin and allows the CPU address and data bus to expand outward. ■ Block Diagram of External Memory Access Figure 8.2-1 External Bus Controller P0 P1 P2 P3 P0 data P3 P0 P0 direction RB Data control Address control Access control CM44-10148-4E Access control FUJITSU MICROELECTRONICS LIMITED 183 CHAPTER 8 MEMORY ACCESS MODE 8.2 8.2.1 MB90950 Series Register for External Memory Access (External Bus Pin Control Circuit) There are three types of register for external memory access (external bus pin control circuit). • Auto ready selection register • External address output control register • Bus control signal selection register ■ List of Registers for External Memory Access Figure 8.2-2 List of Registers for External Memory Access (External Bus Pin Control Circuit) Auto ready selection register bit 15 14 13 12 11 10 9 8 IOR1 IOR0 HMR1 HMR0 − − Read/write → (W) (W) (W) (W) (−) (−) (W) (W) Initial value → (0) (0) (1) (1) (1) (1) (0) (0) Address: 0000A5H LMR1 LMR0 ARSR External address output control register bit Address: 0000A6H 7 6 5 4 3 2 1 0 E23 E22 E21 E20 E19 E18 E17 E16 Read/write → (W) (W) (W) (W) (W) (W) (W) (W) Initial value → (0) (0) (0) (0) (0) (0) (0) (0) 12 11 10 9 8 HACR Bus control signal selection register bit Address: 0000A7H 15 14 13 CKE RYE HDE IOBS HMBS WRE LMBS − Read/write → (W) (W) (W) (W) (W) (W) (W) (−) Initial value → (0) (0) (0) (0) (0) (0) (0) (1) ECSR W: Write only 184 FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 8 MEMORY ACCESS MODE 8.2 MB90950 Series 8.2.2 Auto Ready Selection Register (ARSR) Auto ready selection register (ARSR) sets an auto wait time of memory access for each area when externally accessing. ■ Auto Ready Selection Register (ARSR) Figure 8.2-3 Configuration of Auto Ready Selection Register Auto ready selection register bit Address: 0000A5H 15 14 13 12 IOR1 IOR0 HMR1 HMR0 11 10 − − 9 8 LMR1 LMR0 Read/write → (W) (W) (W) (W) (−) (−) (W) (W) Initial value → (0) (0) (1) (1) (1) (1) (0) (0) ARSR W: Write only [bit15, bit14] IOR1, IOR0 The IOR1 and IOR0 bits specify the auto wait function when the 0000F0H to 0000FFH area is accessed externally. The combination of IOR1 and IOR0 bits configures the settings as shown in Table 8.2-1. Table 8.2-1 Functions of IOR1 and IOR0 (Auto Wait Function Specification Bit) IOR1 IOR0 Function 0 0 Auto wait prohibited [Initial value] 0 1 Auto wait of 1 cycle is inserted during external access 1 0 Auto wait of 2 cycles is inserted during external access 1 1 Auto wait of 3 cycles is inserted during external access [bit13, bit12] HMR1, HMR0 The HMR1 and HMR0 specify the auto wait function when the 800000H to FFFFFFH area is accessed externally. The combination of HMR1 and HMR0 bits configures the settings as shown in Table 8.2-2. Table 8.2-2 Functions of HMR1 and HMR0 (Auto Wait Function Specification Bit) CM44-10148-4E HMR1 HMR0 Function 0 0 Auto wait prohibited 0 1 Auto wait of 1 cycle is inserted during external access 1 0 Auto wait of 2 cycles is inserted during external access 1 1 Auto wait of 3 cycles is inserted during external access [Initial value] FUJITSU MICROELECTRONICS LIMITED 185 CHAPTER 8 MEMORY ACCESS MODE 8.2 MB90950 Series [bit9, bit8] LMR1, LMR0 The LMR1 and LMR0 specify the auto wait function when the 008000H to 7FFFFFH area is accessed externally. The combination of LMR1 and LMR0 bits configures the settings as shown in Table 8.2-3. Table 8.2-3 Functions of LMR1 and LMR0 (Auto Wait Function Specification Bit) 186 LMR1 LMR0 Function 0 0 Auto wait prohibited [Initial value] 0 1 Auto wait of 1 cycle is inserted during external access 1 0 Auto wait of 2 cycles is inserted during external access 1 1 Auto wait of 3 cycles is inserted during external access FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 8 MEMORY ACCESS MODE 8.2 MB90950 Series 8.2.3 External Address Output Control Register (HACR) The external address output control register (HACR) is a register to control the external output by the addresses (A23 to A16). Each bit corresponds to the address A23 to A16 and controls each address output pin as shown in Figure 8.2-4. All bits of this register are write-only. "1" will be used for read. ■ External Address Output Control Register (HACR) Figure 8.2-4 Configuration of External Address Output Control Register External address output control register bit Address: 0000A6H 7 6 5 4 3 2 1 0 E23 E22 E21 E20 E19 E18 E17 E16 Read/write → (W) (W) (W) (W) (W) (W) (W) (W) Initial value → (0) (0) (0) (0) (0) (0) (0) (0) HACR W: Write only The HACR register controls the output for the addresses (A23 to A16) that lead to external circuits. The eight bits correspond to the addresses A23 to A16 and control the address output pin as shown below. The HACR register cannot access when the device is in the single chip mode. In this case, all pins function as I/O ports regardless of the values in this register. All bits of this register are write-only. "1" will be used for read. Table 8.2-4 Functions of External Address Output Control Register (E23 to E16 Bit) CM44-10148-4E 0 Pins correspond to address outputs (AXX). [Initial value] 1 Pins correspond to I/O port (P2X). Set this bit to "1" if it is used as a peripheral resource. FUJITSU MICROELECTRONICS LIMITED 187 CHAPTER 8 MEMORY ACCESS MODE 8.2 8.2.4 MB90950 Series Bus Control Signal Selection Register (ECSR) Bus control signal selection register (ECSR) is a register to set the control functions of bus operations in the external bus mode. It cannot access when the device is in the single chip mode. In this case, all pins function as I/O ports regardless of the values in this register. All bits of bus control signal selection register are write-only. "1" will be used for read. ■ Bus Control Signal Selection Register (ECSR) Figure 8.2-5 Configuration of Bus Control Signal Selection Register Bus control signal selection register bit Address: 0000A7H 15 14 13 CKE RYE HDE IOBS HMBS WRE LMBS 12 11 10 9 8 − Read/write → (W) (W) (W) (W) (W) (W) (W) (−) Initial value → (0) (0) (0) (0) (0) (0) (0) (1) ECSR W: Write only [bit15] CKE The CKE bit controls the output of external clock signal pin (CLK) as shown in Table 8.2-5. Table 8.2-5 Functions of CKE (External Clock (CLK) Output Control Bit) 0 I/O port (P37) operation (Clock output prohibited) [Initial value] 1 Clock signal (CLK) output allowed [bit14] RYE The RYE bit controls the input of external ready (RDY) signal pin as shown in Table 8.2-6. Table 8.2-6 Functions of RYE (External Ready (RDY) Input Control Bit) 0 I/O port (P36) operation (External RDY input prohibited) [Initial value] 1 External ready (RDY) input allowed [bit13] HDE The HDE bit specifies the input/output allowance for hold-related signals. The settings of HDE bit will control the hold request input signal (HRQ) and hold acknowledgment output signal (HAK) as shown in Table 8.2-7. 188 FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 8 MEMORY ACCESS MODE 8.2 MB90950 Series Table 8.2-7 Functions of HDE (Input/Output Allowance Specification Bit for Hold-related Pin) 0 I/O port (P35, P34) operation (Hold function input/output prohibited) [Initial value] 1 Hold request (HRQ) input/Hold acknowledgment (HAK) output allowance [bit12] IOBS The IOBS bit specifies the bus width when the area 0000F0H to 0000FFH is externally accessed during the external data bus 16-bit mode. Table 8.2-8 shows the control by the setting of this bit. Table 8.2-8 IOBS (Bus Width Specification Bit) 0 16-bit bus width access [Initial value] 1 8-bit bus width access [bit11] HMBS The HMBS bit specifies the bus width when the area 800000H to FFFFFFH is externally accessed during the external data bus 16-bit mode. Table 8.2-9 shows the control by the setting of this bit. Table 8.2-9 Functions of HMBS (Bus Width Specification Bit) 0 16-bit bus width access [Initial value] 1 8-bit bus width access [bit10] WRE The WRE bit controls the output of external write signal (both WRH and WRL pins, in the case of external data bus 16-bit mode, and WR pin, in the case of external data bus 8-bit mode) as shown in Table 8.2-10. When in the external data bus 8-bit mode, P33 functions as an I/O port, regardless of the value set in this bit. Table 8.2-10 Functions of WRE (External Write Signal Output Control Bit) CM44-10148-4E 0 I/O port (P33, P32) operation (Write signal output prohibited) [Initial value] 1 Write strobe signal (both WRH and WRL, or WR only) allowed to output FUJITSU MICROELECTRONICS LIMITED 189 CHAPTER 8 MEMORY ACCESS MODE 8.2 MB90950 Series [bit9] LMBS The LMBS bit specifies the bus width when the area 002000H to 7FFFFFH is externally accessed during the external data bus 16-bit mode. Table 8.2-11 shows the control by the setting of this bit. Table 8.2-11 Functions of LMBS (Bus Width Specification Bit) 0 16-bit bus width access [Initial value] 1 8-bit bus width access Notes: • When in the external data bus 16-bit mode, switch P33 and P32 to an input mode if the WR, WRH, and WRL functions are allowed with the WRE bit (Set the bit3 and bit2 in DDR3 register to "0"). • When in the external data bus 8-bit mode, switch P32 to an input mode if the WR function is allowed with the WRE bit (Set the bit2 in DDR3 register to "0"). • Even if RDY and HRQ signal input is allowed with the RYE and HDE bits, the I/O port function of this port will be enabled. Therefore, be sure to write "0" (input mode) in the DDR3 register that corresponds to the port. 190 FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 8 MEMORY ACCESS MODE 8.3 MB90950 Series 8.3 External Memory Access Control Signal Operations External memory will be accessed in three cycles if the ready function is not used. The 8-bit bus width access in the external 16-bit bus mode is a function to read from and writes to peripheral chips with 8-bit width when peripheral chips with 8-bit width and 16bit width are connected to an external bus in a mixed manner. ■ External Memory Access Control Signal The HMBS/LMBS/IOBS bits in ECSR register specify whether the 16-bit bus width access or the 8-bit bus width access will be performed in the external data bus 16-bit mode. Note that bus operations may not actually be performed by only outputting addresses and ALE signal asserts, and by not asserting RD/WRL/WRH/WR. Be careful not to perform access to peripheral chips using ALE signal only. Figure 8.3-1 Access Timing Chart in the External Data Bus 8-bit Mode Read Write Read P37/CLK P33/WRH (Port data) P32/WRL/WR P31/RD P30/ALE P27 to P20/ A23 to AD16 P17 to P10/ A15 to AD08 P07 to P00/ AD07 AD00 Read address Write address Read address Read address Write address Read address Read address Write address Read data CM44-10148-4E FUJITSU MICROELECTRONICS LIMITED Read address Write data 191 CHAPTER 8 MEMORY ACCESS MODE 8.3 MB90950 Series Figure 8.3-2 Access Timing Chart in the External Data Bus 16-bit Mode (16-bit Bus Width Access) 8-bit bus width byte read Even number address byte read 8-bit bus width byte write Even number address byte write P37/CLK P33/WRH P32/WRL/WR P31/RD P30/ALE Read address P27 to P20/A23 to A16 P17 to P10/AD15 to AD08 Read address P07 to P00/AD07 to AD00 Read address Write address Disabled (Undefined) Write address Write address Read data Odd number address byte read Read address Read address Read address Write data Odd number address byte write P37/CLK P33/WRH P32/WRL/WR P31/RD P30/ALE Read address P27 to P20/A23 to A16 P17 to P10/AD15 to AD08 Read address P07 to P00/AD07 to AD00 Read address Write address Write address Disabled Read address (Undefined) Write address Read address Write data Read data Even number address word read Read address Even number address word write P37/CLK P33/WRH P32/WRL/WR P31/RD P30/ALE Read address P27 to 20/A23 to A16 Write address P17 to 10/AD15 to AD08 Read address Write address Read address P07 to 00/AD07 to AD00 Read address Write address Read address Read data Note: 192 Read address Write data Set external circuits to consistently read in units of words. The settings in the P36/RDY pin and the auto ready selection register (ARSR) will allow the access to low speed memory or peripheral circuits. FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 8 MEMORY ACCESS MODE 8.3 MB90950 Series 8.3.1 Ready Function The settings in the P36/RDY pin and the auto ready selection register (ARSR) will allow the access to low speed memory or peripheral circuits. If the RYE bit in the bus control signal selection register (ECSR) is set to "1", the wait cycle will be used while the "L" level is input to the P36/RDY signal during the access to an external circuit, resulting in an extended access cycle. ■ Ready Function Figure 8.3-3 Ready Function Timing Chart Even number address word read Even number address word write P37/CLK P33/WRH P32/WRL/WR P31/RD P30/ALE P27 to P20/A23 to A16 Read address Write address P17 to P10/AD15 to AD08 Read address Write address P07 to P00/AD07 to AD00 Read address Write address P36/RDY Read data RDY pin fetched Even number address word write Write data Even number address word read P37/CLK P33/WRH P32/WRL/WR P31/RD P30/ALE P27 to 20/A23 to A16 Write address Read address P17 to P10/AD15 to AD08 Write address Address P07 to P00/AD07 to AD00 Write address Address Write data Extended cycled by auto ready CM44-10148-4E FUJITSU MICROELECTRONICS LIMITED 193 CHAPTER 8 MEMORY ACCESS MODE 8.3 MB90950 Series MB90950 series has two types of auto ready functions for external memory access. The auto ready function is a function that can extend access cycles by automatically inserting a wait cycle with 1 to 3 cycles without external circuits when an access is generated to lower address external areas located between address 008000H to 7FFFFFH and upper address external areas located between address 800000H to FFFFFFH. This function is enabled to start by the settings in the LMR1/LMR0 bit (lower address external area) of ARSR and the HMR1/HMR0 bit (upper address external area) of ARSR. In addition, MB90950 series has an auto ready function for I/O independently of the one for memory. Setting "0" to the IOR1/IOR0 bit in the ARSR register will extend the access cycle by automatically inserting a wait cycle with 1 to 3 cycles without external circuits during the access to the external area between address 0000F0H to 0000FFH. If the RYE bit of either the external memory auto ready or the external I/O auto ready is set to "1", the wait cycle remains unchanged if the "L" level continues to be input to the P36/RDY pin after the end of wait cycle by the auto ready function described above. 194 FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 8 MEMORY ACCESS MODE 8.3 MB90950 Series 8.3.2 Hold Function If the HDE bit in the bus control signal selection register (ECSR) is set to "1", the external address hold function by the P34/HRQ and P35/HAK pins will be enabled. ■ Hold Function Inputting the "H" level to the P34/HRQ pin will change the state to hold state after CPU instructions are finished (in the case of string instructions, after finishing processing the "1" element data), changing the state of the pins shown below to high impedance state by outputting "L" level signals from the P35/HAK pin. • Address output : P27/A23 to P20/A16 • Data input/output : P17/AD15 to P10/AD08, P07/AD07 to P00/AD00 • Bus control signal : P30/ALE, P31/RD, P32/WRL/WR, P33/WRH This allows the use of external buses through device external circuits. If "L" level signals are input to the P34/HRQ pin, the P35/HAK pin will output "H" level, and the external pin state will be restored, causing buses to operate again. In STOP state, no hold request input will be accepted. Figure 8.3-4 Hold Timing Hold cycle Read cycle Write cycle P37/CLK P34/HRQ P35/HAK P33/WRH P32/WRL/WR P31/RD P30/ALE P27 to P20/A23 to A16 (Address) (Address) P17 to P10/AD15 to AD08 (Address) P07 to P00/AD07 to AD00 (Address) Read data Write data Notes: • If "H" level is input to the P34/HRQ pin, the P34/HRQ pin shall be kept at "H" level until the P35/ HAK pin reaches "L" level. • Even during the period the P35/HAK pin is at "L" level, the watchdog timer continues to operate without its timer being cleared. If the hold state continues longer than the interval time of watchdog timer set at the WT1/WT0 bit in the watchdog timer control register (WDTC), a watchdog reset will occur. CM44-10148-4E FUJITSU MICROELECTRONICS LIMITED 195 CHAPTER 8 MEMORY ACCESS MODE 8.3 196 FUJITSU MICROELECTRONICS LIMITED MB90950 Series CM44-10148-4E CHAPTER 9 I/O PORTS This chapter explains the functions of I/O ports. 9.1 I/O Ports 9.2 Register List for I/O Ports CM44-10148-4E FUJITSU MICROELECTRONICS LIMITED 197 CHAPTER 9 I/O PORTS 9.1 9.1 MB90950 Series I/O Ports Each pin of I/O ports can specify to be an input or output port by setting the port data direction register (DDR), as long as corresponding peripherals are configured not to use the pins. If a pin is specified as an input, the logic level of the pin will be read. If the pin is specified as an output, the data register value will be read. This also applies to the reading of read-modify-write instruction. ■ Overview of I/O Ports If a pin is used to output other peripheral functions, the logic level of the pin will be read regardless of the data register values. In general, prior to setting the port as an output port, we recommend not to use read-modify-write instructions for register setting, and recommend to switch off the output by peripheral functions. This is because read-modify-write instructions will read the logic level of ports, not register values. Figure 9.1-1 shows the block diagram of I/O ports. Figure 9.1-1 Block Diagram of I/O Ports Internal data bus Data register read Data register Pin Data register write Direction register Direction register write Direction register read 198 FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 9 I/O PORTS 9.2 MB90950 Series 9.2 Register List for I/O Ports There are five types of I/O port registers. • Port data register (PDR0 to PDRA) • Port data direction register (DDR0 to DDRA) • Pull-up control register (PUCR0 to PUCR3) • Analog input enabling register (ADER5 to ADER7) • Input level selection register (ILSR0 to ILSR2) ■ Register List for I/O Ports Figure 9.2-1 shows the bit configuration of each register for I/O ports. Figure 9.2-1 Register List for I/O Ports bit Address: 000000H Address: 000001H Address: 000002H Address: 000003H Address: 000004H Address: 000005H Address: 000006H Address: 000007H Address: 000008H Address: 000009H Address: 00000AH bit Address: 000010H Address: 000011H Address: 000012H Address: 000013H Address: 000014H Address: 000015H Address: 000016H Address: 000017H Address: 000018H Address: 000019H Address: 00001AH bit Address: 00001CH Address: 00001DH Address: 00001EH Address: 00001FH bit Address: 00000BH Address: 00000CH Address: 00000DH bit Address: 00000EH Address: 00000FH Address: 0079A0H CM44-10148-4E 7 6 5 4 3 2 1 0 P07 P06 P05 P04 P03 P02 P01 P00 P17 P16 P15 P14 P13 P12 P11 P10 P27 P26 P25 P24 P23 P22 P21 P20 P37 P36 P35 P34 P33 P32 P31 P30 P47 P46 P45 P44 P43 P42 P41 P40 P57 P56 P55 P54 P53 P52 P51 P50 P67 P66 P65 P64 P63 P62 P61 P60 P77 P76 P75 P74 P73 P72 P71 P70 P87 P86 P85 P84 P83 P82 P81 P80 P97 P96 P95 P94 P93 P92 P91 P90 PA1 PA0 7 6 5 4 3 1 0 D07 D06 D05 D04 D03 D02 2 D01 D00 D17 D16 D15 D14 D13 D12 D11 D10 D27 D26 D25 D24 D23 D22 D21 D20 D37 D36 D35 D34 D33 D32 D31 D30 D40 D47 D46 D45 D44 D43 D42 D41 D57 D56 D55 D54 D53 D52 D51 D50 D67 D66 D65 D64 D63 D62 D61 D60 D77 D76 D75 D74 D73 D72 D71 D70 D87 D86 D85 D84 D83 D82 D81 D80 D97 D96 D95 D94 D93 D92 D91 D90 SIL4 SIL3 SIL2 SIL1 SIL0 DA1 DA0 7 6 4 3 1 0 5 2 PU07 PU06 PU05 PU04 PU03 PU02 PU01 PU00 PU17 PU16 PU15 PU14 PU13 PU12 PU11 PU10 PU27 PU26 PU25 PU24 PU23 PU22 PU21 PU20 PU37 PU36 PU35 PU34 PU33 PU32 PU31 PU30 15/7 14/6 13/5 12/4 11/3 10/2 9/1 ADE15 ADE14 ADE13 ADE12 ADE11 ADE10 ADE9 ADE7 ADE6 ADE5 ADE4 ADE3 ADE2 ADE1 Port 0 data direction register (DDR0) Port 1 data direction register (DDR1) Port 2 data direction register (DDR2) Port 3 data direction register (DDR3) Port 4 data direction register (DDR4) Port 5 data direction register (DDR5) Port 6 data direction register (DDR6) Port 7 data direction register (DDR7) Port 8 data direction register (DDR8) Port 9 data direction register (DDR9) Port A data direction register (DDRA) Port 0 Pull-up control register (PUCR0) Port 1 Pull-up control register (PUCR1) Port 2 Pull-up control register (PUCR2) Port 3 Pull-up control register (PUCR3) 8/0 ADE8 Port 5 Analog input enabling register (ADER5) ADE0 Port 6 Analog input enabling register (ADER6) ADE23 ADE22 ADE21 ADE20 ADE19 ADE18 ADE17 ADE16 9/1 Port 0 data register (PDR0) Port 1 data register (PDR1) Port 2 data register (PDR2) Port 3 data register (PDR3) Port 4 data register (PDR4) Port 5 data register (PDR5) Port 6 data register (PDR6) Port 7 data register (PDR7) Port 8 data register (PDR8) Port 9 data register (PDR9) Port A data register (PDRA) 15/7 14/6 13/5 12/4 11/3 10/2 IL7 IL6 IL5 IL4 IL3 IL2 IL1 IL0 ILT3 ILT2 ILT1 ILT0 ILA IL9 IL8 SIL5 SIL6 Port 7 Analog input enabling register (ADER7) 8/0 Input level selection register (ILSR0) Input level selection register (ILSR1) Input level selection register (ILSR2) FUJITSU MICROELECTRONICS LIMITED 199 CHAPTER 9 I/O PORTS 9.2 9.2.1 MB90950 Series Port Data Register (PDR0 to PDRA) The R/W of I/O port operate differently from those of memory, as described below. • Input mode When reading : Corresponding pin levels will be read. When writing : Written to the latch for output. • Output mode When reading : The value of data register latch will be read. When writing : Written to the latch for output, and output to the corresponding pin. Figure 9.2-2 shows the details of bit configuration for the port data register (PDR). ■ Port Data Register (PDR) Figure 9.2-2 Port Data Register (PDR) bit PDR0 Address: 000000H 7 6 5 4 3 2 1 0 Initial value Access P07 P06 P05 P04 P03 P02 P01 P00 XXXXXXXXB R/W 6 5 4 3 2 1 0 P16 P15 P14 P13 P12 P11 P10 XXXXXXXXB R/W XXXXXXXXB R/W XXXXXXXXB R/W XXXXXXXXB R/W XXXXXXXXB R/W XXXXXXXXB R/W XXXXXXXXB R/W XXXXXXXXB R/W XXXXXXXXB R/W 111111XXB R/W 7 bit PDR1 P17 Address: 000001H bit 7 PDR2 P27 Address: 000002H bit 7 PDR3 P37 Address: 000003H bit 7 PDR4 P47 Address: 000004H bit 7 PDR5 P57 Address: 000005H bit 7 PDR6 P67 Address: 000006H bit 7 PDR7 P77 Address: 000007H bit 7 PDR8 P87 Address: 000008H 7 bit PDR9 P97 Address: 000009H bit PDRA Address: 00000AH 200 7 6 5 4 3 2 1 0 P26 P25 P24 P23 P22 P21 P20 6 5 4 3 2 1 0 P36 P35 P34 P33 P32 P31 P30 6 5 4 3 2 1 0 P46 P45 P44 P43 P42 P41 P40 6 5 4 3 2 1 0 P56 P55 P54 P53 P52 P51 P50 6 5 4 3 2 1 0 P66 P65 P64 P63 P62 P61 P60 6 5 4 3 2 1 0 P76 P75 P74 P73 P72 P71 P70 6 5 4 3 2 1 0 P86 P85 P84 P83 P82 P81 P80 6 5 4 3 2 1 0 P96 P95 P94 P93 P92 P91 P90 6 5 4 3 2 1 0 PA1 PA0 FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 9 I/O PORTS 9.2 MB90950 Series ■ Reading of the Port Data Register The value obtained at the time of reading the port data register (PDR) depends on the state of port data direction register (DDR) and the state of peripheral functions connected to the pins. The values obtained for each combination are shown below. DDR value Output state of peripheral functions Read value 0 (input) Enabled Output value from peripheral functions 1 (output) Enabled Output value from peripheral functions 0 (input) Disabled Pin state 1 (output) Disabled Value of output latch Set the DDR of connected pin to 0 (input), when it is used as an input in peripheral functions. CM44-10148-4E FUJITSU MICROELECTRONICS LIMITED 201 CHAPTER 9 I/O PORTS 9.2 9.2.2 MB90950 Series Port Data Direction Register (DDR0 to DDRA) The port data direction register has the following functions. • Sets the data direction for the pin used as a port. • Sets the input level of the SIN (Serial input of LIN-UART) pin. ■ Port Data Direction Register (DDR0 to DDRA) Figure 9.2-3 shows the details of bit configuration for the port data direction register (DDR0 to DDRA). Figure 9.2-3 Port Data Direction Register (DDR0 to DDRA) bit DDR0 Address: 000010H 7 6 5 4 3 2 1 0 D07 D06 D05 D04 D03 D02 D01 D00 bit 7 DDR1 D17 Address: 000011H bit 7 DDR2 D27 Address: 000012H bit 7 DDR3 D37 Address: 000013H bit 7 DDR4 D47 Address: 000014H bit 7 DDR5 D57 Address: 000015H bit 7 DDR6 D67 Address: 000016H bit 7 DDR7 D77 Address: 000017H bit 7 DDR8 D87 Address: 000018H bit 7 DDR9 D97 Address: 000019H 6 5 4 3 2 1 0 D16 D15 D14 D13 D12 D11 D10 6 5 4 3 2 1 0 D26 D25 D24 D23 D22 D21 D20 6 5 4 3 2 1 0 D36 D35 D34 D33 D32 D31 D30 6 5 4 3 2 1 0 D46 D45 D44 D43 D42 D41 D40 6 5 4 3 2 1 0 D56 D55 D54 D53 D52 D51 D50 6 5 4 3 2 1 0 D66 D65 D64 D63 D62 D61 D60 6 5 4 3 2 1 0 D76 D75 D74 D73 D72 D71 D70 6 5 4 3 2 1 0 D86 D85 D84 D83 D82 D81 D80 6 5 4 3 2 1 0 D96 D95 D94 D93 D92 D91 D90 bit 7 6 5 4 3 DDRA SIL4 SIL3 SIL2 SIL1 SIL0 Address: 00001AH W W W W W 2 1 0 DA1 DA0 R/W R/W Initial value Access 00000000B R/W 00000000B R/W 00000000B R/W 00000000B R/W 00000000B R/W 00000000B R/W 00000000B R/W 00000000B R/W 00000000B R/W 00000000B R/W 00000100B R/W [bit7 to bit0] D00 to DA1:DDR0 to DDRA These bits set the input and output directions for ports. If pins are used as ports, the corresponding pins are controlled in the manner as follows. When set to "0": Sets the corresponding pins to input mode. When set to "1": Sets the corresponding pins to output mode. 202 FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 9 I/O PORTS 9.2 MB90950 Series [bit7 to bit3] SIL4 to SIL0:DDRA These bits forcefully set the input level of the SIN (Serial input of LIN-UART) pin. SIL0 to SIL4 correspond to SIN0 (LIN-UART0) to SIN4 (LIN-UART4), respectively. When set to "0": The ILTx bit settings and the ILx bit to which ILSR corresponds will select CMOS, automotive, or TTL for the input level. See Section "9.2.5 Input Level Selection Register (ILSR0, ILSR1, ILSR2)" for details of ILSR. When set to "1": CMOS will be selected for the input level, independently of the ILTx bit and ILx setting corresponding to ILSR. The initial value for these bits is "0". Table 9.2-1 SIN0/SIN1 Input Level Settings DDRA ILSR1 SIL0/SIL1 bit IL8 bit 0 0 Automotive level 0 1 CMOS level (0.8Vcc/0.2Vcc) 1 x CMOS level (0.7Vcc/0.3Vcc) SIN0(P82) / SIN1(P85) input level Table 9.2-2 SIN2 Input Level Settings DDRA ILSR0 SIL2 bit IL5 bit 0 0 Automotive level 0 1 CMOS level (0.8Vcc/0.2Vcc) 1 x CMOS level (0.7Vcc/0.3Vcc) SIN2(P50) input level Table 9.2-3 SIN3/SIN4 Input Level Settings DDRA ILSR1, ILSR0 SIN3(P12) / SIN4(P15) input level Note: CM44-10148-4E SIL3/SIL4 bit ILT1 bit IL1 bit 0 0 0 Automotive level 0 0 1 CMOS level (0.8Vcc/0.2Vcc) 0 1 x TTL level 1 x x CMOS level (0.7Vcc/0.3Vcc) SIL0 to SIL4 bits are for writing only. When these bits are read, "1" is consistently read. Therefore, do not use instructions such as INC/DEC instruction that perform read-modify-write (RMW) to DDRA registers. FUJITSU MICROELECTRONICS LIMITED 203 CHAPTER 9 I/O PORTS 9.2 MB90950 Series [bit2] DDRA: Unused bit "1" is consistently read from this bit. Writing to this bit does not have any effect. 204 FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 9 I/O PORTS 9.2 MB90950 Series 9.2.3 Pull-up Control Register (PUCR0 to PUCR3) Each pin for port 0 to 3 has a programmable pull-up resistor. Each bit of this register will control whether the corresponding pull-up resistor is used or not used. Figure 9.2-4 shows the bit configuration for the pull-up control register (PUCR0 to PUCR3), and Figure 9.2-5 shows the block diagram for it. ■ Pull-up Control Register (PUCR0 to PUCR3) Figure 9.2-4 Bit Configuration for the Pull-up Control Register (PUCR0 to PUCR3) bit Address: 00001CH Read/Write Initial value 7 6 5 4 3 2 1 0 PU07 PU06 PU05 PU04 PU03 PU02 PU01 PU00 bit Address: 00001DH Read/Write Initial value 15 14 13 12 11 10 9 8 PU17 PU16 PU15 PU14 PU13 PU12 PU11 PU10 PUCR1 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (0) (0) (0) (0) (0) (0) (0) (0) bit Address: 00001EH Read/Write Initial value 7 6 5 4 3 2 1 0 PU27 PU26 PU25 PU24 PU23 PU22 PU21 PU20 PUCR2 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (0) (0) (0) (0) (0) (0) (0) (0) bit Address: 00001FH Read/Write Initial value PUCR0 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (0) (0) (0) (0) (0) (0) (0) (0) 15 14 13 12 11 10 9 8 PU37 PU36 PU35 PU34 PU33 PU32 PU31 PU30 PUCR3 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (0) (0) (0) (0) (0) (0) (0) (0) R/W: Readable/writable ■ Block Diagram for the Pull-up Control Register (PUCR0 to PUCR3) Figure 9.2-5 Block Diagram for the Pull-up Control Register (PUCR0 to PUCR3) Data register Pull-up resistor (about 50 kΩ) P-ch Port input/output Direction register Pull-up control register Internal data bus Controls the pull-up resistor during input mode. When set to "0": No pull-up resistor during input mode. When set to "1": Pull-up resistor during input mode. Note: This is not applied for the output mode (no pull-up resistor). The port data direction register (DDR) determines the I/O mode. In the stop mode (SPL=1), no pull-up resistor (High impedance). If a port is used as an external bus, this function is disabled, and no data will be written to the register. CM44-10148-4E FUJITSU MICROELECTRONICS LIMITED 205 CHAPTER 9 I/O PORTS 9.2 MB90950 Series Analog Input Enabling Register (ADER5 to ADER7) 9.2.4 Figure 9.2-6 shows the bit configuration of the analog input enabling register (ADER5 to ADER7). ■ Analog Input Enabling Register (ADER5 to ADER7) Figure 9.2-6 Bit Configuration for the Analog Input Enabling Register (ADER5 to ADER7) ADER7 bit Address: 00000DH ADER6 bit Address: 00000CH ADER5 bit Address: 00000BH 15 14 13 12 11 10 9 8 ADE23 ADE22 ADE21 ADE20 ADE19 ADE18 ADE17 ADE16 7 6 5 4 3 2 1 0 ADE7 ADE6 ADE5 ADE4 ADE3 ADE2 ADE1 ADE0 15 14 13 12 11 10 9 8 ADE9 ADE8 ADE15 ADE14 ADE13 ADE12 ADE11 ADE10 Initial value Access 11111111B R/W 11111111B R/W 11111111B R/W R/W: Readable/writable Each bit for ADER5 to ADER7 enables and disables the analog input for the pins of port 7 to port 5. ADER5 to ADER7 correspond to port 7 to port 5, respectively. When set to "0": Analog input will be disabled at the corresponding pin. The pins with disabled analog input can be used as I/O ports and an I/O pin for peripheral functions other than an A/D converter. When set to "1": Sets the corresponding pins to the analog input mode. The pin set to the analog input mode will be a dedicated pin for analog input of an A/D converter. It cannot be used as I/O ports and an I/O pin for other peripheral functions. Note: If "1" is set to the analog input enabling bit (ADE23 to ADE0), each pin of port 7 to port 5 will become an analog input pin for an A/D converter. Because the initial value of ADEx bit is 1, each pin of port 7 to port 5 cannot be used as an I/O port or an I/O pin of peripheral functions other than an A/D converter, if it is in the initial state. To use it as an I/O port or an I/O pin for other peripheral devices, set the ADEx bit to "0". 206 FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 9 I/O PORTS 9.2 MB90950 Series 9.2.5 Input Level Selection Register (ILSR0, ILSR1, ILSR2) The input level selection register allows to change the setting from the automotive hysteresis input level to the CMOS hysteresis input level or to the TTL input level. ■ Input Level Selection Register (ILSR0, ILSR1, ILSR2) Figure 9.2-7 Bit Configuration of the Input Level Selection Register (ILSR0, ILSR1, ILSR2) Address bit 15 14 13 12 ILSR1: 00000FH ILSR0: 00000EH ILT3 ILT2 ILT1 ILT0 Read/Write: R/W R/W R/W R/W Initial value: X X X X Address ILSR2 : 0079A0H Read/Write: Initial value: 12 11 10 9 8 7 6 5 4 3 2 1 0 - ILA IL9 IL8 IL7 IL6 IL5 IL4 IL3 IL2 IL1 IL0 - R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 0 X X 11 10 9 8 7 6 5 4 3 2 X X X X X X X 15 14 13 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1 1 1 1 1 1 X 1 X 0 SIL5 SIL6 W 0 W 0 R/W : Readable/writable — : Undefined [bit10 to bit0] ILA to IL0 These bits specify the input level of corresponding ports. IL0 to ILA correspond to port 0 to port A, respectively. When set to "0": Automotive input level. When set to "1": CMOS input level. The initial values for these bits depend on the settings of operation mode (mode pin). • Flash memory mode - Initial value "1" (CMOS input) • Other modes - Initial value "0" (Automotive) [bit11] Unused bit "0" is consistently read from this bit. Writing has no effect. [bit15 to bit12] ILT3 to ILT0 These bits specify the input level of corresponding ports to either TTL or CMOS/Automotive. ILT0 to ILT3 bits correspond to port 0 to port 3, respectively. When set to "0": The IL0 to ILA bits specify the input level of corresponding ports to either CMOS input level or automotive input level. When set to "1": Sets to TTL input level, independently of the settings in IL0 to ILA bits. CM44-10148-4E FUJITSU MICROELECTRONICS LIMITED 207 CHAPTER 9 I/O PORTS 9.2 MB90950 Series [bit1, bit0] SIL5, SIL6:DDRA These bits forcefully set the input level of the SIN (Serial input of LIN-UART) pin. SIL5 and SIL6 correspond to SIN5 (LIN-UART5) and SIN6 (LIN-UART6), respectively. When set to "0": The ILTx bit settings and the ILx bit to which ILSR corresponds will select CMOS, automotive, or TTL for the input level. When set to "1": CMOS will be selected for the input level, independently of the ILTx bit and ILx setting corresponding to ILSR. The initial value for these bits is "0". Table 9.2-4 SIN5/SIN6 Input Level Settings Note: ILSR2 ILSR1 SIL5/SIL6 bit IL9 bit 0 0 Automotive level 0 1 CMOS level (0.8Vcc/0.2Vcc) 1 x CMOS level (0.7Vcc/0.3Vcc) SIN5(P90) / SIN6(P94) Input level SIL5 and SIL6 bits are for writing only. When these bits are read, "1" is consistently read. Therefore, do not use instructions such as INC/DEC instruction that perform read-modifywrite (RMW) to ILSR2 register. * The EN bit of the clock control register (ICCR0, ICCR1) in the I2C interface forcefully sets the input level of P44, P45, P46, and P47. Table 9.2-5 SDA0/SCL0/SDA1/SCL1 Input Level Settings ICCR0,ICCR1 ILSR0 SDA0(P44) / SCL0(P45)/ SDA1(P46)/SCL1(P47) Input level EN bit IL4 bit 0 0 Automotive level 0 1 CMOS level (0.8Vcc/0.2Vcc) 1 x CMOS level (0.7Vcc/0.3Vcc) Note: The threshold of corresponding pin changes immediately after changing the setting of input level selection register. Until 2 machine cycles after changing the input level selection register setting, do not use the read value of corresponding pin. To change the input level selection register setting, disable the corresponding resources. 208 FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 9 I/O PORTS 9.2 MB90950 Series ■ Initial Value of Input Level Selection Register (ILSR0, ILSR1) The initial values for the bits in ILSR0 and ILSR1 registers depend on the state of pin MD2, MD1, and MD0 after the external reset input is canceled, as shown the table below. See "CHAPTER 8 MEMORY ACCESS MODE" for details about the operation modes. Table 9.2-6 Relationship between the Mode Pins and the Input Level Selection Register (ILSR0, ILSR1) Initial Values Initial value MD2 MD1 MD0 Operation modes Port input level ILT0 to ILT3 IL0 to ILA Port 0 to Port 3 Port 4 to Port A 0 0 0 External vector mode 0 1 0 TTL Automotive 0 0 1 External vector mode 1 1 0 TTL Automotive 0 1 0 0 1 1 Automotive Automotive 1 0 0 1 0 1 1 1 0 Flash serial writing 0 0 Automotive Automotive 1 1 1 Flash memory 1 1 TTL TTL Reserved Internal vector mode 0 0 Reserved CM44-10148-4E FUJITSU MICROELECTRONICS LIMITED 209 CHAPTER 9 I/O PORTS 9.2 210 MB90950 Series FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 10 TIME-BASE TIMER This chapter explains the function and operation of the time-base timer. 10.1 Overview of the Time-base Timer 10.2 Block Diagram of the Time-base Timer 10.3 Configuration of the Time-base Timer 10.4 Interrupt of the Time-base Timer 10.5 Operating Explanation of the Time-base Timer 10.6 Notes on Using the Time-base Timer 10.7 Programming Example of the Time-base Timer CM44-10148-4E FUJITSU MICROELECTRONICS LIMITED 211 CHAPTER 10 TIME-BASE TIMER 10.1 10.1 MB90950 Series Overview of the Time-base Timer The time-base timer is an 18-bit free-run counter (time-base timer counter) that counts up in synchronization with the main clock (divide-by-two of the main oscillation clock). • Provides four different types of interval time and can generate interrupt requests for each interval time. • Provides operating clock to the oscillation stabilization wait time timer or peripheral functions. ■ Interval Timer Function • When the counter of the time-base timer reaches the interval time set at the interval time selection bits (TBTC:TBC1, TBC0), an overflow (carry) occurs (TBTC: TBOF=1), resulting in an interrupt request. • If an interrupt caused by an overflow is allowed (TBTC: TBIE=1), an overflow (TBTC: TBOF=1) triggers an interrupt. • The interval time for the time-base timer can be selected from the following four types. Table 10.1-1 shows the interval time for the time-base timer. Table 10.1-1 Interval Time for the Time-base Timer Count clock Interval time 212/HCLK (about 1.0 ms) 2/HCLK (0.5 μs) 214/HCLK (about 4.1 ms) 216/HCLK (about 16.4 ms) 219/HCLK (about 131.1 ms) HCLK: Oscillation clock The time in parentheses applies when the oscillation clock operates at 4 MHz. 212 FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 10 TIME-BASE TIMER 10.1 MB90950 Series ■ Clock Provision • Provides operating clock to the oscillation stabilization wait time timer and peripheral functions including the PPG timer or watchdog timer. Table 10.1-2 shows the clock cycles provided to the each peripheral from the time-base timer. Table 10.1-2 Clock Cycles Provided from the Time-base Timer Clocking provided to Clock cycle 210/HCLK (about 256 μs) 213/HCLK (about 2.0 ms) Oscillation stabilization wait time* 216/HCLK (about 16.4 ms) 217/HCLK (about 32.8 ms) 212/HCLK (about 1.0 ms) 214/HCLK (about 4.1 ms) Watchdog timer 216/HCLK (about 16.4 ms) 219/HCLK (about 131.1 ms) PPG timer 29/HCLK (about 128 μs) HCLK: Oscillation clock The time in parentheses applies when the oscillation clock operates at 4 MHz. *: The oscillation stabilization wait time is an estimated time because the oscillation cycle is unstable right after starting oscillating. CM44-10148-4E FUJITSU MICROELECTRONICS LIMITED 213 CHAPTER 10 TIME-BASE TIMER 10.2 10.2 MB90950 Series Block Diagram of the Time-base Timer The time-base timer consists of the following blocks. • Time-base timer counter • Counter clearing circuit • Interval timer selector • Time-base timer control register (TBTC) ■ Block Diagram of the Time-base Timer Figure 10.2-1 Block Diagram of the Time-base Timer To watchdog timer To PPG timer Time-base timer counter 21/HCLK × 21 × 22 × 23 ⋅⋅⋅ ⋅⋅⋅ × 28 × 29 × 210 × 211 × 212 × 213 × 214 × 215 × 216 × 217 × 218 OF OF OF OF To clock control part oscillation stabilization wait time selector Power-on reset Stop mode CKSCR : MCS=1→0*1 CKSCR : SCS=0→1*2 Counter clearing circuit Interval timer selector TBOF cleared Time-base timer control register (TBTC) Reserved ⎯ TBOF set ⎯ TBIE TBOF TBR TBC1 TBC0 Time-base timer interrupt signal OF HCLK *1 *2 : Overflow : Oscillation clock : Switches the machine clock from main clock to PLL clock : Switches the machine clock from sub clock to main clock The actual interrupt request number of the time-base timer is as follows. Interrupt request number: #25 (19H) 214 FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 10 TIME-BASE TIMER 10.2 MB90950 Series ● Time-base timer counter An 18-bit up counter that uses the divide-by-two clock of the oscillation clock (HCLK) as count clock. ● Counter clearing circuit The value of the time-base timer counter will be cleared due to the following sources. • The time-base timer counter clearing bit of the time-base timer control register (TBTC: TBR=0) • Power-on reset • Transition to the main stop mode or PLL stop mode (CKSCR:SCS=1, LPMCR: STP=1) • Switching of clock modes (from the main clock mode to the PLL clock mode, from the sub clock mode to the PLL clock mode, or from the sub clock mode to the main clock mode) ● Interval timer selector Selects the time-base timer counter output from the four different types. When an overflow (carry) occurs at the bit of the selected interval time due to a count up, an interrupt request is generated. ● Time-base timer control register (TBTC) Selects the interval time, clears the time-base timer counter, allows/prohibits an interrupt, and checks the state of an interrupt request and clears it. CM44-10148-4E FUJITSU MICROELECTRONICS LIMITED 215 CHAPTER 10 TIME-BASE TIMER 10.3 10.3 MB90950 Series Configuration of the Time-base Timer This section explains the time-base timer register and interrupt sources. ■ List of the Time-base Timer Register and Its Initial Value Figure 10.3-1 List of the Time-base Timer Register and Its Initial Value Time-base timer control register (TBTC) bit 15 14 13 12 11 10 9 8 1 1 1 0 0 1 0 0 ■ Generation of an Interrupt Request in the Time-base Timer When the counter bit for the selected interval timer reaches the interval time, the time-base timer sets "1" in the overflow interrupt request flag bit in the time-base timer control register (TBTC:TBOF). When the overflow interrupt request flag bit is set (TBTC: TBOF=1) while an interrupt is allowed (TBTC: TBIE=1), an interrupt request is generated. 216 FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 10 TIME-BASE TIMER 10.3 MB90950 Series 10.3.1 Time-base Timer Control Register (TBTC) Time-base timer control register (TBTC) allows the following settings. • Selecting the interval time for the time-base timer • Clearing the counter value for the time-base timer • Allowing and prohibiting an interrupt request due to an overflow • Checking the state of and clearing the interrupt request flag due to an overflow ■ Time-base Timer Control Register (TBTC) Figure 10.3-2 Time-base Timer Control Register (TBTC) bit Address 0000A9H 15 14 13 12 11 10 9 8 Initial value Reserved TBIE TBOF TBR TBC1 TBC0 R/W R/W R/W W R/W R/W 11100100 B bit9 bit8 TBC1 TBC0 Interval time selection bits 0 0 212/HCLK (about 1.0 ms) 0 1 214/HCLK (about 4.1 ms) 1 0 216/HCLK (about 16.4 ms) 1 1 219/HCLK (about 131.1 ms) HCLK: Oscillation clock The time in parentheses applies when the oscillation clock operates at 4 MHz. bit10 TBR 0 Time-base timer counter clearing bit Reading Writing Clears time-base timer counter Clears the TBOF bit "1" is always read 1 No effect bit11 TBOF Overflow interrupt request flag bit Reading Writing 0 No overflow at the selected Cleared counter bit 1 Overflow at the selected counter bit No effect bit12 TBIE Overflow interrupt enable bit 0 Overflow interrupt request prohibited 1 Overflow interrupt request allowed bit15 Reserved bit Reserved R/W : Readable/Writable : Write only W : Initial value : Undefined CM44-10148-4E 1 Always set to "1". FUJITSU MICROELECTRONICS LIMITED 217 CHAPTER 10 TIME-BASE TIMER 10.3 MB90950 Series Table 10.3-1 Functions of the Time-base Timer Control Register (TBTC) Bit name bit15 Reserved: Reserved bit Always set to "1". bit14, bit13 Undefined bits When reading : The value is undefined. When writing : No effect. TBIE: Overflow interrupt enable bit Enables or prohibits an interrupt caused by the overflow at the interval timer bit in the time-base timer counter. When set to "0": An interrupt request is not generated even when an overflow occurs (TBOF = 1). When set to "1": An interrupt request is generated when an overflow occurs (TBOF = 1). bit11 TBOF: Overflow interrupt request flag bit Shows an overflow (carry) at the interval timer bit in the time-base timer counter. When an overflow (carry) occurs (TBOF=1) while an interrupt is allowed (TBIE=1), an interrupt request is generated. When set to "0" : Cleared. When set to "1" : Invalid. No change. When read with a read-modify-write instruction :"1" is read. Notes: 1) Before clearing the TBOF bit, be sure to prohibit an interrupt (TBIE=0) or mask an interrupt in the interrupt mask register (ILM) of processor status. 2) The TBOF bit is cleared in the case of writing of "0", transition to the main stop mode, transition to the PLL stop mode, transition from the sub clock mode to the main clock mode, transition from the sub clock mode to the PLL clock mode, transition from the main clock mode to the PLL clock mode, writing of "0" into the time-base timer counter clearing bit (TBR), and reset. bit10 TBR: Time-base timer counter clearing bit Clears all bits in the time-base timer counter. When set to "0": Clears all bits in the time-base timer counter to "0". The TBOF bit is also cleared. When set to "1": Invalid. No change. When reading : "1" is always read. bit9, bit8 TBC1, TBC0: Interval time selection bits bit12 218 Function Sets a cycle for the interval timer in the time-base timer counter. • The setting in the TBC1 and TBC0 bits configures the interval time for the time-base timer. • Four different types of interval time are selectable. FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 10 TIME-BASE TIMER 10.4 MB90950 Series 10.4 Interrupt of the Time-base Timer Carrying (overflowing) the interval time bit in the time-base timer counter corresponding to the interval time configured in the time-base timer control register causes the time-base timer to generate an interrupt request (interval timer function). ■ Interrupt of the Time-base Timer • The time-base timer continues to count up while the main clock (divide-by-two of the oscillation clock) is input. • As soon as the interval time configured at the TBC1 and TBC0 bits in the time-base timer control register has been reached, the interval time selection bit corresponding to the interval time selected in the time-base timer counter is carried to generate an overflow. • When an overflow is generated at the interval time selection bit, the overflow interrupt request flag bit in the time-base timer control register (TBTC: TBOF) is set to "1". • When the overflow interrupt request flag bit in the time-base timer control register is set (TBTC: TBOF=1) while an interrupt is allowed (TBTC: TBIE=1), an interrupt request is generated. • The overflow interrupt request flag bit in the time-base timer control register (TBTC: TBOF) will be set when the configured interval time is reached, regardless of whether an interrupt is allowed or prohibited (TBTC: TBIE). • To clear the overflow interrupt request flag bit (TBTC: TBOF), prohibit the interrupt by the time-base timer in interrupt handling (TBTC: TBIE=0) or mask the interrupt by the time-base timer using the ILM bit in the processor status (PS), and then write "0" into the TBOF bit to clear. Note: When an interrupt is allowed (TBTC: TBIE=1) while the overflow interrupt request flag bit in the timebase timer control register is set (TBTC: TBOF=1), an interrupt request will be generated immediately. ■ Interrupt of Time-base Timer and Support for EI2OS/DMA Transfer • The time-base timer does not support the extended intelligent I/O service (EI2OS) and DMA transfer. • For interrupt numbers, the interrupt control register, and interrupt vector addresses, see Section "3.2 Interrupt Vector". CM44-10148-4E FUJITSU MICROELECTRONICS LIMITED 219 CHAPTER 10 TIME-BASE TIMER 10.5 10.5 MB90950 Series Operating Explanation of the Time-base Timer The time-base timer operates as an interval timer or oscillation stabilization wait time timer. It also provides operating clock to peripheral functions. ■ Interval Timer Function When an interrupt is generated for each interval time, it can be used as an interval timer. To operate the time-base timer as an interval timer, the setting in Figure 10.5-1 is necessary. ● Setting of the time-base timer Figure 10.5-1 Setting of the Time-base Timer Time-base timer control register (TBTC) bit15 14 Reserved 1 13 12 11 10 9 8 TBIE TBOF TBR TBC1TBC0 0 0 : Undefined bit : Used bit 0 : Set to "0" 1 : Set to "1" ● Interval timer function operation The time-base timer can be used as an interval timer by generating an interrupt for each set interval time. • The time-base timer continues to count up synchronizing to the main clock (divide-by-two of the oscillation clock), as long as the oscillation clock is working. • When the interval time configured at the interval time selection bits in the time-base timer control register (TBTC:TBC1, TBC0) has been reached, an overflow carrying occurs in the time-base timer counter, resulting in setting "1" in the overflow interrupt request flag bit (TBTC: TBOF). • An overflow interrupt request flag bit is set (TBTC: TBOF=1) while an interrupt is allowed (TBTC: TBIE=1), an interrupt request is generated. Note: An interval time can be longer than the configured interval time due to the clearing operation by the time-base timer counter. 220 FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 10 TIME-BASE TIMER 10.5 MB90950 Series ● Operating example of the time-base timer Interval timer operations in the following states are shown in Figure 10.5-2. • When a power-on reset occurs • When transiting to the sleep mode while the interval timer function is operating • When transiting to the stop mode while the interval timer function is operating • When time-base timer counter clearing is requested When transiting to the stop mode, the time-base timer counter is cleared and count-up operation terminates. When returning from the stop mode, the time-base timer starts counting the main clock oscillation stabilization wait time. Figure 10.5-2 Operating Example of the Time-base Timer Counter value Cleared due to transition to the stop mode 3FFFFH Oscillation stabilization wait overflow 00000H CPU operation Interval period starts (TBTC: TBC1, TBC0 = 11B) Power-on reset Cleared due to interrupt Counter cleared (TBTC: TBR = 0) TBOF bit TBIE bit Sleep SLP bit (LPMCR register) Sleep canceled due to interrupt by time-base timer interval Stop STP bit (LPMCR register) When "11B" is set at the interval time selection bits (TBTC: TBC1, TBC0) (219/HCLK) : Oscillation stabilization wait time HCLK : Oscillation clock CM44-10148-4E FUJITSU MICROELECTRONICS LIMITED 221 CHAPTER 10 TIME-BASE TIMER 10.5 MB90950 Series ■ Operation of Oscillation Stabilization Wait Time Timer The time-base timer can be used as an oscillation stabilization wait time timer for the main clock and PLL clock. • The oscillation stabilization wait time is a time period from when the time-base timer counter starts counting up from "0" to when the configured oscillation stabilization wait time selection bit is overflowed (carried). Table 10.5-1 shows time-base timer clearing conditions and oscillation stabilization wait time. Table 10.5-1 Time-base Timer Clearing Conditions and Oscillation Stabilization Wait Time (1 / 2) Counter cleared TBOF cleared ❍ ❍ Power-on reset ❍ ❍ After the main clock oscillation stabilization wait time is terminated, switches to the main clock mode Watchdog reset × ❍ None External reset Low-voltage detection reset CPU operation detection reset Clock supervisor reset × ❍ None Software reset × ❍ None Main clock to PLL clock (CKSCR: MCS=1 to 0) ❍ ❍ After the PLL clock oscillation stabilization wait time is terminated, switches to the PLL clock mode Main clock to sub clock (CKSCR: SCS=1 to 0) × × After the sub clock oscillation stabilization wait time is terminated, switches to the sub clock mode Sub clock to main clock (CKSCR: SCS=0 to 1) ❍ ❍ After the main clock oscillation stabilization wait time is terminated, switches to the main clock mode Sub clock to PLL clock (CKSCR: MCS=0, SCS=0 to 1) ❍ ❍ After the main clock oscillation stabilization wait time is terminated, switches to the PLL clock mode PLL clock to main clock (CKSCR: MCS=0 to 1) × × None PLL clock to sub clock (CKSCR: MCS=0, SCS=1 to 0) × × None Operation Writing "0" in the time-base timer counter clearing bit (TBTC: TBR) Oscillation stabilization wait time Reset Clock mode switch 222 FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 10 TIME-BASE TIMER 10.5 MB90950 Series Table 10.5-1 Time-base Timer Clearing Conditions and Oscillation Stabilization Wait Time (2 / 2) Counter cleared TBOF cleared Oscillation stabilization wait time Canceling the main stop mode ❍ ❍ After the main clock oscillation stabilization wait time is terminated, switches to the PLL clock mode Canceling the PLL stop mode ❍ ❍ After the main clock oscillation stabilization wait time is terminated, switches to the PLL clock mode Canceling the sub stop mode × × After the sub clock oscillation stabilization wait time is terminated, switches to the sub clock mode × × None Returning to the main clock mode × × None Returning to the sub clock mode × × None Returning to the PLL clock mode × × None Canceling the main sleep mode × × None Canceling the sub sleep mode × × None Canceling the PLL sleep mode × × None Operation Cancellation of stop modes Cancellation of watch modes Canceling the sub watch mode Cancellation of time-base timer modes Cancellation of sleep modes ■ Operating Clock Provision The time-base timer provides operating clock to the PPG timer and watchdog timer. Note: Take notice that clearing the time-base timer counter affects the operation of peripheral functions such as watchdog timer or PPG timer that uses the time-base timer output. Reference: • See "CHAPTER 15 8/16-BIT PPG TIMER" for details on the PPG timer. • See "CHAPTER 11 WATCHDOG TIMER" for details on the watchdog timer. CM44-10148-4E FUJITSU MICROELECTRONICS LIMITED 223 CHAPTER 10 TIME-BASE TIMER 10.6 10.6 MB90950 Series Notes on Using the Time-base Timer This section shows some notes on using the time-base timer. ■ Notes on Using the Time-base Timer ● When clearing an interrupt request To clear the overflow interrupt request flag bit of the time-base timer control register (TBTC: TBOF=0), prohibit the interrupt (TBTC: TBIE=0) or mask the interrupt by the time-base timer using the interrupt level mask register in the processor status. ● When clearing the time-base timer counter Take notice that clearing the time-base timer counter affects the following operations. • The time-base timer is used as an interval timer (interval interrupt) • The watchdog timer is in use • The time-base timer provides operating clock of the PPG timer ● When using as an oscillation stabilization wait time timer • The oscillation clock is not operating after power is turned on or in main stop, PLL stop, and sub clock modes. Therefore, when oscillation starts, the time-base timer provides main clock oscillation stabilization wait time. Depending on the type of oscillator connected to the high-speed oscillator input pins, suitable oscillation stabilization wait time needs to be specified. Reference: See Section "5.6 Oscillation Stabilization Wait Time" for details on the oscillation stabilization wait time. ● Peripheral functions to which the time-base timer provides clock • When transiting to the operation mode where the oscillation clock pauses (the PLL stop mode, sub clock mode, and main stop mode), the time-base timer counter is cleared and the time-base timer stops operating. • When the time-base timer counter is cleared, an interval time from the point of clearance is needed. Therefore, "L" level becomes longer by 1/2 period or "H" level becomes shorter in clock provided by the time-base timer. • In the case of watchdog timer, the watchdog timer counter normally counts because it is cleared concurrently with the time-base timer counter. 224 FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 10 TIME-BASE TIMER 10.7 MB90950 Series 10.7 Programming Example of the Time-base Timer This section shows programming examples of the time-base timer. ■ Programming Example of the Time-base Timer ● Processing specifications Repeatedly generates interval interrupts at 212/HCLK (HCLK: oscillation clock). The interval time is approximately 1.0 ms (when operating at 4 MHz). ● Coding example ICR07 EQU 0000B7H ;Time-base timer interrupt control ;register TBTC EQU 0000A9H ;Time-base timer control register TBOF EQU TBTC:3 ;Interrupt request flag bit TBIE EQU TBTC:2 ;Interrupt allowance bit ;-------Main program------------------------------------CODE CSEG START: ;Data such as stack pointer (SP) are ;supposed to be initialized AND CCR,#0BFH ;Interrupt prohibited MOV I:ICR07 #00H ;Interrupt level 0 (highest) MOV I:TBTC,#10000000B ;Upper three bits are fixed ;TBOF cleared, ;Counter clearing interval time ;212/HCLK selected ;Interrupt allowed ;ILM in PS set to level seven ;Interrupt allowed ;Infinite loop SETB I:TBIE MOV ILM,#07H OR CCR,#40H LOOP: MOV A,#00H MOV A,#01H BRA LOOP ;-------Interrupt program-------------------------------WARI: CLRB I:TBIE ;Interrupt allowance bit cleared CLRB I:TBOF ;Interrupt request flag cleared • User process • SETB I:TBIE ;Interrupt allowed RETI ;Returned from interrupt process CODE ENDS ;-------Vector setting----------------------------------- CM44-10148-4E FUJITSU MICROELECTRONICS LIMITED 225 CHAPTER 10 TIME-BASE TIMER 10.7 VECT VECT 226 MB90950 Series CSEG ORG ABS=0FFH 0FF98H DSL ORG DSL DB ENDS END WARI 0FFDCH START 00H ;Setting a vector for interrupt number ;#25 (19H) ;Reset vector set ;Setting to the single chip mode START FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 11 WATCHDOG TIMER This chapter explains the function and operation of the watchdog timer. 11.1 Overview of the Watchdog Timer 11.2 Configuration of the Watchdog Timer 11.3 Register of the Watchdog Timer 11.4 Operating Explanation of the Watchdog Timer 11.5 Notes on Using the Watchdog Timer 11.6 Programming Example of the Watchdog Timer CM44-10148-4E FUJITSU MICROELECTRONICS LIMITED 227 CHAPTER 11 WATCHDOG TIMER 11.1 11.1 MB90950 Series Overview of the Watchdog Timer The watchdog timer is a 2-bit counter that uses the time-base timer or the watch timer as count clock. If the counter is not cleared within an interval time, the CPU will be reset. ■ Watchdog Timer Function • The watchdog timer is a timer counter that prevents program hang-ups. Once the watchdog timer activates, the watchdog timer counter shall be continuously cleared to stay within the configured interval time. As soon as the watchdog timer counter reaches the interval time without being cleared, the CPU will be reset. This is referred to as a watchdog timer. • The interval time of the watchdog timer is based on the clock cycle input as count clock, and a watchdog reset occurs between the minimum time and maximum time. • The clock source output destination is set with the watchdog clock selection bit in the watch timer control register (WTC: WDCS). • The interval time of the watchdog timer is set with the time-base timer output selection bit and watch timer output selection bit (WDTC: WT1, WT0) in the watchdog timer control register. Table 11.1-1 shows the interval time for the watchdog timer. Table 11.1-1 Interval Time for the Watchdog Timer Minimum Maximum Clock cycle Minimum Maximum Clock cycle About 3.58 ms About 4.61 ms (214 ±211)/ HCLK About 0.287 s About 0.369 s (212 ±29)/ SCLK About 14.33 ms About 18.3 ms (216 ±213)/ HCLK About 2.294 s About 2.949 s (215 ±212)/ SCLK About 57.23 ms About 73.73 ms (218 ±215)/ HCLK About 4.588 s About 5.898 s (216 ±213)/ SCLK About 458.75 ms About 589.82 ms (221 ±218)/ HCLK About 9.175 s About 11.796 s (217 ±214)/ SCLK HCLK: Oscillation clock (4 MHz), SCLK: Sub clock (12.5 kHz) Notes: • In the case where the count clock of the watchdog timer is used as a time-base timer output (carry signal), the generation time of a watchdog reset may become longer when the time-base timer is cleared. • When sub clock is used as machine clock, be sure to set "0" to the watchdog timer clock source selection bit (WDCS) in the watch timer control register (WTC) to specify the watch timer output. 228 FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 11 WATCHDOG TIMER 11.2 MB90950 Series 11.2 Configuration of the Watchdog Timer The watchdog timer consists of the following blocks. • Count clock selector • Watchdog timer counter (2-bit counter) • Watchdog reset generation circuit • Counter clearing control circuit • Watchdog timer control register (WDTC) ■ Block Diagram of the Watchdog Timer Figure 11.2-1 Block Diagram of the Watchdog Timer Watch timer control register (WTC) Watchdog timer control register (WDTC) WRST ERST SRST WTE WT1 WT0 PONR Watchdog Timer 2 Transits to the timebase timer mode Counter clearing control circuit Count clock selector Transits to the watch mode Transits to the stop mode Reset generated Stop Activate Reset generated Transits to the sleep mode WDCS 2-bit counter Watchdog reset generation circuit Internal reset generation circuit Clear 4 4 (Time-base timer counter) Main clock (divide-by-two of HCLK) × 21 × 22 ⋅⋅⋅ × 28 × 29 × 210 × 211 × 212 × 213 × 214 × 215 × 216 × 217 × 218 (Watch counter) Sub clock SCLK* × 21 × 22 ⋅⋅⋅ × 25 × 26 × 27 × 28 × 29 × 210 × 211 × 212 × 213 × 214 × 215 HCLK: Oscillation clock SCLK: Sub clock *: SCLK will be divide-by-eight or divide-by-four of the CR clock. The division ratio will be set at the SCDS bit of PLL/Sub clock control register (PSCCR). (See "CHAPTER 5 CLOCK") CM44-10148-4E FUJITSU MICROELECTRONICS LIMITED 229 CHAPTER 11 WATCHDOG TIMER 11.2 MB90950 Series ● Count clock selector Specify the time-base timer or the watch timer as count clock to be input to the watchdog timer. Four different types of interval time are selectable from each timer output. ● Watchdog timer counter (2-bit counter) This is a 2-bit up counter that uses the time-base timer or the watch timer output as count clock. The clock source output destination is set with the watchdog clock selection bit in the watch timer control register (WTC: WDCS). ● Watchdog reset generation circuit Sends a reset signal after the overflow (carry) of the watchdog timer. ● Counter clearing circuit Clears the watchdog timer counter. ● Watchdog timer control register (WDTC) Activates and clears the watchdog timer, sets an interval time, and keeps a reset generation source. 230 FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 11 WATCHDOG TIMER 11.3 MB90950 Series 11.3 Register of the Watchdog Timer This section explains the register used to set the watchdog timer. ■ List of the Watchdog Timer Register and the Reset Value Figure 11.3-1 List of the Watchdog Timer Register and the Reset Value bit Watchdog timer control register (WDTC) 7 6 1 5 4 3 2 1 0 1 1 1 : Undefined CM44-10148-4E FUJITSU MICROELECTRONICS LIMITED 231 CHAPTER 11 WATCHDOG TIMER 11.3 MB90950 Series Watchdog Timer Control Register (WDTC) 11.3.1 Activates and clears the watchdog timer, sets an interval time, and keeps a reset generation source. ■ Watchdog Timer Control Register (WDTC) Figure 11.3-2 Watchdog Timer Control Register (WDTC) bit Address 0000A8H 7 PONR R 6 5 4 3 2 1 0 Initial value Res. WRST ERST SRST WTE WT1 WT0 R R R R W W W X1XXX111B bit1 bit0 Interval time selection bits (Time-base timer output selection) WT1 WT0 Interval time Minimum Maximum Clock cycle 0 0 About 3.58 ms About 4.61 ms (214 ±211)/HCLK 0 1 About 14.33 ms About 18.3 ms (216 ±213)/HCLK 1 0 About 57.23 ms About 73.73 ms (218 ±215)/HCLK 1 1 About 458.75 ms About 589.82 ms (221 ±218)/HCLK HCLK: Oscillation clock In above table, the interval time applies when HCLK operates at 4 MHz. bit1 bit0 Interval time selection bits (Watch timer output selection) WT1 WT0 Interval time Minimum Maximum Clock cycle 0 0 About 0.287 s About 0.369 s (212 ±29)/SCLK 0 1 About 2.294 s About 2.949 s (215 ±212)/SCLK 1 0 About 4.588 s About 5.898 s (216 ±213)/SCLK 1 1 About 9.175 s About 11.796 s (217 ±214)/SCLK SCLK: Sub clock (See Note below.) In above table, the interval time applies when SCLK operates at 12.5 kHz. bit2 WTE Watchdog timer control bit 0 The first writing after reset: Activates the watchdog timer 1 No effect bit7 bit5 bit4 The second writing or later after reset: Clears the watchdog timer bit3 Reset source bits Reset source PONR WRST ERST SRST R W * X Res. : Read only : Write only : Keeps the previous state : Undefined value : Reserved bit 1 X X X Power-on reset ∗ 1 ∗ ∗ ∗ ∗ Watchdog reset 1 ∗ ∗ ∗ External reset (Inputs "L" level in RST pins) ∗ 1 Software reset (Writes "1" in the RST bit) Note: SCLK will be divide-by-eight or divide-by-four of the CR clock. The division ratio will be set at the SCDS bit of PLL/Sub clock control register (PSCCR). (See "CHAPTER 5 CLOCK") 232 FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 11 WATCHDOG TIMER 11.3 MB90950 Series Table 11.3-1 Functions of the Watchdog Timer Control Register (WDTC) Bit name bit7, bit5 to bit3 PONR, WRST, ERST, SRST: Reset source bits Shows the reset source. • When reset occurs, "1" will be set in the bit that corresponds to the reset source. After reset, the watchdog timer control register (WDTC) can be read to check the reset source. • The reset source bit will be cleared after reading the watchdog timer control register (WDTC). Note: The data other than PONR bit will not be secured after power-on reset. If the PONR bit is set when reading, ignore the other bit data. bit6 Reserved bit When reading : The value is undefined. When writing : No effect. bit2 WTE: Watchdog timer control bit Activates or clears the watchdog timer. When set to "0" (The first time after reset) : Activates. When set to "0" (The second time or later after reset) : Cleared. WT1, WT0: Interval time selection bits Sets the watchdog timer interval time. The interval time differs as shown in Figure 11.3-2 in the case where the watch timer control register (WTC) specifies the watch timer as a clock source for the watchdog timer (watchdog clock selection bit: WDCS=0), and in the case where the main clock mode or PLL clock mode is selected as a clock mode and the WDCS bit in WTC is "1". In sub clock mode, be sure to set the watchdog clock selection bit (WDCS) in the watch timer control register (WTC) to "0" and select the watch timer output. • The data on activating the watchdog timer will be effective. • The written data after activating the watchdog timer will be ignored. • These bits are for writing only. bit1, bit0 CM44-10148-4E Function FUJITSU MICROELECTRONICS LIMITED 233 CHAPTER 11 WATCHDOG TIMER 11.4 11.4 MB90950 Series Operating Explanation of the Watchdog Timer After activating the watchdog timer, when its counter reaches the interval time without being cleared, a watchdog reset occurs. ■ State Transition Chart of the Watchdog Timer The watchdog timer has the following four states. Disabled: Is not operating. Operating: Starts counting from the counter-cleared state. Stopped: Continues the counter-cleared state. Overflowed: Generates a watchdog reset. Figure 11.4-1 State Transition Chart of the Watchdog Timer Disabled (Initial state) Writes "0" in the WTE bit Reset Reset Cancels the stop mode by interrupt Operating Starts counting from the counter-cleared state Stopped Counter-cleared state Transits to the stop mode Counter overflow Overflowed Always Generates a watchdog reset Writes "0" in the WTE bit Transits to the sleep mode Transits to the watch mode Transits to the time-base timer mode 234 FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 11 WATCHDOG TIMER 11.4 MB90950 Series ■ Watchdog Timer Operations To operate the watchdog timer, the configuration shown in Figure 11.4-2 will be necessary. Figure 11.4-2 Watchdog Timer Settings bit 7 Watchdog timer control register (WDTC) 6 5 4 3 2 1 bit 0 WRST ERST SRST WTE WT1 WT0 PONR 0 bit 7 Watch timer control register (WTC) 6 5 4 3 2 1 bit 0 WDCS SCE WTIE WTOF WTR WTC2 WTC1 WTC0 : Used bit 0 : Set to "0" ● Selection of a clock input source • The time-base timer or watch timer can be selected as a clock input source for the watchdog timer count clock. The time-base timer is selected when setting "1" to the watchdog clock selection bit (WTC: WDCS), and the watch timer is selected when setting "0" thereto. It returns to "1" (time-base timer) after resetting. • When operating in the sub clock mode, set "0" to the WDCS bit to select the watch timer. ● Setting of interval time • To select the interval time of the watchdog timer, set the interval time selection bits (WDTC: WT1, WT0). • Set an interval time concurrently with the activation. It will be ignored if written after activating the watchdog timer. ● Activation of watchdog timer When "0" is written to the watchdog timer control bit (WDTC: WTE) after resetting, the watchdog timer activates and starts counting up. CM44-10148-4E FUJITSU MICROELECTRONICS LIMITED 235 CHAPTER 11 WATCHDOG TIMER 11.4 MB90950 Series ● Clearing of the watchdog timer • The watchdog timer will be cleared when "0" is written to the watchdog timer control bit (WDTC: WTE) again within the interval time. If it is not cleared within the interval time, a watchdog timer overflow occurs, resulting in CPU reset. • The watchdog timer is cleared by resetting or transiting to standby modes (the sleep mode, stop mode, watch mode, and time-base timer mode). • When the time-base timer is in operation, the watch mode is in operation, or the mode is sleep mode, the watchdog timer counter will be cleared while the watchdog timer is activating. • Figure 11.4-3 shows the relationship between the watchdog timer clearing timing and the interval time. The interval time differs depending on the timing to clear the watchdog timer. 236 FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 11 WATCHDOG TIMER 11.4 MB90950 Series ● Check of reset sources By reading the reset source bits (WDTC: PONR, WRST, ERST, SRST) in the watchdog timer control register (WDTC) after resetting, reset sources can be checked. Reference: See "CHAPTER 6 RESET" for details on reset source bits. Figure 11.4-3 The Watchdog Timer Clearing Timing and Interval Time [Watchdog timer block diagram] 2-bit counter Clock selector a Divide-bytwo circuit b Divide-bytwo circuit c Reset circuit d Reset signal Enabling and clearing counts WTE bit Count enable output circuit [Minimum interval time] When WTE bit cleared immediately before count clock rises Count starts Counter cleared Count clock a Divide-by-two value b Divide-by-two value c Count allowed Reset signal d 7 × (Count clock cycle/2) Watchdog reset generated WTE bit cleared [Maximum interval time] When WTE bit cleared immediately after count clock rises Count starts Counter cleared Count clock a Divide-by-two value b Divide-by-two value c Count allowed Reset signal 9 × (Count clock cycle/2) WTE bit cleared CM44-10148-4E Watchdog reset generated FUJITSU MICROELECTRONICS LIMITED 237 CHAPTER 11 WATCHDOG TIMER 11.5 11.5 MB90950 Series Notes on Using the Watchdog Timer Take notice of the following points when using the watchdog timer. ■ Notes on Using the Watchdog Timer ● Stopping the watchdog timer The watchdog timer stops on transition to the stop mode. ● Interval time • Because the carry signal of the time-base timer or watch timer is used as count clock for interval time, the interval time of the watchdog timer can be longer when the time-base timer or watch timer is cleared. The time-base timer will also be cleared in the case of transition from the main clock mode to the PLL clock mode, from the sub clock mode to the main clock mode, and from the sub clock mode to the PLL clock mode, in addition to the case where "0" is written to the time-base timer counter clear bit (TBR) in the time-base timer control register (TBTC). • Set an interval time concurrently with the activation of watchdog timer. It will be ignored if set except at the activation. ● Notes on writing programs • When continuously clearing the watchdog timer in the main loop, set a shorter time than the watchdog timer interval time for the main loop processing time including interrupt processing. • Because the watchdog timer is operating during DMA transfer, the hold state, the sleep and time-base timer mode, or the watch mode, the operation time (such as interval time) in each mode has to be taken into consideration in user programs. ● Notes on using sub clock mode In sub clock mode, be sure to set the watchdog clock selection bit (WDCS) in the watch timer control register (WTC) to "0" and select the watch timer output. ● Operations of watchdog timer in the sleep mode, time-base timer mode, and watch mode When transiting to the sleep mode, time-base timer mode, and watch mode, the watchdog timer is cleared and restarts counting (see Table 11.5-1). ● Operations of watchdog timer during DMA transfer Because the watchdog timer operates during DMA transfer, a watchdog reset may occur during DMA transfer. To prevent a reset, take necessary measures in user programs (see Table 11.5-1). 238 FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 11 WATCHDOG TIMER 11.5 MB90950 Series ● Watchdog timer operations in hold state (external bus mode) Even if CPU is in hold state, the watchdog timer is running. Therefore, the watchdog reset might be generated in spite of the hold state. Settle with the user program for avoiding the reset (see Table 11.5-1). ● Operations of watchdog timer in stop mode When transiting to the stop mode, the watchdog timer is cleared and stopped. As soon as the stop mode is canceled, the watchdog timer starts counting again (see Table 11.5-1). ● Operations of watchdog timer in reset The watchdog timer will be disabled by all reset sources. After the reset is canceled, the watchdog timer remains disabled (see Table 11.5-1). Table 11.5-1 Watchdog Timer Clearing Conditions Operation mode Reset WDTC register WTE=0 Stop mode Sleep mode Time-base timer mode Watch mode Hold μDMAC Clear In transition In writing In transition In transition In transition In transition None None Operating (Starts counting after clearing) Operating (Starts counting after clearing) Operating (Starts counting after clearing) Operating (Continues counting) Operating (Continues counting) Watchdog timer state in modes Disabled - Stopped (Keeps cleared) Watchdog reset in modes Not occur - Not occur Occur Occur Occur Occur Occur Operating Operating (Restarts counting after clearing) Operating (Continues counting) Operating (Continues counting) Operating (Continues counting) Operating (Continues counting) Operating (Continues counting) Watchdog timer state after canceling and returning modes CM44-10148-4E Disabled FUJITSU MICROELECTRONICS LIMITED 239 CHAPTER 11 WATCHDOG TIMER 11.6 11.6 MB90950 Series Programming Example of the Watchdog Timer This section shows programming examples of the watchdog timer. ■ Programming Example of the Watchdog Timer ● Processing specifications • Clears the watchdog timer each time in the main program loop. • The main program has to go around once within the minimum interval time of watchdog timer. ● Coding example WDTC EQU 0000A8H ;Watchdog timer control register WTE EQU WDTC:2 ;Watchdog control bit ; ;---------Main program--------------------------------------CODE CSEG START: ;Data such as stack pointer (SP) are ;supposed to be initialized MOV I:WDTC,#00000011B ;Activation of watchdog timer ;Selects a 221+218 cycle for interval ;time LOOP: CLRB I:WTE ;Clearing of the watchdog timer • User process • BRA LOOP ;---------Vector setting------------------------------------VECT CSEG ABS=0FFH ORG 00FFDCH ;Reset vector set DSL START DB 00H ;Setting to the single chip mode VECT ENDS END START 240 FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 12 16-BIT I/O TIMER This chapter explains the functions and operations of the 16-bit I/O timer. 12.1 Overview of 16-bit I/O Timer 12.2 Block Diagram of 16-bit I/O Timer 12.3 Configuration of 16-bit I/O Timer 12.4 Interrupts from 16-bit I/O Timer 12.5 Operations of 16-bit Free-run Timer 12.6 Input Capture Operations 12.7 Output Compare Operations 12.8 Notes on Using the 16-bit I/O Timer 12.9 Sample Programs for 16-bit I/O Timer CM44-10148-4E FUJITSU MICROELECTRONICS LIMITED 241 CHAPTER 12 16-BIT I/O TIMER 12.1 12.1 MB90950 Series Overview of 16-bit I/O Timer The 16-bit I/O timer consists of two 16-bit free-run timers, eight input capture channels, and eight output compare channels. Based on the 16-bit free-run timers, the 16-bit I/O timer can output eight independent waveforms and measure input pulses and external clock cycles. ■ Modules Making Up the 16-bit I/O Timer The 16-bit I/O timer contains the following modules: ● 16-bit free-run timer × 2 • 16-bit free-run timer 0 (ch.0) • 16-bit free-run timer 1 (ch.1) ● Input capture channels × 8 • Input capture unit 0: Captures 16-bit free-run timer 0. - Input capture 0 (ch.0) - Input capture 1 (ch.1) - Input capture 2 (ch.2) - Input capture 3 (ch.3) • Input capture unit 1: Captures 16-bit free-run timer 1. - Input capture 4 (ch.4) - Input capture 5 (ch.5) - Input capture 6 (ch.6) - Input capture 7 (ch.7) ● Output compare channels × 8 • Output compare unit 0: Compares register values with 16-bit free-run timer 0. (Comparison and match detection) - Output compare 0 (ch.0) - Output compare 1 (ch.1) - Output compare 2 (ch.2) - Output compare 3 (ch.3) • Output compare unit 1: Compares register values with 16-bit free-run timer 1. (Comparison and match detection) - Output compare 4 (ch.4) - Output compare 5 (ch.5) - Output compare 6 (ch.6) - Output compare 7 (ch.7) 242 FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 12 16-BIT I/O TIMER 12.1 MB90950 Series ■ Functions of 16-bit I/O Timer ● Functions of 16-bit free-run timer Each 16-bit free-run timer consists of a 16-bit up-counter, a prescaler, and control registers. The count value of the 16-bit free-run timer is used as the reference time for the input capture and output compare units. • The count clock cycle can be selected from among eight options. • An interrupt request can be generated when the counter overflows. • The counter of the 16-bit free-run timer is cleared to "0000H" at a reset, when the timer is cleared (TCCSL: CLR=1), or upon detection of an output compare match. ● Functions of input capture units The input capture units contain eight 16-bit capture registers corresponding to external input pins, control registers, and edge detection circuits. When a trigger edge is input to an external input pin, the 16-bit free-run timer holds its counter value and generates an interrupt request at the same time. • A capture interrupt can be generated independently for each channel. • The input capture unit can activate DMA transfer or extended intelligent I/O service (EI2OS). • The trigger edge can be selected from among the rising edge, falling edge, and both edges. • Each channel works independently, allowing up to eight inputs to be measured. • If you set LIN-UART as the input signal, the baud rate can be measured in LIN slave mode. ● Functions of output compare unit The output compare unit contains eight 16-bit compare registers, control registers, compare control circuits, and output control circuits. The output compare unit compares its register value with the counter value of the 16-bit free-run timer. When they match, the output compare unit inverts the output level of the corresponding output compare pin and generates an interrupt request at the same time. • The output compare unit can activate DMA transfer or extended intelligent I/O service (EI2OS). • The output compare unit has the output pins and interrupt request flags corresponding to its eight output compare registers and allows the individual registers to operate independently. • The output level can be inverted upon detection of compare matches of at least two channels such as output compare ch.0 and ch.1. (The OUT0 and OUT4 pin outputs are not supported.) • The output level of each pin can be set upon activation. CM44-10148-4E FUJITSU MICROELECTRONICS LIMITED 243 CHAPTER 12 16-BIT I/O TIMER 12.2 12.2 MB90950 Series Block Diagram of 16-bit I/O Timer The 16-bit I/O timer consists of the following modules: • 16-bit free-run timer • Input capture units • Output compare units ■ Block Diagram of 16-bit I/O Timer Figure 12.2-1 Block Diagram of 16-bit I/O Timer Internal data bus Input capture unit Dedicated bus 16-bit free-run timer Dedicated bus Output compare unit ● 16-bit free-run timer The count value of the 16-bit free-run timer is used as the base time for the input capture and output compare units. ● Input capture unit When a trigger edge is input to an external input pin or when the trigger edge for LIN slave baud rate measurement is input from LIN-UART, the 16-bit free-run timer holds its counter value and generates an interrupt request at the same time. ● Output compare unit The output compare unit compares its register value with the counter value of the 16-bit free-run timer. When they match, the output compare unit inverts the output level of the corresponding pin and generates an interrupt request at the same time. 244 FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 12 16-BIT I/O TIMER 12.2 MB90950 Series ■ Pin Summary and Interrupt Numbers Table 12.2-1 lists the pins used for the 16-bit I/O timer and their respective interrupts. Table 12.2-1 Pin Summary and Interrupt Numbers Interrupt No. DMA channel EI2OS support #33 (21H) 8 ❍ 6 ❍ P31/IN5 #31 (1FH) IN6 P42/IN6/ RX1/ INT9R #13 (0DH) — × Input capture ch.7 (using 16-bit free-run timer ch.1) IN7 P43/IN7/ TX1 #14 (0EH) — × Output compare ch.0 (using 16-bit free-run timer ch.0) OUT0 P94/ OUT0 #32 (20H) 7 ❍ #34 (22H) 9 ❍ #32 (20H) 7 ❍ #34 (22H) 9 ❍ #30 (1EH) — × Channel Dedicated pin Pin name Input capture ch.0 (using 16-bit free-run timer ch.0) IN0 P24/IN0 Input capture ch.1 (using 16-bit free-run timer ch.0) IN1 P25/IN1 Input capture ch.2 (using 16-bit free-run timer ch.0) IN2 P26/IN2 Input capture ch.3 (using 16-bit free-run timer ch.0) IN3 P27/IN3 Input capture ch.4 (using 16-bit free-run timer ch.1) IN4 P30/IN4 Input capture ch.5 (using 16-bit free-run timer ch.1) IN5 Input capture ch.6 (using 16-bit free-run timer ch.1) Output compare ch.1 (using 16-bit free-run timer ch.0) OUT1 P95/ OUT1 Output compare ch.2 (using 16-bit free-run timer ch.0) OUT2 P96/ OUT2 Output compare ch.3 (using 16-bit free-run timer ch.0) OUT3 P97/ OUT3 Output compare ch.4 (using 16-bit free-run timer ch.1) OUT4 P34/ OUT4 Output compare ch.5 (using 16-bit free-run timer ch.1) OUT5 P35/ OUT5 Output compare ch.6 (using 16-bit free-run timer ch.1) OUT6 P36/ OUT6 Output compare ch.7 (using 16-bit free-run timer ch.1) OUT7 P37/ OUT7 16-bit free-run timer ch.0 (overflow interrupt or output compare ch.0 compare match interrupt) FRCK0 P44/ FRCK0/ SDA0 16-bit free-run timer ch.1 (overflow interrupt or output compare ch.4 compare match interrupt) CM44-10148-4E FRCK1 P45/ FRCK1/ SCL0 FUJITSU MICROELECTRONICS LIMITED 245 CHAPTER 12 16-BIT I/O TIMER 12.2 12.2.1 MB90950 Series Block Diagram of 16-bit Free-run Timer The MB90950 series contains two channels of 16-bit free-run timer, each of which consists of the following blocks: ■ Block Diagram of 16-bit Free-run Timer Figure 12.2-2 Block Diagram of 16-bit Free-run Timer Output count values to input capture and output compare units. Timer data register (TCDT0,♦TCDT1) OF 16-bit counter CLK STOP CLR External clock Prescaler Output compare register 0 match signal (♦ Output compare register 4) 3 Timer control status register (lower) (TCCSL0,♦TCCSL1) Internal data bus (TCDT0,♦TCDT1) IVF IVFE STOP MODE CLR CLK2 CLK1 CLK0 Free-run timer overflow interrupt request Timer control status register (upper) (TCCSH0,♦TCCSH1) ECKE φ : Machine clock OF : Overflow ♦ : Name for 16-bit free-run timer ch.1 ● Prescaler The prescaler divides the frequency of the machine clock signal and supplies the product to the 16-bit counter as its count clock signal. The count clock cycle can be selected from among eight options, depending on the settings in the timer control status register (TCCSL: CLK2 to CLK0). ● Timer data register (TCDT) The timer data register can read the counter value of the 16-bit free-run timer. While the 16-bit free-run timer is inactive, the counter value can be set by writing it to the TCDT register. ● Timer control status registers (TCCSH, TCCSL) The timer control status registers (upper and lower) can be used to select the count clock, select the counter clear condition, clear the counter, enable counting, enable interrupt requests, and to check the overflow generation flag. 246 FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 12 16-BIT I/O TIMER 12.2 MB90950 Series 12.2.2 Block Diagrams of Input Capture Units The individual input capture units consist of the blocks illustrated below. ■ Block Diagrams of Input Capture Units Figure 12.2-3 Block Diagram of Input Capture Unit 0 16-bit free-run timer Edge detection circuit IN3 Input capture data register 3 (IPCP3) Pin IN2 Input capture data register 2 (IPCP2) Pin Input capture edge register (ICE23) IEI3 IEI2 2 2 ICP3 ICP2 ICE3 ICE2 EG31 EG30 EG21 EG20 Input capture interrupt request Input capture control status register (ICS01) Internal data bus Input capture control status register (ICS23) ICP1 ICP0 ICE1 ICE0 EG11 EG10 EG01 EG00 2 2 Input capture edge register (ICE01) ICUS1 ICUS0 IEI1 IEI0 IN1 Pin Input capture data register 1 (IPCP1) LIN-UART1 IN0 Pin Input capture data register 0 (IPCP0) LIN-UART0 Edge detection circuit CM44-10148-4E FUJITSU MICROELECTRONICS LIMITED 247 CHAPTER 12 16-BIT I/O TIMER 12.2 MB90950 Series Figure 12.2-4 Block Diagram of Input Capture Unit 1 16-bit free-run timer Edge detection circuit IN7 Pin Input capture data register 7 (IPCP7) LIN-UART3 IN6 Pin Input capture data register 6 (IPCP6) LIN-UART2 LIN-UART4 2 ICUS7 ICUS61 ICUS60 IEI7 IEI6 Input capture edge register (ICE67) 2 2 ICP7 ICP6 ICE7 ICE6 EG71 EG70 EG61 EG60 Input capture interrupt request Input capture control status register (ICS45) Internal data bus Input capture control status register (ICS67) ICP5 ICP4 ICE5 ICE4 EG51 EG50 EG41 EG40 2 2 Input capture edge register (ICE45) ICUS5 ICUS4 IEI5 IEI4 IN5 Pin Input capture data register 5 (IPCP5) LIN-UART6 IN4 Pin Input capture data register 4 (IPCP4) LIN-UART5 Edge detection circuit 248 FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 12 16-BIT I/O TIMER 12.2 MB90950 Series ● Input capture data registers 0 to 7 (IPCP0 to IPCP7) • The input capture data registers hold the captured counter value of the 16-bit free-run timers. • Input capture data registers 0 to 3 hold the counter value of 16-bit free-run timer 0. • Input capture data registers 4 to 7 hold the counter value of 16-bit free-run timer 1. ● Input capture control status registers 01, 23, 45, 67(ICS01, ICS23, ICS45, ICS67) • The input capture control status registers can be used to select the edge trigger, enable capturing, enable capture interrupt requests, and to check the valid edge detection flag for the individual input capture units. • There are four input capture control status registers. These are used to control the input capture operations of their respective channels as shown in Table 12.2-2. ● Input capture edge registers 01, 23, 45, 67(ICE01, ICE23, ICE45, ICE67) • The input capture edge registers display the polarities of edges detected through the input capture of their respective channels. They are also used to select the input signal (external pin INx or LIN-UART). When LIN-UART is selected as the input, the baud rate can be measured in LIN slave mode (see Section "19.7.3 Operation of LIN Function (Operating Mode 3)"). • There are four input capture edge registers. These are used to control the input capture operations of their respective channels as shown in Table 12.2-2. Table 12.2-2 Correspondence between Input Capture Registers and Pins Input capture control status register Input capture edge register ICS01 ICE01 Input capture unit 0 ICS23 ICS45 Input pin Input from LIN-UART IPCP0 IN0 UART0 IPCP1 IN1 UART1 IPCP2 IN2 — IPCP3 IN3 — IPCP4 IN4 UART5 IPCP5 IN5 UART6 IPCP6 IN6 UART2, UART4 IPCP7 IN7 UART3 ICE23 ICE45 Input capture unit 1 ICS67 Input capture data register ICE67 ● Edge detection circuit The edge detection circuit detects the edges of signals input to the external input pins. The edge type to be detected can be selected from among the rising edge, falling edge, both edges, and no detection (capture off). CM44-10148-4E FUJITSU MICROELECTRONICS LIMITED 249 CHAPTER 12 16-BIT I/O TIMER 12.2 12.2.3 MB90950 Series Block Diagram of Output Compare Unit The output compare unit consists of the following blocks: ■ Block Diagram of Output Compare Unit Figure 12.2-5 Block Diagram of Output Compare Unit 0 (1) Output compare interrupt request Output compare control status register OCS2, OCS3 (OCS6, OCS7) CMOD1 CMOD0 OTE3 OTE2 OTD3 OTD2 IOP3 IOP2 IOE3 IOE2 2 2 CST3 CST2 2 2 Timer data register TCDT0 (TCDT1) 16-bit free-run timer 0 (1) Compare control circuit 3 (7) OCCP3 (OCCP7) Output compare register 3 (7) Compare control circuit 2 (6) OUT3 (OUT7) Output control circuit 3 (7) Internal data bus OCCP2 (OCCP6) Output compare register 2 (6) Pin OUT2 (OUT6) Output control circuit 2 (6) Pin Compare control circuit 1 (5) OUT1 (OUT5) OCCP1 (OCCP5) Output control circuit 1 (5) Output compare register 1 (5) Pin OUT0 (OUT4) Output control circuit 0 (4) Compare control circuit 0 (4) Pin OCCP0 (OCCP4) Output compare register 0 (4) 2 2 CMOD1 CMOD0 OTE1 OTE0 OTD1 OTD0 IOP1 IOP0 IOE1 IOE0 Output compare control status register OCS0, OCS1(OCS4, OCS5) CST1 CST0 Output compare interrupt request Components of output compare unit 1 are designated as in parentheses. 250 FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 12 16-BIT I/O TIMER 12.2 MB90950 Series ● Output compare registers 0 to 7 (OCCP0 to OCCP7) • The output compare registers contain the values to be compared with the counter value of the 16-bit free-run timer. • The values set in output compare registers 0 to 3 are compared with the counter value of 16-bit free-run timer 0. • The values set in output compare registers 4 to 7 are compared with the counter value of 16-bit free-run timer 1. • When a value set in output compare registers 0 to 7 matches the counter value of the free-run timer, the output level of the corresponding output compare output pin is inverted and an interrupt request is issued. ● Output compare control status registers 0 to 7 (OCS0 to OCS7) • The output compare control status registers can be used to set and check the output levels of the output compare pins, enable their output, select the output level inversion mode, enable and check compare match interrupts, and to enable output comparison. • There are four output compare control status registers. These are used to control the output comparison of their respective channels as shown in Table 12.2-3. Table 12.2-3 Correspondence between Output Compare Control Status Registers and Pins Register name Output compare unit 0 Output compare unit 1 Output compare register controlled Output pin Output compare control status register 0, 1 (OCS0, OCS1) Output compare register 0 OUT0 Output compare register 1 OUT1 Output compare control status register 2, 3 (OCS2, OCS3) Output compare register 2 OUT2 Output compare register 3 OUT3 Output compare control status register 4, 5 (OCS4, OCS5) Output compare register 4 OUT4 Output compare register 5 OUT5 Output compare control status register 6, 7 (OCS6, OCS7) Output compare register 6 OUT6 Output compare register 7 OUT7 ● Compare control circuits 0 to 7 The compare control circuits compare the output compare register values with the 16-bit free-run timer value and, if a compare match is detected, output a compare match signal to the corresponding output control circuit. ● Output control circuits 0 to 7 The output control circuits inverts the output level of an output compare pin when the output compare register value matches the 16-bit free-run timer value. CM44-10148-4E FUJITSU MICROELECTRONICS LIMITED 251 CHAPTER 12 16-BIT I/O TIMER 12.3 12.3 MB90950 Series Configuration of 16-bit I/O Timer This section details the pins, interrupt triggers, and registers for the 16-bit I/O timer. ■ Pins for 16-bit I/O Timer The pins used for the 16-bit I/O timer also serve as general-purpose I/O ports. Table 12.3-1 lists the pins, their functions, and the settings for use by the 16-bit I/O timer. Table 12.3-1 Pins for 16-bit I/O Timer Channel Pin name Pin function Setting required for pin use 16-bit free-run timer 0 P44/ SDA0/ FRCK0 General-purpose I/O port / I2C0 data input/output / external clock input • Use the port direction register (DDR) to set the pins as input ports. • Disable I2C0 operation (ICCR0:EN=0). 16-bit free-run timer 1 P45/ SCL0/ FRCK1 General-purpose I/O port / I2C0 clock input/output / external clock input • Use the port direction register (DDR) to set the pins as input ports. • Disable I2C0 operation (clock control register ICCR0:EN=0). 252 Input capture 0 P24/IN0 Use the port direction register (DDR) to set the pin as an input port. Input capture 1 P25/IN1 Use the port direction register (DDR) to set the pin as an input port. Input capture 2 P26/IN2 Input capture 3 P27/IN3 Input capture 4 P30/IN4 Use the port direction register (DDR) to set the pin as an input port. Input capture 5 P31/IN5 Use the port direction register (DDR) to set the pin as an input port. Input capture 6 P42/ IN6/ RX1/ INT9R General-purpose I/O port / capture input / CAN input / external interrupt input Use the port direction register (DDR) to set the pin as an input port. Input capture 7 P43/ IN7/ TX1 General-purpose I/O port / capture input / CAN output • Use the port direction register (DDR) to set the pin as an input port. • Set CAN1 to disable output (CAN control status register CSR1: TOE=0) Output compare 0 P94/OUT0 Enable output compare output (OCS1: OTE0=1) Output compare 1 P95/OUT1 Enable output compare output (OCS1: OTE1=1) Output compare 2 P96/OUT2 Enable output compare output (OCS3: OTE2=1) Output compare 3 P97/OUT3 Output compare 4 P34/OUT4 Output compare 5 P35/OUT5 Enable output compare output (OCS5: OTE5=1) Output compare 6 P36/OUT6 Enable output compare output (OCS7: OTE6=1) Output compare 7 P37/OUT7 Enable output compare output (OCS7: OTE7=1) General-purpose I/O port / capture input General-purpose I/O port / compare output Use the port direction register (DDR) to set the pin as an input port. Use the port direction register (DDR) to set the pin as an input port. Enable output compare output (OCS3: OTE3=1) Enable output compare output (OCS5: OTE4=1) FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 12 16-BIT I/O TIMER 12.3 MB90950 Series ■ Generation of Interrupt Requests by the 16-bit I/O Timer The 16-bit I/O timer can generate the following types of interrupt requests: ● Timer counter overflow interrupt An interrupt request is generated when either of the following events occurs with overflow interrupt requests enabled (TCCSL: IVFE=1): • The 16-bit free-run timer causes an overflow. • The counter of the 16-bit free-run timer is cleared (with TCCSL:MODE=1) as the counter value matches an output compare register value. ● Input capture interrupt When input capture interrupt requests have been enabled (ICS01:ICE=1), an interrupt request is generated if a trigger edge is detected at the input capture pin or if the trigger edge for LIN slave baud rate measurement is input from LIN-UART. ● Output compare interrupt When output compare interrupt requests have been enabled (OCS0: IOE=1), an interrupt request is generated if the counter value of the 16-bit free-run timer matches an output compare register value. CM44-10148-4E FUJITSU MICROELECTRONICS LIMITED 253 CHAPTER 12 16-BIT I/O TIMER 12.3 12.3.1 MB90950 Series Timer Control Status Registers (Upper) (TCCSH0, TCCSH1) The timer control status registers (upper) can be used to select the count clock and counter clear condition, clear the counter, enable counting and interrupts, and to check the interrupt request flag. ■ Timer Control Status Registers (Upper) (TCCSH0, TCCSH1) Figure 12.3-1 Timer Control Status Registers (Upper) (TCCSH0, TCCSH1) Address: bit TCCSH0 : 007943H TCCSH1 : 007947H Initial value 15 14 13 ECKE Reserved - R/W R/W - 12 11 10 9 8 Reserved Reserved Reserved Reserved Reserved 01100000B R/W R/W R/W R/W R/W bit15 External clock input enable bit ECKE 0 Use internal clock (prescaler output). 1 Use external clock (FRCK0/FRCK1 pin input). R/W : Readable/writable : Undefined bit : Initial value Table 12.3-2 Functions of Timer Control Status Registers (Upper) (TCCSH0, TCCSH1) Bit name Function bit15 ECKE: External clock input enable bit This bit selects the count clock for the 16-bit free-run timer. Setting the bit to "1": Selects the clock signal input via the external pin FRCK0/FRCK1. Setting the bit to "0": Selects the internal clock signal (output from the prescaler). Note: Set the ECKE bit with the free-run timer inactive (TCCSL:STOP=1). When inputting the clock from FRCK, set FRCK0 (DDR4:bit4=0) and FRCK1 (DDR4:bit5=0). bit14 Reserved bit This bit is reserved. Always write "1" to this bit. bit13 Undefined bit When read : "1" is read. When written : The bits have no effect. bit12 to bit8 Reserved bits These bits are reserved. Always write "0" to these bits. 254 FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 12 16-BIT I/O TIMER 12.3 MB90950 Series 12.3.2 Timer Control Status Registers (Lower) (TCCSL0, TCCSL1) The timer control status registers (lower) can be used to select the count clock and counter clear condition, clear the counter, enable counting and interrupts, and to check the interrupt request flag. ■ Timer Control Status Registers (Lower) (TCCSL0, TCCSL1) Figure 12.3-2 Timer Control Status Registers (Lower) (TCCSL0, TCCSL1) Address bit 7 6 5 4 3 2 1 0 TCCSL0:007942H IVF IVFE STOP MODE CLR CLK2 CLK1 CLK0 TCCSL1:007946H R/W R/W R/W R/W R/W R/W R/W R/W Initial value 00000000 B bit2 bit1 bit0 CLK2 CLK1 CLK0 Count clock cycle select bits 0 0 0 1/φ 0 0 1 2/φ 0 1 0 4/φ 0 1 1 8/φ 1 0 0 16/φ 1 0 1 32/φ 1 1 0 64/φ 1 1 1 φ: Machine clock frequency 128/φ bit3 CLR Timer clear bit 0 No effect 1 Clears the counter (TCDT = 0000H). bit4 MODE Clear condition select bit 0 Clears the counter value at a reset or with the clear bit set. 1 Clears the counter value at a reset, with the clear bit set, or with a compare register match. bit5 STOP Timer operation stop bit 0 Enables timer operation. 1 Disables (stops) timer operation. bit6 IVFE Timer overflow interrupt enable bit 0 Disables timer overflow interrupts. 1 Enables timer overflow interrupts. bit7 IVF R/W : Readable/writable Timer overflow generation flag When read When written 0 Causes no timer overflow. Clears this IVF bit. 1 Causes a timer overflow. No effect : Initial value CM44-10148-4E FUJITSU MICROELECTRONICS LIMITED 255 CHAPTER 12 16-BIT I/O TIMER 12.3 MB90950 Series Table 12.3-3 Functions of Timer Control Status Registers (Lower) (TCCSL0, TCCSL1) (1 / 2) Bit name bit7 IVF: Timer overflow generation flag This bit indicates the occurrence of a timer overflow. [Condition for setting the bit to "1"] The bit is set in either of the following two conditions: • The 16-bit free-run timer causes an overflow. • The counter is cleared upon detection of a compare match between the counter value of 16bit free-run timer 0/1 and the value of output compare register 0/4 (only with TCCSL: MODE=1). [When the bit is set to "1"] When the IVF bit is set to "1" with timer overflow interrupt requests enabled (TCCSL:IVFE=1), an interrupt request is generated. Setting the bit to "0": Clears the flag. Setting the bit to "1": Has not effect. When read by a read-modify-write instruction, the bit always returns "1". bit6 IVFE: Timer overflow interrupt enable bit This bit enables or disables interrupt requests to be generated when the timer overflow generation flag bit (TCCSL: IVF) is set to "1". Setting the bit to "1": Generates an interrupt request when the IVF bit is set to "1". Setting the bit to "0": Disables the generation of interrupt requests. STOP: Timer operation stop bit This bit enables or disables (stops) the operation of the 16-bit free-run timer. Setting the bit to "0": Enables timer operation, allowing the timer to be incremented based on the count clock set by CLK2 to CLK0. Setting the bit to "1": Stops timer operation. Note: When the 16-bit free-run timer stops operation, the output compare operation is stopped as well. MODE: Clear condition select bit This bit selects the condition for clearing the counter value of the 16-bit free-run timer (TCDT register). Setting the bit to "0": Clears the TCDT counter value in either of the following conditions: • A reset occurs. • The timer clear bit is set to "1" (TCCSL:CLR=1). Setting the bit to "1": Clears the TCDT counter value in any of the following conditions: • A reset occurs. • The timer clear bit is set to "1" (TCCSL:CLR=1). • 16-bit free-run timer 0 is cleared when the counter value of 16-bit free-run timer 0 matches the value of output compare register 0. • 16-bit free-run timer 1 is cleared when the counter value of 16-bit free-run timer 1 matches the value of output compare register 4. CLR: Timer clear bit This bit clears the counter (TCDT) of the 16-bit free-run timer in synchronization with a transition point of the counter. Setting the bit to "1": Clears the TCDT to "0000H". Setting the bit to "0": Has no effect. When read: The bit always returns "0". Notes: • To clear the counter with the 16-bit free-run timer inactive (TCCSL:STOP=1), write "0000H" directly to the TCDT. • Writing "0" to this bit before the next count clock cycle after writing "1" prevents the counter value from being initialized. bit5 bit4 bit3 256 Function FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 12 16-BIT I/O TIMER 12.3 MB90950 Series Table 12.3-3 Functions of Timer Control Status Registers (Lower) (TCCSL0, TCCSL1) (2 / 2) Bit name bit2 to bit0 CLK2, CLK1, CLK0: Count clock cycle select bits Function These bits set the count clock cycle for the 16-bit free-run timer. Note: Select the count clock cycle with the output compare unit inactive (TCCSL:STOP=1) and the input capture units inactive (ICSnm: EGn1, EGn0=00B or ICSnm:EGm1, EGm0=00B). n = 0, 2, 4, 6 m = n+1 CM44-10148-4E FUJITSU MICROELECTRONICS LIMITED 257 CHAPTER 12 16-BIT I/O TIMER 12.3 12.3.3 MB90950 Series Timer Data Registers (TCDT0, TCDT1) The timer data registers are 16-bit up-counters. • The timer data registers can read the counter value of the 16-bit free-run timer. • While the 16-bit free-run timer is inactive, the counter value can be set. ■ Timer Data Registers (TCDT0, TCDT1) Figure 12.3-3 Timer Data Registers (TCDT0, TCDT1) Address TCDT0 upper: 007941H TCDT1 upper: 007945H bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 Tn15 Tn14 Tn13 Tn12 Tn11 Tn10 Tn9 Tn8 Initial value 00000000B R/W R/W R/W R/W R/W R/W R/W R/W TCDT0 lower: 007940H TCDT1 lower: 007944H bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Initial value Tn7 Tn6 Tn5 Tn4 Tn3 Tn2 Tn1 Tn0 00000000B R/W R/W R/W R/W R/W R/W R/W R/W R/W: Readable/writable n = 0, 1 These registers allow the counter value of the 16-bit free-run timer to be read from. [Conditions for clearing the counter value] The counter value is cleared to "0000H" in any of the following conditions: • An overflow occurs. • A compare match occurs (only with TCCSL: MODE=1). • The timer clear bit in the timer control status register is set to "1" (TCCSL: CLR=1). • The timer data registers are set to "0000H" with the 16-bit free-run timer inactive. • A reset occurs. [Setting the counter value] If you set the timer by writing a counter value in the timer data registers (TCDT), access the TCDT with the timer inactive (TCCSL: STOP=1). Note: To read from or write to the timer data registers, be sure to use a word instruction (MOVW). 258 FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 12 16-BIT I/O TIMER 12.3 MB90950 Series 12.3.4 Input Capture Control Status Registers (ICS) This section describes the functions of input capture control status registers. ICS01, ICS23, ICS45, ICS67 correspond to input pins as follows: ICS01: IN0 IN1 Input capture ch.0, ch.1 ICS23: IN2 IN3 Input capture ch.2, ch.3 ICS45: IN4 IN5 Input capture ch.4, ch.5 ICS67: IN6 IN7 Input capture ch.6, ch.7 ■ Input Capture Control Status Register (ICS) Figure 12.3-4 Input Capture Control Status Register (ICS) 7 bit Address ICS01: 000050H ICS23: 000052H ICS45: 000054H ICS67: 000056H 6 ICPm ICPn 5 4 3 2 1 0 ICEm ICEn EGm1 EGm0 EGn1 EGn0 R/W R/W R/W R/W R/W R/W R/W R/W Initial value 00000000B bit1 EGn1 0 0 1 1 bit0 EGn0 0 1 0 1 Edge select bits n Detect no edge. (Operation stopped) Detect the rising edge. Detect the falling edge. Detect both edges. bit3 EGm1 0 0 1 1 bit2 EGm0 0 1 0 1 Edge select bits m Detect no edge. (Operation stopped) Detect the rising edge. Detect the falling edge. Detect both edges. bit4 ICEn 0 1 Capture interrupt enable bit n Disables input capture 0 interrupts. Enables input capture 0 interrupts. bit5 ICEm Capture interrupt enable bit m 0 Disables input capture 1 interrupts. 1 Enables input capture 1 interrupts. bit6 ICPn 0 1 Valid edge detection flag bit n When read When written Valid edge not detected for input Clears this ICP0 bit. capture 0 Valid edge detected for input No effect capture 0 bit7 ICPm 0 R/W : Readable/writable : Initial value CM44-10148-4E n = 0, 2, 4, 6 m = n+1 1 Valid edge detection flag bit m When read When written Valid edge not detected for input Clears this ICP1 bit. capture 1 Valid edge detected for input No effect capture 1 FUJITSU MICROELECTRONICS LIMITED 259 CHAPTER 12 16-BIT I/O TIMER 12.3 MB90950 Series Table 12.3-4 Functions of Input Capture Control Status Register (ICS) Bit name Function ICPm: Valid edge detection flag bit m This bit is set to "1" upon detection of a valid edge at the INm pin. If input capture m interrupt requests have been enabled (ICSnm:ICEm=1), an interrupt request is generated when the ICPm bit is set. Setting the bit to "0": Clears the flag. Setting the bit to "1": Has no effect. "1" is always read by a read-modify-write (RMW) instruction. If setting "1" to this bit and writing "0" to it occur simultaneously, writing "0" has priority. bit6 ICPn: Valid edge detection flag bit n This bit is set to "1" upon detection of a valid edge at the INn pin. • If input capture n interrupt requests have been enabled (ICSnm:ICEn=1), an interrupt request is generated when the ICPn bit is set. Setting the bit to "0": Clears the flag. Setting the bit to "1": Has no effect. "1" is always read by a read-modify-write (RMW) instruction. If setting "1" to this bit and writing "0" to it occur simultaneously, writing "0" has priority. bit5 ICEm: Capture interrupt enable bit m This bit enables or disables input capture m interrupt requests. Setting the bit to "1": Generates an interrupt request when valid edge detection flag bit m is set to "1" (ICSnm: ICPm=1). bit4 ICEn: Capture interrupt enable bit n This bit enables or disables input capture n interrupt requests. Setting the bit to "1": Generates an interrupt request when valid edge detection flag bit n is set to "1" (ICSnm: ICPn=1). bit3, bit2 EGm1, EGm0: Edge select bits m These bits select the capture trigger edge for input capture register m. • Trigger edge setting enables or disables capturing as well. Setting the bits to "00B": Detects no edge and stops capturing. bit1, bit0 EGn1, EGn0: Edge select bits n These bits select the capture trigger edge for input capture register n. • Trigger edge setting enables or disables capturing as well. Setting the bits to "00B": Detects no edge and stops capturing. bit7 n = 0, 2, 4, 6 m = n+1 Note: When using the input capture units, set the port data direction register (DDRx) of the generalpurpose I/O port to be shared, to an input port. 260 FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 12 16-BIT I/O TIMER 12.3 MB90950 Series 12.3.5 Input Capture Registers (IPCP0 to IPCP7) • Input capture registers contain counter values captured from the 16-bit free-run timer. • These are 16-bit read-only registers. There are input capture registers 0 to 7 (IPCP0 to IPCP7). ■ Input Capture Registers (IPCP0 to IPCP7) Figure 12.3-5 Input Capture Registers (IPCP0 to IPCP7) Address IPCP0 (upper): 007921H bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 Initial value MB90F952 MB90V950 CP15 CP14 CP13 CP12 CP11 CP10 CP09 CP08 00000000B XXXXXXXXB CP07 CP06 CP05 CP04 CP03 CP02 CP01 CP00 00000000B XXXXXXXXB R R R R R R R R bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 IPCP0 (lower): 007920H R R R R R R R R bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 IPCP1 (upper): 007923H CP15 CP14 CP13 CP12 CP11 CP10 CP09 CP08 00000000B XXXXXXXXB CP07 CP06 CP05 CP04 CP03 CP02 CP01 CP00 00000000B XXXXXXXXB R R R R R R R R bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 IPCP1 (lower): 007922H R R R R R R R R bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 IPCP2 (upper): 007925H CP15 CP14 CP13 CP12 CP11 CP10 CP09 CP08 00000000B XXXXXXXXB CP07 CP06 CP05 CP04 CP03 CP02 CP01 CP00 00000000B XXXXXXXXB R R R R R R R R bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 IPCP2 (lower): 007924H R R R R R R R R bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 IPCP3 (upper): 007927H CP15 CP14 CP13 CP12 CP11 CP10 CP09 CP08 00000000B XXXXXXXXB CP07 CP06 CP05 CP04 CP03 CP02 CP01 CP00 00000000B XXXXXXXXB R R R R R R R R bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 IPCP3 (lower): 007926H R R R R R R R R bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 IPCP4 (upper): 007929H CP15 CP14 CP13 CP12 CP11 CP10 CP09 CP08 00000000B XXXXXXXXB CP07 CP06 CP05 CP04 CP03 CP02 CP01 CP00 00000000B XXXXXXXXB R IPCP4 (lower): 007928H R R R R R R R bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 R R R R R R R R bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 IPCP5 (upper): 00792BH CP15 CP14 CP13 CP12 CP11 CP10 CP09 CP08 00000000B XXXXXXXXB CP07 CP06 CP05 CP04 CP03 CP02 CP01 CP00 00000000B XXXXXXXXB R IPCP5 (lower): 00792AH IPCP6 (upper): 00792DH R R R R R R bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 R R R R R R R R bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 CP15 CP14 CP13 CP12 CP11 CP10 CP09 CP08 00000000B XXXXXXXXB CP07 CP06 CP05 CP04 CP03 CP02 CP01 CP00 00000000B XXXXXXXXB R IPCP6 (lower): 00792CH R R R R R R R R bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 R R R R R R R R bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 IPCP7 (upper): 00792FH CP15 CP14 CP13 CP12 CP11 CP10 CP09 CP08 00000000B XXXXXXXXB CP07 CP06 CP05 CP04 CP03 CP02 CP01 CP00 00000000B XXXXXXXXB R IPCP7 (lower): 00792EH R : Read only CM44-10148-4E R R R R R R R bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 R R R R R R R R FUJITSU MICROELECTRONICS LIMITED 261 CHAPTER 12 16-BIT I/O TIMER 12.3 MB90950 Series When the capture trigger edge (set by ICSnm: EGn1, EGn0; or EGm1, EGm0) is detected at the IN0 to IN7 pins, input capture registers 0 to 7 corresponding to the pin contain the counter value of the 16-bit free-run timer. For input capture registers 0, 1, 4, 5, 6, and 7, however, the signal from LIN-UART can be selected as the input signal (by using the ICE:IEI bit). For details, see Section "12.3.6 Input Capture Edge Registers (ICE01, ICE23, ICE45, ICE67)". • Input capture registers are read-only; they cannot be written to. n = 0, 2, 4, 6 m = n+1 Note: To read input capture registers, be sure to use a word instruction (MOVW). 262 FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 12 16-BIT I/O TIMER 12.3 MB90950 Series 12.3.6 Input Capture Edge Registers (ICE01, ICE23, ICE45, ICE67) Input capture edge registers are used to indicate the detected edge direction and to select the external pin or LIN-UART as the input signal source. In combination with LIN-UART, the input capture edge registers can measure the baud rate during LIN slave operation. ICE01, ICE23, ICE45, ICE67 correspond to input capture channels and input pins (UART) as follows: ICE01: Input capture ch.0, ch.1 IN0 (/UART0) IN1 (/UART1) ICE23: Input capture ch.2, ch.3 IN2 IN3 ICE45: Input capture ch.4, ch.5 IN4 (/UART5) IN5 (/UART6) ICE67: Input capture ch.6, ch.7 IN6 (/UART2, 4) IN7 (/UART3) ■ Input Capture Edge Registers (ICE01, ICE23, ICE45, ICE67) Figure 12.3-6 Input Capture Edge Registers (ICE01, ICE23, ICE45, ICE67) bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 Initial value ICUS0 IEI1 IEI0 111010XXB ICE01: 000051H ICUS1 R/W R/W R R bit10 Input signal select bit 0 ICUS0 External pin IN0 input signal 0 Signal from UART0 1 bit12 Input signal select bit 1 ICUS1 0 External pin IN1 input signal Signal from UART1 1 bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 IEI3 IEI2 R R bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 ICUS5 ICUS4 IEI5 IEI4 ICE23: 000053H ICE45: 000055H Initial value 111111XXB Initial value 111100XXB R R bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 Initial value ICUS7 ICUS61 ICUS60 IEI7 IEI6 111000XXB R/W R/W ICE67: 000057H R/W R/W R/W R/W : Readable/writable : Read only R : Undefined X : Undefined value : Initial value n = 0, 2, 4, 6 m = n+1 CM44-10148-4E R R bit10 Input signal select bit 4 ICUS4 External pin IN4 input signal 0 Signal from UART5 1 bit11 Input signal select bit 5 ICUS5 External pin IN5 input signal 0 Signal from UART6 1 bit8 Detected edge display bit n IEIn Detects falling edge. 0 Detects rising edge. 1 bit9 Detected edge display bit m IEIm Detects falling edge. 0 Detects rising edge. 1 bit11 bit10 Input signal select bits 61, 60 ICUS61ICUS60 External pin IN6 input signal 0 0 Signal from UART2 0 1 0 1 Signal from UART4 1 1 bit12 Input signal select bit 7 ICUS7 External pin IN7 input signal 0 Signal from UART3 1 FUJITSU MICROELECTRONICS LIMITED 263 CHAPTER 12 16-BIT I/O TIMER 12.3 MB90950 Series Table 12.3-5 Functions of Input Capture Edge Register 01 (ICE01) Bit name bit15 Function Undefined bits When read : "1" is read. When written : The bit has no effect. bit12 ICUS1: Input signal select bit 1 This bit selects the input signal to be used to trigger of input capture 1. Setting the bit to "0": Selects external pin IN1. Setting the bit to "1": Selects LIN-UART1. bit11 Undefined bit When read : "1" is read. When written: The bit has no effect. bit10 ICUS0: Input signal select bit 0 This bit selects the input signal to be used to trigger of input capture 0. Setting the bit to "0": Selects external pin IN0. Setting the bit to "1": Selects LIN-UART0. IEI1: Detected edge display bit 1 This bit indicates the type (rising or falling) of edge detected by input capture 1. • This bit is read only. Setting the bit to"0": Indicates that the falling edge has been detected. Setting the bit to"1": Indicates that the rising edge has been detected. Note: The value of this bit remains invalid while capturing is stopped (ICS01: EG11, EG10=00B). IEI0: Detected edge display bit 0 This bit indicates the type (rising or falling) of edge detected by input capture 0. • This bit is read only. Setting the bit to"0": Indicates that the falling edge has been detected. Setting the bit to"1": Indicates that the rising edge has been detected. Note: The value of this bit remains invalid while capturing is stopped (ICS01: EG01, EG00=00B). to bit13 bit9 bit8 264 FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 12 16-BIT I/O TIMER 12.3 MB90950 Series Table 12.3-6 Functions of Input Capture Edge Register 23 (ICE23) Bit name bit15 to Undefined bits When read : "1" is read. When written : The bits have no effect. IEI3: Detected edge display bit 3 This bit indicates the type (rising or falling) of edge detected by input capture 3. • This bit is read only. Setting the bit to"0": Indicates that the falling edge has been detected. Setting the bit to"1": Indicates that the rising edge has been detected. Note: The value of this bit remains invalid while capturing is stopped (ICSnm:EGm1, EGm0=00B). (n = 2 m = n+1) IEI2: Detected edge display bit 2 This bit indicates the type (rising or falling) of edge detected by input capture 2. • This bit is read only. Setting the bit to"0": Indicates that the falling edge has been detected. Setting the bit to"1": Indicates that the rising edge has been detected. Note: The value of this bit remains invalid while capturing is stopped (ICSnm:EGn1, EGn0=00B). (n = 2 m = n+1) bit10 bit9 bit8 Function Table 12.3-7 Functions of Input Capture Edge Register 45 (ICE45) Bit name bit15 Function Undefined bits When read : "1" is read. When written : The bits have no effect. bit11 ICUS5: Input signal select bit 5 This bit selects the input signal to be used as trigger of input capture 5. Setting the bit to "0": Selects external pin IN5. Setting the bit to "1": Selects LIN-UART5. bit10 ICUS4: Input signal select bit 4 This bit selects the input signal to be used as trigger of input capture 4. Setting the bit to "0": Selects external pin IN4. Setting the bit to "1": Selects LIN-UART4. IEI5: Detected edge display bit 5 This bit indicates the type (rising or falling) of edge detected by input capture 5. • This bit is read only. Setting the bit to "0": Indicates that the falling edge has been detected. Setting the bit to "1": Indicates that the rising edge has been detected. Note: The value of this bit remains invalid while capturing is stopped (ICSnm:EGm1, EGm0=00B). (n = 4 m = n+1) IEI4: Detected edge display bit 4 This bit indicates the type (rising or falling) of edge detected by input capture 4. • This bit is read only. Setting the bit to "0": Indicates that the falling edge has been detected. Setting the bit to "1": Indicates that the rising edge has been detected. Note: The value of this bit remains invalid while capturing is stopped (ICSnm:EGn1, EGn0=00B). (n = 4 m = n+1) to bit12 bit9 bit8 CM44-10148-4E FUJITSU MICROELECTRONICS LIMITED 265 CHAPTER 12 16-BIT I/O TIMER 12.3 MB90950 Series Table 12.3-8 Functions of Input Capture Edge Register 67 (ICE67) Bit name bit15 Function Undefined bits When read : "1" is read. When written : The bits have no effect. bit12 ICUS7: Input signal select bit 7 This bit selects the input signal to be used to trigger of input capture 7. Setting the bit to "0": Selects external pin IN7. Setting the bit to "1": Selects LIN-UART3. bit11, bit10 ICUS61, ICU60: Input signal select bits 61, 60 These bits select the input signal to be used to trigger of input capture 6. Setting the bits to "00B": Selects external pin IN6. Setting the bits to "01B": Selects LIN-UART2. Setting the bits to "11B" or "10B": Selects LIN-UART4. to bit13 This bit indicates the type (rising or falling) of edge detected by input capture 7. This bit is read only. bit9 IEI7: Detected edge display bit 7 Setting the bit to "0": Indicates that the falling edge has been detected. Setting the bit to "1": Indicates that the rising edge has been detected. Note: The value of this bit remains invalid while capturing is stopped (ICS67: EG71, EG70=00B). This bit indicates the type (rising or falling) of edge detected by input capture 6. This bit is read only. bit8 IEI6: Detected edge display bit 6 Setting the bit to "0": Indicates that the falling edge has been detected Setting the bit to "1": Indicates that the rising edge has been detected. Note: The value of this bit remains invalid while capturing is stopped (ICS67: EG61, EG60=00B). Note: If the LIN-UART is selected as the input signal source (ICEnm: ICUS) for input capture channel 0, 1, 4, 5, 6, or 7, the input capture channel is used to calculate the baud rate with the LIN-UART operating in LIN slave mode. In this case, enable input capture interrupts (ICSnm: ICEn=1 or ICEm=1) and select the detection of both edges (ICSnm: EGn1, EGn0=11B or EGm1, EGm0=11B). For details on baud rate calculation, see Section "19.7.3 Operation of LIN Function (Operating Mode 3)". n = 0, 2, 4, 6 266 m = n+1 FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 12 16-BIT I/O TIMER 12.3 MB90950 Series 12.3.7 Output Compare Control Status Register (OCS) (Upper) The output compare control status register (OCS) (upper) can be used to enable the output of output compare pins, set and check their output level, and to select the output level inversion mode. OCS1, OCS3, OCS5, and OCS7 correspond to output pins and channels as follows: OCS1: OUT0 OUT1 Output compare ch.0, ch.1 OCS3: OUT2 OUT3 Output compare ch.2, ch.3 OCS5: OUT4 OUT5 Output compare ch.4, ch.5 OCS7: OUT6 OUT7 Output compare ch.6, ch.7 ■ Output Compare Control Status Register (OCS) (Upper) Figure 12.3-7 Output Compare Control Status Register (OCS) (Upper) Address bit 15 14 OCS1 : 000059 H OCS3 : 00005B H CMOD1 OCS5 : 00005DH OCS7 : 00005F H R/W 13 12 CMOD0 11 10 9 8 OTEm OTEn OTDm OTDn Initial value 01100000 B R/W R/W R/W R/W R/W bit8 OTDn Output level setting bit n 0 Sets OUTn output level to "L". OUTn pin output level 1 Sets OUTn output level to "H". bit9 OTDm Output level setting bit m 0 Sets OUTm output level to "L". OUTm pin output level 1 Sets OUTm output level to "H". bit10 OTEn Compare output enable bit n 0 General-purpose I/O port 1 Output compare output (OUTn) bit11 OTEm Compare output enable bit m 0 General-purpose I/O port 1 Output compare output (OUTm) R/W : Readable/writable : Undefined : Initial value CM44-10148-4E bit15 bit12 CMOD1 CMOD0 Output level inversion mode select bits 0 0 0 1 Set the condition for inverting the pin output level. For details, see Table 12.3-10. 1 0 1 1 n = 0, 2, 4, 6 m = n+1 FUJITSU MICROELECTRONICS LIMITED 267 CHAPTER 12 16-BIT I/O TIMER 12.3 MB90950 Series Table 12.3-9 Functions of Output Compare Control Status Register (OCS) (Upper) Bit name Function These bits set the compare match detection condition for inverting the pin output level. bit15, bit12 CMOD1, CMOD0: Output level inversion mode select bits bit14, bit13 Undefined bits When read : "1" is read. When written : The bits have no effect. bit11 OTEm: Compare output enable bit m This bit enables the output of output compare pin OUTm. Setting the bit to "1": Assigns the pin as an output compare output pin. Setting the bit to "0": Assigns the pin as a general-purpose I/O port. bit10 OTEn: Compare output enable bit n This bit enables the output of output compare pin OUTn. Setting the bit to "1": Assigns the pin as an output compare output pin. Setting the bit to "0": Assigns the pin as a general-purpose I/O port. OTDm: Output level setting bit m This bit sets the output level of the OUTm pin. • When output compare pin output is enabled (OCS: OTEm=1), the "L" or "H" level set by the OTDm bit is output at the OUTm pin. • Set the OTDm bit while output comparison is stopped (OCS: CSTm=0). When read: The bit returns the output level of the OUTm pin. OTDn: Output level setting bit n This bit sets the output level of the OUTn pin. • When output compare pin output is enabled (OCS: OTEn=1), the "L" or "H" level set by the OTDn bit is output at the OUTn pin. • Set the OTDn bit while output comparison is stopped (OCS: CSTn=0). When read: The bit returns the output level of the OUTn pin. bit9 bit8 Table 12.3-10 lists the output level inversion modes and compare match detection conditions. n = 0, 2, 4, 6 m = n+1 268 FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 12 16-BIT I/O TIMER 12.3 MB90950 Series Table 12.3-10 Output Level Inversion Mode and Compare Match Detection Controlled register name Output level inversion mode CMOD1 CMOD0 X 0 Output inverted pin name Compared register name Output inverted pin name Free-run timer 0: OCCP1 X 1 Free-run timer 0: OCCP0 Free-run timer 0: OCCP1 0 0 Free-run timer 0: OCCP3 OCS1 OUT0 Free-run timer 0: OCCP0 OUT1 Free-run timer 0: OCCP2 Free-run timer 0: OCCP3 Free-run timer 0: OCCP2 0 1 OCS3 OUT2 1 OUT3 0 Free-run timer 0: OCCP0 Free-run timer 0: OCCP2 1 1 X 0 Free-run timer 1: OCCP5 X 1 Free-run timer 1: OCCP4 Free-run timer 1: OCCP5 0 0 Free-run timer 1: OCCP7 OUT4 Free-run timer 1: OCCP4 OUT5 Free-run timer 1: OCCP6 Free-run timer 1: OCCP7 Free-run timer 1: OCCP6 0 1 1 0 OUT6 OUT7 Free-run timer 1: OCCP4 Free-run timer 1: OCCP6 1 CM44-10148-4E Free-run timer 0: OCCP0 Free-run timer 0: OCCP3 Free-run timer 0: OCCP0Free-run timer 0: OCCP2 Free-run timer 0: OCCP3 OCS5 OCS7 Compared register name 1 FUJITSU MICROELECTRONICS LIMITED Free-run timer 1: OCCP4 Free-run timer 1: OCCP7 Free-run timer 1: OCCP4 Free-run timer 1: OCCP6 Free-run timer 1: OCCP7 269 CHAPTER 12 16-BIT I/O TIMER 12.3 12.3.8 MB90950 Series Output Compare Control Status Register (OCS) (Lower) This section describes the functions of the output compare control status register. OCS0, OCS2, OCS4, and OCS6 correspond to output pins and channels as follows: OCS0: Output compare ch.0, ch.1 OCS2: Output compare ch.2, ch.3 OCS4: Output compare ch.4, ch.5 OCS6: Output compare ch.6, ch.7 ■ Output Compare Control Status Register (OCS) (Lower) Figure 12.3-8 Output Compare Control Status Register (OCS) (Lower) Address 6 bit 7 5 4 3 OCS0: 000058H IOPm IOPn IOEm IOEn OCS2: 00005AH OCS4: 00005CH OCS6: 00005EH R/W R/W R/W R/W 2 1 0 CSTm CSTn Initial value 00001100B R/W R/W bit0 CSTn Compare operation enable bit n 0 Disables operation of output compare ch n. 1 Enables operation of output compare ch n. bit1 CSTm Compare operation enable bit m 0 Disables operation of output compare ch m. 1 Enables operation of output compare ch m. bit4 IOEn Compare match interrupt enable bit n 0 Disables output compare ch n interrupts. 1 Enables output compare ch n interrupts. bit5 IOEm Compare match interrupt enable bit m 0 Disables output compare ch m interrupts. 1 Enables output compare ch m interrupts. bit6 IOPn 0 1 Compare match flag bit n When read When written Detects no compare match Clears this IOPn bit. of output compare ch n. Detects a compare match No effect of output compare ch n. bit7 IOPm R/W : Readable/writable : Undefined : Initial value 270 0 1 Compare match flag bit m When read When written Detects no compare match Clears this IOPm bit. of output compare ch m. Detects a compare match of No effect output compare ch m. n = 0, 2, 4, 6 m = n+1 FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 12 16-BIT I/O TIMER 12.3 MB90950 Series Table 12.3-11 Functions of Output Compare Control Status Register (OCS) (Lower) Bit name Function This bit is set to "1" when the value of output compare register m matches the counter value of the corresponding 16-bit free-run timer. bit7 IOPm: Compare match flag bit m If compare match interrupt requests have been enabled (OCS:IOEm=1), an interrupt request is generated when the IOPm bit is set to "1". Setting the bit to "0": Clears the flag. Setting the bit to "1": Has no effect. Note: When read by read-modify-write instruction, the bit always returns "1". If setting "1" to this bit and writing "0" to it occur simultaneously, writing "0" has priority. This bit is set to "1" when the value of output compare register n matches the counter value of the corresponding 16-bit free-run timer. If compare match interrupt requests have been enabled (OCS:IOEn=1), an interrupt request is generated when the IOPn bit is set to "1". bit6 IOPn: Compare match flag bit n bit5 IOEm: Compare match interrupt enable bit m This bit enables or disables interrupt requests to be generated when the value of output compare register m matches the counter value of the corresponding 16-bit free-run timer. Setting the bit to "1": Generates an interrupt request when compare match flag bit m (OCS:IOPm) is set to "1". bit4 IOEn: Compare match interrupt enable bit n This bit enables or disables interrupt requests to be generated when the value of output compare register n matches the counter value of the corresponding 16-bit free-run timer. Setting the bit to "1": Generates an interrupt request when compare match flag bit n (OCS:IOPn) is set to "1". bit3, bit2 Undefined bits When read : "1" is read. When written : The bits have no effect. bit1 CSTm: Compare operation enable bit m This bit enables or disables comparison of output compare ch m. Setting the bit to "0": Disables comparison. Setting the bit to "1": Enables comparison. Note: When a 16-bit free-run timer is stopped (TCCSL:STOP=1), the operation of the corresponding output compare channel is stopped. bit0 CSTn: Compare operation enable bit n This bit enables or disables comparison of output compare ch n. Setting the bit to "0": Disables comparison. Setting the bit to "1": Enables comparison. Note: When a 16-bit free-run timer is stopped (TCCSL:STOP=1), the operation of the corresponding output compare channel is stopped. Setting the bit to "0": Clears the flag. Setting the bit to "1": Has no effect. Note: When read by read-modify-write instruction, the bit always returns "1". If setting "1" to this bit and writing "0" to it occur simultaneously, writing "0" has priority. n = 0, 2, 4, 6, m = n+1 CM44-10148-4E FUJITSU MICROELECTRONICS LIMITED 271 CHAPTER 12 16-BIT I/O TIMER 12.3 12.3.9 MB90950 Series Output Compare Registers (OCCP0 to OCCP7) Output compare registers contain values to be compared with the counter value of the 16-bit free-run timer. • There are eight channels: output compare registers 0 to 7 (OCCP0 to OCCP7). ■ Output Compare Registers (OCCP0 to OCCP7) Figure 12.3-9 Output Compare Registers (OCCP0 to OCCP7) Address bit15 bit14 bit13 bit12 bit11 bit10 bit9 OCCP0 (upper): 007931H C15 C14 C13 C12 C11 bit8 C10 C09 C08 Initial value XXXXXXXXB R/W R/W R/W R/W R/W R/W R/W R/W bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 OCCP0 (lower): 007930H C07 C06 C05 C04 C03 C02 C01 C00 XXXXXXXXB R/W R/W R/W R/W R/W R/W R/W R/W bit15 bit14 bit13 bit12 bit11 bit10 bit9 OCCP1 (upper): 007933H C15 C14 C13 C12 C11 bit8 C10 C09 C08 XXXXXXXXB R/W R/W R/W R/W R/W R/W R/W R/W bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 OCCP1 (lower): 007932H C07 C06 C05 C04 C03 C02 C01 C00 XXXXXXXXB R/W R/W R/W R/W R/W R/W R/W R/W bit15 bit14 bit13 bit12 bit11 bit10 bit9 OCCP2 (upper): 007935H C15 C14 C13 C12 C11 bit8 C10 C09 C08 XXXXXXXXB R/W R/W R/W R/W R/W R/W R/W R/W bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 OCCP2 (lower): 007934H C07 C06 C05 C04 C03 C02 C01 C00 XXXXXXXXB R/W R/W R/W R/W R/W R/W R/W R/W bit15 bit14 bit13 bit12 bit11 bit10 bit9 OCCP3 (upper): 007937H C15 C14 C13 C12 C11 bit8 C10 C09 C08 XXXXXXXXB R/W R/W R/W R/W R/W R/W R/W R/W bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 OCCP3 (lower): 007936H C07 C06 C05 C04 C03 C02 C01 C00 XXXXXXXXB R/W R/W R/W R/W R/W R/W R/W R/W R/W : Readable/writable X : Undefined (Continued) 272 FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 12 16-BIT I/O TIMER 12.3 MB90950 Series (Continued) Address bit15 bit14 bit13 bit12 bit11 bit10 bit9 OCCP4 (upper): 007939H C15 C14 C13 C12 C11 bit8 C10 C09 C08 Initial value XXXXXXXXB R/W R/W R/W R/W R/W R/W R/W R/W bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 OCCP4 (lower): 007938H C07 C06 C05 C04 C03 C02 C01 C00 XXXXXXXXB R/W R/W R/W R/W R/W R/W R/W R/W bit15 bit14 bit13 bit12 bit11 bit10 bit9 OCCP5 (upper): 00793BH C15 C14 C13 C12 C11 bit8 C10 C09 C08 XXXXXXXXB R/W R/W R/W R/W R/W R/W R/W R/W bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 OCCP5 (lower): 00793AH C07 C06 C05 C04 C03 C02 C01 C00 XXXXXXXXB R/W R/W R/W R/W R/W R/W R/W R/W bit15 bit14 bit13 bit12 bit11 bit10 bit9 OCCP6 (upper): 00793DH C15 C14 C13 C12 C11 bit8 C10 C09 C08 XXXXXXXXB R/W R/W R/W R/W R/W R/W R/W R/W bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 OCCP6 (lower): 00793CH C07 C06 C05 C04 C03 C02 C01 C00 XXXXXXXXB R/W R/W R/W R/W R/W R/W R/W R/W bit15 bit14 bit13 bit12 bit11 bit10 bit9 OCCP7 (upper): 00793FH C15 C14 C13 C12 C11 bit8 C10 C09 C08 XXXXXXXXB R/W R/W R/W R/W R/W R/W R/W R/W bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 OCCP7 (lower): 00793EH C07 C06 C05 C04 C03 C02 C01 C00 XXXXXXXXB R/W R/W R/W R/W R/W R/W R/W R/W R/W : Readable/writable X : Undefined Output compare register values are compared with the counter value of the free-run timer. When a match is detected, the level at the output compare output pin is inverted and an interrupt request is generated. After a release from a reset, the values of output compare registers are indeterminate. Before enabling comparison, set the registers to the values to be compared. (OCS: CST=1) Note: To read from or write to output compare registers, be sure to use a word instruction (MOVW). CM44-10148-4E FUJITSU MICROELECTRONICS LIMITED 273 CHAPTER 12 16-BIT I/O TIMER 12.4 12.4 MB90950 Series Interrupts from 16-bit I/O Timer • An interrupt from the 16-bit I/O timer is triggered by the occurrence of an overflow from the counter of the 16-bit free-run timer, the input of a trigger edge to an input capture input pin, the input of a trigger edge for LIN slave baud rate measurement from the LIN-UART, or the detection of an output compare match. • An interrupt via an input capture channel (other than ch.6 and ch.7) or output compare channel can be used to activate DMA transfer or extended intelligent I/O service (EI2OS). An interrupt via an input capture channel (ch.6 or ch.7) can be used to activate EI2OS. ■ Interrupts from 16-bit I/O Timer Table 12.4-1 lists the interrupt control bits and interrupt trigger events of the 16-bit I/O timer. Table 12.4-1 Interrupts from 16-bit I/O Timer Timer counter overflow interrupt Input capture interrupt Output compare interrupt Interrupt request flag TCCSL: IVF ICSnm: ICPn, ICPm OCSn: IOPn, IOPm Interrupt request output enable bit TCCSL: IVFE ICSnm: ICEn, ICEm OCSn: IOEn, IOEm 16-bit free-run timer counter overflow or counter clear by compare match when MODE=1 Input of valid edge to input capture input pin, and input of trigger edge for LIN slave baud rate measurement from LINUART Interrupt generation triggers Match of output compare register value with counter value n = 0, 2, 4, 6 m = n+1 ● Timer counter overflow interrupt Case in which the timer overflow interrupt request flag is set The timer overflow generation flag in the timer control status register is set in either of the following cases. (TCCSL: IVF=1) • The 16-bit free-run timer is incremented to cause an overflow ("FFFFH" → "0000H"). • A compare match as shown below is detected when clearing by a compare match has been enabled (TCCSL: MODE=1): - The value of output compare register 0 matches the value of 16-bit free-run timer 0. - The value of output compare register 4 matches the value of 16-bit free-run timer 1. Case in which a timer overflow interrupt request is generated An interrupt request is generated when the timer overflow generation flag is set to "1" (TCCSL: IVF=1) with timer overflow interrupt requests enabled (TCCSL: IVFE=1). 274 FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 12 16-BIT I/O TIMER 12.4 MB90950 Series ● Input capture interrupt An interrupt is generated as follows when a selected valid edge (ICS: EG) is detected at an input capture pin or when the trigger edge for LIN slave baud rate measurement is input from the LIN-UART (assuming that both edges have been selected as valid edges). • Upon edge detection, the current counter value of the 16-bit free-run timer is held in the input capture register. • The valid edge detection flag in the input capture control status register is set to "1". (ICS: ICP=1) • An interrupt request is generated if the output of input capture interrupt requests has been enabled (ICS: ICE=1). ● Output compare interrupt An interrupt is generated as follows when a match is detected between the value of an output compare register and the counter value of the 16-bit free-run timer. • The output compare match flag in the output compare control status register is set to "1". (OCS:IOP=1) ■ 16-bit I/O • An interrupt request is generated if output compare interrupt requests have been enabled (OCS: IOE=1). Timer Interrupts and EI2OS Reference: See "CHAPTER 3 INTERRUPTS" for interrupt numbers, interrupt control registers, and interrupt vector addresses. ■ Support for DMA Transfer and EI2OS Features The input capture units (other than ch.6 and ch.7) and the output compare units (all channels) support DMA transfer and EI2OS features. The input capture channels (ch.6, ch.7) support only the EI2OS feature. Note, however, that other interrupts sharing the interrupt control register (ICR) must be disabled before the DMA or EI2OS feature can be used. CM44-10148-4E FUJITSU MICROELECTRONICS LIMITED 275 CHAPTER 12 16-BIT I/O TIMER 12.5 12.5 MB90950 Series Operations of 16-bit Free-run Timer The 16-bit free-run timer increments its counter from "0000H" after a release from a reset. The counter value of the 16-bit free-run timer is used as the base time for the output compare and input capture units. ■ Operations of 16-bit Free-run Timer The 16-bit free-run timer must be set as shown in Figure 12.5-1 so that it can operate. Figure 12.5-1 Settings for 16-bit Free-run Timer bit15 14 13 12 11 10 9 bit8 bit7 5 4 3 2 1 bit0 IVF IVFE STOP MODE CLR CLK2 CLK1 CLK0 TCCSH/TCCSL ECKE × TCDT 6 × × × × × × 0 0 Counter value of 16-bit free-run timer : Used bit × : Undefined bit 0 : Set to "0" [Setting the counter value of the 16-bit free-run timer] • As the 16-bit free-run timer is enabled for operation after a release from a reset (TCCSL: STOP=0), it is incremented from a counter value of "0000H". • To set the counter value of the 16-bit free-run timer, disable the operation of the 16-bit free-run timer (TCCSL: STOP=1), set the count start value in the timer data register, then enable timer operation (TCCSL: STOP=0). [Generation of a timer overflow and an interrupt request] • When the 16-bit free-run timer causes an overflow ("FFFFH" → "0000H"), the timer overflow generation flag is set to "1" (TCCSL: IVF) and the counter is incremented starting from "0000H". • An interrupt request is generated if timer overflow interrupt requests have been enabled (TCCSL: IVFE=1). 276 FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 12 16-BIT I/O TIMER 12.5 MB90950 Series [Clearing sources and timings for clearing the counter value] • Table 12.5-1 lists the clearing sources and timings for clearing the 16-bit free-run timer. Table 12.5-1 Clearing Sources and Timings for Clearing the Counter Value Clearing source Clearing timing Writing "1" to the timer clear bit in the timer control status register (TCCSL: CLR) Synchronous with the occurrence of the trigger event Writing "0000H" to an inactive timer data register Synchronous with the occurrence of the trigger event Occurrence of a reset Synchronous with the occurrence of the trigger event Occurrence of a timer overflow Synchronous with count timing Occurrence of a compare match (TCCSL: MODE=1) Synchronous with count timing • If you enable the clearing on occurrence of a compare match (TCCSL: MODE=1), the compare match flag is set to "1" (OCS: IOP) when a compare match as shown below is detected. At the same time, the counter value is cleared to "0000H" and the counter is incremented. - The value of output compare register 0 matches the value of 16-bit free-run timer 0. - The value of output compare register 4 matches the value of 16-bit free-run timer 1. Figure 12.5-2 shows the timing of clearing the counter when a match with a compare register is detected. Figure 12.5-2 16-bit Free-run Timer Clear Timing φ Count clock Compare match Counter value Compare register value φ: Machine clock CM44-10148-4E N-1 0000H N N Counter cleared FUJITSU MICROELECTRONICS LIMITED 277 CHAPTER 12 16-BIT I/O TIMER 12.5 MB90950 Series Figure 12.5-3 shows the clearing of the counter on occurrence of an overflow. Figure 12.5-3 Clearing the Counter upon Overflow Counter value Overflow FFFFH BFFFH 7FFFH 3FFFH 0000H Time Reset Figure 12.5-4 shows the clearing of the counter on occurrence of a match with a compare register. Figure 12.5-4 Clearing the Counter upon Detection of a Compare Match Counter value FFFFH BFFFH Match Match 7FFFH 3FFFH 0000H Time Reset Compare register value 278 BFFFH FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 12 16-BIT I/O TIMER 12.6 MB90950 Series 12.6 Input Capture Operations Upon detection of the valid edge of an input signal from an external input pin or upon input of the trigger edge for LIN slave baud rate measurement from the LIN-UART, the input capture unit stores the counter value of the 16-bit free-run timer in the input capture register and generates an interrupt request. ■ Input Capture Operations The input capture unit must be set as shown in Figure 12.6-1 so that it can be used. Figure 12.6-1 Settings for Input Capture Operation bit15 14 13 ICE/ICS × × × 12 11 10 ICUS1/ ICUS0/ ICUS61 ICUS7 ICUS60 9 bit8 bit7 6 5 4 3 2 1 bit0 IEIm IEIn ICPm ICPn ICEm ICEn EGm1EGm0 EGn1 EGn0 Holding the capture counter value IPCP DDR port direction register Set that bit to "0" which corresponds to the pin to be used as a capture input pin. : Used bit (Set the bits corresponding to the channels to be used.) : Used bit (These bits exist only in ICE01 and ICE67. Set the bits for baud rate measurement in LIN slave mode.) × : Undefined bit n = 0, 2, 4, 6 m = n+1 [Input capture operations] The following operations are performed when the selected valid edge (ICS: EG) is detected at an input capture pin or when the trigger edge for LIN slave baud rate measurement is input from the LIN-UART: • Upon detection, the current counter value of the 16-bit free-run timer is held in the input capture register. • The direction of the detected edge is held in the detected edge display bit. (Rising edge: IEI=1, falling edge: IEI=0) • The valid edge detection flag in the input capture control status register is set to "1". (ICS:ICP=1) • An interrupt request is generated when input capture interrupt requests have been enabled (ICS: ICE=1). • To measure the baud rate in LIN slave mode, set the LIN-UART as the input signal source (ICE: ICUS), enable input capture interrupt requests (ICS: ICE=1), and select both edges as valid edges (ICE: EG1, EG0=11B). For calculation of the baud rate, see Section "19.7.3 Operation of LIN Function (Operating Mode 3)". Figure 12.6-2 shows the timing of data capturing by the input capture unit. Figure 12.6-3 shows the input capture operations with the rising edge/falling edge set as the valid edge. Figure 12.6-4 shows the input capture operations with both edges set as valid edges. CM44-10148-4E FUJITSU MICROELECTRONICS LIMITED 279 CHAPTER 12 16-BIT I/O TIMER 12.6 MB90950 Series Figure 12.6-2 Timing of Data Capturing by Input Capture Unit φ Counter value N N+1 Input capture input Valid edge Capture signal Capture register N+1 Data captured φ: Machine clock Figure 12.6-3 Input Capture Operations (Rising Edge/Falling Edge) Counter value FFFFH BFFFH 7FFFH 3FFFH Time 0000H Reset INn (Rising edge) INm (Falling edge) Capture n Undefined Capture m Undefined 3FFFH 7FFFH n = 0, 2, 4, 6 m = n+1 Figure 12.6-4 Input Capture Operations (Both Edges) Counter value FFFFH BFFFH 7FFFH 3FFFH 0000H Time Reset INn (Both edges) Capture example Undefined BFFFH 3FFFH n = 0 to 7 280 FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 12 16-BIT I/O TIMER 12.7 MB90950 Series 12.7 Output Compare Operations The output compare unit compares the set compare value with the counter value of the 16-bit free-run timer. When a match is detected, it inverts the output level at the output compare pin and generates an interrupt request. ■ Output Compare Operations The output compare unit must be set as shown in Figure 12.7-1 so that it can be used. Figure 12.7-1 Settings for Output Compare Operations bit15 14 13 12 11 10 9 bit8 bit7 6 5 4 3 2 × × 1 bit0 CSTm CSTn CMOD0 OTEm OTEn OTDm OTDn IOPm IOPn IOEm IOEn OCSm/OCSn CMOD1 × × Set the value to compare. OCCP : Used bit : Undefined bit × : Set that bit to "1" which corresponds to the output compare pin to be used. n = 0, 2, 4, 6 m = n+1 [Output compare operations] • The output compare unit compares the output compare register value with the counter value of the 16bit free-run timer. When a match is detected, it performs the following operations: - The level at the output compare output pin is inverted. - The output compare match flag in the output compare control status register is set to "1". (OCS:IOP=1) - An interrupt request is generated if output compare interrupt requests have been enabled (OCS: IOE=1). [Output level setting and inversion timing] • The output level at the output compare pin can be set by the output level setting bit (OCS: OTD) in the output compare control status register. • When a compare match is detected, the output level is inverted in synchronization with the count timing of the 16-bit free-run timer. • Comparison with the counter value of the 16-bit free-run timer is not performed while the output compare register is being updated. CM44-10148-4E FUJITSU MICROELECTRONICS LIMITED 281 CHAPTER 12 16-BIT I/O TIMER 12.7 MB90950 Series Figure 12.7-2 to Figure 12.7-4 show output compare operations. Figure 12.7-2 Output Compare Timing φ Counter value N N+1 Compare register value N Compare match φ: Machine clock Figure 12.7-3 Inversion of the Output Level at Output Compare Output Pin Counter value N N+1 N Compare register value N+1 N Compare match signal Output pin Figure 12.7-4 Compare Operations with Output Compare Register Being Updated Counter value N N+1 N+2 N+3 No match signal generated Value of compare register 0 M N+1 Write to compare register 0 Value of compare register 1 M N+3 Write to compare register 1 Compare 0 stopped 282 FUJITSU MICROELECTRONICS LIMITED Compare 1 stopped CM44-10148-4E CHAPTER 12 16-BIT I/O TIMER 12.7 MB90950 Series ● Output inversion using two or three compare registers Depending on the settings of the output level inversion mode select bits (OCS: CMOD1, CMOD0), the output level at the OUT pin (other than OUT0 and OUT4) can be inverted when a compare match occurs on any of up to three output compare channels. See Table 12.3-10 for the settings of the output level inversion mode select bits and relevant pin output level inversion triggers. Figure 12.7-5 shows a sample waveform to be output when the output level at the OUT (m) pin is inverted upon detection of a match between output compare ch (n) and output compare ch (m). Figure 12.7-5 Sample Output Waveform of Output Compare Counter value FFFFH BFFFH 7FFFH 3FFFH Time 0000H Reset Value of compare register (n) BFFFH Value of compare register (m) 7FFFH Corresponding to compare (n) OUT(n) Corresponding to compare (n) and compare (m) OUT (m) n = 0, 2, 4, 6 CM44-10148-4E m = n+1 FUJITSU MICROELECTRONICS LIMITED 283 CHAPTER 12 16-BIT I/O TIMER 12.8 12.8 MB90950 Series Notes on Using the 16-bit I/O Timer Pay attention to the following points in using the 16-bit I/O timer. ■ Notes on Using the 16-bit I/O Timer ● Note on enabling output comparison When the 16-bit free-run timer stops counting, the output compare operation is stopped as well because the output compare operation is synchronous with the clock of the 16-bit free-run timer. Before enabling output comparison (OCS: CST=1), therefore, enable the timer operation of the 16-bit freerun timer (TCCSL: STOP=0). ● Notes on setting the 16-bit free-run timer • Do not update the count clock select bits (TCCSL: CLK2 to CLK0) during operation of the 16-bit freerun timer (TCCSL: STOP=0). • The counter value of the 16-bit free-run timer is initialized to "0000H" at a reset. • Before setting the counter value by directly writing it to the timer data register (TCDT), stop the 16-bit free-run timer (TCCSL: STOP=1). • To write to the TCDT, be sure to use a word instruction. ● Operation delay owing to synchronization As the input capture and output compare units are synchronous with the operating clock, they involve a delay in operation time. The input capture unit captures data in synchronization with the machine clock after detecting the trigger signal from the pin. The output compare unit performs comparison in synchronization with the count clock of the free-run timer. ● Delay in match detection owing to the updating of the output compare register If a match with the counter value of the 16-bit free-run timer is detected with the output compare register being updated, the match detection is nullified. In advance, read and check the count value of the free-run timer or clear the free-run timer to "0000H". When the same value is written to the timer data register (TCDT) and the compare clear register and counting is started while counting is stopped, a compare match occurs at next count. 284 FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 12 16-BIT I/O TIMER 12.9 MB90950 Series 12.9 Sample Programs for 16-bit I/O Timer This section provides sample programs for the 16-bit I/O timer. ■ Sample Program for 16-bit I/O Timer ● Processing specifications • Measure the cycle of the signal to be input to the IN0 pin. • Use 16-bit free-run timer 0 and input capture 0. • Select the rising edge as the trigger edge to be detected. • Set machine clock (φ) to 24 MHz and select 4/φ (0.17 μs) as the count clock of the free-run timer. • Use the timer overflow interrupt and the capture interrupt of input capture 0. • Count free-run timer overflow interrupts to be used for cycle calculation. • Cycle can be calculated as follows: Cycle = (overflow count × 10000H + N-th IPCP0 value - (N-1)-th IPCP0 value) × count clock cycle = (overflow count × 10000H + N-th IPCP0 value - (N-1)-th IPCP0 value) × 0.17 μs ● Coding example ICR09 ICR11 DDR2 TCCSL TCDT ICS01 IPCP0 IVF0 ICP0 DATA EQU EQU EQU EQU EQU EQU 0000B9H 0000BBH 000012H 007942H 007940H 000050H ;Interrupt control register ;Interrupt control register ;Port-2 data direction register ;Timer control status register ;Timer data register ;Input capture control status register ;Status register ;Input capture register 0 ;Timer overflow generation flag bit ;Valid edge detection flag bit EQU 007920H EQU TCCSL:7 EQU ICS01:6 DSEG ABS=00H ORG 0100H OV_CNT RW 1H DATA ENDS ;Overflow counter ; ;---------Main program--------------------------------------------CODE CSEG START: ; ;Initialize resources such as the stack ;pointer (SP) in advance. AND CCR,#0BFH ;Disable interrupts. MOV I:ICR09,#00H ;Interrupt level 0 (Highest) MOV I:ICR11,#00H ;Interrupt level 0 (Highest) MOV I:DDR2,#00000000B ;Set the port-2 direction. CM44-10148-4E FUJITSU MICROELECTRONICS LIMITED 285 CHAPTER 12 16-BIT I/O TIMER 12.9 MOV MOV MOV OR MB90950 Series I:TCCSL,#01001010B ;Enable counting and clear the counter; ;Enable overflow, interrupts; ;Select count clock 4/φ and clear the ;counter. I:ICS01,#00010001B ;Select the IN0 pin. External trigger. ;Set IPCP0 to select the rising edge. ;Set IPCP1 to select no edge detection. ;Clear each valid edge detection flag. ;Enable input capture interrupt requests. ILM,#07H ;Set PS's ILM to level 7. CCR,#40H ;Enable interrupts. LOOP: • User processing • BRA LOOP ;---------Interrupt program----------------------------------------WARI0: CLRB I:ICP0 ;Clear the valid edge detection flag. • ;Save the OV-CNT and input capture values. User processing • MOV A,0 ;Clear the overflow counter MOV OV_CNT,A ;for the next cycle measurement. RETI ;Return from the interrupt service. WARI1: CLRB I:IVF0 ;Clear the timer overflow generation flag. INC OV_CNT ;Increment the overflow counter. • User processing • RETI ;Return from the interrupt service. CODE ENDS ;---------Vector setting------------------------------------------VECT CSEG ABS=0FFH ORG 00FF78H ;Set a vector at interrupt No. #33 (21H). ;(Input capture) DSL WARI0 ORG 00FF84H ;Set a vector at interrupt No. #30 (1EH). ;(Overflow) DSL WARI1 ORG 00FFDCH ;Set a reset vector. DSL START DB 00H ;Set single-chip mode. VECT ENDS END START 286 FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 12 16-BIT I/O TIMER 12.9 MB90950 Series ■ Sample Program for Output Compare Unit ● Processing specifications • Use 16-bit free-run timer 0 and output compare 0. • Use an output compare value of "5555H", OUT0 pin, and OCCP0 register. • Invert the pin output level upon detection of a compare match and generate an interrupt at the same time. • Set machine clock (φ) to 24 MHz and select 4/φ (0.17 μs) as the count clock for the 16-bit free-run timer. ● Coding example ICR10 EQU 0000BAH ;Interrupt control register TCCS EQU 007942H ;Timer control status register TCDT EQU 007940H ;Timer data register OCS0 EQU 000058H ;Output compare control status register OCS1 EQU 000059H ;Output compare control status register OCCP0 EQU 007930H ;Output compare register IOP0 EQU OCS0:6 ;Compare match flag bit ; ;---------Main program--------------------------------------CODE CSEG START: ; ;Initialize resources such as the stack ;pointer (SP) in advance. AND CCR,#0BFH ;Disable interrupts MOV I:ICR10,#00H ;Interrupt level 0 (Highest) MOV I:TCCSL,#00001010B ;Enable counting and clear the counter. ;Disable overflow interrupts; Select count ;clock 4/φ. MOVW I:OCCP0,#5555H ;Set the compare register. MOV I:OCS0,#00010001B ;Clear the compare match flag; Enable the ;operation of output compare 0. MOV I:OCS1,#00000100B ;Enable the output of output compare 0; Set ;the pin output level to "L". MOV ILM,#07H ;Set PS's ILM to level 7. OR CCR,#40H ;Enable interrupts. LOOP: • User processing • BRA LOOP ;---------Interrupt program---------------------------------WARI: CLRB I:IOP0 ;Clear the compare match flag. • User processing • RETI ;Return from the interrupt service. CODE ENDS ;---------Vector setting------------------------------------VECT CSEG ABS=0FFH CM44-10148-4E FUJITSU MICROELECTRONICS LIMITED 287 CHAPTER 12 16-BIT I/O TIMER 12.9 VECT 288 ORG DSL ORG DSL DB ENDS END MB90950 Series 00FF7CH WARI 00FFDCH START 00H ;Set a vector at interrupt No. #32 (20H). ;Set a reset vector. ;Set single-chip mode. START FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 13 16-BIT RELOAD TIMERS This chapter describes the functions and operations of 16-bit reload timers. 13.1 Overview of 16-bit Reload Timers 13.2 Block Diagram of 16-bit Reload Timer 13.3 Configuration of 16-bit Reload Timers 13.4 Interrupts of 16-bit Reload Timers 13.5 Operations of 16-bit Reload Timers 13.6 Notes on Using 16-bit Reload Timers 13.7 Sample Programs for 16-bit Reload Timers CM44-10148-4E FUJITSU MICROELECTRONICS LIMITED 289 CHAPTER 13 16-BIT RELOAD TIMERS 13.1 13.1 MB90950 Series Overview of 16-bit Reload Timers The 16-bit reload timer has the following features: • Allowing the count clock to be selected from among three types of internal clocks and an external event clock. • Capable of selecting a software trigger or external trigger as the activation trigger. • Capable of generating an interrupt to the CPU when the 16-bit timer register underflows; therefore available as an interval timer using an interrupt. • Offering a choice of two different modes for use when the 16-bit timer register (TMR) underflows. One is one shot mode that causes the TMR register to stop counting and the other is reload mode that allows the TMR to continue counting with the 16-bit reload register value reloaded. • Supporting extended intelligent I/O service (EI2OS, for all of the 4 channels) and DMA transfer (16-bit reload timers 0 to 2 only). • The MB90950 series contains four channels of 16-bit reload timers. ■ Operation Modes of 16-bit Reload Timer Table 13.1-1 shows the operation modes of the 16-bit reload timer. Table 13.1-1 Operation Modes of 16-bit Reload Timer Count clock Activation trigger Operation when an underflow occurs Internal clock mode Software trigger External trigger One shot mode Reload mode Event count mode Software trigger One shot mode Reload mode ■ Internal Clock Mode • Setting the count clock select bits in the timer control status register (TMCSR:CSL1, CSL0) to "00B", "01B", or "10B" places the 16-bit reload timer in internal clock mode. • In internal clock mode, the 16-bit reload timer counts down in synchronization with the internal clock. • The count clock select bits in the timer control status register (TMCSR:CSL1, CSL0) can be used to select one of the three different count clock cycles. • The activation trigger is the software trigger or external trigger set for edge detection. 290 FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 13 16-BIT RELOAD TIMERS 13.1 MB90950 Series ■ Event Count Mode • Setting the count clock select bits in the timer control status register (TMCSR:CSL1, CSL0) to "11B" places the 16-bit reload timer in event count mode. • In event count mode, the 16-bit reload timer is decremented in synchronization with edge detection of the external event clock input to the TIN pin. • The activation trigger is the software trigger. • The 16-bit reload timer can be used as an interval timer using an external clock signal of a fixed period. CM44-10148-4E FUJITSU MICROELECTRONICS LIMITED 291 CHAPTER 13 16-BIT RELOAD TIMERS 13.1 MB90950 Series ■ Operation when an Underflow Occurs When the activation trigger is input, the value set in the 16-bit reload register is reloaded into the 16-bit timer register and the 16-bit reload timer starts being decrementing in synchronization with the count clock. An underflow occurs when the 16-bit timer register is decremented from "0000H" to "FFFFH". • An underflow interrupt occurs when an underflow occurs with underflow interrupts enabled (TMCSR:INTE=1). • The operation to be performed by the 16-bit reload timer when an underflow occurs is set by the reload select bit in the timer control status register (TMCSR:RELD). [One shot mode (TMCSR:RELD=0) ] When an underflow occurs in this mode, the16-bit timer register (TMR) stops counting. When the next activation trigger is input, the TMR register is reloaded with the value set in the 16-bit reload register (TMRLR) to start counting. • In one shot mode, the TOT0 to TOT3 pins output "H" or "L" level rectangular waves while the 16-bit timer register is counting. • The rectangular wave level ("H" or "L") can be set by the pin output level select bit in the timer control status register (TMCSR:OUTL). [Reload mode (TMCSR:RELD=1) ] When an underflow occurs in this mode, the 16-bit timer register (TMR) is reloaded with the value set in the 16-bit reload register and continues counting. • In reload mode, a toggle wave is output each time the TMR register underflows during counting. The toggle wave inverts the TOT pin output level. • The toggle wave level ("H" or "L") at reload timer activation can be set by the pin output level select bit in the timer control status register (TMCSR:OUTL). • The 16-bit reload timer can be used as an interval time using underflow interrupts. Table 13.1-2 16-bit Reload Timer Time Intervals Count clock Internal clock mode Event count mode Count clock cycle Time interval example 21T (0.083 μs) 0.083 μs to 5.46 ms 23T (0.33 μs) 0.33 μs to 21.8 ms 25T (1.3 μs) 1.3 μs to 87.4 ms 23T or more 0.33 μs or more T: Machine cycle The time interval examples and the values in ( ) are calculated assuming a machine clock frequency of 24 MHz. Reference: 16-bit reload timer 1 can be used as the activation trigger for the A/D converter. 292 FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 13 16-BIT RELOAD TIMERS 13.2 MB90950 Series 13.2 Block Diagram of 16-bit Reload Timer Each of 16-bit reload timers 0, 1, 2, and 3 consists of the following blocks: • Count clock generator circuit • Reload control circuit • Output control circuit • Operation control circuit • 16-bit timer register (TMR) • 16-bit reload register (TMRLR) • Timer control status register (TMCSR) ■ Block Diagram of 16-bit Reload Timer Figure 13.2-1 Block Diagram of 16-bit Reload Timer Internal data bus TMRLR 16-bit reload register Reload signal TMR 16-bit timer register Count clock generator circuit Machine clock Prescaler 3 Reload control circuit UF CLK Gate input Effective clock decision circuit φ Wait signal To A/D converter (ch.1 only) Clear Internal clock Pin TIN Input control circuit Output control circuit CLK Clock selector Output signal generator circuit Pin TOT EN External clock 3 2 Select signal Operation control circuit Function selection Reserved Reserved Reserved CSL1 CSL0 MOD2 MOD1 MOD0 OUTE OUTL RELD INTE UF CNTE TRG Timer control status register (TMCSR) CM44-10148-4E FUJITSU MICROELECTRONICS LIMITED Interrupt request output 293 CHAPTER 13 16-BIT RELOAD TIMERS 13.2 MB90950 Series ● Details of pins and other items in the block diagram The MB90950 series contains four channels of 16-bit reload timers. Listed below are the actual pin names, internal peripheral resource output, interrupt request numbers, and DMA channels of the individual channels of 16-bit reload timers. Table 13.2-1 Pin Names, Internal Peripheral Resource Output, Interrupt Numbers, and DMA Channels of 16-bit Reload Timers Reload timer 0 Reload timer 1 Reload timer 2 Reload timer 3 TIN pin P80 P10 P82 P53 TOT pin P81 P11 P83 P54 Output to internal peripheral resource — A/D converter — — #17(11H) #18(12H) #19(13H) #20(14H) 0 1 2 — Interrupt request No. DMA channel No. ● Count clock generator circuit This block generates a count clock signal to be supplied to the 16-bit timer register (TMR) based on the machine clock signal or external event clock signal. ● Reload control circuit This block reloads the 16-bit timer register (TMR) with the value set in the 16-bit reload register either to start 16-bit reload timer operation or when the TMR register underflows. ● Output control circuit This block inverts the TOT pin output when an underflow occurs and enables or disables TOT pin output. ● Operation control circuit This block activates or stops the 16-bit reload timer. ● 16-bit timer register (TMR) This block is a 16-bit down counter. When read, it returns the current count value. ● 16-bit reload register (TMRLR) This block sets the time interval for the 16-bit reload timer. The value set in the 16-bit reload register is reloaded into the 16-bit timer register (TMR) either to start 16-bit reload timer operation or when the TMR register underflows. 294 FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 13 16-BIT RELOAD TIMERS 13.2 MB90950 Series ● Timer control status register (TMCSR) This block is used to select the 16-bit reload timer operation mode, set operating conditions, select the activation trigger, activate the reload timer using the software trigger, select the reload operation mode, enable/disable interrupt requests, set the TOT pin output level, and set TOT output pins. CM44-10148-4E FUJITSU MICROELECTRONICS LIMITED 295 CHAPTER 13 16-BIT RELOAD TIMERS 13.3 13.3 MB90950 Series Configuration of 16-bit Reload Timers This section describes the pins, registers, and interrupt sources of 16-bit reload timers. ■ Pins of 16-bit Reload Timers The pins of 16-bit reload timers can serve as general-purpose I/O ports as well. Table 13.3-1 shows the functions of the pins and their required settings for use for 16-bit reload timers. Table 13.3-1 Pins of 16-bit Reload Timers (1 / 2) Pin names Pin functions Settings required for use as 16-bit reload timer General-purpose I/O port/ A/D converter trigger input/ External interrupt 12/ 16-bit reload timer input 0 • Port direction register: Set the register for use as an input port (DDR8:D80=0). • Disable external interrupts (by setting the external interrupt enable register ENIR1:EN12 = 0) or use P04 in place of P80 as an external interrupt input port (by setting the external interrupt source select register EISSR:INT12R = 0). • A/D control register: Set the register to disable trigger activation (ADCS1:STS1, STS0 = 00B/10B) P81 / CKOT / INT13R/ TOT0 General-purpose I/O port/ Clock monitor output/ External interrupt 13/ 16-bit reload timer output 0 • Disable external interrupts (by setting the external interrupt enable register ENIR1:EN13 = 0) or use P05 in place of P81 as an external interrupt input port (by setting the external interrupt source select register EISSR:INT12R = 0). • Clock output enable register: Disable clock monitor output (CLKR:CKEN=0). • Timer control status register: Enable timer output (TMCSR0:OUTE=1). P10 / TIN1 General-purpose I/O port/ 16-bit reload timer input 1 • Port direction register (DDR1): Set the register for use as an input port (DDR1:D10=0). P11 / TOT1 General-purpose I/O port/ 16-bit reload timer output 1 • Timer control status register: Enable timer output (TMCSR1:OUTE=1). P82 / SIN0 / INT14R / TIN2 General-purpose I/O port/ UART input 0/ External interrupt 14/ 16-bit reload timer input 2 • Port direction register: Set the register for use as an input port (DDR8:D82=0). • Serial control register: Set the register to disable reception (SCR0:RXE=0). • Disable external interrupts (by setting the external interrupt enable register ENIR1:EN14 = 0) or use P06 in place of P82 as an external interrupt input port (by setting the external interrupt source select register EISSR:INT12R = 0). P83 / SOT0 / TOT2 General-purpose I/O port/ UART output 0/ 16-bit reload timer output 2 • Serial control register: Set the register to disable transmission (SCR0:TXE=0). • Timer control status register: Enable timer output (TMCSR2:OUTE=1). P53 / AN11 / TIN3 General-purpose I/O port/ A/D converter analog input 11/ 16-bit reload timer input 3 • Port direction register: Set the register for use as an input port (DDR5:D53=0). • Analog input enable register: Set the register to disable analog input (ADER5:ADE11=0). P80 / ADTG / INT12R/ TIN0 296 FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 13 16-BIT RELOAD TIMERS 13.3 MB90950 Series Table 13.3-1 Pins of 16-bit Reload Timers (2 / 2) Pin names P54 / AN12 / TOT3 Pin functions General-purpose I/O port/ A/D converter analog input 12/ 16-bit reload timer output 3 CM44-10148-4E Settings required for use as 16-bit reload timer • Analog input enable register: Set the register to disable analog input (ADER5:ADE12=0). • Timer control status register: Enable timer output (TMCSR3:OUTE=1). FUJITSU MICROELECTRONICS LIMITED 297 CHAPTER 13 16-BIT RELOAD TIMERS 13.3 MB90950 Series ■ Registers of Each 16-bit Reload Timer and Their Reset Values ● Registers of 16-bit reload timer 0 Figure 13.3-1 Registers of 16-bit Reload Timer 0 and Their Reset Values bit Timer control status register: Upper byte (TMCSR0) bit Timer control status register: Lower byte (TMCSR0) bit 16-bit timer register: Upper byte (TMR0) bit 16-bit timer register: Lower byte (TMR0) bit 16-bit reload register: Upper byte (TMRLR0) bit 16-bit reload register: Lower byte (TMRLR0) 15 14 13 12 11 10 9 8 1 1 1 1 0 0 0 0 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 X X X X X X X X 7 6 5 4 3 2 1 0 X X X X X X X X 15 14 13 12 11 10 9 8 X X X X X X X X 7 6 5 4 3 2 1 0 X X X X X X X X X : Undefined ● Registers of 16-bit reload timer 1 Figure 13.3-2 Registers of 16-bit Reload Timer 1 and Their Reset Values bit Timer control status register: Upper byte (TMCSR1) bit Timer control status register: Lower byte (TMCSR1) bit 16-bit timer register: Upper byte (TMR1) bit 16-bit timer register: Lower byte (TMR1) bit 16-bit reload register: Upper byte (TMRLR1) bit 16-bit reload register: Lower byte (TMRLR1) 15 14 13 12 11 10 9 8 1 1 1 1 0 0 0 0 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 X X X X X X X X 7 6 5 4 3 2 1 0 X X X X X X X X 15 14 13 12 11 10 9 8 X X X X X X X X 7 6 5 4 3 2 1 0 X X X X X X X X X :Undefined 298 FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 13 16-BIT RELOAD TIMERS 13.3 MB90950 Series ● Registers of 16-bit reload timer 2 Figure 13.3-3 Registers of 16-bit Reload Timer 2 and Their Reset Values bit Timer control status register: Upper byte (TMCSR2) bit Timer control status register: Lower byte (TMCSR2) bit 16-bit timer register: Upper byte (TMR2) bit 16-bit timer register: Lower byte (TMR2) bit 16-bit reload register: Upper byte (TMRLR2) bit 16-bit reload register: Lower byte (TMRLR2) 15 14 13 12 11 10 9 8 1 1 1 1 0 0 0 0 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 X X X X X X X X 7 6 5 4 3 2 1 0 X X X X X X X X 15 14 13 12 11 10 9 8 X X X X X X X X 7 6 5 4 3 2 1 0 X X X X X X X X X :Undefined ● Registers of 16-bit reload timer 3 Figure 13.3-4 Registers of 16-bit Reload Timer 3 and Their Reset Values bit Timer control status register: Upper byte (TMCSR3) bit Timer control status register: Lower byte (TMCSR3) bit 16-bit timer register: Upper byte (TMR3) bit 16-bit timer register: Lower byte (TMR3) bit 16-bit reload register: Upper byte (TMRLR3) bit 16-bit reload register: Lower byte (TMRLR3) 15 14 13 12 11 10 9 8 1 1 1 1 0 0 0 0 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 X X X X X X X X 7 6 5 4 3 2 1 0 X X X X X X X X 15 14 13 12 11 10 9 8 X X X X X X X X 7 6 5 4 3 2 1 0 X X X X X X X X X :Undefined CM44-10148-4E FUJITSU MICROELECTRONICS LIMITED 299 CHAPTER 13 16-BIT RELOAD TIMERS 13.3 MB90950 Series ■ Generation of an Interrupt Request by a 16-bit Reload Timer When a 16-bit reload timer is activated and the count value in the 16-bit timer register is decremented from "0000H" to "FFFFH", the register causes an underflow and the UF bit in the timer control status register is set to "1" (TMCSR:UF). An interrupt request is generated when underflow interrupts have been enabled (TMCSR:INTE=1). 300 FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 13 16-BIT RELOAD TIMERS 13.3 MB90950 Series 13.3.1 Upper Byte of Timer Control Status Register (TMCSR:H) The upper byte of the timer control status register (TMCSR:H) is used to set the operation mode and count clock. Note that bit 7 in lower byte of the timer control status register (TMCSR:L) is also covered in this section. ■ Upper Byte of Timer Control Status Register (TMCSR:H) Figure 13.3-5 Upper Byte of Timer Control Status Register (TMCSR:H) Address: TMCSR0 TMCSR1 TMCSR2 TMCSR3 : 000061H : 000063H : 000065H : 000067H bit 15 14 Reserved Reserved R R/W 13 12 Reserved 11 10 9 8 7 Initial value CSL1 CSL0 MOD2 MOD1 MOD0 11110000 B R/W R/W R/W R/W R/W R/W bit9 bit8 bit7 MOD2 MOD1 MOD0 0 0 0 0 0 1 Operation mode select bits (internal clock mode) (CSL1, CSL0=00B, 01B, 10B) Input pin function Effective edge/level − Trigger prohibition Rising edge 0 1 0 0 1 1 Trigger input 1 X 0 1 X 1 bit9 bit8 bit7 MOD2 MOD1 MOD0 X 0 0 X 0 1 X 1 0 X 1 1 bit11 bit10 CSL1 CSL0 0 0 0 1 1 0 1 1 Falling edge Both edges "L" level Gate input "H" level Operation mode select bits (event count mode) (CSL1, CSL0=11B) Input pin function Effective edge − − Rising edge Trigger input Falling edge Both edges Count clock select bits Count clock Count clock cycle 21T 23T Internal clock mode 25T Event count mode External event clock T: Machine cycle bit12 Reserved Always write "1" to this bit. R/W − : Readable/writable bit14 : Undefined bit Reserved Always write "1" to this bit. : Initial value Reserved "1" is always read. Writing has no effect on operation. bit15 CM44-10148-4E FUJITSU MICROELECTRONICS LIMITED 301 CHAPTER 13 16-BIT RELOAD TIMERS 13.3 MB90950 Series Table 13.3-2 Functions of Upper Bytes of Timer Control Status Register (TMCSR:H) Bit name bit15 Reserved bit When the bits are read : "1" is read. When the bits are written to : Operation is not affected. bit14 Reserved bit Always write "1" to this bit. bit13 Undefined bit When the bits are read : "1" is read. When the bits are written to : Operation is not affected. bit12 Reserved bit Always write "1" to this bit. CSL1, CSL0: Count clock select bits Select the count clock for the 16-bit reload timer. When the bits are set to other than "11B": The internal clock is used for counting (internal clock mode). When the bits are set to "11B": Edges of the external event clock signal are counted (event count mode). MOD2, MOD1, MOD0: Operation mode select bits Set the operating conditions for the 16-bit reload timer. [In internal clock mode] The MOD2 bit selects the function of the input pin. When the MOD2 bit is "0": The input pin serves as a trigger input. The MOD1 and MOD0 bits select the edge to be detected. When the edge is detected, the value set in the 16-bit reload register is reloaded into the 16-bit timer register (TMR) to start the count operation of the TMR register. When the MOD2 bit is "1": The input pin serves as a gate input. The MOD1 bit is not used; the MOD0 bit selects the signal level ("H", "L") to be detected. The 16-bit timer register performs counting only when the signal level is input. [In event count mode] The MOD2 bit is not used. The input pin inputs an external event clock signal. The MOD1 and MOD0 bits are used to select the edge to be detected. bit11, bit10 bit9 to bit7 302 Function FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 13 16-BIT RELOAD TIMERS 13.3 MB90950 Series 13.3.2 Lower Byte of Timer Control Status Register (TMCSR:L) The lower byte of the timer control status register (TMCSR:L) is used to enable/disable the timer operation, set the software trigger, check whether an underflow has occurred, enable/disable underflow interrupts, select reload mode, and set the TOT pin output. ■ Lower Byte of Timer Control Status Register (TMCSR:L) Figure 13.3-6 Lower Byte of Timer Control Status Register (TMCSR:L) bit 7 Address: TMCSR0 : 000060H TMCSR1 : 000062H TMCSR2 : 000064H TMCSR3 : 000066H 6 5 4 3 2 1 0 OUTE OUTL RELD INTE UF CNTE TRG Initial value 00000000B R/W R/W R/W R/W R/W R/W R/W bit0 TRG Software trigger bit 0 Has no effect on operation. 1 Starts counting after reloading. bit1 CNTE Timer operation enable bit 0 Disables timer operation. 1 Enables timer operation (waiting for an activation trigger). bit2 UF Underflow generation flag bit When read When written to 0 No underflow The UF bit is cleared. 1 Underflow generated No effect bit3 INTE Underflow interrupt enable bit 0 Disables underflow interrupts. 1 Enables underflow interrupts. bit4 RELD Reload select bit 0 One shot mode 1 Reload mode bit5 OUTL TOT pin output level select bit One shot mode (RELD=0) Reload mode (RELD=1) 0 Outputs "H"-level rectangular wave during counting. Outputs "L"-level toggle wave at reload timer activation. 1 Outputs "L"-level rectangular wave during counting. Outputs "H"-level toggle wave at reload timer activation. bit6 TOT pin output enable bit OUTE R/W : Initial value * Pin function : Readable/writable 0 General-purpose I/O port 1 TOT output : For MOD0 (bit7), see Section "13.3.1 Upper Byte of Timer Control Status Register (TMCSR:H)". CM44-10148-4E FUJITSU MICROELECTRONICS LIMITED 303 CHAPTER 13 16-BIT RELOAD TIMERS 13.3 MB90950 Series Table 13.3-3 Functions of Lower Byte of Timer Control Status Register (TMCSR:L) (1 / 2) Bit name OUTE: TOT output pin enable bit Sets the function of the TOT pin of the 16-bit reload timer. When the bit is set to "0": The pin serves as a general-purpose I/O port. When the bit is set to "1": The pin serves as the TOT pin for the 16-bit reload timer. OUTL: TOT pin output level select bit Sets the output level of the output pin of the 16-bit reload timer. The pin level is always inverted by changing the OUTL bit regardless of the CNTE bit. <When one shot mode is selected (RELD=0)> When the bit is set to "0": The pin outputs "H"-level rectangular wave while the timer register is counting. When the bit is set to "1": The pin outputs "L"-level rectangular wave while the timer register is counting. <When reload mode is selected (RELD=1)> When the bit is set to "0": The pin outputs "L"-level toggle wave at reload timer activation. When the bit is set to "1": The pin outputs "H"-level toggle wave at reload timer activation. bit4 RELD: Reload select bit Sets the reload operation to be performed when an underflow occurs. When the bit is set to "1": When an underflow occurs, the 16-bit timer register is reloaded with the value set in the 16bit reload register to continue counting (reload mode). When the bit is set to "0": When an underflow occurs, the 16-bit timer register stops counting (one shot mode). bi3 INTE: Underflow interrupt enable bit Enables or disables underflow interrupts. An interrupt request occurs when an underflow occurs (TMCSR:UF=1) with underflow interrupts enabled (TMCSR:INTE=1). bit2 UF: Underflow generation flag bit Indicates that the timer register has caused an underflow. When the bit is set to "0": The flag is cleared. When the bit is set to "1": No effect is produced. "1" is always read by a read-modify-write instruction. CNTE: Timer operation enable bit Enables or disables the operation of the 16-bit reload timer. When the bit is set to "1": The 16-bit reload timer waits for an activation trigger. When the activation trigger is input, the reload timer causes the timer register to restart counting. When the bit is set to "0": The 16-bit reload timer causes the timer register to stop counting. bit6 bit5 bit1 304 Function FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 13 16-BIT RELOAD TIMERS 13.3 MB90950 Series Table 13.3-3 Functions of Lower Byte of Timer Control Status Register (TMCSR:L) (2 / 2) Bit name bit0 CM44-10148-4E TRG: Software trigger bit Function Activates the 16-bit reload timer by software. The software trigger function works only when the timer operation is enabled (CNTE=1). When the bit is set to "0": The setting is invalid and makes no change. When the bit is set to "1": The 16-bit timer register (TMR) is reloaded with the value set in the 16-bit reload register to start counting. When read: "0" is always read. FUJITSU MICROELECTRONICS LIMITED 305 CHAPTER 13 16-BIT RELOAD TIMERS 13.3 13.3.3 MB90950 Series 16-bit Timer Register (TMR) The 16-bit timer register is a 16-bit down counter. The current count value is read from the timer register. ■ 16-bit Timer Register (TMR) Figure 13.3-7 16-bit Timer Register (TMR) Address: bit 15 TMR0 : 007949 H TMR1 : 00794BH TMR2 : 00794DH TMR3 : 00794F H D15 D14 Address: TMR0 : 007948 H TMR1 : 00794AH TMR2 : 00794CH TMR3 : 00794EH R : Read only X : Undefined 14 R 13 12 D13 D12 D11 D10 R bit 7 R 11 R 10 R 9 8 Initial value D9 D8 XXXXXXXX B R R R 6 5 4 3 2 1 0 D7 D6 D5 D4 D3 D2 D1 D0 R R R R R R R R Initial value XXXXXXXX B When the activation trigger is input with the timer operation enabled (TMCSR:CNTE=1), the 16-bit timer register (TMR) is reloaded with the value set in the 16-bit reload register (TMRLR) to start counting. If the timer operation is disabled (TMCSR:CNTE=0), the TMR register retains its value. An underflow occurs if the TMR register decrements its value from "0000H" to "FFFFH" during counting. [In reload mode] When the 16-bit timer register (TMR) underflows, it is reloaded with the value set in the 16-bit reload register (TMRLR) to restart counting. [In one shot mode] When the 16-bit timer register (TMR) underflows, it stops counting and enters the activation trigger input wait state. The TMR register retains its value as "FFFFH". Notes: • Although the 16-bit timer register (TMR) can be read even during counting, be sure to use a word instruction (MOVW). • The 16-bit timer register (TMR) is located at the same address as that of the 16-bit reload register (TMRLR). Write access to that address writes a set value to the TMRLR register without affecting the TMR register. Read access to the address reads the current count value from the TMR register. 306 FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 13 16-BIT RELOAD TIMERS 13.3 MB90950 Series 13.3.4 16-bit Reload Register (TMRLR) The 16-bit reload register sets the value to be reloaded into the 16-bit timer register (TMR). When the activation trigger is input, the 16-bit timer register is reloaded with the value set in the 16-bit reload register to start counting. ■ 16-bit Reload Register (TMRLR) Figure 13.3-8 16-bit Reload Register (TMRLR) Address: TMRLR0 : 007949 H TMRLR1 : 00794B H TMRLR2 : 00794DH TMRLR3 : 00794F H Address: TMRLR0 : 007948 H TMRLR1 : 00794A H TMRLR2 : 00794CH TMRLR3 : 00794E H W : Write only X :Undefined bit 15 14 D15 D14 W 13 12 D13 D12 D11 D10 W bit 7 W 11 W 10 W W 9 8 Initial value D9 D8 XXXXXXXX B W W 6 5 4 3 2 1 0 D7 D6 D5 D4 D3 D2 D1 D0 W W W W W W W W Initial value XXXXXXXX B Before setting the 16-bit reload register, disable the timer operation (TMCSR:CNTE=0). After setting the 16-bit reload register, enable the timer operation (TMCSR:CNTE=1). When the activation trigger is input, the 16-bit timer register (TMR) is reloaded with the value set in the 16-bit reload register (TMRLR) to start counting. Notes: • Before writing to the 16-bit timer register, disable the 16-bit reload timer operation (TMCSR:CNTE=0). Be sure to use a word instruction (MOVW) to write to the timer register. • The 16-bit reload register (TMRLR) is located at the same address as that of the 16-bit timer register (TMR). Write access to that address writes a set value to the TMRLR register without affecting the TMR register. Read access to the address reads the current count value from the TMR register. • Read-modify-write (RMW) instructions such as INC/DEC cannot be used. CM44-10148-4E FUJITSU MICROELECTRONICS LIMITED 307 CHAPTER 13 16-BIT RELOAD TIMERS 13.4 13.4 MB90950 Series Interrupts of 16-bit Reload Timers The 16-bit reload timer generates an interrupt request when the 16-bit timer register underflows. ■ Interrupts of 16-bit Reload Timers The 16-bit timer register (TMR) underflows when its value is decremented from "0000H" to "FFFFH" during counting. When an underflow occurs, the underflow generation flag bit in the timer control status register (TMCSR:UF) is set to "1". An interrupt request occurs when underflow interrupts have been enabled (TMCSR:INTE=1) If setting "1" to the UF bit and writing "0" to it occur simultaneously, writing "0" has priority. Table 13.4-1 Interrupt Control Bits and Interrupt Sources of 16-bit Reload Timers Interrupt request flag bit Interrupt request enable bit Interrupt source 16-bit reload timer 0 16-bit reload timer 1 16-bit reload timer 2 16-bit reload timer 3 TMCSR0: UF TMCSR1: UF TMCSR2: UF TMCSR3: UF TMCSR0: INTE TMCSR1: INTE TMCSR2: INTE TMCSR3: INTE Underflow of 16-bit timer register (TMR1) Underflow of 16-bit timer register (TMR2) Underflow of 16-bit timer register (TMR3) Underflow of 16-bit timer register (TMR0) ■ 16-bit Reload Timer Interrupts, EI2OS, and DMA Transfer Reference: See "CHAPTER 3 INTERRUPTS" for interrupt numbers, interrupt control registers, and interrupt vector addresses. ■ EI2OS Features and DMA Transfer of 16-bit Reload Timers 16-bit reload timers 0 to 3 support EI2OS features. 16-bit reload timers 0 to 2 support DMA transfer. EI2OS or DMA transfer can be activated when the 16-bit timer register underflows. Note, however, that EI2OS/DMA can be used only when any other peripheral resource sharing the interrupt control register (ICR) is not using an interrupt. 16-bit reload timers 0 and 1 share ICR03; 16-bit reload timers 2 and 3 share ICR04. When 16-bit reload timers 0 to 3 use EI2OS/DMA, disable interrupts by the other 16-bit reload timers sharing the same ICR register. 308 FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 13 16-BIT RELOAD TIMERS 13.5 MB90950 Series 13.5 Operations of 16-bit Reload Timers This section describes the settings for the 16-bit reload timer and its counter operating states. ■ 16-bit Reload Timer Settings ● Settings for internal clock mode Counting the internal clock signal requires the settings in Figure 13.5-1. Figure 13.5-1 Settings for Internal Clock Mode bit15 TMCSR 14 13 Reserved Reserved 12 11 Reserved 10 9 8 7 6 5 4 3 CSL1 CSL0 MOD2 MOD1 MOD0 OUTE OUTL RELD INTE 2 1 0 UF CNTE TRG 1 1 Other than "11B" Value to be reloaded into 16-bit timer register TMRLR : Used bit 1 : Set to "1" ● Settings for event count mode The operation using external event inputs requires the settings in Figure 13.5-2. Figure 13.5-2 Settings for Event Count Mode bit15 TMCSR 14 Reserved Reserved 13 12 − Reserved 1 TMRLR 11 10 9 8 7 6 5 4 3 2 1 0 CSL1 CSL0 MOD2 MOD1 MOD0 OUTE OUTL RELD INTE UF CNTE TRG 1 1 1 Value to be reloaded into 16-bit timer register Set the bit in the port direction register (DDR) to "0" which corresponds to the pin to be used as a TIN pin. : Used bit 1 : Set to "1" CM44-10148-4E FUJITSU MICROELECTRONICS LIMITED 309 CHAPTER 13 16-BIT RELOAD TIMERS 13.5 MB90950 Series ■ Operating States of 16-bit Timer Register The operating state of the 16-bit timer register is determined by the timer operation enable bit in the timer control status register (TMCSR:CNTE) and the WAIT signal. The operating states available are the stopped state (STOP state), activation trigger input wait state (WAIT state), and executing state (RUN state). Figure 13.5-3 illustrates the transitions of the operating state of the 16-bit timer register. Figure 13.5-3 Operating State Transition Diagram Reset STOP state CNTE=0, WAIT=1 TIN pin: Input disabled TOT pin: General-purpose I/O port 16-bit timer register: Retains the value existing when the operation is stopped. The value immediately after a reset is indeterminate. CNTE=0 CNTE=0 CNTE=1 TRG=0 RUN state CNTE=1, WAIT=0 TIN pin: Serves as the input pin for the 16-bit reload timer. WAIT state CNTE=1, WAIT=1 TIN pin: Accepts trigger input only. TOT pin: Outputs the 16-bit reload register value. 16-bit timer register: Retains the value existing when the operation is stopped. The value immediately after a reset is indeterminate. TRG=1 (Software trigger) External trigger from TIN CNTE=1 TRG=1 UF=1& RELD=0 (One shot mode) TOT pin: Serves as the output pin for the 16-bit reload timer. 16-bit timer register: Operating UF=1& RELD=1 (Reload mode) LOAD CNTE=1, WAIT=0 Loads the content of the 16-bit reload register into the 16-bit timer register. TRG=1 (Software trigger) External trigger from TIN End of loading : State transition by hardware WAIT TRG CNTE UF RELD 310 : State transition by register access : WAIT signal (internal signal) : Software trigger bit (TMCSR) : Timer operation enable bit (TMCSR) : Underflow generation flag bit (TMCSR) : Reload select bit (TMCSR) FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 13 16-BIT RELOAD TIMERS 13.5 MB90950 Series 13.5.1 Operations in Internal Clock Mode In internal clock mode, you can select one of the three different operation modes by setting the operation mode select bits in the timer control status register (TMCSR: MOD2 to MOD0). The TOT pin outputs the rectangular or toggle wave depending on the operation mode and reload mode settings. ■ Settings for Internal Clock Mode • Setting the count clock select bits (CSL1, CSL0) in the timer control status register to "00B", "01B", or "10B" places the 16-bit reload timer in internal clock mode. • In internal clock mode, the 16-bit timer register counts down in synchronization with the internal clock. • You can select one of the three different count clock cycles by setting the count clock select bits (CSL1, CSL0) in the timer control status register. [Setting the value to be reloaded into the 16-bit timer register] After the 16-bit reload timer is activated, the value set in the 16-bit reload register (TMRLR) is reloaded into the 16-bit timer register (TMR). 1. Disable the timer operation (TMCSR:CNTE=0). 2. Set the 16-bit reload register to the value to be reloaded into the 16-bit timer register. 3. Enable the timer operation (TMCSR:CNTE=1). Note: It takes a time period of 1T (T: machine cycle) for the value set in the 16-bit reload register (TMRLR) to be reloaded into the 16-bit timer register (TMR) after the activation trigger is input. CM44-10148-4E FUJITSU MICROELECTRONICS LIMITED 311 CHAPTER 13 16-BIT RELOAD TIMERS 13.5 MB90950 Series ■ Operations when the 16-bit Timer Register Underflows The 16-bit timer register (TMR) underflows when its value is decremented from "0000H" to "FFFFH" during counting. • When an underflow occurs, the underflow generation flag bit in the timer control status register (TMCSR:UF) is set to "1". • An underflow interrupt occurs when the underflow interrupt enable bit in the timer control status register (TMCSR:INTE) contains "1". • The reload operation to be performed when an underflow occurs is set by the reload select bit in the timer control status register (TMCSR:RELD). [In one shot mode (TMCSR:RELD=0)] When the 16-bit timer register (TMR) underflows, it stops counting and enters the activation trigger input wait state. When the next activation trigger is input, the TMR register restarts counting. In one shot mode, the TOT pin outputs rectangular wave while the TMR register is counting. You can select the rectangular wave level ("H" or "L") by setting the pin output level select bit in the timer control status register (TMCSR:OUTL). [In reload mode (TMCSR:RELD=1)] When the 16-bit timer register (TMR) underflows, it is reloaded with the value set in the 16-bit reload register (TMRLR) to continue counting. In reload mode, a toggle wave is output each time the TMR register underflows during counting. The toggle wave inverts the TOT pin output level. The toggle wave level ("H" or "L") at reload timer activation can be selected by setting the pin output level select bit in the timer control status register (TMCSR:OUTL). ■ Operations in Internal Clock Mode Internal clock mode, you can select the operation mode by setting the operation mode select bits in the timer control status register (TMCSR:MOD2 to MOD0). Disable the timer operation by setting the timer operation enable bit in the timer control status register (TMCSR:CNTE) to "0". 312 FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 13 16-BIT RELOAD TIMERS 13.5 MB90950 Series [Software trigger mode (MOD2 to MOD0=000B)] When you select software trigger mode, set the software trigger bit in the timer control status register (TMCSR:TRG) to "1" to activate the 16-bit reload timer. When the 16-bit reload timer is activated, the 16bit timer register (TMR) is reloaded with the value set in the 16-bit reload register (TMRLR) to start counting. Note: If you set the timer operation enable bit (TMCSR:CNTE) and software trigger bit (TMCSR:TRG) in the timer control status register to "1" at the same time, the 16-bit timer register starts counting simultaneously with the activation of the 16-bit reload timer. However, timer activation at the gate input operation is enabled by the software trigger. Figure 13.5-4 Count Operations in Software Trigger Operation Mode (One Shot Mode) Counter clock Counter Reload data -1 0000 H FFFF H Reload data -1 0000 H FFFFH Data load signal UF bit set CNTE bit TRG bit T* TOT pin Activation trigger input wait state T : Machine cycle * : It takes a time period of 1T to load data from the reload register after trigger input. Figure 13.5-5 Count Operations in Software Trigger Operation Mode (Reload Mode) Counter clock Counter Reload data -1 0000 H Reload data -1 0000 H Reload data -1 0000 H Reload data -1 Data load signal UF bit set CNTE bit TRG bit T* TOT pin T : Machine cycle * : It takes a time period of 1T to load data from the reload register after trigger input. CM44-10148-4E FUJITSU MICROELECTRONICS LIMITED 313 CHAPTER 13 16-BIT RELOAD TIMERS 13.5 MB90950 Series [External trigger mode (MOD2 to MOD0=001B, 010B, 011B)] When you select external trigger mode, input an external effective edge to the TIN pin to activate the 16-bit reload timer. When the 16-bit reload timer is activated, the 16-bit timer register (TMR) is reloaded with the value set in the 16-bit reload register (TMRLR) to start counting. • You can select the rising edge, falling edge, or both edges to be detected, by setting the operation mode select bits in the timer control status register (TMCSR:MOD2 to MOD0). Note: See "Data sheet" for standard of the trigger pulse width input to the TIN pin and pulse width of a gate input. Figure 13.5-6 Count Operations in External Trigger Mode (One Shot Mode) Counter clock Counter Reload data -1 0000 H FFFF H Reload data -1 0000 H FFFF H Data load signal UF bit set CNTE bit TIN pin 2T to 2.5T * TOT pin Activation trigger input wait state T : Machine cycle * : It takes a time period of 2 to 2.5 T to load data from the reload register after external trigger input. Figure 13.5-7 Count Operations in External Trigger Mode (Reload Mode) Counter clock Counter Reload data -1 0000 H Reload data -1 0000 H Reload data -1 0000 H Reload data -1 Data load signal UF bit set CNTE bit TIN pin TOT pin 2T to 2.5T * T : Machine cycle * : It takes a time period of 2 to 2.5 T to load data from the reload register after external trigger input. 314 FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 13 16-BIT RELOAD TIMERS 13.5 MB90950 Series [External gate input operation mode (MOD2 to MOD0=1x0B, 1x1B)] When you select external gate input operation mode, set the software trigger bit in the timer control status register (TMCSR:TRG) to "1" to activate the 16-bit reload timer. When the 16-bit reload timer is activated, the value set in the 16-bit reload timer (TMRLR) is reloaded into the 16-bit timer register (TMR). • While the set gate input level remains input to the TIN pin after the 16-bit reload timer is activated, the 16-bit timer register continues counting. • You can select the gate input level ("H" or "L") by setting the operation mode select bits in the timer control status register (TMCSR: MOD2 to MOD0). Figure 13.5-8 Count Operations in External Gate Input Operation Mode (One Shot Mode) Counter clock Counter Reload data -1 0000 H -1 Reload data FFFFH -1 -1 Data load signal UF bit set CNTE bit TRG bit T* T* TIN pin TOT pin Activation trigger input wait state T : Machine cycle * : It takes a time period of 1 T to load data from the reload register after trigger input. Figure 13.5-9 Count Operations in External Gate Input Operation Mode (Reload Mode) Counter clock Counter Reload data -1 -1 -1 0000H Reload data -1 -1 Data load signal UF bit set CNTE bit TRG bit TIN pin T* TOT pin T : Machine cycle * : It takes a time period of 1T to load data from the reload register after trigger input. CM44-10148-4E FUJITSU MICROELECTRONICS LIMITED 315 CHAPTER 13 16-BIT RELOAD TIMERS 13.5 13.5.2 MB90950 Series Operations in Event Count Mode In event count mode, the activated 16-bit reload timer detects the edge of the signal input to the TIN pin to cause the 16-bit timer register to start counting. The TOT pin outputs rectangular or toggle wave depending on the operation mode and reload mode settings. ■ Settings for Event Count Mode • Setting the count clock select bits in the timer control status register (TMCSR: CSL1, CSL0) to "11B" places the 16-bit reload timer in event count mode. • In event count mode, the 16-bit timer register is decremented in synchronization with edge detection of the external event clock input to the TIN pin. [Setting the counter initial value] After the 16-bit reload timer is activated, the value set in the 16-bit reload register (TMRLR) is reloaded into the 16-bit timer register (TMR). 1. Disable the 16-bit reload timer operation (TMCSR:CNTE=0). 2. Set the 16-bit reload register to the value to be reloaded into the 16-bit timer register. 3. Enable the 16-bit reload timer operation (TMCSR:CNTE=1). Note: It takes a time period of 1 T (T: machine cycle) for the value set in the 16-bit reload register (TMRLR) to be loaded into the 16-bit timer register (TMR) after the activation trigger is input. 316 FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 13 16-BIT RELOAD TIMERS 13.5 MB90950 Series ■ Operations when the 16-bit Timer Register Underflows The 16-bit timer register (TMR) underflows when its value is decremented from "0000H" to "FFFFH" during counting. • When an underflow occurs, the underflow generation flag bit in the timer control status register (TMCSR:UF) is set to "1". • An underflow interrupt occurs when the underflow interrupt enable bit in the timer control status register (TMCSR:INTE) contains "1". • The reload operation to be performed when an underflow occurs is set by the reload select bit in the timer control status register (TMCSR:RELD). [In one shot mode (TMCSR:RELD=0)] When the 16-bit timer register (TMR) underflows, it stops counting and enters the activation trigger input wait state. When the next activation trigger is input, the TMR register restarts counting. In one shot mode, the TOT pin outputs rectangular wave while the TMR register is counting. You can select the rectangular wave level ("H" or "L") by setting the pin output level select bit in the timer control status register (TMCSR:OUTL). [In reload mode (TMCSR:RELD=1)] When the 16-bit timer register (TMR) underflows, it is reloaded with the value set in the 16-bit reload register (TMRLR) to continue counting. In reload mode, a toggle wave is output each time the TMR register underflows during counting. The toggle wave inverts the TOT pin output level. The toggle wave level ("H" or "L") at reload timer activation can be selected by setting the pin output level select bit in the timer control status register (TMCSR:OUTL). CM44-10148-4E FUJITSU MICROELECTRONICS LIMITED 317 CHAPTER 13 16-BIT RELOAD TIMERS 13.5 MB90950 Series ■ Operations in Event Count Mode Enable the 16-bit reload timer operation by setting the timer operation enable bit in the timer control status register (TMCSR:CNTE) to "1". Setting the software trigger bit in the timer control status register (TMCSR:TRG) to "1" activates the 16-bit reload timer. When the 16-bit reload timer is activated, the 16-bit timer register (TMR) is loaded with the value set in the 16-bit reload register (TMRLR) to start counting. The TMR register performs counting while detecting edges of the external event clock signal input to the TIN pin after the 16-bit reload timer is activated. Timer activation in event mode is enabled by the software trigger. • You can select the rising edge, falling edge, or both edges to be detected, by setting the operation mode select bits in the timer control status register (TMCSR: MOD2 to MOD0). Note: For "H" width and "L" width of the clock input to the TIN pin, conform to standard of "Data sheet". Figure 13.5-10 Count Operations in Event Count Mode (One Shot Mode) TIN pin Counter Reload data -1 0000H FFFFH Reload data -1 0000H FFFFH Data load signal UF bit set CNTE bit TRG bit T* TOT pin Activation trigger input wait state T : Machine cycle * : It takes a time period of 1 T to load data from the reload register after trigger input. Figure 13.5-11 Count Operations in Event Count Mode (Reload Mode) TIN pin Counter Reload data -1 0000 H Reload data -1 0000 H Reload data -1 0000H Reload data -1 Data load signal UF bit set CNTE bit TRG bit TOT pin T* T : Machine cycle * : It takes a time period of 1 T to load data from the reload register after trigger input. 318 FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 13 16-BIT RELOAD TIMERS 13.6 MB90950 Series 13.6 Notes on Using 16-bit Reload Timers Take the following precautions in using 16-bit reload timers: ■ Notes on Using 16-bit Reload Timers ● Notes on programming for setting • Before setting the 16-bit reload register (TMRLR), disable the timer operation (TMCSR:CNTE=0). • Although the 16-bit timer register (TMR) can be read even with the TMR register counting, be sure to use a word instruction for read access. • Before updating the CSL1 and CSL0 bits in the timer control status register (TMCSR), disable the timer operation (TMCSR:CNTE=0). ● Notes on interrupts • It is impossible to return from interrupt processing when the UF bit in the timer control status register (TMCSR) contains "1" with underflow interrupt output enabled (TMCSR:INTE=1). Be sure to clear the UF bit. Note, however, that the UF bit is cleared automatically when EI2OS or DMA transfer is used. • When a 16-bit reload timer uses EI2OS or DMA transfer, disable interrupts by 16-bit reload timers sharing the same interrupt control register (ICR). ● Timer operation when changing RELD bit during counter operation When changing the RELD bit during counter operation, the operation is continued and the TOT pin output value is retained until next underflow occurs. An example of operation when changing the RELD bit during counter is shown below. When the bit is "1", it indicates the reload mode. When the bit is "0", it indicates the one shot mode. CM44-10148-4E FUJITSU MICROELECTRONICS LIMITED 319 CHAPTER 13 16-BIT RELOAD TIMERS 13.6 MB90950 Series Figure 13.6-1 Changing RELD Bit from "1" to "0" in OUTL=0 and TOT="L" during Counter Operation Reload data : 0004H Count clock Counter xxxx 0003H 0004H 0002H 0001H 0000H FFFFH Data load signal UF bit set CNTE bit TRG bit RELD bit OUTL=0 "L" OUTL=1 "H" TOT pin retains its value when changing RELD bit TOT pin Reload mode One shot mode Counter operation Counter Stop Figure 13.6-2 Changing RELD Bit from "1" to "0" in OUTL=0 and TOT="H" during Counter Operation Reload data : 0004H Count clock Counter xxxx 0004H 0003H 0002H 0001H 0000H 0004H 0003H 0002H 0001H 0000H FFFFH Data load signal UF bit set CNTE bit TRG bit RELD bit TOT pin retains its value when changing RELD bit OUTL=0 TOT pin OUTL=1 Reload mode One shot mode Counter operation Counter Stop Figure 13.6-3 Changing RELD Bit from "0" to "1" during Counter Operation Reload data : 0004H Count clock Counter xxxx 0004H 0003H 0200H 0001H 0000H 0004H 0003H Data load signal UF bit set CNTE bit TRG bit RELD bit TOT pin retains its value when changing RELD bit OUTL=0 TOT pin OUTL=1 One shot mode Reload mode Counter operation 320 FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 13 16-BIT RELOAD TIMERS 13.6 MB90950 Series When changing the RELD bit simultaneously with underflow during counter operation, the counter value and TOT pin output will be as follows. (1) Changing RELD bit from "1" to "0" (reload mode to one shot mode) The counter is stopped at FFFFH for the counter value and at value which counter is stopped (initial value) for TOT pin(Example : Figure 13.6-4). (2) Changing RELD bit from "0" to "1" (one shot mode to reload mode) The counter is stopped at the reload data value for the counter value and at value which counter is stopped(initial value) for TOT value (Example : Figure 13.6-5). Figure 13.6-4 Changing RELD Bit from "1" to "0" Simultaneously with Underflow Reload data : 0002H Count clock Counter xxxx 0002H 0001H 0000H 0002H 0001H 0000H FFFFH No data load signal occurs Data load signal UF bit set CNTE bit TRG bit RELD bit TOT pin output changes to counter value stopped OUTL=0 TOT pin OUTL=1 Reload mode One shot mode Counter operation Counter Stop Figure 13.6-5 Changing RELD Bit from "0" to "1" Simultaneously with Underflow Reload data : 0002H Count clock Counter xxxx 0002H 0001H 0000H 0002H Data load signal occurs Data load signal UF bit set CNTE bit TRG bit RELD bit TOT pin output changes to counter value stopped OUTL=0 TOT pin OUTL=1 One shot mode Counter operation CM44-10148-4E Reload mode Counter Stop FUJITSU MICROELECTRONICS LIMITED 321 CHAPTER 13 16-BIT RELOAD TIMERS 13.7 13.7 MB90950 Series Sample Programs for 16-bit Reload Timers This section provides sample programs to use the 16-bit reload timer in internal clock mode and in event count mode. ■ Sample Program for Internal Clock Mode ● Processing specifications • Use 16-bit reload timer 0 to generate 24-ms interval timer interrupts. • Use the reload timer in reload mode to generate an interrupt repeatedly. • Activate the timer using a software trigger without using the external trigger input. • Neither EI2OS nor DMA is used. • The machine clock is 24 MHz; the count clock is 1.33 μs. ● Coding example ICR03 ;Interrupt control register for 16-bit ;reload timer TMCSR0 EQU 000060H ;Timer control status register TMR0 EQU 007948H ;16-bit timer register TMRLR0 EQU 007948H ;16-bit reload register UF0 EQU TMCSR0:2 ;Interrupt request flag bit CNTE0 EQU TMCSR0:1 ;Counter operation enable bit TRG0 EQU TMCSR0:0 ;Software trigger bit ;--------Main program-------------------------------------CODE CSEG ; : ;Assume that the items such as the stack ;pointer (SP) have been initialized. AND CCR,#0BFH ;Disable interrupts. MOV I:ICR03,#00H ;Interrupt level 0 (Highest) CLRB I:CNTE0 ;Suspend the counter. MOVW I:TMRLR0,#4650H ;Set 24-ms timer data. MOVW I:TMCSR0,#0000100000011011B ;Operate as an interval timer with clock 1.33 μs ;Disable external trigger and external output. ;Select reload mode and enable interrupts. ;Clear the interrupt flag and start counting. MOV ILM,#07H ;Set ILM in PS to level 7. OR CCR,#40H ;Enable interrupts. LOOP: 322 EQU 0000B3H FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 13 16-BIT RELOAD TIMERS 13.7 MB90950 Series • User processing • BRA LOOP ; ;---------Interrupt program-------------------------------WARI: CLR I:UF0 ;Clear the interrupt request flag. • • User processing • • RETI ;Return from interrupt. CODE ENDS ;---------Vector setting----------------------------------VECT CSEG ABS=0FFH ORG 00FFB8H ;Set a vector for interrupt #17(11H). DSL WARI ORG 00FFDCH ;Set a reset vector. DSL START DB 00H ;Set single-chip mode. VECT ENDS END START ■ Sample Program for Event Count Mode ● Processing specifications • Use 16-bit reload timer 0 to generate an interrupt when it counts the rising edge of the pulse input to the external event input pin 10000 times. • Operate the reload timer in one shot mode. • Select the rising edge as the external trigger input. • Neither EI2OS nor DMA is used. ● Coding example ICR03 ;Interrupt control register for 16-bit ;reload timer TMCSR0 EQU 000060H ;Timer control status register TMR0 EQU 007948H ;16-bit timer register TMRLR0 EQU 007948H ;16-bit reload register DDR8 EQU 000018H ;Port data register UF0 EQU TMCSR0:2 ;Interrupt request flag bit CNTE0 EQU TMCSR0:1 ;Counter operation enable bit TRG0 EQU TMCSR0:0 ;Software trigger bit ;---------Main program------------------------------------CODE CSEG CM44-10148-4E EQU 0000B3H FUJITSU MICROELECTRONICS LIMITED 323 CHAPTER 13 16-BIT RELOAD TIMERS 13.7 ; MB90950 Series : ;Assume that the items such as the stack ;pointer (SP) have been initialized. ;Assume that no A/D converter is used or ;that the reload timer is used in software ;activation mode (ACS1: STS1, 0 = 00B). AND CCR,#0BFH ;Disable interrupts. MOV I:ICR03,#00H ;Interrupt level 0 (Highest) MOV I:DDR8,00H ;Set the P80/TIN0 pins for input. CLRB I:CNTE0 ;Suspend the counter. MOVW I:TMRLR0,#2710H;Set the reload value to 10,000 (times). MOVW I:TMCSR0,#0000110001001011B ;Operate the counter and select the rising ;edge. ;Disable external output. ;Select one shot mode and enable ;interrupts. ;Clear the interrupt flag and start ;counting. MOV ILM,#07H ;Set the ILM in PS to level 7. OR CCR,#40H ;Enable interrupts. LOOP: • User processing • BRA LOOP ; ;---------Interrupt program-------------------------------WARI: CLR I:UF0 ;Clear the interrupt request flag. • • User processing • • RETI ;Return from interrupt. CODE ENDS ;---------Vector setting----------------------------------VECT CSEG ABS=0FFH ORG 00FFB8H ;Set a vector for interrupt #17(11H). DSL WARI ORG 00FFDCH ;Set a reset vector. DSL START DB 00H ;Set single-chip mode. VECT ENDS END START 324 FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 14 WATCH TIMER This chapter explains the functions and operations of the watch timer. 14.1 Overview of Watch Timer 14.2 Block Diagram of Watch Timer 14.3 Configuration of Watch Timer 14.4 Interrupt of Watch Timer 14.5 Operating Explanation of Watch Timer 14.6 Example Program of Watch Timer CM44-10148-4E FUJITSU MICROELECTRONICS LIMITED 325 CHAPTER 14 WATCH TIMER 14.1 14.1 MB90950 Series Overview of Watch Timer The watch timer is a 15-bit free-run counter that counts up in synchronization with the sub clock. • The interval time can be selected from 8 types and an interrupt request can be generated for each interval time. • An operation clock is supplied to the timer for sub clock oscillation stabilization wait time and to the watchdog timer. • The sub clock is always used as a count clock regardless of the settings of the clock selection register (CKSCR). ■ Interval Timer Function • When the watch timer reaches the interval time set by the interval time selection bits (WTC: WTC2 to WTC0), the bit corresponding to the interval time of the watch timer counter generates an overflow (carry) and the overflow flag bit is set (WTC:WTOF = 1). • If an interrupt due to the generation of overflow is enabled (WTC:WTIE=1), an interrupt request is generated when the overflow flag bit is set (WTC:WTOF=1). • The interval time of the watch timer can be selected from 8 types shown in Table 14.1-1. Table 14.1-1 Interval Time of Watch Timer Sub clock cycle Interval time 28/SCLK (20.48 ms) 29/SCLK (40.96 ms) 210/SCLK (81.92 ms) 1/SCLK (80 μs) 211/SCLK (163.84 ms) 212/SCLK (327.68 ms) 213/SCLK (655.36 ms) 214/SCLK (1310.72 ms) 215/SCLK (2621.44 ms) SCLK: Sub clock frequency The value within parentheses indicates a calculation example of sub clock operating at 12.5 kHz. 326 FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 14 WATCH TIMER 14.1 MB90950 Series ■ Cycle of Clock Supply The watch timer supplies an operation clock to the timer for sub clock oscillation stabilization wait time and to the watchdog timer. Table 14.1-2 shows the cycles of clocks supplied from the watch timer. Table 14.1-2 Cycle of Clock Supplied from Watch Timer Clock supply to Clock cycle Timer for sub clock oscillation stabilization wait time 214/SCLK (1.31 s) 210/SCLK (82 ms) 213/SCLK (655 ms) Watchdog timer 214/SCLK (1.31 s) 215/SCLK (2.26 s) SCLK: Sub clock frequency The value within parentheses indicates a calculation example of sub clock operating at 12.5 kHz. Note: Sub clock SCLK frequency is the value of the CR clock that is dividing by 8 or 4. Division ratio is set by SCDS bit in PLL/sub clock control register (PSCCR). CM44-10148-4E FUJITSU MICROELECTRONICS LIMITED 327 CHAPTER 14 WATCH TIMER 14.2 14.2 MB90950 Series Block Diagram of Watch Timer The watch timer consists of the following blocks: • Watch timer counter • Counter clear circuit • Interval timer selector • Watch timer control register (WTC) ■ Block Diagram of Watch Timer Figure 14.2-1 Block Diagram of Watch Timer To watchdog timer Watch timer counter SCLK × 21 × 2 2 × 2 3 × 2 4 × 2 5 × 2 6 × 27 × 28 × 29 × 210 × 211 × 212 × 213 × 214 × 215 OF OF OF OF Power-on reset Transition to hardware standby Transition to stop mode OF OF Counter clear circuit OF OF To sub clock oscillation stabilization wait time Interval timer selector Watch timer interrupt OF : Overflow SCLK : Sub clock WDCS SCE WTIE WTOF WTR WTC2 WTC1 WTC0 Watch timer control register (WTC) The actual interrupt request number of the watch timer is as follows: Interrupt request number: #27 (1BH) ● Watch timer counter This counter is a 15-bit up counter that uses the sub clock (SCLK) as a count clock. ● Counter clear circuit The counter clear circuit clears the watch timer counter. 328 FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 14 WATCH TIMER 14.2 MB90950 Series ● Interval timer selector The interval timer selector sets the overflow flag bit when the watch timer counter reaches the interval time value by referring to the interval time set in the watch timer control register (WTC). ● Watch timer control register (WTC) The watch timer control register selects the interval time, clears the watch timer counter, enables or disables interrupt, checks the overflow (carry) state, and clears the overflow flag bit. CM44-10148-4E FUJITSU MICROELECTRONICS LIMITED 329 CHAPTER 14 WATCH TIMER 14.3 14.3 MB90950 Series Configuration of Watch Timer This section shows the registers and interrupt sources of the watch timer. ■ List of Registers and Initial Values of Watch Timer Figure 14.3-1 List of Registers and Initial Values of Watch Timer bit Watch timer control register (WTC) 7 6 5 4 3 2 1 0 1 × 0 0 1 0 0 0 X: Undefined ■ Generation of Interrupt Request in Watch Timer • When the interval time that has been set by the interval time selection bits (WTC: WTC2 to WTC0) is reached, the overflow flag bit (WTC:WTOF) is set to "1". • If interrupt by a watch timer counter overflow (carry) is enabled (WTC:WTIE=1), an interrupt request is generated when the overflow flag bit is set (WTC:WTOF=1). 330 FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 14 WATCH TIMER 14.3 MB90950 Series 14.3.1 Watch Timer Control Register (WTC) The functions of the watch timer control register (WTC) are shown below. ■ Watch Timer Control Register (WTC) Figure 14.3-2 Watch Timer Control Register (WTC) Address 0000AAH bit 7 6 5 4 3 2 1 0 Initial value WDCS SCE WTIE WTOF WTR WTC2 WTC1 WTC0 R/W R 1X001000B R/W R/W R/W R/W R/W R/W bit2 bit1 bit0 WTC2 WTC1 WTC0 Interval time selection bits 0 0 0 28/SCLK (20.48 ms) 0 0 1 29/SCLK (40.96 ms) 0 1 0 210/SCLK (81.92 ms) 0 1 1 211/SCLK (163.84 ms) 1 0 0 212/SCLK (327.68 ms) 1 0 1 213/SCLK (655.36 ms) 1 1 0 214/SCLK (1310.72 ms) 1 bit3 1 1 215/SCLK (2621.44 ms) WTR 0 1 Watch timer clear bit Read ⎯ Always "1" is read Write Clears watch timer counter No effect bit4 WTOF 0 1 Overflow flag bit Read Write No overflow of the bit corresponding to a set Clears WTOF bit interval time occurred Overflow of the bit corresponding to a set No effect interval time occurred bit5 Overflow interrupt enable bit WTIE 0 Disables interrupt request 1 Enables interrupt request bit6 Oscillation stabilization wait time end bit SCE 0 In oscillation stabilization wait state 1 Oscillation stabilization wait time end bit7 R/W R X SCLK : Readable/writable : Read only : Undefined : Sub clock : Initial value CM44-10148-4E WDCS 0 1 Watchdog clock selection bit (Input clock of watchdog timer) Main or PLL clock mode Sub clock mode Watch timer Set "0" Time-base timer The value within parentheses indicates a calculation example of sub clock operating at 12.5 kHz. FUJITSU MICROELECTRONICS LIMITED 331 CHAPTER 14 WATCH TIMER 14.3 MB90950 Series Table 14.3-1 Functions of Watch Timer Control Register (WTC) Bit name bit7 WDCS: Watchdog clock selection bit bit6 SCE: Oscillation stabilization wait time end bit bit5 bit4 WTIE: Overflow interrupt enable bit WTOF: Overflow flag bit Function This bit selects the operation clock of the watchdog timer. <Main clock mode or PLL clock mode> When set to "0": Selects the output of watch timer as an operation clock of watchdog timer. When set to "1": Selects the output of time-base timer as an operation clock of watchdog timer. <Sub clock mode> Always set this bit to "0" to select the output of the watch timer. Note: As the watch timer and time-base timer operate asynchronously, the watchdog timer may run fast when WDCS bit is changed from "0" to "1". The watchdog timer must be cleared before and after changing this bit. This bit indicates that the oscillation stabilization wait time of the sub clock ends. When cleared to "0": Indicates that the sub clock is in oscillation stabilization wait state. When set to "1" : Indicates that the oscillation stabilization wait time ends. The oscillation stabilization wait time of the sub clock is fixed at 214/SCLK (SCLK: sub clock frequency). This bit enables or disables generation of an interrupt request due to an overflow (carry) of the watch timer counter. When set to "0": No interrupt request is generated even if an overflow occurs (WTOF=1). When set to "1": An interrupt request is generated if an overflow occurs (WTOF=1). This bit is set to "1" when the counter value of the watch timer reaches the value set by the interval time selection bit. If interrupt request is enabled (WTIE=1), an interrupt request is generated when an overflow (carry) occurs (WTOF=1). When set to "0": Clears the flag. When set to "1": No effect. • The overflow flag bit is set to "1" if an overflow (carry) of the bit of the watch timer counter corresponding to the interval time set by the interval time selection bits (WTC2 to WTC0) occurs. • For a read-modify-write (RMW) instruction, "1" is always read. bit3 bit2 to bit0 332 WTR: Watch timer clear bit This bit clears the watch timer counter. When set to "0": Clears the watch timer counter to "0000H". When set to "1": No effect. When read : Always "1" is read. WTC2, WTC1, WTC0: Interval time selection bits These bits set the interval time of the watch timer. • When the interval time set by the WTC2 to WTC0 bits is reached, the corresponding bit of the watch timer counter generates an overflow (carry) and the overflow flag bit is set (WTC:WTOF=1). • When setting WTC2 to WTC0 bits, set WTOF bit to "0" at the same time. FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 14 WATCH TIMER 14.4 MB90950 Series 14.4 Interrupt of Watch Timer When the interval time is reached, the overflow flag bit is set to "1" and an interrupt request is generated if interrupt of the watch timer is enabled. ■ Interrupt of Watch Timer Table 14.4-1 shows the interrupt control bits and interrupt sources of the watch timer. Table 14.4-1 Interrupt Control Bits of Watch Timer Watch timer Interrupt source Interval time of watch timer counter Interrupt request flag bit WTC: WTOF (overflow flag bit) Interrupt source enable bit WTC: WTIE • When the value set by the interval time selection bits (WTC2 to WTC0) in the watch timer control register (WTC) is reached, the overflow flag bit in WTC is set to "1" (WTC:WTOF=1). • If interrupt is enabled for the watch timer (WTC:WTIE=1), an interrupt request is generated when the overflow flag bit is set (WTC:WTOF=1). • To cancel an interrupt request, set WTOF bit to "0" by interrupt process. ■ Watch Timer Interrupt and EI2OS/DMA Transfer Function • The watch timer does not support the extended intelligent I/O service (EI2OS) function and DMA transfer. • For interrupt number, interrupt control register and interrupt vector address, see "CHAPTER 3 INTERRUPTS". CM44-10148-4E FUJITSU MICROELECTRONICS LIMITED 333 CHAPTER 14 WATCH TIMER 14.5 14.5 MB90950 Series Operating Explanation of Watch Timer The watch timer operates as an interval timer or a timer for sub clock oscillation stabilization wait time. It also supplies an operation clock to the watchdog timer. ■ Watch Timer Counter The watch timer counter continues to count up in synchronization with the sub clock (SCLK) while the sub clock (SCLK) is operating. ● Clearing watch timer counter The watch timer counter will be cleared to "0000H" in the following cases: • Power-on reset • Transition to sleep mode • Setting the watch timer clear bit (WTR) in the watch timer control register (WTC) to "0" Note: When a watch timer counter clear occurs, it affects the interrupt operation of the watchdog timer and interval timer that use outputs from the watch timer counter. When clearing the watch timer by setting the watch timer clear bit (WTR) in the watch timer control register (WTC) to "0", do so after setting the overflow interrupt enable bit (WTIE) in WTC to "0" to disable watch timer interrupt. In addition, before enabling the interrupt, clear an interrupt request by setting the overflow bit (WTOF) in WTC to "0". ■ Interval Timer Function The watch timer can be used as an interval timer by generating an interrupt at each interval time. ● Setting for when using watch timer as interval timer To make the watch timer operate as an interval timer, the setting shown in Figure 14.5-1 is required. Figure 14.5-1 Setting of Watch Timer bit7 WTC 6 5 4 3 2 1 0 WDCS SCE WTIE WTOF WTR WTC2 WTC1 WTC0 : Used bit : Unused bit • When the value set by the interval time selection bits (WTC1, WTC0) in the watch timer control register (WTC) is reached, the overflow flag bit in WTC is set to "1" (WTC:WTOF=1). • When the overflow flag bit is set (WTC:WTOF = 1) with the overflow interrupt of the watch timer counter enabled (WTC:WTIE = 1), an interrupt request is generated. • The overflow flag bit (WTC:WTOF) is set when the interval time is reached from the timing, as a starting point, at which the watch timer is cleared last. 334 FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 14 WATCH TIMER 14.5 MB90950 Series ● Clearing overflow flag bit (WTC:WTOF) When the mode transits to stop mode, WTOF bit is cleared concurrently with the mode transition because the watch timer is used as the timer for oscillation stabilization wait time of the sub clock. ■ Setting for Operation Clock of Watchdog Timer The watchdog clock selection bit (WDCS) in the watch timer control register (WTC) can be used to set the clock input source of the watchdog timer. When using the sub clock as the machine clock, be sure to set the WDCS bit to "0" to select watch timer output. ■ Timer for Oscillation Stabilization Wait Time of Sub Clock When the watch time returns from power-on reset or stop mode, it functions as a timer for oscillation stabilization wait timer of the sub clock. The sub clock oscillation stabilization wait time is fixed at 214/SCLK (SCLK: sub clock). CM44-10148-4E FUJITSU MICROELECTRONICS LIMITED 335 CHAPTER 14 WATCH TIMER 14.6 14.6 MB90950 Series Example Program of Watch Timer This section shows an example program of the watch timer. ■ Example Program of Watch Timer ● Processing specification An interrupt at 213/SCLK (SCLK: sub clock) interval is generated repeatedly. The interval time of this case is approximately 655.36 ms (when the sub clock operates at 12.5 kHz). ● Coding example ICR08 EQU 0000B8H ;Interrupt control register WTC EQU 0000AAH ;Watch timer control register WTOF EQU WTC:4 ;Overflow flag bit ; ;---------Main program--------------------------------------CODE CSEG START: ; ;Stack pointer (SP) etc. should be ;initialized in advance AND CCR,#0BFH ;Disables interrupt MOV I:ICR07,#00H ;Interrupt level 0 (highest) MOV I:WTC,#10100101B ;Enables interrupt ;Clears overflow flag ;Clears watch timer counter ;213/SCLK (655.36 ms) MOV ILM,#07H ;Sets ILM in PS to level 7 OR CCR,#40H ;Enables interrupt LOOP: • User processing • BRA LOOP ;---------Interrupt program---------------------------------WARI: CLRB I:WTOF ;Clears overflow flag • User processing • RETI ;Returns from interrupt processing CODE ENDS ;---------Vector setting------------------------------------VECT CSEG ABS=0FFH ORG 00FF90H ;Sets vector to interrupt #27 (1BH) 336 FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 14 WATCH TIMER 14.6 MB90950 Series VECT CM44-10148-4E DSL ORG DSL DB ENDS END WARI 00FFDCH START 00H ;Resets vector setting ;Sets to single chip mode START FUJITSU MICROELECTRONICS LIMITED 337 CHAPTER 14 WATCH TIMER 14.6 338 MB90950 Series FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 15 8/16-BIT PPG TIMER This chapter explains the functions and operations of the 8/16-bit PPG timer. 15.1 Overview of 8/16-bit PPG Timer 15.2 Block Diagram of 8/16-bit PPG Timer 15.3 Configuration of 8/16-bit PPG Timer 15.4 Interrupts of 8/16-bit PPG Timer 15.5 Operating Explanation of 8/16-bit PPG Timer 15.6 Notes on Using 8/16-bit PPG Timer CM44-10148-4E FUJITSU MICROELECTRONICS LIMITED 339 CHAPTER 15 8/16-BIT PPG TIMER 15.1 15.1 MB90950 Series Overview of 8/16-bit PPG Timer The 8/16-bit PPG timer is the 2-channel reload timer module (PPG0, PPG1) that can perform pulse output of any cycle and duty ratio. The following operation can be performed by combining the 2 channel modules. • 8-bit PPG output 2-channel independent operation mode • 16-bit PPG output operation mode • 8+8-bit PPG output operation mode The MB90950 series has eight built-in 8/16-bit PPG timers. This section explains the functions of PPG0/1. PPG2/3, PPG4/5, PPG6/7, PPG8/9, PPGA/B, PPGC/D, and PPGE/F have the same functions as PPG0/1. ■ Functions of 8/16-bit PPG Timer The 8/16-bit PPG timer consists of four 8-bit reload registers (PRLH0/PRLL0, PRLH1/PRLL1) and two PPG down counters (PCNT0, PCNT1). • The "H" width and "L" width of an output pulse can be set separately, so the output pulse cycle and duty ratio can be set arbitrarily. • The count clock can be selected from six internal clocks. • The 8/16-bit PPG timer can be used as an interval timer by generating an interrupt request at each interval time. • An external circuit enables the 8/16-bit PPG timer to be used as a D/A converter. 340 FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 15 8/16-BIT PPG TIMER 15.1 MB90950 Series ■ Operation Modes for 8/16-bit PPG Timer ● 8-bit PPG output 2-channel independent operation mode This mode makes each 2-channel module (PPG0, PPG1) operate as an independent 8-bit PPG timer. Table 15.1-1 shows the interval times in 8-bit PPG output 2-channel independent operation mode. Table 15.1-1 Interval Times in 8-bit PPG Output 2-channel Independent Operation Mode PPG0, PPG1 Count clock cycle Interval time Output pulse time 1/φ (31.25 ns) 1/φ to 28/φ 2/φ to 29/φ 2/φ (62.5 ns) 2/φ to 29/φ 22/φ to 210/φ 22/φ (125 ns) 22/φ to 210/φ 23/φ to 211/φ 23/φ (250 ns) 23/φ to 211/φ 24/φ to 212/φ 24/φ (500 ns) 24/φ to 212/φ 25/φ to 213/φ 29/HCLK (128 μs) 29/HCLK to 217/HCLK 210/HCLK to 218/HCLK HCLK : Oscillation clock φ : Machine clock frequency The value within parentheses is the value operating at HCLK=4 MHz and φ=32 MHz. ● 16-bit PPG output operation mode This mode concatenates the 2-channel modules (PPG0, PPG1) to operate as a 16-bit 1-channel PPG timer. Table 15.1-2 shows the interval times in 16-bit PPG output operation mode. Table 15.1-2 Interval Times in 16-bit PPG Output Operation Mode Count clock cycle Interval time Output pulse time 1/φ (31.25 ns) 1/φ to 216/φ 2/φ to 217/φ 2/φ (62.5 ns) 2/φ to 217/φ 22/φ to 218/φ 22/φ (125 ns) 22/φ to 218/φ 23/φ to 219/φ 23/φ (250 ns) 23/φ to 219/φ 24/φ to 220/φ 24/φ (500 ns) 24/φ to 220/φ 25/φ to 221/φ 29/HCLK (128 μs) 29/HCLK to 225/HCLK 210/HCLK to 226/HCLK HCLK : Oscillation clock φ : Machine clock frequency The value within parentheses is the value operating at HCLK=4 MHz and φ=32 MHz. CM44-10148-4E FUJITSU MICROELECTRONICS LIMITED 341 CHAPTER 15 8/16-BIT PPG TIMER 15.1 MB90950 Series ● 8+8 bit PPG output operation mode This mode makes the PPG0 of the 2-channel modules operate as an 8-bit prescaler, operated by inputting the PPG0 underflow output as PPG1 count clock. Table 15.1-3 shows the interval times in 8+8-bit PPG output operation mode. Table 15.1-3 Interval Times in 8+8-bit PPG Output Operation Mode PPG0 PPG1 Count clock cycle Interval time Output pulse time Interval time Output pulse time 1/φ (31.25 ns) 1/φ to 28/φ 2/φ to 29/φ 1/φ to 216/φ 2/φ to 217/φ 2/φ (62.5 ns) 2/φ to 29/φ 22/φ to 210/φ 2/φ to 217/φ 22/φ to 218/φ 22/φ (125 ns) 22/φ to 210/φ 23/φ to 211/φ 22/φ to 218/φ 23/φ to 219/φ 23/φ (250 ns) 23/φ to 211/φ 24/φ to 212/φ 23/φ to 219/φ 24/φ to 220/φ 24/φ (500 ns) 24/φ to 212/φ 25/φ to 213/φ 24/φ to 220/φ 25/φ to 221/φ 29/HCLK (128 μs) 29/HCLK to 217/HCLK 210/HCLK to 218/HCLK 29/HCLK to 225/HCLK 210/HCLK to 226/HCLK HCLK : Oscillation clock φ : Machine clock frequency The value within parentheses is the value operating at HCLK=4 MHz and φ=32 MHz. 342 FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 15 8/16-BIT PPG TIMER 15.2 MB90950 Series 15.2 Block Diagram of 8/16-bit PPG Timer The MB90950 series contains eight built-in 8/16-bit PPG timers (with two channels each). One 8/16-bit PPG timer consists of 2-channel 8-bit PPG timers. This section shows the block diagrams of the 8/16-bit PPG timer 0 and 8/16-bit PPG timer 1. PPG2, 4, 6, 8, A, C, and E have the same function as PPG0, and PPG3, 5, 7, 9, B, D, and F have the same function as PPG1. ■ Channels and PPG Pins of PPG Timers Figure 15.2-1 shows the relationship between the channels and the PPG pins of the 8/16-bit PPG timers in the MB90950 series. Figure 15.2-1 Channels and PPG Pins of PPG Timers Pin PPG0/PPG1 PPG01: REV PPG0 output pin Pin PPG1 output pin Pin PPG2/PPG3 PPG23: REV PPG2 output pin Pin PPG3 output pin PPG4/PPG5 Pin PPG45: REV PPG4 output pin Pin PPG5 output pin PPG6/PPG7 Pin PPG67: REV PPG6 output pin Pin PPG7 output pin PPG8/PPG9 Pin PPG89: REV PPG8 output pin Pin PPG9 output pin PPGA/PPGB Pin PPGAB: REV PPGA output pin Pin PPGB output pin PPGC/PPGD Pin PPGCD: REV PPGC output pin Pin PPGD output pin PPGE/PPGF Pin PPGEF: REV PPGE output pin Pin PPGF output pin CM44-10148-4E FUJITSU MICROELECTRONICS LIMITED 343 CHAPTER 15 8/16-BIT PPG TIMER 15.2 15.2.1 MB90950 Series Block Diagram of 8/16-bit PPG Timer 0 The 8/16-bit PPG timer 0 consists of the following blocks. ■ Block Diagram of 8/16-bit PPG Timer 0 Figure 15.2-2 Block Diagram of 8/16-bit PPG Timer 0 "H" level side data bus "L" level side data bus PPG0 reload register PRLH0 ("H" level side) PPG0 operation mode control register (PPGC0) PRLL0 ("L" level side) PEN0 Reserved PE0 PIE0 PUF0 PPG0 temporary buffer 0 (PRLBH0) Interrupt request R output* S Q 2 Reload register L/H selector Count start value Select signal Reload Clear Pulse selector PPG0 down counter (PCNT0) Operation mode control signal PPG1 underflow PPG0 underflow (to PPG1) Underflow CLK PPG0 Invert output latch Pin PPG output control circuit PPG0 Time-base timer output (512/HCLK) Peripheral clock (1/φ) Peripheral clock (2/φ) Peripheral clock (4/φ) Peripheral clock (8/φ) Peripheral clock (16/φ) PPG1 output Count clock selector 3 Select signal PCS2 PCS1 PCS0 PCM2 PCM1 PCM0 REV PPG0/1 count clock selection register (PPG01) − : Undefined Reserved : Reserve bit HCLK : Oscillation clock frequency φ : Machine clock frequency * : The interrupt output of 8/16-bit PPG timer 0 is combined to one interrupt by OR circuit with the interrupt request output of PPG timers 1, 4 and 5. 344 FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 15 8/16-BIT PPG TIMER 15.2 MB90950 Series ● Details of pins in the block diagram Table 15.2-1 shows the actual pin names and interrupt request numbers of the 8/16-bit PPG timer. Table 15.2-1 Pins and Interrupt Request Numbers in Block Diagram Output pin Channel PPG:REV=0 PPG:REV=1 PPG0 P60 / PPG0 P90 / PPG1 PPG1 P90 / PPG1 P60 / PPG0 PPG2 P61 / PPG2 P91 / PPG3 PPG3 P91 / PPG3 P61 / PPG2 PPG4 P62 / PPG4 P92 / PPG5 PPG5 P92/ PPG5 P62 / PPG4 PPG6 P63 / PPG6 P93 / PPG7 PPG7 P93/ PPG7 P63 / PPG6 PPG8 P64 / PPG8 P20 / PPG9 PPG9 P20 / PPG9 P64 / PPG8 PPGA P65 / PPGA P21 / PPGB PPGB P21 / PPGB P65 / PPGA PPGC P66 / PPGC P22 / PPGD PPGD P22 / PPGD P66 / PPGC PPGE P67/ PPGE P23 / PPGF PPGF P23/ PPGF P67 / PPGE Interrupt request number #21 (15H) #22 (16H) #21 (15H) #22 (16H) #23 (17H) #24 (18H) #23 (17H) #24 (18H) ● PPG0 operation mode control register (PPGC0) This register enables or disables the operation, pin output, and underflow interrupt of the 8/16-bit PPG timer. It also indicates the occurrence of an underflow. ● PPG0/1 count clock selection register (PPG01) This register sets the count clock of the 8/16-bit PPG timer and the switching between PPG0 and PPG1 output pins. ● PPG0 reload registers (PRLH0, PRLL0) These registers set the "H" width or "L" width of output pulse. The values set in PPG0 reload registers are reloaded into the PPG0 down counter (PCNT0) when the 8/16-bit PPG timer is activated. CM44-10148-4E FUJITSU MICROELECTRONICS LIMITED 345 CHAPTER 15 8/16-BIT PPG TIMER 15.2 MB90950 Series ● PPG0 down counter (PCNT0) This counter is an 8-bit down counter that counts down by alternately reloading the values set in the PPG0 reload registers (PRLH0, PRLL0). When an underflow occurs, the pin output is inverted. This counter can be used as a 1-channel 16-bit PPG down counter by concatenating 2-channel PPG down counters (PPG0, PPG1). ● PPG0 temporary buffer (PRLBH0) This buffer prevents deviation of the output pulse width caused by the timing of writing to the PPG reload registers (PRLH0, PRLL0). This buffer stores the PRLH0 value temporarily and enables the set value of the PRLH0 in synchronization with the timing of writing to the PRLL0. ● Reload register L/H selector This selector detects the current pin output level to select which side of the reload register, "L" side (PRLL0) or "H" side (PRLH0), is reloaded into the PPG0 down counter. ● Count clock selector This selector selects the count clock to be input to the PPG down counter 0 from five divided clocks of the machine clock or the divided clock of the time-base timer. ● PPG output control circuit This circuit inverts the pin output level and the output when an underflow occurs. 346 FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 15 8/16-BIT PPG TIMER 15.2 MB90950 Series 15.2.2 Block Diagram of 8/16-bit PPG Timer 1 The 8/16-bit PPG timer 1 consists of the following blocks. ■ Block Diagram of 8/16-bit PPG Timer 1 Figure 15.2-3 Block Diagram of 8/16-bit PPG Timer 1 "H" side data bus "L" side data bus PPG1 operation mode control register (PPGC1) PPG1 reload register PRLH1 ("H" side) PRLL1 ("L" side) PEN1 PE1 PIE1 PUF1 MD1 MD0 Operation mode control signal Reserved 2 PPG1 temporary buffer (PRLBH1) R S Reload selector L/H selector Count start value PPG0 underflow (from PPG0) Q Select signal Reload Clear PPG1 down counter Underflow (PCNT1) PPG1 underflow (to PPG0) Interrupt request output* Invert CLK PPG1 output latch Pin PPG1 PPG output control circuit MD0 PPG0 output Time-base timer output (512/HCLK) Peripheral clock (1/φ) Peripheral clock (2/φ) Peripheral clock (4/φ) Peripheral clock (8/φ) Peripheral clock (16/φ) Counter clock selector 3 Select signal PCS2 PCS1 PCS0 PCM2 PCM1 PCM0 REV − : Undefined PPG0/1 count clock selection register (PPG01) Reserved : Reserved bit HCLK : Oscillation clock frequency φ : Machine clock frequency * : The interrupt output of 8/16-bit PPG timer 1 is combined to one interrupt by OR circuit with the interrupt request output of PPG timers 0, 4 and 5. CM44-10148-4E FUJITSU MICROELECTRONICS LIMITED 347 CHAPTER 15 8/16-BIT PPG TIMER 15.2 MB90950 Series ● Details of pins in the block diagram Table 15.2-2 shows the actual pin names and interrupt request numbers of the 8/16-bit PPG timer. Table 15.2-2 Pins and Interrupt Request Numbers in Block Diagram Output pin Channel PPG:REV=0 PPG:REV=1 PPG0 P60 / PPG0 P90 / PPG1 PPG1 P90 / PPG1 P60 / PPG0 PPG2 P61 / PPG2 P91 / PPG3 PPG3 P91 / PPG3 P61 / PPG2 PPG4 P62 / PPG4 P92 / PPG5 PPG5 P92/ PPG5 P62 / PPG4 PPG6 P63 / PPG6 P93 / PPG7 PPG7 P93/ PPG7 P63 / PPG6 PPG8 P64 / PPG8 P20 / PPG9 PPG9 P20 / PPG9 P64 / PPG8 PPGA P65 / PPGA P21 / PPGB PPGB P21 / PPGB P65 / PPGA PPGC P66 / PPGC P22 / PPGD PPGD P22 / PPGD P66 / PPGC PPGE P67/ PPGE P23 / PPGF PPGF P23/ PPGF P67 / PPGE Interrupt request number #21 (15H) #22 (16H) #21 (15H) #22 (16H) #23 (17H) #24 (18H) #23 (17H) #24 (18H) ● PPG1 operation mode control register (PPGC1) This register sets the operation mode of the 8/16-bit PPG timer. It enables or disables the operation, pin output, and underflow interrupt of the 8/16-bit PPG timer 1. It also indicates the occurrence of an underflow. ● PPG0/1 count clock selection register (PPG01) This register sets the count clock of the 8/16-bit PPG timer. ● PPG1 reload registers (PRLH1, PRLL1) These registers set the "H" width or "L" width of output pulse. The values set in PPG1 reload registers are reloaded into the PPG1 down counter (PCNT1) when the 8/16-bit PPG timer 1 is activated. 348 FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 15 8/16-BIT PPG TIMER 15.2 MB90950 Series ● PPG1 down counter (PCNT1) This counter is an 8-bit down counter that counts down by alternately reloading the values set in the PPG1 reload registers (PRLH1, PRLL1). When an underflow occurs, the pin output is inverted. This counter can be used as a 1-channel 16-bit PPG down counter by concatenating 2-channel PPG down counters (PPG0, PPG1). ● PPG1 temporary buffer (PRLBH1) This buffer prevents deviation of the output pulse width caused by the timing of writing to the PPG reload registers (PRLH1, PRLL1). This buffer stores the PRLH1 value temporarily and enables the set value of the PRLH1 in synchronization with the timing of writing to the PRLL1. ● Reload register L/H selector This selector detects the current pin output level to select which side of the reload register, "L" side (PRLL1) or "H" side (PRLH1), is reloaded into the PPG1 down counter. ● Count clock selector This selector selects the count clock to be input to the PPG1 down counter from five divided clocks of the machine clock or the divided clock of the time-base timer. ● PPG output control circuit This circuit inverts the pin output level and the output when an underflow occurs. CM44-10148-4E FUJITSU MICROELECTRONICS LIMITED 349 CHAPTER 15 8/16-BIT PPG TIMER 15.3 15.3 MB90950 Series Configuration of 8/16-bit PPG Timer This section shows the pins, registers and interrupt sources of the 8/16-bit PPG timer. ■ Pins of 8/16-bit PPG Timer The pins of the 8/16-bit PPG timer serve as general-purpose I/O ports. Table 15.3-1 shows the pin functions and pin settings for using the 8/16-bit PPG timer. Table 15.3-1 Pins of 8/16-bit PPG Timer (1 / 2) 350 Channel Pin name PPG0 P60 / AN0 / PPG0 General-purpose I/O port/ A/D converter analog input 0/ PPG output 0 • Analog input enable register: Set to disable (ADER6:ADE0=0) • PPG operation mode control register: Enable pin output (PPGC0:PE0=1) PPG1 P90 / PPG1 General-purpose I/O port/ PPG output 1 • PPG operation mode control register: Enable pin output (PPGC1:PE1=1) PPG2 P61 / AN1 / PPG2 General-purpose I/O port/ A/D converter analog input 1/ PPG output 2 • Analog input enable register: Set to disable (ADER6:ADE1=0) • PPG operation mode control register: Enable pin output (PPGC2:PE0=1) PPG3 P91 / PPG3 General-purpose I/O port/ PPG output 3 • PPG operation mode control register: Enable pin output (PPGC3:PE1=1) PPG4 P62 / AN2 / PPG4 General-purpose I/O port/ A/D converter analog input 2/ PPG output 4 • Analog input enable register: Set to disable (ADER6:ADE2=0) • PPG operation mode control register: Enable pin output (PPGC4:PE0=1) PPG5 P92 / PPG5 General-purpose I/O port/ PPG output 5 • PPG operation mode control register: Enable pin output (PPGC5:PE1=1) PPG6 P63 / AN3 / PPG6 General-purpose I/O port/ A/D converter analog input 3/ PPG output 6 • Analog input enable register: Set to disable (ADER6:ADE3=0) • PPG operation mode control register: Enable pin output (PPGC6:PE0=1) PPG7 P93 / PPG7 General-purpose I/O port/ PPG output 7 • PPG operation mode control register: Enable pin output (PPGC7:PE1=1) PPG8 P64 / AN4 / PPG8 General-purpose I/O port/ A/D converter analog input 4/ PPG output 8 • Analog input enable register: Set to disable (ADER6:ADE4=0) • PPG operation mode control register: Enable pin output (PPGC8:PE0=1) PPG9 P20 / PPG9 General-purpose I/O port/ PPG output 9 • PPG operation mode control register: Enable pin output (PPGC9:PE1=1) Pin function Setting required for use of 8/16-bit PPG timer FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 15 8/16-BIT PPG TIMER 15.3 MB90950 Series Table 15.3-1 Pins of 8/16-bit PPG Timer (2 / 2) CM44-10148-4E Channel Pin name PPGA P65 / AN5 / PPGA General-purpose I/O port/ A/D converter analog input 5/ PPG output A • Analog input enable register: Set to disable (ADER6:ADE5=0) • PPG operation mode control register: Enable pin output (PPGCA:PE0=1) PPGB P21 / PPGB General-purpose I/O port/ PPG output B • PPG operation mode control register: Enable pin output (PPGCB:PE1=1) PPGC P66 / AN6 / PPGC General-purpose I/O port/ A/D converter analog input 6/ PPG output C • Analog input enable register: Set to disable (ADER6:ADE6=0) • PPG operation mode control register: Enable pin output (PPGCC:PE0=1) PPGD P22 / PPGD General-purpose I/O port/ PPG output D • PPG operation mode control register: Enable pin output (PPGCD:PE1=1) PPGE P67 / AN7 / PPGE General-purpose I/O port/ A/D converter analog input 7/ PPG output E • Analog input enable register: Set to disable (ADER6:ADE7=0) • PPG operation mode control register: Enable pin output (PPGCE:PE0=1) PPGF P23 / PPGF General-purpose I/O port/ PPG output F • PPG operation mode control register: Enable pin output (PPGCF:PE1=1) Pin function Setting required for use of 8/16-bit PPG timer FUJITSU MICROELECTRONICS LIMITED 351 CHAPTER 15 8/16-BIT PPG TIMER 15.3 MB90950 Series ■ List of Registers and Initial Values of 8/16-bit PPG Timer Figure 15.3-1 List of Registers and Initial Values of 8/16-bit PPG Timer PPG0 operation mode control register: H (PPGCm) PPG0 operation mode control register: L (PPGCn) PPGn/m count clock selection register (PPGnm) bit 15 14 13 12 11 10 9 8 0 1 0 0 0 0 0 1 7 6 5 4 3 2 1 0 0 1 0 0 0 1 1 1 7 6 5 4 3 2 1 0 0 0 0 0 0 0 1 0 bit 15 14 13 12 11 10 9 8 bit 7 6 5 4 3 2 1 0 bit 15 14 13 12 11 10 9 8 bit 7 6 5 4 3 2 1 0 bit bit PPGn reload register: H (PRLHn) PPGn reload register: L (PRLLn) PPGm reload register: H (PRLHm) PPGm reload register: L (PRLLm) ×: Undefined n = 0, 2, 4, 6, 8, A, C, E m = 1, 3, 5, 7, 9, B, D, F ■ Generation of Interrupt in 8/16-bit PPG Timer In the 8/16-bit PPG timer, the underflow generation flag bits in the PPG operation mode control register (PPGCn: PUFn, PPGCm: PUFm) are set to "1" when an underflow occurs. If underflow interrupt of the channel causing an underflow is enabled (PPGCn:PIE0=1, PPGCm:PIE1=1), an underflow interrupt request is generated to the interrupt controller. 352 FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 15 8/16-BIT PPG TIMER 15.3 MB90950 Series 15.3.1 PPG0 Operation Mode Control Register (PPGC0) The PPG0 operation mode control register provides the following settings for the 8/16bit PPG timer 0 operation: • Enabling or disabling operation of 8/16-bit PPG timer 0 • Switching between pin functions (enabling or disabling pulse output) • Enabling or disabling underflow interrupt • Setting interrupt request flag set by the occurrence of underflow Only the function of PPGC0 is explained in this section. PPGC2, 4, 6, 8, A, C, and E have the same function as PPGC0, setting the respective 8/16-bit PPG timers 2, 4, 6, 8, A, C, and E. ■ PPG0 Operation Mode Control Register (PPGC0) Figure 15.3-2 PPG0 Operation Mode Control Register (PPGC0) bit 7 ch.0 PPGC0 Other channels: ch.2 PPGC2 ch.4 PPGC4 ch.6 PPGC6 ch.8 PPGC8 ch.A PPGCA ch.C PPGCC ch.E PPGCE Address 000030H 6 − PEN0 R/W − 000034H 000038H 00003CH 000040H 000044H 000048H 00004CH 5 4 3 PE0 PIE0 PUF0 0 2 1 − Re− served R/W R/W R/W − − W Initial value 01000111 B bit0 Reserved 1 Reserved bit Be sure to set this bit to "1" bit3 PUF0 0 1 Underflow generation flag bit Read No underflow Underflow detected Write Clears PUF0 bit No effect bit4 PIE0 0 1 Underflow interrupt enable bit Disables interrupt request Enables interrupt request bit5 PPG0 pin output enable bit PE0 0 1 General-purpose I/O port (Disables pulse output) PPG0 output (Enables pulse output) bit7 PPG0 operation enable bit PEN0 R/W : Readable/writable W : Write only − : Undefined 0 1 Disables count operation (Retains "L" level output) Enables count operation : Initial value CM44-10148-4E FUJITSU MICROELECTRONICS LIMITED 353 CHAPTER 15 8/16-BIT PPG TIMER 15.3 MB90950 Series Table 15.3-2 Functions of PPG0 Operation Mode Control Register (PPGC0) Bit name 354 Function bit7 PEN0: PPG0 operation enable bit This bit enables or disables the count operation of the 8/16-bit PPG timer 0. When set to "0": Disables count operation When set to "1": Enables count operation • When the pulse output is enabled (PE0=1) while the count operation is disabled (PEN0=0), "L" level output is retained. bit6 Undefined bit Read : The value is undefined Write : No effect bit5 PE0: PPG0 pin output enable bit This bit switches between PPG0 pin functions and enables or disables the pulse output. When set to "0": Functions as a general-purpose I/O port. The pulse output is disabled When set to "1": Functions as PPG0 output pin. The pulse output is enabled bit4 PIE0: Underflow interrupt enable bit This bit enables or disables interrupt. When set to "0": Generates no interrupt request even when an underflow occurs (PUF0 = 1) When set to "1": Generates an interrupt request when an underflow occurs (PUF0 = 1) bit3 PUF0: Underflow generation flag bit 8-bit PPG output 2-channel independent operation mode, 8+8-bit PPG output operation mode: Generates an underflow (PUF0 = 1) when the value of the PPG0 down counter is counted down from "00H" to "FFH" 16-bit PPG output operation mode: Generates an underflow (PUF0 = 1) when the value of the PPG0+PPG1 down counter is counted down from "0000H" to "FFFFH" • When an underflow occurs (PUF0=1) while underflow interrupt is enabled (PIE0=1), an interrupt request is generated. When set to "0": Clears this bit When set to "1": No effect Read by a read-modify-write instruction: "1" is read bit2, bit1 Undefined bits Write : No effect Read : The value is undefined. bit0 Reserved: Reserved bit Be sure to set this bit to "1". FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 15 8/16-BIT PPG TIMER 15.3 MB90950 Series 15.3.2 PPG1 Operation Mode Control Register (PPGC1) The PPG1 operation mode control register provides the following settings for the 8/16bit PPG timer 1 operation: • Enabling or disabling operation of 8/16-bit PPG timer 1 • Switching between pin functions (enabling or disabling pulse output) • Enabling or disabling underflow interrupt • Setting interrupt request flag set by the occurrence of underflow • Setting operation mode for 8/16-bit PPG timers 1 and 0 Only the function of PPGC1 is explained in this section. PPGC3, 5, 7, 9, B, D, and F have the same function as PPGC1, setting the respective 8/16-bit PPG timers 3, 5, 7, 9, B, D, and F. ■ PPG1 Operation Mode Control Register (PPGC1) Figure 15.3-3 PPG1 Operation Mode Control Register (PPGC1) ch.1 PPGC1 Other channels: ch.3 PPGC3 ch.5 PPGC5 ch.7 PPGC7 ch.9 PPGC9 ch.B PPGCB ch.D PPGCD ch.F PPGCF bit 15 14 Address PEN1 − 000031H R/W − 13 12 11 10 9 PE1 PIE1 PUF1 MD1 MD0 R/W R/W R/W R/W R/W 8 Initial value Reserved 01000001 B W bit8 Reserved 000035H 000039H 00003DH 000041H 000045H 000049H 00004DH 1 Reserved bit Be sure to set this bit to "1" bit10 bit9 MD1 MD0 0 0 0 1 1 1 0 1 Operation mode selection bits 8-bit PPG output 2-channel independent operation mode 8+8-bit PPG output operation mode Setting is prohibited 16-bit PPG output operation mode bit11 PUF1 0 1 Underflow generation flag bit Read Write No underflow Clears PUF1 bit Underflow detected No effect bit12 PIE1 0 1 Underflow interrupt enable bit Disables underflow interrupt request Enables underflow interrupt request bit13 PE1 0 1 R/W : Readable/writable W : Write only − : Undefined : Initial value CM44-10148-4E PPG1 pin output enable bit General-purpose I/O port (Disables pulse output) PPG1 output (Enables pulse output) bit15 PEN1 0 1 PPG1 operation enable bit Disables count operation (Retains "L" level output) Enables count operation FUJITSU MICROELECTRONICS LIMITED 355 CHAPTER 15 8/16-BIT PPG TIMER 15.3 MB90950 Series Table 15.3-3 Functions of PPG1 Operation Mode Control Register (PPGC1) Bit name bit15 PEN1: PPG1 operation enable bit This bit enables or disables the count operation of the 8/16-bit PPG timer 1. When set to "0": Disables count operation When set to "1": Enables count operation • When the pulse output is enabled (PE1=1) while the count operation is disabled (PEN1=0), "L" level output is retained. bit14 Undefined bit Read : The value is undefined Write : No effect bit13 PE1: PPG1 pin output enable bit This bit switches between PPG1 pin functions and enables or disables the pulse output. When set to "0": Functions as a general-purpose I/O port. The pulse output is disabled When set to "1": Functions as PPG1 output pin. The pulse output is enabled bit12 PIE1: Underflow interrupt enable bit This bit enables or disables interrupt. When set to "0": Generates no interrupt request even when an underflow occurs (PUF1 = 1) When set to "1": Generates an interrupt request when an underflow occurs (PUF1 = 1) PUF1: Underflow generation flag bit 8-bit PPG output 2-channel independent operation mode, 8+8-bit PPG output operation mode: Generates an underflow (PUF1 = 1) when the value of the PPG1 down counter is counted down from "00H" to "FFH" 16-bit PPG output operation mode: Generates an underflow (PUF1 = 1) when the value of the PPG0+PPG1 down counter is counted down from "0000H" to "FFFFH" • When an underflow occurs (PUF1=1) while underflow interrupt request is enabled (PIE1=1), an interrupt request is generated. When set to "0": Clears this bit When set to "1": No effect Read by a read-modify-write instruction: "1" is read MD1, MD0: Operation mode selection bits These bits set the operation mode of the 8/16-bit PPG timer. [Any mode other than 8-bit PPG output 2-channel independent operation mode] • Set the two bits of the PPG operation enable bits (PEN0, PEN1) at the same time using a word instruction. • Do not set operation of only one of the two channels (PEN1=0/PEN0=1 or PEN1=1/PEN0=0). Note: Do not set MD1, MD0=10B. Reserved: Reserved bit Be sure to set this bit to "1". bit11 bit10, bit9 bit8 356 Function FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 15 8/16-BIT PPG TIMER 15.3 MB90950 Series 15.3.3 PPG0/1 Count Clock Selection Register (PPG01) The PPG0/1 count clock selection register selects the count clock and the output pin for the 8/16-bit PPG timers 0 and 1. Only the function of PPG01 is explained in this section. PPG23, 45, 67, 89, AB, CD, and EF have the same function as PPG01, setting the respective 8/16-bit PPG timers 2 and 3, 4 and 5, 6 and 7, 8 and 9, A and B, C and D, and E and F. ■ PPG0/1 Count Clock Selection Register (PPG01) Figure 15.3-4 PPG0/1 Count Clock Selection Register (PPG01) ch.1 PPG01 Other channels: ch.3 PPG23 ch.5 PPG45 ch.7 PPG67 ch.9 PPG89 ch.B PPGAB ch.D PPGCD ch.F PPGEF Address 000032H 7 6 5 4 3 2 PCS2 PCS1 PCS0 PCM2 PCM1 PCM0 000036H R/W R/W R/W R/W R/W R/W 00003AH 00003EH 000042H 000046H 00004AH 00004EH 1 0 − REV Initial value 0 0 0 0 0 0 1 0B R/W bit0 REV 0 1 bit4 PPG output pin selection bit Outputs pulses from the standard output pins Switches between output pin PPGn and PPGm bit3 bit2 PCM2 PCM1 PCM0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 bit7 bit6 bit5 PCS2 PCS1 PCS0 R/W : Readable/writable : Undefined HCLK : Initial value φ : Oscillation clock : Machine clock frequency PPG0 count clock selection bits 1/φ (31.25 ns) 2/φ (62.5 ns) 22/φ (125 ns) 23/φ (250 ns) 24/φ (500 ns) Setting is prohibited Setting is prohibited 29/HCLK (128 μs) PPG1 count clock selection bits 0 0 0 0 0 1 1/φ (31.25 ns) 0 1 0 22/φ (125 ns) 0 1 1 23/φ (250 ns) 1 0 0 24/φ (500 ns) 1 1 0 1 1 0 Setting is prohibited 1 1 1 29/HCLK (128 2/φ (62.5 ns) Setting is prohibited μs) The value within parentheses is the value operating at HCLK=4 MHz and φ=32 MHz. CM44-10148-4E FUJITSU MICROELECTRONICS LIMITED 357 CHAPTER 15 8/16-BIT PPG TIMER 15.3 MB90950 Series Table 15.3-4 Functions of PPG0/1 Count Clock Selection Register (PPG01) Bit name Function These bits set the count clock of the 8/16-bit PPG timer 1. bit7 to bit5 PCS2 to PCS0: PPG1 count clock selection bits • The count clock is selected from five divided clocks of the machine clock or the divided clock of the time-base timer. • The settings of the PPG1 count clock select bits (PCS2 to PCS0) are valid only in 8-bit PPG output 2-channel independent mode (PPGC1: MD1, MD0=00B). PCM2 to PCM0: PPG0 count clock selection bits bit1 Undefined bit Read : The value is undefined Write: No effect REV: PPG output pin selection bit This bit switches the output pins of the 8/16-bit PPG timers 0 and 1. When set to "0": Outputs from the standard output pins PPG0 → PPG0 output pin PPG1 → PPG1 output pin When set to "1": Switches output pins PPG0 → PPG1 output pin PPG1 → PPG0 output pin bit0 358 These bits set the count clock of the 8/16-bit PPG timer 0. bit4 to bit2 • The count clock is selected from five divided clocks of the machine clock or the divided clock of the time-base timer. FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 15 8/16-BIT PPG TIMER 15.3 MB90950 Series 15.3.4 PPG Reload Registers (PRLL0/PRLH0, PRLL1/PRLH1) The value (reload value) from which the PPG down counter starts counting is set in the PPG reload registers. The registers have an 8-bit for each "L" level side and "H" level side. Only the function of PRLL0/PRLH0 and PRLL1/PRLH1 is explained in this section. PRLL2/PRLH2 to PRLLF/PRLHF have the same function as PRLL0/PRLH0, setting the respective 8/16-bit PPG timers 2 to F. ■ PPG Reload Registers (PRLL0/PRLH0, PRLL1/PRLH1) Figure 15.3-5 PPG Reload Registers (PRLL0/PRLH0, PRLL1/PRLH1) ch.0 PRLH0 ch.1 PRLH1 Address bit15 bit14 bit13 bit12 bit11 bit10 007901H 007903H Other channels: ch.2 ch.3 ch.4 ch.5 ch.6 ch.7 ch.8 ch.9 ch.A ch.B ch.C ch.D ch.E ch.F PRLH2 PRLH3 PRLH4 PRLH5 PRLH6 PRLH7 PRLH8 PRLH9 PRLHA PRLHB PRLHC PRLHD PRLHE PRLHF 007905H 007907H 007909H 00790BH 00790DH 00790FH 007911H 007913H 007915H 007917H 007919H 00791BH 00791DH 00791FH Address ch.0 PRLL0 ch.1 PRLL1 007900H 007902H Other channels: ch.2 ch.3 ch.4 ch.5 ch.6 ch.7 ch.8 ch.9 ch.A ch.B ch.C ch.D ch.E ch.F PRLL2 PRLL3 PRLL4 PRLL5 PRLL6 PRLL7 PRLL8 PRLL9 PRLLA PRLLB PRLLC PRLLD PRLLE PRLLF bit9 bit8 Initial value D15 D14 D13 D12 D11 D10 D9 D8 R/W R/W R/W R/W R/W R/W R/W R/W bit7 bit6 bit5 bit4 bit3 D7 D6 D5 D4 R/W R/W R/W R/W R/W D3 bit2 bit1 XXXXXXXX B bit0 D2 D1 D0 R/W R/W R/W Initial value XXXXXXXX B 007904H 007906H 007908H 00790AH 00790CH 00790EH 007910H 007912H 007914H 007916H 007918H 00791AH 00791CH 00791EH R/W : Readable/writable × : Undefined CM44-10148-4E FUJITSU MICROELECTRONICS LIMITED 359 CHAPTER 15 8/16-BIT PPG TIMER 15.3 MB90950 Series Table 15.3-5 shows each register function of the PPG reload registers. Table 15.3-5 Functions of PPG Reload Registers Function 8/16-bit PPG timer 0 8/16-bit PPG timer 1 Retains the reload value at "L" level side PRLL0 PRLL1 Retains the reload value at "H" level side PRLH0 PRLH1 Notes: • In 16-bit PPG output operation mode (PPGC1: MD1, MD0=11B), set the reload registers using a long-word instruction or set the PPG0 and PPG1 in this order using a word instruction. • In 8+8-bit PPG output operation mode (PPGC1: MD1, MD0=01B), set both "L" level and "H" level sides of the PPG reload register (PRLL0/PRLH0) in the 8/16-bit PPG timer 0 to the same value. Setting a different value in "L" level and "H" level sides may cause the 8/16-bit PPG timer 1 to have a different PPG output wave form for each clock cycle. 360 FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 15 8/16-BIT PPG TIMER 15.4 MB90950 Series 15.4 Interrupts of 8/16-bit PPG Timer The 8/16-bit PPG timer can generate an interrupt request when an underflow of the PPG down counter occurs. It does not support the extended intelligent I/O service (EI2OS) and DMA transfer. ■ Interrupts of 8/16-bit PPG Timer Table 15.4-1 shows the interrupt control bits and interrupt sources of the 8/16-bit PPG timer. Table 15.4-1 Interrupt Control Bits of 8/16-bit PPG Timer PPGn PPGm Interrupt request flag bit PPGCn: PUF0 PPGCm: PUF1 Interrupt request enable bit PPGCn: PIE0 PPGCm: PIE1 Interrupt source Generation of PPGn down counter underflow Generation of PPGm down counter underflow Note: n = 0, 2, 4, 6, 8, A, C, E m=n+1 [8-bit PPG output 2-channel independent operation mode, 8+8-bit PPG output operation mode] • In 8-bit PPG output 2-channel independent operation mode or 8+8-bit PPG output operation mode, the PPGn and PPGm can generate an interrupt independently. • When the PPGn or PPGm down counter is counted down from "00H" to "FFH", an underflow occurs. When an underflow occurs, the underflow generation flag bit of the channel generating the underflow is set (PPGCn: PUF0=1 or PPGCm: PUF1=1). • If interrupt request of the channel that causes an underflow is enabled (PPGCn: PIE0=1 or PPGCm: PIE1=1), an interrupt request is generated. [16-bit PPG output operation mode] • In 16-bit PPG output operation mode, when the PPGn+PPGm down counter is counted down from "0000H" to "FFFFH", an underflow occurs. When an underflow occurs, the underflow generation flag bits of the two channels are set at the same time (PPGCn: PUF0=1 and PPGCm: PUF1=1). • An interrupt request is generated when an underflow occurs if interrupt request of either of the two channels is enabled (PPGCn: PIE1=0, PPGCm: PIE1=1 or PPGCn: PIE0=1, PPGCm: PIE1=0). • To prevent duplication of interrupt requests, disable the underflow interrupt enable bit of either of the two channels in advance (PPGCn: PIE0=0, PPGCm: PIE1=1 or PPGCn: PIE0=1, PPGCm: PIE1=0). • If the underflow generation flag bits of the two channels are set (PPGCn: PUF0=1 and PPGCm: PUF1=1), clear the two channels at the same time. CM44-10148-4E FUJITSU MICROELECTRONICS LIMITED 361 CHAPTER 15 8/16-BIT PPG TIMER 15.4 MB90950 Series ■ Interrupts of 8/16-bit PPG Timer For interrupt number, interrupt control register, and interrupt vector address, see "CHAPTER 3 INTERRUPTS". 362 FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 15 8/16-BIT PPG TIMER 15.5 MB90950 Series 15.5 Operating Explanation of 8/16-bit PPG Timer The 8/16-bit PPG timer outputs a pulse width of any frequency and any duty ratio continuously. ■ Operation of 8/16-bit PPG Timer ● Output operation of 8/16-bit PPG timer • The 8/16-bit PPG timer has two ("L" level side and "H" level side) 8-bit reload registers (PRLLn/ PRLHn, PRLLm/PRLHm) for each channel. • The values set in the reload registers (PRLLn/PRLHn, PRLLm/PRLHm) are reloaded alternately into the PPG down counters (PCNTn, PCNTm). • After reloading the value into the PPG down counters, counting down starts in synchronization with the count clock set by the PPG count clock select bits (PPGnm: PCM2 to PCM0, PCS2 to PCS0). • If the values set in the reload registers are reloaded to the PPG down counters due to underflow, the pin output is inverted. Figure 15.5-1 shows the output wave form of 8/16-bit PPG timer. Figure 15.5-1 Output Wave Form of 8/16-bit PPG Timer Operation start Operation stop PPG operation enable bit (PEN) PPG output pin T × (L + 1) T × (H + 1) L : Value of PPG reload register (PRLL) H : Value of PPG reload register (PRLH) T : Count clock cycle ● Operation mode of 8/16-bit PPG timer While the operation of the 8/16-bit PPG timer is enabled (PPGCn: PEN0=1, PPGCm: PEN1=1), a pulse wave is output continuously from the PPG output pin. The pulse wave can be set to any frequency and duty ratio. The pulse output of the 8/16-bit PPG timer will not stop until operation of the 8/16-bit PPG timer is stopped (PPGCn: PEN0=0, PPGCm: PEN1=0). • 8-bit PPG output 2-channel independent operation mode • 16-bit PPG output operation mode • 8+8-bit PPG output operation mode Note: CM44-10148-4E n = 0, 2, 4, 6, 8, A, C, E m=n+1 FUJITSU MICROELECTRONICS LIMITED 363 CHAPTER 15 8/16-BIT PPG TIMER 15.5 MB90950 Series 8-bit PPG Output 2-channel Independent Operation Mode 15.5.1 In 8-bit PPG output 2-channel independent operation mode, the 8/16-bit PPG timer is set as an 8-bit PPG timer with two independent channels. PPG output operation and interrupt request generation can be performed independently for each channel. ■ Setting for 8-bit PPG Output 2-channel Independent Operation Mode To operate in 8-bit PPG output 2-channel independent operation mode, the setting shown in Figure 15.5-2 is required. Figure 15.5-2 Setting for 8-bit PPG Output 2-channel Independent Operation Mode bit15 14 PPGCm/PPGCn PEN1 13 12 11 10 9 PE1 PIE1 PUF1 MD1 MD0 1 0 0 bit8 bit7 Reserved PEN0 1 6 5 4 3 2 1 bit0 Reserved PE0 PIE0 PUF0 1 1 PPGnm (Reserved area) PRLHn/PRLLn Set PPGn "H" level side reload value Set PPGn "L" level side reload value PRLHm/PRLLm Set PPGm "H" level side reload value Set PPGm "L" level side reload value PCS2PCS1 PCS0 PCM2PCM1 PCM0 REV : Used bit − : Undefined bit 1 : Set to "1" 0 : Set to "0" Note: n = 0, 2, 4, 6, 8, A, C, E m=n+1 Note: Set both "H" level side and "L" level side of the PPG reload registers (PRLLn/PRLHn, PRLLm/PRLHm) at the same time using a word instruction. 364 FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E MB90950 Series CHAPTER 15 8/16-BIT PPG TIMER 15.5 ● Operation in 8-bit PPG output 2-channel independent operation mode • The 8-bit PPG timer with two channels performs an independent PPG operation in each channel. • When pin output is enabled (PPGCn:PE0=1, PPGCm:PE1=1), a PPGn pulse wave is output from the PPGn pin and a PPGm pulse wave is output from the PPGm pin if the PPG output pin selection is set to standard (PPGnm:REV=0). If PPG output pin switching is set (PPGnm:REV=1), a PPGm pulse wave is output from the PPGn pin and a PPGn pulse wave is output from the PPGm pin. • When the reload value is set in the PPG reload registers (PRLLn/PRLHn, PRLLm/PRLHm) to enable the operation of the PPG timer (PPGCn: PEN0=1, PPGCm: PEN1=1), the PPG down counter of the enabled channel starts counting. • To stop the count operation of the PPG down counter, disable the operation of the PPG timer of the channel to be stopped (PPGCn: PEN0=0, PPGCm: PEN1=0). The count operation of the PPG down counter is stopped and the output of the PPG output pin is held at "L" level. • When the PPG down counter of one channel generates an underflow, the reload values set in the PPG reload registers (PRLLn/PRLHn, PRLLm/PRLHm) are reloaded into the PPG down counter in which the underflow occurs. • When an underflow occurs, the underflow generation flag bit in the channel that causes the underflow is set (PPGCn: PUF0=1, PPGCm: PUF1=1). If interrupt request is enabled at the channel that causes the underflow (PPGCn: PIE0=1, PPGCm: PIE1=1), an interrupt request is generated. CM44-10148-4E FUJITSU MICROELECTRONICS LIMITED 365 CHAPTER 15 8/16-BIT PPG TIMER 15.5 MB90950 Series ● Output wave form in 8-bit PPG output 2-channel independent operation mode • Both the "L" and "H" pulse widths to be output are determined by adding 1 to the values of the PPG reload register of each channel and multiplying them by the count clock cycle. For example, if the value of the PPG reload register is "00H", the pulse width becomes one cycle of the count clock, and if the value is "FFH", the pulse width becomes 256 cycles of the count clock. The calculation formulas for pulse width are given below: PL=T × (L+1) PH=T × (H+1) PL : "L" width of output pulse PH : "H" width of output pulse L : 8-bit value of PPG reload register (PRLLn or PRLLm) H : 8-bit value of PPG reload register (PRLHn or PRLHm) T : Count clock cycle Figure 15.5-3 shows the output wave form in 8-bit PPG output 2-channel independent operation mode. Figure 15.5-3 Output Wave Form in 8-bit PPG Output 2-channel Independent Operation Mode Operation start Operation stop PPG operation enable bit (PEN) PPG output pin T × (L + 1) T × (H + 1) L : Value of PPG reload register (PRLL) H : Value of PPG reload register (PRLH) T : Count clock cycle Note: 366 n = 0, 2, 4, 6, 8, A, C, E m=n+1 FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 15 8/16-BIT PPG TIMER 15.5 MB90950 Series 15.5.2 16-bit PPG Output Operation Mode In 16-bit PPG output operation mode, the 8/16-bit PPG timer is set as a 16-bit PPG timer with one channel. ■ Setting for 16-bit PPG Output Operation Mode To operate in 16-bit PPG output operation mode, the setting shown in Figure 15.5-4 is required. Figure 15.5-4 Setting for 16-bit PPG Output Operation Mode bit15 14 PPGCm/PPGCn PEN1 1 13 12 11 10 9 PE1 PIE1 PUF1 MD1 MD0 1 1 bit8 bit7 Reserved PEN0 1 6 5 4 3 2 PE0 PIE0 PUF0 1 1 bit0 Reserved 1 PPGnm (Reserved area) PRLHn/PRLLn Set lower 8 bits of PPGn "H" level side reload value PRLHm/PRLLm Set upper 8 bits of PPGm "H" level side reload value Set upper 8 bits of PPGm "L" level side reload value × − 1 0 PCS2 PCS1 PCS0 PCM2 PCM1 PCM0 REV Set lower 8 bits of PPGn "L" level side reload value : Used bit : Unused bit : Undefined bit : Set to "1" : Set to "0" Note: n = 0, 2, 4, 6, 8, A, C, E m=n+1 Note: Set values in the PPG reload registers using a long-word instruction or set the PPGn and PPGm (PRLLn → PRLLm, PRLHn → PRLHm) in this order using a word instruction. CM44-10148-4E FUJITSU MICROELECTRONICS LIMITED 367 CHAPTER 15 8/16-BIT PPG TIMER 15.5 MB90950 Series ● Operation in 16-bit PPG Output Operation Mode • When pin output of either PPGn pin or PPGm pin is enabled (PPGCn:PE0=1, PPGCm: PE1=1), a pulse wave of the same wave form is output from both the PPGn and PPGm pins. • When the reload value is set in the PPG reload registers (PRLLn/PRLHn, PRLLm/PRLHm) to enable operation of the PPG timers (PPGCn:PEN0=1 and PPGCm: PEN1=1) simultaneously, the PPG down counters start counting as a 16-bit down counter (PCNTn + PCNTm). • To stop the count operation of the PPG down counters, disable the operation of the PPG timers of both channels (PPGCn: PEN0=0 and PPGCm: PEN1=0) simultaneously. The count operation of the PPG down counters is stopped and the output of the PPG output pin is held at "L" level. • If the PPGm down counter generates an underflow, the reload values set in the PPGn and PPGm reload registers (PRLLn/PRLHn, PRLLm/PRLHm) are reloaded into the PPG down counter (PCNTn + PCNTm) simultaneously. • When an underflow occurs, the underflow generation flag bits in both channels are set simultaneously (PPGCn:PUF0=1, PPGCm:PUF1=1). If interrupt request is enabled at either channel (PPGCn: PIE0=1, PPGCm: PIE1=1), an interrupt request is generated. Notes: • In 16-bit PPG output operation mode, the underflow generation flag bits in the two channels are set simultaneously (PPGCn:PUF0=1 and PPGCm:PUF1=1) when an underflow occurs. To prevent duplication of interrupt requests, disable either of the underflow interrupt enable bits in the two channels (PPGCn:PIE0=0, PPGCm:PIE1=1 or PPGCn:PIE0=1, PPGCm:PIE1=0). • If underflow generation flag bits are set, clear the two channels at the same time (PPGCn: PUF0=0 and PPGCm: PUF1=0). n = 0, 2, 4, 6, 8, A, C, E m=n+1 368 FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 15 8/16-BIT PPG TIMER 15.5 MB90950 Series ● Output wave form in 16-bit PPG output operation mode Both the "L" and "H" pulse widths to be output are determined by adding 1 to the values of the PPG reload register of each channel and multiplying them by the count clock cycle. For example, if the value of the PPG reload register is "0000H", the pulse width becomes one cycle of the count clock, and if the value is "FFFFH", the pulse width becomes 65,536 cycles of the count clock. The calculation formulas for pulse width are given below: PL=T × (L+1) PH=T × (H+1) PL : "L" width of output pulse PH : "H" width of output pulse L : 16-bit value of PPG reload register (PRLLn+PRLLm) H : 16-bit value of PPG reload register (PRLHn+PRLHm) T : Count clock cycle Figure 15.5-5 shows the output wave form in 16-bit PPG output operation mode. Figure 15.5-5 Output Wave Form in 16-bit PPG Output Operation Mode Operation start Operation stop PPG operation enable bit (PEN) PPG output pin T × (L + 1) T × (H + 1) L : 16-bit value of PPG reload register (PRLLm+PRLLn) H : 16-bit value of PPG reload register (PRLHm+PRLHn) T : Count clock cycle Note: n = 0, 2, 4, 6, 8, A, C, E m=n+1 CM44-10148-4E FUJITSU MICROELECTRONICS LIMITED 369 CHAPTER 15 8/16-BIT PPG TIMER 15.5 15.5.3 MB90950 Series 8+8-bit PPG Output Operation Mode In 8+8-bit PPG output operation mode, the 8/16-bit PPG timer is set as an 8-bit PPG timer in which PPG0 operates as an 8-bit prescaler and PPG1 operates using PPG output of the PPG0 as a clock source. ■ Setting for 8+8-bit PPG Output Operation Mode To operate in the 8+8-bit PPG output operation mode, the setting shown in Figure 15.5-6 is required. Figure 15.5-6 Setting for 8+8-bit PPG Output Operation Mode bit15 14 PPGCm/PPGCn PEN1 1 PPGnm 13 12 11 10 9 bit8 bit7 Re- PE1 PIE1 PUF1 MD1 MD0 served PEN0 0 1 1 (Reserved area) 6 5 4 3 2 PE0 PIE0 PUF0 1 bit0 Reserved 1 1 PCS2 PCS1 PCS0 PCM2 PCM1 PCM0 REV PRLHn/PRLLn Set PPGn "H" level side reload value Set PPGn "L" level side reload value PRLHm/PRLLm Set PPGm "H" level side reload value Set PPGm "L" level side reload value × − 1 0 : Used bit : Unused bit : Undefined bit : Set to "1" : Set to "0" Note: n = 0, 2, 4, 6, 8, A, C, E m=n+1 Note: Set both "H" level side and "L" level side of the PPG reload registers (PRLLn/PRLHn, PRLLm/PRLHm) at the same time using a word instruction. 370 FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 15 8/16-BIT PPG TIMER 15.5 MB90950 Series ● Operation in 8+8-bit PPG output operation mode • The PPGn operates as the prescaler of the PPGm timer and the PPGm operates using the PPGn output as a count clock. • When pin output is enabled (PPGCn: PE0=1, PPGCm: PE1=1), a PPGn pulse wave is output from the PPGn pin and a PPGm pulse wave is output from the PPGm pin if the PPG output pin selection is set to standard (PPGnm: REV=0). If PPG output pin switching is set (PPGnm: REV=1), the output pins of PPGn and PPGm will be switched. • When the reload value is set in the PPG reload registers (PRLLn/PRLHn, PRLLm/PRLHm) to enable operation of the PPG timer (PPGCn:PEN0=1 and PPGCm: PEN1=1), the PPG down counter starts counting. • To stop the count operation of the PPG down counter, disable the operation of the PPG timers of both channels (PPGCn: PEN0=0 and PPGCm: PEN1=0) at the same time. The count operation of the PPG down counter is stopped and the output of the PPG output pin is held at "L" level. • When the PPG down counter of one channel generates an underflow, the reload values set in the PPG reload registers (PRLLn/PRLHn, PRLLm/PRLHm) are reloaded into the PPG down counter in which the underflow occurs. • When an underflow occurs, the underflow generation flag bit in the channel that causes the underflow is set (PPGCn:PUF0=1, PPGCm:PUF1=1). If interrupt request is enabled at the channel that causes the underflow (PPGCn: PIE0=1, PPGCm: PIE1=1), an interrupt request is generated. Notes: • Do not operate PPGm (PPGCm:PEN1=1) when PPGn is stopped (PPGCn:PEN0=0). • It is recommended to set both "L" level and "H" level sides of the PPG reload registers (PRLLn/ PRLHn, PRLLm/PRLHm) to the same value. n = 0, 2, 4, 6, 8, A, C, E m=n+1 CM44-10148-4E FUJITSU MICROELECTRONICS LIMITED 371 CHAPTER 15 8/16-BIT PPG TIMER 15.5 MB90950 Series ● Output wave form in 8+8-bit PPG output operation mode Both the "L" and "H" pulse widths to be output are determined by adding 1 to the values of the PPG reload register of each channel and multiplying them by the count clock cycle. The calculation formulas for pulse width are given below: PL=T × (Ln+1) × (Lm+1) PH=T × (Hn+1) × (Hm+1) PL : "L" width of output pulse from PPGm pin PH : "H" width of output pulse from PPGm pin Ln : 8-bit value of PPG reload register (PRLLn) Hn : 8-bit value of PPG reload register (PRLHn) Lm : 8-bit value of PPG reload register (PRLLm) Hm : 8-bit value of PPG reload register (PRLHm) T : Count clock cycle Figure 15.5-7 shows the output wave form in 8+8-bit PPG output operation mode. Figure 15.5-7 Output Wave Form in 8+8-bit PPG Output Operation Mode Operation disable Operation start PPG operation enable bit (PEN0, PEN1) T × (L 0 + 1) T × (H 0 + 1) PPGn output pin PPGm output pin T × (L0 + 1) × (L1+ 1) Ln Hn Lm Hm T : 8-bit value of PPG reload register (PRLLn) : 8-bit value of PPG reload register (PRLHn) : 8-bit value of PPG reload register (PRLLm) : 8-bit value of PPG reload register (PRLHm) : Count clock cycle Note: 372 T × (H 0 + 1) × (H 1 + 1) n = 0, 2, 4, 6, 8, A, C, E m=n+1 FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 15 8/16-BIT PPG TIMER 15.6 MB90950 Series 15.6 Notes on Using 8/16-bit PPG Timer Note the following when using the 8/16-bit PPG timer. ■ Notes on Using 8/16-bit PPG Timer ● Effect on 8/16-bit PPG timer when using time-base timer output • If output of the time-base timer is used as count clock input of the 8/16-bit PPG timer (PPGnm: PCM2 to PCM0=111B, PCS2 to PCS0=111B), deviation may occur in the first count cycle in which the PPG timer is started by trigger input or in the count cycle immediately after the PPG timer is stopped. • When the time-base timer counter is cleared (TBTC:TBR=0) during count operation of the PPG down counter, deviation may occur in the count cycle. ● Setting of PPG reload registers when using 8-bit PPG timer • The "L" level side and "H" level side pulse widths are determined at the timing of reloading the values in the "L" level PPG reload registers (PRLLn, PRLLm) into the PPG down counter. • If the 8-bit PPG timer is used in 8-bit PPG output 2-channel independent operation mode or 8+8-bit PPG output operation mode, set both "H" level side and "L" level side of the PPG reload registers (PRLLn/PRLHn, PRLLm/PRLHm) at the same time using a word instruction. Using a byte instruction may cause an unexpected pulse to be generated. [Example of rewriting PPG reload registers using a byte instruction] If the value in the "H" level side PPG reload register (PRLH) is rewritten after the value in the "L" level side PPG reload register (PRLL) is rewritten using a byte instruction immediately before the signal level of the PPG pin switches from "H" to "L", a pulse having "L" width set after rewriting and "H" width set before rewriting will be generated just one time. Figure 15.6-1 shows a wave form of when the values in the PPG reload registers are rewritten using a byte instruction. Note: CM44-10148-4E n = 0, 2, 4, 6, 8, A, C, E m=n+1 FUJITSU MICROELECTRONICS LIMITED 373 CHAPTER 15 8/16-BIT PPG TIMER 15.6 MB90950 Series Figure 15.6-1 Wave Form of when PPG Reload Registers are Rewritten Using a Byte Instruction PRLL A PRLH B C D A +B A +B B +C C+D B B C+D C+D D D Timing of updating reload value PPG pin A B A C C C <1> <2> <1>: Change the value (A→ C) of PPG reload register (PRLL) <2>: Change the value (B → D) of PPG reload register (PRLH) ● Setting of PPG reload registers when using 16-bit PPG timer Set the PPG reload registers (PRLLn/PRLHn, PRLLm/PRLHm) using a long-word instruction or set PPGn → PPGm (PRLLn/PRLHn → PRLLm/PRLHm) in this order using a word instruction. [Reload timing in 16-bit PPG output operation mode] In 16-bit PPG output operation mode, the reload values written to the PPGn reload register are written temporarily to the temporary latch and then transferred to the PPGn reload register (PRLLn, PRLHn) after reload values are written to the PPGm reload register. Therefore, when setting PPGm reload values, it is necessary to set reload values in the PPGn reload register simultaneously or set reload values in the PPGn reload register before setting reload values in the PPGm reload register. Figure 15.6-2 shows the reload timing in 16-bit PPG output operation mode. Figure 15.6-2 Reload Timing in 16-bit PPG Output Operation Mode Reload value of PPGn Write to PPGn in any mode other than 16-bit PPG output operation mode 16-bit PPG output operation mode only Temporary latch 374 Write to PPGm Transfer in synchronization with writing to PPGm PPG reload register (PRLLn, PRLHn) Note: Reload value of PPGm PPG reload register (PRLLm, PRLHm) n = 0, 2, 4, 6, 8, A, C, E m=n+1 FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 16 DTP/EXTERNAL INTERRUPT This chapter explains the functions and operations of the DTP/external interrupt. 16.1 Overview of DTP/External Interrupt 16.2 Block Diagram of DTP/External Interrupt 16.3 Configuration of DTP/External Interrupt 16.4 Explanation of Operation of DTP/External Interrupt 16.5 Notes on Using DTP/External Interrupt 16.6 Program Example of DTP/External Interrupt Circuit CM44-10148-4E FUJITSU MICROELECTRONICS LIMITED 375 CHAPTER 16 DTP/EXTERNAL INTERRUPT 16.1 16.1 MB90950 Series Overview of DTP/External Interrupt The DTP/external interrupt sends interrupt requests from external peripheral devices or data transfer requests to CPU to generate an external interrupt request, or activates the DMA/extended intelligent I/O service (EI2OS). ■ DTP/External Interrupt Function The DTP/external interrupt follows the same procedure as resource interrupts to send interrupt requests from external peripheral devices to the CPU to generate an external interrupt request, or activates the DMA/extended intelligent I/O service (EI2OS). If the extended intelligent I/O service (EI2OS) is disabled in the interrupt control register (ICR:ISE=0) and the DMA transfer is disabled in the DMA enable register (DER:EN=0), the external interrupt function is enabled, branching to interrupt processing. If the DMA or the EI2OS is enabled, the DTP function is enabled and automatic data transfer is performed, branching to interrupt processing after the completion of data transfer for the specified number of times. Table 16.1-1 shows an overview of the DTP/external interrupt. Table 16.1-1 Overview of DTP/External Interrupt External Interrupt Input pin DTP Function 16 pins: INT0 to INT7, INT8 to INT15 (INT8R to INT15R) Set for each pin using the detection level setting registers (ELVR). Interrupt source Input of "H" level/"L" level Interrupt number #26(1AH), #28(1CH) Interrupt control The interrupt request output is enabled/disabled using the DTP/external interrupt enable register (ENIR) Interrupt flag The interrupt source is held using the DTP/external interrupt source register (EIRR) Processing selection DMA and EI2OS are disabled. (DER:EN=0 and ICR: ISE=0) DMA or EI2OS is enabled. (DER:EN=1 or ICR: ISE=1) A branch is caused to the external interrupt processing DMA or EI2OS performs automatic data transfer and completes the specified number of time for data transfers, causing a branch to the interrupt processing Process 376 Input of "H" level/"L" level/rising edge/ falling edge FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 16 DTP/EXTERNAL INTERRUPT 16.2 MB90950 Series 16.2 Block Diagram of DTP/External Interrupt A block diagram of the DTP/external interrupt is shown below. ■ Block Diagram of DTP/External Interrupt Figure 16.2-1 Block Diagram of DTP/External Interrupt Detection level setting register (ELVR0) LB7 LA7 LB6 LA6 LB5 LA5 LB4 LA4 Pin Level edge selector INT7 Pin Level edge selector Internal data bus Level edge selector Pin Level edge selector INT2 Level edge selector INT5 Pin Pin INT3 INT6 Pin LB3 LA3 LB2 LA2 LB1 LA1 LB0 LA0 Pin Level edge selector INT1 Level edge selector INT4 Pin Level edge selector INT0 DTP/external interrupt input detection circuit ER7 ER6 ER5 ER4 ER3 ER2 ER1 ER0 Interrupt request signal DTP/external interrupt source register (EIRR0) Interrupt request signal EN7 EN6 EN5 EN4 EN3 EN2 EN1 EN0 DTP/external interrupt enable register (ENIR0) CM44-10148-4E FUJITSU MICROELECTRONICS LIMITED 377 CHAPTER 16 DTP/EXTERNAL INTERRUPT 16.2 MB90950 Series Figure 16.2-2 Block Diagram of DTP/External Interrupt Detection level setting register (ELVR1) LB15 LA15 LB14 LA14 LB13 LA13 LB12 LA12 Pin Level edge selector INT15 Pin Level edge selector Internal data bus Level edge selector Pin Level edge selector INT10 Level edge selector INT13 Pin Pin INT11 INT14 Pin LB11 LA11 LB10 LA10 LB9 LA9 LB8 LA8 Pin Level edge selector INT9 Level edge selector INT12 Pin Level edge selector INT8 DTP/external interrupt input detection circuit ER15 ER14 ER13 ER12 ER11 ER10 ER9 ER8 Interrupt request signal DTP/external interrupt source register (EIRR1) Interrupt request signal EN15 EN14 EN13 EN12 EN11 EN10 EN9 EN8 DTP/external interrupt enable register (ENIR1) ● DTP/external interrupt input detection circuit This circuit detects interrupt requests or data transfer requests generated from external peripheral devices. The interrupt request flag bit corresponding to the pin whose level or edge set by the detection level setting register is detected is set to "1" (EIRR1:ER). 378 FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 16 DTP/EXTERNAL INTERRUPT 16.2 MB90950 Series ● Detection level setting register (ELVR0/ELVR1) This register sets the level or edge of input signals from external peripheral devices that cause DTP/external interrupt source. ● DTP/external interrupt source register (EIRR0/EIRR1) This register holds DTP/external interrupt sources. If a valid signal is input to the DTP/external interrupt pin, the corresponding DTP/external interrupt request flag bit is set to "1". ● DTP/external interrupt enable register (ENIR0/ENIR1) This register enables or disables DTP/external interrupt requests from external peripheral devices. ■ Details of Pins and Interrupt Numbers Table 16.2-1 shows the pins and interrupt numbers used in the DTP/external interrupt. Table 16.2-1 Pins and Interrupt Numbers Used by DTP/External Interrupt Pin Channel P70 INT0 P71 INT1 P72 INT2 P73 INT3 P74 INT4 P75 INT5 P76 INT6 P77 INT7 P00 / PA0 INT8 / INT8R P01 / P42 INT9 / INT9R P02 / P32 INT10 / INT10R P03 / P12 INT11 / INT11R P04 / P80 INT12 / INT12R P05 / P81 INT13 / INT13R P06 / P82 INT14 / INT14R P07 / P84 INT15 / INT15R Interrupt Number DMA Number #26(1AH) 3 #28(1CH) 4 #26(1AH) 3 #28(1CH) 4 INT8 to INT15 / INT8R to INT15R are selected in the external interrupt source select register (EISSR). CM44-10148-4E FUJITSU MICROELECTRONICS LIMITED 379 CHAPTER 16 DTP/EXTERNAL INTERRUPT 16.3 16.3 MB90950 Series Configuration of DTP/External Interrupt This section lists and details the pins, interrupt sources, and registers in the DTP/ external interrupt. ■ Pins of DTP/External Interrupt The pins used by the DTP/external interrupt serve as general-purpose I/O ports. Table 16.3-1 lists the pin functions and the pin setting required for use in the DTP/external interrupt. Table 16.3-1 Pins of DTP/External Interrupt (1 / 2) Pin Name Pin Function Pin Settings Required for Use in DTP/External Interrupt P70/INT0/AN16 P71/INT1/AN17 P72/INT2/AN18 P73/INT3/AN19 P74/INT4/AN20 General-purpose I/O ports / DTP external interrupt inputs / A/D converter analog input • Set as input ports in port direction register (DDR7) • Set the analog input enable register (ADER7) as disabled P75/INT5/AN21 P76/INT6/AN22 P77/INT7/AN23 P00/INT8/AD00 P01/INT9/AD01 P02/INT10/AD02 P03/INT11/AD03 P04/INT12/AD04 P05/INT13/AD05 General-purpose I/O ports / DTP external interrupt inputs / Address data bus lower I/O • Set the external interrupt source select register (EISSR) to 0 • Set as input ports in port direction register (DDR0) Note: Available only in the single-chip mode P06/INT14/AD06 P07/INT15/AD07 380 FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 16 DTP/EXTERNAL INTERRUPT 16.3 MB90950 Series Table 16.3-1 Pins of DTP/External Interrupt (2 / 2) Pin Name Pin Function PA0/ INT8R/ RX0 General-purpose I/O ports / DTP external interrupt inputs / CAN0 input Rx0 P42/ INT9R/ RX1/ IN6 General-purpose I/O ports / DTP external interrupt inputs / CAN1 input Rx1 / Input capture input IN6 P32/ INT10R/ WR1/WR/ RX2 General-purpose I/O ports / DTP external interrupt inputs / Write strobe outputs / CAN2 input Rx2 P12/ INT11R/ AD10/ SIN3 General-purpose I/O ports / DTP external interrupt inputs / Address data bus upper I/O UART3 input SIN3 P80/ INT12R/ TIN0/ ADTG General-purpose I/O ports / DTP external interrupt inputs / Reload timer 0 trigger input TIN0 / A/D converter trigger input ADTG P81/ INT13R/ TOT0/ CKOT General-purpose I/O ports / DTP external interrupt inputs / Reload timer 0 output TOT0 / Clock monitor output CKOT P82/ INT14R/ SIN0/ TIN2 General-purpose I/O ports / DTP external interrupt inputs / UART0 input SIN0 / Reload timer 2 trigger input TIN2 P84/ INT15R/ SCK0 General-purpose I/O ports / DTP external interrupt inputs / UART0 clock I/O SCK0 CM44-10148-4E Pin Settings Required for Use in DTP/External Interrupt • Set the external interrupt source select register (EISSR) to 1 • Set as input ports in port direction register (DDR) • Set the external interrupt source select register (EISSR) to 1 • Set as input ports in port direction register (DDR) • Set the timer control status register (TMCSR0:OUTE) as output disabled • Set the clock output enable register (CLKR:CKEN) as output disabled • Set the external interrupt source select register (EISSR) to 1 • Set as input ports in port direction register (DDR) FUJITSU MICROELECTRONICS LIMITED 381 CHAPTER 16 DTP/EXTERNAL INTERRUPT 16.3 MB90950 Series ■ List of Registers and Reset Values in DTP/External Interrupt Figure 16.3-1 List of Registers and Reset Values in DTP/External Interrupt 7 6 5 4 3 2 1 0 Initial value EN7 EN6 EN5 EN4 EN3 EN2 EN1 EN0 00000000 B 7 6 5 4 3 2 1 0 EN15 EN14 EN13 EN12 EN11 EN10 EN9 EN8 15 14 13 12 11 10 9 8 Address: 0000C7H ER7 ER6 ER5 ER4 ER3 ER2 ER1 ER0 bit EIRR1 Address: 0000CB H 15 14 13 12 11 10 9 8 ER15 ER14 ER13 ER12 ER11 ER10 ER9 ER8 7 6 5 4 3 2 1 0 LB3 LA3 LB2 LA2 LB1 LA1 LB0 LA0 15 14 13 12 11 10 9 8 LB7 LA7 LB6 LA6 LB5 LA5 LB4 LA4 7 6 5 4 3 2 1 0 LB11 LA11 LB10 LA10 LB9 LA9 LB8 LA8 15 14 13 12 11 10 9 8 LB15 LA15 LB14 LA14 LB13 LA13 LB12 LA12 7 6 5 4 3 2 1 0 ENIR0 bit Address: 0000C6 H ENIR1 bit Address: 0000CA H EIRR0 ELVR0 bit bit Address: 0000C8 H ELVR0 bit Address: 0000C9 H ELVR1 bit Address: 0000CCH ELVR1 bit Address: 0000CDH EISSR bit Address: 0000CE H INT15R INT14R INT13R INT12R INT11R INT10R INT9R INT8R 382 FUJITSU MICROELECTRONICS LIMITED 00000000 B XXXXXXXXB XXXXXXXXB 00000000 B 00000000B 00000000B 00000000B 00000000B CM44-10148-4E CHAPTER 16 DTP/EXTERNAL INTERRUPT 16.3 MB90950 Series 16.3.1 DTP/External Interrupt Source Register (EIRR0/EIRR1) This register holds DTP/external interrupt sources. If a valid signal is input to the DTP/external interrupt pin, the corresponding interrupt request flag bit is set to "1". EIRR0 corresponds to INT0 to INT7, and EIRR1 corresponds to INT8 to INT15/INT8R to INT15R. ■ DTP/External Interrupt Source Register (EIRR0/EIRR1) Figure 16.3-2 DTP/External Interrupt Source Register (EIRR0/EIRR1) Address EIRR0: 0000C7H bit 15 14 13 12 11 10 9 8 ER7 ER6 ER5 ER4 ER3 ER2 ER1 ER0 R/W R/W R/W R/W R/W R/W R/W R/W Initial value: XXXXXXXB bit15 to bit8 ER7 to ER0 0 1 Address EIRR1: 0000CBH bit 15 14 13 12 11 10 9 R/W R/W R/W R/W R/W R/W R/W R/W Writing Clear of ER bit No effect Initial value: XXXXXXXB bit15 to bit8 ER15 to ER8 CM44-10148-4E Reading No DTP/external interrupt input DTP/external interrupt input 8 ER15 ER14 ER13 ER12 ER11 ER10 ER9 ER8 R/W: Readable/writable X : Undefined DTP/External interrupt request flag bits 0 1 DTP/External interrupt request flag bits Reading No DTP/external interrupt input DTP/external interrupt input FUJITSU MICROELECTRONICS LIMITED Writing Clear of ER bit No effect 383 CHAPTER 16 DTP/EXTERNAL INTERRUPT 16.3 MB90950 Series Table 16.3-2 Function of DTP/External Interrupt Source Register (EIRR) Bit name bit15 to bit8 384 ER15 to ER8(EIRR1), ER7 to ER0(EIRR0): DTP/External interrupt request flag bits Function These bits are set to "1" when the edges or level signals set by the detection condition select bits in the detection level setting register (ELVR:LB, LA) are input to the DTP/external interrupt pins. When set to "1": When the DTP/external interrupt request enable bit (ENIR:EN) is set to "1", an interrupt request is generated to the corresponding DTP/external interrupt channel. When set to "0": Cleared. When set to "1": No effect. If setting "1" to these bits and writing "0" to them occur simultaneously, writing "0" has priority. Note: For a read-modify-write (RMW) instruction, "1" is always read. If more than one DTP/external interrupt request is enabled (ENIR:EN=1), clear only the bit in the channel that accepts an interrupt (EIRR:ER=0). No other bits must be cleared unconditionally. The value of DTP/external interrupt request flag bit (EIRR:ER) is valid only when DTP/external interrupt request enable bit (ENIR: EN) is set to "1". When DTP/external interrupt is disabled (ENIR: EN=0), DTP/external interrupt request flag bit may be set without relation that DTP/external interrupt factor exists. Clear the corresponding DTP/external interrupt request flag bit (EIRR:ER) immediately before enabling the DTP/external interrupt (ENIR: EN=1). Reference: When the DMA transfer or extended intelligent I/O service (EI2OS) is activated, the interrupt request flag bit is automatically cleared after the completion of data transfer (EIRR:ER=0). FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 16 DTP/EXTERNAL INTERRUPT 16.3 MB90950 Series 16.3.2 DTP/External Interrupt Enable Register (ENIR0/ENIR1) The DTP/external interrupt enable register (ENIR0/ENIR1) enables/disables the DTP/ external interrupt request in the external peripheral devices. ENIR0 corresponds to INT0 to INT7, and ENIR1 corresponds to INT8 to INT15/INT8R to INT15R. ■ DTP/External Interrupt Enable Register (ENIR0/ENIR1) Figure 16.3-3 DTP/External Interrupt Enable Register (ENIR0/ENIR1) bit 7 Address ENIR0: 0000C6H 6 5 4 3 2 1 0 EN7 EN6 EN5 EN4 EN3 EN2 EN1 EN0 R/W R/W R/W R/W R/W R/W R/W R/W Initial value: 00000000B bit7 to bit0 EN7 to EN0 0 1 bit 7 Address ENIR1: 0000CAH 6 5 4 3 2 1 0 EN15 EN14 EN13 EN12 EN11 EN10 EN9 EN8 R/W R/W R/W R/W R/W R/W R/W R/W Initial value: 00000000B bit7 to bit0 EN15 to EN8 0 1 R/W : Readable/writable : Initial value DTP/external interrupt request enable bits Disable DTP/external interrupt Enable DTP/external interrupt DTP/external interrupt request enable bits Disable DTP/external interrupt Enable DTP/external interrupt Table 16.3-3 Functions of DTP/External Interrupt Enable Register (ENIR0/ENIR1) Bit name bit7 to bit0 CM44-10148-4E EN15 to EN8(ENIR1), EN7 to EN0(ENIR0): DTP/external interrupt request enable bits Function These bits enable or disable the DTP/external interrupt request to the DTP/external interrupt channel. If the DTP/external interrupt request enable bit (ENIR:EN) and the DTP/external interrupt request flag bit (EIRR:ER) are set to "1", the interrupt request is generated to the corresponding DTP/ external interrupt pin. Reference: The state of the DTP/external interrupt pin can be read directly using the port data register irrespective of the setting of the DTP/ external interrupt request enable bit. FUJITSU MICROELECTRONICS LIMITED 385 CHAPTER 16 DTP/EXTERNAL INTERRUPT 16.3 MB90950 Series Table 16.3-4 Correspondence among DTP/External Interrupt Pins, DTP/External Interrupt Request Flag Bits, and DTP/External Interrupt Request Enable Bits 386 DTP/external interrupt pin DTP/external interrupt request flag bit DTP/external interrupt request enable bit INT0 ER0 EN0 INT1 ER1 EN1 INT2 ER2 EN2 INT3 ER3 EN3 INT4 ER4 EN4 INT5 ER5 EN5 INT6 ER6 EN6 INT7 ER7 EN7 INT8 / INT8R ER8 EN8 INT9 / INT9R ER9 EN9 INT10 / INT10R ER10 EN10 INT11 / INT11R ER11 EN11 INT12 / INT12R ER12 EN12 INT13 / INT13R ER13 EN13 INT14 / INT14R ER14 EN14 INT15 / INT15R ER15 EN15 FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 16 DTP/EXTERNAL INTERRUPT 16.3 MB90950 Series 16.3.3 Detection Level Setting Register (ELVR0/ELVR1) The detection level setting register sets the level or edge of input signals that cause the interrupt sources of the DTP/external interrupt pin. ELVR0 corresponds to INT0 to INT7, and ELVR1 corresponds to INT8 to INT15/INT8R to INT15R. ■ Detection Level Setting Register (ELVR0/ELVR1) Figure 16.3-4 Detection Level Setting Register (ELVR0/ELVR1) Address ELVR0: 0000C8B bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value LB7 LA7 LB6 LA6 LB5 LA5 LB4 LA4 LB3 LA3 LB2 LA2 LB1 LA1 LB0 LA0 0000000000000000B R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W bit15 to bit0 LB7, LB6 LB5, LB4 LB3, LB2 LB1, LB0 0 0 1 1 Address ELVR1: 0000CCB bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 LA7, LA6, LA5, LA4, LA3, LA2, LA1, LA0 Detection condition select bits 0 1 "L" level detection "H" level detection 0 1 Rising edge detection Falling edge detection 1 0 Initial value LB15 LA15 LB14 LA14 LB13 LA13 LB12 LA12 LB11 LA11 LB10 LA10 LB9 LA9 LB8 LA8 0000000000000000B R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W bit15 to bit0 LB15, LB14, LB13, LB12, LB11, LB10, LB9, LB8, LA15, LA14, LA13, LA12, LA11, LA10, LA9, LA8 0 0 1 0 1 R/W : Readable/writable : Initial value 0 1 1 Detection condition select bits "L" level detection "H" level detection Rising edge detection Falling edge detection Table 16.3-5 Functions of Detection Level Setting Register (ELVR0/1) Bit name bit15 to bit0 ELVR1: LB15, LA15 to LB8, LA8 ELVR0: LB7, LA7 to LB0, LA0 Detection condition select bits CM44-10148-4E Function These bits set the levels or edges of input signals from external peripheral devices that cause interrupt sources in the DTP/external interrupt pins. • Two levels or two edges are selectable for external interrupts, and two levels are selectable for DMA or EI2OS. Reference: When the set detection signal is input to the DTP/external interrupt pins, the DTP/external interrupt request flag bits are set to "1" even if DTP/external interrupt requests are disabled (ENIR:EN=0). FUJITSU MICROELECTRONICS LIMITED 387 CHAPTER 16 DTP/EXTERNAL INTERRUPT 16.3 MB90950 Series Note: If any setting of this register is changed, the interrupt source flag can be set. Therefore, If you want to change the setting of this register, disable the interrupt (or, set the corresponding bit of ENIR0/ENIR1 to "0") in advance. To enable the interrupt (or, set the corresponding bit of ENIR0/ENIR1 to "1") after the setting of this register is changed, be sure to clear the interrupt source flag bit (the corresponding bit of EIRR0/ EIRR1). Table 16.3-6 Correspondence between Detection Level Setting Register and Channels DTP/External Interrupt Pin Register Name Bit name INT0 LB0, LA0 INT1 LB1, LA1 INT2 LB2, LA2 INT3 LB3, LA3 ELVR0 INT4 LB4, LA4 INT5 LB5, LA5 INT6 LB6, LA6 INT7 LB7, LA7 INT8 / INT8R LB8, LA8 INT9 / INT9R LB9, LA9 INT10 / INT10R LB10, LA10 INT11 / INT11R LB11, LA11 ELVR1 388 INT12 / INT12R LB12, LA12 INT13 / INT13R LB13, LA13 INT14 / INT14R LB14, LA14 INT15 / INT15R LB15, LA15 FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 16 DTP/EXTERNAL INTERRUPT 16.3 MB90950 Series 16.3.4 External Interrupt Source Select Register (EISSR) This register can change the assignment of the external interrupt pin of upper 8 bits. This allows the external interrupt of upper 8-bits when the external bus is used. Also, the function such as CAN wakeup is implemented. ■ Selection of External Interrupt Source The external interrupt pin of the upper 8-bit is normally assigned to INT15 to INT8, and shares the port 0/ external bus and pin. In the external bus mode, the port 0 cannot be used as the external interrupt pin. However, those external interrupt can be used by assigning them to other pins (INT15R to INT8R). The pin is switched by the external interrupt source select register (EISSR). In addition, because INT15R to INT8R share the function such as CAN input pin, the function such as CAN wakeup is implemented. See Table 16.3-8 for the pin function of INT15R to INT8R. Figure 16.3-5 DTP/External Interrupt Source Select Register (EISSR) 7 6 5 4 3 2 1 0 Address EISSR: 0000CEH INT15R INT14R INT13R INT12R INT11R INT10R INT9R INT8R Initial value: 00000000B R/W R/W R/W R/W R/W R/W R/W R/W bit7 to bit0 INT15R to INT8R R/W : Readable/writable X : Undefined : Initial value 0 1 External Interrupt Source Select Bits Set pins INT15 to INT8 (Port 0) as external interrupt source Set pins INT15R to INT8R as external interrupt source * See Table 16.3-8 for the pin assignment of INT15R to INT8R. Table 16.3-7 Function of DTP/External Interrupt Source Select Register (EISSR) Bit name bit7 to bit0 CM44-10148-4E INT15R to INT8R: External interrupt source select bits Function When these bits are set to "1", the input pin of the corresponding external interrupt source (upper 8-bit) is assigned to the INT15R to INT8R. When set to "0": The external interrupt source of the upper 8-bit is assigned to INT15 to INT8 pins. When set to "1": The external interrupt source of the upper 8-bit is assigned to the INT15R to INT8R pins. FUJITSU MICROELECTRONICS LIMITED 389 CHAPTER 16 DTP/EXTERNAL INTERRUPT 16.3 MB90950 Series Table 16.3-8 External Interrupt Source Select (Upper 8-bit) 390 EISSR Bit "0" (Initial Value) INT8R INT8 : P00 INT8R : PA0 (RX0) INT9R INT9 : P01 INT9R : P42 (RX1/IN6) INT10R INT10: P02 INT10R: P32 (RX2) INT11R INT11: P03 INT11R: P12 (SIN3) INT12R INT12: P04 INT12R: P80 (TIN0/ADTG) INT13R INT13: P05 INT13R: P81 (TOT0/CKOT) INT14R INT14: P06 INT14R: P82 (SIN0/TIN2) INT15R INT15: P07 INT15R: P84 (SCK0) FUJITSU MICROELECTRONICS LIMITED "1" CM44-10148-4E CHAPTER 16 DTP/EXTERNAL INTERRUPT 16.4 MB90950 Series 16.4 Explanation of Operation of DTP/External Interrupt The DTP/external interrupt has an external interrupt function and a DTP function. This section explains the setting and operation of each function. ■ Setting of DTP/External Interrupt Using the DTP/external interrupt requires the setting shown in Figure 16.4-1. Figure 16.4-1 Setting of DTP/External Interrupt bit15 14 ICR Interrupt Control Register (EI2 At DTP OS) At DTP (DMA) ENIR1/ENIR0 11 10 9 bit8 bit7 6 5 4 3 2 1 bit0 – – – – 0 1 – – – 0 1 EN15 EN14 EN13 EN12 EN11 EN10 EN9 EN8 EN7 EN6 EN5 EN4 EN3 EN2 EN1 EN0 – – – – – – – – – – – – – – – – – – – – – – 0 1 0 1 – – – – – – EN15 EN14 EN13 EN12 EN11 EN10 EN9 EN8 EN7 EN6 EN5 EN4 EN3 EN2 EN1 EN0 ❍ EIRR1/EIRR0 12 ICS3 ICS2 ICS1 ICS0 ISE IL2 IL1 IL0 ICS3 ICS2 ICS1 ICS0 ISE IL2 IL1 IL0 At external interrupt/DTP (DMA) – At DTP (EI2OS) DER (DMA enable register) 13 ❍ ❍ ❍ ❍ ❍ ❍ ❍ ❍ ❍ ❍ ❍ ❍ ❍ ❍ ❍ ER15 ER14 ER13 ER12 ER11 ER10 ER9 ER8 ER7 ER6 ER5 ER4 ER3 ER2 ER1 ER0 ELVR0 LB7 LA7 LB6 LA6 LB5 LA5 LB4 LA4 LB3 LA3 LB2 LA2 LB1 LA1 LB0 LA0 ELVR1 LB15 LA15 LB14 LA14 LB13 LA13 LB12 LA12 LB11 LA11 LB10 LA10 LB9 LA9 LB8 LA8 DDR port direction register Set the bit corresponding to pin used for the DTP/external interrupt input to "0" ADER7 (Analog input enable) Only when using INT7 to INT0 ● TMCSR0 (Timer control) Only when using INT13R ● Reserved Reserved – – ● ● – – – – ● ● ● ● CSL1 CSL0 MOD2 MOD1 MOD0 OUTE OUTL RELD INTE UF CNTE TRG – – – – – 0 – – CLKR (Clock output enable) Only when using INT13R − ❍ ● 0 1 – – – – CKEN FRQ2 FRQ1 FRQ0 – – – – – – – – – – – – 0 – – – : Undefined bit : Used bit : Set the bit corresponding to used pin to "1" : Set the bit corresponding to used pin to "0" : Set "0" : Set "1" CM44-10148-4E FUJITSU MICROELECTRONICS LIMITED 391 CHAPTER 16 DTP/EXTERNAL INTERRUPT 16.4 MB90950 Series ● Setting procedure To use the DTP/external interrupt, set each register by using the following procedure: 1. Set the input port to the general-purpose I/O port, which is shared with the pin to be used as external interrupt input. 2. Set the interrupt request enable bit corresponding to the DTP/external interrupt channel to be used to "0" (ENIR:EN). 3. Use the detection condition select bit corresponding to the DTP/external interrupt pin to be used to set the edge or level to be detected (ELVR:LA, LB). 4. Set the interrupt request flag bit corresponding to the DTP/external interrupt channel to be used to "0" (EIRR:ER). 5. Set the interrupt request enable bit corresponding to the DTP/external interrupt channel to be used to "1" (ENIR:EN). • When setting the registers for the DTP/external interrupt, the external interrupt request must be disabled in advance (ENIR:EN=0). • When enabling the DTP/external interrupt request (ENIR:EN=1), the corresponding DTP/external interrupt request flag bit must be cleared in advance (EIRR:ER=0). These actions prevent an interrupt request from mistakenly occurring when setting the register. ● Selecting of external interrupt function and DTP function Whether the external interrupt function or the DTP function is executed depends on the setting of the EI2OS enable bit (ICR:ISE) and DMA enable register (DER:EN) in the corresponding interrupt control register. If the ISE bit is set to "1", the extended intelligent I/O service (EI2OS) is enabled. If the EN bit is set to "1", the DMA transfer is enabled. If both the ISE and EN bits are set to "0", the EI2OS or DMA transfer is disabled, and the external interrupt function is executed. Notes: • All interrupt requests assigned to one interrupt control register have the same interrupt levels (IL2 to IL0). • If two or more interrupt requests are assigned to one interrupt control register and the EI2OS is used in one of them, other interrupt requests cannot be used. 392 FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 16 DTP/EXTERNAL INTERRUPT 16.4 MB90950 Series ■ DTP/External Interrupt Operation Table 16.4-1 shows the control bits and the interrupt sources for the DTP/external interrupt. Table 16.4-1 Control Bits and Interrupt Sources for DTP/External Interrupt DTP/External Interrupt Interrupt request flag bit EIRR0: ER7 to ER0, EIRR1: ER15 to ER8 Interrupt request enable bit ENIR0: EN7 to EN0, ENIR1: EN15 to EN8 Interrupt source Input of valid edge/level to INT15 to INT0, INT15R to INT8R pins If the interrupt request from the DTP/external interrupt is output to the interrupt controller and the EI2OS enable bit (ICR:ISE) and DMA enable register (DER:EN) in the interrupt control register are set to "0", the interrupt processing is executed. If either of the bits is set to "1", the extended intelligent I/O service (EI2OS) or DMA transfer is executed. CM44-10148-4E FUJITSU MICROELECTRONICS LIMITED 393 CHAPTER 16 DTP/EXTERNAL INTERRUPT 16.4 MB90950 Series Figure 16.4-2 shows the operation of the DTP/external interrupt. Figure 16.4-2 Operation of DTP/External Interrupt DTP/external interrupt circuit Other request ELVR Interrupt controller CPU ICR YY EIRR IL CMP CMP ILM ICR XX ENIR Interrupt processing Source DMA activation DTP/external interrupt request generated Memory ↔ Peripheral data transfer Interrupt controller reception judge Renewal of descriptor Descriptor data counter CPU interrupt reception judge =0 Interrupt processing ≠0 Reset or stop Interrupt processing microprogram activation Recovery from DTP processing Recovery from DMA processing (DTP processing) 1 DER:EN EI2OS activation 0 1 Memory ↔ Peripheral data transfer ICR:ISE Renewal of descriptor 0 External interrupt activation Descriptor data counter Processing and interrupt flag clear =0 Interrupt processing ≠0 Reset or stop Recovery from external interrupt Recovery from DTP processing Recovery from EI2OS processing (DTP processing) 394 FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 16 DTP/EXTERNAL INTERRUPT 16.4 MB90950 Series 16.4.1 External Interrupt Function The DTP/external interrupt has an external interrupt function for generating an interrupt request by detecting the signal (edge or level) in the DTP/external interrupt pin. ■ External Interrupt Function • When the signal (edge or level) set in the detection level setting register is detected in the DTP/external interrupt pin, the interrupt request flag bit in the DTP/external interrupt source register (EIRR:ER) is set to "1". • If the interrupt request enable bit in the DTP/external interrupt enable register is enabled (ENIR:EN=1) with the interrupt request flag bit set to "1", the interrupt request generation is posted to the interrupt controller. • If an interrupt request is preferred to other interrupt request by the interrupt controller, the interrupt request is generated. • If the level of an interrupt request (ICR:IL) is higher than that of the interrupt level mask bit in the condition code register (CCR:ILM) and the interrupt enable bit is enabled (CCR:I=1), the CPU performs interrupt processing after completion of the current instruction execution and branches to interrupt processing. • At interrupt processing, set the corresponding DTP/external interrupt request flag bit to "0" and clear the DTP/external interrupt request. Notes: • When the DTP/external interrupt activation source is generated, the DTP/external interrupt request flag bit (EIRR:ER) is set to "1", regardless of the setting of the DTP/external interrupt request enable bit (ENIR:EN). • When the interrupt processing is activated, clear the DTP/external interrupt request flag bit that caused the activation source. Control cannot be returned from the interrupt while the DTP/ external interrupt request flag bit is set to "1". When clearing, do not clear any flag bit other than the accepted DTP/external interrupt source. CM44-10148-4E FUJITSU MICROELECTRONICS LIMITED 395 CHAPTER 16 DTP/EXTERNAL INTERRUPT 16.4 16.4.2 MB90950 Series DTP Function The DTP/external interrupt has the DTP function that detects the signal of the external peripheral device from the DTP/external interrupt pin to activate the DMA transfer or extended intelligent I/O service (EI2OS). ■ DTP Function The DTP function detects the signal level set by the detection level setting register of the DTP/external interrupt function to activate the DMA transfer or EI2OS. • When the DMA transfer is already enabled (DER:EN=1) at the point when the interrupt request is accepted, DMA is activated and the data starts to be transferred. • When the EI2OS operation is already enabled (ICR:ISE=1) at the point when the interrupt request is accepted, EI2OS is activated and the data starts to be transferred. • When transfer of one data item is completed, the descriptor is updated and the DTP/external interrupt request flag bit is cleared to prepare for the next request from the DTP/external interrupt pin. • When the DMA/EI2OS completes transfer of all the data, control branches to the interrupt processing. Figure 16.4-3 Example of Interface with External Peripheral Device (When Using EI2OS in Single-chip Mode) "H" level request (ELVR:LB0, LA0=01B) Input to INT0 pin (DTP source) Descriptor CPU internal operation select and read Update of descriptor Peripheral device of external connection Internal data bus Read and write operation*2 DTP source*1 Data transfer request Interrupt INT DTP/external request interrupt circuit CPU (EI 2OS) Internal memory *1: This must be canceled within three machine clocks after the start of data transfer. *2: When the extended intelligent I/0 service is "peripheral function → internal memory transfer". 396 FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 16 DTP/EXTERNAL INTERRUPT 16.5 MB90950 Series 16.5 Notes on Using DTP/External Interrupt This section explains the precautions when using the DTP/external interrupt. ■ Notes on Using DTP/External Interrupt ● Condition of external-connected peripheral device when DTP function is used • When using the DTP function, the peripheral device must automatically clear a data transfer request when data transfer is performed. • Inactivate the transfer request signal within three machine clocks after starting data transfer. If the transfer request signal remains active, the DTP/external interrupt regards the transfer request signal as a generation of next transfer request. ● External interrupt input polarity • When the edge detection is set in the detection level setting register, the minimum pulse width is required to detect the edge described in the data sheet. See the data sheet. • When a level causing an interrupt source is input with level detection set in the detection level setting register, the interrupt request flag bit in the DTP/external interrupt source register (EIRR:ER) is set to "1" and the source is held as shown in Figure 16.5-1. With the source is held in the interrupt request flag bit (EIRR:ER), the request to the interrupt controller remains active if the interrupt request is enabled (ENIR:EN=1) even after the DTP/external interrupt source is canceled. To cancel the request to the interrupt controller, clear the interrupt request flag bit (EIRR:ER) as shown in Figure 16.5-2. Figure 16.5-1 Clearing Interrupt Request Flag Bit (EIRR:ER) when Level is Set DTP/external interrupt source DTP/interrupt input detection circuit Interrupt request flag bit (EIRR:ER) Enable gate To interrupt controller (interrupt request) The source remains held unless cleared. Figure 16.5-2 DTP/External Interrupt Source and Interrupt Request Generated when Interrupt Request is Enabled DTP/external interrupt source (when "H" level detected) Interrupt source canceled Interrupt request issued to interrupt controller The interrupt request is inactivated by clearing the interrupt request flag bit (EIRR:ER) CM44-10148-4E FUJITSU MICROELECTRONICS LIMITED 397 CHAPTER 16 DTP/EXTERNAL INTERRUPT 16.5 MB90950 Series ● Precautions on interrupts • When the DTP/external interrupt is used as the external interrupt function, no return from interrupt processing can be made with the DTP/external interrupt request flag bit set to "1" (EIRR:ER=1) and the DTP/external interrupt request set to "enabled" (ENIR:EN=1). Always set the DTP/external interrupt request flag bit to "0" (EIRR:ER=0) at interrupt processing. • When the level detection is set in the detection level setting register and the level that becomes the interrupt source remains input, the DTP/external interrupt request flag bit is reset immediately even when cleared (EIRR:ER=0). Disable the DTP/external interrupt request output as needed (ENIR:EN=0), or cancel the interrupt source itself. 398 FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 16 DTP/EXTERNAL INTERRUPT 16.6 MB90950 Series 16.6 Program Example of DTP/External Interrupt Circuit This section gives a program example for the DTP/external interrupt function. ■ Program Example of DTP/External Interrupt Function ● Processing specification An external interrupt is generated by detecting the rising edge of the pulse input to the INT0 pin. ● Coding example ICR07 DDR7 ENIR0 EQU EQU EQU 0000B7H 000017H 0000C6H ;Interrupt control register ICR7 ;Port 7 direction register ;DTP/external interrupt enable ;register 0 EIRR0 EQU 0000C7H ;DTP/external interrupt source ;register 0 ELVR0L EQU 0000C8H ;Detection level setting register ;0:"L" ELVR0H EQU 0000C9H ;Detection level setting register ;0:"H" ADER7 EQU 00000DH ;Port7 analog input enable register ER0 EQU EIRR0:0 ;INT0 Interrupt request flag bit EN0 EQU ENIR0:0 ;INT0 Interrupt request enable bit ;---------Main program--------------------------------------CODE CSEG START: ;Stack pointer (SP), etc., already initialized MOV I:ADER7,#00000000B ;Set analog input of Port7 to ;disabled MOV I:DDR7,#00000000B ;Set DDR7 to input port AND CCR,#0BFH ;Interrupts disabled MOV I:ICR07,#00H ;Interrupt level 0 (highest) CLRB I:EN0 ;INT0 disabled using ENIR MOV I:ELVR0L,#00000010B;Rising edge selected for INT0 CLRB I:ER0 ;INT0 interrupt request flag cleared ;using EIRR SETB I:EN0 ;INT0 interrupt request enabled using ;ENIR MOV ILM,#07H ;Set ILM in PS to level 7 OR CCR,#40H ;Interrupt enabled LOOP: • Processing by user • BRA CM44-10148-4E LOOP FUJITSU MICROELECTRONICS LIMITED 399 CHAPTER 16 DTP/EXTERNAL INTERRUPT 16.6 MB90950 Series ;---------Interrupt program---------------------------------WARI: CLRB I:ER0 ;Interrupt request flag cleared • Processing by user • RETI ;Return from interrupt processing CODE ENDS ;---------Vector setting------------------------------------VECT CSEG ABS=0FFH ORG 00FF94H ;Set vector to interrupt number ;#26(1AH) DSL WARI ORG 00FFDCH ;Set reset vector DSL START DB 00H ;Set to single-chip mode VECT ENDS END START ■ Program Example of DTP Function ● Processing specification • Channel 0 of the extended intelligent I/O service (EI2OS) is activated by detecting the "H" level of the signal input to the INT0 pin. • RAM data is output to port 0 by performing DTP processing (EI2OS). ● Coding example 400 ICR07 EQU 0000B7H DDR0 DDR7 ENIR0 EQU EQU EQU 000010H 000017H 0000C6H EIRR0 EQU 0000C7H ELVR0L ELVR0H ADER7 ER0 EN0 ; BAPL BAPM BAPH ISCS IOAL IOAH EQU EQU EQU EQU EQU 0000C8H 0000C9H 00000DH EIRR:0 ENIR:0 ;DTP/external interrupt control ;register ;Port 0 direction register ;Port 7 direction register ;DTP/external interrupt enable ;register 0 ;DTP/external interrupt source ;register 0 ;Detection level setting register 0: L ;Detection level setting register 0: H ;Port7 analog input enable register ;INT0 Interrupt request flag bit ;INT0 Interrupt request enable bit EQU EQU EQU EQU EQU EQU 000100H 000101H 000102H 000103H 000104H 000105H ;Buffer address pointer lower ;Buffer address pointer middle ;Buffer address pointer higher ;EI2OS status register ;I/O address register lower ;I/O address register higher FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 16 DTP/EXTERNAL INTERRUPT 16.6 MB90950 Series DCTL EQU 000106H ;Data counter lower DCTH EQU 000107H ;Data counter higher ; ;---------Main program--------------------------------------CODE CSEG START: ;Stack pointer (SP), etc., already initialized MOV I:ADER7,#00000000B ;Set analog input of Port7 to ;disabled MOV I:DDR0,#11111111B ;Set DDR0 to output port MOV I:DDR7,#00000000B ;Set DDR7 to input port AND CCR,#0BFH ;Interrupts disabled MOV I:ICR07,#08H ;Interrupt level 0 (highest) EI2OS ;ch.0 ;Data bank register (DTB) = 00H MOV BAPL,#00H ;Address for storing output data set MOV BAPM,#06H ;(600H to 60AH used) MOV BAPH,#00H MOV ISCS,#12H ;Byte transfer, buffer address + 1, ;I/O address fixed, transfer from ;memory to I/O MOV IOAL,#00H ;Set port 0 as transfer destination MOV IOAH,#00H ;address pointer MOV DCTL,#0AH ;Set transfer count to 10 MOV DCTH,#00H ; CLRB I:EN0 ;INT0 disabled using ENIR MOV I:ELVR0L,#00000001B ;"H" level detection set for INT0 CLRB I:ER0 ;INT0 interrupt request flag cleared ;using EIRR SETB I:EN0 ;INT0 interrupt request enabled using ;ENIR MOV ILM,#07H ;Set ILM in PS to level 7 OR CCR,#40H ;Interrupt enabled LOOP: • Processing by user • BRA LOOP ; ;---------Interrupt program---------------------------------WARI: CLRB I:ER0 ;INT0 interrupt request flag cleared • Processing by user • CODE ; CM44-10148-4E RETI ENDS ;Return from interrupt processing FUJITSU MICROELECTRONICS LIMITED 401 CHAPTER 16 DTP/EXTERNAL INTERRUPT 16.6 MB90950 Series ;---------Vector setting------------------------------------VECT CSEG ABS=0FFH ORG 00FF94H ;Set vector to interrupt number ;#26(1AH) DSL WARI ORG 00FFDCH ;Set reset vector DSL START DB 00H ;Set to single-chip mode VECT ENDS END START 402 FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 17 8/10-BIT A/D CONVERTER This chapter explains the functions and operations of the 8/10-bit A/D converter. 17.1 Overview of 8/10-bit A/D Converter 17.2 Block Diagram of 8/10-bit A/D Converter 17.3 Configuration of 8/10-bit A/D Converter 17.4 Interrupt of 8/10-bit A/D Converter 17.5 Operating Explanation of 8/10-bit A/D Converter 17.6 Notes on Using 8/10-bit A/D Converter CM44-10148-4E FUJITSU MICROELECTRONICS LIMITED 403 CHAPTER 17 8/10-BIT A/D CONVERTER 17.1 17.1 MB90950 Series Overview of 8/10-bit A/D Converter The 8/10-bit A/D converter converts an analog input voltage to an 8- or 10-bit digital value by using RC-type successive approximation conversion method. • The input signal can be selected from analog input pins of up to 24 channels. • The activation trigger can be selected from software trigger, internal timer output, and external trigger. ■ Functions of 8/10-bit A/D Converter The 8/10-bit A/D converter converts an analog voltage (input voltage) that is input to the analog input pin to an 8- or 10-bit digital value (A/D conversion). The 8/10-bit A/D converter has the following functions: • A/D conversion time is a minimum of 1.78 μs* per channel including sampling time. • Sampling time is a minimum of 0.75 μs* per channel. • Conversion method is RC-type successive approximation conversion method with sample & hold circuit. • A resolution of 8 bits or 10 bits can be set. • The analog input pins can be used up to 24 channels. • An interrupt request can be generated by storing an A/D conversion result to the A/D data register. • When an interrupt request is generated, μDMAC or EI2OS can be activated. • The activation trigger can be selected from software, internal timer output, and external trigger (falling edge). * : When the machine clock frequency is 32MHz and AVCC is 4.5V or higher. 404 FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 17 8/10-BIT A/D CONVERTER 17.1 MB90950 Series ■ Conversion Modes of 8/10-bit A/D Converter The following types of conversion modes are available for the 8/10-bit A/D converter. Table 17.1-1 Conversion Modes of 8/10-bit A/D Converter Conversion mode CM44-10148-4E Description Single conversion mode A/D conversion is performed sequentially from the start channel to the end channel. When A/D conversion for the end channel ends, the A/D conversion function is stopped. Continuous conversion mode A/D conversion is performed sequentially from the start channel to the end channel. When A/D conversion for the end channel ends, the A/D conversion continues to operate by returning to the start channel. Stop conversion mode A/D conversion is performed stopping by one channel. When A/D conversion for the end channel ends, it returns to the start channel and repeats A/D conversions and the stops. FUJITSU MICROELECTRONICS LIMITED 405 CHAPTER 17 8/10-BIT A/D CONVERTER 17.2 17.2 MB90950 Series Block Diagram of 8/10-bit A/D Converter The 8/10-bit A/D converter consists of the following blocks. ■ Block Diagram of 8/10-bit A/D Converter Figure 17.2-1 Block Diagram of 8/10-bit A/D Converter Interrupt request output A/D control status register BUSY INT INTE PAUS STS1 STS0 STRT ⎯ MD1 MD0 S10 ⎯ (ADCS0/ADCS1) ⎯ ⎯ ⎯ Reserved 2 ADTG Pin From 16-bit reload timer 1 TO Activation selector Software activation 2 AN0 to AN7 AN15 to AN8 AN23 to AN16 Comparator Control circuit Analog channel selector AVRH/AVRL AVcc AVss D/A converter 3 3 ADC_END (Conversion result write) Sample & hold circuit Buffer register Internal data bus φ Conversion result write control circuit OE A/D data register D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 (ADCR0/ ADCR1) Decoder 10 A/D setting register (ADSR0/ ST2 ST1 ST0 CT2 CT1 CT0 ANS4 ANS3 ANS2 ANS1 ANS0 ANE4 ANE3 ANE2 ANE1 ANE0 ADSR1) TO ⎯ Reserved φ 406 : Internal timer output : Undefined : Be sure to set to "0" : Machine clock FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 17 8/10-BIT A/D CONVERTER 17.2 MB90950 Series ● Details of pins in block diagram Table 17.2-1 shows the actual pin names and interrupt request numbers for the 8/10-bit A/D converter. Table 17.2-1 Pins and Interrupt Request Numbers in Block Diagram Pin name/interrupt request number in block diagram ADTG Actual pin name/interrupt request number Trigger input pin P80/ADTG Internal timer output Output of 16-bit reload timer 1 AN0 to AN7 Analog input pins ch.0 to ch.7 P60/AN0 to P67/AN7 AN8 to AN15 Analog input pins ch.8 to ch.15 P50/AN8 to P57/AN15 AN16 to AN23 Analog input pins ch.16 to ch.23 P70/AN16 to P77/AN23 AVRH / AVRL Vref+ / Vref- input pin AVRH / AVRL AVCC VCC input pin AVCC AVSS VSS input pin AVSS Interrupt request output #29(1DH) TO Interrupt request output ● A/D control status register (ADCS) This register activates the A/D conversion function by software, selects the activation trigger for the A/D conversion function, selects the conversion mode, enables or disables interrupt request, checks and clears the interrupt request flag, pauses A/D conversion operation and checks the status during conversion, and selects the resolution. ● Buffer register This register temporarily stores the A/D conversion result. ● A/D data register (ADCR) The A/D conversion result is temporarily stored in the buffer register. The result is stored in this register when the result is determined after the A/D conversion. This register can be used to read the result. ● A/D setting register (ADSR) This register sets the start channel, end channel, compare time and sampling time for A/D conversion. ● Activation selector This selector selects the trigger to start A/D conversion. An internal timer output or external pin input can be set as the start trigger. CM44-10148-4E FUJITSU MICROELECTRONICS LIMITED 407 CHAPTER 17 8/10-BIT A/D CONVERTER 17.2 MB90950 Series ● Decoder This decoder selects the analog input pin to be used for A/D conversion based on the settings of the A/D conversion start channel selection bits (ADSR: ANS4 to ANS0) and the A/D conversion end channel selection bits (ADSR: ANE4 to ANE0) in the A/D setting register. ● Analog channel selector This selector selects the pin to be used for A/D conversion from analog input pins of 24 channels by receiving a signal from the decoder. ● Sample & hold circuit This circuit holds the input voltage selected by the analog channel selector. The conversion can be performed without being affected by the fluctuation of the input voltage during the A/D conversion by holding the input voltage immediately after A/D conversion is stared. ● D/A converter This converter generates the reference voltage to compare it with the input voltage held in the sample & hold circuit. ● Comparator This comparator compares the D/A converter output voltage with the input voltage held in the sample & hold circuit to determine which voltage has a larger/smaller size. ● Control circuit This circuit determines the A/D conversion value by receiving the large/small signal from the comparator. When the conversion result is determined, the result data is stored in the A/D data register via the conversion result write control circuit. If interrupt request is enabled, an interrupt is generated. ● Conversion result write control circuit When the conversion result is determined after A/D conversion, the result temporarily stored in the buffer register is transferred to the A/D data register. 408 FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 17 8/10-BIT A/D CONVERTER 17.3 MB90950 Series 17.3 Configuration of 8/10-bit A/D Converter This section shows the pins, registers, and interrupt sources of the A/D converter. ■ Pins of 8/10-bit A/D Converter The pins of the 8/10-bit A/D converter serve as general-purpose I/O ports. Table 17.3-1 shows the pin functions and pin settings for using the 8/10-bit A/D converter. Table 17.3-1 Pins of 8/10-bit A/D Converter (1 / 2) Function name Pin name Trigger input P80 / ADTG ch.0 P60 / AN0 ch.1 P61 / AN1 ch.2 P62 / AN2 ch.3 P63 / AN3 ch.4 P64 / AN4 ch.5 P65 / AN5 ch.6 P66 / AN6 ch.7 P67 / AN7 ch.8 P50 / AN8 ch.9 P51 / AN9 ch.10 P52 / AN10 ch.11 P53 / AN11 ch.12 P54 / AN12 ch.13 P55 / AN13 ch.14 P56 / AN14 ch.15 P57 / AN15 CM44-10148-4E Settings for using 8/10-bit A/D converter Pin function General-purpose I/O port / external trigger input Set as input port in port direction register DDR8 General-purpose I/O port / analog input / PPG output Enable input of analog signal (Set the bits corresponding to ADER6: ADE7 to ADE0 to "1") General-purpose I/O port / analog input / UART2 I/O General-purpose I/O port / analog input / reload timer 3 I/O Enable input of analog signal (Set the bits corresponding to ADER5: ADE15 to ADE8 to "1") General-purpose I/O port / analog input FUJITSU MICROELECTRONICS LIMITED 409 CHAPTER 17 8/10-BIT A/D CONVERTER 17.3 MB90950 Series Table 17.3-1 Pins of 8/10-bit A/D Converter (2 / 2) 410 Function name Pin name ch.16 P70 / AN16 ch.17 P71 / AN17 ch.18 P72 / AN18 ch.19 P73 / AN19 ch.20 P74 / AN20 ch.21 P75 / AN21 ch.22 P76 / AN22 ch.23 P77 / AN23 Settings for using 8/10-bit A/D converter Pin function General-purpose I/O port / analog input / external interrupt input Enable input of analog signal (Set the bits corresponding to ADER7: ADE23 to ADE16 to "1") FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 17 8/10-BIT A/D CONVERTER 17.3 MB90950 Series ■ List of Registers and Initial Values of 8/10-bit A/D Converter Figure 17.3-1 List of Registers and Initial Values of 8/10-bit A/D Converter A/D control status register 1 ADCS1 14 bit 15 Address: 000069H BUSY INT R/W 13 12 11 10 9 R/W R/W R/W R/W A/D control status register 0 ADCS0 bit 7 6 5 4 3 2 00000001 B W 1 0 MD1 MD0 S10 Reserved R/W R/W R/W A/D data register 1 ADCR1 bit 15 R/W 14 13 12 11 10 Address: 00006BH A/D data register 0 ADCR0 bit 7 Address: 00006AH Initial value INTE PAUS STS1 STS0 STRT R/W Address: 000068H 8 9 8 D9 R D8 R Initial value 00011110 B Initial value 11111100 B 6 5 4 3 2 1 0 Initial value D7 D6 D5 D4 D3 D2 D1 D0 00000000B R R R R R R R R ADSR1 A/D setting register 1 ADSR1 bit 15 14 13 ST2 R/W ST1 R/W ST0 R/W A/D setting register 0 ADSR0 bit 7 6 5 Address: 00006DH Address: 00006CH 12 11 10 CT2 CT1 R/W R/W 4 3 9 8 Initial value CT0 ANS4 ANS3 R/W R/W R/W 2 1 0 ANS2 ANS1 ANS0 ANE4 ANE3 ANE2 ANE1 ANE0 R/W R/W R/W R/W R/W R/W R/W 00000000B Initial value 00000000B R/W R/W : Readable/writable R : Read only W : Write only : Undefined bit X : Undefined CM44-10148-4E FUJITSU MICROELECTRONICS LIMITED 411 CHAPTER 17 8/10-BIT A/D CONVERTER 17.3 17.3.1 MB90950 Series A/D Control Status Register 1 (ADCS1) The A/D control status register 1 (ADCS1) provides the following settings: • Activating A/D conversion function by software • Selecting activation trigger for A/D conversion • Enabling or disabling interrupt request by storing A/D conversion result in the A/D data register • Checking and clearing interrupt request flag by storing A/D conversion result in the A/D data register • Pausing A/D conversion operation and checking the status during conversion ■ A/D Control Status Register 1 (ADCS1) Figure 17.3-2 A/D Control Status Register 1 (ADCS1) bit 15 Address 14 13 12 11 10 9 000069 H BUSY INT INTE PAUS STS1 STS0 STRT R/W R/W R/W R/W R/W R/W W 8 Initial value - 00000001B bit8 - Undefined bit Read value is always "1" bit9 STRT A/D conversion software activation bit 0 Does not activate A/D conversion function 1 Activates A/D conversion function bit11 bit10 A/D conversion activation trigger selection bits STS1 STS0 0 0 Activation by software 0 1 Activation by software or external pin trigger 1 0 Activation by software or 16-bit reload timer 1 1 Activation by software, external pin trigger or 16-bit reload timer bit12 Pause flag bit PAUS (Enabled only when EI2OS or DMA is used) Read 0 1 Write Conversion is not paused Clears to "0" Conversion is paused Setting is prohibited bit13 Interrupt request enable bit INTE Disables interrupt request 0 Enables interrupt request 1 bit14 INT 0 1 Interrupt request flag bit Read A/D conversion uncompleted Write Clears to "0" A/D conversion completed No effect bit15 BUSY R/W : Readable/writable W : Write only : Undefined bit : Initial value 412 A/D conversion operating flag bit 0 Read A/D conversion completed (non-activated state) Write Terminates A/D conversion function forcibly 1 A/D conversion in progress No effect FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E MB90950 Series CHAPTER 17 8/10-BIT A/D CONVERTER 17.3 Table 17.3-2 Function of A/D Control Status Register 1 (ADCS1) (1 / 3) bit15 bit14 bit13 Bit name Function BUSY: A/D conversion operating flag bit This bit forcibly terminates the 8/10-bit A/D converter. When this bit is read, it indicates whether the 8/10-bit A/D converter is operating or stopped. When set to "0": 8/10-bit converter is forcibly terminated When set to "1": No effect When reading : "1" is read when the 8/10-bit A/D converter is operating and "0" is read when the converter is stopped "1" is read at "stop state" in stop conversion mode. Notes: • "1" is read when this bit is read by a RMW instruction. • In single conversion mode, this bit is cleared when A/D conversion is completed. • In continuous conversion mode and stop conversion mode, this bit will not be cleared until "0" is written to stop. • When the forced stop (BUSY= 0) and activation (software(STRT=1)/external trigger/timer) of the A/D converter occur at the same time, the forced stop is preferred. INT: Interrupt request flag bit This bit indicates that an interrupt request is generated. • The INT bit is set to "1" when an A/D conversion is completed and its result is stored in the A/D data register (ADCR). • When the interrupt request flag bit is set (INT=1) if interrupt request is enabled (INTE=1), an interrupt request is generated. • This bit is cleared when "0" is written to it. In addition, it will be cleared automatically when a transfer of A/D conversion result data by EI2OS/μDMAC is completed. • If setting "1" to this bit and writing "0" to it occur simultaneously, writing "0" has priority. When set to "0": Clears this bit When set to "1": No effect Note: "1" is read when this bit is read by a RMW instruction. INTE: Interrupt request enable bit This bit enables or disables interrupt request output. When the interrupt request flag bit is set (INT=1) if interrupt request is enabled (INTE=1), an interrupt request is generated. Note: Be sure to set this bit to "1" if transferring A/D conversion result by EI2OS/μDMAC. CM44-10148-4E FUJITSU MICROELECTRONICS LIMITED 413 CHAPTER 17 8/10-BIT A/D CONVERTER 17.3 MB90950 Series Table 17.3-2 Function of A/D Control Status Register 1 (ADCS1) (2 / 3) Bit name bit12 bit11, bit10 414 Function PAUS: Pause flag bit PAUS bit indicates that the A/D conversion data protection function has been worked. PAUS bit is valid only if interrupt request output is set to enable (ADCS:INTE=1). When A/D conversion data protection function worked: Sets this bit to "1" When written, this bit is set by "1" and it is cleared by "0". • When A/D conversion is performed with interrupt request output enabled (ADCS:INTE=1), an interrupt request is generated at the same time as the interrupt request flag bit (ADCS:INT) is set after the A/D conversion ends once. If the next A/D conversion ends without clearing the interrupt request flag bit (ADCS:INT), the A/D conversion operation will be paused to prevent the previous data from being overwritten and destroyed (A/D conversion data protection function). When an A/D conversion operation is paused, PAUS bit is set to "1". • When the interrupt request flag bit (ADCS:INT) is cleared, the 8/10-bit A/D converter cancels the pause state and restarts the A/D conversion operation. • The interrupt request flag bit (ADCS:INT) is cleared by writing "0" to it. In addition, if an A/D conversion result is transferred from the A/D data register using EI2OS/μDMAC, the interrupt request flag bit (ADCS:INT) is cleared by EI2OS/μDMAC once the transfer of the A/D conversion result is completed. Notes: • For the A/D conversion data protection function, see Section "17.5.5 A/D Conversion Data Protection Function". • PAUS bit is not cleared automatically even when the pause state is canceled. Write "0" to clear PAUS bit. STS1, STS0: A/D conversion activation trigger selection bits These bits select the trigger (activation trigger) to activate the 8/10-bit A/D converter. • 00B: Software activation • 01B: External pin trigger/software activation • 10B: 16-bit reload timer 1/software activation • 11B: External pin trigger/16-bit reload timer 1/software activation Notes: • When external pin trigger is selected (01B, 11B), A/D conversion starts when an falling edge is detected at ADTG pin. • When 16-bit reload timer is selected (10B, 11B), A/D conversion starts when the output of the 16-bit reload timer 1 becomes "1". Notes: • When multiple activation triggers are set (settings other than STS1, STS0=00B), 8/10-bit A/D converter will be activated by the first-generated activation trigger. • When changing the activation trigger setting, set while the operation of peripheral functions which may generate an activation trigger is stopped (in trigger inactive state). FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 17 8/10-BIT A/D CONVERTER 17.3 MB90950 Series Table 17.3-2 Function of A/D Control Status Register 1 (ADCS1) (3 / 3) Bit name bit9 STRT: A/D conversion software activation bit bit8 Undefined bit CM44-10148-4E Function This bit activates the 8/10-bit A/D converter by software. When set to "1" : Activates 8/10-bit A/D converter. • Reactivates by the STRT bit only in the single conversion mode 1 (MD1/MD0=00B). When set to "0" : Invalid. No change. Notes: • "0" is always read. (For MB90V950, "0" is read in the read-modify-write (RMW) instruction and "1" is read in the read instruction except the read-modify-write (RMW) instruction.) • When the forced stop (BUSY=0) and software activation (STRT=1) of the A/D converter are written simultaneously, the forced stop is preferred. • Read : Always "1" is read • Write : No effect FUJITSU MICROELECTRONICS LIMITED 415 CHAPTER 17 8/10-BIT A/D CONVERTER 17.3 17.3.2 MB90950 Series A/D Control Status Register 0 (ADCS0) The A/D control status register 0 (ADCS0) provides the following settings: • Selecting A/D conversion mode • Selecting A/D conversion start channel and end channel ■ A/D Control Status Register 0 (ADCS0) Figure 17.3-3 A/D Control Status Register 0 (ADCS0) Address bit 7 6 5 4 3 2 1 0 000068H MD1 MD0 S10 - - - - Reserved R/W R/W R/W - - - - R/W Initial value 00011110B bit0 Reserved 0 bit5 S10 0 1 R/W : Readable/writable - : Undefined bit : Initial value 416 Reserved bit Always write "0" to this bit Resolution selection bit Set A/D conversion resolution to 10 bits Set A/D conversion resolution to 8 bits bit7 bit6 MD1 MD0 0 0 1 0 0 1 1 1 A/D conversion mode selection bits Single conversion mode 1 Single conversion mode 2 Continuous conversion mode Stop conversion mode FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 17 8/10-BIT A/D CONVERTER 17.3 MB90950 Series Table 17.3-3 Function of A/D Control Status Register 0 (ADCS0) Bit name Function MD1, MD0: A/D conversion mode selection bits These bits set the A/D conversion mode. For details on how to use each mode, see Section "17.5 Operating Explanation of 8/ 10-bit A/D Converter". Single conversion mode 1 and single conversion mode 2: • A/D conversion is continuously performed through analog inputs from the start channel (ADSR: ANS4 to ANS0) to the end channel (ADSR:ANE4 to ANE0). • A/D conversion operation stops when the A/D conversion of the end channel is completed. • See Section "17.5 Operating Explanation of 8/10-bit A/D Converter" on the difference between single conversion modes 1 and 2. • In single conversion mode 1, reactivation during the A/D conversion is allowed. However, reactivation is ignored when A/D conversion data protection function is activated and A/D is in the pause state. Continuous conversion mode: • A/D conversion for analog inputs from the start channel (ADSR: ANS4 to ANS0) to the end channel (ADSR: ANE4 to ANE0) is performed continuously. • After completing the A/D conversion of the end channel, it returns to the analog input of the start channel and continues the A/D conversion. Stop conversion mode: • A/D conversion starts from the start channel (ADSR: ANS4 to ANS0). A/D conversion operation stops when the A/D conversion for one channel is completed. When an activation trigger is input while A/D conversion operation pauses, the A/D conversion for the next channel is performed. • A/D conversion operation pauses at the completion of A/D conversion for the end channel. When an activation trigger is input while A/D conversion operation pauses, the A/D conversion is continued by returning to the analog input for the start channel. Note: If changing the conversion mode, perform in the stop state before A/D conversion is started. In single conversion mode 1, when the termination of A/D conversion and reactivation of A/D conversion occur simultaneously, the operation during A/D conversion is stopped and a reactivation is generated. bit5 S10: Resolution selection bit This bit sets the A/D conversion resolution. When set to "0": Sets the A/D conversion resolution to 10 bits of the A/D conversion data bits D9 to D0. When set to "1": Sets the A/D conversion resolution to 8 bits of the A/D conversion data bits D7 to D0. Note: When changing S10 bit, perform in the stop state before A/D conversion is started. If S10 bit is changed after A/D conversion is started, the conversion result stored in the A/D conversion data bits (D9 to D0) will become invalid. bit4 to bit1 Undefined bits These bits are read only. Initial value is "1". bit0 Reserved bit Always write "0" to this bit. bit7, bit6 CM44-10148-4E FUJITSU MICROELECTRONICS LIMITED 417 CHAPTER 17 8/10-BIT A/D CONVERTER 17.3 17.3.3 MB90950 Series A/D Data Registers 0/1 (ADCR0/ADCR1) The A/D data registers (ADCR0/ADCR1) are used to store digital values generated as a result of a conversion. ADCR0 stores the lower 8 bits and ADCR1 stores the highest 2 bits of a conversion result. These registers are rewritten after each conversion is completed, and normally the last conversion value is stored in them. ■ A/D Data Registers (ADCR0/ADCR1) Figure 17.3-4 A/D Data Registers (ADCR0/ADCR1) A/D data register 1 Address bit 15 ADCR1 00006BH A/D data register 0 Address ADCR0 00006AH 14 13 12 11 10 9 8 Initial value - - - - - D9 D8 11111100B R R 6 5 4 3 2 1 0 Initial value D7 D6 D5 D4 D3 D2 D1 D0 00000000B R R R R R R R R bit 7 R : Read only - : Undefined bit Table 17.3-4 Function of A/D Data Registers (ADCR0/ADCR1) Bit name bit15 to bit10 bit9 to bit0 418 Function Undefined bits When reading, always "1" is read. D9 to D0: A/D conversion data bits These bits store the result of an A/D conversion. When resolution is set to 10 bits (S10=0): Stores conversion data in 10 bits from D9 to D0. When resolution is set to 8 bits (S10=1): Stores conversion data in 8 bits from D7 to D0. At this time, the read values of D9 to D8 become "1" Notes: • Writing to these registers is prohibited. • Use a word instruction (MOVW) to read the conversion result stored in the A/D conversion data bits (D9 to D0). FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 17 8/10-BIT A/D CONVERTER 17.3 MB90950 Series 17.3.4 A/D Setting Register (ADSR0/ADSR1) The A/D setting register (ADSR0/ADSR1) provides the following settings: • Setting A/D conversion times (sampling time, compare time) • Setting sampling channels (start channel, end channel) • Displaying the current sampling channel ■ A/D Setting Register (ADSR0/ADSR1) Figure 17.3-5 A/D Setting Register (ADSR0/ADSR1) Address bit 15 00006C H 14 13 12 11 10 9 7 8 6 5 4 3 2 1 0 ST2 ST1 ST0 CT2 CT1 CT0 ANS4 ANS3 ANS2 ANS1 ANS0 ANE4 ANE3 ANE2 ANE1 ANE0 Initial value 0000000000000000 B R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W bit4 to bit0 ANE4 to ANE0 A/D conversion end channel selection bits 11111B to 00000B (Initial value:00000B) Pin AN31(*1) to Pin AN0 bit9 to bit5 A/D conversion start channel selection bits ANS4 to ANS0 Write (inactivated state) 11111B to 00000B Pins AN31(*) (Initial value:00000B) to AN0 Read during conversion Read during pause in stop conversion mode Channel Channel number number during converted immediately conversion before the event bit12 bit11 bit10 CT2 CT1 CT0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Compare time selection bits 22/φ 33/φ 44/φ 66/φ 88/φ 132/φ 176/φ 264/φ φ:Internal operating frequency 32MHz 0.69μs*2 24MHz 0.92μs*2 16MHz 1.38μs*2 1.03μs*2 1.38μs*2 2.06μs*2 2.75μs 4.13μs 1.38μs*2 1.83μs*2 2.75μs 3.67μs 5.50μs 2.06μs*2 2.75μs 4.13μs 5.50μs 8.25μs 5.50μs 7.33μs 11.0μs 8.25μs 11.0μs 16.5μs bit15 bit14 bit13 R/W : Readable/writable φ : Mschine clock : Initial value ST2 ST1 ST0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Sampling time selection bits 4/φ 6/φ 8/φ 12/φ 24/φ 36/φ 48/φ 128/φ φ:Internal operating frequency 32MHz 24MHz 16MHz 0.13μs*2 0.17μs*2 0.25μs*2 0.19μs*2 0.25μs*2 0.38μs*2 0.75μs*2 1.13μs*2 0.25μs*2 0.33μs*2 0.50μs*2 1.00μs*2 1.50μs 0.38μs*2 0.50μs*2 0.75μs*2 1.50μs 2.25μs 1.50μs 2.00μs 3.00μs 4.00μs 5.33μs 8.00μs *1: Pin AN23 to Pin AN0 can be set. Pins AN24 or higher do not exist. *2: When AVcc is lower than 4.5V, do not set. Conversion accuracy cannot be assured. CM44-10148-4E FUJITSU MICROELECTRONICS LIMITED 419 CHAPTER 17 8/10-BIT A/D CONVERTER 17.3 MB90950 Series Table 17.3-5 Function of A/D Setting Register (ADSR0/ADSR1) (1 / 2) Bit name Function bit15 to bit13 ST2 to ST0: Sampling time selection bits These bits set the A/D conversion sampling time. • These bits set the time from starting A/D conversion to sampling and holding the input analog voltage via sampling & hold circuit. • For the settings of these bits, see Table 17.3-6. bit12 to bit10 CT2 to CT0: Compare time selection bits These bits set the A/D conversion compare time. • These bits set the time from A/D converting the analog input to store it in data bits (D9 to D0). • For the settings of these bits, see Table 17.3-7. ANS4 to ANS0: A/D conversion start channel selection bits These bits set the channel at which an A/D conversion starts. If reading these bits, you can verify the currently converted channel number if in the process of A/D conversion, and the last A/D converted channel number if the A/D conversion is completed or stopped. In addition, even if a value is set to these bits, the previous A/D converted channel number instead of the set value will be read until an A/D conversion starts. These bits are initialized to "00000B " at reset. Start channel < End channel: An A/D conversion starts at the channel set by A/D conversion start channel selection bits (ANS4 to ANS0) and ends at the channel set by A/D conversion end channel selection bits (ANE4 to ANE0). Start channel = End channel: A/D conversion is performed only for one channel set by A/D conversion start (= end) channel selection bits (ANS4 to ANS0 = ANE4 to ANE0). Start channel > End channel: Do not set this setting. Continuous conversion mode, stop conversion mode: When an A/D conversion ends at the channel set by the A/D conversion end channel selection bits (ANE4 to ANE0), it returns to the channel set by the A/D conversion start channel selection bits (ANS4 to ANS0). When reading (in a mode except stop conversion mode): The channel number (31 to 0) under A/D conversion is read. When reading (in stop conversion mode): When reading during a stop, the channel number A/D-converted immediately before the stop is read. Notes: • Do not set the A/D conversion start channel bits (ANS4 to ANS0) during A/D conversion. • When writing to this bit, use word access. If byte write or bit manipulation is performed, an A/D conversion may start from an unexpected channel. • After setting the start channel to A/D conversion start channel selection bits (ANS4 to ANS0), do not set A/D conversion mode selection bits (MD1, MD0) and A/D conversion end channel selection bits (ANE4 to ANE0) by readmodify-write (RMW) instructions. As to ANS3 to ANS0 bits, the previous conversion channel is read until A/D conversion operation starts. When MD1 and MD0 bits and ANE4 to ANE0 bits are set by read-modify-write (RMW) instructions after setting the start channel to ANS4 to ANS0 bits, the values of ANE4 to ANE0 bits may be rewritten. bit9 to bit5 420 FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E MB90950 Series CHAPTER 17 8/10-BIT A/D CONVERTER 17.3 Table 17.3-5 Function of A/D Setting Register (ADSR0/ADSR1) (2 / 2) Bit name bit4 to bit0 ANE4 to ANE0: A/D conversion end channel selection bits CM44-10148-4E Function These bits set the channel at which an A/D conversion ends. Start channel < End channel: An A/D conversion starts at the channel set by A/D conversion start channel selection bits (ANS4 to ANS0) and ends at the channel set by A/D conversion end channel selection bits (ANE4 to ANE0). Start channel = End channel: A/D conversion is performed only for one channel set by A/D conversion start (= end) channel selection bits (ANS4 to ANS0 = ANE4 to ANE0). Start channel > End channel: Do not use this setting. Continuous conversion mode, stop conversion mode: When an A/D conversion ends at the channel set by the A/D conversion end channel selection bits (ANE4 to ANE0), it returns to the channel set by the A/D conversion start channel selection bits (ANS4 to ANS0). Notes: • Do not set the A/D conversion end channel selection bits (ANE4 to ANE0) during A/D conversion. • After the A/D conversion start channel selection bits (ANS4, ANS3,ANS2, ANS1, ANS0) are set, do not set the sampling time selection bits (ST2, ST1, ST0), compare time selection bits (CT2, CT1, CT0) and A/D conversion end channel selection bits (ANE4, ANE3, ANE2, ANE1, ANE0) using a readmodify-write instruction. Because the previous conversion channel is read from ANS4, ANS3, ANS2, ANS1, ANS0 bits until a new A/D conversion operation starts, the values of ANS4, ANS3, ANS2, ANS1, ANS0 bits may be rewritten if ST2, ST1, ST0 bits, CT2, CT1, CT0 bits and ANE4, ANE3, ANE2, ANE1, ANE0 bits are set using a read-modify instruction after setting ANS4, ANS3, ANS2, ANS1, ANS0 bits. FUJITSU MICROELECTRONICS LIMITED 421 CHAPTER 17 8/10-BIT A/D CONVERTER 17.3 MB90950 Series ■ Setting for Sampling Time (ST2 to ST0 Bits) Table 17.3-6 Relationship between ST2 to ST0 Bits and Sampling Time Setting Example (φ:Internal operating frequency) ST2 ST1 ST0 Sampling time setting 0 0 0 0 0 0 φ= 32MHz φ= 24MHz φ=16MHz 4 machine cycles 0.13μs 0.17μs 0.25μs 1 6 machine cycles 0.19μs 0.25μs 0.38μs 1 0 8 machine cycles 0.25μs 0.33μs 0.50μs 0 1 1 12 machine cycles 0.38μs 0.50μs 0.75μs 1 0 0 24 machine cycles 0.75μs 1.00μs 1.50μs 1 0 1 36 machine cycles 1.13μs 1.50μs 2.25μs 1 1 0 48 machine cycles 1.50μs 2.00μs 3.00μs 1 1 1 128 machine cycles 4.00μs 5.33μs 8.00μs The sampling time must be set based on the drive impedance Rext connected to analog input. Conversion accuracy is not assured if the following conditions are not met: See the data sheet for parameters. • Rext ≤ Rextmax: Set the sampling time to STmin or higher. • Rext > Rextmax: Set the sampling time to ST shown in the following expression, or higher. ST = (Rin+Rext) × Cin × 7 ■ Setting for Compare Time (CT2 to CT0 Bits) Table 17.3-7 Relationship between CT2 to CT0 Bits and Compare Time Setting Example (φ:Internal operating frequency) CT2 CT1 CT0 Compare time setting 0 0 0 0 0 0 φ=32MHz φ=24MHz φ=16MHz 22 machine cycles 0.69μs 0.92μs 1.38μs 1 33 machine cycles 1.03μs 1.38μs 2.06μs 1 0 44 machine cycles 1.38μs 1.83μs 2.75μs 0 1 1 66 machine cycles 2.06μs 2.75μs 4.13μs 1 0 0 88 machine cycles 2.75μs 3.67μs 5.50μs 1 0 1 132 machine cycles 4.13μs 5.50μs 8.25μs 1 1 0 176 machine cycles 5.50μs 7.33μs 11.0μs 1 1 1 264 machine cycles 8.25μs 11.0μs 16.5μs The compare time must be set in accordance with the analog supply voltage AVCC. See the data sheet for details. 422 FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 17 8/10-BIT A/D CONVERTER 17.3 MB90950 Series 17.3.5 Analog Input Enable Register (ADER5 to ADER7) This register enables or disables analog input pins used for the 8/10-bit A/D converter. ■ Analog Input Enable Register (ADER5 to ADER7) Figure 17.3-6 Analog Input Enable Register (ADER5 to ADER7) bit 15 Address 14 13 12 11 10 9 8 Initial value ADER5: 00000BH ADE15 ADE14 ADE13 ADE12 ADE11 ADE10 ADE9 ADE8 11111111B R/W R/W R/W R/W R/W R/W R/W R/W bit15 to bit8 ADE15 to ADE8 Analog input enable bits 15 to 8 (AN15 to AN8) Disables analog input 0 1 Enables analog input bit 7 Address ADER6: 00000CH 6 5 4 3 2 1 0 Initial value ADE7 ADE6 ADE5 ADE4 ADE3 ADE2 ADE1 ADE0 11111111B R/W R/W R/W R/W R/W R/W R/W R/W bit7 to bit0 Analog input enable bits 7 to 0 (AN7 to AN0) ADE7 to ADE0 Disables analog input 0 1 Enables analog input Address bit 15 14 13 12 11 10 9 8 Initial value ADER7: 00000DH ADE23 ADE22 ADE21 ADE20 ADE19 ADE18 ADE17 ADE16 11111111B R/W R/W R/W R/W R/W R/W R/W R/W R/W : Readable/writable : Initial value bit15 to bit8 ADE23 to ADE16 Analog input enable bits 23 to 6 (AN23 to AN16) Disables analog input 0 1 Enables analog input Table 17.3-8 Function of Port 5 Analog Input Enable Register (ADER5) Bit name bit15 to bit8 ADE15 to ADE8: Analog input enable bit15 to bit8 Function These bits enable or disable analog input of the A/D conversion analog input pins AN15 to AN8 placed on port 5. When set to "0": Disables analog input When set to "1": Enables analog input Table 17.3-9 Function of Port 6 Analog Input Enable Register (ADER6) Bit name bit7 to bit0 ADE7 to ADE0: Analog input enable bit7 to bit0 CM44-10148-4E Function These bits enable or disable analog input of the A/D conversion analog input pins AN7 to AN0 placed on port 6. When set to "0": Disables analog input When set to "1": Enables analog input FUJITSU MICROELECTRONICS LIMITED 423 CHAPTER 17 8/10-BIT A/D CONVERTER 17.3 MB90950 Series Table 17.3-10 Function of Port 7 Analog Input Enable Register (ADER7) Bit name bit15 to bit8 ADE23 to ADE16: Analog input enable bit23 to bit16 Function These bits enable or disable analog input of the A/D conversion analog input pins AN23 to AN16 placed on port 7. When set to "0": Disables analog input When set to "1": Enables analog input Notes: • To use as an analog input pin, set it to analog input by writing "1" to the bit in the analog input enable register (ADER5 to ADER7) corresponding to the pin to be used. • Setting an analog input pin to ADEx=0 is prohibited. Always set to ADEx=1. • Each analog input pin serves as a general-purpose I/O port and an input/output of peripheral functions. The pin set to ADEx=1 forcibly becomes an analog input pin regardless of the I/O settings in port direction register (DDR5 to DDR7) and in each peripheral function, and cannot be used for other purposes. 424 FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 17 8/10-BIT A/D CONVERTER 17.4 MB90950 Series 17.4 Interrupt of 8/10-bit A/D Converter The 8/10-bit A/D converter can generate an interrupt request when the conversion result is set in the A/D data register (ADCR) after an A/D conversion is completed. The μDMAC and the extended intelligent I/O service (EI2OS) can be used. ■ Interrupt of A/D Converter When the A/D conversion of an analog input voltage is completed and the A/D conversion result is stored in the A/D data register (ADCR), the interrupt request flag bit in the A/D control status register (ADCS: INT) is set to "1". When the interrupt request flag bit is set (ADCS: INT=1) with interrupt request output enabled (ADCS: INTE=1), an interrupt request is generated. ■ Interrupt of 8/10-bit A/D Converter, and μDMAC and EI2OS Reference: See "CHAPTER 3 INTERRUPTS" for details of the interrupt number, interrupt control register, interrupt vector address, and DMA channel. ■ μDMAC and EI2OS of 8/10-bit A/D Converter In the 8/10-bit A/D converter, the μDMAC or EI2OS function can be used to transfer the A/D conversion result from the A/D data register (ADCR) to memory. For information on how to use the μDMAC/ EI2OS functions, see Section "17.5.4 Conversion Operation with μDMAC or EI2OS Function" and Section "17.5.5 A/D Conversion Data Protection Function". CM44-10148-4E FUJITSU MICROELECTRONICS LIMITED 425 CHAPTER 17 8/10-BIT A/D CONVERTER 17.5 17.5 MB90950 Series Operating Explanation of 8/10-bit A/D Converter For A/D conversion operation of the 8/10-bit A/D converter, the following A/D conversion modes are available. Each mode is set based on the setting of the A/D conversion mode selection bits in the A/D control status register (ADCS: MD1, MD0). • Single conversion mode • Continuous conversion mode • Stop conversion mode ■ Single Conversion Mode (ADCS: MD1, MD0=00B or 01B) • When an activation trigger is input, the analog inputs from the start channel (ADSR: ANS4 to ANS0) to the end channel (ADSR: ANE4 to ANE0) are A/D-converted continuously. • A/D conversion operation stops at the time of completing of the A/D conversion for the end channel. • When setting to single conversion mode 1 (ADCS:MD1, MD0=00B), reactivation during A/D conversion is allowed. However, reactivation is ignored when A/D conversion data protection function is triggered and A/D is in the pause state. • When setting to single conversion mode 2 (ADCS:MD1, MD0=01B), reactivation during A/D conversion is not allowed. Notes: • In single conversion mode 1 (ADCS:MD1, MD0=00B), do not input an activation trigger during A/D conversion or a pause* as this may cause a restart of the 8/10-bit A/D converter. • In single conversion mode 2 (ADCS:MD1, MD0=01B), a restart of the 8/10-bit A/D converter will not occur even if an activation trigger is input during A/D conversion or a pause*. • To restart in either single conversion mode 1 or 2, follow the order indicated in Section "17.5.1 Single Conversion Mode". *: The pause state is in a state which conversion is suspended due to the A/D conversion protection function. For details, see Section "17.5.5 A/D Conversion Data Protection Function". ■ Continuous Conversion Mode (ADCS: MD1, MD0=10B) • When an activation trigger is input, the analog inputs from the start channel (ADSR: ANS4 to ANS0) to the end channel (ADSR: ANE4 to ANE0) are A/D-converted continuously. • When A/D conversion for the end channel is completed, it is continued by returning to the analog input of the start channel. ■ Stop Conversion Mode (ADCS: MD1, MD0=11B) • When a start trigger is input, A/D conversion starts for the start channel (ADSR: ANS4 to ANS0). The A/D conversion operation stops at the completion of A/D conversion for one channel. This state is called the "stop state". When a start trigger is input while the A/D conversion operation stops, A/D conversion is performed for the next channel. • The A/D conversion operation stops at the completion of A/D conversion for the end channel. When a start trigger is input while the A/D conversion operation stops, A/D conversion is continued by returning to the analog input of the start channel. 426 FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 17 8/10-BIT A/D CONVERTER 17.5 MB90950 Series 17.5.1 Single Conversion Mode In single conversion mode, A/D conversion is performed sequentially from the start channel to the end channel. The A/D conversion operation stops at the completion of the A/D conversion for the end channel. ■ Setting for Single Conversion Mode To operate the 8/10-bit A/D converter in single conversion mode, the settings shown in Figure 17.5-1 are required. Figure 17.5-1 Setting for Single Conversion Mode bit15 14 13 12 11 10 ADCS 9 bit8 bit7 6 5 4 3 2 1 bit0 BUSY INT INTE PAUS STS1 STS0 STRT − MD1 MD0 S10 − − − − 0 ADCR − − − − − − Reserved 0 D9 to D0 (Holds conversion results) ADSR ST2 ST1 ST0 CT2 CT1 CT0 ANS4 ANS3 ANS2 ANS1 ANS0 ANE4 ANE3 ANE2 ANE1 ANE0 ADER5 ADE15 ADE14 ADE13 ADE12 ADE11 ADE10 ADE9 ADE8 ADER7/ ADER6 ADE23 ADE22 ADE21 ADE20 ADE19 ADE18 ADE17 ADE16 ADE7 ADE6 ADE5 ADE4 ADE3 ADE2 ADE1 ADE0 − : Undefined : Used bit : Set the bit corresponding to the pin to be used as an analog input pin to "1" 0 : Set to "0" CM44-10148-4E FUJITSU MICROELECTRONICS LIMITED 427 CHAPTER 17 8/10-BIT A/D CONVERTER 17.5 MB90950 Series ■ Single Conversion Mode Operation and How to Use it • When a start trigger is input, A/D conversion starts from the channel set by the A/D conversion start channel selection bits (ANS4 to ANS0) and is performed continuously up to the channel set by the A/D conversion end channel selection bits (ANE4 to ANE0). • The A/D conversion operation stops at the completion of the A/D conversion for the channel set by the A/D conversion end channel selection bits (ANE4 to ANE0). • To terminate an A/D conversion operation forcibly, write "0" to the A/D conversion operating flag bit in the A/D control status register (ADCS:BUSY). [If start channel and end channel are the same] If the start and end channels are set to the same channel number (ADSRS: ANS4 to ANS0=ADSR: ANE4 to ANE0), A/D conversion for only one channel set as the start channel (= end channel) is performed only once and terminated. [Conversion order in single conversion mode] Table 17.5-1 shows an example of the conversion order in single conversion mode. Table 17.5-1 Conversion Order in Single Conversion Mode Start channel End channel Conversion order in single conversion mode AN0 pin (ADSR: ANS=00000B) AN3 pin (ADSR: ANE=00011B) AN0 → AN1 → AN2 → AN3 → End AN3 pin (ADSR: ANS=00011B) AN3 pin (ADSR: ANE=00011B) AN3 → End [Restart] To restart A/D conversion during A/D conversion execution or a pause state, terminate the conversion forcibly once and then restart it. Follow the procedure below: 1) Clear the A/D conversion operating flag bit (ADCS:BUSY) 2) Clear the interrupt request flag bit (ADCS:INT) 3) Set the A/D conversion software activation bit (ADCS:STRT) 428 FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 17 8/10-BIT A/D CONVERTER 17.5 MB90950 Series 17.5.2 Continuous Conversion Mode In continuous conversion mode, A/D conversion is performed sequentially from the start channel to the end channel. When the A/D conversion for the end channel is completed, the A/D conversion operation is continued by returning to the start channel. ■ Setting for Continuous Conversion Mode To operate the 8/10-bit A/D converter in continuous conversion mode, the settings shown in Figure 17.5-2 are required. Figure 17.5-2 Setting for Continuous Conversion Mode bit15 14 13 12 11 10 ADCS 9 bit8 bit7 6 4 3 2 1 bit0 BUSY INT INTE PAUS STS1 STS0 STRT − MD1 MD0 S10 − − − − 1 ADCR − − − − − − 5 0 Reserved 0 D9 to D0 (Holds conversion results) ADSR ST2 ST1 ST0 CT2 CT1 CT0 ANS4 ANS3 ANS2 ANS1 ANS0 ANE4 ANE3 ANE2 ANE1 ANE0 ADER5 ADE15 ADE14 ADE13 ADE12 ADE11 ADE10 ADE9 ADE8 ADER7/ ADER6 ADE23 ADE22 ADE21 ADE20 ADE19 ADE18 ADE17 ADE16 ADE7 ADE6 ADE5 ADE4 ADE3 ADE2 ADE1 ADE0 − : Undefined : Used bit : Set the bit corresponding to the pin to be used as an analog input pin to "1" 1 : Set to "1" 0 : Set to "0" ■ Continuous Conversion Mode Operation and How to Use It • When a start trigger is input, an A/D conversion starts from the channel set by the A/D conversion start channel selection bits (ANS4 to ANS0) and is performed continuously up to the channel set by the A/D conversion end channel selection bits (ANE4 to ANE0). • When the A/D conversion for the channel set by the A/D conversion end channel selection bits (ANE4 to ANE0) is completed, the A/D conversion is continued by returning to the channel set by the A/D conversion start channel selection bits (ANS4 to ANS0). • To terminate an A/D conversion forcibly, write "0" to the A/D conversion operating flag bit in the A/D control status register (ADCS:BUSY). [If start channel and end channel are the same] If the start and end channels are set to the same channel (ADSR: ANS4 to ANS0=ADSR: ANE4 to ANE0), the A/D is repeatedly converted for one channel set as the start channel (= end channel). CM44-10148-4E FUJITSU MICROELECTRONICS LIMITED 429 CHAPTER 17 8/10-BIT A/D CONVERTER 17.5 MB90950 Series [Conversion order in continuous conversion mode] Table 17.5-2 shows an example of the conversion order in continuous conversion mode. Table 17.5-2 Conversion Order in Continuous Conversion Mode Start channel End channel Conversion order in continuous conversion mode AN0 pin (ADSR: ANS=00000B) AN3 pin (ADSR: ANE=00011B) AN0 → AN1 → AN2 → AN3 → AN0→ Repeat AN3 pin (ADSR: ANS=00011B) AN3 pin (ADSR: ANE=00011B) AN3 → AN3 → Repeat [Restart] To restart A/D conversion during A/D conversion execution or a pause state, terminate the conversion forcibly once and then restart it. Follow the procedure below: 1) Clear the A/D conversion operating flag bit (ADCS:BUSY) 2) Clear the interrupt request flag bit (ADCS:INT) 3) Set the A/D conversion software activation bit (ADCS:STRT) 430 FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 17 8/10-BIT A/D CONVERTER 17.5 MB90950 Series 17.5.3 Stop Conversion Mode In stop conversion mode, A/D conversion is performed by repeatedly starting and stopping for each channel. When a start trigger is input after an A/D conversion operation stops at the completion of the A/D conversion for the end channel, the A/D conversion is continued by returning to the start channel. ■ Setting for Stop Conversion Mode To operate the 8/10-bit A/D converter in stop conversion mode, the settings shown in Figure 17.5-3 are required. Figure 17.5-3 Setting for Stop Conversion Mode bit15 14 13 12 11 10 ADCS 9 bit8 bit7 6 4 3 2 1 bit0 BUSY INT INTE PAUS STS1 STS0 STRT − MD1 MD0 S10 − − − − 1 ADCR − − − − − − 5 1 Reserved 0 D9 to D0 (Holds conversion results) ADSR ST2 ST1 ST0 CT2 CT1 CT0 ANS4 ANS3 ANS2 ANS1 ANS0 ANE4 ANE3 ANE2 ANE1 ANE0 ADER5 ADE15 ADE14 ADE13 ADE12 ADE11 ADE10 ADE9 ADE8 ADER7/ ADER6 ADE23 ADE22 ADE21 ADE20 ADE19 ADE18 ADE17 ADE16 ADE7 ADE6 ADE5 ADE4 ADE3 ADE2 ADE1 ADE0 − : Undefined : Used bit : Set the bit corresponding to the pin to be used as an analog input pin to "1" 1 : Set to "1" 0 : Set to "0" ■ Stop Conversion Mode Operation and How to Use It • When a start trigger is input, an A/D conversion starts at the channel set by the A/D conversion start channel selection bits (ANS4 to ANS0). The A/D conversion operation stops at the completion of the A/D conversion for one channel. When a start trigger is input while the A/D conversion operation stops, A/D conversion for the next channel is performed. • The A/D conversion operation stops at the completion of the A/D conversion for the channel set by the A/D conversion end channel selection bits (ANE4 to ANE0). When a start trigger is input while the A/D conversion operation stops, the A/D conversion is continued by returning to the channel set by the A/D conversion start channel selection bits (ANS4 to ANS0). • In order to terminate an A/D conversion forcibly, write "0" to the A/D conversion operating flag bit in the A/D control status register (ADCS:BUSY). CM44-10148-4E FUJITSU MICROELECTRONICS LIMITED 431 CHAPTER 17 8/10-BIT A/D CONVERTER 17.5 MB90950 Series [If start channel and end channel are the same] If the start and end channels are set to the same channel (ADSR:ANS4 to ANS0=ADSR: ANE4 to ANE0), A/D conversion for one channel set as the start channel (= end channel) and stop are repeated. [Conversion order in stop conversion mode] Table 17.5-3 shows an example of the conversion order in stop conversion mode. Table 17.5-3 Conversion Order in Stop Conversion Mode Start channel End channel Conversion order in stop conversion mode AN0 pin (ADSR: ANS=00000B) AN3 pin (ADSR: ANE=00011B) AN0 → stop/start → AN1 → stop/start → AN2 → stop/start → AN3 → stop/start → AN0 → repeat AN3 pin (ADSR: ANS=00011B) AN3 pin (ADSR: ANE=00011B) AN3 → stop/start → AN3 → stop/start → repeat [Restart] To restart A/D conversion during A/D conversion execution or a pause state, terminate the conversion forcibly once and then restart it. Follow the procedure below: 1) Clear the A/D conversion operating flag bit (ADCS:BUSY) 2) Clear the interrupt request flag bit (ADCS:INT) 3) Set the A/D conversion software activation bit (ADCS:STRT) 432 FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 17 8/10-BIT A/D CONVERTER 17.5 MB90950 Series 17.5.4 Conversion Operation with μDMAC or EI2OS Function The 8/10-bit A/D converter can transfer an A/D conversion result to memory by using the μDMAC or EI2OS function. ■ Conversion Operation with μDMAC/EI2OS Function Figure 17.5-4 shows the conversion operation flow when the μDMAC or EI2OS function is used. Figure 17.5-4 Conversion Operation Flow When μDMAC/EI2OS Function Is Used Activate A/D converter Sample & hold Start A/D conversion End A/D conversion Generate interrupt Activate μDMAC or EI2OS Transfer conversion result Completed a specified number of times? * NO Interrupt clear YES Process interrupt *: The number of times is determined by the DMA or EI2OS setting CM44-10148-4E FUJITSU MICROELECTRONICS LIMITED 433 CHAPTER 17 8/10-BIT A/D CONVERTER 17.5 17.5.5 MB90950 Series A/D Conversion Data Protection Function The data protection function is triggered when A/D conversion is performed while interrupt request output is enabled. ■ Explanation of A/D Conversion Data Protection Function of 8/10-bit A/D Converter The A/D conversion data protection function prevents A/D conversion data from being left behind. The 8/10-bit A/D converter has one A/D data register (ADCR1/ADCR0) to store conversion data and one buffer register to store the next conversion result. Once A/D conversion is completed, the conversion data is first stored in the buffer register, and then stored into the A/D data register. The operation of the A/D converter varies depending on whether the A/D conversion data protection function is switched ON or OFF, as described below. • When the interrupt request enable bit (ADCS:INTE) is set to "0", the data protection function is turned off. In this case, if conversion is performed more than once continuously, the conversion result is stored in the A/D data register after each conversion. (This allows the latest conversion data to be always stored.) • When the interrupt request enable bit (ADCS:INTE) is set to "1", the data protection function is turned on. When conversion is performed more than once continuously in this state and the next conversion is completed before the result of the previous conversion is read from the A/D data register (interrupt request flag bit:ADCS:INT=1; State A), the conversion result is stored in the buffer register and the A/D conversion pauses (State B). If the interrupt request flag bit (ADCS:INT) is cleared to "0" during State B, the data stored in the buffer register is transferred to the A/D data register. (See Figure 17.5-5) Figure 17.5-5 Operation of A/D Conversion Data Protection Function 1 (Normal Operation) State A Activation source A/D State B 2 1 Conversion Stop A/D data register (ADCR1/ADCR0) 434 Undefined State B 3 Conversion Pause Stop Conversion Interrupt request flag bit (INT) Buffer register State A Pause When INT is cleared, A/D result is transferred from buffer register to ADCR1/ADCR0 to set stop state. AD1 Undefined AD2 Undefined AD1 FUJITSU MICROELECTRONICS LIMITED AD3 AD2 CM44-10148-4E CHAPTER 17 8/10-BIT A/D CONVERTER 17.5 MB90950 Series Figure 17.5-6 Operation of A/D Conversion Data Protection Function 2 (In case without clearing INT bit) State A Activation source A/D 2 1 Conversion State B 3 (This activation is ignored) Stop Conversion Pause AD1 Undefined AD2 Interrupt request flag bit (INT) Buffer register A/D data register (ADCR1/ADCR0) Undefined AD1 ■ How to Use A/D Conversion Data Protection Function This item explains how to use the A/D conversion data protection function for when μDMAC/EI2OS is used as well as when it is not used. ● How to use the data protection function when μDMAC/EI2OS is not used • Set the interrupt request flag bit in the A/D control status register (ADCS:INTE) to "1" to start A/D conversion. • After completion of the A/D conversion, the result of the A/D conversion is stored in the buffer register and the succeeding content of the buffer register is transferred to the A/D data register (ADCR1/ ADCR0). At this point, the interrupt request flag bit in the A/D control status register (ADCS:INT) is set to "1". • If the interrupt request flag bit (ADCS:INT), which was set upon the completion of the previous A/D conversion, is still set to "1" upon the completion of the next A/D conversion, the A/D conversion operation pauses in order to prevent overwriting, immediately before the content of the buffer register is transferred to the A/D data register. At this point, the pause flag bit in the A/D control status register (ADCS:PAUS) is set to "1". • Since interrupt request in the A/D control status register is enabled (ADCS: INTE=1), an interrupt request is generated when the interrupt request flag bit is set. When the interrupt request flag bit is cleared after the A/D data register is read in the interrupt routine, the pause state is canceled and the content of the buffer register is transferred to the A/D data register. In case of continuous A/D conversion, the A/D conversion operation resumes. At this point, however, the pause flag bit (ADCS:PAUS) is not cleared automatically. To clear the bit, write "0" to it. Notes: • The A/D conversion data protection function does not operate unless interrupt requests are enabled. Make sure that the interrupt request output enable bit in the A/D control status register (ADCS:INTE) is always set to "1". If interrupt requests are disabled during a pause (ADCS:INTE=0), A/D conversion starts and data in the A/D data register may be rewritten. • To perform continuous conversion, always program it so that the data stored in the A/D data register is read before the interrupt request flag bit (ADCS:INT) is cleared. If the interrupt request flag bit (ADCS:INT) is cleared before the data stored in the A/D data register is read while A/D conversion is paused, the initially stored conversion data is deleted and the next data is read. CM44-10148-4E FUJITSU MICROELECTRONICS LIMITED 435 CHAPTER 17 8/10-BIT A/D CONVERTER 17.5 MB90950 Series ● How to use the data protection function when μDMAC/EI2OS is used • Enable the use of the DMA or EI2OS function and set the interrupt request enable bit in the A/D control status register (ADCS:INT) to "1" to start A/D conversion. • After completion of the A/D conversion, the result of the A/D conversion is stored in the buffer register, and then the content of the buffer register is transferred to the A/D data register (ADCR). At this point, the interrupt request flag bit in the A/D control register (ADCS:INT) is set to "1" and DMA or EI2OS starts. If the next A/D conversion is completed before the result of the A/D conversion is transferred from the A/D data register to the memory, the A/D conversion operation pauses in order to prevent overwriting, immediately before the content of the buffer register is transferred to the A/D data register. At this point, the pause flag bit in the A/D control status register (ADCS:PAUS) is set to "1". • Once the DMA or EI2OS transfer is completed, the interrupt request flag bit (ADCS:INT) is cleared to "0", the pause state is canceled, and the content of the buffer register is transferred to the A/D data register. In case of continuous A/D conversion, the A/D conversion operation resumes. At this point, however, the pause flag bit (ADCS:PAUS) is not cleared automatically. To clear the bit, write "0" to it. Notes: • The A/D conversion data protection function does not operate unless interrupt requests are enabled. Make sure that the interrupt request output enable bit in the A/D control status register (ADCS:INTE) is always set to "1". • If the result of A/D conversion is transferred to the memory by the μDMAC or EI2OS function, do not clear the interrupt request flag bit (ADCS:INT=0), or this may rewrite the data in the A/D data register currently being transferred. • If the result of A/D conversion is transferred to the memory by the μDMAC or EI2OS function, do not disable interrupt requests. If interrupt requests are disabled (ADCS:INTE=0) during a pause, A/D conversion starts and the data in the A/D data register may be rewritten. Figure 17.5-7 shows the flow of the data protection function when μDMAC/EI2OS is used. 436 FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 17 8/10-BIT A/D CONVERTER 17.5 MB90950 Series Figure 17.5-7 Processing Flow of A/D Conversion Data Protection Function when μDMAC/EI2OS is Used Set μDMAC or EI2OS Activate A/D continuous conversion Complete the first conversion Store data in A/D data register Activate μDMAC or EI2OS Complete the second conversion μDMAC/ EI2OS end? NO Pause A/D YES Store data in A/D data register Third conversion Activate μDMAC or EI2OS Continue Complete all conversions μDMAC/ EI2OS end? NO Pause A/D YES Activate μDMAC or EI2OS Interrupt processing Stop A/D conversion Note: The flowchart at stop the A/D converter is omitted. Do not use µDMAC and EI2OS simultaneously. CM44-10148-4E End FUJITSU MICROELECTRONICS LIMITED 437 CHAPTER 17 8/10-BIT A/D CONVERTER 17.6 17.6 MB90950 Series Notes on Using 8/10-bit A/D Converter Note the following points when using the 8/10-bit A/D converter. ■ Notes on Using 8/10-bit A/D Converter ● Analog input pin • The analog input pins serve as general-purpose I/O ports of ports 5 to 7. When using the pin as an analog input pin, switch the pin to analog input pin by setting the analog input enable register (ADER5 to ADER7). • When using the pin as an analog input pin, write "1" to the bit in the analog input enable register (ADER5 to ADER7) corresponding to the pin to be used to set it to analog input enable. • If an intermediate-level signal is input to the pin being set as a general-purpose I/O port, input leakage current will flow in the gate. When using the pin as an analog input pin, be sure to set the pin to analog input enable. ● Order of turning on the 8/10-bit A/D converter power supply and analog input • Be sure to turn on the digital power supply (VCC) before turning on the 8/10-bit A/D converter power supply and analog inputs. • Turn off the digital power supply after turning off the 8/10-bit A/D converter power supply and analog inputs. • Turn on and off AVRH in order not to exceed AVCC. (There is no problem to turn on or off the analog power supply and digital power supply concurrently). ● Supply voltage of 8/10-bit A/D converter • For latch-up prevention, the 8/10-bit A/D converter power supply (AVCC) must not exceed the voltage of the digital power supply (VCC). 438 FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 18 CLOCK MONITOR FUNCTION This chapter explains the functions and operations of the clock monitor. 18.1 Overview of Clock Monitor Function 18.2 Block Diagram of Clock Monitor Function 18.3 Configuration of Clock Monitor Function 18.4 Program Example of Clock Monitor Function CM44-10148-4E FUJITSU MICROELECTRONICS LIMITED 439 CHAPTER 18 CLOCK MONITOR FUNCTION 18.1 18.1 MB90950 Series Overview of Clock Monitor Function The clock monitor function outputs division clock of the machine clock for monitoring from the clock monitor pin (CKOT). ■ Overview of Clock Monitor Function • When the output enable bit of the clock output enable register is set to "1" (CLKR:CKEN=1), the clock is output from the clock monitor pin (CKOT). • The frequency of the clock to be output is set by the output frequency selection bit of the clock output enable register (CLKR: FRQ2 to FRQ0). Table 18.1-1 shows the frequency of the clock to be output using the clock monitor function. Table 18.1-1 Output Frequency for Clock Monitor Function FRQ2 to FRQ0 Bits Clock Output Frequency 000B φ=24MHz φ=16MHz φ=8MHz Cycle Frequency Cycle Frequency Cycle Frequency φ/21 83 ns 12 MHz 125 ns 8 MHz 250 ns 4 MHz 001B φ/22 167 ns 6 MHz 250 ns 4 MHz 500 ns 2 MHz 010B φ/23 333 ns 3 MHz 500 ns 2 MHz 1.0 μs 1 MHz 011B φ/24 667 ns 1.5 MHz 1.0 μs 1 MHz 2.0 μs 500 kHz 100B φ/25 1.3 μs 750 kHz 2.0 μs 500 kHz 4.0 μs 250 kHz 101B φ/26 2.7 μs 375 kHz 4.0 μs 250 kHz 8.0 μs 125 kHz 110B φ/27 5.3 μs 187.5 kHz 8.0 μs 125 kHz 16.0 μs 62.5 kHz 111B φ/28 10.7 μs 93.75 kHz 16.0 μs 62.5 kHz 32.0 μs 31.25 kHz φ : Machine clock frequency 440 FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 18 CLOCK MONITOR FUNCTION 18.2 MB90950 Series 18.2 Block Diagram of Clock Monitor Function The clock monitor function module consists of the following blocks: • Prescaler • Count clock selector • Clock output enable register ■ Block Diagram of Clock Monitor Function Figure 18.2-1 Block Diagram of Clock Monitor Function Internal data bus Prescaler Count clock selector Pin CKOT Output enable Clock output enable register (CLKR) 3 CKEN FRQ2 FRQ1 FRQ0 − : Undefined φ : Machine clock frequency ● Prescaler Divides the machine clock φ and provides it to the count clock selector. ● Count clock selector Selects the clock to be output from 8 types of division clock. ● Clock output enable register Enables the clock output and selects the output frequency. ■ Details of Pin The following shows the detail of the pin of the clock monitor function: CKOT pin: P81/CKOT CM44-10148-4E FUJITSU MICROELECTRONICS LIMITED 441 CHAPTER 18 CLOCK MONITOR FUNCTION 18.3 18.3 MB90950 Series Configuration of Clock Monitor Function This section details the pins and registers of the clock monitor function. ■ Pin of Clock Monitor Function The clock monitor pin (CKOT) serve as general-purpose I/O ports. Table 18.3-1 shows the pin function and the setting to be used in clock monitor function. Table 18.3-1 Pin of Clock Monitor Function Pin Name P81/ TOT0/ INT13R/ CKOT 442 Pin Function General-purpose I/O ports / 16-bit reload timer input 0 / External interrupt 13 / Clock monitor output Required Setting for Use of Clock Monitor Function • • • Reload timer output disabled (TMCSR0: OUTE=0) External interrupt 13 disabled (ENIR1: EN13=0) or use P05 instead of P81 (EISSR: INT13R=0) Clock output enabled (CLKR: CKEN=1) FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 18 CLOCK MONITOR FUNCTION 18.3 MB90950 Series 18.3.1 Clock Output Enable Register (CLKR) Clock output enable register (CLKR) enables the clock output and selects the output frequency. ■ Clock Output Enable Register (CLKR) Figure 18.3-1 Clock Output Enable Register (CLKR) Address 7 6 5 4 00796CH - - - - 3 2 1 0 Initial value CKEN FRQ2 FRQ1 FRQ0 11110000B R/W R/W R/W R/W bit2 bit1 bit0 FRQ2 FRQ1 FRQ0 Output Frequency Select Bits 0 0 0 φ/21 0 0 1 φ/22 0 1 0 φ/23 0 1 1 φ/24 1 0 0 φ/25 1 0 1 φ/26 1 1 0 φ/27 1 1 1 φ/28 bit3 CKEN R/W : Readable/writable - : Undefined Output Enable Bit 0 General-purpose I/O port 1 Clock output : Initial value Table 18.3-2 Functions of Clock Output Enable Register (CLKR) Bit name Function bit7 to bit4 Undefined bits Read : The value is undefined. Write : No effect. bit3 CKEN: Output enable bit Enables the output of clock monitor pin (CKOT). When set to "1": Set to the clock monitor pin. When set to "0": Set to general-purpose I/O port. bit2 to bit0 FRQ0, FRQ1, FRQ2: Output frequency select bits Sets the frequency of the clock to be output. The division rate for the machine clock can be selected and set from 8 types. CM44-10148-4E FUJITSU MICROELECTRONICS LIMITED 443 CHAPTER 18 CLOCK MONITOR FUNCTION 18.4 18.4 MB90950 Series Program Example of Clock Monitor Function This section gives a program example of the clock monitor. ■ Program Example of Clock Monitor ● Processing specification • When the machine clock is φ=24MHz, the clock at the frequency of 750 kHz is output from the CKOT pin. • The bits FRQ2 to FRQ0 are "100B" (clock: φ/25). ● Coding example CLKR EQU 00796CH ;Clock output control register ; ;---------Main program--------------------------------------------CODE CSEG START: ; ;Stack pointer (SP), etc., already ;initialized MOV I:CLKR,#00001100B ;Clock output enabled, φ/25 set ; • Processing by user • CODE ENDS END START ;---------Vector setting------------------------------------------VECT CSEG ABS=0FFH ORG 00FFDCH ;Set reset vector DSL START DB 00H ;Set to single-chip mode 444 FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 19 LIN-UART This chapter explains the functions and operations of LIN-UART. 19.1 Overview of LIN-UART 19.2 Configuration of LIN-UART 19.3 Pins of LIN-UART 19.4 Registers of LIN-UART 19.5 Interrupts of LIN-UART 19.6 Baud Rate of LIN-UART 19.7 Operation of LIN-UART 19.8 Notes on Using LIN-UART CM44-10148-4E FUJITSU MICROELECTRONICS LIMITED 445 CHAPTER 19 LIN-UART 19.1 19.1 MB90950 Series Overview of LIN-UART The LIN (Local Interconnect Network)-UART is a general-purpose serial data communication interface for synchronous or asynchronous (start-stop synchronization) communication with external devices. In addition to a bidirectional communication function (normal mode) and master/slave communication function (multiprocessor mode: supports both master and slave operation), the LIN-UART also supports the special functions used by the LIN bus. ■ Functions of LIN-UART ● Functions of LIN-UART The LIN-UART is a general-purpose serial data communication interface for exchanging serial data with other CPUs and peripheral devices. Table 19.1-1 lists the functions of the LIN-UART. Table 19.1-1 Functions of LIN-UART (1 / 2) Function Data buffer Full-duplex double-buffer Serial input The LIN-UART performs oversampling 5 times using machine clock and determines the received value by majority decision of sampling time (only asynchronous mode). Transfer mode • Clock synchronization (Select start/stop synchronization, or start/stop bit) • Clock asynchronous (Start/stop bits available) Baud rate • Dedicated baud rate generator provided (made of a 15-bit reload counter) • The external clock can be input and also be adjusted by the reload counter. Data length • 7 bits (not in synchronous or LIN mode) • 8 bits Signal type NRZ (Non Return to Zero) Start bit timing Synchronization with the falling edge of the start bit in asynchronous mode. Reception error detection • Framing error • Overrun error • Parity error (Not supported in operating mode 1) Interrupt request • Reception interrupts (reception completed, reception error detected, LIN Synch break detected) • Transmit interrupts (transmit data empty) • Interrupt request to ICU (LIN Synch field detected: LSYN) • Extended intelligent I/O service (EI2OS) and DMA function can be supported for both transmission and reception. Master/slave mode communication function (Multiprocessor mode) Capable of 1 (master) to n (slaves) communication (support both the master and slave system) Synchronous mode Master or slave function 446 FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 19 LIN-UART 19.1 MB90950 Series Table 19.1-1 Functions of LIN-UART (2 / 2) Function Pin access Serial I/O pin state can be read directly. • • • • • LIN bus option Master device operation Slave device operation LIN Synch break detection LIN Synch break generation Detection of LIN Synch field start/stop edges connected to the input capture 0, 1, 4, 5, 6 and 7 Synchronous serial clock Continuous output to the SCK pin is possible for synchronous communication using the start/stop bits. Clock delay option Special synchronous clock mode for delaying the clock (used for SPI) The LIN-UART operates in four different modes. The operating mode is selected by the MD0 and MD1 bits in the LIN-UART serial mode register (SMR). Modes 0 and 2 are used for bidirectional serial communication; mode 1 for master/slave communication; and mode 3 for LIN master/slave communication. Table 19.1-2 LIN-UART Operating Modes Data length Operating mode No parity 0 Normal mode 1 Multiprocessor mode 2 Normal mode 3 LIN mode With parity 7 bits or 8 bits Synchronous method Stop bit length Data bit format Asynchronous 1 bit or 2 bits 7 bits or 8 bits +1* — 8 bits 8 bits — Asynchronous LSB first MSB first Synchronous None, 1 bit, 2 bits Asynchronous 1 bit LSB first — : Unavailable setting * : "+1" is the address/data selection bit (A/D) used for communication control in multiprocessor mode. The MD1 and MD0 bits in the LIN-UART serial mode register (SMR) are used to select the following LIN-UART operating modes. Table 19.1-3 LIN-UART Operating Modes CM44-10148-4E MD1 MD0 Mode Type 0 0 0 Asynchronous (Normal mode) 0 1 1 Asynchronous (Multiprocessor mode) 1 0 2 Synchronous (Normal mode) 1 1 3 Asynchronous (LIN mode) FUJITSU MICROELECTRONICS LIMITED 447 CHAPTER 19 LIN-UART 19.1 MB90950 Series Notes: • Mode 1 supports both master and slave operation when the master and slave are connected. • Mode 3 is fixed to communication format 8N-1, LSB first. • When the mode is changed, the UART stops transmission/reception and waits until the next communication starts. ■ LIN-UART Interrupts and EI2OS Table 19.1-4 LIN-UART Interrupts and EI2OS Interrupt control register Channel Interrupt No. Vector table address Register name Address Lower Upper Bank EI2OS μDMAC channel LIN-UART0 reception #35(23H) ICR12 0000BCH FFFF70H FFFF71H FFFF72H *1 DRQ10*3 LIN-UART0 transmission #36(24H) ICR12 0000BCH FFFF6CH FFFF6DH FFFF6EH *2 DRQ11 LIN-UART1/3/5 reception #37(25H) ICR13 0000BDH FFFF68H FFFF69H FFFF6AH *1 DRQ12*3 LIN-UART1/3/5 transmission #38(26H) ICR13 0000BDH FFFF64H FFFF65H FFFF66H *2 DRQ13 LIN-UART2/4/6 reception #39(27H) ICR14 0000BEH FFFF60H FFFF61H FFFF62H *1 DRQ14*3 LIN-UART2/4/6 transmission #40(28H) ICR14 0000BEH FFFF5CH FFFF5DH FFFF5EH *2 DRQ15 *1: ICR12 to ICR14 are shared with multiple interrupt sources; therefore, they are only available when such sources are not used as interrupts. EI2OS stop function is available when a reception error is detected. *2: ICR12 to ICR14 are shared with multiple interrupt sources; therefore, they are only available when such sources are not used as interrupts. *3: DMA stop function is available when a reception error is detected. 448 FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 19 LIN-UART 19.2 MB90950 Series 19.2 Configuration of LIN-UART This section briefly outlines the blocks that form the LIN-UART. ■ LIN-UART Consists of the Following Blocks. • Reload counter • Reception control circuit • Reception shift register • Reception data register (RDR) • Transmission control circuit • Transmit shift register • Transmit data register (TDR) • Error detection circuit • Oversampling circuit • Interrupt generation circuit • LIN Synch break/Synch Field detection circuit • Bus idle detection circuit • LIN-UART serial mode register (SMR) • Serial control register (SCR) • Serial status register (SSR) • Extended communication control register (ECCR) • Extended status control register (ESCR) CM44-10148-4E FUJITSU MICROELECTRONICS LIMITED 449 CHAPTER 19 LIN-UART 19.2 MB90950 Series ■ Block Diagram of LIN-UART Figure 19.2-1 Block Diagram of LIN-UART OTO, EXT, REST CLK PE ORE FRE Transmission clock Reception clock Reload counter SCKn Interrupt generation circuit Transmission control circuit Reception control, twice Pin SINn Pin Start bit detection circuit Transmission start circuit Reception bit counter Transmission bit counter Reception parity counter Transmission parity counter Restart reception reload counter Oversampling circuit TIE RIE LBIE LBD RBI TBI Reception IRQ Transmission TDRE IRQ SOTn Pin RDRF SOTn SINn Internal signal to capture LIN break/ Synch Field detection circuit To DMA/ EI2OS SINn Transmit shift register Reception shift register Transmission start Bus idle detection circuit Error detection circuit PE ORE FRE LIN break generation circuit RDRn LBR LBL1 LBL0 TDRn RBI LBD TBI Internal data bus PE ORE FRE RDRF TDRE BDS RIE TIE SSRn register MD1 MD0 OTO EXT REST UPCL SCKE SOE SMRn register PEN P SBL CL A/D CRE RXE TXE SCRn register LBIE LBD LBL1 LBL0 SOPE SIOP CCO SCES LBR ESCRn register MS SCDE SSM ECCRn register RBI TBI n = 0, 1, 2, 3, 4, 5, 6 450 FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 19 LIN-UART 19.2 MB90950 Series ■ Explanation of Each Block ● Reload counter This block is a 15-bit reload counter serving as a dedicated baud rate generator. The block consists of a 15bit register for reload values; it generates the transmission/reception clock from the external or internal clock. The count value in the transmission reload counter is read from BGRn1 and BGRn0. ● Reception control circuit This block consists of a reception bit counter, a start bit detection circuit, and a reception parity counter. The reception bit counter counts the reception data bits and sets a flag in the serial status register when one data reception is completed according to the specified data length. If the reception interrupt is enabled at this time, a reception interrupt request is generated. The start bit detection circuit detects a start bit in a serial input signal. When a start bit is detected, the circuit sends a signal to the reload counter in synchronization with the start bit falling edge. The reception parity counter calculates the parity of the received data. ● Reception shift register This register retrieves data received from the SINn pin while bit-shifting and transfers it to the RDR register upon completion of reception. ● Reception data register (RDR) This register retains the received data. Serial input data is converted and stored in the reception data register. ● Transmission control circuit This block consists of a transmission bit counter, a transmission start circuit, and a transmission parity counter. The transmission bit counter counts the transmit data bits and sends 1 data item according to the specified data length. A flag is set in the serial status register when the transmission bit counter starts sending the data to be written. If the transmit interrupt is enabled at this time, a transmit interrupt request is generated. The transmission start circuit starts transmission when data is written to the TDR. The transmission parity counter generates a parity bit for data to be transmitted if the data is parity-checked. ● Transmit shift register The data written to TDR is transferred to the transmit shift register, and output to the SOTn pin while bitshifting. ● Transmit data register (TDR) This register sets the transmit data. The written data is converted to serial data and output. ● Error detection circuit This circuit detects an error upon completion of reception, if any. If an error occurs, the corresponding error flag is set. CM44-10148-4E FUJITSU MICROELECTRONICS LIMITED 451 CHAPTER 19 LIN-UART 19.2 MB90950 Series ● Oversampling circuit In asynchronous mode, the LIN-UART performs oversampling 5 times using machine clock and determines the received value by majority decision of sampling time. The LIN-UART stops during operation in synchronous mode. ● Interrupt generation circuit This circuit controls all interrupt sources. An interrupt is generated immediately if the corresponding interrupt enable bit has been set. ● LIN Synch break/Synch Field detection circuit This circuit detects a LIN Synch break when the LIN master node transmits a message header. The LBD flag bit is set when the LIN Synch break is detected. An internal signal (LSYN) is output to the capture in order to detect the 1st and 5th falling edges of the LIN Synch Field and to measure the actual serial clock synchronization transmitted by the master node. ● LIN Synch break generation circuit This circuit generates a LIN Synch break with the specified length. ● Bus idle detection circuit This circuit detects that no transmission or reception is in progress, and generates the TBI and RBI flag bits. ● LIN-UART serial mode register (SMR) Operating functions are as follows: • Selects the LIN-UART operating mode • Selects a clock input source • Selects between 1-to-1 connection or reload counter connection for the external clock • Resets a dedicated reload timer • LIN-UART software reset (maintains register settings) • Enables/disables output to the serial data pin • Enables/disables output to the clock pin ● Serial control register (SCR) Operating functions are as follows: • Sets the availability of the parity bit • Selects the parity bit • Sets the stop bit length • Sets the data length • Selects the frame data format in mode 1 • Clears the error flag • Enable/disable transmission • Enable/disable reception 452 FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 19 LIN-UART 19.2 MB90950 Series ● Serial status register (SSR) Operating functions are as follows: • Checks transmission/reception or error status • Selects the transfer direction (LSB first or MSB first) • Enables/disables reception interrupts • Enables/disables transmit interrupts ● Extended status control register (ESCR) • Enables/disables LIN Synch break interrupts • Detects LIN Synch breaks • Selects the LIN Synch break length • Direct access to the SINn and SOTn pins • Sets continuous clock output in LIN-UART synchronous clock mode • Selects the sampling clock edge ● Extended communication control register (ECCR) • Bus idle detection • Synchronous clock setting • LIN Synch break generation CM44-10148-4E FUJITSU MICROELECTRONICS LIMITED 453 CHAPTER 19 LIN-UART 19.3 19.3 MB90950 Series Pins of LIN-UART This section lists and details the pins, interrupt sources and registers of LIN-UART. ■ Pins of LIN-UART The LIN-UART pins also serve as general-purpose ports. Table 19.3-1 shows their functions and I/O format as well as the settings for when the LIN-UART is used. Table 19.3-1 Pins of LIN-UART Pin name Pin function P82/SIN0 P85/SIN1 P50/SIN2 P12/SIN3 P15/SIN4 P90/SIN5 P94/SIN6 Port input/output, serial data input P83/SOT0 P86/SOT1 P51/SOT2 P13/SOT3 P16/SOT4 P91/SOT5 P95/SOT6 Port input/output, serial data output P84/SCK0 P87/SCK1 P52/SCK2 P14/SCK3 P17/SCK4 P92/SCK5 P96/SCK6 I/O format Pull-up selection Standby control Settings required to use the pin Set to the input port (DDR: corresponding bit = 0) CMOS output, CMOS/ automotive input P12 to P17: With pull-up, Others: No pull-up Available Set to enable output (SMRn: SOE = 1) Set to the input port when inputting clock (DDR: corresponding bit = 0) Port input/output, serial clock input/output Set to enable output when outputting clock (SMRn: SCKE = 1) Refer to the Data Sheet "■ Electrical Characteristics - 3. DC Characteristics" for the value. 454 FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 19 LIN-UART 19.3 MB90950 Series ■ Block Diagram of LIN-UART Pins Figure 19.3-1 Block Diagram of LIN-UART Pins Peripheral input Peripheral output Port data register (PDR) Peripheral output enable Internal data bus PDR read Output write P-ch PDR read Pin Port direction register (DDR) N-ch Direction latch General-purpose I/O pin/SIN General-purpose I/O pin/SCK General-purpose I/O pin/SOT DDR write Standby control (SPL = 1) DDR read Standby control: Stop mode (SPL =1), watch mode (SPL =1), time-base timer mode (SPL =1) Note: A peripheral I/O signal is input and output using a pin with a peripheral function. CM44-10148-4E FUJITSU MICROELECTRONICS LIMITED 455 CHAPTER 19 LIN-UART 19.4 19.4 MB90950 Series Registers of LIN-UART This section lists the registers of LIN-UART. ■ List of LIN-UART Registers Figure 19.4-1 List of LIN-UART Registers • LIN-UART0 Address: bit15 bit8 bit7 bit0 000021H, 000020H SCR0 (Serial control register) SMR0 (Serial mode register) 000023H, 000022H SSR0 (Serial status register) RDR0/TDR0 (Reception data register / Transmit data register) 000025H, 000024H ESCR0 (Extended status control register) ECCR0 (Extended communication control register) 000027H, 000026H BGR01 (Baud rate generator register) BGR00 (Baud rate generator register) • LIN-UART1 Address: bit15 bit8 bit7 bit0 000029H, 000028H SCR1 (Serial control register) SMR1 (Serial mode register) 00002BH 00002AH SSR1 (Serial status register) RDR1/TDR1 (Reception data register / Transmit data register) 00002DH 00002CH ESCR1 (Extended status control register) ECCR1 (Extended communication control register) 00002FH 00002EH BGR11 (Baud rate generator register) BGR10 (Baud rate generator register) • LIN-UART2 Address: bit15 bit8 bit7 bit0 0000D9H 0000D8H SCR2 (Serial control register) SMR2 (Serial mode register) 0000DBH 0000DAH SSR2 (Serial status register) RDR2/TDR2 (Reception data register / Transmit data register) 0000DD 0000DCH ESCR2 (Extended status control register) ECCR2 (Extended communication control register) 0000DFH 0000DEH BGR21 (Baud rate generator register) BGR20 (Baud rate generator register) • LIN-UART3 Address: bit15 bit8 bit7 bit0 007951H, 007950H SCR3 (Serial control register) SMR3 (Serial mode register) 007953H, 007952H SSR3 (Serial status register) RDR3/TDR3 (Reception data register / Transmit data register) 007955H, 007954H ESCR3 (Extended status control register) ECCR3 (Extended communication control register) 007957H, 007956H BGR31 (Baud rate generator register) BGR30 (Baud rate generator register) • LIN-UART4 Address: bit15 bit8 bit7 bit0 007959H, 007958H SCR4(Serial control register) SMR4 (Serial mode register) 00795BH 00795AH SSR4 (Serial status register) RDR4/TDR4 (Reception data register / Transmit data register) 00795DH 00795CH ESCR4 (Extended status control register) ECCR4 (Extended communication control register) 00795FH 00795EH BGR41 (Baud rate generator register) BGR40 (Baud rate generator register) (Continued) 456 FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 19 LIN-UART 19.4 MB90950 Series (Continued) • LIN-UART5 Address: bit15 bit8 bit7 bit0 007991H, 007990H SCR5 (Serial control register) SMR5 (Serial mode register) 007993H, 007992H SSR5 (Serial status register) RDR5/TDR5 (Reception data register / Transmit data register) 007995H, 007994H ESCR5 (Extended status control register) ECCR5 (Extended communication control register) 007997H, 007996H BGR51 (Baud rate generator register) BGR50 (Baud rate generator register) • LIN-UART6 Address: bit15 bit8 bit7 bit0 007999H, 007998H SCR6 (Serial control register) SMR6 (Serial mode register) 00799BH 00799AH SSR6 (Serial status register) RDR6/TDR6 (Reception data register / Transmit data register) 00799DH 00799CH ESCR6 (Extended status control register) ECCR6 (Extended communication control register) 00799FH 00799EH BGR61 (Baud rate generator register) BGR60 (Baud rate generator register) CM44-10148-4E FUJITSU MICROELECTRONICS LIMITED 457 CHAPTER 19 LIN-UART 19.4 19.4.1 MB90950 Series Serial Control Register (SCR) The serial control register (SCR) is used to set parity, select the stop bit length and data length, select the frame data format in mode 1, clear the reception error flag, and enable/disable transmission/reception. ■ Serial Control Register (SCR) Figure 19.4-2 Serial Control Register (SCR) Address bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 PEN P SBL CL SCR0 : 000021H SCR1 : 000029H R/W R/W R/W R/W SCR2 : 0000D9H SCR3 : 007951H SCR4 : 007959H SCR5 : 007991H SCR6 : 007999H bit0 Initial value 00000000B A/D CRE RXE TXE R/W W R/W R/W bit8 TXE Transmit enable bit 0 Disables transmission 1 Enables transmission bit9 RXE Reception enable bit 0 Disables reception 1 Enables reception bit10 Reception error flag clear bit CRE Write Read 0 No effect 1 Clears reception error flag (PE, FRE, ORE) "0" is always read bit11 A/D Address/data format selection bit 0 Data frame 1 Address frame bit12 CL Data length selection bit 0 7-bit 1 8-bit bit13 SBL Stop bit length selection bit 0 1-bit 1 2-bit bit14 P 458 Even parity 1 Odd parity R/W : Readable/Writable bit15 W : Write only PEN : Initial value Parity selection bit 0 Parity enable bit 0 No parity 1 With parity FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 19 LIN-UART 19.4 MB90950 Series Table 19.4-1 Functions of Each Bit in Serial Control Register (SCR) Bit name Function bit15 PEN: Parity enable bit Specifies whether or not to add (at transmission) and detect (at reception) a parity bit. Note: The parity bit is added only in operating mode 0, or in operating mode 2 with the settings that start/stop is set (ECCR:SSM = 1). This bit is fixed to "0" in modes 1 and 3. bit14 P: Parity selection bit Sets either odd parity (1) or even parity (0) if the parity bit has been selected (SCR:PEN = 1). bit13 SBL: Stop bit length selection bit Sets the bit length of the stop bit (frame end mark in transmit data) in operating mode 0, 1 (asynchronous) or in operating mode 2 (synchronous) with the settings that start/ stop bit is set (ECCR:SSM = 1). This bit is fixed to "0" in mode 3. Note: At reception, only the first bit of the stop bit is always detected. bit12 CL: Data length selection bit Specifies the data length to be transmitted and received. This bit is fixed to "1" in mode 2 and mode 3. bit11 A/D: Address/data format selection bit Specifies the data format for the frame to be transmitted and received in multiprocessor mode (mode 1). Write to this bit in master mode; read this bit in slave. • When set to "0": Set to data frame. • When set to "1": Set to address data frame. The value of last received data format is read. Note: See Section "19.8 Notes on Using LIN-UART" for using this bit. bit10 CRE: Reception error flag clear bit This bit clears the FRE, ORE, and PE flags in the serial status register (SSR). • Writing "1": Clears the error flag. • Writing "0": No effect. Reading this bit always returns "0". RXE: Reception enable bit Enables or disables the reception of LIN-UART. • Setting to "0": Disables data frame reception. • Setting to "1": Enables data frame reception. The LIN Synch break detection in mode 3 is not affected. Note: When the reception is disabled (RXE = 0) during reception, the reception halts immediately. In that case, the data is not guaranteed. TXE: Transmit enable bit Enables or disables the transmission of LIN-UART. • Setting to "0": Disables data frame transmission. • Setting to "1": Enables data frame transmission. Note: When the transmission is disabled (TXE = 0) during transmission, the transmission halts immediately. In that case, the data is not guaranteed. bit9 bit8 CM44-10148-4E FUJITSU MICROELECTRONICS LIMITED 459 CHAPTER 19 LIN-UART 19.4 19.4.2 MB90950 Series LIN-UART Serial Mode Register (SMR) The LIN-UART serial mode register (SMR) is used to select the operating mode, specify the baud rate clock, and enable/disable output to the serial data and clock pins. ■ LIN-UART Serial Mode Register (SMR) Figure 19.4-3 Serial Mode Register (SMR) Address bit15 SMR0:000020H SMR1:000028H SMR2:0000D8H SMR3:007950H SMR4:007958H SMR5:007990H SMR6:007998H bit8 bit7 bit6 bit5 bit4 bit2 bit3 bit1 bit0 Initial value MD1 MD0 OTO EXT REST UPCL SCKE SOE 00000000B R/W R/W R/W R/W W W R/W R/W bit0 SOE LIN-UART serial data output enable bit 0 General-purpose I/O port 1 LIN-UART serial data output pin bit1 SCKE LIN-UART serial clock output enable bit 0 General-purpose I/O port or LIN-UART clock input pin 1 LIN-UART serial clock output pin bit2 LIN-UART programmable clear bit UPCL Write 0 No effect 1 LIN-UART reset Read "0" is always read bit3 Reload counter restart bit REST Write 0 No effect 1 Restarts the reload counter Read "0" is always read bit4 EXT External serial clock source selection bit 0 Uses the baud rate generator (reload counter) 1 Uses the external serial clock source bit5 OTO R/W : Readable/Writable W : Write only 1-to-1 external clock input enable bit 0 Uses the baud rate generator (reload counter) 1 Uses the external clock directly bit7 bit6 MD1 MD0 0 0 Operating mode setting bits Mode 0: Asynchronous normal 0 1 Mode 1: Asynchronous multiprocessor 1 0 Mode 2: Synchronous 1 1 Mode 3: Asynchronous LIN : Initial value 460 FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 19 LIN-UART 19.4 MB90950 Series Table 19.4-2 Functions of Each Bit in Serial Mode Register (SMR) Bit name Function bit7, bit6 MD1, MD0: Operating mode selection bits These bits set the operating mode. bit5 OTO: 1-to-1 external clock input enable bit Writing "1" enables the external clock to be used directly as the LIN-UART serial clock. It is used for slave operation (ECCR:MS = 1) in operating mode 2. When EXT = 0, the OTO bit is fixed to "0". bit4 EXT: External serial clock source selection bit Selects a clock input. Setting to "0" selects the clock of the internal baud rate generator (reload counter), while setting to "1" selects the external serial clock source. bit3 REST: Reload counter restart bit Writing "1" restarts the reload counter. Writing "0" has no effect. "0" is always read. UPCL: LIN-UART programmable clear bit (LIN-UART software reset) Writing "1" resets the LIN-UART immediately (LIN-UART software reset). Note however that the register settings are maintained. At that time, transmission and reception are suspended. All of the transmit/reception interrupt sources (TDRE, RDRF, LBD, PE, ORE, FRE) are reset. Reset the LIN-UART after the interrupt and transmission are disabled. Also, the reception data register is cleared (RDR = 00H), and the reload counter is restarted. Writing "0" to this bit has no effect. Reading this bit always returns "0". Note: Execute LIN-UART software reset (UPCL=1) when the TXE bit of the serial control register (SCR) is "0". SCKE: LIN-UART serial clock output enable bit Controls the serial clock I/O port. When "0" is written, the SCKn pin works as a general-purpose I/O port or a serial clock input pin. When "1" is written, this pin serves as the serial clock output pin and outputs the clock in operating mode 2. When ECCR:MS=1, the SCKE bit is fixed to "0". Note: When the SCKn pin is used as a serial clock input (SCKE = 0), set the corresponding DDR bits in the general-purpose I/O port as an input port. Also, select the external clock (EXT = 1) by using the clock selection bit. Reference: When the SCKn pin is set as a serial clock output (SCKE = 1), this pin works as a serial clock output pin regardless of the state of the general-purpose I/O port. SOE: LIN-UART serial data output enable bit Enables or disables output of serial data. When "0" is set, the SOTn pin serves as a general-purpose I/O port. When "1" is set, it works as a serial data output pin (SOTn). Reference: When set as a serial data output (SOE = 1), the SOTn pin works as a SOTn pin regardless of the state of a general-purpose I/O port. bit2 bit1 bit0 CM44-10148-4E FUJITSU MICROELECTRONICS LIMITED 461 CHAPTER 19 LIN-UART 19.4 19.4.3 MB90950 Series Serial Status Register (SSR) The serial status register (SSR) is used to check the status of transmission/ reception or error, and to enable/disable interrupts. ■ Serial Status Register (SSR) Figure 19.4-4 Serial Status Register (SSR) Address SSR0:000023H SSR1:00002BH SSR2:0000DBH SSR3:007953H SSR4:00795BH SSR5:007993H SSR6:00799BH bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit0 PE ORE FRE RDRF TDRE BDS RIE TIE R R R R R Initial value 00001000B R/W R/W R/W bit8 TIE Transmit interrupt request enable bit 0 Disables transmit interrupts. 1 Enables transmit interrupts. bit9 RIE Reception interrupt request enable bit 0 Disables reception interrupts. 1 Enables reception interrupts. bit10 BDS Transfer direction selection bit 0 LSB first (transfer from the least significant bit) 1 MSB first (transfer from the most significant bit) bit11 TDRE Transmit data empty flag bit 0 Transmit data register (TDR) contains data. 1 Transmit data register (TDR) is empty. bit12 RDRF Reception data full flag bit 0 Reception data register (RDR) is empty. 1 Reception data register (RDR) contains data. bit13 FRE Framing error flag bit 0 No framing error 1 Framing error exists. bit14 ORE Overrun error flag bit 0 No overrun error 1 Overrun error exists. bit15 PE R/W : Readable/Writable R : Read only Parity error flag bit 0 No parity error 1 Parity error exists. : Initial value 462 FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 19 LIN-UART 19.4 MB90950 Series Table 19.4-3 Functions of Each Bit in Serial Status Register (SSR) (1 / 2) Bit name Function bit15 PE: Parity error flag bit • This bit is set to "1" when a parity error occurs during reception with PE = 1, and cleared by writing "1" to the CRE bit in the LIN-UART serial control register (SCR). • Outputs a reception interrupt request when both PE bit and RIE bit are "1". • When this flag is set, the data in the reception data register (RDR) is invalid. bit14 ORE: Overrun error flag bit • This bit is set to "1" when an overrun occurs during reception, and cleared by writing "1" to the CRE bit in the LIN-UART serial control register (SCR). • Outputs a reception interrupt request when both ORE bit and RIE bit are "1". • When this flag is set, the data in the reception data register (RDR) is invalid. bit13 FRE: Framing error flag bit • This bit is set to "1" when a framing error occurs during reception, and cleared by writing "1" to the CRE bit in the LIN-UART serial control register (SCR). • Outputs a reception interrupt request when both FRE bit and RIE bit are "1". • When this flag is set, the data in the reception data register (RDR) is invalid. Note: When SCR:SBL is 1, and a framing error is detected at the first or second bit (stop bit), this bit is set to "1" regardless of which stop bit. Therefore, it is necessary to determine whether the reception data is valid or invalid at the second stop bit. bit12 RDRF: Reception data full flag bit • This flag shows the status of the reception data register (RDR). • This bit is set to "1" when received data is loaded into RDR, and cleared to "0" by reading the reception data register (RDR). • Outputs a reception interrupt request when both RDRF bit and RIE bit are "1". TDRE: Transmit data empty flag bit • This flag shows the status of the transmit data register (TDR). • This bit is set to "0" by writing the transmit data to TDR, and indicates that the TDR has valid data. This bit is set to "1" when data is loaded into the transmit shift register and the transmission starts, and indicates that the TDR does not have valid data. • Outputs a transmit interrupt request when both TDRE bit and TIE bit are "1". • When the TDRE bit is "1", setting the LBR bit in the extended communication control register (ECCR) to "1" changes the TDRE bit to "0". Then, the TDRE bit goes back to "1" when TDR does not have valid data after LIN Synch break is generated. Note: The initial state is TDRE = 1. BDS: Transfer direction selection bit Specifies whether the transfer serial data is transferred from the least significant bit (LSB first, BDS = 0) or from the most significant bit (MSB first, BDS = 1). It is fixed to "0" in mode 3. Note: Data values are exchanged between the upper and lower when reception data is written to the reception data register (RDR). Consequently, if the BDS bit is rewritten after reception data is written to RDR, the RDR data will be invalid. bit11 bit10 CM44-10148-4E FUJITSU MICROELECTRONICS LIMITED 463 CHAPTER 19 LIN-UART 19.4 MB90950 Series Table 19.4-3 Functions of Each Bit in Serial Status Register (SSR) (2 / 2) Bit name Function bit9 RIE: Reception interrupt request enable bit • Enables or disables the output of a reception interrupt request to the CPU. • Outputs a reception interrupt request when both the RIE bit and the reception data flag bit (RDRF) are "1", or when one or more error flag bits (PE, ORE, FRE) is "1". bit8 TIE: Transmit interrupt request enable bit • Enables or disables the output of a transmit interrupt request to the CPU. • Outputs a transmit interrupt request when both TIE bit and TDRE bit are "1". 464 FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 19 LIN-UART 19.4 MB90950 Series 19.4.4 Reception Data Register / Transmit Data Register (RDR/TDR) The reception and transmit data registers are located at the same address. If read, they work as the reception data register; if written, they work as the transmit data register. ■ Bit Configuration of Reception Data Register / Transmit Data Register (RDR/TDR) Figure 19.4-5 shows the bit configuration of the reception register. Figure 19.4-5 Reception Data Register / Transmit Data Register (RDR/TDR) Address RDR0/TDR0: 000022H RDR1/TDR1: 00002AH RDR2/TDR2: 0000DAH RDR3/TDR3: 007952H RDR4/TDR4: 00795AH RDR5/TDR5: 007992H RDR6/TDR6: 00799AH bit 7 6 5 4 3 2 1 0 Initial value 00000000B [RDR] 11111111B [TDR] R/W R/W R/W R/W R/W R/W R/W R/W bit7 to bit0 R/W: Readable/Writable R/W Data register Read Reads from the reception data register Write Writes to the transmit data register ■ Reception Data Register (RDR) The reception data register (RDR) is the data buffer register for the serial data reception. The serial data signal sent to the serial input pin (SINn pin) is converted via a shift register and stored in the reception data register (RDR). If the data length is 7 bits, the upper 1 bit (RDR:D7) is "0". The reception data full flag bit (SSR:RDRF) is set to "1" when received data is stored into the reception data register (RDR). If the reception interrupt is enabled (SSR:RIE = 1), a reception interrupt request is generated. Read the reception data register (RDR) when the reception data full flag bit (SSR:RDRF) is "1". The reception data full flag bit (SSR:RDRF) is automatically cleared to "0" by reading the reception data register (RDR). Also, the reception interrupt is cleared when the reception interrupt is enabled and no error occurs. When the reception error occurs (any of SSR:PE, ORE, or FRE is "1"), the data in the reception data register (RDR) is invalid. CM44-10148-4E FUJITSU MICROELECTRONICS LIMITED 465 CHAPTER 19 LIN-UART 19.4 MB90950 Series ■ Transmit Data Register (TDR) The transmit data register (TDR) is the data buffer register for the serial data transmission. If the data to be transmitted is written to the transmit data register (TDR) when transmission is enabled (SCR:TXE = 1), the transmit data is transferred to the transmit shift register, converted to serial data, and output from the serial data output pin (SOTn pin). If the data length is 7 bits, the data in the upper 1 bit (TDR:D7) is invalid. The transmit data empty flag (SSR:TDRE) is cleared to "0" when transmit data is written to the transmit data register (TDR). The transmit data empty flag (SSR:TDRE) is set to "1" after the data is transferred to the transmit shift register and the transmission starts. If the transmit data empty flag (SSR:TDRE) is "1", the next transmit data can be written. If the transmit interrupt is enabled, a transmit interrupt is generated. Write the next transmit data by generating the transmit interrupt, or when the transmit data empty flag (SSR:TDRE) is "1". Note: The transmit data register is a write-only register; the reception data register is a read-only register. Since both registers are located at the same address, the write value and read value are different. Thus, read-modify-write (RMW) instructions such as the INC/DEC instruction cannot be used. 466 FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 19 LIN-UART 19.4 MB90950 Series 19.4.5 Extended Status Control Register (ESCR) The extended status control register (ESCR) has the settings for enabling/ disabling LIN Synch break interrupt, LIN Synch break length selection, LIN Synch break detection, direct access to the SINn and SOTn pins, continuous clock output in LIN-UART synchronous clock mode and sampling clock edge. ■ Bit Configuration of Extended Status Control Register (ESCR) Figure 19.4-6 shows the bit configuration of the extended status control register (ESCR). Table 19.4-4 shows the function of each bit. Figure 19.4-6 Bit Configuration of Extended Status Control Register (ESCR) Address bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 ESCR0 : 000025H LBIE LBD LBL1 LBL0 SOPE SIOP CCO SCES ESCR1 : 00002DH ESCR2 : 0000DDH R/W R/W R/W R/W R/W R/W R/W R/W ESCR3 : 007955H ESCR4 : 00795DH ESCR5 : 007995H ESCR6 : 00799DH bit0 Initial value 00000X00B bit8 SCES 0 1 Sampling clock edge selection bit (mode 2) Sampling at the rising edge of the clock (normal) Sampling at the falling edge of the clock (inverted clock) bit9 CCO 0 1 Continuous clock output enable bit (mode 2) Disables continuous clock output Enables continuous clock output bit10 SIOP 0 1 Serial I/O pin direct access bit Write (SOPE = 1) Read Fixes SOTn pin to "0" Read the value of SINn pin Fixes SOTn pin to "1" bit11 SOPE 0 1 Serial output pin direct access enable bit Disables serial output pin direct access Enables serial output pin direct access bit13 LBL1 0 0 1 1 bit12 LBL0 0 1 0 1 LIN Synch break length selection bits 13 bits 14 bits 15 bits 16 bits bit14 LBD 0 1 R/W X : Readable/Writable : Undefined bit15 LBIE 0 1 LIN Synch break detection flag bit Write Read Clears LIN Synch break No LIN Synch break detection flag detection With LIN Synch break No effect detection LIN Synch break detection interrupt enable bit Disables LIN Synch break detection interrupt Enables LIN Synch break detection interrupt : Initial value CM44-10148-4E FUJITSU MICROELECTRONICS LIMITED 467 CHAPTER 19 LIN-UART 19.4 MB90950 Series Table 19.4-4 Functions of Each Bit in Extended Status Control Register (ESCR) Bit name Function LBIE: LIN Synch break detection interrupt enable bit This bit enables or disables LIN Synch break detection interrupts. An interrupt is generated when the LIN Synch break detection flag (LBD) is "1" and the interrupt is enabled (LBIE = 1). This bit is fixed to "0" in mode 1 and mode 2. bit14 LBD: LIN Synch break detection flag bit This bit is set to "1" when the LIN Synch break is detected in operating mode 3 (the serial input is "0" when bit width is 11 bits or more). Also, writing "0" clears the LBD bit and the interrupt. Although the bit is always read as "1" when the RMW instruction is executed, this does not indicate that a LIN Synch break has been detected. Note: To detect a LIN Synch break, enable the LIN Synch break detection interrupt (LBIE = 1), and then disable the reception (SCR:RXE = 0). bit13, bit12 LBL1/0: LIN Synch break length selection bits These bits specify the bit length for the LIN Synch break generation time. The LIN Synch break length for reception is always 11 bits. bit11 SOPE: Serial output pin direct access enable bit* Setting this bit to "1" when serial data output is enabled (SMR:SOE = 1) enables direct writing to the SOTn pin.* bit10 SIOP: Serial I/O pin direct access bit* Normal read instruction always returns the value of the SINn pin. When direct access to the serial output pin is enabled (SOPE = 1), the SOTn pin reflects the value written to this bit. Note: The bit operation instruction returns the bit value of the SOTn pin in the read cycle.* bit9 CCO: Continuous clock output enable bit If the SCKn pin is set to output clock when operating mode 2 and master setting are selected, this will enable the continuous serial clock output from the SCKn pin. Note: When the CCO bit is "1", the SSM bit in the ECCR should be set to "1". bit8 SCES: Sampling clock edge selection bit When SCES is set to "1" in operating mode 2 with the slave setting, the sampling edge switches from the rising edge to the falling edge. When the SCKn pin is set to output clock in operating mode 2 with the master setting (ECCR:MS=0), the internal serial clock and the output clock signal are inverted. This bit should be fixed to "0" in operating modes 0, 1, and 3. bit15 *: Table 19.4-5 Interaction between SOPE and SIOP SOPE SIOP 0 R/W No effect (but the write value is retained) Return the SINn value 1 R/W Write "0" or "1" to SOTn Return the SINn value 0 RMW No effect (but the write value is retained) Return the SOTn value 1 RMW Write "0" or "1" to SOTn Return the SOTn value 468 Write to SIOP FUJITSU MICROELECTRONICS LIMITED Read from SIOP CM44-10148-4E CHAPTER 19 LIN-UART 19.4 MB90950 Series 19.4.6 Extended Communication Control Register (ECCR) The extended communication control register (ECCR) is used for the bus idle detection, the synchronous clock setting, and the LIN Synch break generation. ■ Bit Configuration of Extended Communication Control Register (ECCR) Figure 19.4-7 shows the bit configuration of the extended communication control register (ECCR). Table 19.4-6 shows the function of each bit. Figure 19.4-7 Bit Configuration of Extended Communication Control Register (ECCR) Address bit15 ECCR0:000024H ECCR1:00002CH ECCR2:0000DCH ECCR3:007954H ECCR4:00795CH ECCR4:007994H ECCR4:00799CH bit8 bit7 bit6 bit5 LBR MS W R/W bit4 bit3 bit2 SCDE SSM R/W R/W bit1 bit0 RBI TBI R R Initial value 000000XXB bit0 TBI* 0 1 Transmit bus idle detection flag bit In transmission No transmission bit1 RBI* 0 1 Reception bus idle detection flag bit In reception No reception bit2 Unused bit The read value is "0". Always write "0". bit3 SSM 0 1 bit4 SCDE 0 1 bit5 MS 0 1 Start/stop mode enable bit (mode 2) No start/stop bit With start/stop bit Serial clock delay enable bit (mode 2) Disables clock delay Enables clock delay Master/slave mode selection bit (mode 2) Master mode (serial clock generation) Slave mode (external serial clock reception) bit6 LBR 0 R/W R W X 1 : Readable/Writable : Read only : Write only : Undefined : Initial value LIN Synch break generation bit Write Read No effect LIN Synch break generation "0" always read bit7 Unused bit The read value is "0". Always write "0". * : Not used when SSM is "0" in operating mode 2 CM44-10148-4E FUJITSU MICROELECTRONICS LIMITED 469 CHAPTER 19 LIN-UART 19.4 MB90950 Series Table 19.4-6 Functions of Each Bit in Extended Communication Control Register (ECCR) Bit name Function bit7 Unused bit This bit is unused. The read value is undefined. Always write "0". bit6 LBR: Lin Synch break generation bit Setting this bit to "1" in mode 3 generates a LIN Synch break which has the length specified by LBL0/LBL1 in the ESCR. Set the bit to "0" in mode 0. bit5 MS: Master/slave mode selection bit In mode 2, the master or slave can be selected. When MS is set to "0" (master mode selected), a synchronous clock is generated. When MS is set to "1" (slave mode selected), the external serial clock is received. In modes 0, 1 and 3, it is fixed to "0". Modify this bit only when the SCR:TXE bit is "0". Note: When slave mode is selected, set the clock source to the external clock to enable the input of the external clock. (SMR:SCKE=0, EXT=1, OTO=1) bit4 SCDE: Serial clock delay enable bit Setting the SCDE bit to "1" in the master mode operation during mode 2 outputs a delayed serial clock as shown in Figure 19.7-5. This bit is effective in SPI. In modes 0, 1 and 3, it is fixed to "0". bit3 SSM: Start/stop bit mode enable bit This bit adds the start/stop bit to the synchronous data format when set to "1" in mode 2. In modes 0, 1 and 3, it is fixed to "0". bit2 Unused bit This bit is unused. The read value is undefined. Always write "0". bit1 RBI: Reception bus idle detection flag bit This bit is set to "1" when the SIN pin is set to "H" level and reception is not performed. Do not use this bit in operating mode 2. bit0 TBI: Transmit bus idle detection flag bit This bit is set to "1" when there is no transmission at the SOTn pin. Do not use this bit when MS is "0" in operating mode 2. 470 FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 19 LIN-UART 19.4 MB90950 Series 19.4.7 Baud Rate Generator Register 0, 1 (BGRn0/BGRn1) The baud rate generator register 0, 1 (BGRn0/BGRn1) sets the division ratio of the serial clock. Moreover, the count value in the transmit reload counter is read from this generator. ■ Bit Configuration of Baud Rate Generator Register (BGRn0/BGRn1) Figure 19.4-8 shows the bit configuration of the baud rate generator register (BGRn0/BGRn1). Figure 19.4-8 Bit Configuration of Baud Rate Generator Register (BGRn0/BGRn1) Address bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 BGR00: 000026H BGR01: 000027H BGR10: 00002EH BGR11: 00002FH BGR20: 0000DEH BGR21: 0000DFH BGR30: 007956H BGR31: 007957H BGR40: 00795EH BGR41: 00795FH BGR50: 007996H BGR51: 007997H BGR60: 00799EH BGR61: 00799FH bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Initial value 00000000 B 00000000 B R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W bit7 to bit0 Write Read Baud rate generator register n0 Write to reload counter bits 0 to 7. Read transmit reload counter bits 0 to 7. bit14 to bit8 Write Read Baud rate generator register n1 Write to reload counter bits 8 to 14. Read transmit reload counter bits 8 to 14. bit15 R/W : Readable/Writable R : Read only n = 0, 1, 2, 3, 4, 5, 6 Undefined bit The read value is "0". Writing has no effect on operation. The baud rate generator register sets the division ratio of the serial clock. BGRn1 is associated with the upper bits; BGRn0 is associated with the lower bits. The reload value of the counter can be written and the transmit reload counter value can be read from them. Byte/word access is also possible. Writing a reload value other than "0" to the baud rate generator registers causes the reload counter to start counting. CM44-10148-4E FUJITSU MICROELECTRONICS LIMITED 471 CHAPTER 19 LIN-UART 19.5 19.5 MB90950 Series Interrupts of LIN-UART The LIN-UART has reception interrupts and transmit interrupts, which are generated by following interrupt sources. • When received data is set in the reception data register (RDR), or when a reception error occurs • When transmit data is transferred from the transmit data register (TDR) to the transmit shift register and the transmission starts • When a LIN Synch break is detected Each interrupt supports the extended intelligent I/O service (EI2OS) and DMA. ■ Interrupts of LIN-UART Table 19.5-1 shows the interrupt control bits and interrupt sources of the LIN-UART. Table 19.5-1 Interrupt Control Bits and Interrupt Sources of LIN-UART TX/RX/ Capture Interrupt request flag bit Flag register 0 1 2 3 RDRF SSR ❍ ❍ ❍ ❍ Writing reception data to RDR ORE SSR ❍ ❍ ❍ ❍ Overrun error FRE SSR ❍ ❍ ❍ Framing error PE SSR ❍ × × Parity error LBD ESCR × × ❍ Detecting LIN Synch ESCR:LBIE break Writing "0" to ESCR:LBD Writing transmit data; writing "1" to LIN Synch break generation bit (ECCR:LBR) RX ❍ Interrupt source × Interrupt source enable bit SSR:RIE TDRE SSR ❍ ❍ ❍ ❍ ICP0/ICP1/ ICP4/ICP5/ ICP6/ICP7 ICS01/ ICS45/ ICS67 × × × ❍ 1st falling edge in LIN Synch field ICP0/ICP1/ ICP4/ICP5/ ICP6/ICP7 ICS01/ ICS45/ ICS67 × × × ❍ 5th falling edge in LIN Synch field Clearing interrupt request flag Reading reception data Transmit register being SSR:TIE empty TX Input capture Operating mode ICS01/ ICS45/ ICS67: ICE0/ ICE1/ ICE4/ ICE5/ ICE6/ ICE7 Writing "1" to reception error flag clear bit (SCR:CRE) Disabling ICP0/ICP1/ICP4/ ICP5/ICP6/ICP7 : Used bit × : Unused bit : Available only when ECCR:SSM=1 472 FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 19 LIN-UART 19.5 MB90950 Series ● Reception interrupts Each flag bit in the serial status register (SSR) is set to "1" when any of the following operation occurs in reception mode: Data reception completed When the reception data is transferred from the reception shift register to the reception data register (RDR) (RDRF = 1) Overrun error When RDRF is 1, and the next reception data is transferred from the reception shift register to the reception data register (RDR) (ORE=1) without RDR being read by the CPU Framing error Stop bit reception error (FRE=1) Parity error Parity detection error (PE=1) A reception interrupt request is generated if the reception interrupt is enabled (SSR:RIE=1) when any of the above flag bits is "1". The RDRF flag is automatically cleared to "0" by reading the reception data register (RDR). All of error flags are cleared to "0" by writing "1" to the reception error flag clear bit (CRE) in the serial control register (SCR). Note: CRE flag is write-only, and retains "1" for one clock cycle when "1" is written. ● Transmit Interrupts The transmit data register empty flag bit (TDRE) in the serial status register (SSR) is set to "1" when the transmit data is transferred from the transmit data register (TDR) to the transmit shift register, and the transmission starts. If the transmit interrupt is enabled (SSR:TIE=1) in this case, a transmit interrupt request is generated. Note: Since the initial value of TDRE is "1" after hardware/software reset, an interrupt is generated immediately after the TIE bit is set to "1". Moreover, the TDRE is cleared by writing data to the transmit data register (TDR), or by writing "1" to the LIN Synch break generation bit (ECCR:LBR). ● LIN Synch break interrupts This works for LIN slave operation in operation mode 3. The LIN Synch break detection flag bit (LBD) in the extended status control register (ESCR) is set to "1" when the bus (serial input) is "0" for 11 bits or longer. The LIN Synch break interrupt and the LBD flag are cleared by writing "0" to the LBD flag. The LBD flag must be cleared before the capture interrupt is generated in the LIN Synch field. To detect a LIN Synch break, the reception must be disabled (SCR:RXE=0). CM44-10148-4E FUJITSU MICROELECTRONICS LIMITED 473 CHAPTER 19 LIN-UART 19.5 MB90950 Series ● LIN Synch field edge detection interrupt This works for LIN slave operation in operation mode 3. After a LIN Synch break is detected, the internal signal is set to "1" at the first falling edge of the LIN Synch field, and clear to "0" after the fifth falling edge. When the capture side is configured to input the internal signal (ICU0/ICU1/ICU4/ICU5/ICU6/ICU7) and to detect both edges, an input capture interrupt is generated if enabled. The difference in the count values detected by the capture function corresponds to the 8 bits in the master serial clock. The new baud rate can be calculated from this value. When a falling edge of the start bit is detected, the reload counter restarts automatically. ■ LIN-UART Interrupts and EI2OS Table 19.5-2 LIN-UART Interrupts and EI2OS Interrupt control register Channel Vector table address EI2OS Interrupt No. Register name Address Lower Upper Bank DMA channel LIN-UART0 reception #35(23H) ICR12 0000BCH FFFF70H FFFF71H FFFF72H *1 DRQ10*3 LIN-UART0 transmission #36(24H) ICR12 0000BCH FFFF6CH FFFF6DH FFFF6EH *2 DRQ11 LIN-UART1/3/5 reception #37(25H) ICR13 0000BDH FFFF68H FFFF69H FFFF6AH *1 DRQ12*3 LIN-UART1/3/5 transmission #38(26H) ICR13 0000BDH FFFF64H FFFF65H FFFF66H *2 DRQ13 LIN-UART2/4/6 /reception #39(27H) ICR14 0000BEH FFFF60H FFFF61H FFFF62H *1 DRQ14*3 LIN-UART2/4/6 transmission #40(28H) ICR14 0000BEH FFFF5CH FFFF5DH FFFF5EH *2 DRQ15 *1: ICR12 to ICR14 are shared with multiple interrupt sources; therefore, they are only available when such sources are not used as interrupts. EI2OS stop function is available when a reception error is detected. *2: ICR12 to ICR14 are shared with multiple interrupt sources; therefore, they are only available when such sources are not used as interrupts. *3: DMA stop function is available when a reception error is detected. ■ EI2OS Function of LIN-UART LIN-UART has a circuit supporting the EI2OS. As a result, the EI2OS can be activated individually for each reception/transmit interrupt. ● Reception As the interrupt control register is also shared by transmit interrupts and other UART, the EI2OS is available only when no other interrupts are enabled. ● Transmission As the interrupt control register is also shared by reception interrupts and other UART, the EI2OS is available only when no other interrupts are enabled. 474 FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 19 LIN-UART 19.5 MB90950 Series 19.5.1 Timing of Reception Interrupt Generation and Flag Set Reception interrupts include a reception completion (SSR:RDRF) and an occurrence of a reception error (SSR:PE, ORE, FRE). ■ Timing of Reception Interrupt Generation and Flag Set Received data is stored in the reception data register (RDR) when the first stop bit is detected in mode 0, 1, 2 (SSM=1), 3, or when the last data bit is detected in mode 2 (SSM=0). Each error flag is set when a reception is completed (SSR:RDRF=1), or when a reception error occurs (SSR:PE, ORE, FRE = 1). If the reception interrupt is enabled (SSR:RIE=1) at this time, a reception interrupt is generated. Note: When a reception error occurs in each mode, the data in the reception data register (RDR) is invalid. Figure 19.5-1 shows the timing of reception and flag set. Figure 19.5-1 Timing of Reception and Flag Set Reception data (Mode 0/Mode 3) ST D0 D1 D2 … D5 D6 D7/P SP ST Reception data (Mode 1) ST D0 D1 D2 … D6 D7 A/D SP ST D0 D1 D2 … D4 D5 D6 D7 D0 Reception data (Mode 2) PE*1, FRE RDRF ORE*2 (RDRF = 1) Reception interrupts generated *1: PE flag is always "0" in mode 1 and mode 3. *2: An overrun error occurs if the next data is transferred before received data is read (RDRF = 1). ST: Start bit, SP: Stop bit, A/D: Mode 1 (multiprocessor) address data selection bit Note: Figure 19.5-1 does not show all receptions in mode 0. It only shows examples for "7P1" and "8N1" (P = "even parity" or "odd parity"). Figure 19.5-2 ORE Flag Set Timing Reception data RDRF ORE CM44-10148-4E FUJITSU MICROELECTRONICS LIMITED 475 CHAPTER 19 LIN-UART 19.5 19.5.2 MB90950 Series Timing of Transmit Interrupt Generation and Flag Set Transmit interrupts are generated when the transmit data is transferred from the transmit data register (TDR) to the transmit shift register and then the transmission starts. ■ Timing of Transmit Interrupt Generation and Flag Set When the data written to the transmit data register (TDR) is transferred to the transmit shift register and then the transmission starts, the next data becomes writable (SSR:TDRE=1). If the transmit interrupt is enabled (SSR:TIE=1) at this time, a transmit interrupt is generated. TDRE bit is a read-only bit and cleared to "0" only by writing data to the transmit data register (TDR). Figure 19.5-3 shows the timing of the transmission and flag set in each LIN-UART mode. Figure 19.5-3 Timing of Transmission and Flag Set Transmit interrupt generated Transmit interrupt generated Mode 0, Mode1, Mode2 (SSM=1) or Mode 3: Write to TDR TDRE Serial output ST D0 D1 D2 D3 D4 D5 D6 D7 P SP ST D0 D1 D2 D3 D4 D5 D6 D7 P SP A/D A/D Transmit interrupt generated Transmit interrupt generated Mode 2 (SSM=0): Write to TDR TDRE Serial output D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 ST: Start bit, D0 to D7: Data bits, P: Parity (SSM=1 in modes 0 and 2), SP: Stop bit A/D: Address data selection bit (mode 1) Note: Figure 19.5-3 does not show all transmissions in mode 0. It only shows an example for "8p1" (p = "even parity" or "odd parity"). No parity bit or address data selection bit are transmitted in mode 3, or in mode 2 with SSM=0. 476 FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 19 LIN-UART 19.5 MB90950 Series ■ Transmit Interrupt Request Generation Timing If the TDRE flag is set to "1" when the transmit interrupt is enabled (SSR:TIE=1), a transmit interrupt request is generated. Note: Since the TDRE bit is initially set to "1", a transmit interrupt is generated immediately after the transmit interrupt is enabled (SSR:TIE=1). Be careful with the timing for enabling the transmit interrupt since the TDRE bit can be cleared only by writing new data to the transmit data register (TDR). CM44-10148-4E FUJITSU MICROELECTRONICS LIMITED 477 CHAPTER 19 LIN-UART 19.6 19.6 MB90950 Series Baud Rate of LIN-UART One of the following can be selected for the LIN-UART transmission/reception clock source: • Dedicated baud rate generator (reload counter) • External clock input to the baud rate generator (reload counter) • External clock (using the SCKn pin input clock directly) ■ LIN-UART Baud Rate Selection The baud rate can be selected from the following three different rates. Figure 19.6-1 shows the baud rate selection circuit. ● Baud rate derived from the internal clock divided by the dedicated baud rate generator (reload counter) Two internal reload counters are provided and assigned to the transmit and reception serial clock respectively. The baud rate is selected by setting a 15-bit reload value in the baud rate generator register 1, 0 (BGRn1, BGRn0). The reload counter divides the internal clock by the specified value. It is used in asynchronous mode and in synchronous mode (master). To set the clock source, select the use of the internal clock and baud rate generator (SMR:EXT=0, OTO=0). ● Baud rate derived from the external clock divided by the dedicated baud rate generator (reload counter) The external clock is used as the clock source for the reload counter. The baud rate is selected by setting a 15-bit reload value in the baud rate generator register 1, 0 (BGRn1, BGRn0). The reload counter divides the external clock by the specified value. It is used in asynchronous mode. To set the clock source, select the use of the external clock and baud rate generator (SMR:EXT=1, OTO=0). This mode is available in case that an oscillator with a special frequency is divided for use. ● Baud rate by the external clock (1-to-1 mode) The clock input from the clock input pin (SCKn) of the LIN-UART is used as the baud rate (synchronous mode 2, slave operation (ECCR:MS=1)). It is used in synchronous mode (slave). To set the clock source, select the external clock and its direct use (SMR:EXT=1, OTO=1). 478 FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 19 LIN-UART 19.6 MB90950 Series Figure 19.6-1 LIN-UART Baud Rate Selection Circuit Start bit falling edge detection Reception clock REST Reload value: v Reception 15-bit reload counter Set Rxc = 0? Reload FF 0 Reset Rxc = v/2? 1 Reload value: v CLK 0 SCKn (External clock input) 1 Transmit 15-bit reload counter Counter value: TXC EXT Txc = 0? Set OTO FF Reload 0 Reset Txc = v/2? 1 Transmit clock Internal data bus EXT REST OTO SMRn register BGR14 BGR13 BGR12 BGR11 BGR10 BGR9 BGR8 BGRn1 register BGR7 BGR6 BGR5 BGR4 BGR3 BGR2 BGR1 BGR0 BGRn0 register n=0,1,2,3,4,5,6 CM44-10148-4E FUJITSU MICROELECTRONICS LIMITED 479 CHAPTER 19 LIN-UART 19.6 19.6.1 MB90950 Series Baud Rate Setting This section shows baud rate settings and the calculation result of serial clock frequencies. ■ Baud Rate Calculation The two 15-bit reload counters are set by the baud rate generator register 1, 0 (BGRn1, BGRn0). The expressions for the baud rate are as follows. Reload value: v = (φ / b)-1 v: Reload value, b: Baud rate, φ: Machine clock or external clock frequency Calculation example Assuming that the machine clock is 16 MHz, the internal clock is used, and the baud rate is set to 19200 bps: Reload value: v= ( 16 × 106 19200 ) -1 = 832 Thus, the actual baud rate can be calculated as follows. b= φ (v + 1) = 16 × 106 = 19207.6831 833 Note: The reload counter halts if the reload value is set to "0". Therefore, the minimum division ratio should be 2. For transmission/reception in asynchronous mode, the reload value must be at least "4" in order to determine the reception value by oversampling for 5 times. 480 FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 19 LIN-UART 19.6 MB90950 Series ■ Reload Value and Baud Rate for Each Clock Speed Table 19.6-1 shows the reload value and baud rate for each clock speed. Table 19.6-1 Reload Value and Baud Rate 8 MHz 10 MHz 16 MHz 20 MHz 24 MHz 32 MHz Baud rate value dev. value dev. value dev. value dev. value dev. value dev. 4M — — — — — — — — 5 0 7 0 2M — — — — 7 0 9 0 11 0 15 0 1M 7 0 9 0 15 0 19 0 23 0 31 0 500000 15 0 19 0 31 0 39 0 47 0 63 0 460800 — — — — — — — — 51 -0.16 68 -0.64 250000 31 0 39 0 63 0 79 0 95 0 127 0 230400 — — — — — — — — 103 -0.16 138 0.08 153600 51 -0.16 64 -0.16 103 -0.16 129 -0.16 155 -0.16 207 -0.16 125000 63 0 79 0 127 0 159 0 191 0 255 0 115200 68 -0.64 86 0.22 138 0.08 173 0.22 207 -0.16 277 0.08 76800 103 -0.16 129 -0.16 207 -0.16 259 -0.16 311 -0.16 416 0.08 57600 138 0.08 173 0.22 277 0.08 346 -0.06 416 0.08 555 0.08 38400 207 -0.16 259 -0.16 416 0.08 520 0.03 624 0 832 -0.04 28800 277 0.08 346 < 0.01 554 -0.01 693 -0.06 832 -0.03 1110 -0.01 19200 416 0.08 520 0.03 832 -0.03 1041 0.03 1249 0 1666 0.02 10417 767 < 0.01 959 < 0.01 1535 < 0.01 1919 < 0.01 2303 < 0.01 3071 < 0.01 9600 832 0.04 1041 0.03 1666 0.02 2083 0.03 2499 0 3332 -0.01 7200 1110 < 0.01 1388 < 0.01 2221 < 0.01 2777 < 0.01 3332 < 0.01 4443 -0.01 4800 1666 0.02 2082 -0.02 3332 < 0.01 4166 < 0.01 4999 0 6666 < 0.01 2400 3332 < 0.01 4166 < 0.01 6666 < 0.01 8332 < 0.01 9999 0 13332 < 0.01 1200 6666 < 0.01 8334 0.02 13332 < 0.01 16666 < 0.01 19999 0 26666 < 0.01 600 13332 < 0.01 16666 < 0.01 26666 < 0.01 — — — — — — 300 26666 < 0.01 — — — — — — — — — — The unit of frequency deviation (dev.) is %. Note: The maximum baud rate for synchronous mode is 1/6 of the machine clock (value=5). ■ External Clock The external clock is selected by writing "1" to the EXT bit in the LIN-UART serial mode register (SMR). In the baud rate generator, the external clock can be used in the same way as the internal clock. When slave operation is used in synchronous mode 2, select the 1-to-1 external clock input mode (SMR:OTO=1). In this mode, the external clock input to SCKn is input directly to the UART serial clock. Note: The external clock signal is synchronized with the internal clock in the LIN-UART. Therefore, If the external clock used cannot be synchronized, the LIN-UART operation becomes unstable. CM44-10148-4E FUJITSU MICROELECTRONICS LIMITED 481 CHAPTER 19 LIN-UART 19.6 MB90950 Series ■ Reload Counter Operation Figure 19.6-2 shows the operation of the 2 reload counters when the reload value is 832. Figure 19.6-2 Operation of Reload Counter Transmit/reception clock Reload counter 001 000 832 831 830 829 828 827 413 412 411 410 Reload counter value Transmit/reception clock Reload counter 417 416 415 414 Note: The falling edge of the serial clock signal is generated after the reload value divided by 2 ((v+1)/2) is counted. 482 FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 19 LIN-UART 19.6 MB90950 Series 19.6.2 Reload Counter This block is a 15-bit reload counter serving as a dedicated baud rate generator. It generates the transmit/reception clock from the external or internal clock. The count value in the transmit reload counter can be read from the baud rate generator registers (BGRn1, BGRn0). ■ Function of Reload Counter There are two kinds of reload counters: transmit and reception. They work as the dedicated baud rate generator. The block consists of a 15-bit register for reload values; it generates the transmit/reception clock from the external or internal clock. The count value in the transmit reload counter can be read from the baud rate generator registers (BGRn1, BGRn0). ● Count start Writing a reload value other than "0" to the baud rate generator registers (BGRn1, BGRn0) causes the reload counter to start counting. ● Restart The reload counter restarts under the following conditions: For both transmit/reception reload counters • UART programmable reset (SMR:UPCL bit) • Programmable restart (SMR:REST bit) For reception reload counter • Detection of the falling edge of the start bit in asynchronous mode CM44-10148-4E FUJITSU MICROELECTRONICS LIMITED 483 CHAPTER 19 LIN-UART 19.6 MB90950 Series Two reload counters restart at the next clock cycle when the REST bit in the serial mode register (SMR) is set to "1". This function enables the transmit reload counter to be used as a simple timer. Figure 19.6-3 shows an example of using this function (when reload value is 100). Figure 19.6-3 Example of Using a Simple Timer by Restarting the Reload Timer Machine clock Clock output of reload counter REST Reload counter 37 36 35 100 99 98 97 96 95 94 93 92 91 90 89 88 87 BGRn0/BGRn1 read 90 Data bus : don't care The number of machine cycles "cyc" after restart in this example is obtained by the following expression. cyc = v - c + 1 = 100 - 90 + 1 = 11 v: Reload value, c: Reload counter value Note: The reload counters also restart when the UART is reset by writing "1" to the SMR:UPCL bit. • Automatic restart (reception reload counter only) The reception reload counter is restarted when the falling edge of the start bit is detected in asynchronous mode. This is the function to synchronize the reception shift register with the reception data. ● Clearing the counter When a reset occurs, the reload values in the baud rate generator registers (BGRn1, BGRn0) and the reload counter are cleared to "00H", and the reload counter halts. Although the counter value is temporarily cleared to "00H" by the LIN-UART reset (writing "1" to SMR:UPCL), the reload counter restarts since the reload value is retained. The counter value is not cleared to "00H" by the restart setting (writing "1" to SMR:REST), and the reload counter restarts. 484 FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 19 LIN-UART 19.7 MB90950 Series 19.7 Operation of LIN-UART LIN-UART operates in mode 0 for bidirectional serial communication, in mode 1 for master/slave multiprocessor communication, and in modes 2 and 3 for master/slave bidirectional communication. ■ Operation of LIN-UART ● Operating mode The LIN-UART has four operation modes (0 to 3), allowing the connections and the data transfer methods between CPUs to be selected as listed in Table 19.7-1. Table 19.7-1 LIN-UART Operating Modes Data length Operating mode No parity 0 Normal mode 1 Multiprocessor mode 2 Normal mode 3 LIN mode With parity 7 bits or 8 bits 7 bits or 8 bits + 1* Stop bit length Data bit format 1 bit or 2 bits LSB first MSB first Asynchronous — 8 bits 8 bits Synchronization method — Asynchronous Synchronous None, 1 bit, 2 bits Asynchronous 1 bit LSB first —: Unavailable setting *: "+1" is the address/data selection bit (A/D) used for communication control in multiprocessor mode. Note: Both master and slave operation are supported in a system with master/slave connection in mode 1. In mode 3, the communication format is fixed to 8N1, LSB first. When the mode is switched, the UART stops all transitions and receptions and waits for the next operation. ■ Inter-CPU Connection Method You can select either external clock 1-to-1 connection (normal mode) or master/slave connection (multiprocessor mode). In either method, data length, parity setting, synchronization type must be the same between all CPUs and thus the operating mode must be selected as follows. • 1-to-1 connection: Two CPUs must use the same method as in either operating mode 0 or 2. Select the operating mode 0 for asynchronous method or the operating mode 2 for synchronous method. Also, for the operating mode 2, set one CPU as the master and the other as the slave. • Master/slave connection: Select operating mode 1. Use the system as a master/slave system. CM44-10148-4E FUJITSU MICROELECTRONICS LIMITED 485 CHAPTER 19 LIN-UART 19.7 MB90950 Series ■ Synchronous Method In asynchronous method, the reception clock is synchronized with the falling edge of the reception start bit. In synchronous method, it can be synchronized by the master clock signal or the clock signal generated in master operation. ■ Signaling NRZ (Non Return to Zero). ■ Enabling Transmission/Reception The LIN-UART uses the SCR:TXE bit and the SCR:RXE bit to control transmission and reception, respectively. To disable transmission or reception, follow the procedure described below. • If the reception is in progress, wait until the reception is completed, read the reception data register (RDR), and then disable the reception. • If the transmission is in progress, wait until the transmission is completed, and then disable the transmission. 486 FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 19 LIN-UART 19.7 MB90950 Series 19.7.1 Operation of Asynchronous Modes (Operation Modes 0, 1) When LIN-UART is used in operating mode 0 (normal mode) or operating mode 1 (multiprocessor mode), the transfer method is asynchronous. ■ Operation of Asynchronous Mode ● Transmit/reception data format Transmit/reception data always begins with a start bit ("L" level) followed by transmission/reception for a specified data bit length, and ends with at least one stop bit ("H" level). The bit transfer direction (LSB first or MSB first) is determined by the BDS bit in the serial status register (SSR). When a parity is used, the parity bit is always placed between the last data bit and the first stop bit. In operating mode 0, select 7-bit or 8-bit for the data length. You can select whether or not to use a parity. Also, the stop bit length (1 or 2) can be selected. In operating mode 1, the data length is 7-bit or 8-bit, the parity is not added, and the address/data bit is added. The stop bit length (1 or 2) can be selected. The bit length of transmit/reception frame is calculated as follows: Length = 1 + d + p + s (d = Number of data bits [7 or 8], p = parity [0 or 1], s = Number of stop bits [1 or 2]) Figure 19.7-1 shows the data format in asynchronous mode. CM44-10148-4E FUJITSU MICROELECTRONICS LIMITED 487 CHAPTER 19 LIN-UART 19.7 MB90950 Series Figure 19.7-1 Transmit/Reception Data Format (Operating Modes 0, 1) [Operating mode 0] ST D0 ST D0 D1 D2 D3 D4 D5 D6 D7 SP SP P: Not used D1 D2 D3 D4 D5 D6 D7 SP Data 8-bit ST D0 D1 D2 D3 D4 D5 D6 D7 P SP SP P: Used ST D0 D1 D2 D3 D4 D5 D6 D7 ST D0 D1 D2 D3 D4 D5 D6 SP SP ST D0 D1 D2 D3 D4 D5 D6 SP ST D0 D1 D2 D3 D4 D5 D6 P SP P: Not used Data 7-bit P SP SP P: Used ST D0 D1 D2 D3 D4 D5 D6 P SP ST D0 D1 D2 D3 D4 D5 D6 D7 A/D SP SP ST D0 D1 D2 D3 D4 D5 D6 D7 A/D SP ST D0 D1 D2 D3 D4 D5 D6 A/D SP SP [Operating mode 1] Data 8-bit Data 7-bit ST D0 ST SP P A/D D1 D2 D3 D4 D5 D6 A/D SP : Start bit : Stop bit : Parity bit : Address/data bit Note: When the BDS bit in the serial status register (SSR) is set to "1" (MSB first), the bits are processed in the order of D7, D6, … D1, D0 (P). ● Transmission If the transmit data register empty flag bit (TDRE) in the serial status register (SSR) is "1", transmit data can be written into the transmit data register (TDR). Writing data sets the TDRE flag to "0". If transmission is enabled (TXE in the serial control register (SCR) is set to 1) at this time, the data is written to the transmit shift register and the transmission is started sequentially from the start bit in the next serial clock cycle. An interrupt is generated if the TDRE flag is set when the transmit interrupt is enabled (TIE=1). Care must be taken that as the TDRE initial value is "1", an interrupt is generated immediately after "1" is written to TIE in that state. 488 FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 19 LIN-UART 19.7 MB90950 Series When the data length is set to 7-bit (CL=0), the MSB in the TDR is an unused bit regardless of the transfer direction selection bit (BDS) setting (LSB first or MSB first). Note: Since the initial value of transmit data empty flag bit (SSR:TDRE) is "1", an interrupt is generated as soon as transmit interrupts are enabled (SSR:TIE=1). ● Reception The reception is performed when reception is enabled (SCR:RXE=1). When the start bit is detected, 1 frame data is received according to the data format defined in the serial control register (SCR). If an error occurs, the error flag (SSR:PE, ORE, FRE) is set. After the reception of the 1 frame data is completed, the received data is transferred from the reception shift register to the reception data register (RDR), and the reception data register full flag bit (SSR:RDRF) is set to "1". If the reception interrupt request is enabled (SSR:RIE=1) at this time, a reception interrupt request is output. To read the received data, check the error flag status after 1 frame data reception is completed and read the received data from the reception data register (RDR) if the reception is normal. If a reception error occurs, perform error processing. When the received data is read, the reception data register full flag bit (SSR:RDRF) is cleared to "0". When the data length is set to 7-bit (CL=0), the MSB in the TDR is an unused bit regardless of the transfer direction select bit (BDS) setting (LSB first or MSB first). Note: Data in the reception data register (RDR) becomes valid when the reception data register full flag bit (SSR:RDRF) is set to "1" and no error occurs (SSR:PE, ORE, FRE=0). ● Clock to be used Internal or external clock is used. For the baud rate, select the baud rate generator (SMR:EXT = 0 or 1, OTO = 0). ● Stop bit You can select 1 or 2 stop bits at transmission. When 2 bits of the stop bit are selected, both of the stop bits are detected during reception. When the first stop bit is detected, the reception data register full flag (SSR:RDRF) is set to "1". When no start bit is detected after that, the reception bus idle flag (ECCR:RBI) is set to "1", indicating that the reception is not performed. ● Error detection In mode 0, parity, overrun, and frame errors can be detected. In mode 1, overrun and frame errors can be detected. Parity errors, on the other hand, cannot be detected. CM44-10148-4E FUJITSU MICROELECTRONICS LIMITED 489 CHAPTER 19 LIN-UART 19.7 MB90950 Series ● Parity You can specify whether or not to add (at transmission) and detect (at reception) a parity bit. The parity enable bit (SCR:PEN) can be used to determine whether or not to use a parity; the parity selection bit (SCR:P) can be used to select the odd or even parity. In operating mode 1, the parity cannot be used. Figure 19.7-2 Transmission Data when Parity is Enabled SIN ST SP 1 0 1 1 0 0 0 0 0 SOT ST Parity error occurs in even parity during reception (SCR:P = 0) SP Transmission of even parity (SCR:P = 0) SP Transmission of odd parity (SCR:P = 1) 1 0 1 1 0 0 0 0 1 SOT ST 1 0 1 1 0 0 0 0 0 Data Parity ST: Start bit, SP: Stop bit, Parity used (PEN = 1) Note: In operating mode 1, the parity cannot be used. ● Data signaling NRZ data format. ● Data transfer method LSB first or MSB first can be selected for the data bit transfer method. 490 FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 19 LIN-UART 19.7 MB90950 Series 19.7.2 Operation of Synchronous Mode (Operating Mode 2) When LIN-UART is used in operating mode 2 (normal mode), the transfer method is clock synchronous. ■ Operation of Synchronous Mode (Operating Mode 2) ● Transmit/reception data format In synchronous mode, you can transmit and receive 8-bit data and select whether or not to include the start bit and stop bit (ECCR:SSM). When the start/stop bit is included (ECCR:SSM = 1), you can select whether or not to include the parity bit (SCR:PEN). Figure 19.7-3 shows the data format in synchronous mode. Figure 19.7-3 Transmit/Reception Data Format (Operating Mode 2) Transmit/reception data (ECCR:SSM=0,SCR:PEN=0) D0 D1 D2 D3 D4 D5 D6 D7 * Transmit/reception data (ECCR:SSM=1,SCR:PEN=0) ST D0 D1 D2 D3 D4 D5 D6 D7 SP Transmit/reception data (ECCR:SSM=1,SCR:PEN=1) ST D0 P SP * D1 D2 D3 D4 D5 D6 D7 SP SP *: When 2 stop bits are set (SCR:SBL = 1) ST: Start bit, SP: Stop bit, P: Parity bit, LSB first ● Clock inversion function When the SCES bit in the extended status control register (ESCR) is "1", the serial clock is inverted. In slave mode, the LIN-UART samples data at the falling edge of the received serial clock. Note that, in master mode, the mark level is set to "0" when the SCES bit is "1". Figure 19.7-4 Transmit Data Format During Clock Inversion Transmit/reception clock (SCES = 0, CCO = 0): Mark level Transmit/reception clock (SCES = 1, CCO = 0): Mark level Transmit/reception data (SSM=1) (No parity, 1 stop bit) ST SP Data frame ● Start/stop bit When the SSM bit in the extended communication control register (ECCR) is "1", the start and stop bits are added as in asynchronous mode. CM44-10148-4E FUJITSU MICROELECTRONICS LIMITED 491 CHAPTER 19 LIN-UART 19.7 MB90950 Series ● Clock supply In clock synchronous mode (normal), the number of the transmit/reception bits must be equal to the number of the clock cycles. When the start/stop bit is enabled, the number of the added start/stop bits must be equal, as well. When the serial clock output is enabled (SMR:SCKE=1) in master mode (ECCR:MS=0), a synchronous clock is output automatically at transmission/reception. When the serial clock output is disabled (SMR:SCKE=0) or the slave mode is selected (ECCR:MS=1), the clock for each bit of transmit/reception data must be supplied from the outside. The clock signal must remain at the mark level as long as it is irrelevant to transmission/reception. Setting the SCDE bit in the ECCR to "1", a delayed transmit clock is output as shown in Figure 19.7-5. This function is required when the receiving device samples data at the rising or falling edge of the clock. Figure 19.7-5 Transmission Clock Delay (SCDE=1) Write transmit data Reception data sample edge (SCES = 0) Transmit/reception clock (normal) Mark level Transmit/reception clock (SCDE=1) Transmit/reception data Mark level Mark level 0 1 1 LSB 0 1 0 Data 0 1 MSB When the SCES bit in the extended status register (ESCR) is "1", the LIN-UART clock is inverted, and received data is sampled at the falling edge of the clock. At this time, the value of the serial data must be enabled at the timing of the clock falling edge. When the CCO bit in the ESCR is "1", the serial clock output from the SCKn pin is supplied continuously in master mode. In this mode, add the start/stop bit (SSM=1) in order to clarify the beginning and end of the data frame. Figure 19.7-6 shows the operation of this function. Figure 19.7-6 Continuous Clock Supply (Mode 2) Transmit/reception clock (SCES = 0, CCO = 1): Transmit/reception clock (SCES = 1, CCO = 1): Transmit/reception data (SSM=1) (No parity, 1 stop bit) ST SP Data frame ● Error detection When the start/stop bits are disabled (ECCR:SSM=0), only overrun errors are detected. 492 FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 19 LIN-UART 19.7 MB90950 Series ● Communication settings for synchronous mode To communicate in synchronous mode, the following settings are required. • Baud rate generator register (BGRn0/BGRn1) Set the dedicated baud rate reload counter to a required value. • Serial mode register (SMR) MD1, MD0 : "10B" (Mode 2) SCKE : "1" . . . . . Use the dedicated baud rate reload counter. "0" . . . . . Input external clock. SOE : "1" . . . . . Enable transmission/reception. "0" . . . . . Enable reception only. • Serial control register (SCR) RXE, TXE : Set "1" to either one of them. A/D : The value of this bit is disabled, as the address/data format selection function cannot be used. CL : This bit is set to 8-bit length automatically, and its value is disabled. CRE : "1" . . . . . The error flag is cleared, and reception is suspended. --- For SSM=0: PEN, P, SBL: Since not used, parity bit and stop bit are disabled. --- For SSM=1: PEN : "1" . . . . . . . Add/detect parity bit, "0" . . . . . . . Not use parity bit P "0" . . . . . . . Odd parity : "1" . . . . . . . Even parity, SBL : "1" . . . . . . . Stop bit length 2, "0" . . . . . . . Stop bit length 1 • Serial status register (SSR) BDS: "0" . . . . . . . LSB first, "1" . . . . . . . MSB first RIE : "1" . . . . . . . Enable reception interrupt, "0" . . . . . . . Disable reception interrupt TIE : "1" . . . . . . . Enable transmit interrupt, "0" . . . . . . . Disable transmit interrupt • Extended communication control register (ECCR) SSM : "0" . . . . . . . Not use start/stop bit (normal) "1" . . . . . . . Use start/stop bit (extended function) MS : "0" . . . . . . . Master mode (serial clock output) "1" . . . . . . . Slave mode (input serial clock from master device) Note: To start communication, write data into the transmit data register (TDR). To only receive data, disable the serial output (SMR:SOE=0), and then write dummy data into the TDR. Enabling continuous clock and start/stop bit allows bidirectional communication as in asynchronous mode. CM44-10148-4E FUJITSU MICROELECTRONICS LIMITED 493 CHAPTER 19 LIN-UART 19.7 19.7.3 MB90950 Series Operation of LIN Function (Operating Mode 3) In operating mode 3, the LIN-UART works as the LIN master and the LIN slave. In operating mode 3, the data format is set to 8N1-LSB first. ■ Asynchronous LIN Mode Operation ● Operation as LIN master In LIN mode, the master determines the baud rate for the entire bus, and the slave synchronizes to the master. The baud rate is fixed to the requested value when the master starts operating after the initial setting. Writing "1" to the LBR bit in the extended communication control register (ECCR) outputs 13 to 16 bits at the "L" level from the SOTn pin. These bits are the LIN Synch break indicating the beginning of a LIN message. The TDRE flag bit in the serial status register (SSR) is set to "0". After the break, it is set to "1" (initial value), if no valid data is contained in the transmit data register (TDR). If the TIE bit in SSR is "1" at this time, a transmit interrupt is output. The length of the LIN break transmitted is set by the LBL0/LBL1 bits in ESCR as in the following table. Table 19.7-2 LIN Break Length LBL0 LBL1 Break length 0 0 13 bits 1 0 14 bits 0 1 15 bits 1 1 16 bits Synch field is transmitted as byte data 0x55 following the LIN break. 0x55 can be written to the TDR after the LBR bit is set to "1" even if the TDRE flag is "0". ● Operation as LIN slave In LIN slave mode, the LIN-UART must synchronize to the baud rate for the master. The LIN-UART generates a reception interrupt when LIN break interrupt is enabled (LBIE=1) even though reception is disabled (RXE=0). The LBD bit in the ESCR is set to "1" at this time. Writing "0" to the LBD bit clears the reception interrupt request flag. For calculation of the baud rate, the following example shows the operation of the UART0. When the UART0 detects the first falling edge of Synch field, the internal signal to be input to the input capture (ICU0) is set to "H" to start ICU0. The internal signal should be "L" at the fifth falling edge. ICU0 must be set to LIN mode (ICE01). Also, ICU0 interrupts must be enabled and set for the detection at both edges (ICS01). The time for which the input signal to ICU0 is the value obtained by multiplying the baud rate by 8. The baud rate setting value is calculated by the following expressions. 494 FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 19 LIN-UART 19.7 MB90950 Series When the free-run timer is not overflowing: BGR value = { (b - a) × Fe / (8 × φ) } -1 When the free-run timer is overflowing: BGR value = { (max + b - a) × Fe / (8 × φ) } -1 max : Maximum value of free-run timer a : ICU data register value after the 1st interrupt b : ICU data register value after the 2nd interrupt φ : Machine clock frequency (MHz) Fe : External clock frequency (MHz) Calculation based on the internal baud rate generator in use (EXT=0), and Fe=φ Note: Do not set the baud rate if the new BGR value calculated based on Synch field as above in LIN slave mode involves an error from the baud rate over ±15%. For the relationship between the UART and ICU, see Section "12.5 Operations of 16-bit Free-run Timer" and Section "12.6 Input Capture Operations". ● LIN Synch break detection interrupt and flag The LIN break detection (LBD) flag in ESCR is set to "1" when the LIN Synch break is detected in slave mode. When the LIN break interrupt is enabled (LBIE=1), an interrupt is generated. Figure 19.7-7 Timing of LIN Synch Break Detection and Flag Set Serial clock cycle # 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Serial clock Serial input (LIN bus) FRE (RXE=1) LBD (RXE=0) Reception interrupt occurs when RXE=1 Reception interrupt occurs when RXE=0 The above diagram shows the timing of the LIN Synch break detection and flag. Since the data framing error (FRE) flag bit in SSR generates a reception interrupt 2 bits earlier than a LIN break interrupt (for 8N1), set the RXE to "0" when a LIN break is used. The LIN Synch break detection works only in operating mode 3. CM44-10148-4E FUJITSU MICROELECTRONICS LIMITED 495 CHAPTER 19 LIN-UART 19.7 MB90950 Series Figure 19.7-8 shows the beginning of a typical LIN message and the UART operation. Figure 19.7-8 UART Operation in LIN Slave Mode Serial clock Serial input (LIN bus) LBR cleared by CPU LBD ICU input (LSYN) Synch break (when set to 14 bits) Synch field ● LIN bus timing Figure 19.7-9 LIN Bus Timing and UART Signals Previous serial clock No clock (Calculation frame) Newly calculated serial clock ICU count LIN bus (SIN) RXE LBD (IRQ0) LBIE ICU input (LSYN) IRQ(ICU) RDRF (IRQ0) RIE RDR read by CPU Reception interrupt enabled LIN break starts LIN break detected, interrupt generated IRQ cleared by CPU (LBD->0) LBIE disabled IRQ (ICU) IRQ cleared: ICU started IRQ(ICU) IRQ cleared: Baud rate calculated and set Reception enabled Falling edge of start bit 1 byte of reception data saved to RDR RDR read by CPU 496 FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 19 LIN-UART 19.7 MB90950 Series 19.7.4 Serial Pin Direct Access Transmission pin (SOTn) or reception pin (SINn) can be accessed directly. ■ LIN-UART Pin Direct Access The LIN-UART allows the programmer to directly access the serial I/O pins. The status of the serial input pin (SINn) can be read by using the serial I/O pin direct access bit (ESCR:SIOP). You can set the value of the serial output pin (SOTn) arbitrarily when the serial output is enabled (SMR:SOE=1) after direct write to the serial output pin (SOTn) is enabled (ESCR:SOPE=1), and then "0" or "1" is written to the serial I/O pin direct access bit (ESCR:SIOP). In LIN mode, this feature is used for reading transmitted data or for error handling when a LIN bus line signal is physically incorrect. Notes: • Direct access is allowed only when transmission is not in progress (the transmit shift register is empty). • Before enabling transmission (SMR:SOE=1), write a value to the serial output pin direct access bit (ESCR:SIOP). This prevents a signal of an unexpected level from being output since the SIOP bit holds a previous value. • While the value of the SINn pin is read by normal read, the value of the SOTn pin is read for the SIOP bit by the RMW instructions. CM44-10148-4E FUJITSU MICROELECTRONICS LIMITED 497 CHAPTER 19 LIN-UART 19.7 19.7.5 MB90950 Series Bidirectional Communication Function (Normal Mode) Normal serial bidirectional communication can be performed in operation mode 0 or 2. Asynchronous communication can be selected in operating mode 0, while synchronous communication can be selected in operating mode 2. ■ Bidirectional Communication Function To operate the LIN-UART in normal mode (operating mode 0 or 2), the settings shown in Figure 19.7-10 are required. Figure 19.7-10 Settings of LIN-UART Operating Modes 0 and 2 bit15 bit14 bit13 bit12 bit11 bit10 bit9 SCRn, SMRn PEN P bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 SBL CL A/D CRE RXE TXE MD1 MD0 OTO EXT REST UPCL SCKE SOE Mode 0 Mode 2 SSRn, TDRn/RDRn PE ORE FRE RDRF TDRE BDS RIE TIE Mode 0 Mode 2 ESCRn, ECCRn LBIE LBD LBL1 LBL0 SOPE SIOP CCO SCES Set conversion data (during writing) Retain reception data (during reading) LBR MS SCDE SSM RBI TBI Mode 0 Mode 2 : Used bit : Unused bit : Set "1" : Set "0" : Used when SSM = 1 (Synchronous start/stop bit mode) : Bit automatically set correctly n = 0, 1, 2, 3, 4, 5, 6 ● Inter-CPU connection For bidirectional communication, two CPUs are interconnected as shown in Figure 19.7-11. Figure 19.7-11 Connection Example of Bidirectional Communication in LIN-UART Mode 2 SOT SOT SIN Output Input SCK SIN SCK CPU-1 (Master) CPU-2 (Slave) ● Communication procedure The communication is started from transmitting end at arbitrary timing when data is ready to be transmitted. The receiving end returns ANS (per 1 byte in this example) regularly after the transmitted data is received. Figure 19.7-12 shows an example of bidirectional communication flowchart. 498 FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 19 LIN-UART 19.7 MB90950 Series Figure 19.7-12 Example of Bidirectional Communication Flowchart (Transmitting end) (Receiving end) Start Start Set operating mode (0 or 2) Set operating mode (Match with the transmitting end) Communicate with 1 byte data set in TDR Data transmission NO NO Read and process received data CM44-10148-4E YES Received data exists YES Received data exists Read and process received data Data transmission Transmit 1 byte data (ANS) FUJITSU MICROELECTRONICS LIMITED 499 CHAPTER 19 LIN-UART 19.7 19.7.6 MB90950 Series Master/Slave Mode Communication Function (Multiprocessor Mode) Operating mode 1 allows communication between multiple CPUs connected in master/ slave mode. It can be used as a master or slave. ■ Master/Slave Mode Communication Function To operate the LIN-UART in multiprocessor mode (operating mode 1), the settings shown in Figure 19.713 are required. Figure 19.7-13 Settings of LIN-UART Operating Mode 1 bit15 bit14 bit13 bit12 bit11 bit10 SCRn, SMRn PEN P SBL CL bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 A/D CRE RXE TXE MD1 MD0 OTO EXT REST UPCL SCKE SOE Mode 1 SSRn, TDRn/RDRn PE ORE FRE RDRF TDRE BDS RIE TIE Set conversion data (during writing) Retain reception data (during reading) Mode 1 ESCRn, ECCRn LBIE LBD LBL1 LBL0 SOPE SIOP CCO SCES LBR MS SCDE SSM RBI TBI Mode 1 : Used bit : Unused bit : Set "1" : Set "0" : Bit automatically set correctly n = 0, 1, 2, 3, 4, 5, 6 ● Inter-CPU connection For master/slave mode communication, a communication system is configured by connecting between 1 master CPU and multiple slave CPUs with 2 common communication lines, as shown in Figure 19.7-14. The LIN-UART can be used as the master or slave. Figure 19.7-14 Connection Example of LIN-UART Master/Slave Mode Communication SOT SIN Master CPU SOT SIN Slave CPU#0 500 SOT SIN Slave CPU#1 FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 19 LIN-UART 19.7 MB90950 Series ● Function selection For master/slave mode communication, select the operating mode and the data transfer method, as shown in Table 19.7-3. Table 19.7-3 Selection of Master/Slave Mode Communication Function Operating mode Master CPU Address Transmission/ reception Data transmission/ reception Mode 1 (A/D bit transmission/ reception) Slave CPU Mode 1 (A/D bit transmission/ reception) Data Parity Synchronous method Stop bit Bit direction None Asynchronous 1 bit or 2 bits LSB first or MSB first A/D = 1 + 7- or 8-bit address A/D = 1 + 7- or 8-bit data ● Communication procedure Communication is started by transmitting address data from the master CPU. The address data, whose A/D bit is set as "1", determines the slave CPU to be the destination. Each slave CPU checks address data by using a program, and communicates with the master CPU when the data matches an assigned address. Figure 19.7-15 shows a flowchart for master/slave mode communication (multiprocessor mode). CM44-10148-4E FUJITSU MICROELECTRONICS LIMITED 501 CHAPTER 19 LIN-UART 19.7 MB90950 Series Figure 19.7-15 Master/Slave Mode Communication Flowchart (Master CPU) (Slave CPU) Start Start Set to operating mode 1 Set to operating mode 1 Set SINn pin to serial data input Set SOTn pin to serial data output Set SINn pin to serial data input Set SOTn pin to port input Set 7 or 8 data bits Set 1 or 2 stop bits Set 7 or 8 data bits Set 1 or 2 stop bits Set "1" in A/D bit Enable transmission/ reception Enable transmission/ reception Receive bytes Transmit address to slave A/D bit = 1 NO YES Match with slave address Set "0" in A/D bit YES Communicate with master CPU Communicate with slave CPU Terminate communication? NO Terminate communication? NO NO YES YES Communicate with another slave CPU NO YES Disable transmission/ reception End 502 FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 19 LIN-UART 19.7 MB90950 Series 19.7.7 LIN Communication Function For LIN-UART communication, a LIN device can be used in the LIN master system or the LIN slave system. ■ LIN Master/Slave Mode Communication Function Figure 19.7-16 shows the required settings for the LIN communication mode of LIN-UART (operating mode 3). Figure 19.7-16 Settings of LIN-UART Operating Mode 3 SCRn, SMRn PEN P SBL CL A/D CRE RXE TXE MD1 MD0 OTO EXT REST UPCLSCKE SOE Mode 3 SSRn, TDRn/RDRn PE ORE FRE RDRFTDRE BDS RIE TIE Set conversion data (during writing) Retain reception data (during reading) Mode 3 ESCRn, ECCRn LBIE LBD LBL1 LBL0 SOPE SIOP CCO SCES LBR MS SCDESSM RBI TBI Mode 3 : Used bit : Unused bit : Set "1" : Set "0" : Bit automatically set correctly n = 0, 1, 2, 3, 4, 5, 6 ● LIN device connection Figure 19.7-17 shows the communication system between 1 LIN master and LIN slave. The LIN-UART can serve as the LIN master or LIN slave. Figure 19.7-17 Example of LIN Bus System Communication SOT SOT LIN bus SIN LIN master CM44-10148-4E SIN Transceiver Transceiver FUJITSU MICROELECTRONICS LIMITED LIN slave 503 CHAPTER 19 LIN-UART 19.7 19.7.8 MB90950 Series Example Flowchart of LIN-UART LIN Communication (Operating Mode 3) This section shows example flowcharts of LIN-UART LIN communication. ■ LIN Master Device Figure 19.7-18 LIN Master Flowchart Start Initial settings: Set to operating mode 3 Enable serial data output, Set baud rate, Set Synch break length TXE = 1, TIE = 0, RXE = 1, RIE = 1 NO Message? (Reception) YES YES Wake up? (0x80 reception) NO Receive Data field? RDRF = 1 Reception interrupt RXE = 0 Enable Synch break interrupts Transmit Synch break ECCR: LBR = 1 Transmit Synch field: TDR = 0x55 (Transmission) RDRF = 1 Reception interrupt Receive Data 1*1 YES NO Set transmit data 1, TDR = Data 1, Enable transmit interrupts TDRE = 1 Transmit interrupt Receive Data N*1 Set transmit data N, TDR = Data N, Disable transmit interrupts LBD = 1 Synch break interrupt RDRF = 1 Reception interrupt Enable reception LBD = 0 Disable Synch break interrupts Receive Data 1 *1 Read Data 1 RDRF = 1 Reception interrupt RDRF = 1 Reception interrupt Receive Synch field *1 Set Identify field: TDR = lD Receive Data N *1 Read Data N RDRF = 1 Reception interrupt Receive ID field*1 No error? NO Process error*2 YES *1: Process an error if it occurs. *2: • If the FRE or ORE flag is set "1", write "1" to the SCR:CRE bit to clear the error flag. • If the ESCR:LBD bit is set to "1", execute the UART reset. Note: Detect an error in each process and handle it appropriately. 504 FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 19 LIN-UART 19.7 MB90950 Series ■ LIN Slave Device Figure 19.7-19 LIN Slave Flowchart Start Initial settings: Set to operating mode 3 Enable serial data output TXE = 1, TIE = 0, RXE = 0, RIE = 1 Connect UART with ICU Disable reception Enable ICU interrupts Enable Synch break interrupts LBD = 1 Synch break interrupt Clear Synch break detection ESCR: LBD = 0 Disable Synch break interrupts ICU interrupt (Reception) YES Receive Data field? NO (Transmission) RDRF = 1 Reception interrupt Set transmit data 1 TDR = Data 1 Enable transmit interrupts Receive Data 1*1 RDRF = 1 Reception interrupt TDRE = 1 Transmit interrupt Receive Data N*1 Set transmit data N, TDR = Data N, Disable transmit interrupts Read ICU data Clear ICU interrupt flag ICU interrupt Disable reception RDRF = 1 Reception interrupt Read ICU data Adjust baud rate Enable reception Clear ICU interrupt flag Disable ICU interrupts Receive Data 1 *1 Read Data 1 RDRF = 1 Reception interrupt RDRF = 1 Reception interrupt Receive Data N *1 Read Data N Disable reception Receive Identify field*1 No error? NO Process error*2 YES Sleep mode? NO YES Wake-up received? *1: Process an error if it occurs. *2: • If the FRE or ORE flag is set "1", write "1" to the SCR:CRE bit to clear the error flag. • If the ESCR:LBD bit is set to "1", execute the UART reset. Note: Detect an error in each process and handle it appropriately. CM44-10148-4E YES NO Wake-up transmitted? YES NO Transmit wake-up code FUJITSU MICROELECTRONICS LIMITED 505 CHAPTER 19 LIN-UART 19.8 19.8 MB90950 Series Notes on Using LIN-UART This section shows notes on using the LIN-UART. ■ Notes on Using LIN-UART ● Enabling operation The LIN-UART has the TXE (transmission) and RXE (reception) enable bit in the serial control register (SCR) for transmission and reception, respectively. As both transmission and reception are disabled by default (initial value), these operations must be enabled before transfer. Also, you can disable these operations to stop transfer as required. ● Setting communication mode The communication mode must be set while the LIN-UART is stopped. If the mode is set during transmission/reception, the transmitted/received data is not guaranteed. ● Timing of enabling transmit interrupts Since the default (initial) value of the transmit data empty flag bit (SSR:TDRE) is "1" (no transmit data, transmit data write enabled), a transmit interrupt request is generated immediately when transmit interrupt request is enabled (SSR:TIE=1). To prevent this, be sure to set the transmit data before setting the TIE flag to "1". ● Changing operation setting It is recommended to reset the LIN-UART after changing its settings, such as adding the start/stop bit or changing the data format. The correct operation settings are not guaranteed even if you reset the LIN-UART (SMR:UPCL=1) at the same time as setting the LIN-UART serial mode register (SMR). Therefore, it is recommended to reset the LIN-UART (SMR:UPCL=1) once again, after setting the bit in LIN-UART serial mode register (SMR). ● Using LIN function Although the LIN functions are available in operating mode 3, the LIN format is automatically set in mode 3 (8-bit data, no parity, 1 stop bit, LSB first). While the length of LIN break transmit bit is variable, the detection bit length is fixed to 11 bits ● Setting LIN slave When starting LIN slave mode, be sure to set the baud rate before receiving the LIN Synch break in order to ensure that at least 13 bits of the LIN Synch break is detected. 506 FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 19 LIN-UART 19.8 MB90950 Series ● Program compatibility Although the LIN-UART resembles the old FJ-UART, there is no program compatibility between them. Even when the same programming pattern is used, the register structure is different. Moreover, a reload value is currently used to determine the baud rate setting, rather than selecting a preset value. ● Bus idle function The bus idle function is not available in synchronous mode 2, when SSM is 0. ● A/D bit (Serial control register (SCR): Address/data format selection bit) • The A/D bit is used to select the address/data for transmission in write operation, and to read the A/D bit received last in read operation. Internally, the A/D bit values for transmission and reception are stored in separate registers. The transmit A/D bit value is read when RMW instructions are used. Otherwise, the received A/D data is read. • At transmission, when the TDRE bit changes from "0" to "1", the transmit A/D bit is also loaded to the transmit shift register along with the data in the transmit data register (TDR). Therefore, set the transmit A/D bit before writing to the transmit data register (TDR). ● LIN-UART software reset Execute the LIN-UART software reset (SMR:UPCL=1) when the TXE bit in the serial control register (SCR) is "0". ● Synch break detection In mode 3 (LIN mode), when serial input more than 11 bits is "0", the LBD bit in the extended status control register (ESCR) is set to "1" (Synch break detection) and the LIN-UART waits for the Synch field. As a result, when serial input more than 11 bits is "0" (except Synch break), the LIN-UART recognizes that the Synch break is input (LBD=1), and then waits for the Synch field. In this case, execute the LIN-UART reset (SMR: UPCL=1). CM44-10148-4E FUJITSU MICROELECTRONICS LIMITED 507 CHAPTER 19 LIN-UART 19.8 508 MB90950 Series FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 20 2 I C INTERFACE (400 kHz) This chapter explains the functions and operations of the high-speed I2C interface. 20.1 Overview of I2C Interface (400 kHz) 20.2 Registers of I2C Interface 20.3 Operations of I2C Interface 20.4 Programming Flowcharts CM44-10148-4E FUJITSU MICROELECTRONICS LIMITED 509 CHAPTER 20 I2C INTERFACE (400 kHz) 20.1 20.1 MB90950 Series Overview of I2C Interface (400 kHz) The I2C interface is a serial I/O port that supports internal IC BUS and operates as the master/slave devices on I2C bus. The MB90950 series provides two I2Cs. ■ Features of I2C Interface (400 kHz) The I2C interface (400 kHz) has the following features: • Master/slave sending and receiving function • Arbitration function • Clock synchronization function • General-purpose call addressing function • Transfer direction detection function • Function that generates and detects the re-activation condition • Bus error detection function • 7-bit master/slave addressing • 10-bit master/slave addressing • Interface for 7-bit and 10-bit slave address • Disabling of acknowledgement for slave address reception (only in master mode) • Address mask function to provide the interface for composite slave addresses (in 7-bit and 10-bit modes) • Transmission at up to 400 kbps • Built-in noise filters for SDA/SCL • Data reception at 400 kbps when the machine clock exceeds 6 MHz regardless of the prescaler setting • Generation of transfer interrupts and bus error interrupts • Lowering of speed by slave at the bit level and byte level The I2C interface does not support the SCL clock stretching at the bit level because the interface can receive the data in full scale at 400kbps when the machine clock exceeds 6 MHz regardless of the prescaler setting. However, the clock stretching is executed at the byte level when SCL becomes "L" during the interrupt (INT=1 in the IBCR register). ■ Block Diagram of I2C Interface Figure 20.1-1 shows a block diagram of the I2C interface (400 kHz). 510 FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 20 I2C INTERFACE (400 kHz) 20.1 MB90950 Series Figure 20.1-1 Block Diagram of I2C Interface (400 kHz) ICCR I2C enable EN ICCR 2 CS4 Clock division 1 3 4 5 ... 32 CS3 5 CS2 5 Synchronous Clock selector CS1 CS0 IBSR BB RSC LRB Clock division 2 (divided by 12) SCL duty cycle generator Shift clock generator Bus busy Repeat activation Bus observer Last bit Bus error Send/receive TRX Address data ADT Internal data bus AL Arbitration lost detector ICCR NSF Enable IBCR BER BEIE MCU IRQ Interrupt request INTE INT Noise filter SCL SDA SCL SDA IBCR SCC MSS ACK Activation Master ACK enable GC-ACK enable Activate-stop condition generator ACK generator GCAA 8 IBSR AAS IDAR 8 Slave General-purpose call GCA ISMK 7-bit mode enable ENSB ITMK 10-bit mode enable ENTB Reception address length RAL 10 Slave address comparator 7 10 ITBA ITMK 7 ISBA ISMK 10 10 7 7 CM44-10148-4E FUJITSU MICROELECTRONICS LIMITED 511 CHAPTER 20 I2C INTERFACE (400 kHz) 20.2 20.2 MB90950 Series Registers of I2C Interface This section explains the function of the registers used in the I2C interface. ■ Register List of I2C Interface Figure 20.2-1 shows a register list of the I2C interface. Figure 20.2-1 Register List of I2C Interface Bus control register (IBCR0/IBCR1) Address: bit 15 IBCR0: 007971H IBCR1: 007981H 14 13 12 11 10 9 8 BER BEIE SCC MSS ACK GCAA INTE INT R/W R/W W R/W R/W R/W R/W R/W IBCR0/IBCR1 Initial value 00000000B Bus status register (IBSR0/IBSR1) Address: bit 7 IBSR0: 007970H IBSR1: 007980H 6 5 BB RSC AL R R R 4 3 2 1 0 IBSR0/IBSR1 LRB TRX AAS GCA ADT Initial value R R R 00000000B 10 9 8 ITBAH0/ITBAH1 (upper) R R 10-bit slave address register (ITBA0/ITBA1) Address: bit 15 14 13 12 11 ITBAH0: 007973H ITBAH1: 007983H TA9 TA8 Initial value R/W R/W 00000000B Address: 0 6 5 4 3 2 1 bit 7 ITBAL0: 007972H TA7 TA6 TA5 TA4 TA3 TA2 TA1 TA0 ITBAL1: 007982H R/W R/W R/W R/W R/W R/W R/W R/W ITBAL0/ITBAL1 (lower) Initial value 00000000B 10-bit slave address mask register (ITMK0/ITMK1) Address: bit 15 ITMKH0: 007975H ITMKH1: 007985H Address: ITMKL0: 007974H ITMKL1: 007984H 14 13 12 11 10 9 8 ENTB RAL TM9 TM8 R/W R/W R/W R/W bit 7 6 5 4 3 2 1 0 ITMKH0/ITMKH1 (upper) Initial value 00111111B ITMKL0/ITMKL1 (lower) TM7 TM6 TM5 TM4 TM3 TM2 TM1 TM0 Initial value R/W R/W R/W R/W R/W R/W R/W R/W 11111111B 7-bit slave address register (ISBA0/ISBA1) Address: bit 7 ISBA0: 007976H ISBA1: 007986H R/W W R — 6 5 4 3 2 1 0 ISBA0/ISBA1 SA6 SA5 SA4 SA3 SA2 SA1 SA0 Initial value R/W R/W R/W R/W R/W R/W R/W 00000000B : Readable/writable : Write only : Read only : Undefined (Continued) 512 FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 20 I2C INTERFACE (400 kHz) 20.2 MB90950 Series (Continued) 7-bit slave address mask register (ISMK0/ISMK1) Address: bit 15 ISMK0: 007977H ISMK1: 007987H 14 13 12 11 10 9 8 ENSB SM6 SM5 SM4 SM3 SM2 SM1 SM0 R/W R/W R/W R/W R/W R/W R/W R/W ISMK0/ISMK1 Initial value 01111111B Data register (IDAR0/IDAR1) Address: IDAR0: 007978H IDAR1: 007988H bit 7 6 5 4 3 2 1 0 D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W IDAR0/IDAR1 Initial value 00000000B Clock control register (ICCR0/ICCR1) Address: ICCR0: 00797BH ICCR1: 00798BH bit 15 14 13 12 11 10 9 8 NSF EN CS4 CS3 CS2 CS1 CS0 R/W R/W R/W R/W R/W R/W R/W ICCR0/ICCR1 Initial value 00011111B R/W : Readable/writable — : Undefined CM44-10148-4E FUJITSU MICROELECTRONICS LIMITED 513 CHAPTER 20 I2C INTERFACE (400 kHz) 20.2 20.2.1 MB90950 Series Bus Status Register (IBSR0, IBSR1) This section explains the function of the bus status register (IBSR0, IBSR1). ■ Functions of the Bus Status Register (IBSR0, IBSR1) The bus status register (IBSR0, IBSR1) has the following functions: • Bus busy detection • Re-activation condition detection • Arbitration lost detection • Acknowledgement detection • Data transfer direction indication • Addressing detection as slave • General-purpose call address detection • Address data transfer detection ■ Bit Function of the Bus Status Register (IBSR0, IBSR1) This register is read-only. All bits of this register is controlled by hardware. All the bits are cleared when the interface is not enabled (EN=0 in ICCR). Figure 20.2-2 shows the bit configuration of the bus status register (IBSR0, IBSR1). 514 FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 20 I2C INTERFACE (400 kHz) 20.2 MB90950 Series Figure 20.2-2 Bit Configuration of Bus Status Register (IBSR0, IBSR1) Address: bit 7 IBSR0: 007970H IBSR1: 007980H 6 5 4 3 2 1 0 BB RSC AL LRB TRX AAS GCA ADT R R R R R R R R IBSR0/IBSR1 Initial value 00000000B bit0 ADT 0 1 Address data transfer flag bit Received data is not an address data (or the bus is free) Received data is an address data bit1 General call address flag bit GCA 0 No general-purpose call address is received as slave 1 General-purpose call address is received as slave bit2 AAS Addressed as slave bit 0 No addressing as slave 1 Received data is an address data bit3 TRX Transfer/receiver bit 0 Data transmission is not in progress 1 Data transmission is in progress bit4 LRB Last received bit 0 Reception is detected 1 Reception is not detected bit5 AL Arbitration lost flag bit 0 Arbitration lost is not detected 1 Arbitration lost is detected during master transmission bit6 RSC Repeated start condition flag bit 0 Re-activation condition is not detected 1 Re-activation condition is detected (bus busy) R : Read only bit7 BB Bus busy flag bit 0 Stop condition is detected (bus idle) 1 Activation condition is detected (bus busy) : Initial value CM44-10148-4E FUJITSU MICROELECTRONICS LIMITED 515 CHAPTER 20 I2C INTERFACE (400 kHz) 20.2 MB90950 Series Table 20.2-1 Functions of Bus Status Register (IBSR0, IBSR1) (1 / 2) Bit name Function bit7 BB: Bus busy flag bit This bit indicates the state of the I2C bus. "0": Stop condition is detected (bus idle) "1": Activation condition is detected (bus busy) This bit is set to "1" when the activation condition is detected. It is reset when the stop condition is detected. bit6 RSC: Repeated start condition flag bit This bit indicates the state of the re-activation condition. "0": Re-activation condition is not detected "1": Bus busy, re-activation condition is detected This bit is cleared when the address data transfer ends (ADT=0) or when the stop condition is detected. AL: Arbitration lost flag bit This bit indicates the state of the arbitration lost. "0": Arbitration lost is not detected "1": Arbitration lost occurs during master transmission This bit is cleared when writing "0" to the INT bit or "1" to the MSS bit of the IBCR register. Arbitration lost occurs if: • The transmission data does not match the data on the SDA line at the rising edge of SCL pin. • Another master generates a re-activation condition in the first bit of the data byte. • The interface cannot generate an activation or stop condition because the SCL pin line is driven to "L" by another slave device. LRB: Last received bit This bit is used to store an acknowledgement message from the receiving device to the transmitter. "0": Reception is detected "1": Reception is not detected This bit is changed if the hardware receives bit9 (response bit), and cleared if an activation or stop condition is detected. TRX: Transfer/receiver bit This bit indicates the transmission operation during the data transfer. "0": Data is not transmitted "1": Data is being transmitted • This bit is set to "1" if: - An activation condition occurs in master mode. - The first byte has been transferred, and read access is executed in slave mode, or the data is being sent in master mode. • This bit is set to "0" if: - The bus is idle (BB=0 in IBSR). - An arbitration lost occurs. - "1" is written to the SCC bit in the master interrupt status (MSS=1, INT=1). - The MSS bit is cleared in the master interrupt status (MSS=1, INT=1). - Interface is run in slave mode and the last transferred byte is not detected. - Interface is run in slave mode and the data is being received. - Interface is run in master mode and the data is being read from the slave. bit5 bit4 bit3 516 FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E MB90950 Series CHAPTER 20 I2C INTERFACE (400 kHz) 20.2 Table 20.2-1 Functions of Bus Status Register (IBSR0, IBSR1) (2 / 2) Bit name Function bit2 AAS: Addressed as slave bit This bit indicates the state of the slave addressing detection. "0": The interface is not specified as a slave for the address "1": The interface is specified as a slave for the address This bit is cleared when a (re-)activation or stop condition is detected. This bit is set when either 7-bit or 10-bit slave address or both of the slave addresses are detected. bit1 GCA: General call address flag bit This bit indicates the state of the general-purpose call address (0x00) reception. "0": General-purpose call address is not received as slave "1": General-purpose call address is received as slave This bit is cleared when a (re-)activation or stop condition is detected. ADT: Address data transfer flag bit This bit indicates the state of the address data transfer detection. "0": Received data is not an address data (or the bus is free) "1": Received data is an address data This bit is set to "1" if an activation condition is detected. It is cleared after the second byte if the 10-bit slave address header along with the write access is detected. Otherwise, it is cleared after the first byte. "After the first or second byte" means the following: • "0" is written to the MSS bit during master interrupt (MSS=1, INT=1 in IBCR). • "1" is written to the SCC bit during master interrupt (MSS=1, INT=1 in IBCR). • The INT bit is cleared. • All the bytes start to be transferred if the interface is not used as a master or slave for the current transfer. bit0 CM44-10148-4E FUJITSU MICROELECTRONICS LIMITED 517 CHAPTER 20 I2C INTERFACE (400 kHz) 20.2 20.2.2 MB90950 Series Bus Control Register (IBCR0, IBCR1) This section explains the function of the bus control register (IBCR0, IBCR1). ■ Functions of Bus Control Register (IBCR0, IBCR1) The bus control register (IBCR0, IBCR1) has the following functions: • Interrupt enable • Interrupt generation • Bus error detection • Re-activation condition generation • Master/slave mode selection • General-purpose call acknowledgement generation enable • Data byte acknowledgement generation enable ■ Bit Function of Bus Control Register (IBCR0, IBCR1) The write access to this register occurs only if INT=1 or the transfer is started. When the ACK bit or GCAA bit is changed, the bus error can occur. Therefore, user cannot perform the write access to this register during the transfer operation. All the bits except BER and BEIE are cleared if the interface is not enabled (EN=0 in ICCR). Figure 20.2-3 shows the bit configuration of the bus control register (IBCR0, IBCR1). 518 FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 20 I2C INTERFACE (400 kHz) 20.2 MB90950 Series Figure 20.2-3 Bit Configuration of Bus Control Register (IBCR0, IBCR1) bit 15 Address: IBCR0: 007971H IBCR1: 007981H 14 13 12 11 10 9 8 BER BEIE SCC MSS ACK GCAA INTE INT R/W R/W W R/W R/W R/W R/W R/W IBCR0/IBCR1 Initial value 00000000B bit8 INT 0 1 Interrupt flag bit See Table 20.2-2 bit9 Interrupt enable bit INTE Interrupt disable bit 0 Interrupt enable bit 1 bit10 GCCA 0 1 General call address acknowledge bit No acknowledgement occurs when a general-purpose call address byte is received Acknowledgement occurs when a general-purpose call address byte is received bit11 ACK 0 1 Data byte acknowledge bit No acknowledgement occurs when a data byte is received Acknowledgement occurs when a data byte is received bit12 Master/slave selection bit MSS Slave mode 0 1 Master mode (See Table 20.2-2 for details) bit13 SCC N/A 0 1 Start condition continue bit Repeated activation condition occurs during the master transfer bit14 Bus error interrupt enable bit BEIE Bus error interrupt disabled 0 Bus error interrupt enabled 1 bit15 BER R/W W : Readable/writable 0 : Write only 1 Bus error flag bit Writing Bus error interrupt is cleared N/A Reading No error is detected An error is detected : Initial value CM44-10148-4E FUJITSU MICROELECTRONICS LIMITED 519 CHAPTER 20 I2C INTERFACE (400 kHz) 20.2 MB90950 Series Table 20.2-2 Functions of Bus Control Register (IBCR0, IBCR1) (1 / 3) Bit name Function This bit is the bus error interrupt flag. The bit is set by hardware and cleared by user. For a read-modify-write access, "1" is always read. Write access "0": Bus error interrupt flag is cleared "1": N/A Read access "0": No bus error is detected "1": One of the following error states is detected: If this bit is set, the EN bit of the ICCR register is cleared. The I2C interface is stopped, and data transfer is halted. All the bits of the IBSR and IBCR registers except BER and BEIE are cleared. The BER bit must be cleared before the interface is enabled again. • This bit is set to "1" if: - An activation or stop condition is detected at an illegal location during the transfer of the address data or bit2 to bit9 (acknowledgement bits). - The 10-bit address header with 10-bit read access is received before the 10-bit write access is performed. • When the interface is enabled during the transfer, the detection of the first two conditions shown above is enabled after the first stop condition is received, in order to prevent an incorrect bus error report from being issued. bit15 BER: Bus error flag bit bit14 BEIE: Bus error interrupt enable bit This bit enables the bus error interrupt. Only user can change this bit. "0": Bus error interrupt disabled "1": Bus error interrupt enabled If this bit is set to "1", occurrence of interrupt is enabled when the BER bit is set to "1". SCC: Start condition continue bit This bit is used to generate the re-activation condition. This bit is write-only and "0" is always read. "0": N/A "1": Re-activation condition occurs in the master transfer. If "1" is written to this bit in master mode (MSS=1, INT=1), a re-activation condition is generated and the INT bit is automatically cleared. bit13 520 FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E MB90950 Series CHAPTER 20 I2C INTERFACE (400 kHz) 20.2 Table 20.2-2 Functions of Bus Control Register (IBCR0, IBCR1) (2 / 3) Bit name bit12 bit11 bit10 bit9 Function MSS: Master/slave selection bit This bit is the master/slave mode selection bit. Only user can set this bit. It can be cleared by user or hardware. "0": Enters the slave mode. "1": Enters the master mode and generates an activation condition to send the data byte of the address (IDAR register). This bit is cleared when arbitration lost occurs during master transmission. If "0" is written to this bit during setting a master interrupt (MSS=1, INT=1), the INT bit is automatically cleared and a stop condition is generated to end the data transfer. Note that the MSS bit is immediately reset and the stop condition can be checked by polling the BB bit of the IBSR register. • If "1" is written to this bit when the bus is idle (MSS=0, BB=0), an activation condition is generated and the content (address data) of the IDAR register is sent. • If "1" is written to this bit while the bus is busy (BB=1, TRX=0 in IBSR; MSS=0 in IBCR), the interface waits for the bus to be free and starts transmission. • If the interface is specified as a slave for the address that is accompanied by a write access (data reception), the transmission starts after the transfer ends and the bus is free again. If the interface is transmitting the data as a slave (AAS=1, TRX=1 in IBSR), the data transmission does not start even if the bus is free again. It is important to check whether the interface is specified as a slave (AAS=1 in IBSR) for the address, whether the data byte transmission has ended normally (MSS=1 in IBCR), or whether the data byte transmission has failed (AL=1 in IBSR) at the next interrupt. ACK: Data byte acknowledge bit This bit enables an acknowledgement generation when a data byte is received. Only user can change this bit. "0": Acknowledgement does not occur when a data byte is received. "1": Acknowledgement occurs when a data byte is received. This bit is disabled when an address byte is received in slave mode. If the interface detects a 7-bit or 10-bit slave address, it acknowledges whether the corresponding enable bits (ENTB in ITMK or ENSB in ISMK) are set. The write access to this bit occurs only if an interrupt is in progress (INT=1) or the bus is idle (BB=0 in the IBSR register). The write access to this bit is available only if the interface is enabled (EN=1 in the ICCR register) and no bus error occurs (BER=0 in the IBCR register). GCCA: General call address acknowledge bit This bit enables the acknowledgement generation when a general-purpose call address is received. Only user can change this bit. "0": Acknowledgement does not occur when a general-purpose call address byte is received. "1": Acknowledgement occurs when a general-purpose call address byte is received. The write access to this bit occurs only if an interrupt is in progress (INT=1) or the bus is idle (BB=0 in the IBSR register). The write access to this bit is available only if the interface is enabled (EN=1 in the ICCR register) and no bus error occurs (BER=0 in the IBCR register). INTE: Interrupt enable bit This bit enables an interrupt generation. Only user can change this bit. "0": Interrupts disabled "1": Interrupt enabled If this bit is set to "1", occurrence of interrupt is enabled when the INT bit is set to "1" by hardware. CM44-10148-4E FUJITSU MICROELECTRONICS LIMITED 521 CHAPTER 20 I2C INTERFACE (400 kHz) 20.2 MB90950 Series Table 20.2-2 Functions of Bus Control Register (IBCR0, IBCR1) (3 / 3) bit8 522 Bit name Function INT: Interrupt flag bit This bit is the transfer end interrupt request flag. This bit is changed by hardware and can be cleared by user. For a read-modify-write access, "1" is always read. Write access "0": Clears the transfer end interrupt request flag "1": N/A Read access "0": The transfer is not ended, not related to the current transfer, or the bus is idle "1": This bit is set to "1" when a 1-byte data transmission/reception, including an acknowledgement bit, is completed, if the following conditions are met: • Device is a bus master • Device is specified as a slave for the address • General-purpose call address was received • Arbitration lost occurred If the device is specified as a slave for the address, this bit is set after the address data is received, including an acknowledgement bit (after the first byte for the 7-bit address reception, or after the second byte for the 10-bit address reception). If this bit is set to "1", the SCL pin line is maintained at the "L" level. If "0" is written to this bit, the settings are cleared. Then, the SCL pin line is opened to transfer the next byte, and a re-activation or stop condition is generated. This bit is cleared when "1" is written to the SCC bit or the MSS bit is cleared. FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 20 I2C INTERFACE (400 kHz) 20.2 MB90950 Series ■ Contention of SCC, MSS, and INT Bits If data is simultaneously written to the SCC, MSS, and INT bits, contention occurs among the next-byte transfer, re-activation condition generation, and stop condition generation. If this situation occurs, the priorities are as follows: • Next-byte transfer and stop condition generation: When "0" is written to the INT bit and "0" is written to the MSS bit, writing of the MSS bit has precedence and a stop condition is generated. • Next-byte transfer and re-activation condition generation: When "0" is written to the INT bit and "1" is written to the SCC bit, writing of the SCC bit has precedence. A re-activation condition is generated, and the content of the IDAR register is transmitted. • Re-activation condition generation and stop condition generation: When "1" is written to the SCC bit and "0" is written to the MSS bit, clearing of the MSS bit has precedence. A stop condition is generated and the interface enters the slave mode. When an instruction that generates a start condition is executed (set "1" to the MSS bit) at timing as shown in Figure 20.2-4 and Figure 20.2-5, an arbitration lost detection (AL bit = 1) prevents an interrupt (INT bit = 1) from being generated. • Condition 1 in which an interrupt (INT bit = 1) does not occur upon detection of AL bit = 1 When an instruction that generates a start condition is executed (set "1" to the MSS bit in the IBCR register) with no start condition detected (BB bit = 0) and with the SDA or SCL pin at the "L" level. Figure 20.2-4 Diagram of Timing at which an Interrupt does not Occur upon Detection of AL Bit = 1 SCL pin "L" SDA pin "L" 1 I2C operation enable state (EN bit = 1) Master mode setting (MSS bit = 1) Arbitration lost detection (AL bit) Bus busy (BB bit) 0 Interrupt (INT bit) CM44-10148-4E 0 FUJITSU MICROELECTRONICS LIMITED 523 CHAPTER 20 I2C INTERFACE (400 kHz) 20.2 MB90950 Series • Condition 2 in which an interrupt (INT bit = 1) does not occur upon detection of AL bit = 1 When an instruction that generates a start condition by enabling an I2C operation (EN bit = 1) is executed (set "1" to the MSS bit in the IBCR register) with the I2C bus occupied by another master. This is because, as shown in Figure 20.2-5, when the other master on the I2C bus starts communication with I2C disabled (EN bit = 0), the I2C bus enters the occupied state with no start condition detected (BB bit = 0). Figure 20.2-5 Diagram of Timing at which an Interrupt does not Occur upon Detection of AL Bit = 1 Start condition The INT bit interrupt does not occur in the 9th clock cycle Stop condition SCL pin SDA pin Slave address ACK DAT ACK EN bit MSS bit AL bit BB bit 0 0 INT bit If a symptom as described above can occur, follow the procedure shown below for software processing: 1) Execute the instruction that generates a start condition (set "1" to the MSS bit) 2) Use, for example, the timer function to wait for the time for 3-bit data transmission at the I2C transfer frequency set in the ICCR register.* Example: I2C transfer frequency of 100 kHz Time for 3-bit data transmission {1/(100 × 103)} × 3 = 30 3) Check the AL and BB bits in the IBSR register and, if the AL bit =1 and BB bit = 0, set the EN bit in the ICCR register to "0" to initialize I2C. When AL bit is not "1" and BB bit is not "0", perform normal processing. 524 FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 20 I2C INTERFACE (400 kHz) 20.2 MB90950 Series A sample flow is given below: Master mode setting Set "1" to the MSS bit in the bus control register (IBCR) Wait for the time for 3-bit data transmission at the I2C transfer frequency set in the clock control register (ICCR)* NO BB bit = 0 and AL bit = 1 YES Set the EN bit to "0" to initialize I2C To normal process *: If an arbitration lost is detected, the AL bit is "1" after the time for 3-bit data transmission at the I2C transfer frequency has elapsed when the MSS bit is set to "1". • Example in which an interrupt (INT bit = 1) occurs upon detection of AL bit = 1 When an instruction which generates a start condition is executed (setting "1" to the MSS bit) with "bus busy" detected (BB bit = 1) and arbitration is lost, the INT bit interrupt occurs upon detection of AL bit = 1. Figure 20.2-6 Diagram of Timing at which an Interrupt Occurs upon Detection of AL Bit = 1 Start condition Interrupt at the 9th clock SCL pin SDA pin Slave address ACK DAT EN bit MSS bit AL bit Clear AL bit by software BB bit INT bit CM44-10148-4E Open SCL pin by clearing INT bit by software FUJITSU MICROELECTRONICS LIMITED 525 CHAPTER 20 I2C INTERFACE (400 kHz) 20.2 20.2.3 MB90950 Series 10-bit Slave Address Register (ITBAH0/ITBAH1, ITBAL0/ITBAL1) This register (ITBAH0/ITBAH1, ITBAL0/ITBAL1) specifies the 10-bit slave address. ■ Functions of 10-bit Slave Address Register (ITBAH0/ITBAH1, ITBAL0/ITBAL1) Write access to this register is available only if the interface is not enabled (EN=0 in ICCR). Figure 20.2-7 shows the bit configuration of the 10-bit slave address register (ITBAH0/ITBAH1, ITBAL0/ITBAL1). Figure 20.2-7 Bit Configuration of 10-bit Slave Address Register (ITBAH0/ITBAH1, ITBAL0/ITBAL1) Address: bit 15 14 13 12 11 10 ITBAH0: 007973 H ITBAH1: 007983 H 9 8 TA9 TA8 R/W R/W Address: ITBAL0: 007972H ITBAL1: 007982H bit 7 6 5 4 3 2 1 0 ITBAH0/ITBAH1 (Upper) Initial value 00000000B ITBAL0/ITBAL1 (Lower) TA7 TA6 TA5 TA4 TA3 TA2 TA1 TA0 Initial value R/W R/W R/W R/W R/W R/W R/W R/W 00000000B R/W : Readable/writable — : Undefined Table 20.2-3 Functions of 10-bit Slave Address Register (ITBAH0/ITBAH1, ITBAL0/ITBAL1) Bit name bit15 to bit10 bit9 to bit0 Function Undefined "0" is always read from these bits. TA9 to TA0: 10-bit slave address bits If a 10-bit address is enabled (ENTB=1 in the ITMK register), the address data is received in the slave mode and then compared with the ITBA register. An acknowledgement is sent to the master after the address header of a 10-bit*1 with write access is received. Then, 2nd received byte is compared with the ITBAL register. If a match is detected, an acknowledgement signal is sent to the master device and the AAS bit is set. In addition, the interface generates a positive response when it receives the 10-bit header*2 with read access after a re-activation condition is generated. All bits of the slave address can be masked using the ITMK register. The received 10-bit slave address is written back to the ITBA register. This is valid only when the AAS bit of the IBSR register is set to "1". * 1: The bit sequence for the 10-bit header (write access) consists of 11110, TA9, TA8, and 0. 2: The bit sequence for the 10-bit header (read access) consists of 11110, TA9, TA8, and 1. * 526 FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 20 I2C INTERFACE (400 kHz) 20.2 MB90950 Series 20.2.4 10-bit Slave Address Mask Register (ITMK0, ITMK1) This register includes the 10-bit slave address mask and 10-bit slave address enable bit. ■ Functions of 10-bit Slave Address Mask Register (ITMK0, ITMK1) Figure 20.2-8 shows the bit configuration of the 10-bit slave address mask register (ITMK0, ITMK1). Figure 20.2-8 Bit Configuration of 10-bit Slave Address Mask Register (ITMK0, ITMK1) Address: bit 15 14 13 12 11 10 9 8 ITMKH0/ITMKH1 (Upper) Initial value ITMKH0: 007975H ITMKH1: 007985H ENTB RAL TM9 TM8 R/W R/W R/W R/W bit 7 Address: ITMKL0: 007974H ITMKL1: 007984H 6 5 4 3 2 1 0 TM7 TM6 TM5 TM4 TM3 TM2 TM1 TM0 00111111B ITMKL0/ITMKL1 (Lower) Initial value 11111111B R/W R/W R/W R/W R/W R/W R/W R/W R/W : Readable/writable — : Undefined CM44-10148-4E FUJITSU MICROELECTRONICS LIMITED 527 CHAPTER 20 I2C INTERFACE (400 kHz) 20.2 MB90950 Series Table 20.2-4 Functions of 10-bit Slave Address Mask Register (ITMK0, ITMK1) Bit name Function ENTB: 10-bit slave address enable bit This bit enables a 10-bit slave address (and the reception response). Write access to this bit is available only if the interface is not enabled (EN=0 in ICCR). "0": 10-bit slave address disabled "1": 10-bit slave address enabled bit14 RAL: Reception slave address length This bit indicates whether the interface is specified as a 7-bit or 10-bit slave for the address. This bit is read-only. "0": Specified as a 7-bit slave for the address "1": Specified as a 10-bit slave for the address If both the 10-bit and 7-bit slave addresses are enabled (ENTB=1, ENSB=1), this bit can be used to determine whether the interface is specified as a 7-bit or 10-bit slave for the address. The content is valid only if the AAS bit of the IBSR register is set to "1". This bit is reset when the interface is disabled (EN=0 in ICCR). bit13 to bit10 Undefined "1" is always read from these bits. TM: 10-bit slave address mask bits This register is used to mask the 10-bit slave address of the interface. Write access to these bits is available only if the interface is disabled (EN=0 in ICCR). "0": Bits are not used for comparison of slave addresses "1": Bits are used for comparison of slave addresses These bits can be used to make the interface check for multiple 10-bit slave addresses. Only the bit set as "1" in this register is used for comparison of 10-bit slave addresses. The received slave address is written back to the ITBA register. The slave address can be determined by reading the ITBA register when the AAS bit of the IBSR register is "1". Note: If the address mask is changed after the interface is enabled, the slave address that was previously received can be overwritten and the slave address should be set again. bit15 bit9 to bit0 528 FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 20 I2C INTERFACE (400 kHz) 20.2 MB90950 Series 20.2.5 7-bit Slave Address Register (ISBA0, ISBA1) This register specifies the 7-bit slave address. ■ Functions of 7-bit Slave Address Register (ISBA0, ISBA1) Write access to this register is available only if the interface is not enabled (EN=0 in ICCR). Figure 20.2-9 shows the bit configuration of the 7-bit slave address register (ISBA0, ISBA1). Figure 20.2-9 Bit Configuration of 7-bit Slave Address Register (ISBA0, ISBA1) bit 7 Address: ISBA0: 007976H ISBA1: 007986H 6 5 4 3 2 1 0 ISBA0/ISBA1 SA6 SA5 SA4 SA3 SA2 SA1 SA0 R/W R/W R/W R/W R/W R/W R/W Initial value 00000000B R/W : Readable/writable — : Undefined Table 20.2-5 Functions of 7-bit Slave Address Register (ISBA0, ISBA1) Bit name bit7 bit6 to bit0 Function Undefined "0" is always read from this bit. SA6 to SA0: 7-bit slave address bits If a 7-bit address is enabled (ENSB=1 in the ISMK register), the address data is received in the slave mode and then compared with the ISBA register. If a match is detected, an acknowledgement signal is sent to the master device and the AAS bit is set. All bits of the slave address can be masked using the ISMK register. The received 7bit slave address is written back to the ISBA register. This is valid only when the AAS bit of the IBSR register is set to "1". The interface does not compare the received data and the content of this register when a 10-bit header or a general-purpose call is received. CM44-10148-4E FUJITSU MICROELECTRONICS LIMITED 529 CHAPTER 20 I2C INTERFACE (400 kHz) 20.2 20.2.6 MB90950 Series 7-bit Slave Address Mask Register (ISMK0, ISMK1) This register includes the 7-bit slave address mask (ISMK0, ISMK1) and 7-bit mode enable bit. ■ Functions of 7-bit Slave Address Mask Register (ISMK0, ISMK1) Write access to this register is available only if the interface is not enabled (EN=0 in ICCR). Figure 20.2-10 shows the bit configuration of the 7-bit slave address mask register (ISMK0, ISMK1). Figure 20.2-10 Bit Configuration of 7-bit Slave Address Mask Register (ISMK0, ISMK1) Address: bit 15 14 13 12 11 10 9 8 ISMK0: 007977H ISMK1: 007987H ENSB SM6 SM5 SM4 SM3 SM2 SM1 SM0 R/W R/W R/W R/W R/W R/W R/W R/W ISMK0/ISMK1 Initial value 01111111B R/W : Readable/writable Table 20.2-6 Functions of 7-bit Slave Address Mask Register (ISMK0, ISMK1) Bit name bit15 bit14 to bit8 530 Function ENSB: 7-bit address enable bit This bit enables a 7-bit slave address (and the reception response). 0: 7-bit slave address disabled 1: 7-bit slave address enabled SM: 7-bit slave address mask bits This register is used to mask the 7-bit slave address of the interface. 0: Bits are not used for comparison of slave addresses 1: Bits are used for comparison of slave addresses These bits can be used to make the interface check for multiple 7-bit slave addresses. Only the bit set as "1" in this register is used for comparison of 7-bit slave addresses. The received slave address is written back to the ISBA register. The slave address can be determined by reading the ISBA register when the AAS bit of the IBSR register is "1". Note: If the address mask is changed after the interface is enabled, the slave address that was previously received can be overwritten and the slave address should be set again. FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 20 I2C INTERFACE (400 kHz) 20.2 MB90950 Series 20.2.7 Data Register (IDAR0, IDAR1) Data register (IDAR0, IDAR1) is used for the serial data transfer. ■ Functions of Data Register (IDAR0, IDAR1) Figure 20.2-11 shows the bit configuration of the data register (IDAR0, IDAR1). Figure 20.2-11 Bit Configuration of Data Register (IDAR0, IDAR1) bit 7 Address: IDAR0: 007978H IDAR1: 007988H 6 D7 D6 5 4 3 2 1 0 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W IDAR0/IDAR1 Initial value 00000000B R/W : Readable/writable Table 20.2-7 Functions of Data Register (IDAR0, IDAR1) Bit name bit7 to bit0 D7 to D0: Data bits CM44-10148-4E Function The data register is used for serial data transfer. Data from MSB is transferred first. Since the writing side of this register is configured as double buffers, the data written when the bus is being used (BB=1) is loaded into the register for serial transfer. When the INT bit of the IBCR register is cleared or the bus is idle (BB=0 in IBSR), the data byte is loaded into the internal transfer register. Since the internal register is directly read during reading, the received data value in this register is valid only if INT=1 in the IBCR register. FUJITSU MICROELECTRONICS LIMITED 531 CHAPTER 20 I2C INTERFACE (400 kHz) 20.2 20.2.8 MB90950 Series Clock Control Register (ICCR0, ICCR1) The clock control register (ICCR0, ICCR1) has the following functions: • Test mode enable • I/O pad noise filter enable • I2C interface operation enable • Serial clock frequency setting ■ Functions of Clock Control Register (ICCR0, ICCR1) Figure 20.2-12 shows the bit configuration of the clock control register (ICCR0, ICCR1). Figure 20.2-12 Bit Configuration of Clock Control Register (ICCR0, ICCR1) Address: ICCR0: 00797BH ICCR1: 00798BH bit 15 14 13 12 11 10 9 8 ICCR0/ICCR1 NSF EN CS4 CS3 CS2 CS1 CS0 Initial value R/W R/W R/W R/W R/W R/W R/W 00011111B R/W : Readable/writable — : Unused 532 FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 20 I2C INTERFACE (400 kHz) 20.2 MB90950 Series Table 20.2-8 Functions of Clock Control Register (ICCR0, ICCR1) Bit name bit15 bit14 bit13 Function Unused "0" is always read from this bit. NSF: I/O pad noise filter enable bit This bit enables the noise filter built in the SDA and SCL I/O pad. 0: Noise filter disabled 1: Noise filter enabled This noise filter controls the single spike from the pulse width 0ns (minimum) to 1 to 1.5 cycles (maximum) of the internal bus. The maximum width of the spike wave that can be controlled is determined by the phase relationship between the I2C signal (SDA, SCL) and the machine clock. This bit should be set to "1" if the interface transmits/receives the data at speed of 100 kbps or more. EN: Enable bit This bit enables the operation of the I2C interface. Only user can set this bit. It can be cleared by both user and hardware. 0: Interface disabled 1: Interface enabled If this bit is set to "0", all bits of the IBSR and IBCR registers (except the BER and BEIE bits) are cleared. The module operation is disabled and the I2C line remains open. This bit is cleared by hardware if the bus error occurs (BER=1 in IBCR). Notes: • If the interface is disabled, the transmission/reception is immediately stopped. In this case, the I2C bus can be put in unfavorable situation. • If the I2C interface operation is inhibited, transmit/receive operation is immediately stopped. • If you wish to inhibit the I2C interface operation after generating the stop condition by writing "0" to the MSS bit, confirm the stop condition is generated (BB=0 for IBSR) before inhibiting the operation (EN=0 for ICCR). These bits set the serial bit transfer speed. These bits can be changed only if the interface is disabled (EN=0) or the EN bit is cleared simultaneously at the time of writing. n 1 bit12 to bit8 CS4 to CS0: Clock prescaler bits CS4 CS3 CS2 CS1 CS0 0 0 0 0 1 Bit rate: φ/28 (+1) 2 0 0 0 1 0 Bit rate: φ/40 (+1) 3 0 0 0 1 1 Bit rate: φ/52 (+1) 4 0 0 1 0 0 Bit rate: φ/64 (+1) 31 1 1 1 1 … 1 Bit rate: φ/400 (+1) (+1): If the noise filter is enabled, add 1 to the divisor. CM44-10148-4E FUJITSU MICROELECTRONICS LIMITED 533 CHAPTER 20 I2C INTERFACE (400 kHz) 20.2 MB90950 Series ■ Clock Prescaler Setting The values of CS0 to CS4 are calculated using the following formula: φ n × 12 + 16 φ Bit rate = n × 12 + 17 Bit rate = n>0, φ: Machine clock, noise filter disabled n>0, φ: Machine clock, noise filter enabled Table 20.2-9 Prescaler Setting n CS4 CS3 CS2 CS1 CS0 1 0 0 0 0 1 2 0 0 0 1 0 3 0 0 0 1 1 1 1 1 • • • 31 Note: 1 1 Do not use n=0 for the prescaler setting, because it is a violation against the SDA/SCL timing. ■ General Clock Frequency Table 20.2-10 shows the general machine clock frequency and the transmission bit transfer speed by the prescaler setting. Table 20.2-10 Relationship between Prescaler Setting Value and Transmission Bit Transfer Speed 100 kbps (Noise filter disabled) Machine Clock [MHz] 534 400 kbps (Noise filter enabled) n Bit Transfer Speed [kbps] n Bit Transfer Speed [kbps] 24 19 98 4 369 20 16 96 3 377 16 12 100 2 390 40/3=13.3 10 98 2 325 12 9 96 2 292 64/6=10.6 8 94 1 367 10 7 100 1 344 8 6 90 1 275 FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 20 I2C INTERFACE (400 kHz) 20.3 MB90950 Series 20.3 Operations of I2C Interface The I2C bus consists of two bidirectional bus lines used for communication: one serial data line (SDA) and one serial clock line (SCL). The I2C interface has two corresponding open-drain I/O pins (SDA/SCL), enabling wired logic. ■ Activation Condition If "1" is written to the MSS bit when the bus is open (BB=0 in IBSR, MSS=0 in IBCR) to place the I2C interface in master mode and to generate an activation condition. If "1" is written to this bit when the bus is idle (MSS=0, BB=0), an activation condition is generated and the content (address data) of the IDAR register is sent. If "1" is written to the SCC bit during interrupt when the bus is run in the master mode (MSS=1, INT=1 in IBCR), a re-activation condition can be generated. If "1" is written to the MSS bit when the bus is busy (BB=1, TRX=0 in IBSR; MSS=0, INT=0 in IBCR), the interface waits for the bus to be open and starts transmission. If the interface is specified as a slave for the address that is accompanied by a write access (data reception), the transmission starts after the transfer ends and the bus is open again. If the interface is transmitting the data as a slave, the data transmission does not start even if the bus is open again. It is important to check whether the interface is specified as a slave (MSS=0 in IBCR, AAS=1 in IBSR) for the address, whether the data byte transmission has ended normally (MSS=1 in IBCR), or whether the data byte transmission has failed (AL=1 in IBSR) at the next interrupt. Otherwise, writing "1" to the MSS or SCC bit has no effect. ■ Stop Condition If "0" is written to the MSS bit in master mode (MSS=1, INT=1 in IBCR) to generate a stop condition and to place the device in slave mode. Otherwise, writing "1" to the MSS bit has no effect. After the MSS bit is cleared, the interface tries to generate a stop condition. However, a stop condition will fail to be generated if the SCL line is driven to the "L" level. An interrupt is generated after the next byte is transferred. ■ Slave Address Detection In slave mode, BB is set to "1" after an activation condition is generated. The data sent from the master device is received by the IDAR register. After the 8-bit data is received, the content of the IDAR register is compared to the ISBA register using the bit mask stored in ISMK if the ENSB bit in the ISMK register is "1". If the comparison result is a match, the AAS bit is set to "1" and the acknowledgement signal is sent to the master. Then, bit0 of the received data (bit0 of the IDAR register) is inverted and stored in the TRX bit. CM44-10148-4E FUJITSU MICROELECTRONICS LIMITED 535 CHAPTER 20 I2C INTERFACE (400 kHz) 20.3 MB90950 Series If the ENTB bit in the ITMK register is "1" and the 10-bit address header (11110, TA9, TA8, 0) is detected, the interface sends an acknowledgement signal to the master and stores the last inverted data bit in the TRX register. No interrupt occurs. Then, the transferred byte is compared to the low-order byte of the ITBA register (using the bit mask stored in ITMK). If the result is a match, an acknowledgement signal is sent to the master, the AAS bit is set to "1", and an interrupt occurs. If the interface has been specified as a slave for the address and a re-activation condition is detected, the AAS bit is set to "1" and an interrupt occurs after the 10-bit address header (11110, TA9, TA8, 1) is received. 10-bit and 7-bit addresses and its bit masks have its own registers. Setting "1" to the ENSB bit of ISMK and the ENTB bit of ITMK enables the interface to check both of the addresses. The received slave address length can be determined whether to be 7 bits or 10 bits by reading the RAL bit of the ITMK register (this bit is valid only if the AAS bit is set to "1"). If the interface is to be used only as a master, setting both of the bits to "0" can prevent a slave address from being given to the interface. All the slave address bits can be masked by setting the corresponding mask register (ITMK or ISMK). ■ Slave Address Mask Only the bits set to "1" in the mask register (ITMK/ISMK) can be used for the address comparison. Other bits are all ignored. The received slave address can be read from the ITBA register (RAL=1: for a 10-bit address) or the ISBA register (RAL=0: for a 7-bit address) if the AAS bit in the IBSR register is "1". If the bit mask is cleared, the interface can be used as the bus monitor because it is always specified as a slave for the address. Note that this feature does not become a real bus monitor because it generates an acknowledgement when a slave address is received even though no other slave device is available. ■ Slave Addressing In master mode, the BB and TRX bits are set to "1" after an activation condition is generated. The content of the IDAR register is sent starting with MSB first. When an acknowledgement signal is received from the slave device after the address data is sent, bit0 (bit0 of the IDAR register that is already sent) of the sent data is inverted and stored in the TRX bit. The acknowledgement response of the slave can be checked using the LRB bit of the IBSR register. This procedure also applies to the re-activation condition. 2 bytes must be sent for a 10-bit slave address for write access. The first byte is the 10-bit address header consisting of 11110, TA9, TA8, 0, and the second byte that follows includes the low-order 8 bits of the 10bit slave address (TA7 to TA0). The 10-bit slave is accessed for read, when the above byte sequence is sent and a re-activation condition (SCC bit of IBCR) is generated as well as the read access 10-bit address header (11110, TA9, TA8, 1). 536 FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 20 I2C INTERFACE (400 kHz) 20.3 MB90950 Series The address data bytes can be summarized as follows: • 7-bit slave, write access : Activation condition - TA6 TA5 TA4 TA3 TA2 TA1 TA0 0 • 7-bit slave, read access : Activation condition - TA6 TA5 TA4 TA3 TA2 TA1 TA0 1 • 10-bit slave, write access: Activation condition - 1 1 1 1 0 TA9 TA8 0 - TA7 TA6 TA5 TA4 TA3 TA2 TA1 TA0 • 10-bit slave, read access : Activation condition - 1 1 1 1 0 TA9 TA8 1 - TA7 TA6 TA5 TA4 TA3 TA2 TA1 TA0 - re-activation - 1 1 1 1 0 TA9 TA8 1 ■ Arbitration If other master device is sending the data simultaneously when the data is being sent in the master mode, the arbitration will occur. If the device sends the data value "1" and the data on the SDA line is the "L" level, the device assumes arbitration to have been lost and sets the AL bit to "1". The AL bit is set to "1" when the interface does not generate an activation condition, or when neither an activation condition nor a stop condition can be generated for any reason even if the interface detects an activation condition in the first bit of the data byte. If the arbitration lost is detected, the MSS and TRX bits are cleared and the device enters the slave mode, and it can determine that its own arbitration lost occurs when the device's slave address is sent. ■ Acknowledgement The acknowledgement bit is sent from the receiver to the sender. The ACK bit of the IBCR register can be used to specify whether an acknowledgement is sent when the data byte is received. Even if an acknowledgement is not returned from the master during data transmission in slave mode (read access from other master), the TRX bit is set to "0" and the device enters the reception mode. This allows the master to generate a stop condition when the slave releases the SCL line. In master mode, an acknowledgement from the slave can be checked by reading the LRB bit of the IBSR register. CM44-10148-4E FUJITSU MICROELECTRONICS LIMITED 537 CHAPTER 20 I2C INTERFACE (400 kHz) 20.4 20.4 MB90950 Series Programming Flowcharts This section provides programming example for transmission and reception to use the I2C interface (400 kHz) module. ■ Example of Slave Addressing and Data Transmission Figure 20.4-1 shows the sample flowcharts for the slave addressing and data transmission. Figure 20.4-1 Sample Flowcharts for Slave Addressing and Data Transmission 7-bit slave addressing Data transmission Start Start Specify the writing slave for the address Clear the BER bit (if it is 1) Interface enabled EN=1 IDAR = Data byte; INT = 0 IDAR: = sl.address<<1+RW; MSS : = 1; INT : = 0 NO INT=1? NO INT=1? YES YES YES BER = 1? YES Bus error BER = 1? NO NO AL = 1? YES ACK? (LRB = 0?) Transfer resumed. Check whether it is AAS AL = 1? YES Transfer resumed. Check whether it is AAS NO ACK? (LRB = 0?) NO NO YES YES Data transmission ready The last byte transmitted? YES NO No ACK from the slave. Generate a re-activation or stop condition Transfer completed. Re-activation condition or stop condition generated 538 FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 20 I2C INTERFACE (400 kHz) 20.4 MB90950 Series ■ Example of Data Reception Figure 20.4-2 shows the sample flowchart for the data reception. Figure 20.4-2 Sample Flowchart for Data Reception Start Specify the reading slave for the address Clear the ACK bit of IBCR if the data is the last byte to be read from the slave; INT: = 0 NO INT = 1? YES BER= 1? YES Bus error NO NO The last byte transmitted? YES Transfer completed. Re-activation condition or stop condition generated CM44-10148-4E FUJITSU MICROELECTRONICS LIMITED 539 CHAPTER 20 I2C INTERFACE (400 kHz) 20.4 MB90950 Series ■ Example of Interrupt Handler Figure 20.4-3 shows the sample flowchart for the interrupt handler. Figure 20.4-3 Sample Flowchart for Interrupt Handler Start INT=1? Interrupt reception from another module NO YES Bus error BER = 1? YES GCA = 1? YES General-purpose call as slave NO NO YES YES AL = 1? Record the transfer failure and retry the transfer YES AAS = 1? AL = 1? NO YES Arbitration lost. Transfer resumed NO No ACK from the slave. YES Generate a LRB = 1? re-activation or stop condition. ADT = 1? NO Start to transfer new data upon the next INT. If required, change the ACK bit NO TRX = 1? TRX = 1? YES YES NO NO Read received byte from the IDAR register. If required, change the ACK bit Store the next sent byte to the IDAR register Read received byte from the IDAR register. If required, change the ACK bit Store the next sent byte to the IDAR register or clear MSS Clear the INT bit End 540 FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 21 CAN CONTROLLER This chapter explains the functions and overview of the CAN controller. 21.1 Features of CAN Controller 21.2 Block Diagram of CAN Controller 21.3 List of Registers 21.4 Classifying the CAN Controller Registers 21.5 Transmission of CAN Controller 21.6 Reception of CAN Controller 21.7 Reception Flowchart of CAN Controller 21.8 How to Use the CAN Controller 21.9 Procedure for Transmission by Message Buffer (x) 21.10 Procedure for Reception by Message Buffer (x) 21.11 Setting Configuration of Multi-level Message Buffer 21.12 Setting the Redirection of CAN1 RX/TX pin 21.13 CAN Direct Mode Register (CDMR) 21.14 Precautions when Using CAN Controller CM44-10148-4E FUJITSU MICROELECTRONICS LIMITED 541 CHAPTER 21 CAN CONTROLLER 21.1 21.1 MB90950 Series Features of CAN Controller The CAN (Controller Area Network) is the standard protocol for serial communication between automobile controllers and is widely used in industrial applications. ■ Features of CAN Controller ● Conforms to CAN Specification Version 2.0 Part A and B Supports transmission/reception in standard frame and extended frame formats ● Supports transmitting of data frames by receiving remote frames ● 16 transmitting/receiving message buffers 29-bit ID and 8-byte data Multi-level message buffer configuration ● Supports full-bit comparison, full-bit mask and partial bit mask filtering. Two acceptance mask registers in either standard frame format or extended frame formats ● Bit rate programmable from 10 kbps to 1 Mbps (A minimum 8 MHz machine clock is required if 1 Mbps is used. Also, a maximum 16MHz machine clock is required if 10kbps is used.) 542 FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 21 CAN CONTROLLER 21.2 MB90950 Series 21.2 Block Diagram of CAN Controller Figure 21.2-1 shows a block diagram of the CAN controller. ■ Block Diagram of CAN Controller Figure 21.2-1 Block Diagram of CAN Controller TQ (Operating clock) F2MC-16LX bus Prescaler 1 to 64 frequency division Clock Bit timing generation SYNC, TSEG1, TSEG2 PSC TS1 BTR TS2 RSJ TOE TS RS CSR HALT NIE NT Node status change interrupt generation IDLE, SUSPND, transmit, receive, ERR, OVRLD Bus state machine Node status change interrupt NS1, 0 Error control RTEC Tr ansmitting/receiving sequencer BVALR TREQR TBFx clear Tr ansmitting buffer x decision TBFx Data counter Error frame generation Acceptance filter control Overload frame generation TDLC RDLC TBFx IDSEL BITER, STFER, CRCER, FRMER, ACKER TCANR Output driver ARBLOST TX TRTRR TCR Stuffing Tr ansmission shift register RFWTR TBFx, set, clear Tr ansmission complete interrupt Tr ansmission complete interrupt generation TDLC TIER CRC generation ACK generation CRCER RBFx, set RDLC RCR Reception complete interrupt Reception complete interrupt generation RIER RBFx, TBFx, set, clear CRC generation/error check Receive shift register STFER Destuffing/stuffing error check RRTRR RBFx, set IDSEL ROVRR Arbitration check ARBLOST AMSR AMR0 0 1 Acceptance filter Receiving buffer x decision BITER Bit error check ACKER Acknowledgment error check AMR1 IDR0 to IDR15, DLCR0 to DLCR15, DTR0 to DTR15 RAM RBFx RAM address generation FRMER Form error check PH1 Input latch RX RBFx, TBFx, RDLC, TDLC, IDSEL LEIR LDER CM44-10148-4E FUJITSU MICROELECTRONICS LIMITED 543 CHAPTER 21 CAN CONTROLLER 21.3 21.3 MB90950 Series List of Registers Table 21.3-1 to Table 21.3-4 list the overall control registers, the message buffers (ID registers), and the message buffers (DLC registers and data registers). ■ List of Overall Control Registers Table 21.3-1 List of Overall Control Registers (1 / 2) Address Register 544 CAN0 CAN1 CAN2 000070H 000080H 0000E0H 000071H 000081H 0000E1H 000072H 000082H 0000E2H 000073H 000083H 0000E3H 000074H 000084H 0000E4H 000075H 000085H 0000E5H 000076H 000086H 0000E6H 000077H 000087H 0000E7H 000078H 000088H 0000E8H 000079H 000089H 0000E9H 00007AH 00008AH 0000EAH 00007BH 00008BH 0000EBH 00007CH 00008CH 0000ECH 00007DH 00008DH 0000EDH 00007EH 00008EH 0000EEH 00007FH 00008FH 0000EFH 007B00H 007D00H 007F00H 007B01H 007D01H 007F01H 007B02H 007D02H 007F02H 007B03H 007D03H 007F03H 007B04H 007D04H 007F04H 007B05H 007D05H 007F05H 007B06H 007D06H 007F06H 007B07H 007D07H 007F07H 007B08H 007D08H 007F08H 007B09H 007D09H 007F09H Abbreviation Access Message buffer valid register BVALR R/W 00000000 00000000 Transmit request register TREQR R/W 00000000 00000000 Transmit cancel register TCANR W 00000000 00000000 Transmit complete register TCR R/W 00000000 00000000 Receive complete register RCR R/W 00000000 00000000 Remote request receiving register RRTRR R/W 00000000 00000000 Receive overrun register ROVRR R/W 00000000 00000000 Receive interrupt enable register RIER R/W 00000000 00000000 Control status register CSR R/W, R 00XXX000 0XXXX0X1 Last event indicator register LEIR R/W XXXXXXXX 000X0000 Receive/Transmit error counter RTEC R 00000000 00000000 Bit timing register BTR R/W X1111111 11111111 IDE register IDER R/W XXXXXXXX XXXXXXXX FUJITSU MICROELECTRONICS LIMITED Initial Value CM44-10148-4E CHAPTER 21 CAN CONTROLLER 21.3 MB90950 Series Table 21.3-1 List of Overall Control Registers (2 / 2) Address Register CAN0 CAN1 CAN2 007B0AH 007D0AH 007F0AH 007B0BH 007D0BH 007F0BH 007B0CH 007D0CH 007F0CH 007B0DH 007D0DH 007F0DH 007B0EH 007D0EH 007F0EH 007B0FH 007D0FH 007F0FH 007B10H 007D10H 007F10H 007B11H 007D11H 007F11H 007B12H 007D12H 007F12H 007B13H 007D13H 007F13H 007B14H 007D14H 007F14H 007B15H 007D15H 007F15H 007B16H 007D16H 007F16H 007B17H 007D17H 007F17H 007B18H 007D18H 007F18H 007B19H 007D19H 007F19H 007B1AH 007D1AH 007F1AH 007B1BH 007D1BH 007F1BH Abbreviation Access Initial Value Transmit RTR register TRTRR R/W 00000000 00000000 Remote frame receive waiting register RFWTR R/W XXXXXXXX XXXXXXXX Transmit interrupt enable register TIER R/W 00000000 00000000 XXXXXXXX XXXXXXXX Acceptance mask select register AMSR R/W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX Acceptance mask register 0 AMR0 R/W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX Acceptance mask register 1 AMR1 R/W XXXXXXXX XXXXXXXX CM44-10148-4E FUJITSU MICROELECTRONICS LIMITED 545 CHAPTER 21 CAN CONTROLLER 21.3 MB90950 Series ■ List of Message Buffers (ID Registers) Table 21.3-2 List of Message Buffers (ID Registers) (1 / 3) Address CAN0 CAN1 CAN2 007A00H to 007A1FH 007C00H to 007C1FH 007E00H to 007E1FH 007A20H 007C20H 007E20H 007A21H 007C21H 007E21H 007A22H 007C22H 007E22H 007A23H 007C23H 007E23H 007A24H 007C24H 007E24H 007A25H 007C25H 007E25H 007A26H 007C26H 007E26H 007A27H 007C27H 007E27H 007A28H 007C28H 007E28H 007A29H 007C29H 007E29H 007A2AH 007C2AH 007E2AH 007A2BH 007C2BH 007E2BH 007A2CH 007C2CH 007E2CH 007A2DH 007C2DH 007E2DH 007A2EH 007C2EH 007E2EH 007A2FH 007C2FH 007E2FH 007A30H 007C30H 007E30H 007A31H 007C31H 007E31H 007A32H 007C32H 007E32H 007A33H 007C33H 007E33H 007A34H 007C34H 007E34H 007A35H 007C35H 007E35H 007A36H 007C36H 007E36H 007A37H 007C37H 007E37H Register Abbreviation Access Generalpurpose RAM -- R/W Initial Value XXXXXXXX to XXXXXXXX XXXXXXXX XXXXXXXX ID register 0 IDR0 R/W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX ID register 1 IDR1 R/W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX ID register 2 IDR2 R/W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX ID register 3 IDR3 R/W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX ID register 4 IDR4 R/W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX ID register 5 IDR5 R/W XXXXXXXX XXXXXXXX 546 FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 21 CAN CONTROLLER 21.3 MB90950 Series Table 21.3-2 List of Message Buffers (ID Registers) (2 / 3) Address Register CAN0 CAN1 CAN2 007A38H 007C38H 007E38H 007A39H 007C39H 007E39H 007A3AH 007C3AH 007E3AH 007A3BH 007C3BH 007E3BH 007A3CH 007C3CH 007E3CH 007A3DH 007C3DH 007E3DH 007A3EH 007C3EH 007E3EH 007A3FH 007C3FH 007E3FH 007A40H 007C40H 007E40H 007A41H 007C41H 007E41H 007A42H 007C42H 007E42H 007A43H 007C43H 007E43H 007A44H 007C44H 007E44H 007A45H 007C45H 007E45H 007A46H 007C46H 007E46H 007A47H 007C47H 007E47H 007A48H 007C48H 007E48H 007A49H 007C49H 007E49H 007A4AH 007C4AH 007E4AH 007A4BH 007C4BH 007E4BH 007A4CH 007C4CH 007E4CH 007A4DH 007C4DH 007E4DH 007A4EH 007C4EH 007E4EH 007A4FH 007C4FH 007E4FH 007A50H 007C50H 007E50H 007A51H 007C51H 007E51H 007A52H 007C52H 007E52H 007A53H 007C53H 007E53H 007A54H 007C54H 007E54H 007A55H 007C55H 007E55H 007A56H 007C56H 007E56H 007A57H 007C57H 007E57H Abbreviation Access Initial Value XXXXXXXX XXXXXXXX ID register 6 IDR6 R/W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX ID register 7 IDR7 R/W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX ID register 8 IDR8 R/W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX ID register 9 IDR9 R/W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX ID register 10 IDR10 R/W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX ID register 11 IDR11 R/W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX ID register 12 IDR12 R/W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX ID register 13 IDR13 R/W XXXXXXXX XXXXXXXX CM44-10148-4E FUJITSU MICROELECTRONICS LIMITED 547 CHAPTER 21 CAN CONTROLLER 21.3 MB90950 Series Table 21.3-2 List of Message Buffers (ID Registers) (3 / 3) Address Register CAN0 CAN1 CAN2 007A58H 007C58H 007E58H 007A59H 007C59H 007E59H 007A5AH 007C5AH 007E5AH 007A5BH 007C5BH 007E5BH 007A5CH 007C5CH 007E5CH 007A5DH 007C5DH 007E5DH 007A5EH 007C5EH 007E5EH 007A5FH 007C5FH 007E5FH Abbreviation Access Initial Value XXXXXXXX XXXXXXXX ID register 14 IDR14 R/W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX ID register 15 IDR15 R/W XXXXXXXX XXXXXXXX 548 FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 21 CAN CONTROLLER 21.3 MB90950 Series ■ List of Message Buffers (DLC Registers) Table 21.3-3 List of Message Buffers (DLC Registers) Address CM44-10148-4E CAN0 CAN1 CAN2 007A60H 007C60H 007E60H 007A61H 007C61H 007E61H 007A62H 007C62H 007E62H 007A63H 007C63H 007E63H 007A64H 007C64H 007E64H 007A65H 007C65H 007E65H 007A66H 007C66H 007E66H 007A67H 007C67H 007E67H 007A68H 007C68H 007E68H 007A69H 007C69H 007E69H 007A6AH 007C6AH 007E6AH 007A6BH 007C6BH 007E6BH 007A6CH 007C6CH 007E6CH 007A6DH 007C6DH 007E6DH 007A6EH 007C6EH 007E6EH 007A6FH 007C6FH 007E6FH 007A70H 007C70H 007E70H 007A71H 007C71H 007E71H 007A72H 007C72H 007E72H 007A73H 007C73H 007E73H 007A74H 007C74H 007E74H 007A75H 007C75H 007E75H 007A76H 007C76H 007E76H 007A77H 007C77H 007E77H 007A78H 007C78H 007E78H 007A79H 007C79H 007E79H 007A7AH 007C7AH 007E7AH 007A7BH 007C7BH 007E7BH 007A7CH 007C7CH 007E7CH 007A7DH 007C7DH 007E7DH 007A7EH 007C7EH 007E7EH 007A7FH 007C7FH 007E7FH Register Abbreviation Access DLC register 0 DLCR0 R/W XXXXXXXX DLC register 1 DLCR1 R/W XXXXXXXX DLC register 2 DLCR2 R/W XXXXXXXX DLC register 3 DLCR3 R/W XXXXXXXX DLC register 4 DLCR4 R/W XXXXXXXX DLC register 5 DLCR5 R/W XXXXXXXX DLC register 6 DLCR6 R/W XXXXXXXX DLC register 7 DLCR7 R/W XXXXXXXX DLC register 8 DLCR8 R/W XXXXXXXX DLC register 9 DLCR9 R/W XXXXXXXX DLC register 10 DLCR10 R/W XXXXXXXX DLC register 11 DLCR11 R/W XXXXXXXX DLC register 12 DLCR12 R/W XXXXXXXX DLC register 13 DLCR13 R/W XXXXXXXX DLC register 14 DLCR14 R/W XXXXXXXX DLC register 15 DLCR15 R/W XXXXXXXX FUJITSU MICROELECTRONICS LIMITED Initial Value 549 CHAPTER 21 CAN CONTROLLER 21.3 MB90950 Series ■ List of Message Buffers (Data Registers) Table 21.3-4 List of Message Buffers (Data Register) (1 / 2) Address 550 Register Abbreviation Access 007E80H to 007E87H Data register 0 (8 bytes) DTR0 R/W XXXXXXXX to XXXXXXXX 007C88H to 007C8FH 007E88H to 007E8FH Data register 1 (8 bytes) DTR1 R/W XXXXXXXX to XXXXXXXX 007A90H to 007A97H 007C90H to 007C97H 007E90H to 007E97H Data register 2 (8 bytes) DTR2 R/W XXXXXXXX to XXXXXXXX 007A98H to 007A9FH 007C98H to 007C9FH 007E98H to 007E9FH Data register 3 (8 bytes) DTR3 R/W XXXXXXXX to XXXXXXXX 007AA0H to 007AA7H 007CA0H to 007CA7H 007EA0H to 007EA7H Data register 4 (8 bytes) DTR4 R/W XXXXXXXX to XXXXXXXX 007AA8H to 007AAFH 007CA8H to 007CAFH 007EA8H to 007EAFH Data register 5 (8 bytes) DTR5 R/W XXXXXXXX to XXXXXXXX 007AB0H to 007AB7H 007CB0H to 007CB7H 007EB0H to 007EB7H Data register 6 (8 bytes) DTR6 R/W XXXXXXXX to XXXXXXXX 007AB8H to 007ABFH 007CB8H to 007CBFH 007EB8H to 007EBFH Data register 7 (8 bytes) DTR7 R/W XXXXXXXX to XXXXXXXX 007AC0H to 007AC7H 007CC0H to 007CC7H 007EC0H to 007EC7H Data register 8 (8 bytes) DTR8 R/W XXXXXXXX to XXXXXXXX 007AC8H to 007ACFH 007CC8H to 007CCFH 007EC8H to 007ECFH Data register 9 (8 bytes) DTR9 R/W XXXXXXXX to XXXXXXXX 007AD0H to 007AD7H 007CD0H to 007CD7H 007ED0H to 007ED7H Data register 10 (8 bytes) DTR10 R/W XXXXXXXX to XXXXXXXX 007AD8H to 007ADFH 007CD8H to 007CDFH 007ED8H to 007EDFH Data register 11 (8 bytes) DTR11 R/W XXXXXXXX to XXXXXXXX 007AE0H to 007AE7H 007CE0H to 007CE7H 007EE0H to 007EE7H Data register 12 (8 bytes) DTR12 R/W XXXXXXXX to XXXXXXXX 007AE8H to 007AEFH 007CE8H to 007CEFH 007EE8H to 007EEFH Data register 13 (8 bytes) DTR13 R/W XXXXXXXX to XXXXXXXX CAN0 CAN1 CAN2 007A80H to 007A87H 007C80H to 007C87H 007A88H to 007A8FH FUJITSU MICROELECTRONICS LIMITED Initial Value CM44-10148-4E CHAPTER 21 CAN CONTROLLER 21.3 MB90950 Series Table 21.3-4 List of Message Buffers (Data Register) (2 / 2) Address CM44-10148-4E Register Abbreviation Access 007EF0H to 007EF7H Data register 14 (8 bytes) DTR14 R/W XXXXXXXX to XXXXXXXX 007EF8H to 007EFFH Data register 15 (8 bytes) DTR15 R/W XXXXXXXX to XXXXXXXX CAN0 CAN1 CAN2 007AF0H to 007AF7H 007CF0H to 007CF7H 007AF8H to 007AFFH 007CF8H to 007CFFH FUJITSU MICROELECTRONICS LIMITED Initial Value 551 CHAPTER 21 CAN CONTROLLER 21.4 21.4 MB90950 Series Classifying the CAN Controller Registers There are three types of CAN controller registers: • Overall control registers • Message buffer control registers • Message buffers ■ Overall Control Registers The overall control registers are the following four registers: • Control status register (CSR) • Last event indicator register (LEIR) • Receive and transmit error counter (RTEC) • Bit timing register (BTR) ■ Message Buffer Control Registers The message buffer control registers are the following 14 registers: • Message buffer valid register (BVALR) • IDE register (IDER) • Transmission request register (TREQR) • Transmission RTR register (TRTRR) • Remote frame receiving wait register (RFWTR) • Transmission cancel register (TCANR) • Transmission complete register (TCR) • Transmission interrupt enable register (TIER) • Reception complete register (RCR) • Remote request receiving register (RRTRR) • Receive overrun register (ROVRR) • Reception interrupt enable register (RIER) • Acceptance mask select register (AMSR) • Acceptance mask registers 0 and 1 (AMR0 and AMR1) ■ Message Buffers The message buffers are the following three registers: • ID register x (x = 0 to 15) (IDR0 to IDR15) • DLC register x (x = 0 to 15) (DLCR0 to DLCR15) • Data register x (x = 0 to 15) (DTR0 to DTR15) 552 FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 21 CAN CONTROLLER 21.4 MB90950 Series 21.4.1 Configuration of Control Status Register (CSR) The register indicates bus operation, node status, transmit output enable and transmit/ receive status. The lower 8 bits with the control status register (CSR) is prohibited from executing any bit manipulation instructions (Read-Modify-Write instructions). Only in the case of HALT bits unchanged (initialization of the macro instructions etc.), use any bit manipulation instructions without problems. ■ Control Status Register (CSR) (Lower) Figure 21.4-1 Control Status Register (Lower) (CSR: L) Address: bit 7 CAN0: 007B00 H CAN1: 007D00H CAN2: 007F00 H 6 5 4 3 TOE - - - - R/W - - - - 2 NIE 1 Reserved 0 CSRn (lower) HALT Initial value 0XXXX0X1B R/W W R/W bit 0 HALT Bus Operation stop bit 0 Write: Cancels bus operation stop Read: Bus operation not in stop mode 1 Write: Stops bus operation Read: Bus operation in stop mode bit 1 Reserved 0 bit 2 NIE Reserved bit Always write "0" to this bit Node status transition interrupt output enable bit 0 Node status transition interrupt output disabled 1 Node status transition interrupt output enabled bit 7 R/W : Readable/writable W : Write only X : Undefined value - : Undefined : Initial value CM44-10148-4E TOE Tr ansmit output enable bit 0 General-purpose I/O port 1 Transmit pin TX n = 0, 1, 2 FUJITSU MICROELECTRONICS LIMITED 553 CHAPTER 21 CAN CONTROLLER 21.4 MB90950 Series ■ Control Status Register (CSR) (Upper) Figure 21.4-2 Control Status Register (Upper) (CSR: H) Address: bit 15 CAN0: 007B01 H CAN1: 007D01H CAN2: 007F01 H 14 13 12 11 TS RS - - - R R - - - 10 9 8 NT NS1 NS0 R/W R CSRn (upper) Initial value 00XXX000B R bit 9 NS1 bit 8 NS0 Node Status bits 0 0 Error active 0 1 Warning (error active) 1 0 Error passive 0 0 Bus off bit 10 NT Node status transition flag 0 No node status transition 1 Node status transition bit 14 RS Receive status bit 0 Message not being received 1 Message being received bit 15 TS 554 R/W : Readable/writable R : Read only X : Undefined value - : Undefined : Initial value Tr ansmit status bit 0 Message not being transmitted 1 Message being transmitted n = 0, 1, 2 FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 21 CAN CONTROLLER 21.4 MB90950 Series 21.4.2 Function of Control Status Register (CSR) The operating status of the register’s each bit is confirmed by following; • Setting "0" or "1" • Function control by writing • Read ■ Control Status Register (CSR) (Lower) Table 21.4-1 Function of the Control Status Register (CSR: L) (1 / 2) Bit name Function bit7 TOE: Transmit output enable bit This bit switches from a general-purpose I/O port to a transmit pin TX. When setting to "0": General-purpose I/O port When setting to "1": transmit pin TX bit6 to bit3 Undefined bits When reading: Value is undefined. When writing: No effect bit2 NIE: Node status transition interrupt output enable bit This bit controls a node status transition interrupt generation when a node status is transferred (CSR: NT = 1). When setting to "0": Interrupt generation is disabled. When setting to "1": Interrupt generation is enabled. bit1 Reserved; Reserved bit This bit is always set to "0". When reading: The value is always "0". CM44-10148-4E FUJITSU MICROELECTRONICS LIMITED 555 CHAPTER 21 CAN CONTROLLER 21.4 MB90950 Series Table 21.4-1 Function of the Control Status Register (CSR: L) (2 / 2) Bit name Function This bit controls the bus halt. The halt state of the bus can be checked by reading this bit. Writing to this bit 0: Cancels bus halt 1: Halt bus Reading this bit 0: Bus operation not in stop state 1: Bus operation in stop state bit0 556 HALT: Bus operation stop bit Note: When writing 0 to this bit during the node status is Bus Off, ensure that 1 is written to this bit. Example program: switch ( IO_CANCT0.CSR.bit.NS ) { case 0 : /* error active */ break; case 1 : /* warning */ break; case 2 : /* error passive */ break; default : /* bus off */ for ( i=0; ( i <= 500 ) & & ( IO_CANCT0.CSR.bit.HALT == 0); i++); IO_CANCT0.CSR.word = 0x0084; /* HALT = 0 */ break; } * The variable "i" is used for fail-safe. For details, see Section "21.4.4 Notes on Using Bus Operation Stop Bit (HALT = 1)" FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 21 CAN CONTROLLER 21.4 MB90950 Series ■ Control Status Register (CSR) Upper Table 21.4-2 Function of the Control Status Register (CSR: H) Bit name bit15 bit14 bit13 to bit11 bit10 bit9, bit8 Function TS: Transmit status bit This bit indicates whether a message is being transmitted. When reading: "0": Message not being transmitted "1": Message being transmitted When error frame or overload frame are transmitted, this bit is cleared to "0". RS: Receive status bit This bit indicates whether a message is being received. When reading: "0": Message not being received "1": Message being received While a message is on the bus, this bit becomes "1". Therefore, this bit is also "1" while a message is being transmitted. This bit does not necessarily indicates whether a receiving message passes through the acceptance filter. As a result, when this bit is "0", it implies that the bus operation is stopped (HALT = 1); the bus is in the intermission/bus idle or a error/overload frame is on the bus. Undefined bits When reading: Value is undefined. When writing: No effect NT: Node status transition flag If the node status is changed to increment, or from Bus Off to Error Active, this bit is set to "1". The condition that this bit is set to "1" as follows. At this time, the interrupt is generated for the node status interrupt enable bit (NIE) = 1. Warning ("01B") 1) Error active ("00B") → Error passive ("10B") 2) Warning ("01B") → 3) Error passive ("10B") → Bus off ("11B") Error active ("00B") 4) Bus off ("11B") → Note: In parentheses, the value of the NS1 and NS0 bits is indicated. At Write: "0": Cleared "1": Not possible to set (No effect) At Read by the read-modify-write instruction Always read "1". NS1, NS0: Node status bits These bits indicate the current node status via the combination. See Section "21.4.3 Correspondence between Node Status Bits and Node Status" for details. CM44-10148-4E FUJITSU MICROELECTRONICS LIMITED 557 CHAPTER 21 CAN CONTROLLER 21.4 21.4.3 MB90950 Series Correspondence between Node Status Bits and Node Status A pair of node status bits, NS1 and NS0, indicate the node status. ■ Correspondence between Node Status Bits (NS1, NS0) and Node Status Table 21.4-3 Correspondence between NS1 and NS0 and Node Status NS1 NS0 Node Status 0 0 Error active 0 1 Warning (error active) 1 0 Error passive 1 1 Bus off Note: Warning (error active) is included in the error active in CAN Specification 2.0B for the node status, however, indicates that the transmit error counter or receive error counter has exceeded 96. The node status transition diagram is shown in Figure 21.4-3. Figure 21.4-3 Node Status Transition Diagram Hardware reset Transition requires that bus operation be released from the stopped state. Error active REC ≥ 96 or TEC ≥ 96 REC < 96 and TEC < 96 REC ≥ 128 or TEC ≥ 128 Warning (Error active) REC: Receive error counter TEC: Transmit error counter After "0" has been written to the HALT bit of the control status register (CSR), continuous 11-bit High levels (recessive bits) are input 128 times to the receive input pin (RX). REC < 128 and TEC < 128 Error passive 558 TEC ≥ 256 Bus off (HALT =1) FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 21 CAN CONTROLLER 21.4 MB90950 Series 21.4.4 Notes on Using Bus Operation Stop Bit (HALT = 1) The bus operation stop bit is set by writing to the bit, hardware reset and the node status. The stop operation of the bus operation is different according to the state of the message buffer. ■ Conditions for Setting Bus Operation Stop (HALT = 1) There are three conditions for setting bus operation stop (HALT = 1): • Hardware reset • When node status changed to bus off • By writing "1" to HALT bit Note: The bus operation should be stopped by writing 1 to HALT before the F2MC-16LX is changed in lowpower consumption mode (stop mode and clock mode). If transmission is in progress when "1" is written to HALT, the bus operation is stopped (HALT = 1) after transmission is terminated. If reception is in progress when "1" is written to HALT, the bus operation is stopped immediately (HALT = 1). If received messages are being stored in the message buffer (x), stop the bus operation (HALT = 1) after storing the messages. To check whether the bus operation has stopped, always read the HALT bit. ■ Conditions for Canceling Bus Operation Stop (HALT = 0) The condition for cancelling the bus operation stop (HALT=0) is writing "0" to HALT. Notes: • Canceling the bus operation stop after hardware reset or by writing "1" to HALT as above conditions is performed after "0" is written to HALT and continuous 11-bit "H" levels (recessive bits) have been input to the receive input pin (RX). • Canceling the bus operation stop when the node status is changed to bus off as above conditions is performed after "0" is written to HALT and continuous 11-bit "H" levels (recessive bits) have been input 128 times to the receive input pin (RX). Then, the values of both transmit and receive error counters reach "0" and the node status is changed to error active. • When writing "0" to HALT bit during the node status is Bus Off, ensure that "1" is written to this bit. ■ State during Bus Operation Stop (HALT = 1) • The bus does not perform any operation, such as transmission and reception. • The transmit output pin (TX) outputs a "H" level (recessive bit). • The values of other registers and error counters are not changed. Note: The bit timing register (BTR) should be set during bus operation stop (HALT = 1). CM44-10148-4E FUJITSU MICROELECTRONICS LIMITED 559 CHAPTER 21 CAN CONTROLLER 21.4 21.4.5 MB90950 Series Last Event Indicator Register (LEIR) This register indicates the last event. The NTE, TCE, and RCE bits are exclusive. When the corresponding bit of the last event is set to "1", other bits are cleared to "0s". ■ Last Event Indicator Register (LEIR) Figure 21.4-4 Last Event Indicator Register (LEIR) Address: bit 7 CAN0: 007B02 H CAN1: 007D02H CAN2: 007F02 H 6 5 4 3 2 1 0 NTE TCE RCE - MBP3 MBP2 MBP1 MBP0 R/W R/W R/W - R/W R/W R/W R/W LEIRn Initial value 000X0000B bit3 MBP3 bit2 bit1 bit0 MBP2 MBP1 MBP0 0000BB to 1111B (initial value: "0000B") Message buffer pointer bits Message Buffer 0 to 15 bit5 RCE Receive completion event bit Read Write 0 The last event has not received. Bit cleared 1 The last event has received. No effect bit6 TCE Transmit completion event bit Read Write 0 The last event has not transmitted. Bit cleared 1 The last event has transmitted. No effect bit7 NTE Node status transition event bit Read R/W : Readable/writable X : Undefined value - : Undefined : Initial value Write 0 The last event is not node status transmitted. Bit cleared 1 The last event is node status transmitted. No effect n = 0, 1, 2 560 FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 21 CAN CONTROLLER 21.4 MB90950 Series ■ Function of Last Event Indicator Register (LEIR) Table 21.4-4 Function of Each Bit of the Last Event Indicator Register (1 / 2) Bit name Function NTE: Node status transition event bit When this bit is "1", node status transition is the last event. This bit is set to "1" after set either of bit of the control status register to "1" (CSR:NT=1). This setting is not related to the setting of NIE bit of the control status register (CSR). At Write: "0": Cleared "1": No effect At read by the read-modify-write instruction: Always read "1". TCE: Transmit completion event bit When this bit is "1", it indicates that transmit completion is the last event. This bit is set to "1" after set either of bit of the transmit completion register to "1" (TCR:TC0 to TC15=1). • This setting is not related to the setting of the transmit complete interrupt enable register (TIER). • When this bit is "1", MBP3 to MBP0 bits show the message buffer number (x) to complete the transmission of the message in the last event. At Write: "0": Cleared "1": No effect At read by the read-modify-write instruction: Always read "1". bit5 RCE: Receive completion event bit When this bit is "1", it indicates that receive completion is the last event. This bit is set to "1" after set either of bit of the receive complete register to "1" (RCR:RC0-to-RC15=1). • This setting is not related to the setting of the receive complete interrupt enable register (RIER). • When this bit is "1", MBP3 to MBP0 bits show the message buffer number (x) to complete the reception of the message in the last event. At Write: "0": Cleared "1": No effect At read by the read-modify-write instruction: Always read "1". bit4 Undefined bit When reading: The value is undefined. When writing: No effect bit7 bit6 CM44-10148-4E FUJITSU MICROELECTRONICS LIMITED 561 CHAPTER 21 CAN CONTROLLER 21.4 MB90950 Series Table 21.4-4 Function of Each Bit of the Last Event Indicator Register (2 / 2) Bit name bit3 to bit0 562 MBP3, MBP2, MBP1, MBP0: Message buffer pointer bits Function When TCE bit or RCE bit is "1", these bits show the message buffer number (x) to generating of the corresponding last event. If the NTE bit is set to "1", these bits have no meaning. At Write: "0": Cleared "1": No effect At read by the read-modify-write instruction: Always read "1". Note: If LEIR is accessed within an CAN interrupt handling, the event causing the interrupt is not necessarily the same as indicated by LEIR. In the time from interrupt request to the LEIR access by the interrupt handler there may occur other CAN events. FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 21 CAN CONTROLLER 21.4 MB90950 Series 21.4.6 Receive and Transmit Error Counters (RTEC) The receive and transmit error counters indicate the counts for transmission errors and reception errors defined in the CAN specifications. These registers can only be read. ■ Receive and Transmit Error Counters (RTEC) Figure 21.4-5 Receive and Transmit Error Counters Address: bit 15 CAN0: 007B05 H CAN1: 007D05H CAN2: 007F05 H Address: CAN0: 007B04 H CAN1: 007D04H CAN2: 007F04 H 14 13 12 11 10 9 8 RTECn (upper) TEC7 TEC6 TEC5 TEC4 TEC3 TEC2 TEC1 TEC0 R R R R R R R R bit 7 6 5 4 3 2 1 0 RTECn (lower) REC7 REC6 REC5 REC4 REC3 REC2 REC1 REC0 R R R R R R R R Initial value 00000000B Initial value 00000000B n = 0, 1, 2 R: Read only ■ Functions of Receive and Transmit Error Counters (RTEC) Table 21.4-5 Function of the Receive and Transmit Error Counters (RTEC) Bit name Function bit15 to bit8 TEC7 to TEC0: Transmit error counter bits These are transmit error counters. TEC7 to TEC0 values indicate 0 to 7 when the counter value is more than 256, and the subsequent increment is not counted for counter value. In this case, Bus Off is indicated for the node status (NS1 and NS0 of control status register CSR = 11). bit7 to bit0 REC7 to REC0: Receive error counter bits These are receive error counters. REC7 to REC0 values indicate 0 to 7 when the counter value is more than 256, and the subsequent increment is not counted for counter value. In this case, Error Passive is indicated for the node status (NS1 and NS0 of control status register CSR = 10). CM44-10148-4E FUJITSU MICROELECTRONICS LIMITED 563 CHAPTER 21 CAN CONTROLLER 21.4 21.4.7 MB90950 Series Bit Timing Register (BTR) Bit timing register (BTR) sets the prescaler and bit timing. ■ Bit Timing Register (BTR) Figure 21.4-6 Bit Timing Register (BTR) Address: bit 15 CAN0: 007B07 H CAN1: 007D07H CAN2: 007F07 H Address: R/W X - 13 12 11 10 9 8 - TS2.2 TS2.1 TS2.0 TS1.3 TS1.2 TS1.1 TS1.0 - R/W R/W R/W R/W R/W R/W R/W bit 7 CAN0: 007B06 H CAN1: 007D06H CAN2: 007F06 H 14 6 5 4 3 2 1 BTRn (upper) Initial value X1111111B 0 RSJ1 RSJ0 PSC5 PSC4 PSC3 REC2 PSC1 PSC0 BTRn (lower) Initial value 11111111B R/W R/W R/W R/W R/W R/W R/W R/W : Readable/Writable : Undefined value : Undefined n = 0, 1, 2 ■ Function of Bit Timing Register (BTR) Table 21.4-6 Function of Each Bit of the Bit Timing Register (BTR) Bit name Function bit14 to bit12 TS2.2 to TS2.0: Time segment 2 setting bits 2 to 0 These bits define the number of the time quanta (TQ’s) by dividing [(TS2.2 to TS2.0) +1] for the time segment 2 (TSEG2). The time segment 2 is equal to the phase buffer segment 2 (PHASE_SEG2) in the CAN specification. bit11 to bit8 TS1.3 to TS1.0: Time segment 1 setting bits 3 to 0 These bits define the number of the time quanta (TQ’s) by dividing [(TS1.3 to TS1.0)+1] for the time segment 1 (TSEG1). The time segment 1 is equal to the propagation segment (PROP_SEG) + phase buffer segment 1 (PHASE_SEG1) in the CAN specification. bit7, bit6 RSJ1, RSJ0: Resynchronization jump width setting bits 1, 0 These bits define the number of the time quanta (TQ’s) by dividing [(RSJ1 to RSJ0)+1] for the resynchronization jump width (RSJW). bit5 to bit0 PSC5 to PSC0: Prescaler setting bits 5 to 0 These bits define the time quanta (TQ) of the CAN controller by dividing system clock. Note: Set bit timing register (BTR) after stopping the bus operation (CSR: HALT=1). Release the bus operation stop by writing "0" in the HALT bit of the control status register after the setting of bit timing register (BTR) is ended. 564 FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 21 CAN CONTROLLER 21.4 MB90950 Series 21.4.8 Prescaler Setting by Bit Timing Register (BTR) The setting of bit timing register (BTR) corresponds to the bit time segments of prescaler in the CAN specification and the CAN controller. ■ Prescaler Settings The bit time segments defined in the CAN specification and the CAN controller are shown in Figure 21.4-7 and Figure 21.4-8 respectively. Figure 21.4-7 Bit Time Segment in CAN Specification Nominal bit time SYNC_SEG PROP_SEG PHASE_SEG1 PHASE_SEG2 Sample point Figure 21.4-8 Bit Time Segment in CAN Controller Nominal bit time SYNC_SEG TSEG1 TSEG2 Sample point The relationship between PSC = PSC5 to PSC0, TS1 = TS1.3 to TS1.0, TS2 = TS2.2 to TS2.0, and RSJ = RSJ1, RSJ0 is shown below. TQ BT = (PSC + 1) x CLK = SYNC_SEG + TSEG1 + TSEG2 = (1 + (TS1 + 1) + (TS2 +1)) x TQ = (3 + TS1 +TS2) x TQ RSJW = (RSJ + 1) x TQ CLK: input clock TQ: time quanta BT: bit time SYNC_SEG: synchronous segment TSEG1 and TSEG2: time segment 1 and 2 resynchronization jump width [(RSJ1 and RSJ0) +1] frequency division CM44-10148-4E FUJITSU MICROELECTRONICS LIMITED 565 CHAPTER 21 CAN CONTROLLER 21.4 MB90950 Series For correct operation, the following conditions should be met. For 1 PSC TSEG1 TSEG1 TSEG2 TSEG2 For PSC = 0 TSEG1 TSEG2 TSEG2 63 2TQ RSJW 2TQ RSJW 5TQ 2TQ RSJW In order to meet the bit timing requirements defined in the CAN specification, additions have to be met, e.g. the delay time has to be considered. 566 FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 21 CAN CONTROLLER 21.4 MB90950 Series 21.4.9 Message Buffer Valid Register (BVALR) Message buffer valid register (BVALR) sets the validity of the message buffers (x) or displays their state. ■ Message Buffer Valid Register (BVALR) Figure 21.4-9 Message Buffer Valid Register (BVALR) Address: CAN0: 000071 H CAN1: 000081 H CAN2: 0000E1 H bit 15 14 13 12 11 10 9 8 BVAL15 BVAL14 BVAL13 BVAL12 BVAL11 BVAL10 BVAL9 BVAL8 BVALRn (upper) Initial value 00000000B R/W R/W R/W R/W R/W R/W R/W R/W Address: CAN0: 000070 H CAN1: 000080 H CAN2: 0000E0 H bit 7 6 5 4 3 2 1 0 BVAL7 BVAL6 BVAL5 BVAL4 BVAL3 BVAL2 BVAL1 BVAL0 R/W R/W R/W R/W R/W R/W R/W R/W BVALRn (lower) Initial value 00000000B n = 0, 1, 2 R/W : Readable/Writable ■ Function of Message Buffer Valid Register (BVALR) 0: Message buffer (x) invalid 1: Message buffer (x) valid If the message buffer (x) is set to invalid, it will not transmit or receive messages. If the buffer is set to invalid during transmission operating, it becomes invalid (BVALx = 0) after the transmission is completed or terminated by an error. If the buffer is set to invalid during reception operating, it immediately becomes invalid (BVALx = 0). If received messages are stored in a message buffer (x), the message buffer (x) is invalid after storing the messages. Notes: • x indicates a message buffer number (x = 0 to 15). • When invaliding a message buffer (x) by writing "0" to a bit (BVALx), execution of a bit manipulation instruction is prohibited until the bit is clear to "0". • To invalidate the message buffer (by setting the BVALR: BVAL0 to BVAL15=0) while the CAN controller is operating for CAN communication (the read value of the CSR: HALT bit is "0" and the CAN controller is operating for CAN bus communication to enable transmission and reception), follow the procedure in Section "21.14 Precautions when Using CAN Controller". CM44-10148-4E FUJITSU MICROELECTRONICS LIMITED 567 CHAPTER 21 CAN CONTROLLER 21.4 21.4.10 MB90950 Series IDE register (IDER) This register sets the frame format used by the message buffers (x) during transmission/reception. ■ IDE Register (IDER) Figure 21.4-10 IDE Register (IDER) Address: bit 15 CAN0: 007B09 H CAN1: 007D09H CAN2: 007F09 H 14 13 12 11 10 9 8 IDE15 IDE14 IDE13 IDE12 IDE11 IDE10 IDE9 IDE8 IDERn(upper) Initial value XXXXXXXXB R/W R/W R/W R/W R/W R/W R/W R/W Address: bit 7 CAN0: 007B08 H CAN1: 007D08H CAN2: 007F08 H 6 5 4 3 2 IDE7 IDE6 IDE5 IDE4 IDE3 IDE2 1 0 IDE1 IDE0 R/W R/W R/W R/W R/W R/W R/W R/W IDERn (lower) Initial value XXXXXXXXB R/W : Readable/Writable X : Undefined value n = 0, 1, 2 ■ Functions of IDE Register (IDER) 0: The standard frame format (ID11 bits) is used for the message buffer (x). 1: The extended frame format (ID29 bits) is used for the message buffer (x). Notes: • This register should be set when the message buffer (x) is invalid (BVALx of the message buffer valid register (BVALR) = 0). Setting when the buffer is valid (BVALx = 1) may cause unnecessary received messages to be stored. • To invalidate the message buffer (by setting the BVALR: BVAL0 to BVAL15=0) while the CAN controller is operating for CAN communication (the read value of the CSR: HALT bit is "0" and the CAN controller is operating for CAN bus communication to enable transmission and reception), follow the procedure in Section "21.14 Precautions when Using CAN Controller". 568 FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 21 CAN CONTROLLER 21.4 MB90950 Series 21.4.11 Transmission Request Register (TREQR) Transmission request register (TREQR) sets transmission requests to the message buffers (x) or displays their state. ■ Transmission Request Register (TREQR) Figure 21.4-11 Transmission Request Register (TREQR) Address: CAN0: 000073 H CAN1: 000083 H CAN2: 0000E3 H bit 15 14 13 12 11 10 9 8 TREQ15 TREQ14 TREQ13 TREQ12 TREQ11 TREQ10 TREQ9 TREQ8 TREQRn (upper) Initial value 00000000B R/W R/W R/W R/W R/W R/W R/W R/W Address: CAN0: 000072 H CAN1: 000082 H CAN2: 0000E2 H bit 7 6 5 4 3 2 1 0 TREQ7 TREQ6 TREQ5 TREQ4 TREQ3 TREQ2 TREQ1 TREQ0 R/W R/W R/W R/W R/W R/W R/W R/W TREQRn (lower) Initial value 00000000B R/W : Readable/Writable n = 0, 1, 2 ■ Functions of Transmission Request Register (TREQR) When "1" is written to TREQx, transmission to the message buffer (x) starts. If RFWTx of the remote frame receiving wait register (RFWTR) *1 is "0", transmission starts immediately. However, if RFWTx = 1, transmission starts after waiting until a remote frame is received (RRTRx of the remote request receiving register (RRTRR)*1 becomes "1"). Transmission starts *2 immediately even when RFWTx = 1, if RRTRx is already 1 when 1 is written to TREQx. *1: For TRTRR and RFWTR, see Sections "21.4.12 Transmission RTR Register (TRTRR)" and "21.4.13 Remote Frame Receiving Wait Register (RFWTR)". *2: For cancellation of transmission, see Sections "21.4.14 Transmission Cancel Register (TCANR)" and "21.4.15 Transmission Complete Register (TCR)". Writing "0" to TREQx is ignored. "0" is read when a read-modify-write instruction is performed. If clearing (to "0") at completion of the transmit operation and setting by writing "1" are concurrent, clearing is preferred. If "1" is written to more than one bit, transmission is performed, starting with the lower-numbered message buffer (x). TREQx is "1" while transmission is pending, and becomes "0" when transmission is completed or canceled. CM44-10148-4E FUJITSU MICROELECTRONICS LIMITED 569 CHAPTER 21 CAN CONTROLLER 21.4 21.4.12 MB90950 Series Transmission RTR Register (TRTRR) This register sets the transmission RTR (Remote Transmission Request) bits for the message buffers (x). ■ Transmission RTR Register (TRTRR) Figure 21.4-12 Transmission RTR Register (TRTRR) Address: CAN0: 007B0BH CAN1: 007D0BH CAN2: 007F0BH bit 15 14 13 12 11 10 9 8 TRTR15 TRTR14 TRTR13 TRTR12 TRTR11 TRTR10 TRTR9 TRTR8 TRTRRn (upper) Initial value 00000000B R/W R/W R/W R/W R/W R/W R/W R/W Address: CAN0: 007B0AH CAN1: 007D0AH CAN2: 007F0AH bit 7 6 5 4 3 2 1 0 TRTR7 TRTR6 TRTR5 TRTR4 TRTR3 TRTR2 TRTR1 TRTR0 R/W R/W R/W R/W R/W R/W R/W R/W TRTRRn (lower) Initial value 00000000B R/W : Readable/Writable n = 0, 1, 2 ■ Functions of Transmission RTR Register (TRTRR) 0: Transmit data frame. 1: Transmit remote frame. 570 FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 21 CAN CONTROLLER 21.4 MB90950 Series 21.4.13 Remote Frame Receiving Wait Register (RFWTR) Remote frame receiving wait register (RFWTR) sets the conditions for starting transmission when a request for data frame transmission is set (TREQx of the transmission request register (TREQR) is "1" and TRTRx of the transmission RTR register (TRTRR) is "0"). ■ Remote Frame Receiving Wait Register (RFWTR) Figure 21.4-13 Remote Frame Receiving Wait Register (RFWTR) Address: CAN0: 007B0DH CAN1: 007D0DH CAN2: 007F0DH bit 15 14 13 12 11 10 9 8 RFWT15 RFWT14 RFWT13 RFWT12 RFWT11 RFWT10 RFWT9 RFWT8 RFWTRn (upper) Initial value XXXXXXXXB R/W R/W R/W R/W R/W R/W R/W R/W Address: CAN0: 007B0CH CAN1: 007D0CH CAN2: 007F0CH bit 7 6 5 4 3 2 1 0 RFWT7 RFWT6 RFWT5 RFWT4 RFWT3 RFWT2 RFWT1 RFWT0 R/W R/W R/W R/W R/W R/W R/W R/W RFWTRn (lower) Initial value XXXXXXXXB R/W : Readable/Writable X : Undefined value n = 0, 1, 2 ■ Functions of Remote Frame Receiving Wait Register (RFWTR) 0: Transmission starts immediately 1: Transmission starts after waiting until remote frame received (RRTRx of remote request receiving register (RRTRR) becomes "1") Notes: • Transmission starts immediately if RRTRx is already "1" when a request for transmission is set. • For remote frame transmission, do not set RFWTx to "1". CM44-10148-4E FUJITSU MICROELECTRONICS LIMITED 571 CHAPTER 21 CAN CONTROLLER 21.4 21.4.14 MB90950 Series Transmission Cancel Register (TCANR) This register cancels a pending request for transmission to the message buffer (x). ■ Transmission Cancel Register (TCANR) Figure 21.4-14 Transmission Cancel Register (TCANR) Address: CAN0: 000075 H CAN1: 000085 H CAN2: 0000E5 H Address: CAN0: 000074 H CAN1: 000084 H CAN2: 0000E4 H bit 15 14 13 12 11 10 9 8 TCAN15 TCAN14 TCAN13 TCAN12 TCAN11 TCAN10 TCAN9 TCAN8 W W W W W W W W bit 7 6 5 4 3 2 1 0 TCAN7 TCAN6 TCAN5 TCAN4 TCAN3 TCAN2 TCAN1 TCAN0 W W W W W W W W TCANRn (upper) Initial value 00000000B TCANRn (lower) Initial value 00000000B n = 0, 1, 2 W : Write only ■ Functions of Transmission Cancel Register (TCANR) When "1" is written to TCANx, this register cancels a pending request for transmission to the message buffer (x). At completion of cancellation, TREQx of the transmission request register (TREQR) becomes "0". Writing "0" to TCANx is ignored. This is a write-only register and its read value is always "0". 572 FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 21 CAN CONTROLLER 21.4 MB90950 Series 21.4.15 Transmission Complete Register (TCR) At completion of transmission by the message buffer (x), the corresponding TCx becomes "1". If TIEx of the transmission complete interrupt enable register (TIER) is "1", an interrupt occurs. ■ Transmission Complete Register (TCR) Figure 21.4-15 Transmission Complete Register (TCR) Address: bit 15 CAN0: 000077 H CAN1: 000087 H CAN2: 0000E7 H Address: CAN0: 000076 H CAN1: 000086 H CAN2: 0000E6 H 14 13 12 11 10 9 8 TC15 TC14 TC13 TC12 TC11 TC10 TC9 TC8 R/W R/W R/W R/W R/W R/W R/W R/W bit 7 6 5 4 3 2 1 0 TC7 TC6 TC5 TC4 TC3 TC2 TC1 TC0 R/W R/W R/W R/W R/W R/W R/W R/W TCRn (upper) Initial value 00000000B TCRn (lower) Initial value 00000000B R/W : Readable/Writable n = 0, 1, 2 ■ Functions of Transmission Complete Register (TCR) ● Conditions for TCx = 0 • Write "0" to TCx. • Write "1" to TREQx of the transmission request register (TREQR). After the completion of transmission, write "0" to TCx to clear it to "0". Writing "1" to TCx is ignored. "1" is read when a read-modify-write instruction is performed. Note: If setting to "1" by completion of the transmit operation and clearing to "0" by writing occur at the same time, the bit is set to "1". CM44-10148-4E FUJITSU MICROELECTRONICS LIMITED 573 CHAPTER 21 CAN CONTROLLER 21.4 21.4.16 MB90950 Series Transmission Interrupt Enable Register (TIER) This register enables or disables the transmission interrupt by the message buffer (x). The transmission interrupt is generated at transmission completion (when TCx of the transmission complete register (TCR) is "1"). ■ Transmission Interrupt Enable Register (TIER) Figure 21.4-16 Transmission Interrupt Enable Register (TIER) Address: CAN0: 007B0FH CAN1: 007D0FH CAN2: 007F0F H Address: CAN0: 007B0EH CAN1: 007D0EH CAN2: 007F0EH bit 15 14 13 12 11 10 9 8 TIE15 TIE14 TIE13 TIE12 TIE11 TIE10 TIE9 TIE8 R/W R/W R/W R/W R/W R/W R/W R/W bit 7 6 5 4 3 2 TIE7 TIE6 TIE5 TIE4 TIE3 TIE2 1 0 TIE1 TIE0 R/W R/W R/W R/W R/W R/W R/W R/W TIERn (upper) Initial value 00000000B TIERn (lower) Initial value 00000000B n = 0, 1, 2 R/W : Readable/Writable ■ Functions of Transmission Interrupt Enable Register (TIER) 0: Transmission interrupt disabled. 1: Transmission interrupt enabled. 574 FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 21 CAN CONTROLLER 21.4 MB90950 Series 21.4.17 Reception Complete Register (RCR) At completion of storing received message in the message buffer (x), RCx becomes "1". If RIEx of the reception complete interrupt enable register (RIER) is "1", an interrupt occurs. ■ Reception Complete Register (RCR) Figure 21.4-17 Reception Complete Register (RCR) Address: CAN0: 000079 H CAN1: 000089 H CAN2: 0000E9 H Address: CAN0: 000078 H CAN1: 000088 H CAN2: 0000E8 H bit 15 14 13 12 11 10 9 8 RC15 RC14 RC13 RC12 RC11 RC10 RC9 RC8 R/W R/W R/W R/W R/W R/W R/W R/W bit 7 RC7 6 5 4 3 2 1 0 RC6 RC5 RC4 RC3 RC2 RC1 RC0 R/W R/W R/W R/W R/W R/W R/W R/W RCRn (upper) Initial value 00000000B RCRn (lower) Initial value 00000000B R/W : Readable/Writable n = 0, 1, 2 ■ Functions of Reception Complete Register (RCR) ● Conditions for RCx = 0 Write "0" to RCx. After completion of handling received message, write "0" to RCx to clear it to "0". Writing "1" to RCx is ignored. "1" is read when a read-modify-write instruction is performed. Note: If setting to "1" by completion of the receive operation and clearing to "0" by writing occur at the same time, the bit is set to "1". CM44-10148-4E FUJITSU MICROELECTRONICS LIMITED 575 CHAPTER 21 CAN CONTROLLER 21.4 21.4.18 MB90950 Series Remote Request Receiving Register (RRTRR) After a received remote frame is stored in the message buffer (x), RRTRx becomes "1" (at the same time as RCx setting to "1"). ■ Remote Request Receiving Register (RRTRR) Figure 21.4-18 Remote Request Receiving Register (RRTRR) Address: bit 15 CAN0: 00007B H CAN1: 00008B H CAN2: 0000EBH 14 13 12 11 10 9 8 RRTR15 RRTR14 RRTR13 RRTR12 RRTR11 RRTR10 RRTR9 RRTR8 RRTRRn (upper) Initial value 00000000B R/W R/W R/W R/W R/W R/W R/W R/W Address: bit 7 CAN0: 00007A H CAN1: 00008A H CAN2: 0000EA H 6 5 4 3 2 1 0 RRTR7 RRTR6 RRTR5 RRTR4 RRTR3 RRTR2 RRTR1 RRTR0 R/W R/W R/W R/W R/W R/W R/W R/W RRTRRn (lower) Initial value 00000000B n = 0, 1, 2 R/W : Readable/Writable ■ Functions of Remote Request Receiving Register (RRTRR) ● Conditions for RRTRx = 0 • Write "0" to RRTRx. • After a received data frame is stored in the message buffer (x) (at the same time as RCx setting to "1"). • Transmission by the message buffer (x) is completed (TCx of the transmission complete register (TCR) is "1"). Writing "1" to RRTRx is ignored. "1" is read when a read-modify-write instruction is performed. Note: If setting to "1" by completion of the receive operation and clearing to "0" by writing occur at the same time, the bit is set to "1". 576 FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 21 CAN CONTROLLER 21.4 MB90950 Series 21.4.19 Receive Overrun Register (ROVRR) If RCx of the reception complete register (RCR) is "1" when completing storing of a received message in the message buffer (x), ROVRx becomes "1", indicating that reception has overrun. ■ Receive Overrun Register (ROVRR) Figure 21.4-19 Receive Overrun Register (ROVRR) Address: CAN0: 00007DH CAN1: 00008DH CAN2: 0000EDH bit 15 14 13 12 11 10 9 8 ROVR15 ROVR14 ROVR13 ROVR12 ROVR11 ROVR10 ROVR9 ROVR8 ROVRRn (upper) Initial value 00000000B R/W R/W R/W R/W R/W R/W R/W R/W Address: CAN0: 00007CH CAN1: 00008CH CAN2: 0000ECH bit 7 6 5 4 3 2 1 0 ROVR7 ROVR6 ROVR5 ROVR4 ROVR3 ROVR2 ROVR1 ROVR0 R/W R/W R/W R/W R/W R/W R/W R/W ROVRRn (lower) Initial value 00000000B R/W : Readable/Writable n = 0, 1, 2 ■ Functions of Receive Overrun Register (ROVRR) Writing "0" to ROVRx results in ROVRx = 0. Writing "1" to ROVRx is ignored. After checking that reception has overrun, write "0" to ROVRx to set it to "0". "1" is read when a read-modify-write instruction is performed. Note: If setting to "1" by completion of the receive overrun and clearing to "0" by writing occur at the same time, the bit is set to "1". CM44-10148-4E FUJITSU MICROELECTRONICS LIMITED 577 CHAPTER 21 CAN CONTROLLER 21.4 21.4.20 MB90950 Series Reception Interrupt Enable Register (RIER) Reception interrupt enable register (RIER) enables or disables the reception interrupt by the message buffer (x). The reception interrupt is generated at reception completion (when RCx of the reception completion register (RCR) is "1"). ■ Reception Interrupt Enable Register (RIER) Figure 21.4-20 Reception Interrupt Enable Register (RIER) Address: CAN0: 00007F H CAN1: 0000BFH CAN2: 0000EFH Address: CAN0: 00007E H CAN1: 0000BEH CAN2: 0000EEH bit 15 14 13 12 11 10 9 8 RIE15 RIE14 RIE13 RIE12 RIE11 RIE10 RIE9 RIE8 R/W R/W R/W R/W R/W R/W R/W R/W bit 7 6 5 4 3 2 1 0 RIE7 RIE6 RIE5 RIE4 RIE3 RIE2 RIE1 RIE0 R/W R/W R/W R/W R/W R/W R/W R/W RIERn (upper) Initial value 00000000B RIERn (lower) Initial value 00000000B R/W : Readable/Writable n = 0, 1, 2 ■ Functions of Reception Interrupt Enable Register (RIER) 0: Reception interrupt disabled. 1: Reception interrupt enabled. 578 FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 21 CAN CONTROLLER 21.4 MB90950 Series 21.4.21 Acceptance Mask Select Register (AMSR) This register selects masks (acceptance mask) for comparison between the received message ID’s and the message buffer (x) ID’s. ■ Acceptance Mask Select Register (AMSR) Figure 21.4-21 Acceptance Mask Select Register (AMSR) Address: bit CAN0: 007B10 H CAN1: 007D10H CAN2: 007F10 H Address: bit CAN0: 007B11 H CAN1: 007D11H CAN2: 007F11 H Address: 7 6 5 4 3 2 1 0 AMS3.1 AMS3.0 AMS2.1 AMS2.0 AMS1.1 AMS1.0 AMS0.1 AMS0.0 R/W R/W R/W R/W R/W R/W R/W R/W 15 14 13 12 11 10 9 8 AMS7.1 AMS7.0 AMS6.1 AMS6.0 AMS5.1 AMS5.0 AMS4.1 AMS4.0 bit CAN0: 007B12 H CAN1: 007D12H CAN2: 007F12 H Address: CAN0: 007B13 H CAN1: 007D13H CAN2: 007F13 H R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 AMS11.1 AMS11.0 AMS10.1 AMS10.0 AMS9.1 AMS9.0 AMS8.1 AMS8.0 R/W R/W R/W R/W R/W R/W R/W R/W bit 15 14 13 12 11 10 9 8 AMSRn (Byte 0) Initial value XXXXXXXXB AMSRn (Byte 1) Initial value XXXXXXXXB AMSRn (Byte 2) Initial value XXXXXXXXB AMSRn (Byte 3) AMS15.1 AMS15.0 AMS14.1 AMS14.0 AMS13.1 AMS13.0 AMS12.1 AMS12.0 R/W R/W R/W R/W R/W R/W R/W R/W : Readable/Writable X : Undefined value R/W Initial value XXXXXXXXB n = 0, 1, 2 ■ Functions of Acceptance Mask Select Register (AMSR) Table 21.4-7 Selection of acceptance Mask AMSx.1 AMSx.0 0 0 Full-bit comparison 0 1 Full-bit mask 1 0 Acceptance mask register 0 (AMR0) 1 1 Acceptance mask register 1 (AMR1) CM44-10148-4E Acceptance Mask FUJITSU MICROELECTRONICS LIMITED 579 CHAPTER 21 CAN CONTROLLER 21.4 MB90950 Series Notes: • AMSx.1 and AMSx.0 should be set when the message buffer (x) is invalid (BVALx of the message buffer valid register (BVALR) is "0"). Setting when the buffer is valid (BVALx = 1) may cause unnecessary received messages to be stored. • To invalidate the message buffer (by setting the BVALR: BVAL bit to 0) while the CAN controller is operating for CAN communication (the read value of the CSR: HALT bit is "0" and the CAN controller is operating for CAN bus communication to enable transmission and reception), follow the procedure in Section "21.14 Precautions when Using CAN Controller". 580 FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 21 CAN CONTROLLER 21.4 MB90950 Series 21.4.22 Acceptance Mask Registers 0, 1 (AMR0, AMR1) There are two acceptance mask registers, AMR0 and AMR1, both of which are available either in the standard frame format or extended frame format. AM28 to AM18 (11 bits) are used for acceptance masks in the standard frame format and AM28 to AM0 (29 bits) are used for acceptance masks in the extended format. ■ Acceptance Mask Registers 0, 1 (AMR0, AMR1) Figure 21.4-22 Acceptance Mask Register 0 (AMR0) Address: CAN0: 007B14 H CAN1: 007D14H CAN2: 007F14 H Address: CAN0: 007B15 H CAN1: 007D15H CAN2: 007F15 H Address: CAN0: 007B16 H CAN1: 007D16H CAN2: 007F16 H Address: CAN0: 007B17 H CAN1: 007D17H CAN2: 007F17 H bit 7 6 5 4 3 2 1 0 AM28 AM27 AM26 AM25 AM24 AM23 AM22 AM21 R/W R/W R/W R/W R/W R/W R/W R/W bit 15 14 13 12 11 10 9 8 AM20 AM19 AM18 AM17 AM16 AM15 AM14 AM13 R/W R/W R/W R/W R/W R/W R/W R/W bit 7 6 5 4 3 2 1 0 AM12 AM11 AM10 AM9 AM8 AM7 AM6 AM5 R/W R/W R/W R/W R/W R/W R/W R/W bit 15 14 13 12 11 10 9 8 AM4 AM3 AM2 AM1 AM0 - - - R/W R/W R/W R/W R/W - - - AMR0n (Byte 0) Initial value XXXXXXXXB AMR0n (Byte 1) Initial value XXXXXXXXB AMR0n (Byte 2) Initial value XXXXXXXXB AMR0n (Byte 3) Initial value XXXXXXXXB n = 0, 1, 2 R/W : Readable/writable X - : : : Undefined value Undefined Used bit in standard frame format CM44-10148-4E FUJITSU MICROELECTRONICS LIMITED 581 CHAPTER 21 CAN CONTROLLER 21.4 MB90950 Series Figure 21.4-23 Acceptance Mask Register 1 (AMR1) Address: CAN0: 007B18 H CAN1: 007D18H CAN2: 007F18 H Address: CAN0: 007B19 H CAN1: 007D19H CAN2: 007F19 H Address: CAN0: 007B1AH CAN1: 007D1AH CAN2: 007F1AH bit 7 6 5 4 3 2 1 0 AM28 AM27 AM26 AM25 AM24 AM23 AM22 AM21 R/W R/W R/W R/W R/W R/W R/W R/W bit 15 14 13 12 11 10 9 8 AM20 AM19 AM18 AM17 AM16 AM15 AM14 AM13 R/W R/W R/W R/W R/W R/W R/W R/W bit 7 6 5 4 3 2 1 0 AM12 AM11 AM10 AM9 AM8 AM7 AM6 AM5 R/W R/W R/W R/W R/W R/W R/W R/W Address: CAN0: 007B1BH CAN1: 007D1BH CAN2: 007F1BH bit 15 14 13 12 11 10 9 8 AM4 AM3 AM2 AM1 AM0 - - - R/W R/W R/W R/W R/W - - - AMR1n (Byte 0) Initial value XXXXXXXXB AMR1n (Byte 1) Initial value XXXXXXXXB AMR1n (Byte 2) Initial value XXXXXXXXB AMR1n (Byte 3) Initial value XXXXXXXXB n = 0, 1, 2 R/W X - : : : : Readable/Writable Undefined value Undefined Used bit in standard frame format ■ Functions of Acceptance Mask Registers 0, 1 (AMR0, AMR1) ● 0: Compare Compare the bit of the acceptance code (ID register IDRx for comparing with the received message ID) corresponding to this bit (bit set to "0") with the bit of the received message ID. If there is no match, no message is received. ● 1: Mask Mask the bit of the acceptance code ID register (IDRx) corresponding to this bit (bit set to "1"). No comparison is made with the bit of the received message ID. Notes: • AMR0 and AMR1 should be set when all the message buffers (x) selecting AMR0 and AMR1 are invalid (BVALx of the message buffer valid register (BVALR) is "0"). Setting when the buffers are valid (BVALx = 1) may cause unnecessary received messages to be stored. • To invalidate the message buffer (by setting the BVALR: BVAL0 to BVAL15=0) while the CAN controller is operating for CAN communication (the read value of the CSR: HALT bit is "0" and the CAN controller is operating for CAN bus communication to enable transmission and reception), follow the procedure in Section "21.14 Precautions when Using CAN Controller". 582 FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 21 CAN CONTROLLER 21.4 MB90950 Series 21.4.23 Message Buffers There are 16 message buffers. Message buffer x (x = 0 to 15) consists of an ID register (IDRx), DLC register (DLCRx), and data register (DTRx). ■ Message Buffers ● Register Configuration • ID register x (x = 0 to 15) (IDRx) This register is a ID register of the message buffer. This register memorizes acceptance code setting, transmission message ID setting, and reception ID. • DLC register x (x = 0 to 15) (DLCRx) This register stores the DLC of the message buffer. This register sets the data length of the message when a data frame and a remote frame are transmitted and the data length of the message when a data frame or a remote frame is received. • Data register x (x = 0 to 15) (DTRx) This register is a data register of the message buffer. This register memorizes the setting of the reception message data or the transmission message data. ● The message buffer (x) is used both for transmission and reception. ● The lower-numbered message buffers are assigned higher priority. • At transmission, when a request for transmission is made to more than one message buffer, transmission is performed, starting with the lowest-numbered message buffer (See Section "21.5 Transmission of CAN Controller"). • At reception, when the received message ID passes through the acceptance filter (mechanism for comparing the acceptance-masked ID of received message and message buffer) of more than one message buffer, the received message is stored in the lowest-numbered message buffer (See Section "21.6 Reception of CAN Controller"). CM44-10148-4E FUJITSU MICROELECTRONICS LIMITED 583 CHAPTER 21 CAN CONTROLLER 21.4 MB90950 Series ● Message buffer that can be used as multi level message buffer When the same acceptance filter is set in more than one message buffer, the message buffers can be used as a multi-level message buffer. This provides allowance for receiving time. (See Section "21.10 Procedure for Reception by Message Buffer (x)"). Notes: • A write operation to message buffers and general-purpose RAM areas should be performed in words to even addresses only. A write operation in bytes causes undefined data to be written to the upper byte at writing to the lower byte. Writing to the upper byte is ignored. When the BVALx bit of the message buffer valid register (BVALR) is "0" (Invalid), the message buffers x (IDRx, DLCRx, and DTRx) can be used as general-purpose RAM. • During the receive/transmit operation of the CAN controller, the CAN controller write/read to/from the message buffers. If the CPU tries to write/read to/from the message buffers in this period, the CPU has to wait a maximum time of 64 machine cycles. This is also true for the general-purpose RAM area (Address: 007A00H to 007A1FH, 007C00H to 007C1FH, and 007E00H to 007E1FH). 584 FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 21 CAN CONTROLLER 21.4 MB90950 Series 21.4.24 ID Register x (x = 0 to 15) (IDR0 to IDR15) ID register x (x = 0 to 15) (IDR0 to IDR15) is the ID register for message buffer (x). ■ ID Register x (x = 0 to 15) (IDR0 to IDR15) Figure 21.4-24 ID Registers x (x = 0 to 15) (IDR0 to IDR15) Address: CAN0: 007A20 H + 4 × x CAN1: 007C20H + 4 × x CAN2: 007E20 H + 4 × x Address: CAN0: 007A21 H + 4 × x CAN1: 007C21H + 4 × x CAN2: 007E21 H + 4 × x Address: CAN0: 007A22 H + 4 × x CAN1: 007C22H + 4 × x CAN2: 007E22 H + 4 × x Address: CAN0: 007A23 H + 4 × x CAN1: 007C23H + 4 × x CAN2: 007E23 H + 4 × x bit 7 6 5 4 3 2 1 0 ID28 ID27 ID26 ID25 ID24 ID23 ID22 ID21 R/W R/W R/W R/W R/W R/W R/W R/W bit 15 14 13 12 11 10 9 8 ID20 ID19 ID18 ID17 ID16 ID15 ID14 ID13 R/W R/W R/W R/W R/W R/W R/W R/W bit 7 6 5 4 ID12 ID11 ID10 ID9 3 2 1 ID8 ID7 ID6 0 ID5 R/W R/W R/W R/W R/W R/W R/W R/W bit 15 14 13 12 11 10 9 8 ID4 ID3 ID2 ID1 ID0 - - - R/W R/W R/W R/W R/W - - - IDRxn (Byte 0) Initial value XXXXXXXXB IDRxn (Byte 1) Initial value XXXXXXXXB IDRxn (Byte 2) Initial value XXXXXXXXB IDRxn (Byte 3) Initial value XXXXXXXXB R/W : Readable/Writable X : Undefined value - : Undefined : Used bit in standard frame format CM44-10148-4E FUJITSU MICROELECTRONICS LIMITED x = 0 to 15 n = 0, 1, 2 585 CHAPTER 21 CAN CONTROLLER 21.4 MB90950 Series ■ Functions of ID Registers x (x = 0 to 15) (IDR0 to IDR15) When using the message buffer (x) in the standard frame format (IDEx of the IDE register (IDER) = 0), use 11 bits of ID28 to ID18. When using the buffer in the extended frame format (IDEx = 1), use 29 bits of ID28 to ID0. ID28 to ID0 have the following functions: • Set acceptance code (ID for comparing with the received message ID). • Set transmitted message ID. Note: In the standard frame format, setting "1" to all bits of ID28 to ID22 is prohibited. • Store the received message ID. Note: All received message ID bits are stored (even if bits are masked by acceptance filter). In the standard frame format, ID17 to ID0 stores image of old message left in the receive shift register. Notes: • A write operation to this register should be performed in words. A write operation in bytes causes undefined data to be written to the upper byte at writing to the lower byte. Writing to the upper byte is ignored. • This register should be set when the message buffer (x) is invalid (BVALx of the message buffer valid register (BVALR) is "0"). Setting when the buffer is valid (BVALx = 1) may cause unnecessary received messages to be stored. • To invalidate the message buffer (by setting the BVALR: BVAL bit to 0) while the CAN controller is operating for CAN communication (the read value of the CSR: HALT bit is "0" and the CAN controller is operating for CAN bus communication to enable transmission and reception), follow the procedure in Section "21.14 Precautions when Using CAN Controller". 586 FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 21 CAN CONTROLLER 21.4 MB90950 Series 21.4.25 DLC Register x (x = 0 to 15) (DLCR0 to DLCR15) DLC register x (x = 0 to 15) (DLCR0 to DLCR15) is the DLC register for message buffer (x). ■ DLC Register x (x = 0 to 15) (DLCR0 to DLCR15) Figure 21.4-25 DLC Registers x (x = 0 to 15) (DLCR0 to DLCR15) Address: CAN0: 007A60 H + 2 × x CAN1: 007C60H + 2 × x CAN2: 007E60 H + 2 × x bit 7 6 5 4 3 2 1 0 - - - - - - - - R/W R/W R/W R/W DLC3 DLC2 DLC1 DLC0 DLCRnx (lower) Initial value XXXXXXXXB R/W : Readable/Writable X : Undefined value - : Undefined x = 0 to 15 n = 0, 1, 2 ■ Functions of DLC Registers x (x = 0 to 15) (DLCR0 to DLCR15) ● Transmission • Set the data length (byte count) of a transmitted message when a data frame is transmitted (TRTRx of the transmitting RTR register (TRTRR) is "0"). • Set the data length (byte count) of a requested message when a remote frame is transmitted (TRTRx = 1). Note: Setting other than 0000B to 1000B (0 to 8 bytes) is prohibited. ● Reception • Store the data length (byte count) of a received message when a data frame is received (RRTRx of the remote frame request receiving register (RRTRR) is "0"). • Store the data length (byte count) of a requested message when a remote frame is received (RRTRx = 1). Note: A write operation to this register should be performed in words. A write operation in bytes causes undefined data to be written to the upper byte at writing to the lower byte. Writing to the upper byte is ignored. CM44-10148-4E FUJITSU MICROELECTRONICS LIMITED 587 CHAPTER 21 CAN CONTROLLER 21.4 21.4.26 MB90950 Series Data Register x (x = 0 to 15) (DTR0 to DTR15) Data register x (x = 0 to 15) (DTR0 to DTR15) is the data register for message buffer (x). This register is used only in transmitting and receiving a data frame but not in transmitting and receiving a remote frame. ■ Data Register x (x = 0 to 15) (DTR0 to DTR15) Figure 21.4-26 Data Registers x (x = 0 to 15) (DTR0 to DTR15) Address: CAN0: 007A80 H + 8 × x CAN1: 007C80H + 8 × x CAN2: 007E80 H + 8 × x bit 7 D7 6 5 4 3 2 1 0 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W Address: CAN0: 007A81 H + 8 × x CAN1: 007C81H + 8 × x CAN2: 007E81 H + 8 × x bit 15 D7 14 13 12 D6 D5 D4 11 D3 DTRxn (Byte 0) Initial value XXXXXXXXB 10 9 8 DTRxn (Byte 1) D2 D1 D0 Initial value XXXXXXXXB R/W R/W R/W R/W R/W R/W R/W R/W Address: CAN0: 007A82 H + 8 × x CAN1: 007C82H + 8 × x CAN2: 007E82 H + 8 × x bit 7 6 5 4 3 2 1 0 D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W Address: CAN0: 007A83 H + 8 × x CAN1: 007C83H + 8 × x CAN2: 007E83 H + 8 × x bit 15 14 13 12 D7 D6 D5 D4 11 D3 10 9 8 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W Address: CAN0: 007A84 H + 8 × x CAN1: 007C84H + 8 × x CAN2: 007E84 H + 8 × x bit 7 D7 6 5 4 3 2 1 0 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W Address: CAN0: 007A85 H + 8 × x CAN1: 007C85H + 8 × x CAN2: 007E85 H + 8 × x bit 15 14 13 12 11 10 9 8 D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W Address: bit 7 CAN0: 007A86 H + 8 × x CAN1: 007C86H + 8 × x CAN2: 007E86 H + 8 × x D7 6 5 4 3 2 1 0 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W Address: CAN0: 007A87 H + 8 × x CAN1: 007C87H + 8 × x CAN2: 007E87 H + 8 × x bit 15 14 13 12 11 10 9 8 D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W : Readable/Writable X : Undefined value - : Undefined 588 DTRxn (Byte 2) Initial value XXXXXXXXB DTRxn (Byte 3) Initial value XXXXXXXXB DTRxn (Byte 4) Initial value XXXXXXXXB DTRxn (Byte 5) Initial value XXXXXXXXB DTRxn (Byte 6) Initial value XXXXXXXXB DTRxn (Byte 7) Initial value XXXXXXXXB x = 0 to 15 n = 0, 1, 2 FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 21 CAN CONTROLLER 21.4 MB90950 Series ■ Functions of Data Registers x (x = 0 to 15) (DTR0 to DTR15) ● Sets transmitted message data (any of 0 to 8 bytes). Data is transmitted in the order of BYTE0, BYTE1, ..., BYTE7, starting with the MSB. ● Stores received message data. Data is stored in the order of BYTE0, BYTE1, ..., BYTE7, starting with the MSB. Even if the received message data is less than 8 bytes, the remaining bytes of the data register (DTRx), to which data are stored, are undefined. Note: A write operation to this register should be performed in words. A write operation in bytes causes undefined data to be written to the upper byte at writing to the lower byte. Writing to the upper byte is ignored. CM44-10148-4E FUJITSU MICROELECTRONICS LIMITED 589 CHAPTER 21 CAN CONTROLLER 21.5 21.5 MB90950 Series Transmission of CAN Controller When "1" is written to TREQx of the transmission request register (TREQR), transmission by the message buffer (x) starts. At this time, TREQx becomes "1" and TCx of the transmission complete register (TCR) becomes "0". ■ Starting Transmission of the CAN Controller If RFWTx of the remote frame receiving wait register (RFWTR) is "0", transmission starts immediately. If RFWTx is "1", transmission starts after waiting until a remote frame is received (RRTRx of the remote request receiving register (RRTRR) becomes "1"). If a request for transmission is made to more than one message buffer (more than one TREQx is "1"), transmission is performed, starting with the lowest-numbered message buffer. Message transmission to the CAN bus (by the transmit output pin TX) starts when the bus is idle. If TRTRx of the transmission RTR register (TRTRR) is "0", a data frame is transmitted. If TRTRx is "1", a remote frame is transmitted. If the message buffer competes with other CAN controllers on the CAN bus for transmission and arbitration fails, or if an error occurs during transmission, the message buffer waits until the bus is idle and repeats retransmission until it is successful. ■ Canceling a Transmission Request from the CAN Controller ● Canceling by transmission cancel register (TCANR) A transmission request for message buffer (x) having not executed transmission during transmission pending can be canceled by writing "1" to TCANx of the transmission cancel register (TCANR). At completion of cancellation, TREQx becomes "0". ● Canceling by storing received message The message buffer (x) having not executed transmission despite transmission request also performs reception. If the message buffer (x) has not executed transmission despite a request for transmission of a data frame (TRTRx = 0 or TREQx = 1), the transmission request is canceled after storing received data frames passing through the acceptance filter (TREQx = 0). Note: A transmission request is not canceled by storing remote frames (TREQx = 1 remains unchanged). If the message buffer (x) has not executed transmission despite a request for transmission of a remote frame (TRTRx = 1 or TREQx = 1), the transmission request is canceled after storing received remote frames passing through the acceptance filter (TREQx = 0). Note: The transmission request is canceled by storing either data frames or remote frames. 590 FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 21 CAN CONTROLLER 21.5 MB90950 Series ■ Completing Transmission of the CAN Controller When transmission is successful, RRTRx becomes "0", TREQx becomes "0", and TCx of the transmission complete register (TCR) becomes "1". If the transmission complete interrupt is enabled (TIEx of the transmission interrupt enable register (TIER) is "1"), an interrupt occurs. ■ Transmission Flowchart of the CAN Controller Figure 21.5-1 Transmission Flowchart of the CAN Controller Transmission request (TREQx := 1) TCx := 0 0 TREQx? 1 0 RFWTx? 1 0 RRTRx? 1 If there are any other message buffers meeting the above conditions, select the lowest-numbered message buffer. NO Is the bus idle? YES 0 1 TRTRx? A data frame is transmitted. A remote frame is transmitted. NO Is transmission successful? YES TCANx? 1 RRTRx : = 0 TREQx := 0 TCx := 1 TREQx := 0 1 TIEx ? 0 0 A transmission complete interrupt occurs. End of transmission CM44-10148-4E FUJITSU MICROELECTRONICS LIMITED 591 CHAPTER 21 CAN CONTROLLER 21.6 21.6 MB90950 Series Reception of CAN Controller Reception starts when the start of data frame or remote frame (SOF) is detected on the CAN bus. ■ Acceptance Filtering The received message in the standard frame format is compared with the message buffer (x) set in the standard frame format (IDEx of the IDE register (IDER) is "0"). The received message in the extended frame format is compared with the message buffer (x) set in the extended frame format (IDEx is "1"). If all the bits set to compare by the acceptance mask agree after comparison between the received message ID and acceptance code (ID register (IDRx) for comparing with the received message ID), the received message passes to the acceptance filter of the message buffer (x). ■ Storing Received Message When the receive operation is successful, received messages are stored in a message buffer (x) including IDs passed through the acceptance filter. When receiving data frames, received messages are stored in the ID register (IDRx), DLC register (DLCRx), and data register (DTRx). Even if received message data is less than 8 bytes, some data is stored in the remaining bytes of the DTRx and its value is undefined. When receiving remote frames, received messages are stored only in the IDRx and DLCRx, and the DTRx remains unchanged. If there is more than one message buffer including IDs passed through the acceptance filter, the message buffer x in which received messages are to be stored is determined according to the following rules. • The order of priority of the message buffer x (x = 0 to 15) rises as its number lower; in other words, message buffer 0 is given the highest and the message buffer 15 is given the lowest priority. • Basically, message buffers with the RCx bit in the receive completion register (RCR) set to "0" are preferred in storing received messages. • If the bits of the acceptance mask select register (AMSR) are set to all bits compare (for message buffers with the AMSx.1 and AMSx.0 bits set to 00B), received messages are stored irrespective of the value of the RCx bit of the RCR. • If there are message buffers with the RCx bit of the RCR set to "0", or with the bits of the AMSR set to all bits compare, received messages are stored in the lowest-number (highest-priority) message buffer x. • If there are no message buffers above-mentioned, received messages are stored in a lower-number message buffer x. • Message buffers should be arranged in ascending numeric order. The lowest message buffers should be with all bits compare, then AMR0 or AMR1 masks. And The highest message buffers should be with all bits mask. 592 FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 21 CAN CONTROLLER 21.6 MB90950 Series Figure 21.6-1 shows a flowchart for determining the message buffer (x) where received messages are to be stored. It is recommended that message buffers be arranged in the following order: message buffers in which each AMSR bit is set to all bits compare, message buffers using AMR0 or AMR1, and message buffers in which each AMSR bit is set to all bits mask. Figure 21.6-1 Flowchart Determining Message Buffer (x) where Received Messages Stored Start Are message buffers with RCx clear to "0" or with AMSx.1 and AMSx.0 set to "00B" found? NO YES Select the lowest-numbered message buffer from above message buffer. Select the lowest-numbered message buffer. End ■ Receive Overrun When the received message is stored in the message buffer (x) with the corresponding RCx bit of the reception complete register (RCR) being already set to 1, it will result in receive overrun. In this case, the corresponding ROVRx bit in the receive overrun register ROVRR is set to "1". ■ Processing for Reception of Data Frame and Remote Frame ● Processing for reception of data frame RRTRx of the remote request receiving register (RRTRR) becomes "0". TREQx of the transmission request register (TREQR) becomes "0" immediately before storing the received message. A transmission request for message buffer (x) having not executed transmission will be canceled. Note: A request for transmission of either a data frame or remote frame is canceled. CM44-10148-4E FUJITSU MICROELECTRONICS LIMITED 593 CHAPTER 21 CAN CONTROLLER 21.6 MB90950 Series ● Processing for reception of remote frame RRTRx becomes "1". If TRTRx of the transmission RTR register (TRTRR) is "1", TREQx becomes "0". As a result, the request for transmitting remote frame to message buffer having not executed transmission will be canceled. Notes: • A request for data frame transmission is not canceled. • For cancellation of a transmission request, see Section "21.5 Transmission of CAN Controller". ■ Completing Reception RCx of the reception complete register (RCR) becomes "1" after storing the received message. If a reception interrupt is enabled (RIEx of the reception interrupt enable register (RIER) is "1"), an interrupt occurs. Note: This CAN controller will not receive any messages transmitted by itself. 594 FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 21 CAN CONTROLLER 21.7 MB90950 Series 21.7 Reception Flowchart of CAN Controller Figure 21.7-1 shows a reception flowchart of the CAN controller. ■ Reception Flowchart of the CAN Controller Figure 21.7-1 Reception Flowchart of the CAN Controller Detection of start of data frame or remote frame (SOF) NO Is any message buffer (x) passing to the acceptance filter found? YES NO Is reception successful? YES Determine message buffer (x) where received messages to be stored. Store the received message in the message buffer (x). 1 RCx? 0 Data frame ROVRx := 1 Remote frame Received message? RRTRx := 0 RRTRx := 1 1 TRTRx? 0 TREQx := 0 RCx := 1 RIEx ? 0 1 A reception interrupt occurs. End of reception CM44-10148-4E FUJITSU MICROELECTRONICS LIMITED 595 CHAPTER 21 CAN CONTROLLER 21.8 21.8 MB90950 Series How to Use the CAN Controller The following settings are required to use the CAN controller: • Bit timing • Frame format • ID • Acceptance filter • Low-power consumption mode ■ Setting Bit Timing The bit timing register (BTR) should be set during bus operation stop (when the bus operation stop bit (HALT) of the control status register (CSR) is "1"). After the setting completion, write "0" to HALT to cancel bus operation stop. ■ Setting Frame Format Set the frame format used by the message buffer (x). When using the standard frame format, set IDEx of the IDE register (IDER) to "0". When using the extended frame format, set IDEx to "1". This setting should be made when the message buffer (x) is invalid (BVALx of the message buffer valid register (BVALR) is "0"). Setting when the buffer is valid (BVALx = 1) may cause unnecessary received messages to be stored. ■ Setting ID Set the message buffer (x) ID to ID28 to ID0 of ID register (IDRx). The message buffer (x) ID need not be set to ID17 to ID0 in the standard frame format. The message buffer (x) ID is used as a transmission message at transmission and is used as an acceptance code at reception. This setting should be made when the message buffer (x) is invalid (BVALx of the message buffer valid register (BVALR) is "0"). Setting when the buffer is valid (BVALx = 1) may cause unnecessary received messages to be stored. ■ Setting Acceptance Filter The acceptance filter of the message buffer (x) is set by an acceptance code and acceptance mask. It should be set when the acceptance message buffer (x) is invalid (BVALx of the message buffer valid register (BVALR) is "0"). Setting when the buffer is valid (BVALx = 1) may cause unnecessary received messages to be stored. Set the acceptance mask used in each message buffer (x) by the acceptance mask select register (AMSR). The acceptance mask registers (AMR0 and AMR1) should also be set if used (For the setting details, see Sections "21.4.21 Acceptance Mask Select Register (AMSR)" and "21.4.22 Acceptance Mask Registers 0, 1 (AMR0, AMR1)"). The acceptance mask should be set so that a transmission request may not be canceled when unnecessary received messages are stored. For example, it should be set to a full-bit comparison if only one specific ID is used for the transmission. 596 FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 21 CAN CONTROLLER 21.8 MB90950 Series ■ Setting Low-power Consumption Mode To set the F2MC-16LX in a low-power consumption mode (stop and watch mode, etc.), write "1" to the bus operation stop bit (HALT) of the control status register (CSR), and then check that the bus operation has stopped (HALT = 1). CM44-10148-4E FUJITSU MICROELECTRONICS LIMITED 597 CHAPTER 21 CAN CONTROLLER 21.9 21.9 MB90950 Series Procedure for Transmission by Message Buffer (x) After setting the bit timing, frame format, ID, and acceptance filter, set BVALx to "1" to activate the message buffer (x). ■ Procedure for Transmission by Message Buffer (x) ● Setting transmit data length code Set the transmit data length code (byte count) to DLC3 to DLC0 of the DLC register (DLCRx). For data frame transmission (when TRTRx of the transmission RTR register (TRTRR) is "0"), set the data length of the transmitted message. For remote frame transmission (when TRTRx = 1), set the data length (byte count) of the requested message. Note: Setting other than 0000B to 1000B (0 to 8 bytes) is prohibited. ● Setting transmit data (only for transmission of data frame) For data frame transmission (when TRTRx of the transmission register (TRTRR) is "0"), set data as the count of byte transmitted in the data register (DTRx). Note: Transmit data should be written while the TREQx bit of the transmission request register (TREQR) is set to "0". There is no need for setting the BVALx bit of the message buffer valid register (BVALR) to "0". Setting the BVALx bit to "0" may cause incoming remote frame to be lost. ● Setting transmission RTR register For data frame transmission, set TRTRx of the transmission RTR register (TRTRR) to "0". For remote frame transmission, set TRTRx to "1". 598 FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 21 CAN CONTROLLER 21.9 MB90950 Series ● Setting conditions for starting transmission (only for transmission of data frame) Set RFWTx of the remote frame receiving wait register (RFWTR) to "0" to start transmission immediately after a request for data frame transmission is set (TREQx of the transmission request register (TREQR) is "1" and TRTRx of the transmission RTR register (TRTRR) is "0"). Set RFWTx to "1" to start transmission after waiting until a remote frame is received (RRTRx of the remote request receiving register (RRTRR) becomes "1") after a request for data frame transmission is set (TREQx = 1 and TRTRx = 0). Note: Remote frame transmission cannot be made, if RFWTx is set to "1". ● Setting transmission complete interrupt When generating a transmission complete interrupt, set TIEx of the transmission interrupt enable register (TIER) to "1". When not generating a transmission complete interrupt, set TIEx to "0". ● Setting transmission request For a transmission request, set TREQx of the transmission request register (TREQR) to "1". ● Canceling transmission request When canceling a pending request for transmission to the message buffer (x), write "1" to TCANx of the transmission cancel register (TCANR). Check TREQx. For TREQx = 0, transmission request cancellation is terminated or transmission is completed. Check TCx of the transmission complete register (TCR). For TCx = 0, transmission request cancellation is terminated. For TCx = 1, transmission is completed. ● Processing for completion of transmission If transmission is successful, TCx of the transmission complete register (TCR) becomes "1". If the transmission complete interrupt is enabled (TIEx of the transmission interrupt enable register (TIER) is "1"), an interrupt occurs. After checking the transmission completion, write "0" to TCx to set it to "0". This cancels the transmission complete interrupt. In the following cases, the pending transmission request is canceled by receiving and storing a message. • Request for data frame transmission by reception of data frame • Request for remote frame transmission by reception of data frame • Request for remote frame transmission by reception of remote frame Request for data frame transmission is not canceled by receiving and storing a remote frame. ID and DLC, however, are changed by the ID and DLC of the received remote frame. Note that the ID and DLC of data frame to be transmitted become the value of received remote frame. CM44-10148-4E FUJITSU MICROELECTRONICS LIMITED 599 CHAPTER 21 CAN CONTROLLER 21.10 21.10 MB90950 Series Procedure for Reception by Message Buffer (x) After setting the bit timing, frame format, ID, and acceptance filter, make the settings described below. ■ Procedure for Reception by Message Buffer (x) ● Setting reception interrupt To enable reception interrupt, set RIEx of the reception interrupt enable register (RIER) to "1". To disable reception interrupt, set RIEx to "0". ● Starting reception When starting reception after setting, set BVALx of the message buffer valid register (BVALR) to "1" to make the message buffer (x) valid. ● Processing for reception completion If reception is successful after passing to the acceptance filter, the received message is stored in the message buffer (x) and RCx of the reception complete register (RCR) becomes "1". For data frame reception, RRTRx of the remote request receiving register (RRTRR) becomes "0". For remote frame reception, RRTRx becomes "1". If a reception interrupt is enabled (RIEx of the reception interrupt enable register (RIER) is "1"), an interrupt occurs. After checking the reception completion (RCx = 1), process the received message. After completion of processing the received message, check ROVRx of the reception overrun register (ROVRR). If ROVRx = 0, the processed received message is valid. Write "0" to RCx to set it to "0" (the reception complete interrupt is also canceled) to terminate reception. If ROVRx = 1, a reception overrun occurred and the next message may have overwritten the processed message. In this case, received messages should be processed again after setting the ROVRx bit to "0" for clearing by writing "0" to it. Figure 21.10-1 shows an example of receive interrupt handling. 600 FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 21 CAN CONTROLLER 21.10 MB90950 Series Figure 21.10-1 Example of Receive Interrupt Handling Interrupt with RCx = 1 Read received messages. A: = ROVRx ROVRx := 0 A = 0? NO YES RCx := 0 End CM44-10148-4E FUJITSU MICROELECTRONICS LIMITED 601 CHAPTER 21 CAN CONTROLLER 21.11 21.11 MB90950 Series Setting Configuration of Multi-level Message Buffer If the receptions are performed frequently, or if several different ID’s of messages are received, in other words, if there is insufficient time for handling messages, more than one message buffer can be combined into a multi-level message buffer to provide allowance for processing time of the received message by CPU. ■ Setting Configuration of Multi-level Message Buffer To provide a multi-level message buffer, the same acceptance filter must be set in the combined message buffers. If the bits of the acceptance mask select register (AMSR) are set to all bits compare ((AMSx.1, AMSx.0) = (0, 0)), multi-level message configuration of message buffers is not allowed. This is because all bits compare causes received messages to be stored irrespective of the value of the RCx bit of the receive completion register (RCR), so received messages are always stored in lower-numbered (higher-priority) message buffers even if all bits compare and identical acceptance code (ID register (IDRx)) are specified for more than one message buffer. Therefore, all bits compare and identical acceptance code should not be specified for more than one message buffer. Figure 21.11-1 shows operational examples of multi-level message buffers. 602 FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 21 CAN CONTROLLER 21.11 MB90950 Series Figure 21.11-1 Examples of Operation of Multi-level Message Buffer Initialization AMS15, AMS14, AMS13 AMSR 10 10 10 Select AMR0. .. . AM28 to AM18 AMR0 ID28 to ID18 Message buffer 13 Message buffer 14 Message buffer 15 0000 1111 111 0101 0000 000 0101 0000 000 0101 0000 000 RC15, RC14, RC13 IDE .. . 0 .. . RCR 0 0 0 .. . 0 .. . ROVRR 0 0 0 .. . 0 .. . ROVR15, ROVR14, ROVR13 Mask Message receiving The received message is stored in message buffer 13. IDE ID28 to ID18 Message receiving 0101 1111 000 0 .. . Message buffer 13 0101 1111 000 0 .. . RCR 0 0 1 .. . ROVRR 0 0 0 .. . Message buffer 14 0101 0000 000 0 .. . Message buffer 15 0101 0000 000 0 .. . Message receiving The received message is stored in message buffer 14. Message receiving 0101 1111 001 0 .. . Message buffer 13 0101 1111 000 0 .. . RCR 0 1 1 .. . 0 .. . ROVRR 0 0 0 .. . 0 .. . Message buffer 14 Message buffer 15 Message receiving 0101 1111 001 0101 0000 000 The received message is stored in message buffer 15. Message receiving 0101 1111 010 0 .. . Message buffer 13 0101 1111 000 0 .. . RCR 1 1 1 .. . Message buffer 14 0101 1111 001 0 .. . ROVRR 0 0 0 .. . Message buffer 15 0101 1111 010 0 .. . Message receiving The received message is stored in message buffer 13. Message receiving 0101 1111 011 0 .. . Message buffer 13 0101 1111 011 0 .. . RCR 1 1 1 .. . Message buffer 14 0101 1111 001 0 .. . ROVRR 0 0 1 .. . Message buffer 15 0101 1111 010 0 .. . Note: Four messages are received with the same acceptance filter set in message buffers 13, 14 and 15. CM44-10148-4E FUJITSU MICROELECTRONICS LIMITED 603 CHAPTER 21 CAN CONTROLLER 21.12 21.12 MB90950 Series Setting the Redirection of CAN1 RX/TX pin CAN1 can be changed the redirection CAN1 RX1/TX1pin (initial setting) to RX0/TX0 pin by the CANSWR register. ■ CAN Switching Register (CANSWR) Figure 21.12-1 CAN1 RX/TX Pin Switching Register (CANSWR) bit 15 Address: CAN1: 00796FH R/W - : : 14 13 12 11 10 - - - - - - - - - - - - 9 8 RXS01 TXS01 R/W R/W CANSWR Initial value 11111100B Readable/Writable Undefined Table 21.12-1 Function of Each Bit of the CAN Switch Register (CANSWR) Bit name Function bit15 to bit10 Undefined bits Always write "0" to these bits. bit9 RXS01: Reception pin switch 0/1 If "0" is written to this bit, input signal of CAN1 is inputted from RX1 pin. (initial value) If "1" is written to this bit, input signal of CAN1 is inputted from RX0 pin. bit8 TXS01: Transmission pin switch 0/1 If "0" is written to this bit, output signal of CAN1 is outputted from TX1 pin. (initial value) If "1" is written to this bit, output signal of CAN1 is outputted from TX0 pin. Figure 21.12-2 Node Status Transition Diagram CAN0 TX TX0 Switched by TXS01 of CANSWR RX0 RX CAN0 RX CAN1 Switched by RXS01 of CANSWR VCC CAN1 604 TX TX1 RX1 FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 21 CAN CONTROLLER 21.13 MB90950 Series 21.13 CAN Direct Mode Register (CDMR) To operate CAN normally, this register must be set correctly. ■ CAN Direct Mode Register (CDMR) Figure 21.13-1 Bit Configuration of the CAN Direct Mode Register (CDMR) Address: bit CAN0: 00796E H R/W - : : 7 6 - - - - 5 4 3 - - - 2 - 1 - 0 - - - - - R/W CDMR DIRECT Initial value 11111110B Readable/Writable Undefined Table 21.13-1 Function of the CAN Direct Mode Register Bit name bit7 to bit1 Undefined bits bit0 DIRECT: direct mode bit Function Always set "1" to this bit. Note: When using CAN controller in MB90V950, the DIRECT bit of this register must be set to "1". If setting the bit to "0", operation is different from that in MB90F952. In MB90F952, setting of the DIRECT bit has no effect on operation. Operation is the same as that in MB90V950 with DIRECT set to "1". CM44-10148-4E FUJITSU MICROELECTRONICS LIMITED 605 CHAPTER 21 CAN CONTROLLER 21.14 21.14 MB90950 Series Precautions when Using CAN Controller Use of the CAN controller requires the following precautions. ■ Precautions for Disabling Message Buffers by BVAL Bits When the message buffer is disabled by using the BVAL bit, CAN controller may not perform the proper receive/transmit operation. This section explains how to prevent such phenomenon. ● Condition When the following two conditions occur at the same time, the CAN controller will not perform to transmit messages normally. • CAN controller is participating in the CAN communication. (i.e. The read value of the CSR: HALT bit is "0" and CAN controller is participating in CAN bus communication to transmit and receive messages). • Message buffers are read and written when BVAL bits disable the message buffers. ● Work around Operation for suppressing transmission request Do not use BVAL bit for suppressing or stopping transmission request, use TCAN bit instead of it. Operation for composing transmission message Be sure to disable the message buffer by using the BVAL bit when setting the ID register or IDE register for composing the transmission message. In this case, perform the either of the following operations before disabling the message buffer by writing "0" to BVAL bit. • Read the transmission request bit (TREQ) to check that there is no transmit request (TREQ = 0) • Read the transmission complete bit (TC) to check that transmission has been completed (TC = 1) If transmit request was made in advance, be sure to verify that there is no pending transmit request before invaliding the message buffer. Never write "0" to BVAL bit until you check that transmit operation is not performed. a) Cancel the transmission request (TCANx=1;), if necessary b) and wait for the transmission completion (while (TREQx=1);) by polling or interrupt. Only after that the transmission buffer can be disabled (BVALx=0;). Note: For case a), if transmission of that buffer has already started, canceling the request is ignored and disabling the buffer is delayed until the end of the transmission. 606 FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E MB90950 Series CHAPTER 21 CAN CONTROLLER 21.14 ■ Notes on Using μDMAC and CAN Controllers Simultaneously • When the CAN controller is operable (CSR:HALT=0, and any of the BVALR:BVALx bits or TREQR:TREQx bits = 1), the μDMAC cannot be used to access the message buffer of the CAN controller by read or write operation. • To access the message buffer of the CAN controller by read or write operation using the μDMAC, make sure beforehand that the CAN controller is stopped (all of the BVALR:BVALx bits = 0, and also all of the TREQR:TREQx bits = 0 or CSR:HALT=1). CM44-10148-4E FUJITSU MICROELECTRONICS LIMITED 607 CHAPTER 21 CAN CONTROLLER 21.14 608 FUJITSU MICROELECTRONICS LIMITED MB90950 Series CM44-10148-4E CHAPTER 22 ADDRESS MATCH DETECTION FUNCTION This chapter explains the functions and operation of the address match detection function. 22.1 Overview of Address Match Detection Function 22.2 Block Diagram of Address Match Detection Function 22.3 Configuration of Address Match Detection Function 22.4 Explanation of Operation of Address Match Detection Function 22.5 Program Example of Address Match Detection Function CM44-10148-4E FUJITSU MICROELECTRONICS LIMITED 609 CHAPTER 22 ADDRESS MATCH DETECTION FUNCTION 22.1 22.1 MB90950 Series Overview of Address Match Detection Function If the address of the instruction to be processed next to the instruction currently processed by the program matches the address set in the detection address setting registers, the address match detection function forcibly replaces the next instruction to be processed by the program with the INT9 instruction to branch to the interrupt processing program. Since the address match detection function can use the INT9 interrupt for instruction processing, the program can be corrected by patch processing. ■ Overview of Address Match Detection Function • The address of the instruction to be processed next to the instruction currently processed by the program is always held in the address latch through the internal data bus. The address match detection function always compares the value of the address held in the address latch with that of the address set in the detection address setting registers. When these compared values match, the next instruction to be processed by the CPU is forcibly replaced with the INT9 instruction, and the interrupt processing program is executed. • There are six detection address setting registers (PADR0 to PADR5), each of which has an interrupt enable bit. The generation of an interrupt due to a match between the address held in the address latch and the address set in the detection address setting registers can be enabled or disabled for each register. 610 FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 22 ADDRESS MATCH DETECTION FUNCTION 22.2 MB90950 Series 22.2 Block Diagram of Address Match Detection Function The address match detection module consists of the following blocks: • Address latch • Address detection control register (PACSR0/PACSR1) • Detection address setting registers (PADR0 to PADR5) ■ Block Diagram of Address Match Detection Function Figure 22.2-1 shows the block diagram of the address match detection function. Figure 22.2-1 Block Diagram of Address Match Detection Function Address latch INT9 instruction (INT9 interrupt generation) Comparator Detection address setting register 0 PADR0 (24-bit) Detection address setting register 1 Internal data bus PADR1 (24-bit) Detection address setting register 5 PADR5 (24-bit) PACSR0 Reserved Reserved AD2E Reserved AD1E Reserved AD0E Reserved AD3E Reserved Address detection control register 0 (PACSR0) PACSR1 Reserved Reserved AD5E Reserved AD4E Reserved Address detection control register 1 (PACSR1) Reserved: Always set to "0". ● Address latch The address latch stores the value of the address output to the internal data bus. ● Address detection control register (PACSR0/PACSR1) The address detection control registers enable or disable output of an interrupt at an address match. ● Detection address setting registers (PADR0 to PADR5) The detection address setting registers set the address that is compared with the value of the address latch. CM44-10148-4E FUJITSU MICROELECTRONICS LIMITED 611 CHAPTER 22 ADDRESS MATCH DETECTION FUNCTION 22.3 22.3 MB90950 Series Configuration of Address Match Detection Function This section lists and details the registers used by the address match detection function. ■ List of Registers and Initial Values of Address Match Detection Function Figure 22.3-1 List of Registers and Initial Values of Address Match Detection Function bit 7 1 1 0 0 bit 15 14 13 12 Address detection control register 0 (PACSR0) Address detection control register 1 (PACSR1) 6 5 4 3 2 1 0 0 0 0 0 11 10 9 8 1 1 0 0 0 0 0 0 bit 7 6 5 4 3 2 1 0 bit 15 14 13 12 11 10 9 8 bit 7 6 5 4 3 2 1 0 bit 15 14 13 12 11 10 9 8 bit 7 6 5 4 3 2 1 0 bit 15 14 13 12 11 10 9 8 bit 7 6 5 4 3 2 1 0 bit 15 14 13 12 11 10 9 8 bit 7 6 5 4 3 2 1 0 bit 7 6 5 4 3 2 1 0 bit 15 14 13 12 11 10 9 8 bit 7 6 5 4 3 2 1 0 bit 15 14 13 12 11 10 9 8 bit 7 6 5 4 3 2 1 0 bit 15 14 13 12 11 10 9 8 bit 7 6 5 4 3 2 1 0 bit 15 14 13 12 11 10 9 8 bit 7 6 5 4 3 2 1 0 Detection address setting register 0 (PADR0): Lower Detection address setting register 0 (PADR0): Middle Detection address setting register 0 (PADR0): Upper Detection address setting register 1 (PADR1): Lower Detection address setting register 1 (PADR1): Middle Detection address setting register 1 (PADR1): Upper Detection address setting register 2 (PADR2): Lower Detection address setting register 2 (PADR2): Middle Detection address setting register 2 (PADR2): Upper Detection address setting register 3 (PADR3): Lower Detection address setting register 3 (PADR3): Middle Detection address setting register 3 (PADR3): Upper Detection address setting register 4 (PADR4): Lower Detection address setting register 4 (PADR4): Middle Detection address setting register 4 (PADR4): Upper Detection address setting register 5 (PADR5): Lower Detection address setting register 5 (PADR5): Middle Detection address setting register 5 (PADR5): Upper 612 FUJITSU MICROELECTRONICS LIMITED ×: Undefined CM44-10148-4E CHAPTER 22 ADDRESS MATCH DETECTION FUNCTION 22.3 MB90950 Series 22.3.1 Address Detection Control Register (PACSR0/PACSR1) The address detection control registers enable or disable output of an interrupt at an address match. If an address match is detected when output of an interrupt at an address match is enabled, the INT9 interrupt is generated. ■ Address Detection Control Register 0 (PACSR0) Figure 22.3-2 Address Detection Control Register 0 (PACSR0) Address bit 7 6 5 4 3 2 1 0 ReReReReRe00009EH served served AD2E served AD1E served AD0E served R/W R/W R/W R/W R/W R/W R/W R/W Initial value 11000000B bit0 Reserved 0 bit1 AD0E 0 1 Reserved bit Be sure to set this bit to "0". Address match detection enable bit 0 Disables address match detection in PADR0 Enables address match detection in PADR0 bit2 Reserved 0 bit3 AD1E 0 1 Reserved bit Be sure to set this bit to "0". Address match detection enable bit 1 Disables address match detection in PADR1 Enables address match detection in PADR1 bit4 Reserved 0 bit5 AD2E 0 1 Reserved bit Be sure to set this bit to "0". Address match detection enable bit 2 Disables address match detection in PADR2 Enables address match detection in PADR2 bit6 Reserved 0 Reserved bit Be sure to set this bit to "0". bit7 Reserved R/W : Readable/writable 0 Reserved bit Be sure to set this bit to "0". : Initial value CM44-10148-4E FUJITSU MICROELECTRONICS LIMITED 613 CHAPTER 22 ADDRESS MATCH DETECTION FUNCTION 22.3 MB90950 Series Table 22.3-1 Functions of Address Detection Control Register (PACSR0) Bit name bit7, bit6 Function Reserved: Reserved bits Be sure to set these bits to "0". bit5 AD2E: Address match detection enable bit 2 The address match detection operation with the detection address setting register 2 (PADR2) is enabled or disabled. When set to "0": Disables the address match detection operation. When set to "1": Enables the address match detection operation. When the value of detection address setting registers 2 (PADR2) matches with the value of address latch at enabling the address match detection operation (AD2E=1), the INT9 instruction is immediately executed. bit4 Reserved: Reserved bit Be sure to set this bit to "0". bit3 AD1E: Address match detection enable bit 1 The address match detection operation with the detection address setting register 1 (PADR1) is enabled or disabled. When set to "0": Disables the address match detection operation. When set to "1": Enables the address match detection operation. When the value of detection address setting registers 1 (PADR1) matches with the value of address latch at enabling the address match detection operation (AD1E=1), the INT9 instruction is immediately executed. bit2 Reserved: Reserved bit Be sure to set this bit to "0". bit1 AD0E: Address match detection enable bit 0 The address match detection operation with the detection address setting register 0 (PADR0) is enabled or disabled. When set to "0": Disables the address match detection operation. When set to "1": Enables the address match detection operation. When the value of detection address setting registers 0 (PADR0) matches with the value of address latch at enabling the address match detection operation (AD0E=1), the INT9 instruction is immediately executed. bit0 Reserved: Reserved bit Be sure to set this bit to "0". 614 FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 22 ADDRESS MATCH DETECTION FUNCTION 22.3 MB90950 Series ■ Address Detection Control Register 1 (PACSR1) Figure 22.3-3 Address Detection Control Register 1 (PACSR1) bit 15 Address 00003BH 14 13 12 11 10 9 8 ReReReReReserved served AD5E served AD4E served AD3E served R/W R/W R/W R/W R/W R/W R/W R/W Initial value 11000000B bit8 Reserved 0 bit9 AD3E 0 1 Reserved bit Be sure to set this bit to "0". Address match detection enable bit 3 Disables address match detection in PADR3 Enables address match detection in PADR3 bit10 Reserved 0 bit11 AD4E 0 1 Reserved bit Be sure set to this bit to "0". Address match detection enable bit 4 Disables address match detection in PADR4 Enables address match detection in PADR4 bit12 Reserved 0 bit13 AD5E 0 1 Reserved bit Be sure set to this bit to "0". Address match detection enable bit 5 Disables address match detection in PADR5 Enables address match detection in PADR5 bit14 Reserved 0 Reserved bit Be sure set to this bit to "0". bit15 Reserved R/W : Readable/writable 0 Reserved bit Be sure set to this bit to "0". : Initial value CM44-10148-4E FUJITSU MICROELECTRONICS LIMITED 615 CHAPTER 22 ADDRESS MATCH DETECTION FUNCTION 22.3 MB90950 Series Table 22.3-2 Functions of Address Detection Control Register (PACSR1) Bit name bit15, bit14 Function Reserved: Reserved bits Be sure to set these bits to "0". bit13 AD5E: Address match detection enable bit 5 The address match detection operation with the detection address setting register 5 (PADR5) is enabled or disabled. When set to "0": Disables the address match detection operation. When set to "1": Enables the address match detection operation. When the value of detection address setting registers 5 (PADR5) matches with the value of address latch at enabling the address match detection operation (AD5E=1), the INT9 instruction is immediately executed. bit12 Reserved: Reserved bit Be sure to set this bit to "0". bit11 AD4E: Address match detection enable bit 4 The address match detection operation with the detection address setting register 4 (PADR4) is enabled or disabled. When set to "0": Disables the address match detection operation. When set to "1": Enables the address match detection operation. When the value of detection address setting registers 4 (PADR4) matches with the value of address latch at enabling the address match detection operation (AD4E=1), the INT9 instruction is immediately executed. bit10 Reserved: Reserved bit Be sure to set this bit to "0". bit9 AD3E: Address match detection enable bit 3 The address match detection operation with the detection address setting register 3 (PADR3) is enabled or disabled. When set to "0": Disables the address match detection operation. When set to "1": Enables the address match detection operation. When the value of detection address setting registers 3 (PADR3) matches with the value of address latch at enabling the address match detection operation (AD3E=1), the INT9 instruction is immediately executed. bit8 Reserved: Reserved bit Be sure to set this bit to "0". 616 FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 22 ADDRESS MATCH DETECTION FUNCTION 22.3 MB90950 Series 22.3.2 Detection Address Setting Registers (PADR0 to PADR5) The value of an address to be detected is set in the detection address setting registers. When the address of the instruction processed by the program matches the address set in the detection address setting registers, the next instruction is forcibly replaced with the INT9 instruction, and the interrupt processing program is executed. ■ Detection Address Setting Registers (PADR0 to PADR5) Figure 22.3-4 Detection Address Setting Registers (PADR0 to PADR5) Address PADR5: Upper PADR2: Upper PADR5: Middle PADR2: Middle PADR5: Lower PADR2: Lower PADR4: Upper PADR1: Upper PADR4: Middle PADR1: Middle PADR4: Lower PADR1: Lower 0079F8H 0079E8H bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 D23 D22 D21 D20 D19 D18 D17 D16 0079F7H 0079E7H R/W R/W R/W R/W R/W R/W R/W R/W bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 D15 D14 D13 D12 D11 D10 D9 D8 0079F6H 0079E6H R/W R/W R/W R/W R/W R/W R/W R/W bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 0079F5H 0079E5H 0079F4H 0079E4H 0079F3H 0079E3H D23 D22 D21 D20 D19 D18 D17 D16 D13 D12 D11 D10 D9 D8 R/W R/W R/W R/W R/W R/W R/W R/W bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 PADR3: Upper PADR0: Upper PADR3: Middle PADR0: Middle PADR3: Lower PADR0: Lower 0079F2H 0079E2H 0079F1H 0079E1H 0079F0H 0079E0H D23 D22 D21 D20 D19 D18 D17 XXXXXXXXB Initial value XXXXXXXXB Initial value XXXXXXXXB Initial value XXXXXXXXB R/W R/W R/W R/W R/W R/W R/W R/W bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 D15 D14 Initial value Initial value XXXXXXXXB Initial value XXXXXXXXB Initial value D16 XXXXXXXXB R/W R/W R/W R/W R/W R/W R/W R/W bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 D15 D14 D13 D12 D11 D10 D9 D8 XXXXXXXXB R/W R/W R/W R/W R/W R/W R/W R/W bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 D7 D6 D5 D4 D3 D2 D1 D0 Initial value Initial value XXXXXXXXB R/W R/W R/W R/W R/W R/W R/W R/W R/W : Readable/writable X : Undefined CM44-10148-4E FUJITSU MICROELECTRONICS LIMITED 617 CHAPTER 22 ADDRESS MATCH DETECTION FUNCTION 22.3 MB90950 Series ■ Functions of Detection Address Setting Registers • There are six detection address setting registers (PADR0 to PADR5) that consist of a high byte (bank), middle byte, and low byte, totaling 24 bits. Table 22.3-3 Address Setting of Detection Address Setting Registers Register Name Detection address setting register 0 Interrupt Output Enabled PACSR0: AD0E (PADR0) Detection address setting register 1 PACSR0: AD1E (PADR1) Detection address setting register 2 PACSR0: AD2E (PADR2) Detection address setting register 3 PACSR1: AD3E (PADR3) Detection address setting register 4 PACSR1: AD4E (PADR4) Detection address setting register 5 (PADR5) PACSR1: AD5E Address Setting Upper Set the upper 8 bits of detection address 0 (bank) Middle Set the middle 8 bits of detection address 0 Lower Set the lower 8 bits of detection address 0 Upper Set the upper 8 bits of detection address 1 (bank) Middle Set the middle 8 bits of detection address 1 Lower Set the lower 8 bits of detection address 1 Upper Set the upper 8 bits of detection address 2 (bank) Middle Set the middle 8 bits of detection address 2 Lower Set the lower 8 bits of detection address 2 Upper Set the upper 8 bits of detection address 3 (bank) Middle Set the middle 8 bits of detection address 3 Lower Set the lower 8 bits of detection address 3 Upper Set the upper 8 bits of detection address 4 (bank) Middle Set the middle 8 bits of detection address 4 Lower Set the lower 8 bits of detection address 4 Upper Set the upper 8 bits of detection address 5 (bank) Middle Set the middle 8 bits of detection address 5 Lower Set the lower 8 bits of detection address 5 • In the detection address setting registers (PADR0 to PADR5), starting address (first byte) of instruction to be replaced with the INT9 instruction should be set. 618 FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 22 ADDRESS MATCH DETECTION FUNCTION 22.3 MB90950 Series Figure 22.3-5 Setting of Starting Address of Instruction Code to be Replaced with INT9 Instruction Set to detection address (Upper: FFH, Middle: 00H, Lower: 1FH) Address Instruction code FF001CH : FF001FH : FF0022H : A8 00 00 4A 00 00 4A 80 08 Mnemonic MOVW MOVW MOVW RW0,#0000 A,#0000 A,#0880 Notes: • When an address other than the first byte is set to the detection address setting registers (PADR0 to PADR5), the instruction code is not replaced with the INT9 instruction and a program of an interrupt processing is not be performed. When the address is set to the second byte or subsequent, the address set by the instruction code is replaced with "01H" (INT9 instruction code) and, which may cause malfunction. • The detection address setting registers (PADR0 to PADR5) should be set after disabling the address match detection (PACSR: AD0E to AD5E=0) of the corresponding address match control registers. If the detection address setting registers are changed without disabling the address match detection, the address match detection function will work immediately after an address match occurs during writing address, which may cause malfunction. • The address match detection function can be used only for addresses of the internal ROM area. If addresses of the external memory area are set, the address match detection function will not work and the INT9 instruction will not be executed. CM44-10148-4E FUJITSU MICROELECTRONICS LIMITED 619 CHAPTER 22 ADDRESS MATCH DETECTION FUNCTION 22.4 22.4 MB90950 Series Explanation of Operation of Address Match Detection Function If the addresses of the instructions executed in the program match those set in the detection address setting registers (PADR0 to PADR5), the address match detection function will replace the first instruction code executed by the CPU with the INT9 (01H) instruction to branch to the interrupt processing program. ■ Operation of Address Match Detection Function Figure 22.4-1 shows the operation of the address match detection function when the detection addresses are set and an address match is detected. Figure 22.4-1 Operation of Address Match Detection Function Program execution Address Address of the instruction to be executed by program matches detection address setting register 0 FF001CH : FF001FH : FF0022H : Instruction code Mnemonic RW0,#0000 MOVW A8 00 00 A,#0000 MOVW 4A 00 00 A,#0880 MOVW 4A 80 08 Replaced with the INT9 instruction (01H) ■ Setting Detection Address 1) Disable the detection address setting register 0 (PADR0) where the detection address is set for address match detection (PACSR0: AD0E=0). 2) Set the detection address in the detection address setting register 0 (PADR0). Set "FFH" at the upper bits, "00H" at the middle bits, and "1FH" at the lower bits of the detection address setting register 0 (PADR0). 3) Enable the detection address setting register 0 (PADR0) where the detection address is set for address match detection (PACSR0: AD0E=1). ■ Program Execution 1) If the address of the instruction to be executed in the program matches the set detection address, the first instruction code at the matched address is replaced with the INT9 instruction code ("01H"). 2) INT9 instruction is executed. INT9 interrupt is generated and then interrupt processing program is executed. 620 FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 22 ADDRESS MATCH DETECTION FUNCTION 22.4 MB90950 Series 22.4.1 Example of Using Address Match Detection Function This section gives an example of patch processing for program correction using the address match detection function. ■ System Configuration and E2PROM Memory Map ● System configuration Figure 22.4-2 gives an example of the system configuration using the address match detection function. Figure 22.4-2 Example of System Configuration Using Address Match Detection Function Serial E2PROM interface MCU E2PROM F2MC-16LX Storing patch program Pull-up resistor SIN CM44-10148-4E Connector (UART) Fetching patch program from the outside FUJITSU MICROELECTRONICS LIMITED 621 CHAPTER 22 ADDRESS MATCH DETECTION FUNCTION 22.4 MB90950 Series ■ E2PROM Memory Map Figure 22.4-3 shows the allocation of the patch program and data at storing the patch program in E2PROM. Figure 22.4-3 Allocation of E2PROM Patch Program and Data E2PROM Address PADR0 PADR1 PADR5 0000H Patch program byte count 0001H Detection address 0 (Lower) 0002H Detection address 0 (Middle) 0003H Detection address 0 (Upper) 0004H Patch program byte count 0005H Detection address 1 (Lower) 0006H Detection address 1 (Middle) 0007H Detection address 1 (Upper) • • • • • • 0014H Patch program byte count 0015H Detection address 5 (Lower) 0016H Detection address 5 (Middle) 0017H Detection address 5 (Upper) 0020H For patch program 1 For patch program 5 Patch program 0 (main body) 0030H Patch program 1 (main body) • • • • • • 0070H For patch program 0 Patch program 5 (main body) ● Patch program byte count The total byte count of the patch program (main body) is stored. If the byte count is "00H", it indicates that no patch program is provided. ● Detection address (24 bits) The address where the instruction code is replaced with the INT9 instruction code due to program error is stored. This address is set in the detection address setting registers (PADR0 to PADR5). ● Patch program (main body) The program executed by the INT9 interrupt processing when the program address matches the detection address is stored. Patch program 0 is allocated from any predetermined address. Patch program 1 is allocated from the address indicating <starting address of patch program 0 + total byte count of patch program 0>. It is same for the patch programs 2 to 5. 622 FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 22 ADDRESS MATCH DETECTION FUNCTION 22.4 MB90950 Series ■ Setting and Operating State ● Initial setting All the E2PROM data are cleared to "00H". ● Occurrence of program error • By using the connector (UART), information about the patch program is transmitted to the MCU (F2MC-16LX) from the outside according to the allocation of the E2PROM patch program and data. • The MCU (F2MC-16LX) stores the information received from outside in the E2PROM. ● Reset sequence • After reset, the MCU (F2MC-16LX) reads the byte count of the E2PROM patch program to check the presence or absence of the patch program. • If the byte count of the patch program is not "00H", the higher, middle and lower bits at detection addresses 0 to 5 are read and set in the detection address setting registers 0 to 5 (PADR0 to PADR5). The patch program (main body) is read according to the byte count of the patch program and written to RAM in MCU (F2MC-16LX). • The patch program (main body) is allocated to the address where the patch program is executed in the INT9 interrupt processing by the address match detection function. • Address match detection operation is enabled (PACSR: AD0E=1, AD1E=1 ... AD5E=1). ● INT9 interrupt processing • Interrupt processing is performed by the INT9 instruction. The MB90950 series has no interrupt request flag by address match detection. Therefore, if the stack information in the program counter is discarded, the detection address cannot be checked. When checking the detection address, check the value of program counter stacked in the interrupt processing routine. • The patch program is executed, branching to the normal program. CM44-10148-4E FUJITSU MICROELECTRONICS LIMITED 623 CHAPTER 22 ADDRESS MATCH DETECTION FUNCTION 22.4 MB90950 Series ■ Operation of Address Match Detection Function at Storing Patch Program in E2PROM Figure 22.4-4 shows the operation of the address match detection function at storing the patch program in E2PROM. Figure 22.4-4 Operation of Address Match Detection Function at Storing Patch Program in E2PROM 000000H (3) Patch program RAM Detection address setting registers E2PROM (1) Detection address setting (reset sequence) Serial E2PROM interface • Patch program byte count • Address for address detection • Patch program ROM (2) (4) Program error FFFFFF H (1) (2) (3) (4) 624 Execution of detection address setting of reset sequence and normal program Branch to patch program which expanded in RAM with INT9 interrupt processing by address match detection Patch program execution by branching of INT9 processing Execution of normal program which branches from patch program FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 22 ADDRESS MATCH DETECTION FUNCTION 22.4 MB90950 Series ■ Flow of Patch Processing for Patching Program Figure 22.4-5 shows the flow of patch processing for patch program using the address match detection function. Figure 22.4-5 Flow of Patch Processing for Patching Program MB90950 E2PROM Patch program byte count: 80H 000000 H I/O area 0000H 000100 H Register/RAM area 0001H Detection address (Lower): 00H 0002H Detection address (Middle): 80H 0003H Detection address (Upper): FFH 000400 H Patch program 000480 H RAM area RAM Stack area 0010H 000900 H Detection address setting registers Patch program 0090H FFFF H FF0000 H Program error FF8000 H ROM FF8050 H FFFFFFH YES Reset INT9 E2PROM: Read 00H Branch to patch program JMP 000400H Execution of patch program E2PROM : 0000H = 0 000400H to 000480H NO End of patch program JMP FF8050H Read detection address E2PROM: 0001H to 0003H ↓ MCU: Set to PADR0 Read patch program E2PROM: 0010H to 008FH ↓ MCU: 000400H to 000047FH Enable address match detection (PACSR: AD0E = 1) Execution of normal program NO CM44-10148-4E Program address = PADR0 YES INT9 FUJITSU MICROELECTRONICS LIMITED 625 CHAPTER 22 ADDRESS MATCH DETECTION FUNCTION 22.5 22.5 MB90950 Series Program Example of Address Match Detection Function This section gives a program example for the address match detection function. ■ Program Example of Address Match Detection Function ● Processing specification If the address of the instruction to be executed by the program matches the address set in the detection address setting register (PADR0), the INT9 instruction is executed. ● Coding example PACSR0 EQU PADRL EQU 00009EH 0079E0H PADRM EQU 0079E1H PADRH EQU 0079E2H ; ; ; ; ; ; ; Address detection Detection address Lower Detection address Middle Detection address Upper control register 0 setting register 0 setting register 0 setting register 0 ; ;---------Main program--------------------------------------CODE CSEG START: ; Stack pointer (SP), etc., ; already initialized MOV PADRL,#00H ; Set address detection register 0 ; (Lower) MOV PADRM,#00H ; Set address detection register 0 ; (Middle) MOV PADRH,#00H ; Set address detection register 0 ; (Upper) ; MOV I:PACSR0,#00000010B ;Enable address match • Processing by user • LOOP: • Processing by user • BRA LOOP ;---------Interrupt program---------------------------------WARI: • processing by user 626 FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E MB90950 Series CHAPTER 22 ADDRESS MATCH DETECTION FUNCTION 22.5 • RETI ; Return from interrupt processing CODE ENDS ;---------Vector setting------------------------------------VECT CSEG ABS=0FFH ORG 00FFD8H DSL WARI ORG 00FFDCH ; Set reset vector DSL START DB 00H ; Set to single-chip mode VECT ENDS END START CM44-10148-4E FUJITSU MICROELECTRONICS LIMITED 627 CHAPTER 22 ADDRESS MATCH DETECTION FUNCTION 22.5 628 FUJITSU MICROELECTRONICS LIMITED MB90950 Series CM44-10148-4E CHAPTER 23 ROM MIRRORING FUNCTION SELECT MODULE This chapter explains the functions and operations of the ROM mirroring function select module. 23.1 Overview of ROM Mirroring Function Select Module 23.2 ROM Mirroring Function Select Register (ROMM) CM44-10148-4E FUJITSU MICROELECTRONICS LIMITED 629 CHAPTER 23 ROM MIRRORING FUNCTION SELECT MODULE 23.1 23.1 MB90950 Series Overview of ROM Mirroring Function Select Module The ROM mirroring function select module provides a setting so that ROM data in the FF bank can be read by access to the 00 bank. ■ Block Diagram of ROM Mirroring Function Select Module Figure 23.1-1 Block Diagram of ROM Mirroring Function Select Module ROM Mirroring Function Select Register (ROMM) Internal data bus ReReReReReReReserved served served served served served served MI Address Address area 00 bank FF bank Data ROM 630 FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 23 ROM MIRRORING FUNCTION SELECT MODULE 23.1 MB90950 Series ■ Memory Space with ROM Mirroring Function Enabled/Disabled Figure 23.1-2 shows the availability of access to memory space when the ROM mirroring function is enabled or disabled. Figure 23.1-2 Memory Space with ROM Mirroring Function Enabled/Disabled Single chip Internal ROM/ external bus External ROM/ external bus ROM area ROM area ROM area (satellite) ROM area (satellite) ROM area (image of FF bank) ROM area (image of FF bank) Extended I/O area Extended I/O area Extended I/O area Generalpurpose register Generalpurpose register Generalpurpose register FFFFFFH Address #1 F78000H F70000H 010000 H 008000 H 007900 H : Internal Address #2 RAM 000100 H 0000F0H 000000 H RAM RAM : Access disabled I/O I/O I/O : External Product name MB90F952 Address #1 FC0000H Address #2 004000H MB90V950AJAS, MB90V950AMAS F80000H 007900H ■ List of Registers and Reset Values of ROM Mirroring Function Select Module Figure 23.1-3 List of Registers and Reset Values of ROM Mirroring Function Select Module bit ROM mirroring function select register (ROMM) CM44-10148-4E 15 14 13 12 11 10 9 8 1 1 1 1 1 1 0 1 FUJITSU MICROELECTRONICS LIMITED 631 CHAPTER 23 ROM MIRRORING FUNCTION SELECT MODULE 23.2 23.2 MB90950 Series ROM Mirroring Function Select Register (ROMM) The ROM mirroring function select register enables or disables the ROM mirroring function. When the ROM mirroring function is enabled, ROM data in the FF bank can be read by access to the 00 bank. ■ ROM Mirroring Function Select Register (ROMM) Figure 23.2-1 ROM Mirroring Function Select Register (ROMM) Address 14 15 13 12 00006FH 11 10 9 8 Reserved MI R/W W/R: Readable/Writable W: Write only : Undefined : Initial value Initial value 11111101B W bit8 MI ROM mirroring function select bit 0 ROM mirroring function disabled 1 ROM mirroring function enabled Table 23.2-1 Functions of ROM Mirroring Function Select Register (ROMM) Bit name Function bit15 to bit10 Undefined bits Read : The value is undefined. Write : No effect. bit9 Reserved bit Set to "0" on the writing operation. bit8 MI: ROM mirroring function select bit This bit enables or disables the ROM mirroring function. When set to "0" : Disables ROM mirroring function. When set to "1" : Enables ROM mirroring function. Note: While the ROM area at addresses "008000H" to "00FFFFH" is being used, access to the ROM mirroring function select register (ROMM) is prohibited. 632 FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 24 FLASH MEMORY This chapter explains the functions and operation of the flash memory. The following three methods are available for writing data to and erasing data from the flash memory: 1) Parallel programmer 2) Serial programmer 3) Executing programs to write/erase data This chapter explains executing programs to write/erase data. 24.1 Outline of Flash Memory 24.2 Block Diagram of the Entire Flash Memory 24.3 Sector Configuration of the Flash Memory 24.4 Write/Erase Modes 24.5 Flash Memory Control Status Register (FMCS) 24.6 Flash Memory Write Control Register (FWR0/FWR1) 24.7 Starting the Flash Memory Automatic Algorithm 24.8 Confirming the Automatic Algorithm Execution State 24.9 Detailed Explanation of Writing to and Erasing Flash Memory 24.10 Notes on Using Flash Memory 24.11 Flash Security Feature CM44-10148-4E FUJITSU MICROELECTRONICS LIMITED 633 CHAPTER 24 FLASH MEMORY 24.1 24.1 MB90950 Series Outline of Flash Memory The MB90950 series has two sets of flash memory. The first set of flash memory is called "main flash", which has a sector configuration of "64K × 2 + 48K × 2 + 8K × 2" and is located in the FFH to FCH banks on the CPU memory map. The second set of flash memory is called "satellite flash", which has a sector configuration of "8K × 4" and is located in the F7H bank on the CPU memory map. This configuration allows the user to execute a flash writing program on the main flash program and write data to or erase data from the satellite flash. The function of the flash memory interface circuit enables read access and program access from the CPU, just like the mask ROM. Data can be written to or erased from the flash memory via the flash memory interface circuit by an instruction operation from the CPU. This allows data to be rewritten during the implementation state by the internal CPU control, resulting in efficient program and data improvements. ■ Features of Flash Memory • Use of automatic program algorithm (Embedded Algorithm: Equivalent to MBM29LV200) • Erase pause/restart function provided • Detection of completion of writing/erasing using data polling or toggle bit functions • Detection of completion of writing/erasing using CPU interrupts • Sector erase function (any combination of sectors) • Minimum of 10,000 write/erase operations • Flash read cycle time (min.): 2 machine cycles Note: The manufacturer code and device code do not have the reading function. These codes cannot be accessed by the command. ■ Writing to/Erasing Flash Memory The same flash memory cannot be used to write/erase and read data at the same time. This means that when writing and erasing data from the main flash memory, only the write operation can be performed without accessing the program from the flash memory, by first copying the program stored in the flash memory and then executing it through RAM. When writing and erasing data from the satellite flash memory, the writing can be done by either executing the program on the main flash memory, or first copying the program stored in the flash memory and then executing it through RAM. Note: Do not place any program in the satellite flash memory. 634 FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 24 FLASH MEMORY 24.2 MB90950 Series 24.2 Block Diagram of the Entire Flash Memory This section shows a block diagram of the entire flash memory. ■ Block Diagram of the Entire Flash Memory Figure 24.2-1 shows a block diagram of the entire flash memory with the flash memory interface circuit included. Figure 24.2-1 Block Diagram of the Entire Flash Memory Flash memory interface circuit Port 0 Port 1 Port 2 Port 3 Port 4 Port 5 F2MC-16LX bus BYTE Flash memory BYTE CE CE OE OE WE WE AQ0 to AQ18 AQ0 to AQ18 DQ0 to DQ15 DQ0 to DQ15 INT RY/BY RY/BY RESET Write enable interrupt signal (to CPU) External reset signal RY/BY Write enable signal CM44-10148-4E FUJITSU MICROELECTRONICS LIMITED 635 CHAPTER 24 FLASH MEMORY 24.3 24.3 MB90950 Series Sector Configuration of the Flash Memory This section shows the sector configuration of the flash memory. ■ Sector Configuration of the Flash Memory Figure 24.3-1 shows the sector configuration of the flash memory. The addresses in the figure indicate the high-order and low-order addresses of each sector. Figure 24.3-1 Sector Configuration of the Flash Memory MB90F952 SA7 (8 Kbytes) SA6 (8 Kbytes) SA5 (48 Kbytes) Writer CPU FFFFFH FFFFFFH FDFFFH FFDFFFH FBFFFH FFBFFFH EFFFFH FEFFFFH DFFFFH FDFFFFH CFFFFH FCFFFFH C3FFFH FC3FFFH C1FFFH FC1FFFH BFFFFH FBFFFFH 77FFFH F77FFFH 75FFFH F75FFFH 73FFFH F73FFFH 71FFFH F71FFFH 70000H F70000H SA4 (64 Kbytes) SA3 (64 Kbytes) SA2 (48 Kbytes) SA1 (8 Kbytes) SA0 (8 Kbytes) Open area SB3 (8 Kbytes) SB2 (8 Kbytes) SB1 (8 Kbytes) SB0 (8 Kbytes) *: The writer address corresponds to the CPU address when data is programmed to flash memory by a parallel writer. This address is where programming and erasing are performed by a general-purpose writer. 636 FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 24 FLASH MEMORY 24.4 MB90950 Series 24.4 Write/Erase Modes The flash memory can be accessed in two different ways: flash memory mode and alternative mode. Flash memory mode enables data to be directly written to or erased from the external pins. Alternative mode enables data to be written to or erased from the CPU via the internal bus. Use the mode external pins to select the mode. ■ Flash Memory Mode The CPU stops when the mode pins are set to 111B while the reset signal is asserted. The flash memory interface circuit is connected directly to ports 0, 1, 2, 3, 4, and 5, enabling direct control from the external pins. This mode makes the MCU seem like a standard flash memory to the external pins, and write/erase can be performed using a flash memory programmer. In flash memory mode, all operations supported by the flash memory automatic algorithm can be used. ■ Alternative Mode The flash memory is located in the F7/FC to FF banks of the CPU memory space and, like ordinary mask ROM, can be read-accessed and program-accessed from the CPU via the flash memory interface circuit. Since writing/erasing the flash memory is performed by instructions from the CPU via the flash memory interface circuit, this mode allows rewriting even when the MCU is soldered on the target board. Note: Sector protection function such as standard flash memory MBM29LV200 does not contain in the flash memory mode. CM44-10148-4E FUJITSU MICROELECTRONICS LIMITED 637 CHAPTER 24 FLASH MEMORY 24.5 24.5 MB90950 Series Flash Memory Control Status Register (FMCS) The flash memory control status register (FMCS) functions are described below. ■ Flash Memory Control Status Register (FMCS) Figure 24.5-1 Flash Memory Control Status Register (FMCS) Address: 0000AEH 7 INTE 6 RDYINT 5 WE 4 3 2 1 0 Initial value ReReReReRDY served served served served R/W R/W R/W R 000X0000B R/W R/W R/W R/W bit0 Reserved bit Reserved 0 Be sure to set "0". bit1 Reserved bit Reserved 0 Be sure to set "0". bit2 Reserved bit Reserved 0 Be sure to set "0". bit3 Reserved bit Reserved 0 Be sure to set "0". bit4 RDY Flash memory write/erase status bit 0 Write/Erase operation executing (next write/erase operation disabled) 1 Write/erase operation completed (next write/erase operation enabled) bit5 WE Flash memory write/erase operations enable bit 0 Write/erase operation of flash memory area disabled 1 Write/erase operation of flash memory area enabled bit6 RDYINT Flash memory operation flag bit Reading Writing 0 Write/erase operation executing Clearing RDYINT bit 1 Write/erase operation completed No effect bit7 INTE R/W : Readable/writable R : Read only X : Undefined : Initial value 638 Flash memory write/erase interrupt enable bit 0 Disable interrupt at write/erase completion 1 Enable interrupt at write/erase completion FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 24 FLASH MEMORY 24.5 MB90950 Series Table 24.5-1 Function Description in the Control Status Register (FMCS) Bit name Function INTE: Flash memory write/erase interrupt enable bit This bit enables or disables an interrupt request output upon completion of the flash memory write/erase operation. When "1" is set, setting "1" in the flash memory operation flag bit (FMCS:RDYINT=1) causes an interrupt request to be output. RDYINT: Flash memory operation flag bit This bit shows the flash memory operation status. When the flash memory automatic algorithm ends upon completion of the flash memory write/ erase operation, this bit is set to "1". • When interrupt upon completion of writing/erasing the flash memory is enabled (FMCS:INTE=1), setting this bit to "1" causes an interrupt request to be generated. • When this bit is "0", writing/erasing the flash memory is disabled. When "0" is set, this bit is cleared. When "1" is set, operation is not affected. When using the read-modify-write (RMW) instruction, "1" is always read out. bit5 WE: Flash memory write/erase operations enable bit This bit enables or disables writing to/erasing flash memory area. This bit is set before starting the writing to/erasing flash memory command. When "0" is set, write/erase signal is not generated by executing the F7/FC to FF bank write/ erase command sequence. When "1" is set, write/erase to flash memory is enabled after executing the F7/FC to FF bank write/erase command sequence. • When performing no write/erase operation, set this bit to "0" to avoid write/erase flash memory in mistake. bit4 RDY: Flash memory write/erase status bit This bit shows status of writing/erasing flash memory. • While this bit is "0", flash memory write/erase operation is disabled. • Even while this bit is "0", a read/reset command such as sector erase pause is accepted. When writing/erasing operation is ended, "1" is set. bit3 to bit0 Reserved: Reserved bits Be sure to set these bits to "0". bit7 bit6 Note: This register can be accessed only with byte-access. CM44-10148-4E FUJITSU MICROELECTRONICS LIMITED 639 CHAPTER 24 FLASH MEMORY 24.5 MB90950 Series ■ Automatic Algorithm End Timing Figure 24.5-2 illustrates the relationship between the automatic algorithm end timing and the respective RDYINT and RDY bits. The RDYINT and RDY bits do not simultaneously change. Create the program to determine the end of the automatic algorithm with either of the bits. Figure 24.5-2 Relationship between Automatic Algorithm End Timing and RDYINT and RDY bits Automatic algorithm termination timing RDYINT bit RDY bit 1 machine cycle 640 FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 24 FLASH MEMORY 24.6 MB90950 Series 24.6 Flash Memory Write Control Register (FWR0/FWR1) The flash memory write control register (FWR0/FWR1) is a register located on the flash memory interface, which is used to set the function that prevents accidental writing to the flash memory. ■ Flash Memory Write Control Register (FWR0/FWR1) The flash memory write control register (FWR0/FWR1) contains write-enable/disable setting bits that correspond to each sector (SA0 to SA7, SB0 to SB3). The initial value indicates "0", which disables write operations. Writing "1" enables write operations for the corresponding sector. Writing "0" turns on the function to prevent accidental write operations. Therefore, once "0" is written, even if "1" is written afterwards, data cannot be written to that sector. If data must be rewritten, a reset must be performed. Figure 24.6-1 1M-bit Flash Memory Write Control Register (FWR0/FWR1) FWR0 Address:0079A2H FWR1 Address:0079A3H bit 7 6 5 4 3 2 1 0 SA7E SA6E SA5E SA4E SA3E SA2E SA1E SA0E bit (0) R/W (0) R/W (0) R/W (0) R/W (0) R/W (0) R/W (0) R/W (0) R/W 15 14 13 12 11 10 9 8 - - - - (0) R/W (0) R/W SB3E SB2E SB1E SB0E (0) R/W (0) R/W (0) R/W (0) R/W (0) R/W (0) R/W R/W :Readable/writable 0 :Write disabled [initial value] CM44-10148-4E FUJITSU MICROELECTRONICS LIMITED 641 CHAPTER 24 FLASH MEMORY 24.6 MB90950 Series Table 24.6-1 Function of Flash Memory Write Control Register (FWR0/FWR1) Bit name Function bit11 to Reserved bits Be sure to write "0" to these bits. The read value is undefined. bit8 These bits set the accidental write prevention function for each corresponding sector of the flash memory. Writing "1" enables writing to the corresponding sector. Writing "0" activates the accidental write prevention function for the corresponding sector. In addition, these bits are initialized to "0" (writing disabled) at a reset. Flash sector correspondence table of accidental write prevention function setting bits (2M-bit flash memory) bit15 to bit12, bit7 to bit0 SB3E to SA0E Accidental write prevention function setting bits Bit Bit name 15 14 13 12 7 6 5 4 3 2 1 0 SB3E SB2E SB1E SB0E SA7E SA6E SA5E SA4E SA3E SA2E SA1E SA0E Write disabled: Write enabled: Accidental write prevented: 642 Corresponding sector of flash memory SB3 SB2 SB1 SB0 SA7 SA6 SA5 SA4 SA3 SA2 SA1 SA0 "0" state. It is possible to write ("1") the register corresponding to each sector while "0" is not written in the flash memory write control register (FWR0/ FWR1) (post-reset state). "1" state. It is possible to write data to the corresponding sector. "0" state. Write operations cannot be enabled ("1"), even if "1" is written to the register corresponding to each sector while "0" is written in the flash memory write control register (FWR0/ FWR1). FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 24 FLASH MEMORY 24.6 MB90950 Series Figure 24.6-2 Examples of Write-disabled/-enabled State and Accidental Write Prevented State in Flash Memory Write Control Register (FWR0/FWR1) Writing to Initialization register Writing to register Initialization RST Accidental write prevented Write disabled Write disabled Accidental write prevented Write disabled Write disabled Accidental write prevented Write disabled Write disabled Write enabled SA0E SA1E SA2E Write disabled Write enabled Write disabled SA3E Write disabled: "0" state. It is possible to write ("1") the register corresponding to each sector while "0" is not written in the flash memory write control register (FWR0/FWR1) (post-reset state). Write enabled: "1" state. It is possible to write data to the corresponding sector. Accidental write prevented: "0" state. Write operations cannot be enabled ("1"), even if "1" is written to the register corresponding to each sector while "0" is written in the flash memory write control register (FWR0/ FWR1). CM44-10148-4E FUJITSU MICROELECTRONICS LIMITED 643 CHAPTER 24 FLASH MEMORY 24.6 MB90950 Series ■ Setup Flow of Flash Memory Write Control Register (FWR0/FWR1) After setting the FMCS:WE bit, set the flash memory write control register (FWR0/FWR1) to "1" for a sector to be written, and set the register to "0" for a sector to be prevented from being accidentally written. Also, as setup by a bit operation instruction is prohibited. Figure 24.6-3 Setup and Procedure of Accidental Write Prevention for Flash Memory Start writing FMCS:WE(bit5) Enable writing to flash memory FWR0/FWR1 Set accidental write prevention for flash memory (Sector to be prevented from accidental write: "0"; Sector to be written: "1") Write command sequence (1) YYYAAAH <- XXAAH (2) YYY554H <- XX55H (3) YYYAAAH <- XXA0H (4) Writing address <- writing data Read internal address Data polling (DQ7) Next address Data Data 0 Timing limit (DQ5) 1 Read internal address Data Data polling (DQ7) Data Write error Final address NO YES FMCS:WE(bit5) Disable writing to flash memory Complete writing 644 YYY : Upper 12 bits of any address that is not set to "0" (write disabled / accidental write prevented) in the flash memory write control register (FWR0/FWR1) within the flash memory area X: Any value FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 24 FLASH MEMORY 24.6 MB90950 Series ■ Setting FMCS:WE When writing to the flash memory, set FMCS:WE to "1" to enable write operations first, then set the flash memory control register (FWR0/FWR1). When FMCS:WE is set to disable write operations ("0"), no write operation is performed for the flash memory, even if such write operation is enabled by the flash memory write control register (FWR0/FWR1). CM44-10148-4E FUJITSU MICROELECTRONICS LIMITED 645 CHAPTER 24 FLASH MEMORY 24.7 24.7 MB90950 Series Starting the Flash Memory Automatic Algorithm Four types of commands are available for starting the flash memory automatic algorithm: Read/Reset, Write, Chip Erase, and Sector Erase. Control of suspend and restart is enabled for Sector Erase. ■ Command Sequence Table Table 24.7-1 lists the commands used for flash memory write/erase. All of the data written to the command register is in bytes, but use word access to write. The data in the high-order bytes at this time is ignored. Table 24.7-1 Command Sequence Table 1st bus write cycle Command sequence 2nd bus write cycle 3rd bus write cycle 4th bus write cycle 5th bus write cycle 6th bus write cycle Bus write access Address Data Address Data Address Data Address Data Address Data Address Data Read/Reset* 1 YYYXXXH XXF0H - - - - - - - - - - Read/Reset* 4 YYYAAAH XXAAH YYY554H XX55H YYYAAAH XXF0H RA RD - - - - Write 4 YYYAAAH XXAAH YYY554H XX55H YYYAAAH XXA0H PA PD - - - - Chip Erase 6 ZZZAAAH XXAAH ZZZ554H XX55H ZZZAAAH XX80H ZZZAAAH XXAAH ZZZ554H XX55H ZZZAAAH XX10H Sector Erase 6 YYYAAAH XXAAH YYY554H XX55H YYYAAAH XX80H YYYAAAH XXAAH YYY554H XX55H SA XX30H Suspension of Sector Erase Entering address YYYXXXH and data "XXB0H"suspends erase operation during Sector Erase. Restart of Sector Erase Entering address YYYXXXH and data "XX30H" restarts Erase after suspension of Sector Erase. RA: Reading address PA: Writing address SA: Sector address (specify any address in the sector) RD: Reading data PD: Writing data YYY: Upper 12 bits of any address that is not set to "0" (write disabled / accidental write prevented) in the flash memory write control register (FWR0/ FWR1) within the flash memory ZZZ: Upper 12 bits of any address within the flash memory *: Both of the two types of read/reset commands can reset the flash memory to the read mode. Notes: • The addresses in the table are values on the CPU memory map. All of the addresses and data are in hexadecimal notation. "X", however, refers to any value. • If the Chip Erase command is issued by accessing a write-enabled sector when write-enabled and write-disabled sectors coexist, the content of all the sectors is erased, including the write-disabled sectors. 646 FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 24 FLASH MEMORY 24.7 MB90950 Series ■ Notes on Issuing Commands The following points must be noted when issuing the commands on the Command Sequence Table. • Enable write operations for each sector before issuing the 1st command. If the above action is not taken, the command will not be recognized properly and it will be necessary to perform a reset to initialize the command sequencer in the flash memory. • If a Chip Erase command is issued for the main flash area (SA0 to SA7), the main flash area (SA0 to SA7) will be erased. If a Chip Erase command is issued for the satellite flash area (SB0 to SB3), the satellite flash area (SB0 to SB3) will be erased. • If a Read/Reset command is issued during the execution of the automatic algorithm, the Reset command will be ignored and the currently executing command will continue. CM44-10148-4E FUJITSU MICROELECTRONICS LIMITED 647 CHAPTER 24 FLASH MEMORY 24.8 24.8 MB90950 Series Confirming the Automatic Algorithm Execution State Because the write/erase flow of the flash memory is controlled using the automatic algorithm, the flash memory has hardware for posting its internal operating state and completion of operation. This automatic algorithm enables confirmation of the operating state of the built-in flash memory using the following hardware sequence flags. ■ Hardware Sequence Flags The hardware sequence flags are configured from the four-bit output of DQ7, DQ6, DQ5, and DQ3. The functions of these bits are those of the data polling flag (DQ7), toggle bit flag (DQ6), timing limit exceeded flag (DQ5), and sector erase timer flag (DQ3). The hardware sequence flags can therefore be used to confirm that writing or chip sector erase has been completed or that erase code write is valid. The hardware sequence flags can be referred by read-accessing the addresses of the target sectors in the flash memory after setting of the command sequence (see Table 24.7-1 in Section "24.7 Starting the Flash Memory Automatic Algorithm"). Table 24.8-1 lists the bit assignments of the hardware sequence flags. Table 24.8-1 Bit Assignments of Hardware Sequence Flags 648 Bit No. 7 6 5 4 3 2 1 0 Hardware sequence flags DQ7 DQ6 DQ5 − DQ3 − − − FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 24 FLASH MEMORY 24.8 MB90950 Series To determine whether automatic writing or chip sector erase is being executed, the hardware sequence flags can be checked or the status can be determined from the RDY bit of the flash memory control register (FMCS) that indicates whether writing has been completed. After writing/erasing has terminated, the state returns to the read/reset state. When creating a program, use one of the flags to confirm that automatic writing/erasing has terminated. Then, perform the next processing operation, such as data read. In addition, the hardware sequence flags can be used to confirm whether a second or subsequent sector erase code write is valid. The following sections describe each hardware sequence flag separately. Table 24.8-2 lists the functions of the hardware sequence flags. Table 24.8-2 Hardware Sequence Flag Functions State DQ7 DQ6 DQ5 DQ3 DQ7 → DATA:7 Toggle → DATA:6 0→ DATA:5 0→ DATA:3 0→1 Toggle 0→1 1 1 Toggle 0 0 0→1 Toggle 0→1 1 Sector erase wait → Erase started 1→0 Toggle 0 0→1 Erase → Sector erase suspended (sector being erased) 0→1 Toggle → 1 0 1→0 Sector erase suspend → Erase restarted (sector being erased) 1→0 1→ Toggle 0 0→1 DATA:7 DATA:6 DATA:5 DATA:3 DQ7 Toggle 1 0 0 Toggle 1 1 Write → Write completed (write address specified) Chip erase → Sector erase completed State change for normal operation Sector erase → Erase completed Timeout period Erase Sector erase suspended (sector not being erased) Abnormal operation Write Chip erase CM44-10148-4E FUJITSU MICROELECTRONICS LIMITED 649 CHAPTER 24 FLASH MEMORY 24.8 24.8.1 MB90950 Series Data Polling Flag (DQ7) The data polling flag (DQ7) uses the data polling function to post that the automatic algorithm is being executed or has terminated. ■ Data Polling Flag (DQ7) Table 24.8-3 and Table 24.8-4 list the state transitions of the data polling flag. Table 24.8-3 Data Polling Flag State Transitions (State Change for Normal Operation) Operating state Write → Completed Chip/sector erase → Completed Sector erase wait → Started Sector erase → Erase suspend (sector being erased) Sector erase suspend → Restarted (sector being erased) Sector erase suspended (sector not being erased) DQ7 DQ7 → DATA:7 0→ 1 0 0→ 1 1→ 0 DATA:7 Table 24.8-4 Data Polling Flag State Transitions (State Change for Abnormal Operation) Operating state Write operation Chip/sector erase operation DQ7 DQ7 0 ● Write Read-access during execution of the automatic write algorithm causes the flash memory to output the opposite data of bit7 last written, regardless of the value at the address specified by the address signal. Read-access at the end of the automatic write algorithm causes the flash memory to output bit7 of the read value of the address specified by the address signal. ● Chip/sector erase For a sector erase, read-access during execution of the chip erase/sector erase algorithm causes the flash memory to output 0 from the sector currently being erased. For a chip erase, read-access causes the flash memory to output "0" regardless of the value at the address specified by the address signal. Read-access at the end of the automatic erase algorithm causes the flash memory to output "1" in the same way. ● Sector erase suspend Read-access during a sector erase suspend causes the flash memory to output "1" if the address specified by the address signal belongs to the sector being erased. The flash memory outputs bit7 (DATA: 7) of the read value at the address specified by the address signal if the address specified by the address signal does not belong to the sector being erased. Referencing this flag together with the toggle bit flag (DQ6) enables a decision to be made on whether the flash memory is in the sector erase suspended state and which sector is being erased. Note: When the automatic algorithm is being started, read-access to the specified address is ignored. Since termination of the data polling flag (DQ7) can be accepted for a data read and other bits output, data read after the automatic algorithm has terminated should be performed after readaccess has confirmed that data polling has terminated. 650 FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 24 FLASH MEMORY 24.8 MB90950 Series 24.8.2 Toggle Bit Flag (DQ6) Like the data polling flag (DQ7), the toggle bit flag (DQ6) uses the toggle bit function to post that the automatic algorithm is being executed or has terminated. ■ Toggle Bit Flag (DQ6) Table 24.8-5 and Table 24.8-6 list the state transitions of the toggle bit flag. Table 24.8-5 Toggle Bit Flag State Transitions (State Change for Normal Operation) Operating state Write → Completed Chip/sector erase → Completed DQ6 Toggle → DATA:6 Toggle → Stop Sector erase wait → Started Sector erase → Erase suspend (sector being erased) Sector erase suspend → Restarted (sector being erased) Sector erase suspended (sector not being erased) Toggle Toggle → 1 1 → Toggle DATA:6 Table 24.8-6 Toggle Bit Flag State Transitions (State Change for Abnormal Operation) Operating state Write Chip/sector erase DQ6 Toggle Toggle ● Write and chip/sector erase Continuous read-access during execution of the automatic write algorithm and chip/sector erase algorithm causes the flash memory to toggle the "1" or "0" state alternately for every read cycle, regardless of the value at the address specified by the address signal. Continuous read-access at the end of the automatic write algorithm and chip/sector erase algorithm causes the flash memory to stop toggling bit6 and output bit6 (DATA: 6) of the read value of the address specified by the address signal. ● Sector erase suspend Read-access during a sector erase suspend causes the flash memory to output "1" if the address specified by the address signal belongs to the sector being erased. The flash memory outputs bit6 (DATA: 6) of the read value at the address specified by the address signal if the address specified by the address signal does not belong to the sector being erased. Reference: For a write, if the sector where data is to be written is rewrite-protected, the toggle bit terminates the toggle operation after approximately 2 μs and without any data being rewritten. For an erase, if all of the selected sectors are rewrite-protected, the toggle bit performs toggling for approximately 100 μs and then returns to the read/reset state without any data being rewritten. CM44-10148-4E FUJITSU MICROELECTRONICS LIMITED 651 CHAPTER 24 FLASH MEMORY 24.8 24.8.3 MB90950 Series Timing Limit Exceeded Flag (DQ5) The timing limit exceeded flag (DQ5) is used to post that execution of the automatic algorithm has exceeded the time (internal pulse count) prescribed in the flash memory. ■ Timing Limit Exceeded Flag (DQ5) Table 24.8-7 and Table 24.8-8 list the state transitions of the timing limit exceeded flag. Table 24.8-7 Timing Limit Exceeded Flag State Transitions (State Change for Normal Operation) Operating state Write → Completed Chip/sector erase → Completed DQ5 0 → DATA:5 0→ 1 Sector erase wait → Started Sector erase → Erase suspend (sector being erased) Sector erase suspend → Restarted (sector being erased) Sector erase suspended (sector not being erased) 0 0 0 DATA:5 Table 24.8-8 Timing Limit Exceeded Flag State Transitions (State Change for Abnormal Operation) Operating state Write Chip/sector erase DQ5 1 1 ● Write and chip/sector erase Read-access after write or chip/sector erase automatic algorithm activation causes the flash memory to output "0" if the time is within the prescribed time (time required for write/erase) or to output "1" if the prescribed time has been exceeded. Because this is done regardless of whether the automatic algorithm is being executed or has terminated, it is possible to determine whether write/erase was successful or unsuccessful. That is, when this flag outputs "1", writing can be determined to have been unsuccessful if the automatic algorithm is still being executed by the data polling function or toggle bit function. For example, writing "1" to a flash memory address where "0" has been written will cause the fail state to occur. In this case, the flash memory will lock and execution of the automatic algorithm will not terminate. In rare cases, it may terminate normally with writing "1". As a result, valid data will not be output from the data polling flag (DQ7). In addition, the toggle bit flag (DQ6) will exceed the time limit without stopping the toggle operation and the timing limit exceeded flag (DQ5) will output "1". Note that this state indicates that the flash memory is not faulty, but has not been used correctly. When this state occurs, execute the Reset command. 652 FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 24 FLASH MEMORY 24.8 MB90950 Series 24.8.4 Sector Erase Timer Flag (DQ3) The sector erase timer flag (DQ3) is used to post whether the automatic algorithm is being executed during the sector erase wait period after the Sector Erase command has been started. ■ Sector Erase Timer Flag (DQ3) Table 24.8-9 and Table 24.8-10 list the state transitions of the sector erase timer flag. Table 24.8-9 Sector Erase Timer Flag State Transitions (State Change for Normal Operation) Operating state Write → Completed Chip/sector erase → Completed DQ3 0 → DATA:3 1 Sector erase wait → Started Sector erase → Erase suspend (sector being erased) Sector erase suspend → Restarted (sector being erased) Sector erase suspended (sector not being erased) 0→1 1→ 0 0→ 1 DATA:3 Table 24.8-10 Sector Erase Timer Flag State Transitions (State Change for Abnormal Operation) Operating state Write Chip/sector erase DQ3 0 1 ● Sector erase Read-access after the Sector Erase command has been started causes the flash memory to output "0" if the automatic algorithm is being executed during the sector erase wait period, regardless of the value at the address specified by the address signal of the sector that issued the command. The flash memory outputs "1" if the sector erase wait period has been exceeded. When the data polling function or toggle bit function indicates that the erase algorithm is being executed, internally controlled erase has already started if this flag is "1". Continuous write of the sector erase codes or commands other than the Sector Erase Suspend command will be ignored until erase is terminated. If this flag is "0", the flash memory will accept write of additional sector erase codes. To confirm this, it is recommended that the state of this flag be checked before continuing to write sector erase codes. If this flag is "1" after the second state check, it is possible that additional sector erase codes may not be accepted. ● Suspending sector erase Read-access during execution of sector erase suspend causes the flash memory to output "0" if the address specified by the address signal belongs to the sector being erased. The flash memory outputs bit3 (DATA: 3) of the read value of the address specified by the address signal if the address specified by the address signal does not belong to the sector being erased. CM44-10148-4E FUJITSU MICROELECTRONICS LIMITED 653 CHAPTER 24 FLASH MEMORY 24.9 24.9 MB90950 Series Detailed Explanation of Writing to and Erasing Flash Memory This section describes each operation procedure of flash memory Read/Reset, Write, Chip Erase, Sector Erase, Sector Erase Suspend, and Sector Erase Restart when a command that starts the automatic algorithm is issued. ■ Detailed Explanation of Writing to and Erasing Flash Memory The flash memory executes the automatic algorithm by issuing a command sequence (see Table 24.7-1 in Section "24.7 Starting the Flash Memory Automatic Algorithm") for a write cycle to the bus to perform Read/Reset, Write, Chip Erase, Sector Erase, Sector Erase Suspend, or Sector Erase Restart operations. Each bus write cycle must be performed continuously. In addition, whether the automatic algorithm has terminated can be determined using the data polling or other function. At normal termination, the flash memory is returned to the read/reset state. Each operation of the flash memory is described in the following order: • Setting the read/reset state • Writing data • Erasing all data (erasing chips) • Erasing optional data (erasing sectors) • Suspending sector erase • Restarting sector erase 654 FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 24 FLASH MEMORY 24.9 MB90950 Series 24.9.1 Setting Flash Memory to the Read/Reset State This section describes the procedure for issuing the Read/Reset command to set the flash memory to the read/reset state. ■ Setting the Flash Memory to the Read/Reset State The flash memory can be set to the read/reset state by sending the Read/Reset command in the command sequence table (see Table 24.7-1 in Section "24.7 Starting the Flash Memory Automatic Algorithm") continuously to the target sector in the flash memory. The Read/Reset command has two types of command sequences that execute the first and fourth bus operations. However, there are no essential differences between these command sequences. The read/reset state is the initial state of the flash memory. When power is supplied on and when a command terminates normally, the flash memory is set to the read/reset state. In the read/reset state, other commands wait for input. In the read/reset state, data is read by regular read-access. As with the mask ROM, program access from the CPU is enabled. The Read/Reset command is not required to read data by a regular read. The Read/Reset command is mainly used to initialize the automatic algorithm in such cases as when a command does not terminate normally. CM44-10148-4E FUJITSU MICROELECTRONICS LIMITED 655 CHAPTER 24 FLASH MEMORY 24.9 24.9.2 MB90950 Series Writing Data to Flash Memory This section describes the procedure for issuing the Write command to write data to the flash memory. ■ Writing Data to the Flash Memory The data write automatic algorithm of the flash memory can be started by sending the Write command in the command sequence table (see Table 24.7-1 in Section "24.7 Starting the Flash Memory Automatic Algorithm") continuously to the target sector in the flash memory. When data write to the target address is completed in the fourth cycle, the automatic algorithm and automatic write are started. ● Specifying addresses Only even addresses can be specified as the write addresses specified in a write data cycle. Odd addresses cannot be written correctly. That is, writing to even addresses must be done in units of word data. Writing can be done in any order of addresses or even if the sector boundary is exceeded. However, the Write command writes only data of one word for each execution. ● Notes on writing data Writing cannot return data "0" to data "1". When data "1" is written to data "0", the data polling algorithm (DQ7) or toggle operation (DQ6) does not terminate and the flash memory elements are determined to be faulty. If the time prescribed for writing is thus exceeded, the timing limit exceeded flag (DQ5) is determined to be an error. Otherwise, the data is viewed as if dummy data "1" had been written. However, when data is read in the read/reset state, the data remains "0". Data "0" can be set to data "1" only by erase operations. All commands are ignored during execution of the automatic write algorithm. If a hardware reset is started during writing, the data of the written addresses will be unpredictable. ■ Writing to the Flash Memory Figure 24.9-1 is an example of the procedure for writing to the flash memory. The hardware sequence flags (see Section "24.8 Confirming the Automatic Algorithm Execution State") can be used to determine the state of the automatic algorithm in the flash memory. Here, the data polling flag (DQ7) is used to confirm that writing has terminated. The data read to check the flag is read from the address written to last. The data polling flag (DQ7) changes at the same time that the timing limit exceeded flag (DQ5) changes. For example, even if the timing limit exceeded flag (DQ5) is "1", the data polling flag bit (DQ7) must be rechecked. 656 FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 24 FLASH MEMORY 24.9 MB90950 Series Also for the toggle bit flag (DQ6), the toggle operation stops at the same time that the timing limit exceeded flag bit (DQ5) changes to "1". The toggle bit flag (DQ6) must therefore be rechecked. Figure 24.9-1 Example of the Flash Memory Write Procedure Start writing FMCS:WE(bit5) Enable writing to flash memory FWR0/FWR1 Set accidental write prevention for flash memory (Sector to be prevented from accidental write: "0"; Sector to be written: "1") Write command sequence (1) YYYAAAH <- XXAAH (2) YYY554H <- XX55H (3) YYYAAAH <- XXA0H (4) Writing address <- writing data Next address Read internal address Data polling (DQ7) 0 Data Timing limit (DQ5) 1 Read internal address Data Data polling (DQ7) Data Write error Final address YES FMCS : (bit5) Disable writing to flash memory Complete writing CM44-10148-4E NO YYY: Upper 12 bits of any address that is not set to "0" (write disabled / accidental write prevented) in the flash memory write control register (FWR0/FWR1) within the flash memory area X: Any value FUJITSU MICROELECTRONICS LIMITED 657 CHAPTER 24 FLASH MEMORY 24.9 24.9.3 MB90950 Series Erasing All Data from Flash Memory (Chip Erase) This section describes the procedure for erasing all data from the flash memory by issuing a Chip Erase command. ■ Erasing All Data from Flash Memory (Chip Erase) All data can be erased from the flash memory by sending repeatedly the Chip Erase command shown on the Command Sequence Table (see Table 24.7-1 in "24.7 Starting the Flash Memory Automatic Algorithm") to the corresponding sectors of both the main flash memory and the satellite flash memory. The Chip Erase command is executed in 6 bus operations. The Chip Erase operation starts upon the completion of the 6th writing cycle. For Chip Erase, the user does not have to write to the flash memory before the erase operation. During the execution of the automatic erase algorithm, the flash memory performs verification by writing "0" before erasing all of the cells automatically. ■ Notes on Chip Erase ● Areas to be erased by the Chip Erase command When the Chip Erase command is issued for the main flash area (SA0 to SA7), the main flash area (SA0 to SA7) will be erased. If the Chip Erase command is issued for the satellite flash area (SB0 to SB3), the satellite flash area (SB0 to SB3) will be erased. ● Note on coexistence of write-enabled and -disabled sectors If the Chip Erase command is issued by accessing a write-enabled sector when write-enabled and writedisabled sectors coexist, the content of all the sectors is erased, including the write-disabled sectors. 658 FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 24 FLASH MEMORY 24.9 MB90950 Series 24.9.4 Erasing Optional Data (Erasing Sectors) in the Flash Memory This section describes the procedure for issuing the Sector Erase command to erase optional data (erase sector) in the flash memory. Individual sectors can be erased. Multiple sectors can also be specified at one time. ■ Erasing Optional Data (Erasing Sectors) in the Flash Memory Optional sectors in the flash memory can be erased by sending the Sector Erase command in the command sequence table (see Table 24.7-1 in Section "24.7 Starting the Flash Memory Automatic Algorithm") continuously to the target sector in the flash memory. ● Specifying sectors The Sector Erase command is executed in six bus operations. Sector erase wait of minimum 50 μs is started by writing the sector erase code (30H) to an accessible even-numbered address in the target sector in the sixth cycle. To erase multiple sectors, write the erase code (30H) to the addresses in the target sectors after the above processing operation. ● Notes on specifying multiple sectors Erase is started when the sector erase wait period of minimum 50 μs terminates after the final sector erase code has been written. That is, to erase multiple sectors at one time, the address of the next erase sector and the erase code (sixth cycle of the command sequence) must be written within 50μs. Otherwise, the address and erase code may not be accepted. The sector erase timer (hardware sequence flag DQ3) can be used to check whether writing of the subsequent sector erase code is valid. At this time, specify so that the address used for reading the sector erase timer indicates the sector to be erased. ■ Sector Erase Procedure for Flash Memory The hardware sequence flags (see Section "24.8 Confirming the Automatic Algorithm Execution State") can be used to determine the state of the automatic algorithm in the flash memory. Figure 24.9-2 shows an example of the procedure for erasing sectors in the flash memory. Here, the toggle bit flag (DQ6) is used to confirm that erasing has terminated. Note that the data that is read to check the flag is read from the sector to be erased. The toggle bit flag (DQ6) stops the toggle operation at the same time that the timing limit exceeded flag (DQ5) is changed to 1. Therefore, even if the timing limit exceeded flag (DQ5) is 1, the toggle bit flag (DQ6) must be rechecked. The data polling flag (DQ7) also changes at the same time that the timing limit exceeded flag bit (DQ5) changes. As a result, the data polling flag (DQ7) must be rechecked. CM44-10148-4E FUJITSU MICROELECTRONICS LIMITED 659 CHAPTER 24 FLASH MEMORY 24.9 MB90950 Series Figure 24.9-2 Example of the Flash Memory Sector Erase Procedure Start erasing FMCS:WE(bit5) Enable erasing to flash memory Erase command sequence (1) YYYAAAH <- XXAAH (2) YYY554H <- XX55H (3) YYYAAAH <- XX80H (4) YYYAAAH <- XXAAH (5) YYY554H <- XX55H (6) Sector address <- Erase code (30H) YES Another erase sector? NO (6) Sector address <- Erase code (30H) Read internal address1 Read internal address Read internal address2 1 DQ3 Toggle bit (DQ6) Data 1 = Data 2 YES Erase specification has not been added within 50 μs. Set remainder re-execution flag, and terminate erase once NO 0 0 Timing limit (DQ5) 1 Read internal address Read internal address NO Toggle bit (DQ6) Data 1 = Data 2 YES Erase error Remainder re-execution flag? YES NO FMCS:WE(bit5) Disable erasing to flash memory Complete erasing 660 YYY: Upper 12 bits of any address that is not set to "0" (write disabled / accidental write prevented) in the flash memory write control register (FWR0) within the flash memory area X: Any value FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 24 FLASH MEMORY 24.9 MB90950 Series 24.9.5 Suspending Sector Erase of Flash Memory This section describes the procedure for issuing the Sector Erase Suspend command to suspend erasing of flash memory sectors. Data can be read from sectors that are not being erased. ■ Suspending Sector Erase of Flash Memory Erasing of flash memory sectors can be suspended by sending the Sector Erase Suspend command in the command sequence table (see Table 24.7-1 in Section "24.7 Starting the Flash Memory Automatic Algorithm") continuously to the target sector in the flash memory. The Sector Erase Suspend command suspends the sector erase operation being executed and enables data to be read from sectors that are not being erased and enables data to be written to sectors that are not being erased. This command is valid only during sector erase operations that include an erase wait time. The command will be ignored during chip erase or write operations. This command is implemented by writing the erase suspend code (B0H). At this time, specify an optional address in the flash memory for the address. An Erase Suspend command issued again during erasing of sectors will be ignored. Entering the Sector Erase Suspend command during the sector erase wait period will immediately terminate sector erase wait, cancel the erase operation, and set the erase stop state. Entering the Erase Suspend command during the erase operation after the sector erase wait period has terminated will set the erase suspend state after a maximum period of 20 μs has elapsed. Sector Erase Suspend command should be entered more than 20 μs after Sector Erase command or Sector Erase Restart command is issued. If Sector Erase Restart command will be issued less than 20 μs after Sector Erase Suspend command is issued, operations after restarting cannot be guaranteed. In the evaluation product, however, the restart command which is issued less than 20 μs is neglected. CM44-10148-4E FUJITSU MICROELECTRONICS LIMITED 661 CHAPTER 24 FLASH MEMORY 24.9 24.9.6 MB90950 Series Restarting Sector Erase of Flash Memory This section describes the procedure for issuing the Sector Erase Restart command to restart suspended erasing of flash memory sectors. ■ Restarting Sector Erase of Flash Memory Suspended erasing of flash memory sectors can be restarted by sending the Sector Erase Restart command in the command sequence table (see Table 24.7-1 in Section "24.7 Starting the Flash Memory Automatic Algorithm") continuously to the target sector in the flash memory. The Sector Erase Restart command is used to restart erasing of sectors from the sector erase suspend state set using the Sector Erase Suspend command. The Sector Erase Restart command is implemented by writing the erase restart code (30H). At this time, specify an optional address in the flash memory area for the address. If a Sector Erase Restart command is issued during sector erase, the command will be ignored. 662 FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 24 FLASH MEMORY 24.10 MB90950 Series 24.10 Notes on Using Flash Memory This section contains notes on using flash memory. ■ Notes on Using Flash Memory ● Entering hardware reset (RST) The "L" level width must be at least 500 ns to enter a hardware reset. ● When a reset is generated during a write/erase operation The write/erase sequence is initialized when a hardware reset or a low-voltage detection reset is generated. After recovering from the reset, the normal operation is performed. The data currently being written/erased becomes indefinite. Therefore, perform the write/erase operation again. Up to 20μs is required for the state machine of the flash memory that receives a hardware reset or a low-voltage detection reset to complete the reset and become readable. This is designed to discharge a high voltage, if such a voltage is used inside the flash memory. It is however only needed when a high voltage is used (when a command other than read/ reset command is issued). In case of a reset in any state other than above, up to 500ns is required to complete a flash memory reset. It takes 200ns from the cancellation of a reset until it becomes readable. The write/erase sequence is not initialized, when a software reset, watchdog timer reset or CPU operation detection reset is generated. After the completion of the write/erase sequence, the normal operation is performed. ● Program access to the main flash memory Read access to the flash memory during the operation of the automatic algorithm is prohibited. This means that no program must be executed in the main flash memory when the main flash memory is being written/ erased. To write to or erase the main flash memory, it is necessary to start the write/erase operation after switching the program area to another area such as RAM. In this case, if a sector containing an interrupt vector is erased, the write/erase interrupt process cannot be executed. Do not place any program in the satellite flash memory. ● Hold function When the CPU accepts a hold request, the write signal WE of the flash memory unit may be skewed, causing erroneous writing or erasing due to an erroneous write. When the acceptance of a hold request is enabled (HDE bit of the bus control signal selection register (ECSR) set to "1"), ensure that the WE bit of the control status register (FMCS) is "0". ● DMA transfer and extended intelligent I/O service (EI2OS) Because write and erase interrupts issued to the CPU from the flash memory interface circuit cannot be accepted by the DMA and EI2OS, they should not be used. ● Transition during write/erase mode Never transit to subclock mode and standby mode (time-base timer mode, watch mode, or stop mode) during the writing mode to flash memory (the WE bit of the control status register (FMCS) is "1"). CM44-10148-4E FUJITSU MICROELECTRONICS LIMITED 663 CHAPTER 24 FLASH MEMORY 24.11 24.11 MB90950 Series Flash Security Feature The flash security feature provides possibilities to protect the content of the flash memory. ■ Overview If the protection code of 01H is written in the security bit of flash memory, access to the flash memory is restricted. Once the flash memory is protected, performing the chip erase operation only can unlock the function otherwise read/write access to the flash memory from any external pins is not generally possible. This function is suitable for applications requiring security of self-containing program and data stored in the flash memory. Address of the security bit is depending on the flash memory size. Table 24.11-1 shows address of the security bit. Table 24.11-1 Address of Flash Security Bit MB90F952 Flash memory size Address of security bit 2M-bit flash memory installed FC0001H ■ Setting Security To set the security, write the protection code 01H in security bit and perform external reset or restart the system after power on. ■ Releasing Security The chip erase is executed, and after external reset or the power supply is turned on again, security is released. ■ Operation with Security Enabled Read : Invalid data is read. Write : No writing can be performed. ■ Other Information • For setting the general-purpose parallel programmer, see the specification of the general-purpose parallel programmer to be used. • Writing the protection code is generally recommended to take place at the end of the flash programming. This is to avoid unnecessary protection during the programming. Notes: • Security bit is allocated in the flash memory area. Writing the protection code 01H to security bit makes security enable. Therefore, do not write 01H in the address when the security feature is not used. • For address of the security bit, see Table 24.11-1. • Specifying sector of flash memory to set security for each sector cannot be performed. Security feature is only for all flash memory area. • When security enabled, the interrupt analysis of the flash memory cannot be performed. 664 FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 25 EXAMPLES OF SERIAL PROGRAMMING CONNECTION FOR FLASH MEMORY PRODUCTS This chapter shows examples of serial programming connection using the AF220/AF210/AF120/AF110 flash microcontroller programmers by Yokogawa Digital Computer Corporation. 25.1 Basic Configuration of Serial Programming Connection for Flash Memory Products 25.2 Example of Serial Programming Connection (User Power Supply Used) 25.3 Example of Serial Programming Connection (Power Supplied from Programmer) 25.4 Example of Minimum Connection to Flash Microcontroller Programmer (User Power Supply Used) 25.5 Example of Minimum Connection to Flash Microcontroller Programmer (Power Supplied from Programmer) CM44-10148-4E FUJITSU MICROELECTRONICS LIMITED 665 CHAPTER 25 EXAMPLES OF SERIAL PROGRAMMING CONNECTION FOR FLASH MEMORY PRODUCTS 25.1 25.1 MB90950 Series Basic Configuration of Serial Programming Connection for Flash Memory Products The AF220/AF210/AF120/AF110 support serial on-board writing (Fujitsu standard) of the flash ROM. This section provides the related specifications. ■ Basic Configuration of Serial Programming Connection Fujitsu standard serial on-board writing uses the AF220/AF210/AF120/AF110 flash microcontroller programmers by Yokogawa Digital Computer Corporation. You can use either program running in the single-chip mode or program running in the internal ROM/external bus mode. Figure 25.1-1 shows the basic configuration for the serial programming connection. Figure 25.1-1 Basic Configuration of Serial Programming Connection Host interface cable RS232C General-purpose common cable (AZ210) AF220/AF210/ AF120/AF110 flash microcontroller programmer + memory card CLK synchronous serial MB90950 series (flash memory product) User system Stand-alone operation enabled Note: For information on the functions of and operational procedures related to the flash microcontroller programmers (AF220/AF210/AF120/AF110), the general-purpose common cable (AZ210) for connection, and the connector, contact Yokogawa Digital Computer Corporation. 666 FUJITSU MICROELECTRONICS LIMITED CM44-10148-4E CHAPTER 25 EXAMPLES OF SERIAL PROGRAMMING CONNECTION FOR FLASH MEMORY PRODUCTS 25.1 MB90950 Series Table 25.1-1 Pin Used for Fujitsu Standard Serial On-Board Programming Pin MD2, MD1, MD0 X0, X1 P00, P01 Function Additional information Mode pins Controls the programming mode from the flash microcontroller programmer. Oscillation pins In programming mode, the CPU internal operation clock signal is one multiple of the PLL clock signal frequency. Therefore, because the oscillation clock frequency becomes the internal operation clock signal, the oscillator used for serial reprogramming is 3 MHz to 16 MHz. Programming activation pins Input "L" level to P00 and "H" level to P01. RST Reset pin SIN0 Serial data input pin SOT0 Serial data output pin SCK0 Serial clock input pin — Use UART0 as the CLK synchronous mode.