The following document contains information on Cypress products. FUJITSU SEMICONDUCTOR CONTROLLER MANUAL CM71-10133-1E FR Family 32-BIT MICROCONTROLLER MB91461 MB91F467R HARDWARE MANUAL FR Family 32-BIT MICROCONTROLLER MB91461 MB91F467R HARDWARE MANUAL Be sure to refer to the “Check Sheet” for the latest cautions on development. “Check Sheet” is seen at the following support page URL : http://www.fujitsu.com/global/services/microelectronics/product/micom/support/index.html “Check Sheet” lists the minimal requirement items to be checked to prevent problems beforehand in system development. FUJITSU LIMITED CONTENTS ■ Objectives and intended reader MB91461, MB91F467RA, and MB91F467RB are Fujitsu’s general-purpose 32-bit RISC microcontrollers designed for embedded control applications on consumer devices and other equipment that require highspeed real-time processing. These microcontrollers use FR60, which is compatible with the FR family, as their CPU. This series incorporates a built-in LIN-UART and CAN controller. Low-power consumption implementation by providing shut-down mode as a one of low-power consumption mode. Note: FR, the abbreviation of FUJITSU RISC controller, is a line of products of FUJITSU Limited. ■ Trademark The company names and brand names herein are the trademarks or registered trademarks of their respective owners. ■ I2C license Purchase of Fujitsu I2C components conveys a license under the Philips I2C Patent Rights to use, these components in an I2C system provided that the system conforms to the I2C Standard Specification as defined by Philips. ■ Organization of this manual This manual consists of the following 28 chapters and appendix. CHAPTER 1 OVERVIEW This chapter explains the basic information such as features, block diagram and overview of MB91461/ F467RA/F467RB. CHAPTER 2 HANDLING DEVICES This chapter describes precautions on handling FR family devices. CHAPTER 3 CPU AND CONTROL BLOCK This chapter provides basic information on FR family’s architecture, specifications and instructions to introduce its CPU core functions. CHAPTER 4 LOW-POWER CONSUMPTION MODE This chapter describes functions and operations of the low-power consumption modes. CHAPTER 5 CLOCK MODULATOR This chapter provides an overview of the Clock Modulator and its features. (This feature is not provided on MB91461.) CHAPTER 6 SUB OSCILLATION STABILIZATION WAIT TIMER This chapter describes the sub oscillation stabilization wait timer. (This feature is not provided on MB91461.) CHAPTER 7 HARDWARE WATCHDOG TIMER This chapter explains the functions of hardware watchdog timer. i CHAPTER 8 MEMORY CONTROLLER This section explains the control of the built-in flash memory installed in MB91F467RA and MB91F467RB. There is an explanation concerning the direct map cash that contributes at the instruction reading speed in the FLASH memory, too. CHAPTER 9 EXTERNAL BUS INTERFACE This chapter explains each function of the external bus interface. CHAPTER 10 I/O PORT This chapter describes I/O ports and the configuration and functions of the registers. CHAPTER 11 INTERRUPT CONTROLLER This chapter describes the overview of the interrupt controller, configuration and functions of the registers, and interrupt controller operation. CHAPTER 12 EXTERNAL INTERRUPT CONTROLLER This chapter describes the overview of the external interrupt controller, configuration and functions of the registers and external interrupt controller operation. CHAPTER 13 MPU / EDSU This chapter describes the memory protection features and embedded debug support features. CHAPTER 14 REALOS RELATED HARDWARE This chapter describes overview, configurations/functions of registers, and operations of REALOS. CHAPTER 15 DMAC (DMA CONTROLLER) This chapter describes the overview of the DMAC, configuration and functions of the registers, and DMAC operation. CHAPTER 16 CAN CONTROLLER This chapter describes the functions and operations of the CAN controller. CHAPTER 17 LIN-UART This chapter describes functions and operations of the LIN-compatible LIN-UART. CHAPTER 18 I2C INTERFACE This chapter describes overview, register configuration/function, and operation of the I2C interface. CHAPTER 19 16-BIT RELOAD TIMER This chapter describes the 16-bit reload timer, the configuration and functions of registers, and 16-bit reload timer operation. CHAPTER 20 16-BIT FREE-RUN TIMER This chapter describes the functions and operation of the 16-bit free-run timer. CHAPTER 21 INPUT CAPTURE This chapter describes the functions and operation of the input capture. CHAPTER 22 OUTPUT COMPARE UNIT This chapter describes the functions and operation of the output compare unit. CHAPTER 23 PPG (PROGRAMMABLE PULSE GENERATOR) This chapter describes the registers, function, and operation of the PPG. CHAPTER 24 REAL TIME CLOCK This chapter describes the register structure and functions, and the operation of RTC module for the real time clock. ii CHAPTER 25 A/D CONVERTER This chapter describes the overview, register configuration and function, and operation of the A/D converter. CHAPTER 26 SUB CLOCK CALIBRATION UNIT This section explains the sub clock calibration unit installed in MB91F467RA and MB91F467RB. CHAPTER 27 FLASH MEMOEY This chapter describes the use of the built-in flash memory. CHAPTER 28 FLASH SECURITY This section explains the security functions of the built-in flash memory installed in MB91F467RA and MB91F467RB. APPENDIX The appendix describes pin states in each CPU state, notes on using the little-endian areas, a list of FR family instructions, and notes on using MB91461, MB91F467RA, MB91F467RB. iii • • • • • • The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of FUJITSU semiconductor device; FUJITSU does not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. FUJITSU assumes no liability for any damages whatsoever arising out of the use of the information. Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of FUJITSU or any third party or does FUJITSU warrant non-infringement of any third-party's intellectual property right or other right by using such information. FUJITSU assumes no liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use of information contained herein. The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). Please note that FUJITSU will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the prior authorization by Japanese government will be required for export of those products from Japan. Copyright © 2007 FUJITSU LIMITED All rights reserved iv CONTENTS CHAPTER 1 1.1 1.2 1.3 1.4 1.5 1.6 CHAPTER 2 2.1 2.2 OVERVIEW ................................................................................................... 1 Overview ............................................................................................................................................. 2 Block Diagram .................................................................................................................................... 5 Package Dimensions .......................................................................................................................... 6 Pin Assignment Diagram .................................................................................................................... 7 Pin Descriptions ................................................................................................................................ 10 I/O Circuit Types ............................................................................................................................... 23 HANDLING DEVICES ................................................................................ 27 Precautions on Handling Devices ..................................................................................................... 28 Precautions for Use .......................................................................................................................... 32 CHAPTER 3 CPU AND CONTROL BLOCK ................................................................... 37 3.1 Memory Space .................................................................................................................................. 3.2 Internal Architecture .......................................................................................................................... 3.2.1 Overview of Instructions .............................................................................................................. 3.3 Instruction Cache (Installed on MB91461) ........................................................................................ 3.3.1 Control Register ........................................................................................................................... 3.3.2 Cache State And Various Operating Modes ................................................................................ 3.3.3 Setting Up the Instruction Cache before Use .............................................................................. 3.4 Programming Model ......................................................................................................................... 3.4.1 General-purpose Registers ......................................................................................................... 3.4.2 Dedicated Registers .................................................................................................................... 3.5 Data Structure ................................................................................................................................... 3.6 Memory Map ..................................................................................................................................... 3.7 Branch Instructions ........................................................................................................................... 3.7.1 Branch Instructions with a Delay Slot .......................................................................................... 3.7.2 Branch Instructions without a Delay Slot ..................................................................................... 3.8 EIT (Exception, Interrupt, and Trap) ................................................................................................. 3.8.1 EIT Interrupt Levels ..................................................................................................................... 3.8.2 Interrupt Control Register (ICR) ................................................................................................... 3.8.3 System Stack Pointer (SSP) ........................................................................................................ 3.8.4 Table Base Register (TBR) ......................................................................................................... 3.8.5 Multiple EIT Processing ............................................................................................................... 3.8.6 EIT Operation .............................................................................................................................. 3.9 Operating Modes .............................................................................................................................. 3.9.1 Bus Mode .................................................................................................................................... 3.9.2 Mode Setting ............................................................................................................................... 3.10 Reset (Device Initialization) .............................................................................................................. 3.10.1 Reset Level .................................................................................................................................. 3.10.2 Reset Source ............................................................................................................................... 3.10.3 Reset Sequence .......................................................................................................................... 3.10.4 Oscillation Stabilization Wait Time .............................................................................................. v 38 39 43 45 48 52 54 56 57 58 65 67 68 69 71 72 73 75 76 77 78 80 84 85 86 89 90 91 93 94 3.10.5 Reset Operation Modes ............................................................................................................... 96 3.11 Clock Generation Control ................................................................................................................. 97 3.11.1 PLL Control .................................................................................................................................. 98 3.11.2 Oscillation Stabilization Wait Time and PLL Lock Wait Time ...................................................... 99 3.11.3 Clock Distribution ....................................................................................................................... 101 3.11.4 Clock Division ............................................................................................................................ 103 3.11.5 Block Diagram of Clock Generation Control Block .................................................................... 104 3.11.6 Registers in the Clock Generation Control Block ...................................................................... 105 3.11.7 Peripheral Circuits in the Clock Control Block ........................................................................... 125 3.12 PLL Interface .................................................................................................................................. 128 3.12.1 Registers for the PLL Interface .................................................................................................. 129 3.12.2 Examples of PLL Multiply Rate Setting ..................................................................................... 136 3.13 Device State Control ....................................................................................................................... 140 3.13.1 Device States and Transitions ................................................................................................... 141 3.14 Interval Timer .................................................................................................................................. 145 CHAPTER 4 4.1 4.2 4.3 4.4 Overview of Low-Power Consumption Mode .................................................................................. Sleep Mode ..................................................................................................................................... Stop Mode ...................................................................................................................................... Shut-down Mode ............................................................................................................................. CHAPTER 5 5.1 5.2 5.3 SUB OSCILLATION STABILIZATION WAIT TIMER .............................. 177 178 179 180 181 183 186 189 HARDWARE WATCHDOG TIMER .......................................................... 191 Overview of Hardware Watchdog Timer ......................................................................................... Configuration of Hardware Watchdog Timer .................................................................................. Hardware Watchdog Timer Register .............................................................................................. Function of Hardware Watchdog Timer .......................................................................................... Notes on Using Hardware Watchdog Timer ................................................................................... CHAPTER 8 8.1 8.2 8.3 CLOCK MODULATOR ............................................................................ 163 Overview of Sub Oscillation Stabilization Wait Timer ..................................................................... Configuration of Sub Oscillation Stabilization Wait Timer ............................................................... Registers of Sub Oscillation Stabilization Wait Timer ..................................................................... WPCRH: Sub Oscillation Stabilization Timer Control Register .................................................. Operation of Sub Oscillation Stabilization Wait Timer .................................................................... Application Note .............................................................................................................................. Caution when Using Sub Oscillation Stabilization Wait Timer ........................................................ CHAPTER 7 7.1 7.2 7.3 7.4 7.5 152 153 155 157 Overview of Clock Modulator .......................................................................................................... 164 Clock Modulator Registers .............................................................................................................. 165 Application Note .............................................................................................................................. 175 CHAPTER 6 6.1 6.2 6.3 6.3.1 6.4 6.5 6.6 LOW-POWER CONSUMPTION MODE ................................................... 151 192 193 194 196 199 MEMORY CONTROLLER ........................................................................ 201 Overview of Memory Controller. ..................................................................................................... 202 Registers ......................................................................................................................................... 203 Explanations of Registers ............................................................................................................... 204 vi 8.4 FLASH access timing settings ........................................................................................................ 216 CHAPTER 9 9.1 9.2 9.2.1 9.2.2 9.2.3 9.2.4 9.2.5 9.2.6 9.2.7 9.3 9.4 9.4.1 9.4.2 9.4.3 9.5 9.6 9.7 9.8 EXTERNAL BUS INTERFACE ................................................................ 219 Features of External Bus Interface ................................................................................................. External Bus Interface Registers .................................................................................................... Area Select Register (ASR0 to ASR4) ...................................................................................... Area Configuration Register (ACR0 to ACR4) ........................................................................... Area Wait Register (AWR0 to AWR4) ....................................................................................... I/O Wait Register for DMAC (IOWR0 to IOWR2) ...................................................................... Chip Select Enable Register (CSER) ........................................................................................ CacHe Enable Register (CHER) ............................................................................................... Terminal and Timing Control Register (TCR) ............................................................................ Chip Select Area ............................................................................................................................. Endian and Bus Access .................................................................................................................. Big Endian Bus Access ............................................................................................................. Little Endian Bus Access ........................................................................................................... Comparison Of External Accesses In Big Endian and Little Endian .......................................... Normal Bus Interface ...................................................................................................................... Address/Data Multiplex Interface .................................................................................................... DMA Access ................................................................................................................................... Procedure for Setting Registers ...................................................................................................... 220 223 224 225 231 237 240 241 242 244 246 247 252 257 261 269 273 276 CHAPTER 10 I/O PORT .................................................................................................. 277 10.1 10.2 10.3 10.4 10.5 10.6 Overview of I/O Ports ...................................................................................................................... Port Input Enable ............................................................................................................................ I/O Port Data Register .................................................................................................................... Setting of Port Function Register .................................................................................................... Selection of Pin Input Level ............................................................................................................ Pull-up and Pull-down Control Register .......................................................................................... 278 282 283 286 310 313 CHAPTER 11 INTERRUPT CONTROLLER .................................................................... 317 11.1 Overview of the Interrupt Controller ................................................................................................ 11.2 Interrupt Controller Registers .......................................................................................................... 11.2.1 Interrupt Control Register (ICR) ................................................................................................. 11.2.2 HRCL (Hold Request Cancellation Request Register) ............................................................... 11.3 Interrupt Controller Operation ......................................................................................................... 318 322 323 324 325 CHAPTER 12 EXTERNAL INTERRUPT CONTROLLER ................................................ 335 12.1 Overview of the External Interrupt Controller................................................................................... 12.2 External Interrupt Controller Registers ............................................................................................ 12.2.1 External Interrupt Enable Register (ENIR) ................................................................................. 12.2.2 External Interrupt Factor Register (EIRR) .................................................................................. 12.2.3 External Interrupt Request Level Setting Register (ELVR) ........................................................ 12.3 Operation of the External Interrupt Controller.................................................................................. vii 336 338 339 340 341 342 CHAPTER 13 MPU / EDSU .............................................................................................. 347 13.1 Overview ......................................................................................................................................... 13.2 Break Functions............................................................................................................................... 13.2.1 Instruction Address Break .......................................................................................................... 13.2.2 Operand Address Break ............................................................................................................. 13.2.3 Data Value Break ....................................................................................................................... 13.2.4 Using Operand with Data Break ................................................................................................ 13.2.5 Memory Protection .................................................................................................................... 13.2.6 Break Factors ............................................................................................................................ 13.3 EDSU Registers .............................................................................................................................. 13.3.1 EDSU Control Register (BCTRL) ............................................................................................... 13.3.2 EDSU Status Register (BSTAT) ................................................................................................. 13.3.3 EDSU Break Detection Interrupt Request Register (BIRQ)........................................................ 13.3.4 EDSU Channel Configuration Register (BCR0 to BCR7) .......................................................... 13.3.5 Break Address/Data Register (BAD0 to BAD31) ....................................................................... 13.4 Quick Reference .............................................................................................................................. 348 349 350 352 355 357 358 360 361 364 368 372 374 383 384 CHAPTER 14 REALOS RELATED HARDWARE ........................................................... 387 14.1 Delayed Interrupt Module ............................................................................................................... 14.1.1 Overview of Delayed Interrupt Module ...................................................................................... 14.1.2 Delayed Interrupt Module Register ............................................................................................ 14.1.3 Operation of the Delayed Interrupt Module ............................................................................... 14.2 Bit Search Module .......................................................................................................................... 14.2.1 Overview of Bit Search Module ................................................................................................. 14.2.2 Bit Search Module Registers ..................................................................................................... 14.2.3 Operation of the Bit Search Module .......................................................................................... 388 389 390 391 392 393 394 396 CHAPTER 15 DMAC (DMA CONTROLLER) .................................................................. 399 15.1 Overview of DMAC (DMA Controller) ............................................................................................. 400 15.2 Detailed Explanation of the DMAC (DMA Controller) Registers ..................................................... 403 15.2.1 DMAC-ch.0, ch.1, ch.2, ch.3, ch.4 Control/Status Registers A ................................................. 404 15.2.2 DMAC-ch.0, ch.1, ch.2, ch.3, ch.4 Control/Status Registers B ................................................. 408 15.2.3 DMAC-ch.0, ch.1, ch.2, ch.3, ch.4 Transfer Source/Transfer Destination Address Setting Registers ................................................................................................................................................. 414 15.2.4 DMAC-ch.0, ch.1, ch.2, ch.3, ch.4 DMAC All-Channel Control Register ................................... 416 15.3 Explanation of the DMAC (DMA Controller) Operation ................................................................... 418 15.3.1 Operational Overview of DMAC (DMA Controller) .................................................................... 419 15.3.2 Transfer Request Setting ........................................................................................................... 421 15.3.3 Transfer Sequence .................................................................................................................... 422 15.3.4 DMA Transfer in General ........................................................................................................... 424 15.3.5 Addressing Mode ....................................................................................................................... 426 15.3.6 Data Types ................................................................................................................................ 427 15.3.7 Transfer Number Control ........................................................................................................... 428 15.3.8 CPU Control .............................................................................................................................. 429 15.3.9 Starting Operation ..................................................................................................................... 430 15.3.10 Transfer Request Acceptance and Transfer .............................................................................. 431 15.3.11 Clearing Peripheral Interrupts by DMA ...................................................................................... 432 viii 15.3.12 Temporary Stop ......................................................................................................................... 15.3.13 Operation End/Stop ................................................................................................................... 15.3.14 Error Stop .................................................................................................................................. 15.3.15 DMAC Interrupt Control ............................................................................................................. 15.3.16 DMA Transfer during Sleep Mode ............................................................................................. 15.3.17 Channel Selection and Control .................................................................................................. 15.4 Operational Flow of DMAC (DMA Controller) ................................................................................. 15.5 Data Path of DMAC (DMA Controller) ............................................................................................ 433 434 435 436 437 438 440 442 CHAPTER 16 CAN CONTROLLER ................................................................................ 445 16.1 Features of CAN ............................................................................................................................. 16.2 CAN Block Diagram ........................................................................................................................ 16.3 CAN Registers ................................................................................................................................ 16.4 CAN Register Functions ................................................................................................................. 16.4.1 General Control Register ........................................................................................................... 16.4.1.1 CAN Control Register (CTRLR)............................................................................................... 16.4.1.2 CAN Status Register (STATR) ................................................................................................ 16.4.1.3 CAN Error Counter (ERRCNT) ............................................................................................... 16.4.1.4 CAN Bit Timing Register (BTR) ............................................................................................... 16.4.1.5 CAN Interrupt Register (INTR) ................................................................................................ 16.4.1.6 CAN Test Register (TESTR) .................................................................................................. 16.4.1.7 CAN Prescaler Expansion Register (BRPER)......................................................................... 16.4.2 Message Interface Register ....................................................................................................... 16.4.2.1 IFx Command Request Register (IFxCREQ) ......................................................................... 16.4.2.2 IFx Command Mask Register (IFxCMSK) .............................................................................. 16.4.2.3 IFx Mask Registers 1, 2 (IFxMSK1, IFxMSK2)........................................................................ 16.4.2.4 IFx Arbitration Registers 1, 2 (IFxARB1, IFxARB2)................................................................. 16.4.2.5 IFx Message Control Register (IFxMCTR) ............................................................................. 16.4.2.6 IFx Data Registers A1, A2, B1, B2 (IFxDTA1, IFxDTA2, IFxDTB1, IFxDTB2) ........................ 16.4.3 Message Object ......................................................................................................................... 16.4.4 Message Handler Register ........................................................................................................ 16.4.4.1 CAN Transmission Request Register (TREQR1, TREQR2) .................................................. 16.4.4.2 CAN Data Update Register (NEWDT1, NEWDT2) ................................................................. 16.4.4.3 CAN Interrupt Pending Register (INTPND1, INTPND2) ......................................................... 16.4.4.4 CAN Message Validation Register (MSGVAL1, MSGVAL2) .................................................. 16.4.5 CAN Prescaler Register (CANPRE) ........................................................................................... 16.5 CAN Controller Functions ................................................................................................................ 16.5.1 Message Object.......................................................................................................................... 16.5.2 Message Transmission Operation .............................................................................................. 16.5.3 Message Reception Operation ................................................................................................... 16.5.4 FIFO Buffer Function ................................................................................................................. 16.5.5 Interrupt Function ...................................................................................................................... 16.5.6 Bit Timing.................................................................................................................................... 16.5.7 Test Mode .................................................................................................................................. 16.5.8 Software Initialization ................................................................................................................. 16.5.9 CAN Clock Prescaler ................................................................................................................. ix 446 447 448 455 456 457 460 463 464 466 468 470 471 472 475 480 481 482 483 484 490 491 493 495 497 499 501 502 504 506 510 512 514 517 522 523 CHAPTER 17 LIN-UART .................................................................................................. 527 17.1 Overview of LIN-UART .................................................................................................................... 17.2 Configuration of LIN-UART.............................................................................................................. 17.3 LIN-UART Registers ....................................................................................................................... 17.3.1 Serial Control Register (SCR) .................................................................................................... 17.3.2 Serial Mode Register (SMR) ...................................................................................................... 17.3.3 Serial Status Register (SSR) ..................................................................................................... 17.3.4 Transmission/Reception Data Registers (RDR/TDR)................................................................. 17.3.5 Extended Status/Control Register (ESCR) ................................................................................ 17.3.6 Extended Communication Control Register (ECCR) .................................................................. 17.3.7 Baud Rate/Reload Counter Register (BGR) .............................................................................. 17.4 LIN-UART Interrupts ....................................................................................................................... 17.4.1 Reception Interrupt Generation and Flag Set Timing ................................................................. 17.4.2 Transmission Interrupt Generation and Flag Timing .................................................................. 17.5 LIN-UART Baud Rate Setting .......................................................................................................... 17.5.1 Baud Rate Setting ...................................................................................................................... 17.5.2 Restarting Reload Counter ......................................................................................................... 17.6 LIN-UART Operations ..................................................................................................................... 17.6.1 Operation in Asynchronous Mode (Operation Modes 0 and 1) ................................................. 17.6.2 Operation in Synchronous Mode (Operation Mode 2) ............................................................... 17.6.3 Operation with LIN Function (Operation Mode 3) ...................................................................... 17.6.4 Direct Access to Serial Pins ...................................................................................................... 17.6.5 Bidirectional Communication Function (Normal Mode) ............................................................. 17.6.6 Master/Slave Communication Function (Multiprocessor Mode) ................................................ 17.6.7 LIN Communication Function .................................................................................................... 17.6.8 Sample Flowchart for LIN-UART in LIN Communication Mode (Operation Mode 3) ................. 17.7 Notes on Using LIN-UART .............................................................................................................. 528 531 536 538 541 544 547 549 552 555 557 561 563 565 567 570 572 574 576 579 583 584 585 588 589 592 CHAPTER 18 I2C INTERFACE ........................................................................................ 595 18.1 I2C Interface Overview .................................................................................................................... 18.2 I2C Interface Register ..................................................................................................................... 18.2.1 Bus Status Register (IBSR) ....................................................................................................... 18.2.2 Bus Control Register (IBCR) ..................................................................................................... 18.2.3 Clock Control Register (ICCR) .................................................................................................. 18.2.4 10-bit Slave Address Register (ITBA) ........................................................................................ 18.2.5 10-bit Slave Address Mask Register (ITMK) ............................................................................. 18.2.6 7-bit Slave Address Register (ISBA) ......................................................................................... 18.2.7 7-bit Slave Address Mask Register (ISMK) ............................................................................... 18.2.8 Data Register (IDAR) ................................................................................................................. 18.3 Explanation of I2C Interface Operation ........................................................................................... 18.4 Operation Flowchart ....................................................................................................................... 596 601 602 606 614 616 617 619 620 621 622 627 CHAPTER 19 16-BIT RELOAD TIMER............................................................................ 631 19.1 Overview of the 16-bit Reload Timer .............................................................................................. 19.2 16-bit Reload Timer Registers ........................................................................................................ 19.2.1 Control Status Register (TMCSR) ............................................................................................. 19.2.2 16-bit Timer Register (TMR) ...................................................................................................... x 632 633 634 639 19.2.3 16-bit Reload Register (TMRLR) ................................................................................................ 640 19.3 16-bit Reload Timer Operation ....................................................................................................... 641 CHAPTER 20 16-BIT FREE-RUN TIMER ........................................................................ 645 20.1 Overview of 16-bit Free-run Timer .................................................................................................. 20.2 16-bit Free-run Timer Registers ...................................................................................................... 20.2.1 Timer Data Register (TCDT) ..................................................................................................... 20.2.2 Timer Control Status Register (TCCS) ...................................................................................... 20.3 16-bit Free-run Timer Operation ..................................................................................................... 20.4 Notes on Using the 16-bit Free-run Timer ...................................................................................... 646 647 648 649 652 654 CHAPTER 21 INPUT CAPTURE...................................................................................... 655 21.1 Overview of the Input Capture ........................................................................................................ 21.2 Input Capture Registers .................................................................................................................. 21.2.1 Input Capture Register (IPCP0 to IPCP3) ................................................................................. 21.2.2 Input Capture Control Register (ICS01,ICS23) ......................................................................... 21.3 Input Capture Operation ................................................................................................................. 656 657 658 659 661 CHAPTER 22 OUTPUT COMPARE UNIT ....................................................................... 663 22.1 Overview of the Output Compare Unit ............................................................................................ 22.2 Output Compare Unit Registers ...................................................................................................... 22.2.1 Compare Register (OCCP0 to OCCP3) ..................................................................................... 22.2.2 Control Register (OCS01,OCS23) ............................................................................................. 22.3 Output Compare Unit Operation ..................................................................................................... 664 665 666 667 670 CHAPTER 23 PPG (PROGRAMMABLE PULSE GENERATOR) .................................. 675 23.1 Overview of PPG ............................................................................................................................ 23.2 PPG Registers ................................................................................................................................ 23.2.1 Control Status Registers (PCNH, PCNL) .................................................................................. 23.2.2 PPG Cycle Setting Register (PCSR) ......................................................................................... 23.2.3 PPG Duty Setting Register (PDUT) ........................................................................................... 23.2.4 PPG Timer Register (PTMR) ..................................................................................................... 23.2.5 General Control Register 10 (GCN10) ...................................................................................... 23.2.6 General Control Register 11 (GCN11) ...................................................................................... 23.2.7 General Control Register 2 (GCN20,GCN21) ........................................................................... 23.3 PPG Operation ............................................................................................................................... 23.3.1 PWM Operation ......................................................................................................................... 23.3.2 One-Shot Operation ................................................................................................................... 23.3.3 Interrupts ................................................................................................................................... 23.3.4 All "L" and All "H" PPG Outputs ................................................................................................. 23.3.5 Activation of Multiple Channels ................................................................................................. 676 679 682 686 687 688 689 692 695 696 697 699 701 702 703 CHAPTER 24 REAL TIME CLOCK ................................................................................. 705 24.1 24.2 24.3 Register Configuration of Real Time Clock ..................................................................................... 706 Block Diagram of Real Time Clock ................................................................................................. 708 Register Details of Real Time Clock ............................................................................................... 709 xi CHAPTER 25 A/D CONVERTER .................................................................................... 715 25.1 Overview of A/D Converter ............................................................................................................. 25.2 Block Diagram of A/D Converter ..................................................................................................... 25.3 Registers of A/D Converter ............................................................................................................. 25.3.1 Analog Input Enable Register (ADER) ...................................................................................... 25.3.2 A/D Control Status Register (ADCS) ......................................................................................... 25.3.3 Data Register (ADCR1, ADCR0) ............................................................................................... 25.3.4 Conversion Time Setting Register (ADCT) ................................................................................ 25.3.5 Start Channel Setting Register (ADSCH) End Channel Setting Register (ADECH) .................. 25.4 Operation of A/D Converter ............................................................................................................ 716 717 718 720 721 726 727 729 731 CHAPTER 26 SUB CLOCK CALIBRATION UNIT .......................................................... 733 26.1 Overview.......................................................................................................................................... 26.2 Clock................................................................................................................................................ 26.3 Explanation of the Registers............................................................................................................ 26.3.1 Calibration Unit Control Register (CUCR) .................................................................................. 26.3.2 32 kHz/100 kHz Timer Data Register (16-bit) (CUTD) ............................................................... 26.3.3 4MHz Timer Data Register (24bit) (CUTR) ................................................................................ 26.4 Notes on Using Sub Clock Calibration Unit .................................................................................... 734 737 738 740 742 744 745 CHAPTER 27 FLASH MEMOEY ...................................................................................... 747 27.1 Overview.......................................................................................................................................... 27.2 Access Modes ................................................................................................................................. 27.2.1 Access from the FR-CPU ........................................................................................................... 27.2.2 Flash Memory Mode .................................................................................................................. 27.3 Auto Program Algorithm ................................................................................................................. 27.3.1 Commands of Auto Program Algorithm ...................................................................................... 27.3.2 Hardware Sequence Flag ........................................................................................................... 27.3.3 Flash Control Register (FLCR) ................................................................................................... 27.3.4 Examples of Using Hardware Sequence Flag ............................................................................ 27.4 Notes on Using Flash Memory ........................................................................................................ 748 755 756 758 759 760 763 765 768 770 CHAPTER 28 FLASH SECURITY.................................................................................... 773 28.1 28.2 28.3 Overview.......................................................................................................................................... 774 Flash Security Vectors..................................................................................................................... 775 Flash Security Control Registers ..................................................................................................... 779 APPENDIX .......................................................................................................................... 785 APPENDIX A APPENDIX B APPENDIX C APPENDIX D I/O Map .............................................................................................................................. Interrupt Vector .................................................................................................................. DMA Transfer Request Source ......................................................................................... Pin State at Serial Programming Mode ............................................................................. 786 827 839 840 INDEX................................................................................................................................... 845 xii Main changes in this edition Page - Changes (For details, refer to main body.) First edition xiii xiv CHAPTER 1 OVERVIEW This chapter explains the basic information such as features, block diagram and overview of MB91461/ F467RA/F467RB. 1.1 Overview 1.2 Block Diagram 1.3 Package Dimensions 1.4 Pin Assignment Diagram 1.5 Pin Descriptions 1.6 I/O Circuit Types 1 CHAPTER 1 OVERVIEW 1.1 Overview MB91461/MB91461RA/MB91461RB are Fujitsu’s general-purpose 32-bit RISC microcontroller, which is designed for embedded control applications that require highspeed real-time processing of consumer appliances. This microcontroller uses FR60 as its CPU, compatible with other products in the FR family. MB91461/MB91461RA/MB91461RB incorporate a built-in LIN-UART and CAN controller. ■ Features ● FR60 CPU • 32-bit RISC, load/store architecture, 5-stage pipeline • Maximum operation frequency: 80 MHz (Source oscillation 20 MHz/4 MHz, multiply by 4/20 (PLL clock multiplication method)) • 16-bit fixed length instructions (basic instructions) • Instruction execution speed: One instruction per cycle • Memory-to-memory transfer instructions, bit processing instructions, barrel shift instructions, etc.: Instructions adapted for embedded applications • Function entry/exit instructions, multiple-register load/store instructions: Instructions supporting C language • Register interlock function: Easier assembler coding enabled • Built-in multiplier supported at the instruction level 1. Signed 32-bit multiplication: 5 cycles 2. Signed 16-bit multiplication: 3 cycles • Interrupt (PC/PS save): 6 cycles (16 levels) • Harvard architecture allowing program access and data access to be executed simultaneously. • Instruction compatibility with the FR family ● Built-in Peripheral Functions • Built-in ROM capacity MB91461: Instruction cache 4 Kbytes F-bus RAM (Used as both instruction and data RAM) 64 Kbytes MB91F467RA/MB91F467RB: Direct map cache (Cache for Flash) 8 Kbytes D-bus RAM (data RAM) 48 Kbytes F-bus RAM (Used as both instruction and data RAM) 16 Kbytes • General-purpose ports: up to 138 ports (MB91F467RA/MB91F467RB), 72 ports (MB91461) • DMAC (DMA Controller) Capable of simultaneous operation of up to 5 channels (one channel for external-to-external operation) Three transfer sources (external pins, internal peripheral, software) Activation sources are selectable by software. Addressing using 32-bit full addressing mode (increment, decrement, fixed) Transfer modes (demand transfer, burst transfer, step transfer, block transfer) Supporting flyby transfers (between external I/O and memories) Selectable transfer data size: 8, 16, or 32-bit Multi-byte transfer enabled (by software) 2 CHAPTER 1 OVERVIEW DMAC descriptor in I/O areas ("200H" to "240H", "1000H" to "1024H") • A/D converter (sequential comparison type) 10-bit resolution: 13 channels (MB91461) 16 channels (MB91F467RA/MB91F467RB) Conversion time: 1 µs (when peripheral macro operation clock is operated at 16.67 MHz): MB91461 3 µs (when peripheral macro operation clock is operated at 16.67 MHz): MB91F467RA, RB • External interrupt input: 16 channels Shared with the RX pins of CAN0 and CAN1 • Bit search module (for REALOS) Search function to locate the position of the first bit that changes from "1" to "0" in one word, from the MSB (high-order bit) • LIN-UART (full duplex double buffer type): 7 channels Synchronous/asynchronous clock operations selectable Sync-break detection Dedicated built-in baud-rate generator • I2C bus interface (supporting 400 kbps): 3 channels 3ch master/slave sending and receiving Arbitration and clock synchronization • CAN controller (C-CAN): 2 channels Transfer speed: up to 1 Mbps 32 send/receive message buffer (MB91461) 32 send/receive message buffer, 64 send/receive message buffer (MB91F467RA/MB91F467RB) • 16-bit PPG timer: 8 channels • 16-bit reload timer: 5 channels • 16-bit free-run timer: 4 channels (one channel each for ICU and OCU) • Input capture: 4 channels (linked to the free-run timer) • Output compare: 4 channels (linked to the free-run timer) • Watchdog timer Watchdog reset output pins available • Real time clock • Power saving modes: sleep mode, stop mode, shutdown mode ● Package: LQFP-176 (FPT-176P-M07) ● CMOS 0.18µm technology ● Power supply voltage: 3.3V/5V (Internal logic by a step-down circuit: 1.8V, partially 5.0V pressure-resistant) ● Operating temperatures: −40°C to +85°C (*) MB91F467RB is an upgraded version of MB91F467RA with improved direct map cache and fixed input threshold. Hereinafter, MB91F467RA and MB91F467RB will be collectively called MB91F467R in this manual. 3 CHAPTER 1 OVERVIEW ■ Product Lineup Table 1.1-1 shows the MB91461/F467R product lineup. Built-in peripheral functions which are not listed are common functions. Table 1.1-1 Configuration List for MB91461 and MB91F467RA/RB Item MB91461 ROM/Flash capacity ⎯ ⎯ 1088 Kbytes ⎯ Instruction cache 4 Kbytes ⎯ ⎯ ⎯ Direct Map Cache ⎯ ⎯ 8 Kbytes* ⎯ D-bus RAM capacity (for data only) ⎯ ⎯ 16 Kbytes(0wait) 32 Kbytes(1wait) ⎯ F-bus RAM capacity (for both instruction and data) 64 Kbytes ⎯ 16 Kbytes ⎯ External interrupt 16ch INT0 to INT15 16ch INT0 to INT15 DMAC 5ch ch.0 to ch.4 5ch ch.0 to ch.4 A/D Converter 13ch ch.0 to ch.12 16ch ch.0 to ch.15 LIN-UART 7ch ch.0 to ch.6 7ch ch.0 to ch.6 I2C 3ch ch.0 to ch.2 3ch ch.0 to ch.2 CAN 2ch(32msg) ch.0,ch.1 2ch (64msg +32msg) ch.0(32msg) ch.1(64msg) 16-bit Programmable Pulse Generator 8ch ch.0 to ch.7 8ch ch.0 to ch.7 16-bit Reload Timer 5ch ch.0 to ch.3,ch.7 5ch ch.0 to ch.3,ch.7 16-bit Free-run Timer 4ch ch.0 to ch.3 4ch ch.0 to ch.3 Input Capture Unit 4ch ch.0 to ch.3 4ch ch.0 to ch.3 Output Compare Unit 4ch ch.0 to ch.3 4ch ch.0 to ch.3 Real Time Clock Yes ⎯ Yes ⎯ 32 kHz Sub clock ⎯ ⎯ Selectable External bus Address 24-bit Data 16-bit ⎯ Address 24-bit Data 16-bit ⎯ Others ROM less device ⎯ Flash device ⎯ Debug Support Unit DSU4 ⎯ ⎯ ⎯ *: MB91F467RA has the limitation in use. 4 Installed channel MB91F467RA/RB Installed channel CHAPTER 1 OVERVIEW 1.2 Block Diagram Figure 1.2-1 shows the block diagram of the MB91461/F467R. ■ Block Diagram Figure 1.2-1 Block Diagram of the MB91461/F467R TRSTX BREAK ICS0 to ICS2 ICD0 to ICD3 DSU FR60 CPU Core (Debug Support) Bit Search I-Cache CAN (2ch) I-bus 32 D-bus 32 32 to 16 Bus Adapter Direct Map Cashe FLASH RAM RX0, RX1 TX0, TX1 Bus Converter SYSCLK ASX RDX WR0X WR1X Ext.bus-IF BRQ BGRNTX CS0X to CS4X A23 to A00 D31 to D16 DREQ0 DACK0X DEOP0 IOWRX IORDX DMAC (5ch) R-bus 16 Interrupt Controller MB91461 Clock Control MB91F467R External Interrupt 16ch TRG0 to TRG3 PPG0 to PPG7 PPG (8ch) TIN0 to TIN3 TOT0 to TOT3 Reload Timer (5ch) FRCK0 to FRCK3 ICU0 to ICU3 Free-run Timer (4ch) PORT interface NMIX INT0 to INT15 PORT LIN-UART(7ch) (including BRG) SIN0 to SIN6 SOT0 to SOT6 SCK0 to SCK6 I2C (3ch) SDA0 to SDA2 SCL0 to SCL2 Input Capture (4ch) RTC OCU0 to OCU3 *1: 16ch (MB91F467R) *2: AN0 to AN15 (MB91F467R) Output Compare (4ch) A/D Converter (13ch)*1 AN0 to AN12*2 ATGX 5 CHAPTER 1 OVERVIEW 1.3 Package Dimensions Figure 1.3-1 shows the package dimensions of MB91461/F467R. Figure 1.3-1 Package Dimensions of MB91461/F467R 120-pin plastic LQFP Lead pitch 0.50 mm Package width × package length 24.0 × 24.0 mm Lead shape Gullwing Sealing method Plastic mold M ounting height 1.70 mm MAX Code (Reference) P-LQFP-0176-24×24-0.50 (FPT-176P-M07) 120-pin plastic LQFP (FPT-176P-M07) Note 1) * : These dimensions do not include resin protrusion. Resin protrusion is +0.25(.010) MAX(each side). Note 2) Pins width and pins thickness include plating thickness. Note 3) Pins width do not include tie bar cutting remainder. 26.00±0.20(1.024±.008)SQ *24.00±0.10(.945±.004)SQ 0.145±0.055 (.006±.002) 132 89 133 88 0.08(.003) Details of "A" part +0.20 1.50 –0.10 +.008 (Mounting height) .059 –.004 0˚~8˚ 0.10±0.10 (.004±.004) (Stand off) INDEX 176 45 "A" LEAD No. 1 44 0.50(.020) C 0.22±0.05 (.009±.002) 0.08(.003) 0.25(.010) M 2004 FUJITSU LIMITED F176013S-c-1-1 Please confirm the latest Package dimension by following URL. http://edevice.fujitsu.com/fj/DATASHEET/ef-ovpklv.html 6 0.50±0.20 (.020±.008) 0.60±0.15 (.024±.006) Dimensions in mm (inches). Note: The values in parentheses are ref erence values. CHAPTER 1 OVERVIEW 1.4 Pin Assignment Diagram Figure 1.4-1 shows the pin assignment diagram of the MB91461/F467R. ■ Pin Assignment Diagram of the MB91461 Figure 1.4-1 shows the pin assignment diagram of the MB91461. 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 VCC5 P17_3 PPG3 P17_2/ PPG2 P17_1/ PPG1 P17_0/ PPG0 P14_3/ ICU3/TTN3/TRG3 P14_2/ ICU2/TIN2/TRG2 P14_1/ ICU1/TIN1/TRG1 P14_0/ ICU0/TIN0/TRG0 P22_3 P22_2/ INT13 P22_0/ INT12 P23_6/ INT11 P23_4/ INT10 VCC5 VSS P15_3/ OCU3/TOT3 P15_2/ OCU2/TOT2 P15_1/ OCU1/TOT1 P15_0/ OCU0/TOT0 P18_2/ SCK6 P18_1/ SOT6 P18_0/ SIN6 P19_6/ SCK5 P19_5/ SOT5 P19_4/ SIN5 P19_2/ SCK4 P19_1/ SOT4 P19_0/ SIN4 VCC5 VSS P20_6/ SCK3/FRCK3 P20_5/ SOT3 P20_4/ SIN3 P20_2/ SCK2/FRCK2 P20_1/ SOT2 P20_0/ SIN2 P21_6/ SCK1/FRCK1 P21_5/ SOT1 P21_4/ SIN1 P21_2/ SCK0/FRCK0 P21_1/ SOT0 P21_0/ SIN0 VCC5 Figure 1.4-1 Pin Assignment Diagram of the MB91461 VSS INT2 / P24_2 lNT3 / P24_3 SDA1/lNT15 / P22_6 SCL1 /P22_7 SDA2/INT4 / P24_4 SCL2/lNT5 / P24_5 DREQ0 DACK0X DEOP0 VCC3 VCC3 VSS C_1 CS4X CS3X CS2X CS1X CS0X IORDX IOWRX RDY BRQ BGRNTX RDX WR0X WR1X SYSCLK ASX VCC3 C_2 VSS X0 X1 VSS D16 D17 D18 D19 D20 D21 D22 D23 VCC3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 1 2 3 TOP View MB91461 Pin Assignment (LQFP-176) 2 power supply products 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 VSS INITX TRSTX MD0 MD1 MD2 MD3 P23_3 / TX1 P23_2 / RX1/INT9 P23_1 / TX0 P23_0 / RX0/lNT8 P24_7 / INT7 P24_6 / INT6 p22_5 / SCL0 P22_4 / SDA0/INT14 P24_1 / lNT1 P24_0 / INT0 AVRH AVCC3 AVSS/AVRL P28_4 / AN12 P28_3 / AN11 P28_2 / AN10 P28_1 / AN9 P28_0 / AN8 P29_7 / AN7 P29_6 / AN6 P29_5 / AN5 P29_4 / AN4 P29_3 / AN3 P29_2 / AN2 P29_1 / AN1 P29_0 / AN0 WDRESETX BREAK ICLK ICS2 ICS1 lCS0 ICD3 lCD2 lCD1 lCD0 VCC3 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 VSS P17_7 / PPG7 P17_6 / PPG6 P17_5 / PPG5 P17_4 / PPG4 P16_7 / ATGX NMIX A23 A22 A21 A20 A19 A18 A17 VSS VCC3 A16 A15 A14 A13 A12 A11 A10 A09 A08 A07 A06 A05 A04 A03 VSS VCC3 A02 A01 A00 D31 D30 D29 D28 D27 D26 D25 D24 VSS 7 CHAPTER 1 OVERVIEW Note: Three I/O blocks (Blocks 1, 2 & 3) are each 176 pins, 162 pins, 133 pins (147 pins), and power supply level (3.3V/5V) to each pin can be set. However, please supply 5V power supply when there is a pin that operates as much as one each block by 5V. Only when the pin for I2C of Block 1 supplies 5V to the power supply, the input of 5V amplitude becomes possible. Moreover, the input threshold of I2C reaches the value based on 3.3V regardless of the power-supply voltage. When I/O Block 1 or 3 is used with 5V pins, the INITX pin requires 5V input. Consequently, I/O Block 3 also requires 5V to be supplied. 8 CHAPTER 1 OVERVIEW ■ Pin Assignment Diagram of the MB91F467R Figure 1.4-2 shows the pin assignment diagram of the MB91F467R. 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 VCC5 P17_3/PPG3 P17_2/ PPG2 P17_1/ PPG1 P17_0/ PPG0 P14_3/ ICU3/TIN3/TRG3 P14_2/ ICU2/TIN2/TRG2 P14_1/ ICU1/TIN1/TRG1 P14_0/ ICU0/TIN0/TRG0 P22_3 P22_2/ INT13 P22_0/ INT12 P23_6/ INT11 P23_4/ INT10 VCC5 VSS P15_3 / OCU3/TOT3 P15_2 / OCU2/TOT2 P15_1 / OCU1/TOT1 P15_0 / OCU0/TOT0 P18_2 / SCK6 P18_1 / SOT6 P18_0 / SIN6 P19_6 / SCK5 P19_5 / SOT5 P19_4 / SIN5 P19_2 / SCK4 P19_1 / SOT4 P19_0 / SIN4 VCC5 VSS P20_6/SCK3/FRCK3 P20_5/SOT3 P20_4/SIN3 P20_2/SCK2/FRCK2 P20_1/SOT2 P20_0/SIN2 P21_6/SCK1/FRCK1 P21_5/SOT1 P21_4/SIN1 P21_2/SCK0/FRCK0 P21_1/SOT0 P21_0/SIN0 VCC5 Figure 1.4-2 Pin Assignment Diagram of the MB91F467R VSS P24_2 P24_3 P22_6 P22_7 P24_4 P24_5 P13_0 P13_1 P13_2 VCC3 VCC3 VSS C_1 CS4X/ P09_4 CS3X/ P09_3 CS2X/ P09_2 CS1X/ P09_1 CS0X/ P09_0 IORDX/ P11_0 IOWRX/ P11_1 RDY/ P08_7 BRQ / P08_6 BGRNTX/ P08_5 RDX / P08_4 WR1X/ P08_1 WR0X/ P08_0 NMIX MCLKE/ P10_6 MCLKI/ P10_5 MCLKO/ P10_4 WEX/ P10_3 BAAX / P10_2 ASX / P10_1 SYSCLK/ P10_0 VCC3 C_2 VSS X0 X1 VSS X0A X1A VCC3 INT2 / INT3 / SDA1/INT15/ SCL1 / SDA2/INT4 / SCL2/INT5 / DREQ0/ DACK0X/ DEOP0/ 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 (5) (1) (2) (3) TOP View MB91F467R Pin Assignment (LQFP-176) 2 power supply products (4) (4) : The I/O voltage level is 3.3V. (5) : The I/O voltage level depends on the voltage for the corresponding VCC5. (4) (4) 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 VSS INITX MD0 MD1 MD2 MD3 P23_3 / TX1 P23_2 / RX1/INT9 P23_1 / TX0 P23_0 / RX0/INT8 P24_7 / INT7 P24_6 / INT6 P24_1 / INT1 P24_0 / INT0 P22_5 / SCL0 P22_4 / SDA0/INT14 AVRH AVCC3 AVSS/AVRL P28_7 / AN15 P28_6 / AN14 P28_5 / AN13 P28_4 / AN12 P28_3 / AN11 P28_2 / AN10 P28_1 / AN9 P28_0 / AN8 P29_7 / AN7 P29_6 / AN6 P29_5 / AN5 P29_4 / AN4 P29_3 / AN3 P29_2 / AN2 P29_1 AN1 P29_0 / AN0 WDRESETX P17_7 / PPG7 P17_6 / PPG6 P17_5 / PPG5 P17_4 / PPG4 P16_7 / ATGX P05_7 / A23 P05_6 / A22 VCC3 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 VSS P05_5 /A21 P05_4 /A20 P05_3 /A19 P05_2 /A18 P05_1 /A17 P05_0 /A16 P06_7 /A15 P06_6 /A14 P06_5 /A13 P06_4 /A12 P06_3 /A11 P06_2 /A10 P06_1 /A09 VSS VCC3 P06_0 / A08 P07_7 / A07 P07_6 / A06 P07_5 / A05 P07_4 / A04 P07_3 / A03 P07_2 / A02 P07_1 / A01 P07_0 / A00 P00_7 / D31 P00_6 / D30 P00_5 / D29 P00_4 / D28 P00_3 / D27 VSS VCC3 P00_2 / D26 P00_1 / D25 P00_0 / D24 P01_7 / D23 P01_6 / D22 P01_5 / D21 P01_4 / D20 P01_3 / D19 P01_2 / D18 P01_1 / D17 P01_0 / D16 VSS Note: Three I/O blocks (Blocks 1, 2 & 3) are each 176 pins, 162 pins, 133 pins (147 pins), and power supply level (3.3V/5V) to each pin can be set. However, please supply 5V power supply when there is a pin that operates as much as one each block by 5V. Only when the pin for I2C of Block 1 supplies 5V to the power supply, the input of 5V amplitude becomes possible. Moreover, the input threshold of I2C reaches the value based on 3.3V regardless of the power-supply voltage. When I/O Block 1 or 3 is used with 5V pins, the INITX pin requires 5V input. Consequently, I/O Block 3 also requires 5V to be supplied. 9 CHAPTER 1 OVERVIEW 1.5 Pin Descriptions Table 1.5-1 shows the pin descriptions of the MB91461/F467R. ■ Pin Descriptions Table 1.5-1 MB91461/F467R Pin Descriptions (1 / 5) Pin no. 2 3 Pin name P24_2 INT2 P24_3 INT3 I/O I/O circuit type I/O D I/O D P22_6 4 SDA1 P22_7 SCL1 C SDA2 I/O Open Drain C C External interrupt input pin I2C bus DATA I/O pin General purpose I/O port I2C bus Clock I/O pin I2C bus DATA I/O pin External interrupt input pin P24_5 SCL2 General purpose I/O port General purpose I/O port I/O Open Drain INT4 7 External interrupt input pin External interrupt input pin P24_4 6 General purpose I/O port General purpose I/O port I/O Open Drain INT15 5 Function General purpose I/O port I/O Open Drain C INT5 I2C bus Clock I/O pin External interrupt input pin 8 DREQ0 I H DMA external transfer request input 9 DACK0X O H DMA external transfer acknowledge output 10 DEOP0 O H DMA external transfer EOP (End of Process) output 15 to 19 CS4X to CS0X O H Chip select outputs 20 IORDX O H Read strobe output for DMA flyby transfer 21 IOWRX O H Write strobe output for DMA flyby transfer 22 RDY I H External ready input 23 BRQ I H External bus release request input 24 BGRNTX O H External bus release acceptance output 25 RDX O H External read strobe output 26 WR0X O H External write strobe output 27 WR1X O H External write strobe output 10 CHAPTER 1 OVERVIEW Table 1.5-1 MB91461/F467R Pin Descriptions (2 / 5) Pin no. Pin name I/O I/O circuit type 28 SYSCLK O H System clock output 29 ASX O H Address strobe output 33 X0 − H Clock (oscillation) input 34 X1 − H Clock (oscillation) output 36 to 43 46 to 53 D16 to D31 I/O H External data bus signals 54 to 56 59 to 72 75 to 81 A00 to A23 O H External address bus signals 82 NMIX I H NMI (Non Maskable Interrupt) input H General purpose I/O port H A/D converter external trigger input H General purpose I/O port H PPG timer output pins 83 84 to 87 P16_7 ATGX P17_4 to P17_7 PPG4 to PPG7 I/O I/O Function 90 to 93 ICD0 to ICD3 I/O H Data I/O pins for a development tool 94 to 96 ICS0 to ICS2 O H Status output pins for a development tool 97 ICLK O I Clock output pin for a development tool 98 BREAK I H Break input pin for a development tool 99 WDRESETX O J Watchdog reset output pin I/O F I/O F 100 to 107 108 to 112 P29_0 to P29_7 AN0 to AN7 P28_0 to P28_4 AN8 to AN12 P24_0, P24_1 116, 117 INT0, INT1 SDA0 I/O D P22_5 SCL0 C INT6 Analog input pins for the A/D converter External interrupt input pin Can be used as a shutdown recovery source I2C bus DATA I/O pin External interrupt input pin I/O Open Drain C P24_6 120 General purpose I/O port General purpose I/O port I/O Open Drain INT14 119 Analog input pins for the A/D converter General purpose I/O port P22_4 118 General purpose I/O port General purpose I/O port I2C bus clock I/O pin General purpose I/O port I/O D External interrupt input pin Can be used as a shutdown recovery source 11 CHAPTER 1 OVERVIEW Table 1.5-1 MB91461/F467R Pin Descriptions (3 / 5) Pin no. Pin name I/O I/O circuit type P24_7 121 INT7 General purpose I/O port I/O D P23_0 122 RX0 P23_1 TX0 I/O D RX1 I/O D P23_3 TX1 TX output pin for CAN0 I/O D RX input pin for CAN1 External interrupt input pin Can be used as a shutdown recovery source I/O D General purpose I/O port TX output pin for CAN0 126 MD3 I A 127 MD2 I A 128 MD1 I A 129 MD0 I B 130 TRSTX I E Reset input pin for a development tool 131 INITX I B External reset input I/O D I/O D 134 135 P21_0 SIN0 P21_1 SOT0 P21_2 136 SCK0 137 138 P21_4 SIN1 P21_5 SOT1 Mode setup pin MD3 is fixed to "0" General purpose I/O port Data input pin for UART0 General purpose I/O port Data output pin for UART0 General purpose I/O port I/O D FRCK0 12 General purpose I/O port General purpose I/O port INT9 125 RX input pin for CAN0 External interrupt input pin Can be used as a shutdown recovery source P23_2 124 External interrupt input pin Can be used as a shutdown recovery source General purpose I/O port INT8 123 Function Clock I/O pin for UART0 External clock input pin for the free-run timer 0 I/O D I/O D General purpose I/O port Data input pin for UART1 General purpose I/O port Data output pin for UART1 CHAPTER 1 OVERVIEW Table 1.5-1 MB91461/F467R Pin Descriptions (4 / 5) Pin no. Pin name I/O I/O circuit type P21_6 139 SCK1 General purpose I/O port I/O D FRCK1 140 141 P20_0 SIN2 P20_1 SOT2 SCK2 I/O D I/O D 144 P20_4 SIN3 P20_5 SOT3 I/O D SCK3 I/O D I/O D 149 150 151 152 153 154 155 P19_0 SIN4 P19_1 SOT4 P19_2 SCK4 P19_4 SIN5 P19_5 SOT5 P19_6 SCK5 P18_0 SIN6 P18_1 SOT6 General purpose I/O port Data output pin for UART2 Clock I/O pin for UART2 General purpose I/O port Data input pin for UART3 General purpose I/O port Data output pin for UART3 General purpose I/O port I/O D FRCK3 148 Data input pin for UART2 External clock input pin for the free-run timer 2 P20_6 145 General purpose I/O port General purpose I/O port FRCK2 143 Clock I/O pin for UART1 External clock input pin for the free-run timer 1 P20_2 142 Function Clock I/O pin for UART3 External clock input pin for the free-run timer 3 I/O D I/O D I/O D I/O D I/O D I/O D I/O D I/O D General purpose I/O port Data input pin for UART4 General purpose I/O port Data output pin for UART4 General purpose I/O port Clock I/O pin for UART4 General purpose I/O port Data input pin for UART5 General purpose I/O port Data output pin for UART5 General purpose I/O port Clock I/O pin for UART5 General purpose I/O port Data input pin for UART6 General purpose I/O port Data output pin for UART6 13 CHAPTER 1 OVERVIEW Table 1.5-1 MB91461/F467R Pin Descriptions (5 / 5) Pin no. 156 Pin name P18_2 SCK6 I/O I/O circuit type I/O D P15_0 to P15_3 157 to 160 OCU0 to OCU3 164 165 166 167 P23_4 INT10 P23_6 INT11 P22_0 INT12 P22_2 INT13 P22_3 I/O D ICU0 to ICU3 TIN0 to TIN3 I/O D I/O D I/O D I/O D I/O D 14 P17_0 to P17_3 PPG0 to PPG3 Output compare output pins General purpose I/O port External interrupt input pin General purpose I/O port External interrupt input pin General purpose I/O port External interrupt input pin General purpose I/O port External interrupt input pin General purpose I/O port General purpose I/O port I/O D TRG0 to TRG3 172 to 175 Clock I/O pin for UART6 Reload timer output pins P14_0 to P14_3 168 to 171 General purpose I/O port General purpose I/O port TOT0 to TOT3 163 Function Input capture input pins External trigger input pin for the reload timers External trigger input pins for PPG I/O D General purpose I/O port PPG timer output pins CHAPTER 1 OVERVIEW Table 1.5-2 MB91461 Pin Descriptions [Power Supply and GND Pins] Pin no. Pin name I/O circuit type Function 1, 13, 32, 35 45, 58, 74, 88 132, 146, 161 VSS (VSS) 11, 12, 30, 44 57, 73, 89 VCC3 (VCC3) 3.3V power supply pins GND pins 133 147 VCC5 (VCC5) 5V power supply pins, used as I/O power supply pins supporting pins 116 to 145. When 3.3V is supplied, I/O performs 3.3V operations. When 5V is used in another I/O power supply block, the I/O block which this pin belongs to must also be set to 5V. 162 VCC5 (VCC5) 5V power supply pins, used as I/O power supply pins supporting pins 148 to 160. When 3.3V is supplied, I/O performs 3.3V operations. 176 VCC5 (VCC5) 5V power supply pins, used as I/O power supply pins supporting pins 2 to 7 and 163 to 175. If there is at least one 5V pin, 5V must be supplied. 113 AVSS/AVRL (AVSS) Analog GND pin for the A/D converter 114 AVCC3 (AVCC3) 3.3V power supply pin for the A/D converter 115 AVRH (AVRH) Reference power supply pin for the A/D converter 14 C_1 − Capacitor connection pin for the internal regulator. 4.7 µF must be connected. 31 C_2 − Capacitor connection pin for the internal regulator. 4.7 µF must be connected. 15 CHAPTER 1 OVERVIEW ■ MB91F467R Pin Descriptions Table 1.5-3 shows the pin descriptions of the MB91F467R. Table 1.5-3 MB91467R Pin Descriptions (1 / 6) Pin no. 2 3 Pin name P24_2 INT2 P24_3 INT3 I/O I/O circuit type I/O D I/O D P22_6 4 SDA1 P22_7 SCL1 C SDA2 I/O Open Drain C C 9 10 15 to 19 20 21 22 23 16 P13_0 DREQ0 P13_1 DACK0 P13_2 DEOP0 P09_4 to P09_0 CS4X to CS0X P11_0 IORDX P11_1 IOWRX P08_7 RDY P08_6 BRQ I2C bus DATA I/O pin General purpose I/O port I2C bus Clock I/O pin I2C bus DATA I/O pin General purpose I/O port I/O Open Drain C INT5 8 External interrupt input pin External interrupt input pin P24_5 SCL2 General purpose I/O port General purpose I/O port I/O Open Drain INT4 7 External interrupt input pin External interrupt input pin P24_4 6 General purpose I/O port General purpose I/O port I/O Open Drain INT15 5 Function I2C bus Clock I/O pin External interrupt input pin I/O H I/O H I/O H I/O H I/O H I/O H I/O H I/O H General purpose I/O port DMA external transfer request input General purpose I/O port DMA external transfer acknowledge output General purpose I/O port DMA external transfer EOP (End of Process) output General purpose I/O port Chip select outputs General purpose I/O port Read strobe output for DMA flyby transfer General purpose I/O port Write strobe output for DMA flyby transfer General purpose I/O port External ready input General purpose I/O port External bus release request input CHAPTER 1 OVERVIEW Table 1.5-3 MB91467R Pin Descriptions (2 / 6) Pin no. 24 25 Pin name P08_5 BGRNTX P08_4 RDX I/O I/O circuit type I/O H I/O H I/O H I/O H External write strobe output (DQMU signal when using SDRAM) I H NMI (Non Maskable Interrupt) input I/O H I/O H I/O H I/O H P08_1 26 WR1X 28 29 30 31 32 WR0X NMIX P10_6 MCLKE P10_5 MCLKI P10_4 MCLKO P10_3 WEX 34 35 BAAX P10_1 ASX P10_0 SYSCLK External bus release acceptance output General purpose I/O port External read strobe output External write strobe output (DQML signal when using SDRAM) General purpose I/O port P10_2 33 General purpose I/O port General purpose I/O port P08_0 27 Function General purpose I/O port Clock enable output signal for SDRAM General purpose I/O port Clock input for SDRAM General purpose I/O port Clock output for SDRAM General purpose I/O port External write enable signal General purpose I/O port I/O H I/O H I/O H Address advance output for burst mode FLASH memory General purpose I/O port Address strobe output General purpose I/O port System clock output 39 X0 -- G Clock (oscillation) input 40 X1 -- G Clock (oscillation) output 42 X0A -- G Sub clock (oscillation) input 43 X1A -- G Sub clock (oscillation) output I/O H I/O H 46 to 53 54 to 56 59 to 63 P01_0 to P01_7 D16 to D23 P00_0 to P00_7 D24 to D31 General purpose I/O port External data bus signals General purpose I/O port External data bus signals 17 CHAPTER 1 OVERVIEW Table 1.5-3 MB91467R Pin Descriptions (3 / 6) Pin no. 64 to 71 Pin name P07_0 to P07_7 A00 to A07 72 75 to 81 P06_0 to P06_7 82 to 87 90, 91 P05_0 to P05_7 92 93 to 96 97 98 to 105 106 to 113 A08 to A15 A16 to A23 P16_7 ATGX P17_4 to P17_7 PPG4 to PPG7 WDRESETX P29_0 to P29_7 AN0 to AN7 P28_0 to P28_7 AN8 to AN15 I/O I/O circuit type I/O H I/O H I/O H I/O H I/O H O J I/O F I/O F P22_4 117 SDA0 P22_5 SCL0 C INT0 to INT1 I/O Open Drain C I/O D INT6 I/O D INT7 I/O D RX0 18 P23_1 TX0 External address bus signals General purpose I/O port A/D converter external trigger input General purpose I/O port PPG timer output pins Watchdog reset output pin General purpose I/O port Analog input pins for the A/D converter General purpose I/O port Analog input pins for the A/D converter I2C bus DATA I/O pin General purpose I/O port I2C bus clock I/O pin External interrupt input pin Can be used as a shutdown recovery source External interrupt input pin Can be used as a shutdown recovery source External interrupt input pin Can be used as a shutdown recovery source General purpose I/O port I/O D RX input pin for CAN0 External interrupt input pin Can be used as a shutdown recovery source INT8 124 General purpose I/O port General purpose I/O port P23_0 123 External address bus signals General purpose I/O port P24_7 122 General purpose I/O port General purpose I/O port P24_6 121 External address bus signals External interrupt input pin P24_0 to P24_1 119 to 120 General purpose I/O port General purpose I/O port I/O Open Drain INT14 118 Function I/O D General purpose I/O port TX output pin for CAN0 CHAPTER 1 OVERVIEW Table 1.5-3 MB91467R Pin Descriptions (4 / 6) Pin no. Pin name I/O I/O circuit type P23_2 125 RX1 General purpose I/O port I/O D P23_3 TX1 I/O D 127 MD3 I A 128 MD2 I K 129 MD1 I K 130 MD0 I K 131 INITX I B I/O D I/O D 134 135 P21_0 SIN0 P21_1 SOT0 P21_2 136 SCK0 138 P21_4 SIN1 P21_5 SOT1 I/O D SCK1 I/O D I/O D 141 P20_0 SIN2 P20_1 SOT2 I/O D SCK2 I/O D I/O D P20_4 SIN3 General purpose I/O port Data input pin for UART0 General purpose I/O port Data output pin for UART0 Clock I/O pin for UART0 General purpose I/O port Data input pin for UART1 General purpose I/O port Data output pin for UART1 Clock I/O pin for UART1 General purpose I/O port Data input pin for UART2 General purpose I/O port Data output pin for UART2 General purpose I/O port I/O D FRCK2 143 External reset input External clock input pin for the free-run timer 1 P20_2 142 Mode setup pin MD3 is fixed to "0" General purpose I/O port FRCK1 140 TX output pin for CAN0 External clock input pin for the free-run timer 0 P21_6 139 General purpose I/O port General purpose I/O port FRCK0 137 RX input pin for CAN1 External interrupt input pin Can be used as a shutdown recovery source INT9 126 Function Clock I/O pin for UART2 External clock input pin for the free-run timer 2 I/O D General purpose I/O port Data input pin for UART3 19 CHAPTER 1 OVERVIEW Table 1.5-3 MB91467R Pin Descriptions (5 / 6) Pin no. 144 Pin name P20_5 SOT3 I/O I/O circuit type I/O D P20_6 145 SCK3 149 150 151 152 153 154 155 156 P19_0 SIN4 P19_1 SOT4 P19_2 SCK4 P19_4 SIN5 P19_5 SOT5 P19_6 SCK5 P18_0 SIN6 P18_1 SOT6 P18_2 SCK6 I/O D OCU0 to OCU3 I/O D I/O D I/O D I/O D I/O D I/O D I/O D I/O D I/O D 164 165 166 20 P23_4 INT10 P23_6 INT11 P22_0 INT12 P22_2 INT13 Clock I/O pin for UART3 General purpose I/O port Data input pin for UART4 General purpose I/O port Data output pin for UART4 General purpose I/O port Clock I/O pin for UART4 General purpose I/O port Data input pin for UART5 General purpose I/O port Data output pin for UART5 General purpose I/O port Clock I/O pin for UART5 General purpose I/O port Data input pin for UART6 General purpose I/O port Data output pin for UART6 General purpose I/O port Clock I/O pin for UART6 General purpose I/O port I/O D TOT0 to TOT3 163 Data output pin for UART3 External clock input pin for the free-run timer 3 P15_0 to P15_3 157 to 160 General purpose I/O port General purpose I/O port FRCK3 148 Function Output compare output pins Reload timer output pins I/O D I/O D I/O D I/O D General purpose I/O port External interrupt input pin General purpose I/O port External interrupt input pin General purpose I/O port External interrupt input pin General purpose I/O port External interrupt input pin CHAPTER 1 OVERVIEW Table 1.5-3 MB91467R Pin Descriptions (6 / 6) Pin no. Pin name I/O I/O circuit type 167 P22_3 I/O D P14_0 to P14_3 168 to 171 ICU0 to ICU3 TIN0 to TIN3 P17_0 to P17_3 PPG0 to PPG3 General purpose I/O port General purpose I/O port I/O D TRG0 to TRG3 172 to 175 Function Input capture input pins External trigger input pin for the reload timers External trigger input pins for PPG I/O D General purpose I/O port PPG timer output pins 21 CHAPTER 1 OVERVIEW Table 1.5-4 MB91F46R Pin Descriptions [Power Supply and GND Pins] Pin no. Pin name I/O circuit type 1,13,38,41 45,58,74,88 132,146,161 VSS (VSS) 11,12,36,44 57,73,89 VCC3 (VCC3) 3.3V power supply pins 22 Function GND pins 133 147 VCC5 (VCC5) 5V power supply pins. These pins are I/O power supplies for pin 117 to pin 145 and the I/O becomes 3.3V operation by supplying 3.3V. If other I/O power supply blocks use 5V, the I/O belonging to this pin must also be set to 5V. 162 VCC5 (VCC5) 5V power supply pin. This pin is I/O power supply for pin 148 to pin 160 and the I/O becomes 3.3V operation by supplying 3.3V. 176 VCC5 (VCC5) 5V power supply pin. This pin is I/O power supply for pin 2 to pin 7 and pin 163 to pin 175. Supply 5V to this pin if one or more 5V operation pins exist. 114 AVSS/AVRL (AVSS) Analog GND pin for the A/D converter 115 AVCC3 (AVCC3) 3.3V power supply pin for the A/D converter 116 AVRH (AVRH) Reference power supply pin for the A/D converter 14 C_1 -- Capacitor connection pin for the internal regulator. 4.7µF must be connected. 37 C_2 -- Capacitor connection pin for the internal regulator. 4.7µF must be connected. CHAPTER 1 OVERVIEW 1.6 I/O Circuit Types This section describes the I/O circuit types. ■ I/O Circuit Types Table 1.6-1 I/O Circuit Types (1 / 4) Type Circuit Remarks 5V CMOS level hysteresis input with pull-down 5V level Input A Pull-down N-ch 5V CMOS level hysteresis input with pull-up Pull-up P-ch B Input 5V level I/O pin for I2C IOL= 3mA N-ch Output drive N-ch 5V resisting pressure (With standby control) C Input Standby control 23 CHAPTER 1 OVERVIEW Table 1.6-1 I/O Circuit Types (2 / 4) Type Circuit Remarks 5V CMOS level output IOL= 4mA Pull-up control 5V CMOS level input P-ch Output drive P-ch 5V CMOS hysteresis level input with pull-up/pulldown control (With standby control) N-ch Output drive N-ch P-ch 5V level D Pull-down control N-ch Input Standby control Input Standby control 3.3V CMOS level hysteresis input 3.3V level E 5V resisting pressure (With standby control) Input 3.3V CMOS level output IOL= 4mA 3.3V level P-ch N-ch Output drive P-ch Output drive N-ch F Input Standby control Input Standby control Analog input 24 3.3V CMOS level input 3.3V CMOS hysteresis level input Analog input (With standby control) CHAPTER 1 OVERVIEW Table 1.6-1 I/O Circuit Types (3 / 4) Type Circuit Remarks 3.3V oscillation cell 3.3V level Input (feedback resistor 1 MΩ) G Standby control 3.3V CMOS level output IOL= 4mA Pull-up control 3.3V CMOS level input P-ch Output drive P-ch 3.3V CMOS hysteresis level input with pull-up/ pull-down control (With standby control) N-ch Output drive N-ch P-ch 3.3V level H N-ch Pull-down control Input Standby control Input Standby control 3.3V CMOS level output I: IOL= 8mA 3.3V level P-ch Output drive P-ch N-ch Output drive N-ch J: IOL= 4mA I, J 25 CHAPTER 1 OVERVIEW Table 1.6-1 I/O Circuit Types (4 / 4) Type Circuit Remarks 5V CMOS level input 5V level K 26 Input CHAPTER 2 HANDLING DEVICES This chapter describes precautions on handling FR family devices. 2.1 Precautions on Handling Devices 2.2 Precautions for Use 27 CHAPTER 2 HANDLING DEVICES 2.1 Precautions on Handling Devices This section explains how to prevent latch-up, perform pin processing, handle circuits and input at power-up. ■ Preventing Latch-up Latch-up may occur in a CMOS IC, if a voltage greater than VCC or less than VSS is applied to an input or output pin, or if an above-rating voltage is applied between VCC and VSS. When latch-up occurs, it may significantly increase the power supply current, resulting in thermal destruction of an element. Therefore, utmost care should be taken that the maximum rating is not exceeded in use. ■ Treatment of Unused Pins Do not leave an unused input pin open, since it may cause a malfunction. Handle by using a pull-up or pulldown resistor. ■ Power Supply Pins In products with multiple VCC and VSS pins, the pins of the same potential are internally connected in the device to avoid abnormal operations including latch-up. However, you must connect all the pins to external power supply and a ground line to lower the electro-magnetic emission level, to prevent abnormal operation of strobe signals caused by the rise in the ground level, and to conform to the total output current rating. Moreover, connect the current supply source with the VCC and VSS pins of this device at the low impedance. It is also advisable to connect a ceramic bypass capacitor of approximately 0.1 µF between VCC and VSS near this device. MB91461/F467R incorporates a built-in step-down regulator. Connect a 4.7 µF bypass capacitor to C_1 and C_2 pins for the regulator. ■ Crystal Oscillator Circuit Noise near the X0 and X1 (X0A, X1A) pins may cause the device to malfunction. Design the printed circuit board so that X0 (X0A) and X1 (X1A), the crystal oscillator, and the bypass capacitor to ground are located as close to the device as possible. It is strongly recommended to design the PC board artwork with the X0 and X1 pins surrounded by ground plane because stable operation can be expected with such a layout. Please ask the crystal maker to evaluate the oscillational characteristics of the crystal and this device. 28 CHAPTER 2 HANDLING DEVICES ■ Notes on Using External Clock When an external clock is used, supply it to X0 (X0A) pin generally, and simultaneously the opposite phase clock to X0 (X0A) must be supplied to X1 (X1A) pin. However, in this case the stop mode (oscillator stop mode) must not be used (This is because the X1 (X1A) pin stops at "H" output in the STOP mode). Figure 2.1-1 Example Application of External Clock (Normal) X0 (X0A) X1 (X1A) Note: STOP mode (oscillation stop mode) cannot be used. ■ Mode Pins (MD0 to MD3) These pins should be connected directly to VCC or VSS. To prevent the device erroneously switching to test mode due to noise, design the printed circuit board such that the distance between the mode pins and VCC or VSS is as short as possible and the connection impedance is low. ■ Power-up Sequence for 3.3V and 5V Power Supplies • Immediately after the power supply is turned on, hold the Low level input to the INITX pin for the settling time required for the oscillator circuit to take the oscillation stabilization wait time (8ms) for the oscillator circuit. • There is no particular start-up sequence for power supply • When canceling a reset (by changing the INITX pin from the Low level to the High level), ensure that 3.3V and 5V power supplies are stable. 29 CHAPTER 2 HANDLING DEVICES ■ Caution on Operations during PLL Clock Mode On this microcontroller, if in case the crystal oscillator breaks off or an external reference clock input stops while the PLL clock mode is selected, a self-oscillator circuit contained in the PLL may continue its operation at its self-running frequency. However, Fujitsu will not guarantee results of operations if such failure occurs. ■ External Bus Setting MB91461/F467R guarantee an external bus clock (SYSCLK) frequency of 400 MHz. Setting the base clock frequency to 40 MHz with DIVR1 (external bus base clock division setting register) initialized sets the external bus frequency also to 80 MHz. Before changing the base clock frequency, set SYSCLK not exceeding 80 MHz. ■ Pull-up Control Connecting a pull-up resistor to the pin serving as an external bus pin cannot guarantee the AC specifications. ■ Notes on the PS Register As the PS register is processed by some instructions in advance, exception handling below may cause the interrupt handling routine to break when the debugger is used or the display contents of flags in the PS register to be updated. As the microcontroller is designed to carry out reprocessing correctly upon returning from such an EIT event, it performs operations before and after the EIT as specified in either case. (1) The following operations are performed when the instruction followed by a DIV0U/DIV0S instruction results in acceptance of a user interrupt or NMI, single-stepping, or a break at a data event or emulator menu. - The D0 and D1 flags are updated in advance. - An EIT handling routine (user interrupt, NMI, or emulator) is executed. - Upon returning from the EIT, the DIV0U/DIV0S instruction is executed and the D0 and D1 flags are updated to the same values as in (1). (2) The following operations are performed when the OR CCR/ST ILM/MOV Ri and PS instructions are executed during a user interrupt or NMI. - The PS register is updated in advance. - An EIT handling routine (user interrupt, NMI, or emulator) is executed. - Upon returning from the EIT, the above instructions are executed and the PS register is updated to the same value as in (1). ■ Software Reset on the Synchronous Mode Be sure to meet the following two conditions before setting "0" to the SRST bit of STCR (standby control register) when the software reset is used on the synchronous mode. • Set the interrupt enable flag (I-Flag) to interrupt disabled (I-Flag = 0). • Not used NMI. 30 CHAPTER 2 HANDLING DEVICES ■ Note on Debugger ● Step execution of RETI command If an interrupt occurs frequently during stepping, only the corresponding interrupt handling routine is executed repeatedly. This will prevent the main routine and low-interrupt-level programs from being executed (For example, whenever RETI is stepped with interrupts by the time-base timer enabled, the timebase timer routine causes a break at the beginning). Disable the corresponding interrupt when the corresponding interrupt handling routine no longer needs debugging. ● Break function If the address at which to cause a hardware break (including an event break) is set to the address currently contained in the system stack pointer or in the area containing the stack pointer, the user program causes a break after the execution of one instruction, despite no actual data access command in the program. To prevent a break, do not set (word) access to the area containing the address in the system stack pointer as the target of a hardware break (including an event break). ● Built-in ROM (FLASH MEMORY, MASKROM) Caution on Operations When Evaluation Chips Are in Use Do not set an built-in ROM area as a DMAC transfer destination. When an built-in ROM area is set as a DMAC transfer destination, this area may be rewritten if a break occurs during a DMAC transfer. However, it is technically possible to set an built-in ROM area as a DMAC transfer destination. ● Operand breaks A stack pointer placed in an area set for a DSU operand break can cause a malfunction. Do not apply a data event break to access to the area containing the address of a system stack pointer. 31 CHAPTER 2 HANDLING DEVICES 2.2 Precautions for Use This section shows the precautions when using dedicated DSU4 (ICE) connection pin. ■ Dedicated DSU4 (ICE) Connection Pin The DSU4 (ICE) connection pin for MB91461 is shown below. Table 2.2-1 DSU4 (ICE) Connection Pin for MB91461 Pin no. Pin name Function 93 to 90 ICD3 to ICD0 Data I/O pins for a development tool 96 to 94 ICS2 to ICS0 Status output pins for a development tool 97 ICLK Clock pin for a development tool 98 BREAK Break pin for a development tool 130 TRSTX Reset pin for a development tool (3.3V/5V input pin) ● Connector for the user target board and MB91461 connection A recommended connector for the user target board is shown below. Manufacturer: Yamaichi Electronics Co., Ltd. Part number: FAP-20-08#* Note: The symbol "*" shown in the part number is a single-digit number that indicates a pin shape. • 1: Right-angled/wrapping • 2: Right-angled/solder dip • 4: Straight/solder dip Figure 2.2-1 Connector for the User Target Board and MB91461 Connection 32 19pin 1pin 20pin 2pin CHAPTER 2 HANDLING DEVICES Table 2.2-2 Pin Function List of Target Side Connector Pin no. Signal line name Input/ output 1 EVCC2 Input OPEN 2 EVCC3 Input OPEN 3 DSUIO I/O OPEN 4 UVCC Output User Vcc output 6 XRSTIN Output Connected to the INITX signal in the user circuit 8 PLVL Input 5 XTRST Input Connected to TRSTX (Pin no. 130) 7 XINIT Input Connected to INITX (Pin no. 131) 9 GND − 10 BREAK Input 11 ICD[3] 12 ICD[2] 13 ICD[1] 14 ICD[0] 15 GND 16 ICS[2] 17 ICS[1] 18 ICS[0] 19 GND − 20 ICLK Output Pin handling OPEN Connected to VSS Connected to BREAK (Pin no. 98) Connected to ICD3 (Pin no. 93) Connected to ICD2 (Pin no. 92) I/O MB91461 − Connected to ICD1 (Pin no. 91) Connected to ICD0 (Pin no. 90) Connected to VSS Connected to ICS2 (Pin no. 96) Output Connected to ICS1 (Pin no. 95) Connected to ICS0 (Pin no. 94) Connected to VSS Connected to ICLK (Pin no. 97) 33 CHAPTER 2 HANDLING DEVICES ● Handling of DSU4 (ICE) pins in mass production Table 2.2-3 Handling of DSU4 (ICE) Pins in Mass Production Pin no. Pin name Pin handling 93 to 90 ICD3 to ICD0 OPEN 96 to 94 ICS2 to ICS0 OPEN 97 ICLK OPEN 98 BREAK OPEN 130 TRSTX Connected to INITX (Pin no. 131: External reset input pin) Figure 2.2-2 Connection Handling of the Reset Pin (TRSTX) for the Development Tool (DSU) in Mass Production INITX Reset input TRSTX As the reset pin (TRSTX) for the development tool supports both 3.3V and 5V power supplies, it can be connected directly to the INITX pin. 34 CHAPTER 2 HANDLING DEVICES ■ Pin State at Serial Programming Mode Pin State at asynchronous serial programming mode of MB91F467RA (FUJISTU FLASH MCU Programmer is used.) • Operation mode setting (At the mode pin is fixed.) MD0 MD1 MD2 MD3 P15_2 P15_3 L L H L L L P21_2: after it resets "H" output after control program is downloaded Hi-Z Unused at time of the serial programming I/O of the other is in the state of Hi-Z. It is recommended to use the mode pin level by fixation programming the serial usually. Please note that there is a pinl that enters the state of the output when you change the MD2 pin as follows. • Operation mode setting (When the mode pin changes on the way.) MD0 MD1 MD2 MD3 P15_2 P15_3 L L H→L L L L P21_2: After it resets "H" output After control program is downloaded Hi-Z P23_0: "H" Output P23_1: After it resets "L" output After it downloads "H" output P23_2: Pulse output of the main clock frequency Unused at time of the serial programming I/O is in the state of Hi-Z. 35 CHAPTER 2 HANDLING DEVICES 36 CHAPTER 3 CPU AND CONTROL BLOCK This chapter provides basic information on FR family’s architecture, specifications and instructions to introduce its CPU core functions. 3.1 Memory Space 3.2 Internal Architecture 3.3 Instruction Cache (Installed on MB91461) 3.4 Programming Model 3.5 Data Structure 3.6 Memory Map 3.7 Branch Instructions 3.8 EIT (Exception, Interrupt, and Trap) 3.9 Operating Modes 3.10 Reset (Device Initialization) 3.11 Clock Generation Control 3.12 PLL Interface 3.13 Device State Control 3.14 Interval Timer 37 CHAPTER 3 CPU AND CONTROL BLOCK 3.1 Memory Space The FR family has a logical address space of 4Gbytes (232 addresses) and the CPU linearly accesses the memory space. ■ Direct Addressing Area The following areas on the address space are used for I/O. In these areas, called "direct addressing areas", operand addresses can be specified directly in instructions. There are different direct addressing areas as shown below, depending on the size of the accessed data. Byte data access : 000H to 0FFH Halfword data access : 000H to 1FFH Word data access : 000H to 3FFH ■ Memory Map Figure 3.1-1 shows the memory map of MB91461/F467R. Figure 3.1-1 Memory Map of MB91461/F467R MB91461 MB91F467R MB91F467R External ROM external bus mode Built-in ROM external bus mode External ROM external bus mode I/O 0000 0400H Direct addressing area (See I/O map) I/O 0000 0400H I/O 0000 1000H 0000 1000H 0000 8000H 0000 BFFFH 0002 4000H BI-ROM 0002 C000H 0001 0000H 0002 0000H I-cache 0003 0000H 0004 0000H F-bus RAM 0010 0000H 0000 0000H 0000 0000H 0000 0000H 0003 0000 H I/O D-bus RAM (1wait) D-bus RAM (0wait) F-bus RAM 0003 4000 H External area Built-in FLASH Reset / mode vector Reset / mode vector 0010 4000 H 0015 0000 H External area Direct addressing area (See I/O map) I/O 0000 0400H 0000 1000H 0002 4000H 0002 C000H 0003 0000 H 0003 4000 H Direct addressing area (See I/O map) I/O D-bus RAM (1wait) D-bus RAM (0wait) F-bus RAM External area 0010 4000 H Reset / mode vector Built-in FLASH External area External area FFFF FFFFH FFFF FFFFH (*) This area is RAM to which the power supply keeps being supplied at the shutdown mode. FFFF FFFFH Each mode is set depending on the mode vector fetch after INITX is negated. (For mode settings, see "3.9.2 Mode Setting".) Note: RAM installed in MB91V460 is all "0" weight. 38 CHAPTER 3 CPU AND CONTROL BLOCK 3.2 Internal Architecture The CPU of the FR family is a high performance core that adopts highly functional instructions for embedded applications as well as a RISC architecture. ■ Features of the Internal Architecture • Adoption of RISC architecture Basic instruction: one instruction per cycle • 32-bit architecture General-purpose registers: 32 bits × 16 • Linear memory space of 4 Gbytes • Multipliers installed 32-bit × 32-bit multiplication: 5 cycles 16-bit × 16-bit multiplication: 3 cycles • Enhanced interrupt processing function High response speed (6 cycles) Multiple interrupts supported Level mask function (16 levels) • Enhanced instructions for I/O operation Memory-to-memory transfer instructions Bit processing instructions • High code efficiency Basic instruction word length: 16 bits • Low-power consumption Sleep mode, stop mode, shutdown mode 39 CHAPTER 3 CPU AND CONTROL BLOCK ■ Structure of the Internal Architecture The CPU of the FR family is based on the Harvard architecture in which the instruction bus and data bus are separated. The 32-bit ←→ 16-bit bus converter is connected to a 32-bit bus (D-bus), providing an interface between the CPU and the peripheral resources. The Harvard ←→ Princeton bus converter is connected to both of the I-bus and D-bus, providing an interface between the CPU and the bus controller. Figure 3.2-1 shows the structure of the internal architecture. Figure 3.2-1 Structure of the Internal Architecture DSU (debug support) FR60CPU Core D-bus I-bus Bit search I-cache RAM 32 32 CAN (2ch) Direct Map Cashe FLASH 32 16 Bus adapter RAM Bus converter 16 R-bus MB91461 MB91F467R DMAC 5ch Peripheral resources 40 External bus interface CHAPTER 3 CPU AND CONTROL BLOCK ■ CPU The 32-bit RISC FR architecture is compactly implemented on the CPU. A five-level instruction pipeline method is adopted to execute one instruction per cycle. The pipeline is composed of the following stages. Figure 3.2-2 shows the instruction pipeline. Instruction fetch (IF): Outputs the instruction address and fetches the instruction. Instruction decode (ID): Decodes the fetched instruction and also reads registers. Execution (EX): Executes the operation. Memory access (MA): Performs memory load or store accesses. Write back (WB): Writes the operation results (or loaded memory data) back to the registers. Figure 3.2-2 Instruction Pipeline CLK Instruction 1 WB Instruction 2 MA WB Instruction 3 EX MA WB Instruction 4 ID EX MA WB Instruction 5 IF ID EX MA WB IF ID EX MA Instruction 6 WB Instructions are not executed out of order. Therefore, if instruction A enters the pipeline ahead of instruction B, instruction A always reaches the writeback stage before instruction B. The standard execution speed is one instruction per cycle. However, load and store instructions that involve a memory wait, branch instructions without a delay slot, and multi-cycle instructions require more than one cycle to execute. The instruction execution speed also drops if delivery of instruction is slow. ■ Instruction Cache The on-chip instruction cache enables a high-performance system to be implemented without the added cost of external high-speed memory and related control logic. Even if the external bus speed is slow, instructions can be supplied to the CPU at high speed. Refer to "3.3 Instruction Cache (Installed on MB91461)" for details of instruction cache. 41 CHAPTER 3 CPU AND CONTROL BLOCK ■ 32-bit ←→ 16-bit Bus Converter This converter provides an interface between the 32-bit F-bus that is accessed at high speed and the 16-bit R-bus and enables the CPU to access data in the internal peripheral circuits. When a 32-bit access from the CPU occurs, the bus converter converts the access into two 16-bit accesses on the R-bus. Note that the access width of some internal peripheral circuits is restricted. ■ Harvard ←→ Princeton Bus Converter This bus converter coordinates CPU instruction and data accesses and provides a smooth interface to the external bus. The CPU has a Harvard architecture in which the instruction and data buses are separated. However, the bus controller that controls the external bus has a single-bus Princeton architecture. The bus converter prioritizes CPU instruction and data accesses and controls access to the bus controller. This function continuously optimizes the order of external bus accesses. 42 CHAPTER 3 CPU AND CONTROL BLOCK 3.2.1 Overview of Instructions In addition to standard RISC instructions, the FR family supports logical operations optimized for embedded applications, bit manipulation instructions, and direct addressing instructions. As each instruction is 16 bits in length (some instructions are 32-bit or 48-bit long), the FR provides superior memory utilization efficiency. The instruction set can be divided into the following functional groups. • Arithmetic operations • Load and store • Branch • Logical operations and bit manipulation • Direct addressing • Others ■ Arithmetic Operations The standard arithmetic operation instructions (add, subtract, compare) and shift instructions (logical shift, arithmetic operation shift) are provided. Addition and subtraction include operations with carry for use in multi-word operations and operations that do not change the flags, a convenience in address calculations. Also, 32-bit × 32-bit multiplication, 16-bit × 16-bit multiplication, and 32-bit / 32-bit step division instructions are provided. In addition, immediate value transfer instructions which set immediate values to registers are provided. Register-to-register transfer instructions are also enabled. The arithmetic operation instructions all perform operations using the general-purpose register and multiplication and division registers in the CPU. ■ Load and Store Load and store instructions read data from or write data to external memory. The instructions are also used to read from and write to the internal peripheral circuits (I/O). Load and store instructions are provided for byte (8 bits), halfword (16 bits), and word length (32 bits) access. In addition to standard register indirect memory addressing, some instructions support register indirect with displacement memory addressing and register indirect with register increment or decrement memory addressing. ■ Branch This includes the branch, call, interrupt, and return instructions. Branch instructions are divided into those that have a delay slot and those that do not. This enables optimization depending on applications. Refer to "3.7 Branch Instructions" for details of branch instructions. 43 CHAPTER 3 CPU AND CONTROL BLOCK ■ Logical Operations and Bit Manipulation Logical operation instructions can perform AND, OR, or EOR logical operations between general-purpose registers or between general-purpose registers and memory (and I/O). The bit manipulation instructions can manipulate the contents of memory (and I/O) directly. These instructions use standard register indirect memory addressing. ■ Direct Addressing Direct addressing instructions are instructions used for access between I/O and general-purpose register or between I/O and memory. Specifying an I/O address directly in an instruction rather than by register indirect addressing provides high-speed, high-efficiency access. Some instructions support register indirect memory addressing with register increment or decrement. ■ Other Instructions These include instructions to set the flags in the PS register and instructions to perform stack operations as well as sign-extend and zero-extend instructions. Function entry and exit processing instructions for highlevel languages and multi-register load/store instructions are also provided. 44 CHAPTER 3 CPU AND CONTROL BLOCK 3.3 Instruction Cache (Installed on MB91461) This section describes the instruction cache. ■ Overview The instruction cache is temporary memory. When an external low-speed memory accesses an instruction code, the instruction cache stores the single-accessed code to increase the second and subsequent access speeds. Setting this memory to the RAM mode enables software to directly read and write instruction cache data RAM and tag RAM. The instruction cache explained here is installed on MB91461. It is not available on MB91F467R. ■ Main Frame Structure • FR basic instruction length: 2 bytes • Block arrangement system: 2-way set associative system • Block: One way consists of 128 blocks One block consists of 16 bytes (= 4 sub-blocks) One sub-block consists of 4 bytes (= 1 bus access unit) Figure 3.3-1 Instruction Cache Structure I3 I2 I1 I0 Cache tag Sub-block 3 Sub-block 2 Sub-block 1 Sub-block 0 Block 0 Cache tag Sub-block 3 Sub-block 2 Sub-block 1 Sub-block 0 Block 127 Cache tag Sub-block 3 Sub-block 2 Sub-block 1 Sub-block 0 Block 0 Sub-block 3 Sub-block 2 Sub-block 1 Sub-block 0 Block 127 128 Blocks ··· Way-1 4 bytes 4 bytes 4 bytes ··· 4 bytes ··· 4 bytes Cache tag ··· ··· 128 Blocks ··· Way-2 45 CHAPTER 3 CPU AND CONTROL BLOCK Figure 3.3-2 Instruction Cache Tag Way-1 bit31 9 Address tag 8 Reserved 7 SBV3 6 SBV2 5 SBV1 Sub-block valid LRU Entry lock 4 SBV0 3 2 TAGV Reserved 1 LRU 0 ETLK 1 0 ETLK TAG valid Way-2 bit31 9 Address tag 8 Reserved 7 SBV3 6 SBV2 Sub-block valid 5 SBV1 4 SBV0 3 TAGV 2 Reserved TAG valid Entry lock [bit31 to bit9] Address tag The upper 23 bits of the memory address of the instruction cached in the corresponding block are stored. The memory address IA of the instruction data stored in sub-block k on block i is as follows: IA = Address tag × 211 + i × 24 + k × 22 These bits are used to perform coincidence checkout of instruction address that the CPU requests access to. • When the requested instruction data is in the cache (hit), the cache transfers the data to the CPU within one cycle. • When the requested instruction data is not in the cache (miss), the CPU and cache simultaneously acquire the data by external access. [bit7 to bit4] SBV3 to SBV0: Sub-block valid When the sub-block valid* is set to "1", the current instruction data at the tagged address is entered in the corresponding sub-block. Normally, two instructions are stored in a sub-block (except for the immediate value transfer instruction). [bit3] TAGV: TAG valid This bit indicates whether address tag value is valid. When this bit is "0", this block is invalid regardless of the sub-valid bit (flushed state). 46 CHAPTER 3 CPU AND CONTROL BLOCK [bit1] LRU bit (way 1 only) This bit is present only for way-1 instruction cache tag. Regarding the selected set, the bit indicates whether a way-1 or way-2 entry was accessed in the cache last. When LRU = 1, a way-1 set entry was accessed last. Conversely, when LRU = 0, a way-2 set entry was accessed last. [bit0] ETLK: Entry lock bit This bit locks all tagged entries within a block in the cache. When ETLK = 1, the locked state prevails so entries are not updated when they are not found in the cache. However, invalid sub-blocks are updated. If the data is not found in the cache when way 1 and way 2 are both entry-locked, the external memory is accessed after the loss of one cycle of "cache miss" evaluation. 47 CHAPTER 3 CPU AND CONTROL BLOCK 3.3.1 Control Register Control register consists of Cache size register (ISIZE) and Instruction Cache control register. This section explains the functions of these registers. ■ Cache Size Register (ISIZE) Figure 3.3-3 The Structure of Cache Size Register (ISIZE) ISIZE (8 bits) bit 000003C7H 7 6 5 4 3 2 − − − − − − − − − − − − 1 0 SIZE1 SIZE0 R/W R/W Initial value ------10B [bit1, bit0] SIZE1 and SIZE0 These bits are used to set the cache size. As shown in Figure 3.3-5, the cache size, IRAM size, and address map in the RAM mode change according to setting of these bits. When the cache size is changed, always turn on cache after unlocking flush and entry lock. Table 3.3-1 Cache Size Register SIZE1 SIZE0 Size 0 0 1 Kbyte 0 1 2 Kbytes 1 0 4 Kbytes [Initial value] 1 1 Setting disabled ■ Instruction Cache Control Register (ICHCR) Instruction Cache Control Register (ICHCR) controls the instruction cache operations. Writing to the ICHCR does not affect caching of instructions fetched within subsequent three cycles. Figure 3.3-4 The Structure of Instruction Cache Control Register (ICHCR) ICHCR (8 bits) bit 000003E7H 48 7 6 5 4 3 2 1 0 Initial value RAM R/W − − GBLK R/W ALFL R/W EOLK R/W ELKR R/W FLSH R/W ENAB R/W 0-000000B CHAPTER 3 CPU AND CONTROL BLOCK [bit7] RAM: RAM Mode Setting the RAM bit to "1" enables instruction cache to operate in the RAM mode. If the ENAB bit is "1" with cache on when the RAM mode is selected, cache RAM will be mapped as shown in Figure 3.35. [bit5] GBLK: Global lock bit This bit locks all current entries in cache. When GBLK = 1, valid entries in the cache are not updated at a "cache miss". However, invalid sub-blocks are updated. The resulting instruction data fetch operation is the same as for unlocked entries. [bit4] ALFL: Auto lock fail bit When a locked entry is attempted to be locked for the second time, the ALFL is set to "1". When entryauto-locked entry is updated for a locked entry, the new entry is not locked in the cache. Referencing is done for program debugging. This is cleared by writing "0". [bit3] EOLK: Entry auto lock bit This bit specifies whether auto locking feature is enabled or disabled for individual entries in instruction cache. Entries accessed (only at miss) while EOLK = 1 are locked when the entry lock bit in the cache tag is set to "1" by hardware. Locked entries are not subsequently updated at a cache miss. However, invalid sub-blocks are updated. To assure proper locking, first flush and then set this bit. [bit2] ELKR: Entry lock release bit This bit is used to clear entry lock bits at all cache tags. When ELKR is set to "1", entry lock bits at all cache tags are cleared to "0" at the next cycle. However, the value of this bit is held only for one clock cycle. It is cleared to "0" at the second and subsequent clock cycles. [bit1] FLSH: Flush bit This bit specifies flushing of instruction cache. When FLSH = 1, the cache data is flushed. However, the value of this bit is held only for 1 clock cycle. It is cleared to "0" at the second and subsequent clock cycles. [bit0] ENAB: Enable bit This bit enables or disables instruction cache. When ENAB = 0, the instruction cache is disabled so instruction accessing from the CPU is performed directly to the outside, without using the cache. When the instruction cache is disabled, instructions in the cache are saved. 49 CHAPTER 3 CPU AND CONTROL BLOCK Figure 3.3-5 RAM Address Map Address 00010000H 00010200H 00010400H 00010600H 00010800H ··· 00014000H 00014200H 00014400H 00014600H 00014800H ··· 00018000H 00018200H 00018400H 00018600H 00018800H ··· Cache OFF RAM OFF Cache OFF RAM ON TAG (way1) Cache ON 4K Cache ON 4K Cache ON 2K Cache ON 2K Cache ON 1K Cache ON 1K RAM OFF RAM ON RAM OFF RAM ON RAM OFF RAM ON TAG TAG TAG(way1) (way1) (way1) [TAG way1] [TAG way1] [TAG way1] [TAG way1] [TAG way1] [TAG way1] [TAG way1] [TAG way1] ··· ··· ··· ··· [TAG way1] TAG TAG TAG TAG(way2) (way2) (way2) (way2) [TAG way2] [TAG way2] [TAG way2] [TAG way2] [TAG way2] [TAG way2] [TAG way2] [TAG way2] ··· ··· ··· [TAG way2] IRAM $RAM(IRAM) $RAM $RAM $RAM(way1) (way1) (way1) (way1) (way1) IRAM IRAM *1 IRAM IRAM (way1) (way1) (way1) (way1) [IRAM way1] [$RAM way1] [$RAM way1] [IRAM way1]*2 [ $/I way1 ] [IRAM way] [ $/I way1 ] ··· ··· ··· ··· ··· ··· ··· 0001C000H IRAM $RAM(IRAM) (way2) (way2) 0001C200H 0001C400H *1 0001C600H 0001C800H [IRAM way2] [$RAM way2] ··· ··· ··· $RAM (way2) IRAM (way2) [$RAM way2] [IRAM way2]*2 ··· ··· $RAM (way2) IRAM (way2) [ $/I way2 ] ··· IRAM (way2) $RAM(way2) IRAM (way2) [IRAM way2] ··· [ $/I way2 ] ··· 00020000H [ ] refers to a mirror area *1 Same as the map when cache is on, in accordance with the value of the ISIZE register. *2 A mirror area is generated in the upper 2 Kbytes of every 4 Kbytes. Note: "$" represents cache. TAGRAM 00010000H 00010004H 00010008H 0001000CH 00010010H 00010014H 00010018H 0001001CH 00010020H 50 $RAM <- Entry at 00x address 00018000H <- Mirror at 00x 00018004H 00018008H 0001800CH <- Entry at 01x address 00018010H <- Mirror at 01x 00018014H 00018018H 0001801CH 00018020H Instruction at 000 address (SBV0) Instruction at 004 address (SBV1) Instruction at 008 address (SBV2) Instruction at 00C address (SBV3) Instruction at 000 address (SBV0) Instruction at 004 address (SBV1) Instruction at 008 address (SBV2) Instruction at 00C address (SBV3) CHAPTER 3 CPU AND CONTROL BLOCK Figure 3.3-6 Memory Assignment for Each Cache Size Address 000H 200H 400H 600H ··· 000H 200H 400H 600H Cache 4K $RAM (WAY1) Cache 2K $RAM Cache 1K $RAM IRAM Cache off IRAM IRAM $RAM (WAY2) ··· $RAM ··· $RAM IRAM IRAM IRAM Note: "$" represents cache. 51 CHAPTER 3 CPU AND CONTROL BLOCK 3.3.2 Cache State And Various Operating Modes This section explains the cache states in Various operating modes and setting method of instruction cache. ■ Cache State in Various Operating Modes The table below indicates the prevailing state for disable and flush when the associated bit is changed by bit manipulation instruction or other instructions. Table 3.3-2 Cache State in Various Operating Modes Immediately after Reset Tag Cache Memory Address Tag The contents are undefined. Sub-block Valid Bit The contents are undefined. LRU The contents are undefined. Entry Lock Bit The contents are undefined. TAG Valid Bit The contents are undefined. Control Register RAM 52 The contents are undefined. Normal Mode Global Lock Unlock Auto Lock Fail No fail Entry Auto Lock Unlock Entry Lock Release No release Enable Disabled Flush Not flushed Disable (ENAB = 0) The preceding state is held. Rewriting is impossible while the cache is disabled. The preceding state is held. Rewriting is impossible while the cache is disabled. The preceding state is held. Rewriting is impossible while the cache is disabled. The preceding state is held. Rewriting is impossible while the cache is disabled. The preceding state is held. Rewriting is impossible while the cache is disabled. The preceding state is held. Flushing is possible while the cache is disabled. The preceding state is held. Flushing is possible while the cache is disabled. The preceding state is held. Rewriting is possible while the cache is disabled. The preceding state is held. Rewriting is possible while the cache is disabled. The preceding state is held. Rewriting is possible while the cache is disabled. The preceding state is held. Rewriting is possible while the cache is disabled. Disabled The preceding state is held. Rewriting is possible while the cache is disabled. Flush The preceding state is held. The preceding state is held. The preceding state is held. The preceding state is held. The preceding state is held. (Entry lock release is required.) All entries are invalid. The preceding state is held. The preceding state is held. The preceding state is held. The preceding state is held. The preceding state is held. The preceding state is held. Flushed in cycle following memory accessing. Reverts to "0" subsequently. CHAPTER 3 CPU AND CONTROL BLOCK ■ Cache Entry Update Cache entries are updated as shown in the following table. Table 3.3-3 Cache Entry Update Unlock Lock Hit Not updated. Not updated. Miss The memory data is loaded and the cache entry data is updated. Not updated at tag miss. Updated when sub-block is invalid. ■ Instruction Cache Area for Caching • Regarding instruction cache, data is cached only in external bus space. • Even if the external memory data is updated by DMA transfer, coherency with cached instructions will not be maintained. In this case, flush the cache to maintain the coherency. • Instruction cache space can be set as non-cacheable area by chip select area. Even in this setting, a penalty of one cycle is incurred compared with the time when the cache is off. (Refer to "9.3 Chip Select Area".) 53 CHAPTER 3 CPU AND CONTROL BLOCK 3.3.3 Setting Up the Instruction Cache before Use This section explains the setting method for using instruction cache. ■ Setting Procedures Perform the following procedures to made the settings for using instruction cache. ● Initializing Before instruction cache is used, its content must be cleared. Set both the FLSH and ELKR bits of the register to "1" to delete the old data. ldi #0x000003e7,r0 // Instruction cache control register address ldi #0B00000110,r1 // Set "1" to FLSH bit (bit1) // Set "1" to ELKR bit (bit2) stb r1,@r0 // Writing to register The cache is now initialized. ● Enabling (turning on) the cache To enable the instruction cache, set the ENAB bit to "1". ldi #0x000003e7,r0 // Instruction cache control register address ldi #0B00000001,r1 // Set "1" to ENAB bit (bit0) stb r1,@r0 // Writing to register Subsequently-accessed instructions will be cached. Cache can be initialized and validated simultaneously. ldi #0x000003e7,r0 // Instruction cache control register address ldi #0B00000111,r1 // Set "1" to ENAB bit (bit0) // Set "1" to FLSH bit (bit1) // Set "1" to ELKR bit (bit2) stb r1,@r0 // Writing to register ● Disabling (turning off) the cache To disable the instruction cache, set the ENAB bit to "0". ldi #0x000003e7,r0 // Instruction cache control register address ldi #0B00000000,r1 // Set "0" to ENAB bit (bit0) stb r1,@r0 // Writing to register In this state (same as the state after a reset), no cache appears to be present and no action is taken. The cache can be turned off if the processing may experience problems due to cache overhead. 54 CHAPTER 3 CPU AND CONTROL BLOCK ● Locking all cached instructions To lock all the currently-cached instructions in the cache to prevent any from disappearing, set the GBLK bit of the register to "1". Unless the ENAB bit is also set to "1", the cache will be turned off and any instructions locked in the cache cannot be used. ldi #0x000003e7,r0 // Instruction cache control register address ldi #0B00100001,r1 // Set "1" to ENAB bit (bit0) // Set "1" to GBLK bit (bit5) stb r1,@r0 // Writing to register ● Locking specific instructions in cache To lock a specific group of instructions (e.g. subroutines) in cache, set the EOLK bit to "1" before executing these instructions. Instructions locked in this manner allow high-speed access as if using a fast built-in ROM. ldi #0x000003e7,r0 // Instruction cache control register address ldi #0B00001001,r1 // Set "1" to ENAB bit (bit0) // Set "1" to EOLK bit (bit3) stb r1,@r0 // Writing to register Instructions succeeding the stb instruction become valid, although this depends on the memory wait count. Set the EOLK bit to "0" when the desired group of instructions has been locked. ldi #0x000003e7,r0 // Instruction cache control register address ldi #0B00000001,r1 // Set "1" to ENAB bit (bit0) // Set "0" to EOLK bit (bit3) stb r1,@r0 // Writing to register ● Unlocking the cached instructions To unlock the data which is locked in (5) above, proceed as follows. ldi #0x000003e7,r0 // Instruction cache control register address ldi #0B00000000,r1 // Cache disabled stb r1,@r0 // Writing to register ldi #0B00000100,r1 // Set "1" to ELKR bit (bit2) stb r1,@r0 // Writing to register As only locked information is unlocked, locked instructions are sequentially replaced with new ones according to the state of the LRU bit. 55 CHAPTER 3 CPU AND CONTROL BLOCK 3.4 Programming Model This section describes the programming model, general-purpose registers, and dedicated registers of the FR family. ■ Basic Programming Model Figure 3.4-1 shows the basic programming model. Figure 3.4-1 Basic Programming Model 32 bits [Initial value] XXXX XXXXH R0 ··· R1 ··· ··· General-purpose registers ··· ··· ··· AC ··· R12 R13 R14 R15 56 ··· ··· Program counter PC Program status PS Table base register TBR Return pointer RP System stack pointer SSP User stack pointer USP Multiplication and division result registers MDH MDL ILM FP XXXX XXXXH SP 0000 0000H SCR CCR CHAPTER 3 CPU AND CONTROL BLOCK 3.4.1 General-purpose Registers Registers R0 to R15 are general-purpose registers. These registers are used as an accumulator for operations or as a pointer for memory access. ■ General-purpose Registers Figure 3.4-2 shows the structure of the general-purpose registers. Figure 3.4-2 Structure of the General-purpose Registers 32 bits [Initial value] R0 XXXX XXXXH R1 ··· ··· ··· ··· ··· ··· ··· ··· ··· R12 R13 R14 AC FP XXXX XXXXH R15 SP 0000 0000H Of the 16 general-purpose registers, the following registers are expected to be used in special applications. Therefore, some of the instructions used are enhanced. R13: Virtual accumulator (AC) R14: Frame pointer (FP) R15: Stack pointer (SP) The initial value of R0 to R14 after a reset is indeterminate. The initial value of R15 is 00000000H (SSP value). 57 CHAPTER 3 CPU AND CONTROL BLOCK 3.4.2 Dedicated Registers Each of the dedicated registers is used for a specific purpose. The FR family has the following dedicated registers: • Program Status (PS) • Condition Code Register (CCR) • System Condition code Register (SCR) • Interrupt Level Mask Register (ILM) • Program Counter (PC) • Table Base Register (TBR) • Return Pointer (RP) • System Stack Pointer (SSP) • User Stack Pointer (USP) • Multiply & Divide register ■ Program Status (PS) Stores the program status (PS) and consists of the ILM, SCR, and CCR sections. All undefined bits are reserved bits and always read as "0". Writing is invalid. Figure 3.4-3 shows the structure of the program status (PS). Figure 3.4-3 The Structure of the Program Status (PS) bit 31 20 16 ILM 58 10 8 7 SCR 0 CCR CHAPTER 3 CPU AND CONTROL BLOCK ■ Condition Code Register (CCR) Figure 3.4-4 shows the structure of the condition code register (CCR). Figure 3.4-4 The Structure of the Condition Code Register (CCR) bit 7 6 5 4 3 2 1 0 Initial value − − S I N Z V C --00XXXXB [bit5] S: Stack flag Specifies the stack pointer used as R15. Table 3.4-1 Stack Flag Value Function 0 SSP is used as R15. Automatically changes to "0" when an EIT occurs (Note that the value saved on the stack is the value before the bit is cleared). 1 USP is used as R15. This bit is cleared to "0" at reset. Set it to "0" when executing a RETI instruction. [bit4] I: Interrupt enable flag Controls the enabling and disabling of user interrupt requests. Table 3.4-2 Interrupt Enable Flag Value Function 0 User interrupts disabled. Cleared to "0" when an INT instruction is executed (Note that the value saved on the stack is the value before the bit is cleared). 1 User interrupts enabled. The ILM value controls the masking of user interrupt requests. This bit is cleared to "0" at reset. [bit3] N: Negative flag Indicates the sign of the operation result interpreted as an integer that is expressed in the complement of 2. Table 3.4-3 Negative Flag Value Function 0 Indicates that the operation has resulted in a positive value. 1 Indicates that the operation has resulted in a negative value. The initial value after a reset is indeterminate. 59 CHAPTER 3 CPU AND CONTROL BLOCK [bit2] Z: Zero flag Specifies whether the operation result was zero. Table 3.4-4 Zero Flag Value Function 0 Indicates that the operation has resulted in a value other than zero. 1 Indicates that the operation has resulted in zero. The initial value after a reset is indeterminate. [bit1] O: Overflow flag Interprets the operand used in the operation as the integer that is expressed in the complement of 2 and specifies whether or not the operation has caused an overflow. Table 3.4-5 Overflow Flag Value Function 0 Indicates that the operation has not caused an overflow. 1 Indicates that the operation has caused an overflow. The initial value after a reset is indeterminate. [bit0] C: Carry flag Specifies whether the operation has caused a carry or borrow from the MSB. Table 3.4-6 Carry Flag Value Function 0 Indicates that neither a carry nor borrow has occurred. 1 Indicates that a carry or borrow has occurred. The initial value after a reset is indeterminate. 60 CHAPTER 3 CPU AND CONTROL BLOCK ■ System Condition Code Register (SCR) Figure 3.4-5 shows the structure of the system condition code register (SCR). Figure 3.4-5 The Structure of the System Condition Code Register (SCR) bit 10 9 8 [Initial value] D1 D0 T XX0B [bit10, bit9] Step division flags These bits store intermediate data during the execution of step divisions. Do not modify the bits during a division operation. If performing other operations during a step division, restarting of the division is assured if the value of the PS register is saved and restored. The initial value after a reset is indeterminate. Executing the DIV0S instruction references the dividend and divisor and sets the bits. Executing the DIV0U instruction forcibly clears the bits. Do not perform any operation in expectation of the D0/D1 bits of the PS register before EIT branching in the EIT processing routine for a DIV0S/DIV0U instruction, user interrupt, and NMI simultaneous acceptance. If the bits are stopped by a break or step immediately before a DIV0S/DIV0U instruction, the D0/D1 bits of the PS register may not display the correct value. However, the operation result shows the correct value once it is restored. [bit8] Step trace trap flag This flag specifies whether the step trace trap is enabled or disabled. Table 3.4-7 Step Trace Trap Flag Value Function 0 Disables the step trace trap. 1 Enables the step trace trap. This disables the user NMI and all the user interrupts. Initialized to "0" at reset. The step trace trap function is used by the emulator. The function cannot be used by the user program when the emulator is in use. 61 CHAPTER 3 CPU AND CONTROL BLOCK ■ Interrupt Level Mask Register (ILM) Figure 3.4-6 shows the structure of the interrupt level mask register (ILM). Figure 3.4-6 The Structure of the Interrupt Level Mask Register (ILM) bit 20 19 18 17 16 [Initial value] ILM4 ILM3 ILM2 ILM1 ILM0 01111B The interrupt level mask register (ILM) stores the interrupt level mask value. The value stored in the interrupt level mask register (ILM) is used for the level mask. Only interrupt requests to the CPU with an interrupt level that has a higher priority than the level in the interrupt level mask register (ILM) are accepted. Level 0 (00000B) has the highest priority and level 31 (11111B) has the lowest priority. Restrictions apply to the values that can be set by the program. When the original value is between 16 and 31: A new value can be set to only 16 to 31. Executing an instruction to set a value to 0 to 15 transfers the "specified value + 16". When the original value is between 0 and 15: When the original value is between 0 and 15, any value between 0 and 31 can be set. It is initialized to 15 (01111B) at reset. ■ Program Counter (PC) Figure 3.4-7 shows the structure of the program counter (PC). Figure 3.4-7 The Structure of the Program Counter (PC) bit 31 PC 0 [Initial value] XXXXXXXXH [bit31 to bit0] This register functions as a program counter and points to the address of the currently executing instruction. Bit0 is set to "0" when updating the PC as part of instruction execution. Bit0 can have the value "1" only when an odd-numbered address is specified as a branch destination address. However, even if bit0 is "1", the bit0 value is ignored and instructions must be located at addresses that are multiples of two. The initial value after a reset is indeterminate. 62 CHAPTER 3 CPU AND CONTROL BLOCK ■ Table Base Register (TBR) Figure 3.4-8 shows the structure of the table base register (TBR). Figure 3.4-8 The Structure of the Table Base Register (TBR) bit 31 0 TBR [Initial value] 000FFC00H This register stores the top address of the vector table used for EIT processing. It is initialized to "000FFC00H" at reset. ■ Return Pointer (RP) Figure 3.4-9 shows the structure of the return pointer (RP). Figure 3.4-9 The Structure of the Return Pointer (RP) bit 31 0 RP [Initial value] XXXXXXXXH This pointer stores the return address from subroutines. Executing the CALL instruction transfers the value of the PC to the RP. Executing the RET instruction transfers the contents of the RP to the PC. The initial value after a reset is indeterminate. ■ System Stack Pointer (SSP) Figure 3.4-10 shows the structure of the system stack pointer (SSP). Figure 3.4-10 The Structure of the System Stack Pointer (SSP) bit 31 SSP 0 [Initial value] 00000000H The SSP is a system stack pointer. It functions as R15 when the S flag is "0". The SSP can also be specified explicitly. The SSP can also be used as the stack pointer that specifies the stack on which to save the PS and PC when an EIT occurs. It is initialized to "00000000H" at reset. 63 CHAPTER 3 CPU AND CONTROL BLOCK ■ User Stack Pointer (USP) Figure 3.4-11 shows the structure of the user stack pointer (USP). Figure 3.4-11 The Structure of the User Stack Pointer (USP) bit 31 0 USP [Initial value] XXXXXXXXH The USP is a user stack pointer. It functions as R15 when the S flag is "1". The USP can also be specified explicitly. The initial value after a reset is indeterminate. It cannot be used in the RETI instruction. ■ Multiply & Divide Registers Figure 3.4-12 shows the structure of the multiply & divide registers. Figure 3.4-12 The Structure of the Multiply & Divide Registers bit 31 0 MDH MDL These registers are used for multiplication and division and are 32 bits in length. The initial value after a reset is indeterminate. When a multiplication is executed: For a 32-bit × 32-bit multiplication, the 64-bit operation result is stored in the multiplication and division result registers as shown below. MDH: Upper 32 bits MDL: Lower 32 bits For a 16-bit × 16-bit multiplication, the result is stored as follows. MDH: Indeterminate MDL: 32-bit result When a division is executed: The dividend is stored in MDL when the calculation is started. When the division is performed by executing DIV0S/DIV0U, DIV1, DIV2, DIV3, DIV4S instructions, the result is stored in MDH and MDL. MDH: Remainder MDL: Quotient 64 CHAPTER 3 CPU AND CONTROL BLOCK 3.5 Data Structure This section describes the data structure of the FR family. ■ Bit Ordering The FR family uses little endian bit ordering. Figure 3.5-1 shows the data assignment of the bit ordering. Figure 3.5-1 Data Assignment of Little Endian Bit Ordering bit 31 29 30 27 28 25 26 23 24 21 22 19 20 17 18 15 16 13 14 11 12 9 10 7 8 5 6 3 4 1 2 MSB 0 LSB ■ Byte Ordering The FR family uses big endian byte ordering. Figure 3.5-2 shows the data assignment of the byte ordering. Figure 3.5-2 Data Assignment of Big Endian Byte Ordering Memory MSB bit 31 23 15 7 LSB 0 10101010B 11001100B 11111111B 00010001B bit 7 0 n Address 10101010B (n+1) Address 11001100B (n+2) Address 11111111B (n+3) Address 00010001B 65 CHAPTER 3 CPU AND CONTROL BLOCK ■ Word Alignment ● Program access Programs used for the FR family must be located at addresses that are multiples of two. Bit0 of the PC is set to "0" when the PC is updated as part of instruction execution. Bit0 can become "1" only when an odd-numbered address is specified as a branch destination address. However, even if bit0 is "1", the bit0 value is ignored and instructions must be located at addresses that are multiples of two. There is no odd-numbered address exception. ● Data access The address for data access in the FR family is forcibly aligned as shown below, depending on the data access size. Word access: Address is a multiple of 4. (The lowest two bits are forcibly set to "00B".) Halfword access: Address is a multiple of 2. (The lowest bit is forcibly set to "0"). Byte access: ———— In word or halfword data access, it is the effective address that may have bits forcibly set to "0". For example, in the @(R13, Ri) addressing mode, the register values prior to the addition are used without change (even if the LSB is "1") and the lower bit of the addition result is masked. The register values before the calculation are not masked. [Example] LD @(R13, R2), R0 R13 00002222H R2 00000003H +) Result of addition Address pin 66 00002225H Lower two bits forcibly masked 00002224H CHAPTER 3 CPU AND CONTROL BLOCK 3.6 Memory Map This section describes the memory map of the FR family. ■ Memory Map The address space is 32-bit long and linear. Figure 3.6-1 shows the memory map. Figure 3.6-1 Memory Map 0000 0000H Byte data 0000 0100H Halfword data Direct addressing area 0000 0200H Word data 0000 0400H 000F FC00H Vector table 000F FFFFH Initial area FFFF FFFFH Direct addressing area The following areas of the address space are I/O areas that can be accessed by direct addressing. Address operands can be specified directly in instructions. The size of directly addressable address areas depends on the length of the data being accessed. Byte data (8 bits): 000H to 0FFH Halfword data (16 bits): 000H to 1FFH Word data (32 bits): 000H to 3FFH Initial vector table area The area between 000FFC00H and 000FFFFFH is the initial EIT vector table area. The vector table used in EIT processing can be set to a user-specified address by changing the time base register (TBR). However, after initialization at reset, the vector table is located in this area. 67 CHAPTER 3 CPU AND CONTROL BLOCK 3.7 Branch Instructions This section describes the branch instructions of the FR family. ■ Overview of the Branch Instructions In the FR family, you can specify whether branch instructions operate with or without a delay slot. 68 CHAPTER 3 CPU AND CONTROL BLOCK 3.7.1 Branch Instructions with a Delay Slot This section describes branch instructions with a delay slot. ■ Branch Instructions with a Delay Slot The instructions with the notation listed below perform the branch operation with a delay slot. JMP:D @Ri CALL:D label12 CALL:D @Ri RET:D BRA:D label9 BNO:D label9 BEQ:D label9 BNE:D label9 BC:D label9 BNC:D label9 BN:D label9 BP:D label9 BV:D label9 BNV:D label9 BLT:D label9 BGE:D label9 BLE:D label9 BGT:D label9 BLS:D label9 BHI:D label9 ■ Description of the Branch Operation with a Delay Slot Branching with a delay slot means that the branch operation occurs after executing the instruction placed immediately after the branch instruction (in what is called the delay slot). As the instruction in the delay slot is executed before the branch operations, the apparent execution speed is one cycle. However, if no useful instruction can be placed in the delay slot, a NOP instruction must be placed instead. [Example] ; Instruction sequence ADD R1, R2 ; BRA:D LABEL ; Branch instruction MOV R2, R3 ; Delay slot: Executed before branching ··· LABEL:ST R3, @R4 ; Branch destination For conditional branch instructions, the instruction in the delay slot is executed whether or not the branch condition is satisfied. Although delayed branch instructions appear to reverse the execution order of some instructions, this only applies to the updating of the program counter (PC). Other operations (such as updating or referencing registers) are executed in the order they appear in the program. The following describes some specific examples. 1) The value of Ri referenced by the JMP:D @Ri or CALL:D @Ri instruction is not changed by any update of Ri by the instruction in the delay slot. [Example] LDI:32 #Label, R0 JMP:D @R0 LDI:8 #0, ; Branch to Label R0 ; Does not change the branch destination address. ··· 69 CHAPTER 3 CPU AND CONTROL BLOCK 2) The value of RP referenced by the RET:D instruction is not changed by any update of RP by the instruction in the delay slot. [Example] RET:D MOV ; Branch to the address previously set in RP. R8, RP ; Does not affect the return operation. ··· 3) The flags referenced by the Bcc:D rel instruction are not affected by the instruction in the delay slot. [Example] ADD #1, R0 ; Flag change BC:D Overflow ; Branch depending on the result of the previous instruction AND CCR #0 ; This flag update does not reference the above branch instruction. ··· 4) Referencing the RP by the instruction in the CALL:D instruction’s delay slot reads the RP value updated by the CALL:D instruction. [Example] CALL:D Label MOV RP, ; Update RP and branch. R0 ; Transfers the RP value resulting from the execution of the above CALL:D. ··· ■ Restrictions on the Operation with a Delay Slot Instructions that can be placed in the delay slot Only instructions that meet the following criteria can be executed in the delay slot. 1-cycle instruction Not a branch instruction Instruction not affected by the order in which it is executed "One-cycle instructions" are instructions with "1", "a", "b", "c", or "d" listed in the number of cycles column of the instruction list. Step trace trap Step trace traps do not occur between execution of branch instructions with a delay slot and the delay slot. Interrupts/NMI Interrupts and NMI are not accepted between execution of branch instructions with a delay slot and the delay slot. Undefined instruction exception If the delay slot contains an undefined instruction, the undefined instruction exception is not generated. In this case, the undefined instruction is executed as a NOP instruction. 70 CHAPTER 3 CPU AND CONTROL BLOCK 3.7.2 Branch Instructions without a Delay Slot This section describes the branch instructions without a delay slot. ■ Instructions without a Delay Slot The instructions with the notation listed below perform the branch operation without a delay slot. JMP @Ri CALL label12 CALL @Ri RET BRA label9 BNO label9 BEQ label9 BNE label9 BC label9 BNC label9 BN label9 BP label9 BV label9 BNV label9 BLT label9 BGE label9 BLE label9 BGT label9 BLS label9 BHI label9 ■ Description of Operation without a Delay Slot Branching without a delay slot means that instructions are always executed in the order they appear in the program. The instruction following the branch instruction is never executed before branching. [Example] ; Instruction sequence ADD R1, R2 ; BRA LABEL ; Branch instruction (without a delay slot) MOV R2, R3 ; Not executed R3, @R4 ; Branch destination ··· LABEL: ST The number of cycles required to execute a branch instruction without a delay slot is two cycles if the branch occurs and one cycle if the branch does not occur. As no instruction can be placed in the delay slot for a branch instruction without a delay slot, instruction code efficiency is increased compared with a branch instruction with a delay slot containing a NOP instruction. Use operation with a delay slot when there is a useful instruction to place in the delay slot and do not use operation with a delay slot otherwise. This satisfies both execution speed and code efficiency. 71 CHAPTER 3 CPU AND CONTROL BLOCK 3.8 EIT (Exception, Interrupt, and Trap) The term EIT is a generic term for exceptions, interrupts and traps. EITs interrupt execution of the current program when an event occurs and pass control to another program. Exceptions are generated based on the execution context. Execution restarts from the instruction that caused the exception. Interrupts are generated independently of the execution context. The event is caused by hardware. Traps are generated based on the execution context. These include traps generated by an operation within the program like a system call. Execution restarts from the instruction following the instruction that caused the trap. ■ EIT Features • Multiple interrupt support • Level mask function for interrupts (15 levels are available to the user.) • Trap instruction (INT) • EITs for activating the emulator (hardware/software) ■ EIT Triggers The following items can generate an EIT. • Reset • User interrupt (internal resources, external interrupts) • NMI • Delayed interrupt • Undefined instruction exception • Trap instruction (INT) • Trap instruction (INTE) • Step trace trap • Coprocessor absent trap • Coprocessor error trap Note: There are restrictions on the delay slot of branch instructions regarding EITs. For more details, see "3.7 Branch Instructions". ■ Returning from EIT To recover from EIT, issue RETI instruction. 72 CHAPTER 3 CPU AND CONTROL BLOCK 3.8.1 EIT Interrupt Levels Interrupt levels have the range 0 to 31 and are managed as a 5-bit value. ■ EIT Interrupt Levels Table 3.8-1 lists the interrupt levels. Table 3.8-1 Interrupt Levels Level Interrupt source Binary Decimal 00000B 0 (System reserved) ··· ··· ··· ··· ··· ··· 00011B 3 (System reserved) 00100B 4 00101B 5 (System reserved) ··· ··· ··· ··· ··· ··· 01110B 14 (System reserved) 01111B 15 NMI (for the user) 10000B 16 Interrupt 10001B 17 Interrupt ··· ··· ··· ··· ··· ··· 11110B 30 Interrupt 11111B 31 — { Remarks If the original value of the ILM is between 16 and 31, values in this range cannot be set to the ILM by the program. INTE instruction Step trace trap When set to the ILM, user interrupts are disabled. When set to the ICR, the interrupt is disabled. Levels 16 to 31 are available for the user. The undefined instruction exception, coprocessor absent trap, coprocessor error trap, and INT instruction are not affected by the interrupt level. Similarly, they do not change the ILM. 73 CHAPTER 3 CPU AND CONTROL BLOCK ■ I Flag This flag enables or disables interrupts. It is located in bit4 of the CCR in the PS. Table 3.8-2 I Flag Value Function 0 Interrupts disabled Cleared to "0" by the INT instruction (However, the value saved on the stack is the value before the bit is cleared). 1 Interrupts enabled Masking of interrupt requests is controlled by the value in ILM. ■ ILM The ILM register is located in the PS register (bit20 to bit16) and stores the interrupt level mask value. Only interrupt requests to the CPU with an interrupt level that has a higher priority than the level in the ILM are accepted. Level 0 (00000B) has the highest priority and level 31 (11111B) has the lowest priority. Restrictions apply to the values that can be set by the program. When the original value is between 16 and 31, only new values between 16 and 31 can be set. Executing an instruction to set a value between 0 and 15 transfers the value "specified value + 16". If the original value is between 0 and 15, any value between 0 and 31 can be set. The ST ILM instruction is used to set any value. ■ Level Mask for Interrupts/NMI When an NMI or interrupt request occurs, the interrupt level of that interrupt source (Refer to Table 3.8-1) is compared with the level mask value held in the ILM. If the following condition is satisfied, the interrupt is masked and the request not accepted: Interrupt level of interrupt source ≥ Level mask value 74 CHAPTER 3 CPU AND CONTROL BLOCK 3.8.2 Interrupt Control Register (ICR) These are registers located in the interrupt controller and set the level for each interrupt request. The Interrupt Control Register (ICR) registers are provided for each interrupt request input. The Interrupt Control Register (ICR) registers are mapped in the I/O memory space and are accessed by the CPU via the bus. ■ Interrupt Control Register (ICR) Bit Structure Figure 3.8-1 shows the bit structure of the interrupt control register (ICR). Figure 3.8-1 The Bit Structure of the Interrupt Control Register (ICR) bit 7 6 5 4 3 2 1 0 − − − − − − ICR4 R ICR3 R/W ICR2 R/W ICR1 R/W ICR0 R/W Initial value ---111111B [bit4] ICR4 Always "1". [bit3 to bit0] ICR3 to ICR0 These are the lower 4 bits of the interrupt level for the interrupt request. They are readable and writable. Including bit4, an Interrupt Control Register (ICR) can have values in the range 16 to 31. ■ ICR Mapping Table 3.8-3 lists the interrupt source, interrupt control register and interrupt vector. Table 3.8-3 Interrupt Source, Interrupt Control Register and Interrupt Vector Interrupt Control Register Interrupt Source IRQ00 IRQ01 IRQ02 IRQ03 ··· ··· IRQ126 IRQ127 Corresponding Interrupt Vector No. No. Address ICR00 00000440H ICR01 00000441H ··· ··· ICR63 0000047FH Address Hexadecimal Decimal 10H 16 TBR+3BCH 11H 17 TBR+3B8H 12H 18 TBR+3B4H 13H 19 TBR+3B0H ··· ··· ··· ··· ··· ··· 3DH 142 TBR+1C4H 8FH 143 TBR+1C0H • TBR initial value: "000FFC00H" • For more details, see "CHAPTER 11 INTERRUPT CONTROLLER". 75 CHAPTER 3 CPU AND CONTROL BLOCK 3.8.3 System Stack Pointer (SSP) The System Stack Pointer (SSP) is used as the pointer to the stack used to save and restore data on receiving or returning from an EIT. ■ System Stack Pointer (SSP) Figure 3.8-2 shows the structure of the system stack pointer (SSP). Figure 3.8-2 The Structure of the System Stack Pointer (SSP) bit 31 0 Initial value 00000000H SSP The value of the System Stack Pointer (SSP) is decremented by 8 by EIT processing and incremented by 8 on returning from the EIT by the RETI instruction. It is initialized to "00000000H" at reset. When the S flag in the CCR is "0", the System Stack Pointer (SSP) can also function as R15 generalpurpose register. ■ Interrupt Stack This is the area pointed to by the SSP and used to save and restore the PC and PS values. After an interrupt occurs, the PC is placed at the address pointed to by SSP and the PS at the address "SSP+4". Figure 3.8-3 shows the interrupt stack. Figure 3.8-3 Interrupt Stack [Before interrupt] SSP 80000000H [After interrupt] SSP 7FFFFFF8H Memory 80000000H 7FFFFFFCH 7FFFFFF8H 76 80000000H 7FFFFFFCH 7FFFFFF8H PS PC CHAPTER 3 CPU AND CONTROL BLOCK 3.8.4 Table Base Register (TBR) This register indicates the top address of the EIT vector table. ■ Table Base Register (TBR) Figure 3.8-4 shows the structure of the table base register (TBR). Figure 3.8-4 The Structure of the Table Base Register (TBR) bit 31 0 Initial value 000FFC00H TBR The vector address for each EIT is calculated by adding the offset value for that EIT to the Table Base Register (TBR). It is initialized to "000FFC00H" at reset. ■ EIT Vector Table The 1 Kbyte area starting from the address pointed to by TBR is the EIT vector area. Each vector consists of four bytes. The following formula shows the relationship between the vector number and vector address. vctadr = TBR + vctofs = TBR + (3FCH − 4 × vct) vctadr: Vector address vctofs: Vector offset vct: Vector number The lower 2 bits of the addition result are always treated as "00B". The initial vector table area after a reset is the area between "000FFC00H" and "000FFFFFH". Special functions are assigned to some vectors. "000FFFFCH" and "000FFFF8H" are always assigned to the reset vector and mode vector respectively, even if the TBR value is modified. Maskable factors are determined by each model. For the vector table designed for MB91461/F467R, see the interrupt vector table shown in "Table B-2". 77 CHAPTER 3 CPU AND CONTROL BLOCK 3.8.5 Multiple EIT Processing When more than one EIT occurs at the same time, the CPU repetitively performs the following operations: select one EIT to accept, execute the EIT sequence, and then detect the next EIT. The CPU executes the handler instructions for the last EIT to be accepted when EIT detection finds no more EITs that can be accepted. Therefore, the sequence for executing the handlers for multiple EITs that occur at the same time is determined by the following two factors: • The priority of the accepting EITs • How other EITs are masked when an EIT is accepted ■ Priority of Accepting EITs The EIT acceptance priority is the priority order for selecting which EIT to execute. The EIT sequence consists of saving the PS and PC, updating the PC (as required), and performing masking of other EITs. Consequently, the handler of the first EIT to be accepted is not necessarily executed first. Table 3.8-4 lists the priority order for accepting EITs and masking of other EITs. Table 3.8-4 Priority Order for Accepting EITs and Masking of Other EITs Priority for accepting EITs 78 EIT Masking of other EITs 1 Reset Other EITs are cleared. 2 Instruction break Other EITs are canceled. (ILM = 4) 3 INTE instruction Other EITs are canceled. (ILM = 4) 4 Undefined instruction exception Other EITs are canceled. (I flag = 0) 5 INT instruction/Coprocessor exception I flag = 0 6 User interrupt ILM = Level of accepted EIT 7 NMI (for the user) ILM = 15 8 NMI (for the emulator) Other EITs are canceled. (ILM = 4) 9 Step trace trap Other EITs are canceled. (ILM = 4) 10 Operand break Other EITs are canceled. (ILM = 4) CHAPTER 3 CPU AND CONTROL BLOCK After accepting an EIT and performing masking of other EITs, the priority for executing the handlers of EITs that occur at the same time is as shown in Table 3.8-5. Table 3.8-5 Execution Priority for EIT Handlers Handler Execution Priority EIT 1 Reset 2 Undefined instruction exception 3 Instruction break 4 INTE instruction 5 NMI (for the emulator) 6 Step trace trap 7 Operand break 8 NMI (for the user) 9 INT instruction/Coprocessor exception 10 User interrupt Figure 3.8-5 shows the multiple EIT processing. Figure 3.8-5 Multiple EIT Processing Main routine NMI handler INT instruction handler Priority (High) NMI occurrence (Low) INT instruction execution (1) Execute first (2) Execute next 79 CHAPTER 3 CPU AND CONTROL BLOCK 3.8.6 EIT Operation This section describes EIT operations. ■ EIT Operation In the following explanation, the transfer source "PC" contains the address of the instruction at which the EIT was detected. Also, in the operation description, the "address of the next instruction" means that the instruction that detected the EIT was as follows. • For LDI:32.......PC + 6 • For LDI:20, COPOP, COPLD, COPST, COPSV.......PC + 4 • For all other instructions.......PC + 2 ■ Operation of User Interrupts and NMI When a user interrupt or user NMI interrupt request is generated, the following sequence determines whether or not the request can be accepted. [Determining whether an interrupt request can be accepted] 1) Compare the interrupt levels of any simultaneously occurring requests and select the interrupt with the highest priority level (smallest level value). As for maskable interruption, the value that corresponding ICR maintains is used as a comparison level. Moreover, the constant is decided beforehand in NMI. 2) If more than one interrupt request with the same level is generated, select the interrupt request with the lowest interrupt number. 3) If the interrupt level ≥ the level mask value, the interrupt request is masked and not accepted. If the interrupt level < the level mask value, proceed to 4). 4) If the selected interrupt request is a maskable interrupt and the I flag is "0", the interrupt request is masked and not accepted. If the I flag is "1", proceed to 5). If the selected interrupt request is an NMI, proceed to 5) regardless of the I flag value. 5) If the above conditions are satisfied, the interrupt request is accepted at the end of the current instruction processing. If a user interrupt or NMI request is accepted when an EIT request is detected, the CPU operates as follows, using the interrupt number corresponding to the accepted interrupt request. Note: ( ) represents the address that the register points to in the operation sequence below. [Operation] 1) SSP − 4 → SSP 2) PS → (SSP) 3) SSP − 4 → SSP 4) Address of the next instruction → (SSP) 5) Interrupt level of the accepted request → ILM 6) "0" → S flag 80 CHAPTER 3 CPU AND CONTROL BLOCK 7) (TBR + vector offset of the received interrupt request) → PC Note: ( ) represents the address that the register points to in the operation sequence below. After the interrupt sequence is completed, the system checks whether any new EITs are present before executing the first instruction of the handler. If an EIT that can be accepted is present, the CPU enters the EIT processing sequence. If the OR CCR, ST ILM, MOV Ri, or PS instruction is executed to enable an interrupt while a user interrupt or NMI is being generated, the above instruction may be executed twice before and after the interrupt handler. However, this does not affect the operation, as it only set the same value twice to the registers in the CPU. Do not perform any operation in expectation of the contents of the PS register before EIT branching in the EIT processing routine. ■ Operation of the INT Instruction INT #u8 instruction operates as follows: Branches to the interrupt handler at the vector indicated by u8. [Operation] 1) SSP − 4 → SSP 2) PS → (SSP) 3) SSP − 4 → SSP 4) PC + 2 → (SSP) 5) "0" → I flag 6) "0" → S flag 7) (TBR + 3FCH-4 × u8) → PC Note: ( ) represents the address that the register points to in the operation sequence below. ■ Operation of the INTE Instruction INTE instruction operates as follows: Branches to the interrupt handler pointed to by vector #9. [Operation] 1) SSP − 4 → SSP 2) PS → (SSP) 3) SSP − 4 → SSP 4) PC + 2 → (SSP) 5) "00100B" → ILM 6) "0" → S flag 7) (TBR + 3D8H) → PC Note: ( ) represents the address that the register points to in the operation sequence below. Do not use the INTE instruction during a processing routine for the INTE instruction or step trace trap. The INTE does not generate an EIT during step execution. 81 CHAPTER 3 CPU AND CONTROL BLOCK ■ Operation of the Step Trace Trap If the T flag in the SCR of the PS is set to enable the step trace function, a trap occurs after execution of each instruction. The trap causes execution to break. [Conditions for detecting a step trace trap] • T flag = 1 • Not a delayed branch instruction • Executing anything other than the processing routine for the INTE instruction and step trace trap If the above conditions are satisfied, a break occurs at the end of the current instruction. [Operation] 1) SSP − 4 → SSP 2) PS → (SSP) 3) SSP − 4 → SSP 4) Address of the next instruction → (SSP) 5) "00100B" → ILM 6) "0" → S flag 7) (TBR + 3CCH) → PC Note: ( ) represents the address that the register points to in the operation sequence below. The user NMI and user interrupts are disabled when the step trace trap is enabled by the T flag. Similarly, the INTE instruction does not generate EITs. In the FR family, a trap is generated from the instruction following the instruction in which the T flag was set. ■ Operation of the Undefined Instruction Exception The undefined instruction exception is generated if an undefined instruction is detected at instruction decoding. [Conditions for detecting an undefined instruction exception] • An undefined instruction is detected at instruction decoding. • The instruction is not in a delay slot (not located immediately after a delayed branch instruction). If the above conditions are satisfied, an undefined instruction exception is generated and execution breaks. [Operation] 1) SSP − 4 → SSP 2) PS → (SSP) 3) SSP − 4 → SSP 4) PC → (SSP) 5) "0" → S flag 6) (TBR + 3C4H) → PC Note: ( ) represents the address that the register points to in the operation sequence below. The saved PC value is the address of the instruction that caused the undefined instruction exception. 82 CHAPTER 3 CPU AND CONTROL BLOCK ■ Coprocessor Absent Trap When a coprocessor instruction is executed to use an unmounted coprocessor, a coprocessor absent trap is generated. [Operation] 1) SSP − 4 → SSP 2) PS → (SSP) 3) SSP − 4 → SSP 4) Address of the next instruction → (SSP) 5) "0" → S Flag 6) (TBR + 3E0H) → PC Note: ( ) represents the address that the register points to in the operation sequence below. ■ Coprocessor Error Trap If an error occurs while using a coprocessor and then the coprocessor instruction that operates the coprocessor is executed, a coprocessor error trap is generated. [Operation] 1) SSP − 4 → SSP 2) PS → (SSP) 3) SSP − 4 → SSP 4) Address of the next instruction (SSP) 5) "0" → S Flag 6)(TBR + 3DCH) → PC Note: ( ) represents the address that the register points to in the operation sequence below. ■ Operation of the RETI Instruction The RETI instruction returns from an EIT processing routine. [Operation] 1) (R15) → PC 2) R15 + 4 → R15 3) (R15) → PS 4) R15 + 4 → R15 Note: ( ) represents the address that the register points to in the operation sequence below. The RETI instruction must be executed when the S flag is "0". 83 CHAPTER 3 CPU AND CONTROL BLOCK 3.9 Operating Modes This section describes the operating modes of the FR family. ■ Overview of the Operating Modes The FR family uses the bus mode and the access mode as its operating modes. ■ Bus Mode The bus mode controls operations of the built-in ROM and external access function. It is set by the values of the mode setup pins (MD2, MD1, MD0) and ROMA bit in the mode data. ■ Access Mode This mode controls the external data bus width. It is set by the values of the WTH1 and WTH0 bits in the mode register as well as the DBW0 bit in ACR0 to ACR3 (Area Configuration Register). 84 CHAPTER 3 CPU AND CONTROL BLOCK 3.9.1 Bus Mode The following three bus modes are available to the FR family. For more details, see "3.1 Memory Space". ■ Bus Mode 0 (Single Chip Mode) In this mode, access to the internal I/O, F-bus RAM and F-bus ROM (FLASH) is valid, but not to other areas. The external pins function as peripheral resources or general-purpose ports. They do not function as bus pins. Note: This mode cannot be used for MB91461. ■ Bus Mode 1 (Built-in ROM & External Bus Mode) In this mode, the internal I/O, F-bus RAM and F-bus ROM (FLASH) are valid. Access to an externally accessible area becomes access to external space. Some external pins function as bus pins. Note: This mode cannot be used in MB91461. ■ Bus Mode 2 (External ROM & External Bus Mode) In this mode, access to the internal I/O and F-bus RAM is enabled but access to F-bus ROM (FLASH) is disabled. As a result, all access can be provided for external space. Some external pins function as bus pins. 85 CHAPTER 3 CPU AND CONTROL BLOCK 3.9.2 Mode Setting The operating modes of the FR family are set by the mode pins (MD2, MD1, MD0) and mode register (MODR). ■ Mode Pins There are three mode pins - MD2, MD1 and MD0. These pins specify how the mode vector fetch is performed. Table 3.9-1 shows setting for the mode vector fetch. Table 3.9-1 Setting for the Mode Vector Fetch Mode Pins Mode Name Reset Vector Access Area Remark MD3 MD2 MD1 MD0 0 0 0 0 Built-in ROM mode vector Internal * Setting prohibited in MB91461 0 0 0 1 External ROM mode vector External Bus width specified by the mode register *: Always set MD3 at "0". However, settings that are not listed in the table are prohibited. Note: The FR family does not support the external mode vector fetch by a multiplexed bus. ■ Mode Register (MODR) The data to be written to the mode register by the mode vector fetch is called mode data. For the mode vector fetch, see "3.10.3 Reset Sequence". After an operating mode has been set in the mode register (MODR), the device operates in this operating mode. MODR is set by all types of reset. User programs cannot write data to MODR. Reference: Traditionally, no data is present at the addresses "000007FFH" of the mode register when using in the FR family. Rewriting is enabled in the emulator mode. Use 8-bit data transfer instructions in this mode. 16-bit and 32-bit transfer instructions cannot write data. Figure 3.9-1 shows the details of the mode register. 86 CHAPTER 3 CPU AND CONTROL BLOCK [Details of the mode register] Figure 3.9-1 Details of the Mode Register MODR Address: bit 000FFFF8H 7 6 5 4 3 0 0 0 0 0 2 1 0 ROMA WTH1 WTH0 Initial value XXXXXXXXB [bit7 to bit3] Reserved bits Always set these bits to "00000B". Operation is not guaranteed when other values are set. [bit2] ROMA (built-in ROM enable bit) This bit specifies whether to validate the internal F-bus RAM and F-bus ROM (FLASH) areas. ROMA Function Remark 0 External ROM mode Validates the Internal F-bus RAM. The built-in ROM area ("40000H" to "FFFFFH") becomes an external area. 1 Built-in ROM mode Validates the Internal F-bus RAM and F-bus ROM (FLASH). Note: Set "0" in MB91461. [bit1, bit0] WTH1 and WTH0 (bus width setting bits) These bits set the bus width that is valid when the external bus mode is selected. When the external bus mode is in use, the values are set at BW1 and BW0 bits of AMD0 (CS0 area). Table 3.9-2 Function WTH1 WTH0 Function Remark 0 0 8-bit bus width External bus mode 0 1 16-bit bus width External bus mode 1 0 - Setting disabled 1 1 Single chip mode Single chip mode Note: The single chip mode cannot be used in MB91461. 87 CHAPTER 3 CPU AND CONTROL BLOCK Note: It is necessary to store the mode data to set it to the mode vector into 000FFFF8H as byte data. Because the big endian is used as byte endian in the FR family, please store the mode data into MSB of bit31 to bit24 as shown in Figure 3.9-2. Figure 3.9-2 Notes of Mode Data Error bit 31 24 23 16 15 8 7 000FFFF8H XXXXXXXXB XXXXXXXXB XXXXXXXXB bit 31 Correct 000FFFF8H 000FFFFCH 88 0 MODR 24 23 16 15 8 7 0 XXXXXXXX XXXXXXXX XXXXXXXX MODR B B B Reset Vector CHAPTER 3 CPU AND CONTROL BLOCK 3.10 Reset (Device Initialization) This section describes reset operations that initialize the devices of MB91461/F467R. ■ Overview of Reset (Device Initialization) When a reset source occurs, the device stops operations of all programs and hardware and performs initialization. This state is called reset state. When the reset source is released, the device restarts the program and hardware operations from the initial state. The series of operations from this reset state through the start of program and hardware operations is called reset sequence. 89 CHAPTER 3 CPU AND CONTROL BLOCK 3.10.1 Reset Level The reset operation of MB91461/F467R is divided into two levels. The occurrence factor and initialization type of each reset differ. This section describes these two reset levels. ■ Setting Initialization Reset (INIT) The most powerful reset level, which initializes all settings, is called setting initialization reset (INIT). The following items are initialized by INIT. [Items that are initialized by INIT] Device operating mode (bus mode and external bus width settings) All settings related to internal clocks (clock source selection, PLL control, division ratio settings) All settings related to the CS0 area of the external bus All settings related to the status of other pins All settings to be initialized by operation initialization reset (RST) For details, see the description of each function. After power-on, always execute INIT at the INITX pin. ■ Operation Initialization Reset (RST) The normal reset level, which initializes program operation, is called operation initialization reset (RST). RST occurs at the same time as INIT. The following items are initialized by RST. [Items that are initialized by RST] Program operation CPU and internal bus Register settings of peripheral circuits I/O port settings All settings related to the CS0 area of the external bus For details, see the description of each function. 90 CHAPTER 3 CPU AND CONTROL BLOCK 3.10.2 Reset Source This section describes the reset sources of the MB91461/F467R and the reset levels to be generated. Past reset sources can be obtained by reading the reset source register (RSRR). (For details of the registers and flags appearing in each description, see "3.11.5 Block Diagram of Clock Generation Control Block" and "3.11.6 Registers in the Clock Generation Control Block"). ■ INITX Pin Input (Setting Initialization Reset Pin) The INITX pin is an external pin that functions as a setting initialization reset pin. A setting initialization reset (INIT) request is generated when a "L" level signal is input to the INITX pin. The INIT request is released by inputting a "H" level signal to the INITX pin. When INIT is generated by a request from this pin, the INIT bit (bit15) in RSRR (reset source register) is set. INIT generated by this request is the most powerful reset of all reset sources and takes priority over all inputs, operations, and status. Always execute INIT at the INITX pin immediately after power-on. Also retain a "L" level input to the INITX pin to secure the oscillation stabilization wait time of the requested oscillation circuit. (Executing INIT at the INITX pin initializes the set oscillation stabilization wait time to the minimum value.) Occurrence source: "L" level input to the external INITX pin Release source: "H" level input to the external INITX pin Occurrence level: Setting initialization reset (INIT) Corresponding flag: INIT bit (bit15) ■ Writing to the SRST Bit in STCR (Software Reset) A software reset request occurs when "0" is written to the SRST bit (bit4) of the standby control register (STCR). The software reset request is an operation initialization reset (RST) request. The software reset request is released when that request is accepted and RST is generated. When the software reset request generates RST, the SRST bit (bit11) in RSRR is set. When the SYNCR bit (bit9) in the time-base counter control register (TBCR) is set, RST is not generated by the software reset request until all bus access stops. 91 CHAPTER 3 CPU AND CONTROL BLOCK For this reason, it may take a long time until RST is generated, depending on the bus usage status. Occurrence source: Writing "0" to the SRST bit (bit4) in STCR Release source: Operation initialization reset (RST) generated Occurrence level: Operation initialization reset (RST) Corresponding flag: SRST bit (bit11) Operating mode setting bits ■ Watchdog Reset Writing data to the watchdog timer control register (RSRR) starts the watchdog timer. If A5H and 5AH are not written subsequently to the watchdog reset occurrence delay register (WPR) within the cycle set by the WT1 and WT0 bits (bit9 and bit8) in the RSRR, a watchdog reset request occurs. The watchdog reset request is the setting initialization reset (INIT) request. When INIT or RST occurs, the accepted watchdog reset request is released. If INIT is generated by the watchdog reset request, the WDOG bit (bit13) in the reset source register (RSRR) is set. If INIT is generated by the watchdog reset request, the set oscillation stabilization wait time is not initialized. Occurrence source: Elapse of set watchdog timer cycle Release source: Generation of setting initialization reset (INIT) or operation initialization reset (RST) Occurrence level: Setting initialization reset (INIT) Corresponding flag: WDOG bit (bit13) ■ Hardware Watchdog Reset The hardware watchdog timer starts immediately after INITX is released. INIT is issued when the counter overflows after the timer remains uncleared for a certain amount of time. Occurrence source: Elapse of set hardware watchdog timer cycle Release source: Generation of setting initialization reset (INIT) or operation initialization reset (RST) Occurrence level: Setting initialization reset (INIT) Corresponding flag: HWDCS bit (bit10) 92 CHAPTER 3 CPU AND CONTROL BLOCK 3.10.3 Reset Sequence When the reset source is released, the device starts execution of the reset sequence. The reset sequence operation differs for each reset level. This section describes such operation at the different levels. ■ Setting Initialization Reset (INIT) Release Sequence When the setting initialization reset (INIT) request is released, the device executes the following operations in sequence: 1) Releases INIT and switches the oscillation stabilization waiting state 2) Retains operation initialization reset (RST) state during oscillation stabilization wait time (bit3 and bit2: OS1 and OS0 in STCR) and stops the internal clock 3) Sets RST and starts internal clock operation 4) Releases RST and switches to the normal operation state 5) Reads mode vector from address 000FFFF8H 6) Writes the mode vector to the mode register (MODR) at address 000007FDH 7) Reads reset vector from address 000FFFFCH 8) Writes the reset vector to the program counter (PC) 9) Starts program operation at the address indicated by PC ■ Operation Initialization Reset (RST) Release Sequence When the RST request is released, the device executes the following operations in sequence: 1) Releases RST and switches to the normal operation state 2) Reads mode vector from address 000FFFF8H 3) Writes the mode vector to the mode register (MODR) at address 000007FDH 4) Reads reset vector from address 000FFFFCH 5) Writes the reset vector to the program counter (PC) 6) Starts program operation at the address indicated by PC Note: As for the reset generated at a time other than stop and shutdown, some RAM contents may be destroyed. 93 CHAPTER 3 CPU AND CONTROL BLOCK 3.10.4 Oscillation Stabilization Wait Time The device automatically switches to the oscillation stabilization wait state when it returns from a state in which the original oscillation stopped, or may have stopped. This function disables use of unstable oscillator output after oscillation has started. During the oscillation stabilization wait time, supply of internal and external clock stops and only the built-in time-base counter operates. The device waits for the elapse of the stabilization wait time set by the standby control register (STCR). This section details the oscillation stabilization wait operation. ■ Oscillation Stabilization Wait Factors The oscillation stabilization wait factors are shown below. ● When setting initialization reset (INIT) is released Immediately after INIT has been released by various factors, the device switches to the oscillation stabilization wait state. After the oscillation stabilization wait time has elapsed, the device switches to operation initialization reset (RST) state. ● At return from the stop mode Immediately after the stop mode has been released, the device switches to the oscillation stabilization wait state. However, if the stop mode is released by the setting initialization reset (INT) request, the device switches to the INIT state. It switches to the oscillation stabilization wait state after INIT has been released. After the oscillation stabilization wait time has elapsed, the device switches to the state corresponding to the stop mode release factor. At return due to input of valid external interrupt request (including NMI): The device switches to the normal operation state. At return due to the INIT request: The device switches to RST state. ● At return due to error state occurrence when PLL is selected If a PLL control error (*) occurs when the PLL is operating as a source clock, the device automatically switches to the oscillation stabilization wait time to secure the PLL lock time. After the oscillation stabilization wait time has elapsed, the device switches to the normal operation state. (*): Change of multiply rate during use of PLL and PLL operation enable bit error, etc. ● When a hardware watchdog reset occurs When a hardware watchdog reset occurs, internal reset is issued during 1024 cycles of the original oscillation clock. As the internal reset sets the OS1 and OS0 bits of the STCR to "0" (initial value), oscillation stabilization wait is not performed. 94 CHAPTER 3 CPU AND CONTROL BLOCK ● At return from the shutdown mode Immediately after the shutdown mode has been released, the device switches to the oscillation stabilization wait state. However, if the shutdown mode is released by the setting initialization reset (INIT) request, the device switches to the INIT state. It switches to the oscillation stabilization wait state after INIT has been released. A signal from the external oscillator or the internal oscillation circuit that is divided by 218 is used as the oscillation stabilization wait time. ■ Selection of Oscillation Stabilization Wait Time The built-in time-base counter is used to count the oscillation stabilization wait time. When the device switches to the oscillation stabilization wait state because an oscillation stabilization wait factor occurs, the built-in time-base counter starts counting the oscillation stabilization wait time after it has been initialized once. The OS1 and OS0 bits (bit3 and bit2) in the standby control register (STCR) can be used to select and set one of the four oscillation stabilization wait times. The set oscillation stabilization wait time can be initialized by setting initialization reset (INIT) at the external INITX pin, return from the shutdown mode, or hardware watchdog reset. At other resets such as the INIT by watchdog reset and the operation initialization reset (RST), the oscillation stabilization wait time that was set before the reset is held. 95 CHAPTER 3 CPU AND CONTROL BLOCK 3.10.5 Reset Operation Modes Operation initialization reset (RST) usually supports two modes: ordinary (asynchronous) reset mode, and synchronous reset mode. Use the SYNCR bit (bit9) in the time-base counter control register (TBCR) to select the mode. The set reset mode can be initialized only by the setting initialization reset (INIT). INIT is always executed asynchronously. This section describes operations of these reset modes. ■ Ordinary Reset Operation Immediate switching to the RST state when the RST request occurs is called ordinary reset. When the RST request is accepted in the ordinary reset mode, the device immediately switches to the RST state, regardless of the internal bus access state. The result of bus access being performed when this mode switches to another mode is not guaranteed. However, the bus access request is always accepted. When the SYNCR bit (bit9) in the TBCR is "0", the device operates in the ordinary reset mode. The initial value after INIT has occurred is the ordinary reset mode. ■ Synchronous Reset Operation Switching to the RST state after all bus accesses have stopped when the RST request occurs is called synchronous reset. Even if the RST request is accepted in the synchronous reset mode, the device does not switch to the RST state if the internal bus is being accessed. When the above request is accepted, a sleep request is issued to the internal buses. When each bus stops operation and switches to the sleep state, the device switches to the RST state. All bus accesses stop when the synchronous reset mode switches to another mode and the results of all bus accesses are guaranteed. However, if bus access does not stop for some reason, each request cannot be accepted. (Even in this case, INIT becomes valid immediately.) Bus access does not stop in the following cases: Reference: • The DMA controller does not delay device switching to each state because it stops transfer when it receives a request. • When the SYNCR bit (bit9) in the TBCR is "1", it indicates the synchronous reset mode. • For using software reset on the synchronous mode, see the limitations of the bit9:SYNCR bit of TBCR (time-base timer counter control register). After INIT has occurred, the initial value returns to the ordinary reset mode. 96 CHAPTER 3 CPU AND CONTROL BLOCK 3.11 Clock Generation Control This section describes clock generation control. ■ Internal Clock Generation The internal clocks of the MB91461/F467R are generated as shown below. Source clock: This clock is generated by dividing a signal from the X0 or X1 pin, or a signal from the internal oscillation circuit by two. Base clock generation: The base clock is generated by selecting either the source clock divided by 2 or the PLL oscillation clock. Generation of each internal clock: Dividing the base clock generates four different types of operating clocks to be supplied to different parts of the device. Generation and control of each clock is described below. For details of the registers and flags in the following descriptions, see "3.11.5 Block Diagram of Clock Generation Control Block" and "3.11.6 Registers in the Clock Generation Control Block". ■ Selection of Clock This section describes selection of the source clock. The source clock is generated by connecting the resonator to pins X0 and X1 (external oscillation pins), oscillating using the internal oscillation circuit, and then dividing this signal by two. All clocks including the external bus clock are supplied by MB91461/F467R itself. An internal base clock is generated by selecting one of the following clocks: • Source clock divided by two • Clock generated by using PLL to multiply the clock that is directly input from the internal oscillation circuit or pins X0 and X1. Clock selection is controlled by the setting of the clock source control register (CLKR). 97 CHAPTER 3 CPU AND CONTROL BLOCK 3.11.1 PLL Control Operation (oscillation) enable/disable and multiply rate settings can be controlled for PLL oscillation circuits corresponding to the main clock. Such settings are controlled by setting the clock source control register (CLKR), PLLDIVM and PLLDIVN (multiply rate setting registers). This section describes control of these PLL settings. ■ Enabling PLL Operation Oscillation enable/disable for the main PLL is controlled according to the setting of the PLL1EN bit (bit10) in the CLKR. PLL1EN is initialized to "0" after setting initialization reset (INIT) has been executed and PLL oscillation is stopped. When PLL oscillation is stopped, PLL output cannot be selected as the source clock. When program operation is started, fist, set the multiply rate for the PLL and enable PLL oscillation. Then, switch the clock after the PLL lock wait time has elapsed. In this case, the time-base timer interrupt should be used to indicate the end of the PLL lock wait time. When PLL output is selected as the base clock, the PLL operation cannot be stopped (write operations to the corresponding register is ignored). Before stopping the PLL e.g. when the device switches to the stop mode, reselect the source clock divided by two as the base clock. When the OSCD1 and OSCD2 bits (bit0 and bit1) in the standby control register (STCR) are set so that oscillation stops in the stop mode, the PLLs also automatically stop when the device switches to the stop mode. When the device subsequently returns from the stop mode, the PLLs automatically start oscillation. When these bits are set so that oscillation does not stop in the stop mode, the PLLs do not stop automatically. In this case, if required, set operation to stop before the device switches to the stop mode. ■ PLL Multiply Rate The PLL multiply rate is set by the PLLDIVM and PLLDIVN registers. All bits of both registers are initialized to "0" after setting initialization reset (INIT) has been executed. [PLL multiply rate setting] To change the PLL multiply rate setting to its initial value, set the rate after starting program operation or before enabling PLL operation. After modifying the multiply rate, switch the source clock to PLL clock when the lock wait time has elapsed. In this case, the time-base timer interrupt should be used to indicate that the PLL lock wait time is over. When changing the PLL multiply rate setting during operation, first, switch the source clock to a clock other than the appropriate PLL. After changing the multiply rate, switch the source clock back to PLL clock, as described above, when the lock wait time has elapsed. 98 CHAPTER 3 CPU AND CONTROL BLOCK 3.11.2 Oscillation Stabilization Wait Time and PLL Lock Wait Time When a clock selected as the source clock is not in a stable operating state, oscillation stabilization wait time is required. (See "3.10.4 Oscillation Stabilization Wait Time".) After PLLs start operation, lock wait time is required until the output stabilizes to the set frequency level. This section describes wait time in each case. ■ Wait Time after Power-on After power-on, it is necessary to input a "L" level signal to the INITX pin (setting initialization reset pin). In this state, the lock wait time need not be considered because no PLL operation is enabled. ■ Wait Time after Setting Initialization When setting initialization reset (INIT) is released, the device switches to the oscillation stabilization wait state. In this state, the oscillation stabilization wait time is generated internally. In this state, the lock wait time need not be considered because no PLL operation is enabled. ■ Wait Time after PLL Operation is Enabled When operation of the inactive PLL is enabled after program operation has started, PLL output cannot be used before the lock wait time has elapsed. If the PLL is not selected as the source clock, program operation can be executed even during the lock wait time. In this case, the time-base timer interrupt should be used to indicate that the PLL lock wait time is over. ■ Wait Time after the PLL Multiply Rate is Changed When the multiply rate setting of the operating PLL is changed after program operation has been started, PLL output cannot be used unless the lock wait time has elapsed. If the PLL is not selected as the source clock, program operation can be executed even during the lock wait time. In this case, the time-base timer interrupt should be used to indicate that the PLL lock wait time is over. 99 CHAPTER 3 CPU AND CONTROL BLOCK ■ Wait Time after Return from the Stop Mode When the device switches to the stop mode after program operation had been started, the oscillation stabilization wait time set by the program is internally generated at cancellation of that mode. If the oscillation circuit for the clock of the clock source is set to stop in the stop mode, the oscillation stabilization wait time of the oscillation circuit or the lock wait time of the PLL being used, whichever is longer, becomes necessary. Set the oscillation stabilization wait time before switching the device to the stop mode. When the oscillation circuit for the clock of the clock source is set not to stop in the stop mode, PLLs are not stopped automatically. Therefore, oscillation stabilization wait time is not required unless PLLs are stopped. Set the oscillation stabilization wait time to the minimum value before entering the stop mode. 100 CHAPTER 3 CPU AND CONTROL BLOCK 3.11.3 Clock Distribution Operating clocks for each function are created from the base clock generated from the selected clock. The device has three internal operating clocks. The division ratio of each of these clocks can be set independently. This section describes such operating clocks. ■ CPU Clock (CLKB) The CPU clock is used by the CPU, internal memory, and internal buses. The following circuits use the CPU clock. • CPU • Built-in RAM • Bit search module • I-bus, D-bus, X-bus, F-bus • DMA controller • DSU The operable upper frequency limit is 80 MHz. Do not set combinations of multiply rate and division ratio that exceed this upper frequency limit. ■ Peripheral Clock (CLKP) The peripheral clock is used by peripheral circuits and peripheral buses. The following circuits use this clock. • Peripheral bus • Clock control block (bus interface block only) • Interrupt controller • Peripheral I/O ports • I/O port bus • External interrupt input • LIN-UART • 16-bit timer • A/D converter • Free-run timer • Reload timer • Up/down counter • Input capture • Output compare • I2C interface • PPG 101 CHAPTER 3 CPU AND CONTROL BLOCK The operable upper frequency limit is 20 MHz. Do not set combinations of multiply rate and division ratio that exceed this upper frequency limit. ■ External Bus Clock (CLKT) The external bus clock is used by the external extension bus interface. The following circuits use the external bus clock. • External extension bus interface • External Clock output The operable upper frequency limit is 40 MHz. Do not set combinations of multiply rate and division ratio that exceed this upper frequency limit. 102 CHAPTER 3 CPU AND CONTROL BLOCK 3.11.4 Clock Division The division ratio of each internal operating clock can be set independently from the base clock. This function enables setting of the optimum operating frequency for each circuit. ■ Setting the Division Ratio The division ratio is set by the basic clock division setting register 0 (DIVR0) and basic clock division setting register 1 (DIVR1). DIVR0 and DIVR1 each have 4 setting bits corresponding to each clock. "Register setting value + 1" is the division ratio for the base clock. Even if the set division ratio is an odd number, the duty is always 50%. When the register setting value is changed, the new division ratio becomes valid from the rising edge of the next clock after setting. ■ Initializing the Division Ratio Setting Division ratio setting is not initialized if an operation initialization reset (RST) occurs, and the division ratio setting before RST occurs is held. The division ratio setting is initialized only when the setting initialization reset (INIT) occurs. In the initial state, the division ratios of all clocks other than the peripheral clock (CLKP) are "1". For this reason, always set a division ratio before changing the clock source to a faster one. Note: The operable upper frequency limit is specified for each clock. Operation is not guaranteed if the operable upper frequency limit is exceeded as a result of the combined source clock selection, PLL multiply rate setting, and division ratio setting. Take care not to make a mistake in the change setting sequence for source clock selection. 103 CHAPTER 3 CPU AND CONTROL BLOCK 3.11.5 Block Diagram of Clock Generation Control Block Figure 3.11-1 shows the block diagram of the clock generation control block. For details of the registers in the diagram, see "3.11.6 Registers in the Clock Generation Control Block". ■ Block Diagram of Clock Generation Control Block Figure 3.11-1 Block Diagram of Clock Generation Control Block [Clock generation block] Selector External bus clock division Stop control Peripheral clock division Selector CPU clock division CPU clock Peripheral clock External bus clock CLKR Register Oscillation circuit 1/2 Source clock Selector X0 X1 Selector R-bus DIVR0, DIVR1 Registers Selector PLL 1/2 Base clock Hardware Watchdog X0A X1A Oscillation circuit CR Oscillation circuit [Stop/sleep control block] Internal interrupt STGR Register Internal reset Stop state State transition control circuit Sleep state Reset occurrence F/F Reset occurrence F/F Internal reset (RST) Internal reset (INIT) [Reset source circuit] INITX pin RSRR Register MB91461 MB91F467R [Watchdog control block] WPR Register Watchdog F/F Time-base counter Counter clock CTBR Register Selector TBCR Register Interrupt enabled 104 Overflow detection F/F Time-base timer interrupt request CHAPTER 3 CPU AND CONTROL BLOCK 3.11.6 Registers in the Clock Generation Control Block This section describes the registers in the clock generation control block. ■ RSRR: Reset Source Register and Watchdog Timer Control Register Figure 3.11-2 shows the structure of the reset source register and watchdog timer control register. Figure 3.11-2 The Structure of the Reset Source Register and Watchdog Timer Control Register RSRR bit Address: 000480H Read/Write Initial value (INITX pin) Initial value (INIT) Initial value (RST) 15 14 13 12 11 10 9 8 INIT (R) 1 * X Reserved WDOG (R) 0 * X Reserved SRST (R) 0 X * Reserved WT1 (R/W) 0 0 0 WT0 (R/W) 0 0 0 (R) X X X (R) X X X (R) X X X * : Initialized depending on the reset source X: Not initialized RSRR is used to retain the preceding reset source, set the cycle of the watchdog timer and control the watchdog timer start. When this register is read, the held reset source is cleared. If a reset occurs several times before the register is read, several reset resource flags are accumulated and set. The watchdog timer is started when this register is written to. Watchdog timer operation continues until RST occurs. [bit15] INIT: External reset occurrence flag This bit indicates whether reset (INIT) was caused by input to the INITX pin. Table 3.11-1 External Reset Occurrence Flag Value Function 0 INIT not caused by input to INITX pin 1 INIT caused by input to INITX pin This bit is cleared to "0" immediately after being read. The bit is read only. Write does not affect other bit values. Upon power-on, supply the "L" level to the INITX pin which is 8ms or greater. Otherwise, the flag may not be set. [bit14] Reserved bit This bit is reserved. 105 CHAPTER 3 CPU AND CONTROL BLOCK [bit13] WDOG: Watchdog reset occurrence flag This bit indicates whether reset (INIT) was caused by the watchdog timer. Table 3.11-2 Watchdog Reset Occurrence Flag Value Function 0 INIT not caused by watchdog timer 1 INIT caused by watchdog timer This bit is cleared to "0" when reset (INIT) is caused by input to the INITX pin upon power-on or immediately after it is read. The bit is read only. Write does not affect other bit values. [bit12] Reserved bit This bit is reserved. [bit11] SRST: Software reset occurrence flag This bit indicates whether reset (RST) is caused by data write (software reset) to the SRST bit of the STCR register. Table 3.11-3 Software Reset Occurrence Flag Value Function 0 RST not caused by software reset 1 RST caused by software reset This bit is cleared to "0" when reset (INIT) is caused by input to the INITX pin upon power-on or immediately after it is read. The bit is read only. Write does not affect other bit values. [bit10] Reserved bit This bit is reserved. 106 CHAPTER 3 CPU AND CONTROL BLOCK [bit9, bit8] WT1 and WT0: Watchdog timer interval select bits These bits are used to set the watchdog timer cycle. Select one of the four watchdog timer cycles from the table below by writing the values to these bits. Table 3.11-4 Watchdog Timer Interval Select Bits Minimum writing interval to WPR required to control watchdog reset occurrence Duration between last 5AH writing to WPR and occurrence of watchdog reset WT1 WT0 0 0 φ × 216 [Initial value] φ × 216 to φ × 217 0 1 φ × 218 φ × 218 to φ × 219 1 0 φ × 220 φ × 220 to φ × 221 1 1 φ × 222 φ × 222 to φ × 223 ("φ" represents the base clock cycle.) These bits are initialized to "00B" at reset (RST). They are read only. Only the first write after reset (RST) is valid and subsequent writes are invalid. 107 CHAPTER 3 CPU AND CONTROL BLOCK ■ STCR: Standby Control Register Figure 3.11-3 shows the structure of the standby control register. Figure 3.11-3 The Structure of the Standby Control Register STCR bit Address: 000481H 7 6 4 3 2 1 0 HIZ SRST OS1 OS0 Reserved OSCD1 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) 0 1 1 0 0 1 1 0 1 1 X X 1 1 0 X 1 X X X X STOP SLEEP Read/Write (R/W) Initial value (INITX pin) 0 Initial value (INIT) 0 Initial value (RST) 5 0 This register is used to control the device operating mode. It switches toe device to the stop or sleep mode (standby mode) and controls the pins in the stop mode and oscillation stop. It also sets the oscillation stabilization wait time and issues a software reset instruction. Note: When selecting a standby mode, always use the following sequence while the synchronous standby mode is in use. The synchronous standby mode is set by the bit8: SYNCS of the time-base counter control register (TBCR). (LDI#value_of_standby,R0) ; "value_of_standby" represents write data to STCR (LDI#_STCR,R12) ; "_STCR" is the STCR address (481H) STB ; Writing to STCR R0,@R12 LDUB @R12,R0 ; Reading from STCR for synchronous standby LDUB @R12,R0 ; Dummy reading from STCR again NOP ; NOP × 5 to adjust the timing NOP NOP NOP NOP [bit7] STOP: STOP mode bit This bit is used to instruct the device to switch to the stop mode. It has priority over bit6 (SLEEP bit) when "1" is written to both bits. Therefore, the device switches to the STOP mode. Table 3.11-5 STOP Mode Bit Value Function 0 The device does not switch to the stop mode [Initial value] 1 The device switches to the stop mode This bit is initialized to "0" when reset (RST) or a stop return factor occurs. This bit is readable and writable. 108 CHAPTER 3 CPU AND CONTROL BLOCK [bit6] SLEEP: SLEEP mode bit This bit is used to instruct the device to switch to the sleep mode. Bit7 (STOP bit) has priority over this bit when both bits are "1". Therefore, the device switches to the stop mode. Table 3.11-6 SLEEP Mode Bit Value Function 0 The device does not switch to the sleep mode [Initial value] 1 The device switches to the sleep mode This bit is initialized to "0" when reset (RST) or a sleep return factor occurs. This bit is readable and writable. [bit5] HIZ: Hi-Z mode bit This bit is used to control the pin state when the device is in the stop mode. Table 3.11-7 Hi-Z Mode Bit Value Function 0 Holds the pin state before the device switches to the stop mode. 1 Sets pin output to the high-impedance state when the device is in the stop mode [Initial value] This bit is initialized to "1" at reset (INIT). This bit is readable and writable. [bit4] SRST: Software reset bit This bit is used to issue the software reset (RST) instruction. Table 3.11-8 Software Reset Bit Value Function 0 Issues the software reset instruction 1 Does not issue the software reset instruction [Initial value] This bit is initialized to "1" at reset (RST). This bit is readable and writable and the read value is always "1". Note: For using software reset on the synchronous mode, see the limitations of the bit9:SYNCR bit of TBCR (time-base timer counter control register). 109 CHAPTER 3 CPU AND CONTROL BLOCK [bit3, bit2] OS1 and OS0: Oscillation stabilization wait time select bits These bits set the oscillation stabilization wait time after a reset (INIT) or after a return to the stop mode. The table below shows the combination of values written to these bits and the four associated oscillation stabilization wait times. Table 3.11-9 Oscillation Stabilization Wait Time Select Bits MB91461 OS1 OS0 Oscillation stabilization wait time 0 0 0 MB91F467R When the original oscillation is 18 MHz When the original oscillation is 4 MHz When the original oscillation is 32.768kHz φ × 21 [Initial value] 0.44 µs 1µs 61µs 1 φ × 211 0.46 ms 1ms 62.5µs 1 0 φ × 216 14.6 ms 32ms 2s 1 1 φ × 222 0.93 s 2s 128s "φ" represents the base clock cycle. These bits are initialized to "00B" at reset (INIT) caused by input to the INITX pin. These bits are readable and writable. [bit1] Reserved bit This bit is reserved. [bit0] OSCD1: Oscillation stop bit This bit controls stop operation of the oscillation circuits in the stop mode Table 3.11-10 Oscillation Stop Bit Value Function 0 Oscillation does not stop in the stop mode 1 Oscillation stops in the stop mode [Initial value] This bit is initialized to "1" at reset (INIT). This bit is readable and writable. 110 CHAPTER 3 CPU AND CONTROL BLOCK ■ TBCR: Time-base Counter Control Register Figure 3.11-4 shows the structure of the time-base counter control register. Figure 3.11-4 The Structure of the Time-base Counter Control Register TBCR bit Address: 000482H Read/Write Initial value (INIT) Initial value (RST) 15 14 13 12 11 10 TBIF R/W 0 TBIE R/W 0 TBC2 R/W X TBC1 R/W X TBC0 R/W X Reserved 0 0 X X X X R/W X 9 8 SYNCR SYNCS R/W R/W 0 0 X X This register controls time-base timer interrupts. The register enables time-base timer interrupts and selects the interrupt interval time. [bit15] TBIF: Time-base timer interrupt flag This bit serves as the time-base timer interrupt flag. The bit indicates that the interval time set by the time-base counter (set at bit13 to bit11: TBC2 to TBC0) has passed. When this bit is set to "1" while interrupt occurrence is enabled by the TBIE bit (bit14: TBIE = 1), a time-base timer interrupt request is generated. Table 3.11-11 Time-base Timer Interrupt Flag Clearing factor "0" written by instruction Setting factor Elapse of the set interval time (falling edge of time-base counter output detected) This bit is initialized to "0" at reset (RST). This bit is readable and writable. However, only "0" can be written. Writing "1" does not change the bit value. The read value of read-modify-write (RMW) instructions is always "1". [bit14] TBIE: Time-base timer interrupt enable bit This bit enables output of the time-base timer interrupt request. The bit controls the interrupt request output caused by the elapse of the interval time to which the timebase counter was set. When this bit is set to "1", a time-base timer interrupt request is generated when bit15 (TBIF bit) is set to "1". Table 3.11-12 Time-base Timer Interrupt Enable Bit Value Function 0 Disables time-base timer interrupt request output [Initial value] 1 Enables time-base timer interrupt request output This bit is initialized to "0" at reset (RST). This bit is readable and writable. 111 CHAPTER 3 CPU AND CONTROL BLOCK [bit13 to bit11] TBC2, TBC1, TBC0: Time-base timer counter select bits These bits set the interval time of the time-base counter used for the time-base timer. The table below shows the combination of values written to these bits and their associated 8 intervals. Table 3.11-13 Time-base Timer Counter Select Bits TBC2 TBC1 TBC0 Timer interval time When the original oscillation is 18 MHz and PLL is multiplied by 4 0 0 0 φ × 211 28.4 µs 0 0 1 φ × 212 56.9 µs 0 1 0 φ × 213 114 µs 0 1 1 φ × 222 58.3 ms 1 0 0 φ × 223 117 ms 1 0 1 φ × 224 233 ms 1 1 0 φ × 225 466 ms 1 1 1 φ × 226 932 ms "φ" represents the base clock cycle. The initial values of these bits are undefined. Always set a value before enabling an interrupt. These bits are readable and writable. [bit10] Reserved bit This bit is reserved. The read value is undefined and write has no effect. [bit9] SYNCR: Synchronous reset enable bit This bit is a synchronous reset enable bit. When an operation initialization reset (RST) request is generated, this bit selects an ordinary reset operation that immediately causes a RST, or a synchronous reset operation that causes RST after all bus access has stopped. Table 3.11-14 Synchronous Reset Enable Bit Value Function 0 Causes ordinary reset operation [Initial value] 1 Causes synchronous reset operation This bit is initialized to "0" at reset (INIT). This bit is readable and writable. As MB91461/F467R only supports the synchronous reset, set the bit to "1" when writing to this register. 112 CHAPTER 3 CPU AND CONTROL BLOCK Note: Be sure to meet the following two conditions before setting "0" to the SRST bit of STCR (standby control register) when the software reset is used on the synchronous mode. • Set the interrupt enable flag (I-Flag) to interrupt disabled (I-Flag = 0). • Not used NMI. [bit8] SYNCS: Synchronous standby enable bit This bit enables synchronous standby operation. When generating a standby request (sleep mode request or stop mode request), this bit selects either the ordinary standby operation in which a transition to the standby state is only caused by a write to the control bit of the STCR register, or the synchronous standby operation in which a transition to the standby state is caused by reading the STCR register after writing to the control bit of the STCR register. Table 3.11-15 Synchronous Standby Enable Bit Value Function 0 Performs ordinary standby operation [Initial value] 1 Performs synchronous standby operation This bit is initialized to "0" at reset (INIT). Note: Always set "1" to set synchronous standby operation when transition to the standby mode. 113 CHAPTER 3 CPU AND CONTROL BLOCK ■ CTBR: Time-base Counter Clear Register Figure 3.11-5 shows the structure of the time-base counter clear register. Figure 3.11-5 The Structure of the Time-base Counter Clear Register CTBR bit Address: 000483H Read/Write Initial value 7 6 5 4 3 2 1 0 D7 (W) X D6 (W) X D5 (W) X D4 (W) X D3 (W) X D2 (W) X D1 (W) X D0 (W) X This register initializes the time-base counter. When "A5H" and "5AH" are written consecutively to this register, all bits of the time-base counter are cleared to "0" immediately after a write to "5AH". There is no time restriction between the "A5H" write and "5AH" write. However, when data other than "5AH" is written after the "A5H" write, the time-base counter is not cleared even when "5AH" is written unless "A5H" is written again. The read value from this register is undefined. Note: When the time-base counter is cleared using this register, the oscillation stabilization wait interval, watchdog timer cycle, and time-base timer cycle change temporarily. 114 CHAPTER 3 CPU AND CONTROL BLOCK ■ CLKR: Clock Source Control Register Figure 3.11-6 shows the structure of the clock source control register. Figure 3.11-6 The Structure of the Clock Source Control Register CLKR bit 15 Address: 000484H Reserved Read/Write (R/W) Initial value (INIT) 0 Initial value (RST) X 14 13 12 Reserved Reserved Reserved (R/W) 0 X (R/W) 0 X (R/W) 0 X 11 10 9 8 SCKEN PLL1EN CLKS1 CLKS0 (R/W) 0 X (R/W) 0 X (R/W) 0 X (R/W) 0 X This register selects the clock source used as the base clock for the system and controls the PLL. This register selects one of two types of clock sources. [bit15 to bit12] Reserved bits These bits are reserved. Always set them to "0". [bit11] SCKEN: Sub clock selection enable bit This bit enables sub clock selection. Modifying the sub clock selection enable bit (SCKEN) while the sub clock is selected as the clock source (CLKS[1:0]=11B) is prohibited (the result is not guaranteed). Modify the setting only when the main clock is selected. (See the explanation for the clock source selection bits (CLKS[1:0]) for details of how to change the clock source.) This bit is not installed on MB91461. Bit 11 is a reserved bit on MB91461. Table 3.11-16 Sub Clock Selection Enable Bit Value Function 0 Disables sub clock selection [Initial value] 1 Enables sub clock selection [bit10] PLL1EN: PLL enable bit This bit enables PLL operation. Do not rewrite this bit when PLL is selected as the clock source. Also, do not select PLL as the clock source when this bit is set to "0" (due to the settings of bit9 and bit8: CLKS1 and CLKS0). If bit0:OSCD1 of the STCR is "1", PLLs stop even when this bit is set to "1" during the stop mode. The PLL operation is enabled after returning from the stop mode. Table 3.11-17 PLL Enable Bit Value Function 0 Stops PLLs [Initial value] 1 Enables PLL operation This bit is initialized to "0" at reset (INIT). This bit is readable and writable. 115 CHAPTER 3 CPU AND CONTROL BLOCK [bit9, bit8] CLKS1 and CLKS0: Clock source select bits These bits set the clock source to be used for the device. Two clock sources are available for selection and the values to be written to these bits are as shown in the table below. While CLKS1 (bit9) is "1", the value of CLKS0 (bit8) cannot be changed. Table 3.11-18 Changing Example of Clock Source Select Bits Unmodifiable Combination Modifiable Combination "00B" → "01B" or "10B" "00B" → "11B" "01B" → "11B" or "00B" "01B" → "10B" "10B" → "00B" "10B" → "01B" or "11B" "11B" → "01B" "11B" → "00B" or "10B" Table 3.11-19 Clock Source Select Bits CLKS1 CLKS0 Clock Source Setting 0 0 Original oscillation input from X0/X1, divided by 4 [Initial value] (MB91461) Original oscillation input from X0/X1, divided by 2 [Initial value] (MB91F467R) 0 1 Original oscillation input from X0/X1, divided by 4 (MB91461) Original oscillation input from X0/X1, divided by 4 (MB91F467R) 1 0 PLL (Main Clock) 1 1 Sub Clock (Setting disabled in MB91461) These bits are initialized to "00B" at reset (INIT). These bits are readable and writable. 116 CHAPTER 3 CPU AND CONTROL BLOCK ■ WPR:Watchdog Reset Generation Postponement Register Figure 3.11-7 shows the structure of the watchdog reset generation postponement register. Figure 3.11-7 The Structure of the Watchdog Reset Generation Postponement Register WPR bit Address: 000485H Read/Write Initial value 7 6 5 4 3 2 1 0 D7 (W) X D6 (W) X D5 (W) X D4 (W) X D3 (W) X D2 (W) X D1 (W) X D0 (W) X This register postpones generation of the watchdog reset. When "A5H" and "5AH" are written consecutively to this register, the detection FF of the watchdog timer is cleared immediately after the "5AH" write to postpone generation of the watchdog reset. There is no minimum time restriction between the "A5H" write and the "5AH" write. However, when data other than "5AH" is written after the "A5H" write, the detection FF of the watchdog timer is not cleared even when "5AH" is written unless "A5H" is written again. Table 3.11-20 shows a correlation between the watchdog reset generation interval and the RSRR register values. The watchdog reset is generated if writing of both data is not completed within the specified period. The duration until watchdog reset generation and the write interval required to postpone the generation depend on the state of WT1 (bit9) and WT0 (bit8) of the RSRR register. Table 3.11-20 Interval of Watchdog Reset Generation Minimum writing interval to WPR, required for control of RSRR watchdog reset generation Time between last "5AH" writing to WPR and watchdog reset generation WT1 WT0 0 0 φ × 216 [Initial value] φ × 216 to φ × 217 0 1 φ × 218 φ × 218 to φ × 219 1 0 φ × 220 φ × 220 to φ × 221 1 1 φ × 222 φ × 222 to φ × 223 "φ" represents the base clock cycle. WT1 (bit9) and WT0 (bit8) of the RSRR register are used to set the watchdog timer cycle. During a time when the CPU is not operating, such as stop, sleep, and DMA transfer, clearing is performed automatically. Therefore, when these conditions occur, the watchdog reset is postponed automatically. However, when a hold request for the external bus (BRQ) is accepted, the watchdog reset is not postponed. For this reason, to hold the external bus for a long period, switch to the sleep mode before inputting the BRQ. The read value of this register is undefined. 117 CHAPTER 3 CPU AND CONTROL BLOCK ■ DIVR0: Base Clock Division Setting Register 0 Figure 3.11-8 shows the structure of the base clock division setting register 0. Figure 3.11-8 The Structure of the Base Clock Division Setting Register 0 DIVR0 bit 15 Address: 000486H B3 Read/Write (R/W) Initial value (INIT) 0 Initial value (RST) X 14 13 12 11 10 9 8 B2 (R/W) 0 X B1 (R/W) 0 X B0 (R/W) 0 X P3 (R/W) 0 X P2 (R/W) 0 X P1 (R/W) 1 X P0 (R/W) 1 X This register controls the base clock division ratio of each internal clock. It sets the division ratio of the clock for the CPU and internal buses (CLKB), and the clock for peripheral circuits and peripheral buses (CLKP). Note: The upper operation frequency limit is defined for each clock. Note that operation is not guaranteed if the upper frequency limit is exceeded by a combination of the source clock selection, PLL multiply rate setting, and division ratio setting. Take care not to make any mistakes in the setting order of change of the source clock selection. When this register setting is modified, the new division ratio becomes valid from the next clock rate. 118 CHAPTER 3 CPU AND CONTROL BLOCK [bit15 to bit12] B3, B2, B1, B0: CLKB division select bits These bits set the division ratio for the CPU clock (CLKB), internal memory, and internal buses. In accordance with the combination of values written to these bits, one base clock division ratio (clock frequency) is selected from the 16 shown in the table below for the CPU and internal bus clocks. The operable upper frequency limit is 75 MHz. Do not set a division ratio causing a frequency that exceeds this limit. Table 3.11-21 CLKB Division Select Bits Clock division ratio Clock frequency: When the original oscillation is 18 MHz and the PLL multiply rate is 4 B3 B2 B1 B0 0 0 0 0 φ 72.0 MHz [Initial value] 0 0 0 1 φ × 2 (2 divisions) 36.0 MHz 0 0 1 0 φ × 3 (3 divisions) 24.0 MHz 0 0 1 1 φ × 4 (4 divisions) 18.0 MHz 0 1 0 0 φ × 5 (5 divisions) 14.4 MHz 0 1 0 1 φ × 6 (6 divisions) 12.0 MHz 0 1 1 0 φ × 7 (7 divisions) 10.3 MHz 0 1 1 1 φ × 8 (8 divisions) 9.0 MHz ··· ··· ··· ··· 1 1 1 1 ··· φ × 16 (16 divisions) ··· 4.5 MHz "φ" represents the base clock cycle. These bits are initialized to "0000B" at reset (INIT). These bits are readable and writable. 119 CHAPTER 3 CPU AND CONTROL BLOCK [bit11 to bit8] P3, P2, P1, P0: CLKP division select bits These bits set the division ratio for the peripheral clock (CLKP). They set the division ratio for the peripheral circuit and peripheral bus clocks (CLKP). In accordance with the combination of values written to these bits, one base clock division ratio (clock frequency) is selected from the 16 shown in the table below for the peripheral circuit and peripheral bus clocks. The operable upper frequency limit is 20 MHz. Do not set a division ratio causing a frequency that exceeds this limit. Table 3.11-22 CLKP Division Select Bits Clock division ratio P2 P1 P0 0 0 0 0 φ 72.0 MHz 0 0 0 1 φ × 2 (2 divisions) 36.0 MHz 0 0 1 0 φ × 3 (3 divisions) 24.0 MHz 0 0 1 1 φ × 4 (4 divisions) 18.0 MHz [Initial value] 0 1 0 0 φ × 5 (5 divisions) 14.4 MHz 0 1 0 1 φ × 6 (6 divisions) 12.0 MHz 0 1 1 0 φ × 7 (7 divisions) 10.3 MHz 0 1 1 1 φ × 8 (8 divisions) 9.0 MHz ··· ··· ··· ··· 1 1 1 1 ··· φ × 16 (16 divisions) "φ" represents the base clock cycle. These bits are initialized to "0011B" at reset (INIT). These bits are readable and writable. 120 Clock frequency: When the original oscillation is 18 MHz and the PLL multiply rate is 4 P3 ··· 4.5 MHz CHAPTER 3 CPU AND CONTROL BLOCK ■ DIVR1: Base Clock Division Setting Register 1 Figure 3.11-9 shows the structure of the base clock division setting register 1. Figure 3.11-9 The Structure of the Base Clock Division Setting Register 1 DIVR1 bit 7 Address: 000487H T3 Read/Write (R/W) Initial value (INIT) 0 Initial value (RST) X 6 5 4 3 2 1 0 T2 (R/W) 0 X T1 (R/W) 0 X T0 (R/W) 0 X Reserved Reserved Reserved Reserved (R/W) 0 X (R/W) 0 X (R/W) 0 X (R/W) 0 X This register controls the base clock division ratio of each internal clock. It sets the division ratio of the clock for the external extension bus interface (CLKT). Note: The upper operation frequency limit is defined for each clock. Note that operation is not guaranteed if the upper frequency limit is exceeded by a combination of the source clock selection, PLL multiply rate setting, and division ratio setting. Take care not to make any mistakes in the setting order of change of the source clock selection. When this register setting is modified, the new division ratio becomes valid from the next clock rate. 121 CHAPTER 3 CPU AND CONTROL BLOCK [bit7 to bit4] T3, T2, T1, T0: CLKT division select bits These bits set the division ratio for the external bus clock (CLKT). They set the division ratio for the clock of the external extension bus interface (CLKT). In accordance with the combination of values written to these bits, one base clock division ratio (clock frequency) is selected from the 16 shown in the table below for the clock of the external extension bus interface. The operable upper frequency limit is 40 MHz. Do not set a division ratio causing a frequency that exceeds this limit. Table 3.11-23 CLKT Division Select Bits Clock division ratio T2 T1 T0 0 0 0 0 φ 72.0 MHz [Initial value] 0 0 0 1 φ × 2 (2 divisions) 36.0 MHz 0 0 1 0 φ × 3 (3 divisions) 24.0 MHz 0 0 1 1 φ × 4 (4 divisions) 18.0 MHz 0 1 0 0 φ × 5 (5 divisions) 14.4 MHz 0 1 0 1 φ × 6 (6 divisions) 12.0 MHz 0 1 1 0 φ × 7 (7 divisions) 10.3 MHz 0 1 1 1 φ × 8 (8 divisions) 9.0 MHz ··· ··· ··· ··· 1 1 1 1 ··· φ × 16 (16 divisions) "φ" represents the base clock cycle. These bits are initialized to "0000B" at reset (INIT). These bits are readable and writable. [bit3 to bit0] Reserved bits These bits are reserved. 122 Clock frequency: When the original oscillation is 18 MHz and the PLL multiply rate is 4 T3 ··· 4.5 MHz CHAPTER 3 CPU AND CONTROL BLOCK ■ CSCFG: Clock Source Configuration Register This register controls the main clock oscillation in sub clock mode. This register is not installed on MB91461. Figure 3.11-10 Clock Source Configuration Register CSCFG bit 7 6 Address: 0004AEH EDSUEN PLLLOCK Read/Write (R/W) (R) Initial value (INIT) 0 X Initial value (RST) X X 5 4 3 2 1 0 RCSEL (R/W) 0 X Reserved CSC3 (R/W) 0 X CSC2 (R/W) 0 X CSC1 (R/W) 0 X CSC0 (R/W) 0 X (R/W) 0 X [bit7] EDSUEN: EDSU/MPU enable bit EDSUEN Function 0 EDSU/MPU is (clock) disabled [Initial value] 1 EDSU/MPU is (clock) enabled [bit6] PLLLOCK: PLL lock bit PLLLOCK Function 0 In the state where PLL is not locked 1 In the state where PLL is locked [bit5] RCSEL: CR oscillator selector bit RCSEL Function 0 CR oscillation is set to 100 kHz [Initial value] 1 CR oscillation is set to 2 MHz The selected oscillation frequency is applied to the clock control unit, flash security unit (change the oscillation to 2 MHz if CRC generation speed needs to be increased) and real-time clock. 100 kHz is always applied to the hardware watchdog (CR-base watchdog) regardless of this setting. [bit4] Reserved bit This bit is a reserved bit. 123 CHAPTER 3 CPU AND CONTROL BLOCK [bit3 to bit0] CSC3 to CSC0: Clock Source Select bits 124 CSC3 to CSC0 Function --00B Real-time clock source is main clock oscillation --01B Real-time clock source is subclock oscillation --10B Real-time clock source is CR oscillation --11B Setting disabled -0--B Subclock calibration source is subclock oscillation -1--B Subclock calibration source is CR oscillation CHAPTER 3 CPU AND CONTROL BLOCK 3.11.7 Peripheral Circuits in the Clock Control Block This section describes the peripheral circuit functions in the clock control block. ■ Time-base Counter The clock control block has a 26-bit time-base counter that operates using base clocks. The time-base counter is used to count the oscillation stabilization wait time (see "3.10.4 Oscillation Stabilization Wait Time") as well as for the following uses. Watchdog timer: The watchdog timer for detecting malfunction of the system uses bit output of the time-base counter for counting. Time-base timer: The time-base counter output is used to generate interval interrupts. ● Watchdog timer The watchdog timer detects the system malfunction by using a time-base counter output. When the watchdog reset generation delay is no longer caused during the set interval due to the program malfunction, the watchdog timer generates the setting initialization reset (INIT) request as a watchdog reset. The watchdog timer explained here is different from the hardware watchdog timer explained in Chapter 7. It enters a stop state immediately after reset. [Watchdog timer activation] The watchdog timer is started by a write to the 1st RSRR (reset factor register / watchdog timer control register) after a reset (RST). At this point, the watchdog timer interval time is set using bit9 and bit8 (WT1 and WT0). Only the interval time set by the first write is valid and all intervals set by succeeding writes are ignored. [Watchdog reset generation delay] After the watchdog timer is started, the program must write data to WPP (watchdog reset generation delay register) regularly in the order of "A5H", "5AH". This operation initializes the watchdog reset generation flag. [Watchdog reset generation] The watchdog reset generation flag is set by the falling edge of the time-base counter output at the set interval. When the flag is still set at detection of the second falling edge, the watchdog timer generates a setting initialization reset (INIT) request as a watchdog reset. 125 CHAPTER 3 CPU AND CONTROL BLOCK [Watchdog timer stop] After the watchdog timer is started, it cannot be stopped until the operation initialization reset (RST) is generated. In the following conditions, where RST is generated, the watchdog timer stops and does not function until it is restarted by the program: - Operation initialization reset (RST) state - Setting initialization reset (INIT) state - Oscillation stabilization wait reset (RST) state [Watchdog timer temporary stop (delay of automatic generation)] When the CPU program operation is stopped, the watchdog timer initializes the watchdog reset generation flag, delaying generation of the watchdog reset. Stop of the program operation means that the program is in one of the following states: - Sleep state - Stop state - Oscillation stabilization wait run state - Breaking the program by using the emulator debugger or the monitor debugger - Period from execution of INTE instruction to execution of RETI instruction - Step trace trap (Break per instruction with the T flag of the PS register being 1) - Instruction cache control registers (ISIZE and ICHCR) Data to cache memory in the RAM mode When the time-base counter is cleared, the watchdog reset generation flag is also initialized at the same time, delaying generation of a watchdog reset. If the state listed above is caused by system malfunction, a watchdog reset may not be generated. In this case, perform a reset (INIT) by using the external INITX pin. Time-base timer The time-base timer is an interval interrupt generation timer that uses the output of the time-base counter. The timer is suitable for counting a relatively long duration of up to {base clock × 226} cycles, such as PLL lock wait time. When the falling edge of output of the time-base counter for the set interval is detected, the time-base timer generates a time-base timer interrupt request. 126 CHAPTER 3 CPU AND CONTROL BLOCK [Time-base timer start and interval setting] The time-base timer sets an interval time by using bit13 to bit11 (TBC2, TBC1, TBC0) of TBCR (timebase counter control register). The falling edge of output of the time-base counter for the set interval is always detected. Therefore, after setting an interval time, clear bit15 (TBIF bit), and then set bit14 (TBIE bit) to "1" to enable the interrupt request output. When changing the interval time, set bit14 (TBIE bit) to "0" in advance to disable the interrupt request output. The time-base counter is always counting and is not affected by these settings. To obtain an accurate interval interrupt time, clear the time-base counter before enabling an interrupt. When not clearing, an interrupt request might occur immediately after an interrupt is enabled. [Clearing time-base counter by program] When data is written to CTBR, in the order of "A5H", "5AH", all bits of the time-base counter are cleared to 0 immediately after "5AH" is written. There are no restrictions on the time between "A5H" and "5AH". However, if data other than "5AH" is written after "A5H" is written, the counter is not cleared even when "5AH" is written unless "A5H" is written again. When the time-base counter is cleared, the watchdog reset generation flag is initialized at the same time, delaying generation of the watchdog reset. [Clearing the time-base counter at the device state] All bits of the time-base counter are simultaneously cleared to "0" in transition to the following device state: - Stop state - Setting initialization reset (INIT) state In the stop state, particularly, the time-base counter is used for counting the oscillation stabilization wait time, so the time-base timer interval interrupt may be generated unintentionally. Therefore, before setting the stop mode, disable the time-base timer interrupt, and do not use the timebase timer. In other states, the operation initialization reset (RST) is generated, so the time-base timer interrupts are automatically disabled. Interval timer This is a 23-bit timer that is not affected by clock source selection or division setting. The interval timer is synchronized with the source clock to count up. 127 CHAPTER 3 CPU AND CONTROL BLOCK 3.12 PLL Interface This section describes PLL multiply settings. Figure 3.12-1 shows the block diagram of PLL. Figure 3.12-1 Block Diagram of PLL Clock Unit XIN1 PLL Interface PLL Crystal or clock input PLLIN X 1/G 1/M CK Phase correction M U X FB 1/N Clock Tree CLKB CLKP CLKT M U X FB1 delay ■ Features The multiply rate is determined by two dividers that are enabled to set any value ranging from 1 to 64. Clock automatic gear up-down function preventing voltage drops and voltage surges 128 CHAPTER 3 CPU AND CONTROL BLOCK 3.12.1 Registers for the PLL Interface This section describes the registers for the PLL interface. ■ PLLDIVM: PLL Divider M Figure 3.12-2 shows the structure of the PLL divider M. Figure 3.12-2 The Structure of the PLL Divider M PLLDIVM bit Address: 00048CH 7 6 5 4 3 2 1 0 Reserved Reserved DVM5 DVM4 DVM3 DVM2 DVM1 DVM0 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) 0 0 0 0 0 0 0 Read/Write (R/W) Initial value 0 PLLDIVM is one of the dividers included in the PLL feedback loop. This divider determines the PLL multiply rate along with PLLDIVN. PLLDIVM also divides PLL oscillation output. It is used as divider that generates a clock affecting the following clock unit. [bit7, bit6] Reserved bits These bits are reserved. Their read value is "0". [bit5 to bit0] DVM5 to DVM0: PLLDIVM division setting value The division number varies as shown below, depending on the value set to DVM5 to DVM0. Table 3.12-1 PLLDIVM Division Setting Value DVM5 to DVM0 Division No. 000000B 1 (No division) 000001B 2 000010B 3 000011B 4 000100B 5 000101B 6 000110B 7 000111B 8 ······ ······ 111111B 64 129 CHAPTER 3 CPU AND CONTROL BLOCK Notes: • Although the division number can be set to "1" (no division), it is recommended to set it to "2" or greater. Please select an even number for the division number to ensure the duty ratio of PLL output is 50%. • When PLL is selected as the clock source (CLKS[1:0] = 10B), the PLLDIVM value cannot be changed. 130 CHAPTER 3 CPU AND CONTROL BLOCK ■ PLLDIVN: PLL Divider N Figure 3.12-3 shows the structure of the PLL divider N. Figure 3.12-3 The Structure of the PLL Divider N PLLDIVN bit Address: 00048DH 7 6 5 4 3 2 1 0 Reserved Reserved DVN5 DVN4 DVN3 DVN2 DVN1 DVN0 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) 0 0 0 0 0 0 0 Read/Write (R/W) Initial value 0 PLLDIVN is one of the dividers included in the PLL feedback loop. This divider determines the PLL multiply rate along with PLLDIVM. [bit7, bit6] Reserved bits These bits are reserved. Their read value is "0". [bit5 to bit0] DVN5 to DVN0: PLLDIVN division setting value The division number varies as shown below, depending on the value set to DVN5 to DVN0. Table 3.12-2 PLLDIVN Division Setting Value DVN5 to DVN0 Division No. 000000B 1 (No division) 000001B 2 000010B 3 000011B 4 000100B 5 000101B 6 000110B 7 000111B 8 ······ ······ 111111B 64 Note: When PLL is selected as the clock source (CLKS[1:0] = 10B), the PLLDIVN value cannot be changed. 131 CHAPTER 3 CPU AND CONTROL BLOCK ■ PLLDIVG PLLDIVG bit 7 Address: 00048EH Reserved Read/Write R/W Initial value (INITX pin input, 0 watchdog reset) Initial value 0 (Software reset) 6 5 4 3 2 1 0 Reserved Reserved Reserved R/W R/W R/W DVG3 R/W DVG2 R/W DVG1 R/W DVG0 R/W 0 0 0 0 0 0 0 0 0 0 X X X X [bit7 to bit4] Reserved bits Always write "0" to these bits. [bit3 to bit0] DVG3 to DVG0: Select divide-by-G for PLL automatic gear start/stop DVG3 to DVG0 Start/Stop frequency for dividing PLL output by G (Generationf: Base clock) 0000B Automatic gear disabled (Initial value) 0001B Source (FCL-PLL): 2 (divide by 2) 0010B Source (FCL-PLL): 3 (divide by 3) 0011B Source (FCL-PLL): 4 (divide by 4) 0100B Source (FCL-PLL): 5 (divide by 5) 0101B Source (FCL-PLL): 6 (divide by 6) 0110B Source (FCL-PLL): 7 (divide by 7) 0111B Source (FCL-PLL): 8 (divide by 8) ...... ..... 1111B Source (FCL-PLL): 16 (divide by 16) Notes: • Although an odd division ratio (3, 5, 7, etc.) can be selected for divide-by-G counter, such value is not a recommended value. Always select an even division ratio (2, 4, 6, etc.). • The register value cannot be changed (CLKS[1:0]=10B) if PLL is selected as a clock source. • Please set to 0000B (initial value) when not use the automatic gear function. 132 CHAPTER 3 CPU AND CONTROL BLOCK ■ PLLMULG PLLMULG bit Address: 00048FH Read/Write Initial value (INITX pin input, watchdog reset) Initial value (Software reset) 7 6 5 4 3 2 1 0 MLG7 R/W MLG6 R/W MLG5 R/W MLG4 R/W MLG3 R/W MLG2 R/W MLG1 R/W MLG0 R/W 0 0 0 0 0 0 0 0 X X X X X X X X [bit7 to bit0] MLG7 to MLG0: Select step multiplication factor for dividing PLL automatic gear by G MLG7 to MLG0 Step multiplication factor for dividing by G 00000000B Divide-by-G step x 1 (multiply by 1) 00000001B Divide-by-G step x 2 (multiply by 2) 00000010B Divide-by-G step x 3 (multiply by 3) 00000011B Divide-by-G step x 4 (multiply by 4) 00000100B Divide-by-G step x 5 (multiply by 5) 00000101B Divide-by-G step x 6 (multiply by 6) 00000110B Divide-by-G step x 7 (multiply by 7) 00000111B Divide-by-G step x 8 (multiply by 8) ...... ..... 11111111B Divide-by-G step x 256 (multiply by 256) Notes: • The register value cannot be changed (CLKS[1:0]=10B) if PLL is selected as a clock source. • When the automatic gear function is not used, this register is not used. 133 CHAPTER 3 CPU AND CONTROL BLOCK ■ PLLCTRL PLLCTRL bit 7 Address: 000490H Reserved Read/Write R/W Initial value (INITX pin input, 0 watchdog reset) Initial value 0 (Software reset) 6 5 4 3 2 1 0 Reserved Reserved Reserved R/W R/W R/W IEDN R/W GRDN R/W IEUP R/W GRUP R/W 0 0 0 0 0 0 0 0 0 0 X X X X [bit7 to bit4] Reserved bits The read value is always "0". [bit3] IEDN: Interrupt enable gear down bit IEDN Function 0 Disables gear down interrupt (Initial value) 1 Enables gear down interrupt [bit2] GRDN: Interrupt flag gear down bit GRDN Function 0 Gear down interrupt is inactive (Initial value) 1 Gear down interrupt is active • If the divide-by-G counter reaches to a programmed end value, this flag is set when a clock source is switched from PLL to clock source oscillation. • "1" is read from this bit when a read-modify-write (RMW) instruction is used. Writing "1" to this bit does not affect the operation. [bit1] IEUP: Interrupt enable gear up bit IEUP 134 Function 0 Disables gear up interrupt (Initial value) 1 Enables gear up interrupt CHAPTER 3 CPU AND CONTROL BLOCK [bit0] GRUP: Interrupt flag gear up bit GRUP Function 0 Gear up interrupt is inactive (Initial value) 1 Gear up interrupt is active • If the divide-by-G counter reaches to an end value defined in the divide-by-M counter, this flag is set when a clock source is switched from oscillation to clock source PLL. • "1" is read from this bit when a read-modify-write (RMW) instruction is used. Writing "1" to this bit does not affect the operation. 135 CHAPTER 3 CPU AND CONTROL BLOCK 3.12.2 Examples of PLL Multiply Rate Setting This section shows examples of PLL setting The table below shows setting examples for PLLDIVM and PLLDIVN. The output of the PLL oscillator should be set within a range from 80 MHz to 170 MHz. Table 3.12-3 Examples of PLL Multiply Rate Setting (1 / 2) PLL input clock [MHz] 136 PLLDIVM Setting PLLDIVN Setting Output of PLL Oscillator [MHz] PLL Output (Output to Clock Unit) [MHz] 4 20 2 160 8 4 14 3 168 12 4 10 4 160 16 4 8 5 160 20 4 8 6 192 24 4 6 7 168 28 4 6 8 192 32 4 6 9 192 36 4 4 10 160 40 4 4 11 176 44 4 4 12 192 48 4 2 19 152 76 4 2 20 160 80 10 2 8 160 80 10 3 5 150 50 10 3 6 180 60 10 4 4 160 40 10 4 5 200 50 10 5 3 150 30 10 5 4 200 40 10 6 3 180 30 10 8 2 160 20 10 9 2 180 20 10 10 2 200 20 12 3 5 180 60 12 4 4 192 48 12 5 3 180 36 12 7 2 168 24 12 8 2 192 24 14 3 4 168 56 14 4 3 168 42 14 6 2 168 28 CHAPTER 3 CPU AND CONTROL BLOCK Table 3.12-3 Examples of PLL Multiply Rate Setting (2 / 2) PLL input clock [MHz] PLLDIVM Setting PLLDIVN Setting Output of PLL Oscillator [MHz] PLL Output (Output to Clock Unit) [MHz] 14 7 2 196 28 16 2 5 160 80 16 3 4 192 64 16 4 3 192 48 16 5 2 160 32 16 6 2 192 32 18 3 3 162 54 18 5 2 180 36 20 2 4 160 80 20 3 3 180 60 20 4 2 160 40 20 5 2 200 40 137 CHAPTER 3 CPU AND CONTROL BLOCK ■ Clock Automatic Gear Up-Down In the PLL interface, a circuit that allows the clock to gear up and gear down smoothly is implemented to prevent voltage drops and surges when a clock source is switched from oscillation to high-frequency PLL output (or vice versa). The main function is implemented using two division counters (divide-by-M counter and divide-by-G counter). A target frequency is specified for PLL feedback in the divide-by-M counter. In another counter, the divide-by-G counter, a frequency is increased from a programmable division specified in the Divide-byG setting (DIVG) to a target frequency specified in the M division setting (DIVM) and then the frequency is decreased from the M division setting (DIVM) to a programmable end frequency (DIVG). If the system clock is modified from a low-frequency to a high-frequency (gear up) or from a highfrequency to a low-frequency (gear down), only the setting with DIVG > DIVM becomes valid clock gear specification. Frequency steps are executed at PLL output frequency multiplier as follows. Oscillator = 4 MHz, M = 2, and N = 20. (This means that if PLL output = 160 MHz and frequency output to C unit = 80 MHz, the frequency multiplier becomes M × N = 40.) The gear divider can be set to any even-numbered divider. In this example, G = 20 and a gear up is performed when the clock source is switched from oscillation to PLL. 1. Step: 1-cycle 8.0 MHz (8.0 MHz is a 20-cycle PLL output.) 2. Step: 2-cycle 8.4 MHz (8.4 MHz is a 19-cycle PLL output.) 3. Step: 3-cycle 8.8 MHz (8.8 MHz is an 18-cycle PLL output.) : 17. Step: 17-cycle 40.0 MHz (40.0 MHz is a 4-cycle PLL output.) 18. Step: 18-cycle 53.3 MHz (53.3 MHz is a 3-cycle PLL output.) 19. Step: 19-cycle 80.0 MHz (80.0 MHz is a 2-cycle PLL output.) → Target frequency reached by the transition to the last step (from 18. to 19. in this example) If a multiplication value is set in the gear multiplication factor register, each step is multiplied. The time from when a start frequency is generated to the time when a target frequency is reached can be calculated using the following formula. i ⎛ i ⎞ ⎜ duration = mul Þ t Þ ∑ k Þ ( i – k + 1 ) – ∑ k Þ ( i – k + 1 )⎟ ⎜ ⎟ ⎝k = 1 ⎠ k = j+1 This formula is the same as the one below (the finite arithmetic series of the first addition term result to the below). i ⎛ ⎞ i Þ ( i + 1 ) Þ ( i + 2 ) ⎜ duration = mul Þ t Þ ---------------------------------------------- – ∑ k Þ ( i – k + 1 )⎟ ⎜ ⎟ 6 ⎝ ⎠ k = j+1 i = G, j = G - M, mul = MULG, t = 1/f(pllout) 138 CHAPTER 3 CPU AND CONTROL BLOCK The above setting is equivalent to 1483 PLL output clock cycles. With this 1483 PLL output clock cycles, the time from the start frequency to the target frequency is 9262500 ps (about 9.3 s). Note: Before using the clock automatic gear function, it is recommended to use the gear up and gear down flags (PLLCTRL.GRUP and PLLCTRL.GRDN) to evaluate the current status of this function. This can prevent error operations that are caused by changing the setting before the completion from occurring in the clock system. Procedure example: 1. Set PLL interface registers (PLLDIVN, PLLDIVM, PLLDIVG, PLLMULG) according to the selected frequency and gear time. 2. Set PLL to ON (CLKR.PLL1EN=1). 3. Enable the corresponding interrupts (PLLCTRL.IEUP, PLLCTRL.IEDN) if an interrupt is received after a gear up or gear down switching. 4. Wait until PLL stabilization wait time. 5. Set base clock division registers (DIV0, DIV1). 6. Switch the clock source to PLL (CLKR.CLKS "00B" → "10B). 7. Wait for until PLLCTRL.GRUP gear up flag (polling or interrupt) before switching the clock source back to oscillation, or confirm the PLLCTRL.GRUP=1 setting before changing bits in the CLKR register. 8. Switch the clock source to oscillation (CLKR.CLKS "10B" → "00B"). 9. Wait for until PLLCTRL.GRDN gear down flag (polling or interrupt) before switching the clock source back to PLL, or confirm the PLLCTRL.GRDN=1 setting before changing bits in the CLKR register. 10. Set PLL to OFF (CLKR.PLL1EN=0). 139 CHAPTER 3 CPU AND CONTROL BLOCK 3.13 Device State Control This section describes the states and control of the MB91461/F467R. ■ Overview of the Device State Control The following device states are available in the MB91461/F467R. • Run state (normal operation) • Sleep state • Stop state • Shutdown state • Oscillation stabilization wait run state • Oscillation wait reset (RST) state • Operation initialization reset (RST) state • Setting initialization reset (INIT) state The above device states as well as the sleep and stop modes designed for low-power consumption mode are detailed below. 140 CHAPTER 3 CPU AND CONTROL BLOCK 3.13.1 Device States and Transitions Figure 3.13-1 shows the device states and transitions of the MB91461/F467R. ■ Device States Figure 3.13-1 Device States Priority levels of transition requests 1 INITX pin = 0 (INIT) 2 INITX pin = 1 (INIT released) 3 Oscillation stabilization wait completed 4 Reset (RST) released 5 Software reset (RST) 6 Sleep (interrupt written) 7 Stop (interrupt written) 8 Shutdown (interrupt written) 9 Interrupt 10 External interrupt requiring no clock 11 Watchdog reset (INIT) (Including hardware watchdog) Power-on Highest 1 Lowest Setting initialization reset (INT) Oscillation stabilization wait end Operation initialization reset (RST) Interrupt request Stop (shutdown) Sleep Setting initialization (INT) 2 1 Shutdown 10 1 Oscillation stabilization wait reset Stop 1 8 10 1 Oscillation stabilization wait run 3 Program reset (RST) 3 7 5 1 6 Sleep RUN 1 4 11 1 9 141 CHAPTER 3 CPU AND CONTROL BLOCK ■ Operation States of the Device The MB91461/F467R has the following operation states. ● Run state (normal operation) This is the state in which the program runs. In the run state, all the internal clocks are supplied and all the circuits are operable. However, the bus clock for the 16-bit peripheral bus is stopped when the peripheral bus is not accessed. Transition requests for each state are accepted. However, if the synchronous reset mode is selected, state transitions responding to some requests operate differently from the normal reset mode. For more details, see "3.10.5 Reset Operation Modes" - "■ Synchronous Reset Operation". ● Sleep state In this state, the program is stopped. Program operation causes state transition. In the sleep state, only CPU program execution is stopped and the peripheral circuits are operable. The internal memory and internal/external buses are stopped unless requested by the DMA controller. When a valid interrupt request is generated, this state is cleared and the device transits to the run state (normal operation). When a setting initialization reset (INIT) request is generated, the device transits to the setting initialization reset (INIT) state. When an operation initialization reset (RST) request is generated, the device transits to the operation initialization reset (RST) state. ● Stop state In this state, the device is stopped. Program operation causes state transition. In the stop state, all internal circuits are stopped. All the internal clocks are stopped and oscillation circuits and PLLs can be set to stop. The stop state can also set external pins (except some pins) to operate at high impedance. When a particular valid interrupt request (requiring no clock) is generated, or an interval timer interrupt request is generated during oscillation, the device transits to the oscillation stabilization wait run state. When a setting initialization reset (INIT) request is generated, the device transits to the setting initialization reset (INIT) state. When an operation initialization reset (RST) request is generated, the device transits to the oscillation stabilization wait reset (RST) state. ● Shutdown state In this state, the device is stopped in all components except RAM. Program operation causes state transition. Power supply is cut off in all components except RAM (MB91461: 64 Kbytes, MB91F467R: 32 Kbytes) and circuits surrounding it. This function allows a significant decrease in leakage currents in the shutdown state. All output except the output to hold the external bus control signal is at high impedance. When a particular valid interrupt request (requiring no clock) is generated, the device transits to the oscillation stabilization wait run state. When a setting initialization reset (INIT) request is generated, the device transits to the setting initialization reset (INIT) state. 142 CHAPTER 3 CPU AND CONTROL BLOCK ● Oscillation stabilization wait run state In this state, the device is stopped. The device transits to this state after returning from the stop state. All internal circuits except the circuits in the clock generation control block (time-base counter and device state control sections) are stopped. Although all the internal clocks are stopped, the oscillation circuit and PLLs that are enabled to operate are active. Control of the external pins at high impedance in the stop state is cleared. When the set oscillation stabilization wait time has elapsed, the device transits to the run state (normal operation). When a setting initialization reset (INIT) request is generated, the device transits to the setting initialization reset (INIT) state. When an operation initialization reset (RST) request is generated, the device transits to the operation initialization reset (RST) state. ● Oscillation stabilization wait reset (RST) state In this state, the device is stopped. The device transits to this state after returning from the stop state or setting initialization reset (INIT) state. All internal circuits except the circuits in the clock generation control block (time-base counter and device state control sections) are stopped. Although all the internal clocks are stopped, the oscillation circuit and PLLs that are enabled to operate are active. Control of the external pins at high impedance in the stop state is cleared. Operation initialization reset (RST) is output to the internal circuits. When the set oscillation stabilization wait time has elapsed, the device transits to the oscillation stabilization wait reset (RST) state. When a setting initialization reset (INIT) request is generated, the device transits to the setting initialization reset (INIT) state. ● Operation initialization reset (RST) state In this state, the program is initialized. When an operation initialization reset (RST) request is accepted, or the oscillation stabilization wait reset (RST) state is terminated, transition occurs. Program execution is stopped in the CPU and the program counter is initialized. Most peripheral circuits are also initialized. All internal clocks, oscillation circuit, and PLLs that are enabled to operate are active. Operation initialization reset (RST) is output to the internal circuits. When an operation initialization reset (RST) request is released, the device transits to the run state (normal operation state) and the operation initialization reset sequence is executed. If this occurs after returning from the setting initialization reset (INIT) state, the setting initialization reset sequence is executed. When a setting initialization reset (INIT) request is generated, the device transits to the setting initialization reset (INIT) state. 143 CHAPTER 3 CPU AND CONTROL BLOCK ● Setting initialization reset (INIT) state In this state, all settings are initialized. When a setting initialization reset (INIT) request is accepted, or the hardware standby state is terminated, transition occurs. In the CPU, program execution is stopped and the program counter is initialized. All peripheral circuits are initialized. While the oscillation circuit operates, PLLs stop operation. All the internal clocks operate except during "L" level input into the external INITX pin. Setting initialization reset (INIT) and operation initialization reset (RST) are output to the internal circuits. When the setting initialization reset (INIT) request is released, the device transits from this state to the oscillation stabilization wait reset (RST) state. After the RST state, the setting initialization reset sequence is executed. ● Priority of each state transition request In any state, every state transition request follows the priority order shown below. However, some requests are only generated in a particular state and only valid in that state. [Highest] ↓ Setting initialization reset (INIT) request Termination of oscillation stabilization wait time (Only the oscillation stabilization wait reset state and the oscillation stabilization wait run state occur.) ↓ Operation initialization reset (RST) request ↓ Valid interrupt request (Only the run state, sleep state, stop state, and shutdown state occur.) ↓ Stop mode request (shutdown) (Writing to register) (Only the run state occurs.) [Lowest] 144 Sleep mode request (Writing to register) (Only the run state occurs.) CHAPTER 3 CPU AND CONTROL BLOCK 3.14 Interval Timer The interval timer is a 23-bit counter synchronized with the source clock to count up. This timer incorporates a function to continuously generate interrupts at a regular interval. ■ Interval Duration of the Interval Timer Table 3.14-1 lists the interval duration of the interval timer. Table 3.14-1 Interval Duration of the Interval Timer Main clock cycle MB91461 1/FXTL MB91F467R 214/FXTL 212/FXTL 219/FXTL 217/FXTL 225/FXTL 223/FXTL Note: FXTL is the clock from the X0 and X1 pins or the oscillation circuit. ■ Block Diagram of the Interval Timer Figure 3.14-1 shows the block diagram of the interval timer. Figure 3.14-1 Block Diagram of the Interval Timer Counter for the interval timer FXTL 0 22 1 2 3 4 5 6 7 8 23 24 25 26 27 28 29 210 211 11 16 22 214 219 225 Source clock Interval timer selector Reset (INIT) Counter clear circuit Interval timer interrupt Interval timer control register (OSCR) WIF WIE WEN Reserved Reserved WS1 WS0 WCL FXTL: Clock from the X0 and X1 pins or the oscillation circuit A division circuit is available on MB91461. A division circuit is not available on MB91F467R. 145 CHAPTER 3 CPU AND CONTROL BLOCK ● Interval timer This is a 23-bit up-counter that uses the clock either from the X0 and X1 pins or the oscillation circuit that is divided by 4 as its count clock. ● Counter clear circuit This circuit clears the counter at reset (INIT) as well as OSCR register settings (WCL = 0). ● Interval timer selector Among three types of division output for the interval timer counter, this circuit selects one for the interval timer. The falling edge of the selected division output becomes an interrupt factor. ● Interval register (OSCR) This register selects the interval duration, clears the counter, controls interrupts, and confirms their state. 146 CHAPTER 3 CPU AND CONTROL BLOCK ■ Registers in the Interval Timer Figure 3.14-2 shows the structure of registers in the interval timer. Figure 3.14-2 The Structure of Registers in the Interval Timer OSCR bit 15 Address: 0004C8H WIF Read/Write (R/W) Initial value (INIT) 0 Initial value (RST) X 14 13 12 11 10 9 8 WIE (R/W) 0 X WEN (R/W) 0 X Reserved Reserved (R/W) − X (R/W) − X WS1 (R/W) 0 X WS0 (R/W) 0 X WCL (R/W) 1 X [bit15] WIF: Timer interrupt flag This is an interval interrupt request flag. This flag is set to "1" by the falling edge of division output of the selected interval timer. When this bit and the interrupt request enable bit are both set to "1", an interval timer interrupt request is generated. Table 3.14-2 Timer Interrupt Flag Value Function 0 Generates no interval timer interrupt request. [Initial value] 1 Generates an interval timer interrupt request. This bit is initialized to "0" at reset (INIT). This bit is readable and writable. However, only "0" can be written. Writing "1" does not change the bit value. The read value of read-modify-write (RMW) instructions is always "1". [bit14] WIE: Timer interrupt enable bit This bit enables and disables output of interrupt request to the CPU. When this bit and the interval timer interrupt request flag bit are set to "1", an interval timer interrupt request is generated. Table 3.14-3 Timer Interrupt Enable Bit Value Function 0 Disables output of an interval timer interrupt request. [Initial value] 1 Enables output of an interval timer interrupt request. This bit is initialized to "1" at reset (INIT). It is readable and writable. 147 CHAPTER 3 CPU AND CONTROL BLOCK [bit13] WEN: Timer operation enable bit This bit enables the timer operation. When this bit is set to "1", the timer counts. Table 3.14-4 Timer Operation Enable Bit Value Function 0 Stops the timer operation. [Initial value] 1 Operates the timer. This bit is initialized to "0" at reset (INIT). It is readable and writable. [bit12, bit11] Reserved bits These bits are reserved. "0" should be written. (Writing "1" is prohibited.) The read value is undefined. [bit10, bit9] WS1 and WS0: Timer interval select bits These bits select the interval timer cycle. The cycle is selected from the following three combinations of output bits of the interval timer counter. Table 3.14-5 Timer Interval Select Bits Interval timer cycle WS1 WS0 MB91461 MB91F467R 0 0 Setting disabled [Initial value] Setting disabled [Initial value] 0 1 214/FXTL 212/FXTL 1 0 219/FXTL 217/FXTL 1 1 225/FXTL 223/FXTL FXTL is the clock from the X0 and X1 pins or the oscillation circuit. These bits are initialized to "00B" at reset (INIT). They are readable and writable. When using the interval timer, write data to this register. [bit8] WCL: Timer clear bit Writing "0" clears the interval timer to "0". Only "0" can be written. Writing "1" has no effect. The read value is always "1". 148 CHAPTER 3 CPU AND CONTROL BLOCK ■ Interval Interrupt The interval timer counter counts by using the clock (source clock) either from the X0 pin and X1 pin or the oscillation circuit that is divided by 2. When the set interval has elapsed, the interval interrupt request flag (WIF) is set to "1". At this point, if the interrupt request enable bit is enabled (WIE = 1), an interrupt request is generated to the CPU. However, when the oscillation circuit is stopped (see section "■ Operation of the interval timer function"), counting is also stopped. Consequently, no interval interrupt is generated. Write "0" to the WIF flag in an interrupt routine to clear the interrupt request. Note that when the specified division output falls, the WIF bit is set regardless of the value of the WIE bit. Notes: • When enabling output of an interrupt request after reset is canceled, or when modifying the WS1 bit (bit0), always clear the WIF and WCL bits at the same time (WIF = WCL = 0). This timer cannot be used to automatically retain the stabilization wait time of the oscillation circuit. • When the WIF bit is set to "1", changing the WIE bit from the disabled state to the enabled state (0 → 1) immediately generates an interrupt request. • When the counter is cleared (OSCR: WCL = 1) at the same time as the selected bit overflows, the WIF bit is not set. ■ Operation of the Interval Timer Function The interval timer counter uses the source clock to count up. In the following state, however, counting is stopped as oscillation from the oscillation circuit is stopped. When the WEN bit is set to "0": When the oscillation circuit is set to stop in the stop mode (the OSCD1 (bit0) of the standby control register (STCR) is set to "1"), and the device enters that mode, counting is stopped during the stop mode. In MB91461/F467R, the OSCD1 bit is initialized to "1" at reset (INIT). Therefore, to operate the interval timer in the stop mode, set the OSCD2 bit to "0" before the device enters the standby state. Clearing the counter (WCL = 0) allows the counter to count from ""000000H". When the counter has reached "7FFFFFH", it goes back to "000000H" to continue to count. The interval interrupt request bit (WIF) is set to "1" by the falling edge of division output of the interval timer that was selected during the counting-up operation. In other words, interval timer interrupt requests are generated at each selected interval, based on the cleared time. 149 CHAPTER 3 CPU AND CONTROL BLOCK ■ Interval Timer Operation Figure 3.14-3 shows the counter state during interval timer operation. Figure 3.14-3 Counter State During Interval Timer Operation 7FFFFFH Counter value TIME Set time · Timer clearing (WCL = 1) * when not "0" · Interval setting (WS1, WS0 = 11B) Clearing in interrupt routine WIF (Interrupt request) WIE (Interrupt mask) ■ Precautions for Use of the Interval Timer The set time is reference only, because the oscillation cycle is unstable immediately after oscillation starts. While the oscillation circuit is stopped, the counter is also stopped. Consequently, no interval timer interrupts are generated. Therefore, when executing processing using an interval timer interrupt, the oscillation circuit should not be stopped. When a WIF flag set request is generated at the same time as "0" clearing is requested by the CPU, the flag set request has priority and the "0" clearing request becomes invalid. 150 CHAPTER 4 LOW-POWER CONSUMPTION MODE This chapter describes functions and operations of the low-power consumption modes. 4.1 Overview of Low-Power Consumption Mode 4.2 Sleep Mode 4.3 Stop Mode 4.4 Shut-down Mode 151 CHAPTER 4 LOW-POWER CONSUMPTION MODE 4.1 Overview of Low-Power Consumption Mode This section explains three low-power consumption modes supported with MB91461/ F467R. ■ Low-Power Consumption Mode ● Sleep mode (Program is stopped) Clock provision for the CPU core is stopped. Operation of the peripheral functions is continued. Writing to the register causes the device to transition to the sleep state. ● Stop mode (Device is stopped) Clock provision for the CPU core and the peripheral function is stopped. The selection of stopping or continuing the main oscillation can be made. ● Shut-down mode (Power is shut) Power supply for entire device except RAM and some control logics is shut internally. Both the oscillation and the clock provision are stopped. 152 CHAPTER 4 LOW-POWER CONSUMPTION MODE 4.2 Sleep Mode CPU keeps stopping with sleep mode in the mode that stops only the clock supplied to CPU core, and the function in the surrounding operating. ■ Overview of Sleep Mode The sleep mode is the state in which the program is stopped. A transition is made to this state depending on the register setting of a software. In the sleep state, only the CPU program execution is stopped and the peripheral circuits can operate. Various internal memories and the internal/external buses are stopped unless requested by the DMA controller. When an enabled interrupt request is generated, the sleep state is cancelled, causing a transition to the RUN state (normal operation). ● Transition to Sleep Mode When "1" is written to bit6 (SLEEP bit) of STCR (standby control register), the sleep mode is established, causing a transition to the sleep state. The sleep state continues until a factor causing a return from the sleep state occurs. When "1" is written to both bit6 and bit7 (STOP bit) of STCR, bit7 is prior to bit6, causing a transition to the stopped state. When establishing the sleep mode, set the synchronous standby mode (set by bit8 (SYNCS bit) of TBCR (time base counter control register)) and always use the following sequence: (LDI #value_of_sleep,R0) ; value_of_sleep is write data to STCR (LDI #_STCR,R12) ; _STCR is STCR address (481H) STB R0,@R12 ; Writing to standby control register (STCR) LDUB @R12,R0 ; Reading STCR for synchronous standby LDUB @R12,R0 ; Once more dummy reading of STCR NOP ; Five NOPs for coordinate the timing NOP NOP NOP NOP [Circuits stopped in sleep state] • CPU program execution • Bit search module (operates when DMA transfer performed) • Various built-in memories (These memories operate when DMA transfer is performed.) • Internal/external buses (These buses operate when DMA transfer is performed.) [Circuits not stopped in sleep state] • Oscillator circuit • Enabled PLL • Clock generation control unit 153 CHAPTER 4 LOW-POWER CONSUMPTION MODE • Interrupt controller • Peripheral circuits • DMA controller • DSU • Interval timer [Factors causing return from sleep state] • Occurrence of enabled interrupt requests When an interrupt request with an interrupt level other than interrupt disable ("1FH") occurs, the sleep mode is cancelled, performing a transition to the RUN state (normal state). In order not to cancel the sleep mode even if an interrupt request occurs, set interrupt disable ("1FH") to the appropriate ICR as an interrupt level. • Occurrence of setting initialization reset (INIT) request When a setting initialization reset (INIT) request occurs, a transition is always made to the INIT state. • Occurrence of operation initialization reset (RST) request When an operation initialization reset (RST) request occurs, a transition is unconditionally made to the RST state. See Section "3.13.1 Device States and Transitions" for the priority of each factor. [Synchronous-standby operation] When bit8 (SYNCS bit) of TBCR (time-base counter control register) is "1", the synchronous-standby operation is enabled. In this case, just writing to the SLEEP bit does not cause a transition to the sleep state. A transition is made to the sleep state by reading the STCR register after this writing. 154 CHAPTER 4 LOW-POWER CONSUMPTION MODE 4.3 Stop Mode The stop mode is a mode that stops the clock supplied to CPU core part and the function in the surrounding. When "1" is written to bit7 (STOP bit) of STCR (standby control register), the stop mode is established, causing a transition to the stopped state. The stopped state continues until a factor causing a return from the stopped state occurs. When "1" is written to both bit6 (SLEEP bit) and bit7 of STCR, bit7 is prior to bit6, causing a transition to the stopped state. [Circuits stopped in stopped state] Oscillator circuit set to be stopped: When bit0 (OSCD1 bit) of STCR (standby control register) is "1", the oscillator circuit for the main clock in the stopped state is placed in the stopped state. In this case, also the interval timer is stopped. PLL with disabled operation or connected to oscillator circuit set to be stopped: When bit0 (OSCD1 bit) of STCR (standby control register) is "1", the PLL for the main clock in the stopped state is placed in the stopped state even if bit10 (PLL1EN bit) of CLKR (clock source control register) is "1". All other internal circuits except the circuits not stopped in stopped state [Circuits not stopped in stopped state] Oscillator circuit not set to be stopped: When bit0 (OSCD1 bit) of STCR (standby control register) is "0", the oscillator circuit for the stopped main clock is not stopped. In this case, also the interval timer is not stopped. PLL with enabled operation and connected to oscillator circuit not set to be stopped: When bit0 (OSCD1 bit) of STCR (standby control register) is "0", the PLL for the main clock in the stopped state is not stopped when bit10 (PLL1EN bit) of CLKR (clock source control register) is "1". [Pin high-impedance control in stopped state] When bit5 (HIZ bit) of STCR (standby control register) is "1", the pin output in the stopped state is placed in the high-impedance state. When bit5 (HIZ bit) of STCR (standby control register) is "0", the pin output in the stopped state holds the value before the transition to the stopped state. For details, see "3.11.6 Registers in the Clock Generation Control Block". [Input to peripheral resource in stopped state] In the stopped state, an input to each peripheral resource is "0". Regarding the external interrupt (INTn) pin and the CAN receiving (RXn) pin, when appropriate PFR is "0", an input of each resource is "0." On the other hand, when the PFR is "1", signal from the pin is transmitted to the resource. 155 CHAPTER 4 LOW-POWER CONSUMPTION MODE [Factors causing return from stopped state] Occurrence of particular effective interrupt requests requiring no clock: Only the following is enabled: external interrupt input pin (INTn pin) and interval timer interrupt during main oscillation. When an interrupt request with an interrupt level other than interrupt disable ("1FH") occurs, the stop mode is cancelled, performing a transition to the RUN state (normal state). In order not to cancel the stop mode even if an interrupt request occurs, set interrupt disable ("1FH") to the appropriate ICR as an interrupt level. Do not set edge detection on an interrupt request level (ELVR register). Occurrence of interval timer interrupt: With bit0 (OSCD1 bit) of STCR (standby control register) set to "0", when an interrupt request of the interval timer occurs, the stop mode is cancelled, performing a transition to the RUN state (normal state). In order not to cancel the stop mode even if an interrupt request occurs, stop the interval timer, or set interrupt disable to the interrupt enabling bit of the interval timer. Occurrence of setting initialization reset (INIT) request: When a setting initialization reset (INIT) request occurs, a transition is unconditionally made to the INIT state. Occurrence of operation initialization reset (RST) request: When an operation initialization reset (RST) request occurs, a transition is unconditionally made to the RST state. [Clock source selection when stop mode enabled] Before setting the stop mode, set the clock source selection so that PLL output is not selected. The restrictions on the frequency division rate setting are the same as in the normal operation. 156 CHAPTER 4 LOW-POWER CONSUMPTION MODE 4.4 Shut-down Mode The Leake current at the standby can be greatly decreased with the shutdown mode in the mode that stops the power supplies other than RAM and a part of control logic. All register settings except RAM* and the returning factor flag of shut-down state are not held. The necessary information need to be stored in RAM before performing a transition to the shut-down mode. In the shut-down mode, all output is placed in the high-impedance state except keeping output of the external bus control signal. Returning from the shut-down mode is performed when a previously specified external interrupt signal is asserted or INITX (external reset pin) is asserted. Returning from the shut-down mode cannot be performed by NMI input. *: 64 Kbytes RAM (F-bus RAM) for instruction/data use for MB91461 (30000H to 3FFFFH), and 32 Kbytes RAM (D-bus RAM) dedicated for data use for MB91F467R (24000H to 2BFFFH). ● SHDE: Shut-down control register Figure 4.4-1 The Structure of Shut-down Control Register Address: 0004D4H bit Read/Write Initial value 7 6 5 4 3 2 1 0 SDENB R/W (0) − (−) (X) − (−) (X) − (−) (X) − (−) (X) − (−) (X) − (−) (X) − (−) (X) (X) (X) (X) (X) (X) (INITX pin, restart from shut-down mode) Initial value (Held) (X) (X) (Software reset, watchdog reset) This register is used to enable the shut-down mode. SDENB (bit7): Shut-down enable "1": Shut-down mode enabled. "2": Shut-down mode disabled. 157 CHAPTER 4 LOW-POWER CONSUMPTION MODE ● EXTE: External interrupt enable register Figure 4.4-2 The Structure of External Interrupt Enable Register Address: 0004D6H bit Read/Write Initial value 7 6 5 4 3 2 1 0 RX1 (R/W) (0) RX0 (R/W) (0) INT7 (R/W) (0) INT6 (R/W) (0) INT3 (R/W) (0) INT2 (R/W) (0) INT1 (R/W) (0) INT0 (R/W) (0) (Held) (Held) (Held) (Held) (Held) (INITX pin, restart from shut-down mode) Initial value (Held) (Held) (Held) (Software reset, watchdog reset) This register is used to select a factor causing return from the shut-down mode. To set this register to the enabled factor causing return, set the bit of this register corresponding to interrupt or CAN receive signal (RX) to "1". Each bit is cleared when returning from the shut-down mode (restart). Therefore this register need to be set every time before performing a transition to the shut-down mode. ● EXTF: External interrupt factor flag Figure 4.4-3 The Structure of External Interrupt Factor Flag Address: 0004D7H bit Read/Write Initial value 7 6 5 4 3 2 1 0 RX1 (R/W) (0) RX0 (R/W) (0) INT7 (R/W) (0) INT6 (R/W) (0) INT3 (R/W) (0) INT2 (R/W) (0) INT1 (R/W) (0) INT0 (R/W) (0) (Held) (Held) (Held) (Held) (Held) (Held) (Held) (Held) (INITX pin) Initial value (Software reset, restart from shut-down, watchdog reset) This register is a factor causing return from the shut-down mode. When there is an input of enable factor causing return, the corresponding flag is set to "1". This register can be written "0". To clear these flags, set to "0" by the CPU instruction or reset through INITX pin. When the first factor is received after transition to the shut-down mode, the information is held in flag and the reset sequence to return starts immediately (approximately 100 µs later). Therefore even if there are several factors causing return, the subsequent factors are not received and the flag is not held. 158 CHAPTER 4 LOW-POWER CONSUMPTION MODE ● EXTLV1: External interrupt level register Figure 4.4-4 The Structure of External Interrupt Level Register Address: 0004D8H bit Read/Write Initial value 7 6 5 4 3 2 1 0 LB7 (R/W) (0) LA7 (R/W) (0) LB6 (R/W) (0) LA6 (R/W) (0) LB5 (R/W) (0) LA5 (R/W) (0) LB4 (R/W) (0) LA4 (R/W) (0) (Held) (Held) (Held) (Held) (Held) (INITX pin, restart from shut-down mode) Initial value (Held) (Held) (Held) (Software reset, watchdog reset) ● EXTLV2: External interrupt level register Figure 4.4-5 The Structure of External Interrupt Level Register Address: 0004D9H bit Read/Write Initial value 7 6 5 4 3 2 1 0 LB3 (R/W) (0) LA3 (R/W) (0) LB2 (R/W) (0) LA2 (R/W) (0) LB1 (R/W) (0) LA1 (R/W) (0) LB0 (R/W) (0) LA0 (R/W) (0) (Held) (Held) (Held) (Held) (Held) (INITX pin, restart from shut-down mode) Initial value (Held) (Held) (Held) (Software reset, watchdog reset) This register is used to specify the interrupt level of the factor causing return from the shut-down mode. Table 4.4-1 External Interrupt Level Register LBx LAx Interrupt Level 0 0 "L" Level (Initial value) 0 1 "H" Level 1 0 Setting disabled 1 1 Setting disabled Note: For an interrupt level from the shut-down mode, only L level or H level can be set. 159 CHAPTER 4 LOW-POWER CONSUMPTION MODE ● Transition to Shut-down Mode The following procedures are required for transition to the shut-down mode. 1) On MB91F467R, if it shifts from the state where external bus is being used in the internal ROM mode to the shut-down mode, set values, in the order of (1) to (3), in the following port control registers corresponding to CS0X, CS1X, CS2X, CS3X, CS4X, BGRNTX, WR0X, WR1X, RDX, ASX, WEX, BAAX, IORDX and IOWRX to prevent external bus control pins from outputting unnecessary pulses. (1) Set port data registers (PDR08/PDR09/PDR10/PDR11) to "1". (2) Set data direction registers (DDR08/DDR09/DDR10/DDR11) to "0". (3) Set port function registers (PFR08/PFR09/PFR10/PFR11) to "0". 2) Set an interrupt signal level to be used for returning from the shut-down mode in EXTLV1 and EXTLV2 (external interrupt level registers). 3) Set SHDE bit in the SHDE (shut-down control register) to "1" to enable shut-down mode. 4) Set an external interrupt channel to be used for returning in EXTE (external interrupt enable register). If the SDENB bit is not set to "1" in advance, the return channel cannot be set to "1". 5) Execute the same instructions as those for transition to the stop mode. By executing 1) to 3) beforehand, it will shift to the shut-down mode after executing the next instruction sequence. (LDI #value_of_stop, R0) ; value_of_sleep is write data to STCR (LDI #_STCR, R12) ; _STCR is STCR address (481H) STB R0, @R12 ; Writing to standby control register (STCR) LDUB @R12, R0 ; Reading STCR for synchronous standby LDUB @R12, R0 ; Once more dummy reading of STCR NOP ; Five NOPs for coordinate the timing NOP NOP NOP NOP During the shut-down mode, though the external bus control signal keeps the last value before the transition to the shut-down mode, all other output is placed in Hi-Z. Input of the pin for return from the shut-down mode keeps input threshold and pull-up/pull-down setting until a factor causing return is received. During the shut-down mode, oscillation is stopped and also power supply to the internal logics is stopped except RAM* to and the shut-down control logic. * 160 64 Kbytes RAM (F-bus RAM) for instruction/data use for MB91461, and 32 Kbytes RAM (D-bus RAM) dedicated for data use for MB91F467R. CHAPTER 4 LOW-POWER CONSUMPTION MODE [Pin state during shut-down mode] Table 4.4-2 Pin State During Shut-down Mode Pin name Pin state WDRESETX ASX CS0X, CS1X, CS2X, CS3X, CS4X IORDX IOWRX RDX WR0X, WR1X BGRNTX Keeps the last state before the transition to the shut-down mode. INT0, INT1, INT2, INT3, INT6, INT7, RX0/INT8, RX1/INT9 Keeps the input threshold setting and the pull-up/pulldown setting during the shut-down mode. Returns to the initial value when performing a transition to reset after the first factor causing return. SYSCLK Is placed in Hi-Z state. Other pins Are placed in Hi-Z state. The pull-up/pull-down setting returns to the initial value. ● Return from Shut-down Mode When an enable level is input to the external interrupt pin set by the external interrupt enable register, reset is performed and the device restarts after starting power supply to the internal logics and waiting stabilization of oscillation. In this case, the factor causing return from the shut-down mode is held in the external interrupt factor flag register (EXTF). A software can determine whether the initial start-up process or the return process from the shut-down mode by detecting the flag register value in the initial setting routine. During the return process, a factor of the subsequent interrupt input after the first factor causing return is not held. [Return by interrupt pin] Regarding the factor causing return from the shut-down mode, when the first factor is received, the information is held in the flag and the reset sequence begins. Even if there are several factors causing return, the subsequent factors are not received and the flag is not held. When a factor causing return from the shut-down mode is received, all pins return to the reset state. Therefore the input threshold setting and the pull-up/pull-down setting of the pins for returning return to the initial state. When a factor causing return is received, the device restarts through the following process. 1) Reactivating power supply from the internal regulator. 2) Waiting for stabilization of the oscillation. 3) Reset cancellation, mode vector fetch, and reset vector fetch. During the shut-down mode, the input threshold setting of the pin for returning keeps the last value before the transition to the shut-down mode. 161 CHAPTER 4 LOW-POWER CONSUMPTION MODE When a return is performed by an interrupt, the interrupt request level setting register (ELVR) cannot be used for edge detection. [Return by INITX pin] When the "L" level is input to INITX pin, the reset is performed. In this case, all interrupt factor flags are cleared. Unlike the return by the interrupt pin, there is no time for waiting for stabilization of the oscillation. Always keep INITX input more than 8 ms to make time for stabilization of the oscillation. Note: NMI cannot be used for return from the shut-down mode. RTC operation stops during the shut-down mode. 162 CHAPTER 5 CLOCK MODULATOR This chapter provides an overview of the Clock Modulator and its features. (This feature is not provided on MB91461.) 5.1 Overview of Clock Modulator 5.2 Clock Modulator Registers 5.3 Application Note 163 CHAPTER 5 CLOCK MODULATOR 5.1 Overview of Clock Modulator This section explains clock modulator provided on MB91F467R. ■ Clock Modulator The clock modulator is intended for the reduction of electromagnetic interference - EMI, by spreading the spectrum of the clock signal over a wide range of frequencies. The module is fed with an unmodulated reference clock with frequency F0, provided by the PLL circuit. This reference clock is frequency modulated, controlled by a random signal. The mean frequency of the modulated clock is equal to the reference clock frequency F0. Figure 5.1-1 Frequency Spectrum of the Modulated Clock (Fundamentals Only) Modulation range Frequency Fmin F0 Fmax ■ Modulation Degree and Frequency Resolution in Frequency Modulation Mode Maximum and minimum frequencies (Fmax and Fmin) of the modulated clock are defined by the modulation degree parameter. Furthermore the resolution of the modulation range is selectable in 7 steps from low (1) to high (7). Higher resolution implies a finer granularity of discrete frequencies in the spectrum of the modulated clock but less possible modulation degrees. In general the highest possible frequency resolution combined with the highest possible modulation degree results in the highest EMI reduction. But for some cases lower modulation degrees may result in a better EMI behavior. Please refer to the table of possible settings in Table 5.2-4 . 164 CHAPTER 5 CLOCK MODULATOR 5.2 Clock Modulator Registers This section lists the clock modulator registers and describes the function of each register in detail. ■ Clock Modulator Registers Figure 5.2-1 Clock Modulator Registers Address: 7 6 5 4 3 2 1 0 0004B9H CMPRL (Lower) Initial value 11111101B R/W R/W R/W R/W R/W R/W R/W R/W 0004B8H 15 14 - - - - 7 0004BBH 6 13 12 11 10 9 8 R/W R/W R/W R/W R/W R/W 5 4 3 2 1 0 - Reserv Reserv Reserv ed ed ed FMOD RUN - FMOD PDX - R/W R/W R/W R - R/W R/W CMPRH (Upper) Initial value XX000010B CMCR Initial value X0010X00B 165 CHAPTER 5 CLOCK MODULATOR ■ Clock Modulator Control Register (CMCR) The Control Register (CMCR) has the following functions: • Set the modulator to power down mode • Modulator enable/disable in frequency modulation mode • Indicates the status of the modulator Figure 5.2-2 Configuration of the Clock Modulator Control Register (CMCR) bit 7 0004BBH 6 5 4 3 2 1 0 - Reser Reser Reser FMOD ved ved ved RUN - FMOD PDX - R/W R/W R/W R - R/W R/W CMCR Initial value X0010X00B bit0 PDX Power down bit 0 Power down mode 1 Power up bit1 FMOD Frequency modulation enable bit 0 Frequency modulation mode disabled. 1 Frequency modulation mode enabled. bit3 FMOD RUN Modulator status in frequency modulation mode 0 Clock frequency unmodulated. 1 Clock frequency modulated. bit4 to bit6 Reserved R/W R X - : : : : Readabel/writable Read only Undefined value Undefined : Initial value bit4 Always write "1" to this bit. bit5, bit6 Always write "0" to this bit. The bits FMODRUN, FMOD, PDX control or indicate the status of the frequency modulation mode. Frequency modulation mode needs some additional configuration (CMPR register). 166 CHAPTER 5 CLOCK MODULATOR ■ Clock Modulator Control Register Contents Table 5.2-1 Function of Each Bit of the Clock Modulator Control Register (1 / 2) Bit name Functions bit7 Undefined This bit is undefined bit. The initial value is undefined. bit6, bit5 Reserved Always write "0" to this bit. bit4 Reserved Always write "1" to this bit. bit3 FMOD RUN: Modulator status in frequency modulation mode bit "0": MCU is running with unmodulated clock "1": MCU is running with frequency modulated clock • FMODRUN indicates the status of the modulator output clock in frequency modulation mode (FMOD=1). If the output clock is frequency modulated, MODRUN is set to "1", otherwise MODRUN is set to "0". • After enabling the frequency modulation mode by setting FMOD to "1", the modulator is calibrated. During this time, the clock is unmodulated. Therefore it takes several us before the output clock switches to modulated clock and the FMODRUN bit is set to "1". The calibration time depends on the frequency of the oscillator. At oscillator (Fc) = 4MHz : Calibration time = 64.00us (calibration time = 256/Fc). During normal operation, after calibration is finished, the clock is not switched to unmodulated clock anymore. • Due to the synchronization of the FMOD signal and the synchronized switching to unmodulated clock, it takes less than 9 × T0 (input clock period) before FMODRUN changes to "0" and the clock switches to unmodulated clock after the modulator is disabled. • The FMODRUN bit is read only. Writing to FMODRUN has no effect. • Before changing the parameter register CMPR, the modulator must be disabled → FMOD=0 and FMODRUN=0. bit2 Undefined This bit is undefined bit. The initial value is undefined. 167 CHAPTER 5 CLOCK MODULATOR Table 5.2-1 Function of Each Bit of the Clock Modulator Control Register (2 / 2) Bit name Functions bit1 FMOD: Frequency modulation enable bit "0": Frequency modulation disabled. "1": Frequency modulation enabled. • To enable the modulator in frequency modulation mode, FMOD must be set to "1". • Before the modulator can be enabled, the PLL must deliver a stable reference clock (PLL lock time must be elapsed). • The specified PLL frequency range for frequency modulation mode is 15 MHz to 25 MHz. • Each PLL output frequency offers a set of possible modulation parameters. The selected setting (CMPR register) and the PLL frequency must match. Please refer to the CMPR register description. • Whenever the PLL output frequency is changed or the PLL is switched off e.g. in power down modes, the modulator must be disabled before → FMOD=0 and FMODRUN=0. • Before the modulator can be enabled, it must be switched from power down to active mode by setting PDX to "1". And the startup time of 6µs must be awaited. Please refer to the application note for a description of the recommended startup sequence. • Before the modulator can be enabled in frequency modulation mode, a proper setting must be selected via the parameter register CMPR. • After enabling the frequency modulation mode by setting FMOD to "1", the modulator is calibrated. During this time, the clock is unmodulated. Therefore the output clock does not switch immediately to modulated clock. The status of the clock (frequency modulated / unmodulated) is indicated by the FMODRUN status bit. Please refer to the FMODRUN bit description. • Due to the synchronization of the FMOD signal and the synchronized switching to unmodulated clock, it takes less than 9 × T0 (input clock period) before the clock switches to unmodulated clock after the modulator is disabled. The modulator can be disabled at any time. Before changing the parameter register CMPR, the modulator must be disabled → FMOD=0 and FMODRUN=0. bit0 PDX: Power down bit "0": Power down mode "1": Power up • PDX is the power down signal for the modulator. Before the frequency modulation mode can be enabled, this bit must be set to "1" and the startup time of 6µs must be awaited. Please refer to the application note for a description of the recommended startup sequence. • Before switching to power down mode (PDX=0), the modulator must be disabled → FMOD=0 and FMODRUN=0. 168 CHAPTER 5 CLOCK MODULATOR In the Table below the modulator states are summarized: Table 5.2-2 Modulator States FMOD PDX FMODRUN (read only) Modulator disabled 0 0 0 Modulator power on, waiting modulator startup time (> 6 µs) 0 1 0 Modulator enabled in frequency modulation mode, modulator is calibrating, modulation not active 1 1 0 Modulator is running in frequency modulation mode modulation is active 1 1 1 Setting disabled Settings other than the above-mentioned Modulator State 169 CHAPTER 5 CLOCK MODULATOR ■ Clock Modulation Parameter Register (CMPR) The Modulation Parameter Register (CMPR) determines the modulation degree in frequency modulation mode. Figure 5.2-3 Modulation Parameter Register Address: bit 7 6 5 4 3 2 1 0 0004B9H CMPRL (Lower) Initial value 11111101B R/W R/W R/W R/W R/W R/W R/W R/W bit 15 14 13 12 11 10 9 8 0004B8H R/W R/W R/W R/W R/W R/W R/W X CMPRH (Upper) Initial value XX000010B : Readable/writable : Undefined value : Undefined The modulation parameter determines the degree of modulation and the maximal and minimal occurring frequencies in the modulated clock. Please refer to the application note for a description of an approach to select the optimal setting. Each set of possible modulation parameters refers to a particular PLL frequency. The PLL frequency and the selected parameter must match. Please refer to the following table of possible settings. The modulation parameter affects only the frequency modulation mode. Note: The modulation parameter must be changed only when the modulator is disabled and the RUN flag is "0" (FMOD=0, FMODRUN=0). 170 CHAPTER 5 CLOCK MODULATOR ■ Modulation Parameter Register Contents Table 5.2-3 Function of Each Bit of the Modulation Parameter Register (CMPR) Bit name Functions bit15, bit14 Undefined This bit is undefined bit. The initial value is undefined. bit13 to bit0 MP13 to MP0: Modulation Parameter bits Depending on the PLL frequency the following modulation parameter settings are possible. The corresponding CMPR register value is stated in Table 5.2-4 . F0: Frequency of unmodulated input clock (PLL frequency) T0: Period of unmodulated input clock (PLL clock period) Resolution: Resolution of frequencies in the modulated clock. low (1) to high (7) Fmin: Minimal frequency occurring in the frequency modulated clock Fmax: Maximal frequency occurring in the frequency modulated clock Phase skew: The maximal phase shift of the modulated clock relative to the unmodulated reference clock in terms of clock periods of the unmodulated clock. Example: phase skew=1.44 In worst case, a sequence of n periods of the modulated clock can be 1.44 x T0 shorter or 1.44 x T0 longer than a sequence of n periods of the unmodulated reference clock. n can be any number > 50 periods Phase skew 50: phase skew for sequences with n<= 50 periods CMPR: register setting of the CMPR register n periods Reference clock + Phase skew n periods Modulated clock n periods Note: Fmax must be designed not to exceed 90MHz. 171 CHAPTER 5 CLOCK MODULATOR The table below shows the recommended setting for several MCU clocks and modulation parameters: Table 5.2-4 Modulation Parameter Settings (1 / 3) Fmax (MHz) +/- phase skew 50 [periods] +/- phase skew min/max [periods] CMPR F0 (MHz) resolution mod degree 16 1 1 15.00 17.14 0.27 0.72 027FH 16 1 2 14.58 17.73 0.53 1.44 047EH 16 1 3 14.17 18.37 0.8 2.16 067DH 16 1 4 13.79 19.05 1.06 2.88 087CH 16 1 5 13.43 19.79 1.33 3.59 0A7BH 16 1 6 13.09 20.58 1.59 4.31 0C7AH 16 1 7 12.76 21.45 1.86 5.03 0E79H 16 1 8 12.45 22.38 2.13 5.75 1078H 16 1 9 12.15 23.41 2.39 6.47 1277H 16 1 10 11.87 24.53 2.66 7.19 1476H 16 1 11 11.60 25.76 2.92 7.91 1675H 16 1 12 11.35 27.13 3.19 8.63 1874H 16 1 13 11.10 28.65 3.45 9.34 1A73H 16 1 14 10.86 30.34 3.72 10.06 1C72H 16 1 15 10.64 32.25 3.98 10.78 1E71H 16 2 1 14.58 17.73 0.39 1.02 02BEH 16 2 2 13.79 19.05 0.78 2.03 04BCH 16 2 3 13.09 20.58 1.17 3.05 06BAH 16 2 4 12.45 22.38 1.56 4.06 08B8H 16 2 5 11.87 24.53 1.95 5.08 0AB6H 16 2 6 11.35 27.13 2.34 6.09 0CB4H 16 2 7 10.86 30.34 2.73 7.11 0EB2H 16 3 1 14.17 18.37 0.78 1.86 02FDH 16 3 2 13.09 20.58 1.56 3.72 04FAH 16 3 3 12.15 23.41 2.34 5.58 06F7H 16 3 4 11.35 27.13 3.13 7.44 08F4H 16 3 5 10.64 32.25 3.91 9.3 0AF1H 16 4 1 13.79 19.05 0.75 2 033CH 172 Fmin (MHz) CHAPTER 5 CLOCK MODULATOR Table 5.2-4 Modulation Parameter Settings (2 / 3) Fmax (MHz) +/- phase skew 50 [periods] +/- phase skew min/max [periods] CMPR F0 (MHz) resolution mod degree 16 4 2 12.45 22.38 1.5 4 0538H 16 4 3 11.35 27.13 2.25 6 0734H 16 5 1 13.43 19.79 1.13 3.94 037BH 16 5 2 11.87 24.53 2.25 7.88 0576H 16 5 3 10.64 32.25 3.38 11.81 0771H 16 6 1 13.09 20.58 1.5 2.67 03BAH 16 6 2 11.35 27.13 3 5.34 05B4H 16 7 1 12.76 21.45 1.81 3.95 03F9H 16 7 2 10.86 30.34 3.63 7.91 05F2H 20 1 1 18.60 21.63 0.27 0.72 027FH 20 1 2 18.08 22.38 0.53 1.44 047EH 20 1 3 17.58 23.20 0.8 2.16 067DH 20 1 4 17.11 24.07 1.06 2.88 087CH 20 1 5 16.66 25.01 1.33 3.59 0A7BH 20 1 6 16.24 26.02 1.59 4.31 0C7AH 20 1 7 15.84 27.13 1.86 5.03 0E79H 20 1 8 15.46 28.33 2.13 5.75 1078H 20 1 9 15.09 29.64 2.39 6.47 1277H 20 1 10 14.74 31.08 2.66 7.19 1476H 20 1 11 14.41 32.67 2.92 7.91 1675H 20 2 1 18.08 22.38 0.39 1.02 02BEH 20 2 2 17.11 24.07 0.78 2.03 04BCH 20 2 3 16.24 26.02 1.17 3.05 06BAH 20 2 4 15.46 28.33 1.56 4.06 08B8H 20 2 5 14.74 31.08 1.95 5.08 0AB6H 20 3 1 17.58 23.20 0.78 1.86 02FDH 20 3 2 16.24 26.02 1.56 3.72 04FAH 20 3 3 15.09 29.64 2.34 5.58 06F7H 20 4 1 17.11 24.07 0.75 2 033CH Fmin (MHz) 173 CHAPTER 5 CLOCK MODULATOR Table 5.2-4 Modulation Parameter Settings (3 / 3) Fmax (MHz) +/- phase skew 50 [periods] +/- phase skew min/max [periods] CMPR F0 (MHz) resolution mod degree 20 4 2 15.46 28.33 1.5 4 0538H 20 4 3 14.09 34.42 2.25 6 0734H 20 5 1 16.66 25.01 1.13 3.94 037BH 20 5 2 14.74 31.08 2.25 7.88 0576H 20 6 1 16.24 26.02 1.5 2.67 03BAH 20 7 1 15.84 27.13 1.81 3.95 2BF5H 24 1 1 22.14 26.20 0.27 0.72 027FH 24 1 2 21.52 27.13 0.53 1.44 047EH 24 1 3 20.93 28.12 0.8 2.16 067DH 24 1 4 20.38 29.19 1.06 2.88 087CH 24 1 5 19.85 30.34 1.33 3.59 0A7BH 24 1 6 19.35 31.59 1.59 4.31 0C7AH 24 1 7 18.87 32.95 1.86 5.03 0E79H 24 2 1 21.52 27.13 0.39 1.02 02BEH 24 2 2 20.38 29.19 0.78 2.03 04BCH 24 2 3 19.35 31.59 1.17 3.05 06BAH 24 3 1 20.93 28.12 0.78 1.86 02FDH 24 3 2 19.35 31.59 1.56 3.72 04FAH 24 3 3 17.99 36.04 2.34 5.58 06F7H 24 4 1 20.38 29.19 0.75 2 033CH 24 5 1 19.85 30.34 1.13 3.94 037BH 24 6 1 19.35 31.59 1.5 2.67 03BAH 24 7 1 18.87 32.95 1.81 3.95 03F9H 174 Fmin (MHz) CHAPTER 5 CLOCK MODULATOR 5.3 Application Note This section explains Startup/stop sequence for frequency modulation mode and modulation parameter. ■ Recommended Startup/Stop Sequence for Frequency Modulation Mode Start order 1. Switch modulator from power down to power up mode PDX=1 2. Switch on PLL 3. Wait PLL lock time. At the same time the modulator starts up. 4. Set CMPR register to a proper setting 5. Enable frequency modulation mode FMOD=1 After the calibration is finished, the clock switches from unmodulated to modulated clock and the FMODRUN flag changes to "1". Stop order 1. Disable modulator FMOD=0 2. Wait until FMODRUN changes to 0 3. Switch to power down mode PDX=0 4. Disable PLL, switch to power down mode, etc. Note: Do not enable the modulator before the PLL lock time has elapsed. Do not disable the PLL while the modulator is running. 175 CHAPTER 5 CLOCK MODULATOR ■ Modulation Parameter for Frequency Modulation Mode It is not possible to recommend a modulation parameter setting to achieve a particular reduction in EMI. The best setting depends much on the actual application, the whole system and the requirements. In order to find the optimal modulation parameter setting in frequency modulation mode, the following approach is recommended. 1. Define the required PLL frequency based on performance needs e.g. 16 MHz 2. Determine the maximal allowed clock frequency of the MCU e.g. 32 MHz 3. Choose the setting with the highest resolution and the highest modulation degree, whose maximal frequency is below the maximal allowed clock frequency of the MCU. e.g. resolution:7, degree:2, CMPR=05F2 H(Fmax= 30.34 MHz) 4. Perform EMI measurements 5. If the EMI measurements does not fulfill the requirements, you may either 6. Reduce the modulation degree at the same frequency resolution (this may improve the reduction in the upper frequency band > 100 MHz, but decrease the reduction of the fundamental < 100 MHz) e.g. resolution:7, degree:1, CMPR=03F9H or Increase the modulation degree at a lower frequency resolution (this may improve the reduction of the fundamental < 100 MHz, but worsen the reduction in the upper frequency band > 100 MHz) or e.g. resolution:5, degree:3, CMPR=0771H Repeat item Operation of 3)-to-5) with the new setting and continue until the best settings is identified ■ Recommended Settings The following table lists some example conditions for PLL clock and maximal allowed MCU clock frequency and the recommended clock modulator setting: Table 5.3-1 Some Example Conditions for PLL Clock 176 F0 PLL clock frequency Maximal allowed MCU clock frequency (refer to the data sheet) 16MHz clock modulator setting Resolution Modulation degree Fmax CMPR 20MHz 5 1 19.79MHz 037BH 16MHz 25MHz 7 1 21.45MHz 03F9H 16MHz 32MHz 7 2 30.34MHz 05F2H 20MHz 25MHz 4 1 24.07MHz 033CH 20MHz 32MHz 7 1 27.13MHz 2BF5H 24MHz 32MHz 6 1 31.59MHz 03BAH CHAPTER 6 SUB OSCILLATION STABILIZATION WAIT TIMER This chapter describes the sub oscillation stabilization wait timer. (This feature is not provided on MB91461.) 6.1 Overview of Sub Oscillation Stabilization Wait Timer 6.2 Configuration of Sub Oscillation Stabilization Wait Timer 6.3 Registers of Sub Oscillation Stabilization Wait Timer 6.4 Operation of Sub Oscillation Stabilization Wait Timer 6.5 Application Note 6.6 Caution when Using Sub Oscillation Stabilization Wait Timer 177 CHAPTER 6 SUB OSCILLATION STABILIZATION WAIT TIMER 6.1 Overview of Sub Oscillation Stabilization Wait Timer This section explains function and feature of sub oscillation stabilization wait timer. ■ Sub Oscillation Stabilization Wait Timer Function The sub oscillation stabilization timer is a 15-bit counter that is counted up with the subclock. This timer does not affect the selection/dividing setting of the MCU operating clock. This timer is used to acquire sub clock oscillation stability wait time if the sub clock oscillation is resumed mainly when the sub clock oscillation is stopped while the main clock is in operation. This function is not provided on MB91461. ■ Features • Type: 15-bit free-run counter • Channel number: 1 channel • Clock source: Sub clock (source oscillation) --- Period = 1/FCL-SUB = 1/32.768kHz • Interval time: 4 types • Period = 210/FCL-SUB, 213/FCL-SUB, 214/FCL-SUB, 215/FCL-SUB, (31.25ms, 0.25s, 0.50s, 1.00s) • Timer clear cause: (Software, overflow, reset (INIT)) • Interrupt: clock interrupt (interval interrupt) • Count value: Cannot read and write (Clear only) 178 CHAPTER 6 SUB OSCILLATION STABILIZATION WAIT TIMER 6.2 Configuration of Sub Oscillation Stabilization Wait Timer The block diagram of sub oscillation stabilization wait timer is shown in Figure 6.2-1 . Figure 6.2-1 Block Diagram of Sub Oscillation Stabilization Wait Timer Interval time WS1 WS0 0 0 0 1 1 0 1 1 WPCR: bit2-1 210 / 213 / 214 / 215 / FCL-SUB FCL-SUB FCL-SUB FCL-SUB WIE Clock timer (14bit free-run timer) Subclock (Oscillation) 32.768 kHz 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 21 22 23 24 25 26 27 29 210 211 212 213 214 215 28 Edge detection Selector 0 1 WPCR: bit6 Interrupt disabled Interrupt enabled 0 WIF WPCR: bit7 0 1 With interrupt request Without interrupt request Clock timer 1 interrupt (#49) WRITE; 0: Flag clear Timer clear WCL WPCR: bit2 0 1 Timer clear No effect on operation 179 CHAPTER 6 SUB OSCILLATION STABILIZATION WAIT TIMER 6.3 Registers of Sub Oscillation Stabilization Wait Timer This section explains the registers used to set the sub oscillation stabilization wait timer. ■ Register List of Sub Oscillation Stabilization Wait Timer Figure 6.3-1 Register List of Sub Oscillation Stabilization Wait Timer WPCRH Address: bit 0004CAH 180 7 6 5 4 3 2 1 0 Initial value WIF WIE WEN Reserved Reserved WS1 WS0 WCL 000XX001B R/W R/W R/W R/W R/W R/W R/W R/W CHAPTER 6 SUB OSCILLATION STABILIZATION WAIT TIMER 6.3.1 WPCRH: Sub Oscillation Stabilization Timer Control Register This register is used to perform interval time selection, timer clear, interrupt control, controls of timer stop and others, and status checks. ■ WPCRH bit 7 6 5 4 3 2 1 0 Initial value WIF R/W WIE R/W WEN R/W Reserved Reserved R/W WS0 R/W WCL R/W 000XX001B R/W WS1 R/W [bit7] WIF : Sub oscillation stabilization timer interrupt request flag WIF Read Operation Write Operation 0 Without interrupt request Clears the interrupt request flag 1 With interrupt request Writing does not affect operation The sub oscillation stabilization timer interrupt request flag bit is set to "1" at the falling edge of the selected interval period output. [bit6] WIE : Interrupt request enable WIE Operation 0 Interrupt request is prohibited 1 Interrupt request enable • If the interrupt request enable bit is set to "1" an interrupt request is enabled. • If the sub oscillation stabilization timer interrupt request flag is (WIF=1), and if the interrupt request enable bit (WIE) is set to "1", an interrupt request is immediately generated. [bit5] WEN : Timer operation enable WEN Operation 0 Stops timer operation 1 Enables timer operation [bit4, bit3] Reserved bit Be sure to write "0". The read value is "0". 181 CHAPTER 6 SUB OSCILLATION STABILIZATION WAIT TIMER [bit2, bit1] WS1, WS0 : Interval period selection WS1 WS0 Interval period (FCL-SUB= 32.768kHz) 0 0 210/FCL-SUB (31.25ms) 0 1 213/FCL-SUB (0.25s) 1 0 214/FCL-SUB (0.50s) 1 1 215/FCL-SUB (1.00s) [bit0] WCL : Timer clear WCL Operation 0 Clears the sub oscillation stabilization timer. 1 Writing does not affect write operation. The timer is also cleared by INITX pin input and watchdog reset. Notes: • Initial value can be set using the setting initialization reset (INITX pin input, watchdog reset), but the operation initialization reset (Software reset) holds the current value instead of initializing it. • If you set the interrupt request enable (WIE= 1), and the interval period selection (WS1,WS0) after canceling the reset, be sure to simultaneously set the timer interrupt request flag (WIF) and the timer clear (WCL) "0". 182 CHAPTER 6 SUB OSCILLATION STABILIZATION WAIT TIMER 6.4 Operation of Sub Oscillation Stabilization Wait Timer This section explains the operation of the sub oscillation stabilization wait timer. ■ Sub Clock Oscillation Stability Wait Interrupt Figure 6.4-1 Timing Chart of Sub Clock Oscillation Stability Wait Interrupt (7) (5) Subclock oscillation example Clock timer count (8) 0400H (6) 0000H Time (1) 210 (bit9) (8) Subclock stop bit WCL (4) (2) WIF (3) WIE (3) (9) (11) (11) Operatin clock mode Subclock Main clock (10) (1) Selects the interval (WS1,WS0) (In this example, 210/FCL-SUB is selected.) (2) Sets the timer so that it is cleared (WCL=0) by software. (3) Sets the flag clear (WIF=0) and the interrupt request enable (WIE=1) by software. (4) Sets the subclock stop release (OSCCR.OSCDS1=0) of the subclock operation by software. (5) The subclock oscillation starts. (6) Counts up with the subclock (source oscillation). (7) Make the subclock oscillation stable. (8) Makes the interval time be the selected time. (Detects the falling of 210 dividing.) (9) If the flag (WIF) becomes "1", the subclock oscillation stability wait interrupt request is generated. (10) Processing cause by an interrupt (Software): Switching the operation clock (Sub-RUN => main RUN) (11) Interrupt request disable (WIE=0) and the interrupt request clear (WIF=0). 183 CHAPTER 6 SUB OSCILLATION STABILIZATION WAIT TIMER ■ Interval Interrupt (Clock Interrupt) Figure 6.4-2 Timing Chart of Interval Interrupt (Clock Interrupt) Clock timer count (4) 4000H (4) 2000H (3) (3) 0000H (2) Time (1) 213 (bit12) WCL (4) (4) (2) WIF (2) WIE (2) (5) (6) (5) (6) (1) Selects the interval time. (WS1,WS0) (In this example, 213/FCL-SUB is selected.) (2) Sets the timer clear (WCL=0), flag clear (WIF=0) and interrupt request enable (WIE=1) by the software. (3) The timer counts up with the subclock (Source oscillation). (4) Makes the interval time be the selected time. (Detects the fall of 213.) (5) If the flag (WIF) is set to "1", interval interrupt request (Clock interrupt request) is generated. (6) Processing caused by an interrupt (Software): The interrupt request clear (WIF=0) (Arbitrary processing such as clock counting) (7) Repeats Items (3) to (6). 184 CHAPTER 6 SUB OSCILLATION STABILIZATION WAIT TIMER ■ Returning from the Stop Mode due to Interval Operation (Clock Interrupt) Figure 6.4-3 Timing Chart of Returning from the Stop Mode due to Interval Operation (Clock Interrupt) Clock timer count 7FFFH 4000H (2) 0000H (3) 214 (bit13) (7) Interval WCL (1) (10) WIF (8) (4) WIE (5) MCU status Main RUN Sub RUN (6) Stop (9) Sub RUN Stop Sub RUN Stop Sub RUN Stop Sub RUN Stop Sub RUN Oscillation stabilization wait time (1) The sub oscillation stabilization timer is cleared by software. (Writes "0" to WCL.) (2) Counts up the sub oscillation stabilization timer with the sub clock. (3) Selects the interval time. (In this example, 0.5 second: Selects (WS1,WS0)=10B.) (4) Sets the flag clear (WIF=0) and sub oscillation stabilization timer interrupt enable (WIE=1) by the software. (5) Switches the MCU operation from the main RUN to sub-RUN. (6) Switches to the stop mode. (7) Makes the interval time be the selected time. (0.5 second) (8) The interrupt request flag (WIF) is set to "1". (9) As the interrupt request is enabled (WIE=1), returns from the stop mode to sub-RUN. (10) Clears the interrupt request flag by software. (Writes "0" to the WIF.) (11) Repeats Items (6) from (10). 185 CHAPTER 6 SUB OSCILLATION STABILIZATION WAIT TIMER 6.5 Application Note This section explains the operation method when the application is used like the method of setting sub oscillation stabilization wait timer etc. ● Setting of Sub Oscillation Stabilization Wait Timer Table 6.5-1 Settings Required for Using the Sub Oscillation Stabilization Timer Setting Setting register Setting the interval time Sub oscillation stabilization timer control register (WPCRH) Count clear Table 6.5-2 Items Required for Enabling Subclock Oscillation Stabilization Timer Interrupt Setting Setting register Setting the interrupt vector and the free-run timer level of the sub oscillation stabilization timer Refer to "CHAPTER 11 INTERRUPT CONTROLLER". Setting the sub oscillation stabilization timer interrupt Clearing the interrupt request Enabling the interrupt request Sub oscillation stabilization timer control register (WPCRH) ● The types of interval time (wait time) and selection method There are four types of interval time, and they are set with the interval selection bit (WPCRH:WS1,WS0). Interval selection bit 186 Interval time setting Interval (Wait time) Example FCL-SUB = 32.768kHz WS1 WS0 0 0 210/FCL-SUB 31.25 ms 0 1 213/FCL-SUB 0.25 s 1 0 214/FCL-SUB 0.50 s 1 1 215/FCL-SUB 1.00 s CHAPTER 6 SUB OSCILLATION STABILIZATION WAIT TIMER ● Method of clearing Sub Oscillation Stabilization Wait Timer The Methods of clearing the sub oscillation stabilization time are following. • Sets the clear bit (WPCRH.WCL). Operation Clear bit (WCL) To clear the sub oscillation stabilization timer Writes "1" • Performs a reset. Clears the 15-bit free-run timer with the initialization reset (INITX pin input, watchdog reset). Note: The operation initialization reset (Software reset) holds the count of a 15-bit free-run timer. • The overflow of the sub oscillation stabilization timer (Next count-up for "FFFFH") causes the count value to be reset to "0000H". ● Interrupt-associated registers The relationship between the interrupt level and the vector is shown in the following table. Refer to "CHAPTER 11 INTERRUPT CONTROLLER" for more information on the interrupt level and the interrupt vector. Interrupt vector (Default) #143 Address: 0FFDC0H Interrupt level setting bit (ICR[4:0]) Interrupt level register (ICR63) Address: 047FH As the interrupt request flag (WPCRH.WIF) is not automatically cleared, clear it before returning from the interrupt processing by the software. (Writes "0" to the WIF bit.) ● Method of interrupt enabled The interrupt enable is set with the interrupt request enable bit (WPCRH.WIE). Interrupt request enable bit (WIE) Interrupt disable Set the value to "0" Interrupt enable Set the value to "1" The interrupt request is cleared with the interrupt request bit (WPCRH.WIF). Interrupt request bit (WIF) Interrupt request clear Writes "0" 187 CHAPTER 6 SUB OSCILLATION STABILIZATION WAIT TIMER ● Method of stop sub oscillation stabilization wait timer count Sets with the timer operation enable bit (WPCRH.WEN). Refer to "6.3 Registers of Sub Oscillation Stabilization Wait Timer". In addition, if the MCU stops the sub clock while the mainclock is being operated, the sub clock oscillation stability wait timer also stops counting. 188 CHAPTER 6 SUB OSCILLATION STABILIZATION WAIT TIMER 6.6 Caution when Using Sub Oscillation Stabilization Wait Timer Please note the following respect when using sub oscillation stabilization wait timer. [Caution of timer interrupt request flag (WIF=1)] • If the setting request (WIF=1) of the timer interrupt request flag and the writing timing where "0" is written to the flag by the software occur simultaneously, the flag is set to "1". • If the interrupt request is enabled (WIE=1) after defeating a reset, and if the interval time is changed, be sure to simultaneously set "0" to the interrupt request enable flag (WIF) and the clear bit (WCL). • The interrupt request flag (WIF) is always read as "1" with the read-modify-write (RMW) instruction. [Caution of initialization reset] • The setting initialization reset (INITX pin input, watchdog reset) initializes the values of the timer interrupt request bit (WIF), timer interrupt request enable bit (WIE), timer enable bit (WEN) and timer clear bit (WCL) to "0", but cannot initialize the interval period selection bit (WS1,WS0). Be sure to set it by the software. • Setting the initial value of the sub oscillation stabilization timer control register is possible using the initialization reset (INITX pin input, watchdog reset), but the operation initialization reset (Software reset) holds the current value instead of initializing the value of the sub oscillation stabilization timer control register. [Caution of immediately after the oscillation has started] • The value for the oscillation stability wait time is an estimated value because the oscillation period of the main clock oscillation and sub clock is unstable for the beginning immediately after the oscillation has started. [Caution of the others] • An unstable clock may be supplied to the entire device, and normal operation is not guaranteed if the sub clock is made to oscillate starting from sub clock stopped state, and if the MCU operation mode is switched from the main RUN to the sub-RUN mode without waiting until the sub clock oscillation becomes stable. Be sure to acquire the sub clock oscillation stability wait time using the sub oscillation stabilization timer, etc. (If the main clock is selected as the clock source, the oscillation stability wait time for the sub clock may not be acquired.) • As the sub oscillation stabilization timer stops while the sub clock stops oscillating, a clock interrupt (interval interrupt) is not generated either. If processing using the clock interrupt (interval interrupt) is performed, enable the sub clock oscillation. (Do not stop the sub clock oscillation). 189 CHAPTER 6 SUB OSCILLATION STABILIZATION WAIT TIMER • The sub oscillation stabilization timer counts up with the sub clock. As a result, the timer stops counting because the sub clock stops oscillating under the following conditions. - If the sub clock is set that it stops in the stop mode (Sub clock oscillation enable bit =1), and then the mode is switched to the stop mode, the sub oscillation stabilization timer stops counting while in the stop mode. - If you want the sub oscillation stabilization timer to continue counting while in stop mode, set the sub clock oscillation enable bit to "0" before switching the mode to the stop mode. - If the sub clock stop bit =1 while in the sub clock, and if the sub clock is specified so that it stops oscillating while the sub clock is in operation, the sub oscillation stabilization timer stops, too, while the sub clock is in operation. 190 CHAPTER 7 HARDWARE WATCHDOG TIMER This chapter explains the functions of hardware watchdog timer. 7.1 Overview of Hardware Watchdog Timer 7.2 Configuration of Hardware Watchdog Timer 7.3 Hardware Watchdog Timer Register 7.4 Function of Hardware Watchdog Timer 7.5 Notes on Using Hardware Watchdog Timer 191 CHAPTER 7 HARDWARE WATCHDOG TIMER 7.1 Overview of Hardware Watchdog Timer Hardware watchdog timer issues the reset signal (setting initialization reset) when internal counter is not cleared for a specified period. ■ Hardware Watchdog Timer Hardware watchdog timer is a module for CPU operation monitoring. This timer immediately starts count up after the setting initialization reset (INIT). This timer must periodically be cleared within a specified period to continue the program execution. When the counter is not cleared over a specified period, such as entering to infinite loop, the reset signal is issued. The width of "L" pulse which is outputted to the external pin WDRESETX is 128 cycles of source oscillation clock, and the width of internal reset is 1024 cycles of the clock. Note: When CPU transfers to the mode which stops operations (standby mode) as follows, the operation of this module is also stopped. • SLEEP mode: CPU stop, peripheral circuit operation • STOP mode: CPU and peripheral circuit operation are stopped. • SHUT-DOWN mode: CPU and peripheral circuit operation are stopped. • RTC mode: CPU and peripheral circuits except for RTC module are stopped. Oscillator operation • Debug mode: When a break is generated by DSU (Debug Support Unit) and debug routine is running. If one of the following conditions is met, hardware watchdog timer is cleared. • "0" writing to CL bit of HWDCS register • Reset • Oscillation stops • Transfer to SLEEP/STOP/SHUT-DOWN, RTC, or Debug mode 192 CHAPTER 7 HARDWARE WATCHDOG TIMER 7.2 Configuration of Hardware Watchdog Timer Hardware watchdog timer consists of the following two circuits. • Watchdog timer • Hardware watchdog timer control register ■ Block Diagram of Hardware Watchdog Timer Figure 7.2-1 Block Diagram of Hardware Watchdog Timer For MB91461 CR oscillation X0/X1 input or oscillation circuit 1/2 For MB91F467R Counter FF Reset signal Clear Reserved Reserved Reserved Reserved CL Reserved Reserved CPUF Internal bus ● Watchdog timer This is a timer for monitoring CPU operation. Clear it periodically after reset releasing. ● Hardware watchdog timer control register This register has a reset flag and clear bit of timer. ● Reset issuance If the timer is not cleared over a specified period, the hardware watchdog timer module issues the setting initialization reset (INIT). The width of internal reset signal is 1024 cycles of source oscillation clock. ● Operating clock for watchdog timer The operating clock for the watchdog timer for MB91461 is a clock derived from X0 (external input or crystal oscillator) and a clock for MB91F467R is from the built-in CR oscillator. 193 CHAPTER 7 HARDWARE WATCHDOG TIMER 7.3 Hardware Watchdog Timer Register Hardware watchdog timer control register has a reset flag and a watchdog timer clear bit. ■ Hardware Watchdog Timer Register Figure 7.3-1 The Structure of Hardware Watchdog Timer Register HWDCS bit 7 6 5 4 Address: 0004C7H Reserved Reserved Reserved Reserved Read/Write (R/W) (R/W) (R/W) (R/W) Initial value 0 0 0 1 3 CL (W) 1 2 1 Reserved Reserved (R/W) 0 (R/W) 0 0 CPUF (R/W) 0 [bit7 to bit4] Reserved: Reserved bits These are reserved bits. Be sure to set these bits to "0001B". [bit3] CL: Timer clear bit This bit is a watchdog timer clear bit. Writing "0" to this bit clears the watchdog timer. Reading value is always "1". Writing "1" is invalid. [bit2, bit1] Reserved: Reserved bits These are reserved bits. Be sure to set these bits to "00B". [bit0] CPUF: CPU reset flag When overflow is generated in watchdog timer, this bit is set to "1". Writing "0" clears this bit. Writing "1" is invalid. This bit is initialized by external reset input (INITX) but not by internal reset (software reset). 194 CHAPTER 7 HARDWARE WATCHDOG TIMER ■ Hardware Watchdog Timer Period Register Figure 7.3-2 Hardware Watchdog Timer Period Register HWWDE bit 7 6 5 4 3 2 Address: 0004C6H Reserved Reserved Reserved Reserved Reserved Reserved Read/write Initial value - 1 0 ED1 R/W 0 ED0 R/W 0 [bit7 to bit2] Reserved: Reserved bit These are reserved bits. [bit1, bit0] ED1, ED0: Watchdog period setting This bit sets a watchdog period. ED1 ED0 Function 0 0 Watchdog period is 216*CR clock cycles (Initial value) 0 1 Watchdog period is 217*CR clock cycles 1 0 Watchdog period is 218*CR clock cycles 1 1 Watchdog period is 219*CR clock cycles Note: This function is not available on MB91461. Notes: • This function cannot be used with MB91461. • This function is not revokable from an initial value at the cycle though operates by the CR oscillation in MB91V460 (It is not revokable from 216 × CR). 195 CHAPTER 7 HARDWARE WATCHDOG TIMER 7.4 Function of Hardware Watchdog Timer If the watchdog timer is not cleared over a specified period, the setting initialization reset (INIT) is issued. In this case, the register value of CPU is not guaranteed. ■ Function of Hardware Watchdog Timer After a reset is released, the hardware watchdog timer starts counting up without waiting the stabilization time. If the timer is not cleared for a specified time and the counter overflows, the setting initialization reset (INIT) is issued. ■ Cycle of Hardware Watchdog Timer For MB91461, the bit length of the hardware watchdog timer is 23 bits and the overflow period is 932.1 ms (when source oscillation is 18 MHz). Table 7.4-1 Hardware Watchdog Timer Period on MB91461 9 MHz 18 MHz Watchdog timer operation clock cycle 0.22 µs 0.11 µs Watchdog timer cycle 1864.1 ms 932.1 ms WDRESETX output pulse width 14.22 µs 7.11 µs Time required for starting external bus cycle after WDRESETX is asserted 113.78 µs 56.89 µs For MB91F467R, because a CR oscillator is used as a clock source of the hardware watchdog timer, the timer period varies depending on the resolution of the CR oscillator. Table 7.4-2 Hardware Watchdog Timer Period on MB91F467R ED1, ED0 Minimum Normal Maximum 5 µs 10 µs 20 µs 00 327.68 ms 655.36 ms 1310.72 ms 01 655.36 ms 1310.72 ms 2621.44 ms 10 1310.72 ms 2621.44 ms 5242.88 ms 11 2621.44 ms 5242.88 ms 10485.76 ms WDRESETX output pulse width − 5 µs 10 µs 20 µs Time required for starting access to built-in FLASH after WDRESETX is asserted − − 740 µs − CR oscillation cycle Watchdog timer period 196 CHAPTER 7 HARDWARE WATCHDOG TIMER ■ Reset Timing for Watchdog Timer Overflow Figure 7.4-1 Reset Timing for Watchdog Timer Overflow For MB91461 (at 18 MHz oscillation) 7.11µs WDRESETX Internal reset 56.89µs For MB91F467R 10µs WDRESETX Internal reset and security processing wait time 740µs 197 CHAPTER 7 HARDWARE WATCHDOG TIMER ■ About WDRESETX Pin Output "L" level by the external reset input (INITX) as well as "L" pulse when the hardware watchdog timer overflows is outputted to the WDRESETX pin. When a watchdog reset is generated, the flash memory returns to the read mode even if the flash memory is in the write/erase mode by connecting the WDRESETX pin and a RESET pin of the external flash memory. Pulses of resets generated by the watchdog timer that is activated by CPU core internal software and pulses of software resets are not outputted to the WDRESETX pin. Therefore, these resets cannot be used as a factor that triggers the return of the flash memory from the write/erase mode. Note: There is no WDRESETX output in MB91V460. Please note that the WDRESETX output cannot be used when ICE is used and operated. 198 CHAPTER 7 HARDWARE WATCHDOG TIMER 7.5 Notes on Using Hardware Watchdog Timer This section explains the notes on using hardware watchdog timer. ■ Notes on Using Hardware Watchdog Timer ● Stop disabled in software Watchdog timer immediately starts operation after releasing reset. The counting cannot be stopped by software. ● Reset control Clearing of the timer is required to control hardware watchdog reset. When "0" is written to CL bit of the hardware watchdog timer control register, the timer is once cleared and the reset issuance is controlled. ● Stop and clear of timer In the mode which CPU is not operating (SLEEP mode, STOP mode, SHUT-DOWN mode and RTC mode), the timer is cleared before transferring to such mode and the count is stopped. Also, when a debug routine is running via DSU, the watchdog timer is cleared and the count is stopped. ● Operation during DMA transfer Writing "0" to CL bit is disabled since DMAC is occupying the bus during the DMA transfer to peripheral resources that are connected to internal D-bus. Therefore, in the case that DMA transfer time is longer than watchdog cycle, a reset is issued. 199 CHAPTER 7 HARDWARE WATCHDOG TIMER 200 CHAPTER 8 MEMORY CONTROLLER This section explains the control of the built-in flash memory installed in MB91F467RA and MB91F467RB. There is an explanation concerning the direct map cash that contributes at the instruction reading speed in the FLASH memory, too. 8.1 Overview of Memory Controller. 8.2 Registers 8.3 Explanations of Registers 8.4 FLASH access timing settings 201 CHAPTER 8 MEMORY CONTROLLER 8.1 Overview of Memory Controller. This section explains the overview of memory controller. This module combines the interfaces to the F-bus memory resources, FLASH memory and General Purpose RAM (also referenced as I/D-RAM). These memories can be combined CODE and DATA storage. While code fetch is possible in general via the F-bus at the FR core, due to performance reasons the code fetch is accelerated by a direct I-bus connection in this products. For FLASH memory access the interface contains an instruction cache and data read buffer. A prefetch mechanism removes CPU internal code fetch latencies for linear code. FLASH memory is installed only on MB91F467R. ● FLASH Interface • Wait timing • Generation of FLASH control signals ATDIN and EQIN for synchronous access. (this version supports independent timing configuration of ADTIN, EQIN and Wait) • Generation of CEX, WEX and OEX • Handling of 32 or 64 bit read mode and 16 or 32 bit read/write mode for programming • Support of external SRAM for emulation devices with 1:1 timing transparency (same wait cycles) • Measures for FLASH macro test and parallel programming support ● General-Purpose RAM Zero wait cycle access to shared code/data memory (up to 64 Kbytes), also referenced as I/D-RAM ● Zero wait cycle access to shared code/data memory (up to 64 Kbytes), also referenced as I/D-RAM Up to 8 Kbytes Instruction cache (4K words entries, one way direct mapped, prefetch miss option) ● Prefetch • Prefetch of consecutive instruction word address to the cache buffer • Prefetch is canceled in case of prefetch miss (branch or data access), thus it works without any penalties in the prefetch miss case. • The FLASH macro needs to support FLASH access cycle cancellation at any point, that means it may not affect the timing of the next complete access cycle (no special recovery condition required from previous access cancellation). 202 CHAPTER 8 MEMORY CONTROLLER 8.2 Registers This section lists the FLASH interface registers. ■ FLASH Interface Register List Table 8.2-1 FLASH-IF Register Overview Register Address 7000H 7004H Block +0 +1 FMCS [R/W] 00001000 FMCR [R/W] ----0000 FMWT [R/W] 11111111 01111111*1 11111111 01011101*2 +2 +3 FCHCR [R/W] ------00 1000011 FMWT2[R/W] -101---- 7008H FMAC [R] 00000000 00000000 00000000 00000000 700CH FCHA0 -------- -0000000 00000000 00000000 7010H FCHA1 -------- -0000000 00000000 00000000 FLASH_IF FMPS [R/W] -----000 *1: Initial value on MB91461 *2: Initial value on MB91F467R Notes: • Read and write access to all registers is byte, halfword and word. • FMCR and FMWT2 registers are not available on MB91461. • The initial values of the wait cycle setting register FMWT differs between the flash-less evaluation device MB91461 and devices with embedded flash memory. 203 CHAPTER 8 MEMORY CONTROLLER 8.3 Explanations of Registers This section explains a detailed function like the bit configuration etc. of the FLASH interface register. ■ FLASH Interface Control Register Control Register byte 0 bit Address:7000H 31 30 29 ASYNC Reserved BIRE RDYEG Read/write → (R/W) (R/W) (R/W) (0) (0) (0) Initial value → bit 23 Control Register byte 1 Address:7001H Read/write → Initial value → Control Register byte 2 28 bit Address: 7002H Read/write → Initial value → bit Control Register byte 3 Address: 7003H Read/write → Initial value → 27 26 25 24 RDY RDYI RW16 LPM (R) (0) (R) (1) 19 (R/W) (R/W) (R/W) (0) (0) (0) 22 21 20 - - - (-) (-) (-) (-) (-) (-) (-) (-) 15 14 13 12 11 10 9 8 - - - - - - REN (TAGE) (-) (-) (-) (-) (-) (-) (-) (-) (-) (-) (-) (-) 7 6 5 4 3 2 LOCK ENAB FLSH (DBEN) PFEN PFMC FMCS 18 LOCK PHASE 17 16 PF2I RD64 FMCR (R/W) (R/W) (R/W) (R/W) (0) (0) (0) (0) FCHCR (R/W) (R/W) (0) (0) 1 0 SIZE1 SIZE0 FCHCR (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (1) (0) (0) (0) (0) (0) (1) (1) ● FLASH Memory Control and Status Register (FMCS) [bit31] ASYNC: ASYNChronous access enable 0 Synchronous FLASH access (Initial value) 1 Asynchronous FLASH access The ASYNC bit is cleared at reset, which enables the fast synchronous FLASH access mode by default. To switch to asynchronous mode, set this bit (however it is basically not recommended to set this bit, neither in read nor in write access). [bit30] Reserved: Reserved bit 204 CHAPTER 8 MEMORY CONTROLLER [bit29] BIRE: Burn-In ROM Enable 0 Disable Burn-In ROM and enable FLASH access at Burn-In ROM address (Initial value) 1 Enable access to the Burn-In ROM [bit28] RDYEG: RDY status hold and qittation register 0 Auto algorithm not started or started and not completed (Initial value) 1 The FLASH auto-algorithm has been completed since last register read access. The RDYEG bit is cleared after reset. The bit is set after 0 →1 transition of FMCS_RDY. The bit shows that the RDY signal of the FLASH is or was active (completed auto-algorithm). The RDYEG bit is cleared automatically at read access to address 7000H. The RDYEG bit is read-only status information. [bit27] RDY: FLASH RDY status of auto-algorithm This bit shows the status of the RDY line of the FLASH macro. RDY is used to signalize the state of the FLASH macro in case of an auto-algorithm was started (e.g. sector erase, chip erase). If RDY returns to "1", the auto-algorithm has been completed. The RDY bit is read-only status information. [bit26] RDYI: RDY output force 0 Inactive (Initial value) 1 Force the RDY output to "1" This bit is reserved for FLASH test. Do not set this bit. [bit25] RW16: 16 bit Read/Write enable to FLASH 0 32 bit read and write access to FLASH is enabled (Initial value) 1 16 bit read and write access to FLASH is enabled This bit is cleared after reset. There is a 32 bit read and write access to the FLASH memory enabled by initial value. Setting of the RW16 bit implies switching from 32 bit into 16 bit mode. When it is intended to write data to the flash memory (or while chip erase or sector erase) then code fetch from the flash memory is not supported. 205 CHAPTER 8 MEMORY CONTROLLER Notes: • To maintain data consistency it is strongly recommended to disable the instruction cache while writing to the FLASH memory and to flush the instruction cache (FLUSH) after completing the write procedure to the FLASH memory. • It is not allowed to switch between the 16 bit, the 32 bit and the 64 bit mode while reading instructions or data from the FLASH memory. • There is no RW16 bit in MB91V460 (The change cannot operate). [bit24] LPM: Low Power Mode 0 Low power mode off (Initial value) 1 Low power mode enabled This bit is cleared after reset. The setting of the low power mode is switched off by initial value. If LPM=0, CEX is permanently asserted to "0" (active). This enables fastest possible FLASH access timing. Setting this bit to "1" enables the low power mode. CEX is asserted low only in case of FLASH access. In between the FLASH macro is in stand-by mode. Note: FLASH memory is not necessary to use this setting since the FLASH memory supports an "automatic sleep mode" which puts the FLASH automatically in a low power consumption state when not accessed. ● FLASH Memory Control Register (FMCR) The FMCR register is not available on the MB91461. [bit19] LOCK: ALEH auto-update lock 0 ALEH setting auto update is enabled (Initial value) 1 ALEH setting auto update is disabled FLASH memories embedded on the MB91467R require a certain timing between ATDIN falling edge and EQIN rising edge. This timing is named tALEH and has usually the same length as the ATDIN duration. By writing the setting of ATDIN length to the FMWT:ATD[2:0] bits, the FMWT2:ALEH[2:0] bits will be updated automatically to the same setting. To avoid this automatic update it is possible to set the LOCK bit. It is also possible to apply a different setting to the FMWT2:ALEH[2:0] bits by writing first to the FMWT:ATD[2:0] bits and second to the FMWT2:ALEH[2:0] bits. 206 CHAPTER 8 MEMORY CONTROLLER [bit18] PHASE: ATDIN/EQIN clock phase 0 ATDIN/EQIN generation is in phase with the core clock (Initial value) 1 ATDIN/EQIN generation is inverted to the core clock At lower core clock frequencies it can be beneficial to change the ATDIN/EQIN generation to inverted core clock to save a wait cycle compared to the generation of these signals in phase with the core clock. It is recommended to always refer to the setting requirements of ATDIN, EQIN and wait cycles for each product which are provided by our company (see also "8.4 FLASH access timing settings"). (PHASE setting is not available on MB91F467R) [bit17] PF2I: Prefetch 32 bit (2 instructions) only 0 Prefetch 64 bit (Initial value) 1 Prefetch 32 bit only When switching on 64 bit read mode (RD64=1) then prefetch will be performed on instruction address IA+8 (when current access is aligned at IA+0) and on instruction address IA+4 (when current access is aligned at IA+4). However, the setting of PF2I=1 in the 64 bit read mode will cause a prefetch only on next instruction address IA+4 (independent of current access alignment is IA+0 or IA+4). Usually prefetching 64 bit is superior to 32 bit only, however it can be the case on strong fragmented code that the performance deteriorates due to replacement of cache entries. In this case it can be sensible to switch to 32 bit prefetch only. [bit16] RD64: Enable 64 bit read mode 0 64 bit read mode is disabled (Initial value) 1 64 bit read mode is enabled Some embedded FLASH memories supports switching the 64 bit read mode to increase the access performance. Please contact our company if this feature is available on the product you are using. This bit is cleared after reset. The 32 bit read and write access to the FLASH memory is enabled by initial value. Setting of the RD64 bit implies switching from 32 bit into 64 bit mode. Writing data to the flash memory is not supported in the 64 bit read only mode. Notes: • It is not allowed to switch between the 16 bit, the 32 bit and the 64 bit mode while reading instructions or data from the FLASH memory. • There is no RD64 bit in MB91V460. 207 CHAPTER 8 MEMORY CONTROLLER ● FLASH Cache Control Register (FCHCR) [bit9] REN: Non-cacheable area Range Enable 0 FCHA1 defines address mask (Initial value) 1 FCHA1 defines second point for the non-cacheable address range from FCHA0 to FCHA1 The bit is cleared after reset. The address defined in FCHA0 is combined with a bit mask defined in FCHA1 to define the non-cacheable area. If the REN bit is set, the non-cacheable area is defined by two points. The non-cacheable range is from addresses greater than or equal to FCHA0 up to addresses less than or equal to FCHA1. [bit8] TAGE: TAG RAM access Enable 0 Memory mapped TAG RAM access disabled (Initial value) 1 Memory mapped TAG RAM access enabled The bit is set to "0" after reset. (TAG RAM access is not available on MB91F467R). [bit7] FLUSH: Flush instruction cache entries 0 Flushing the instruction cache entries has been completed 1 Actually flushing the instruction cache entries This bit is set after reset. If the FLUSH bit is set, the instruction cache entries are flushed sequentially. During this initialization the cache is disabled. The initialization has a duration of 1 clock cycle per cache entry. The number of valid entries depends on the configured cache size. After completion (all entries are flushed) the FLUSH bit is cleared by hardware. Writing a "1" to this bit triggers the flushing of the cache entries. Note: It is not allowed to set the cache size configuration (FCHCR:SZ[1:0]) and FLUSH at the same time (same write access). Always first set the size configuration before flushing the cache. The cash capacity is 8 Kbyte for MB91F467R. 208 CHAPTER 8 MEMORY CONTROLLER [bit6] DBEN: Data Buffer ENable 0 Buffering of read data is disabled (Initial value) 1 Buffering of read data is enabled This bit is cleared after reset. The read data buffer is disabled by initial value. Setting the DBEN bit enables the data read buffer. This is useful to speed up reading of data structures of 8 or 16 bit operands. There is one word data buffer implemented. If the same 32 or 64 bit word address is accessed consecutively, the data is read from the buffer. (Data buffer is not available on MB91F467R.) [bit5] PFEN: PreFetch ENable 0 Prefetch of instructions is disabled (Initial value) 1 Prefetch of instructions is enabled This bit is cleared after reset. The prefetch of instructions is disabled by initial value. Setting the PFEN bit enables the code prefetch from the next word on instruction address IA+4. Prefetch eliminates any latency in the code fetch path of the MCU to the FLASH memory for linear code. When switching on 64 bit read mode (RD64=1) then prefetch will be performed on instruction address IA+8 (when current access is aligned at IA+0) and on instruction address IA+4 (when current access is aligned at IA+4). However, the setting of PF2I=1 in the 64 bit read mode will cause a prefetch only on next instruction address IA+4 (independent of current access alignment is IA+0 or IA+4). A running prefetch cycle can be directly taken over from a matching instruction access. If there is no instruction access in between, the prefetched instruction word is stored in cache memory. If there is an FLASH access (code or data) to an address different from the prefetch address, the prefetch cycle is cancelled immediately. [bit4] PFMC: Prefetch Miss Cache enable 0 Standard cache algorithm (Initial value) 1 Prefetch misses are cached only This bit is cleared after reset. The prefetch miss cache is disabled by initial value. The instruction cache uses the standard algorithm of writing cache entries for each accessed instruction word from FLASH memory. Setting the PFMC bit switches to a second write algorithm for cache entries. This algorithm writes only this instruction words to the cache, which are causing prefetch miss conditions. The FR CPU requests approximately one instruction word (which contains two 16 bit instruction codes) in two clock cycles. If the FLASH data throughput (one word in two cycles) is sufficient for the needs of the CPU, the PFMC option is useful in most cases. If the FLASH access time is two clock cycles, normally no wait states are generated when the next instruction word is requested from a consecutive address and prefetch is enabled. Thus, caching such 209 CHAPTER 8 MEMORY CONTROLLER linear code segments in conjunction with prefetch may not improve the code fetch performance, which is at the optimum already. More interesting is to improve the situation for branches in the code, where prefetch could not remove the latency of accessing it. If FPMC is set to "1", the cache algorithm stores only these FLASH accesses, which have caused a wait condition due to a prefetch miss condition (not matched predicted address). The effect of this algorithm is, that the restricted amount of cache entries is utilized more efficiently. Usually the same performance can be reached with half the cache size. Or, in other words, the cache is as same efficient as it would have the doubled size. The efficiency of the PFMC algorithm depends on the structure of the application. [bit3] LOCK: Global lock of cache entries 0 Write of cache entries enabled (Initial value) 1 Writing of cache entries is disabled, the cache contents is locked This bit is cleared during reset. The cache entries are writable by initial value. If the LOCK bit is set, no new entries can be written to cache memory. The old contents of cache entries remains in memory. There is only a global lock feature for all cache entries. [bit2] ENAB: Instruction cache enable 0 Instruction cache is disabled (Initial value) 1 Instruction cache is enabled This bit is cleared after reset. By initial value the instruction cache is disabled. If the ENAB bit is set, the instruction cache is switched on. The instruction cache is dedicated to FLASH access only. The cache is utilized by the prefetch algorithm as prefetch buffer. Hence prefetch can be used in an unbuffered form with cache disabled. The FLASH access is started in parallel, independent from cache hit or miss evaluation. (If the cache is disabled, the cache entries and the TAG RAM contents can be accessed memory mapped. This feature is disabled in this version of the interface, see the explanation of the TAGE bit.) [bit1, bit0] SZ[1:0]: Cache size configuration 00 0 Kbyte - Cache disabled 01 4 Kbytes (1024 entries) 10 8 Kbytes (2048 entries) 11 16 Kbytes (4096 entries) (Initial value) The cache size is set to "11B" after reset. 210 CHAPTER 8 MEMORY CONTROLLER Notes: • The number of cache entries determines the TAG initialization period at device startup, see the explanation of the FLUSH bit above. • Set the capacity configuration to 8 Kbytes before using FLASH cache. • It is not allowed to set the cache size configuration (FCHCR:SZ[1:0]) and FLUSH at the same time (same write access). Always first set the size configuration before flushing the cache. • The cash of 8 Kbytes is built into MB91F467R, and set A6H, please after setting 02H to the FCHCR register. 211 CHAPTER 8 MEMORY CONTROLLER ■ FLASH Memory Wait Timing Register (FMWT) FLASH Memory Wait Timing Register byte0 30 bit 31 Address: 7004H 29 28 27 26 WTP1 WTP0 WEXH1 WEXH0 WTC3 WTC2 25 24 WTC1 WTC0 FMWT Read/Write → (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (1) (1) (1) (1) (1) (1) (1) (1) Default value → FLASH Memory Wait Timing Register byte1 bit 23 Address: 7005H Read/Write → Default value → 22 (FRAM) ATD2 Read/Write → Default value → Read/Write → Default value → 19 18 17 16 ATD1 ATD0 EQ3 EQ2 EQ1 EQ0 13 12 11 10 9 8 FMWT1 FMWT2 - ALEH2 ALEH1 ALEH0 - - - - (X) (-) (R/W) (R/W) (R/W) (1) (0) (1) (-) (-) (-) (-) (-) (-) (-) (-) FLASH Memory Wait Timing Register byte3 bit 7 Address: 7007H 20 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (0) (1) (1/0) (1) (1) (1) (1/0) (1) FLASH Memory Wait Timing Register byte2 14 bit 15 Address: 7006H 21 6 5 4 3 2 1 0 - - - - - PS2 PS1 PS0 (-) (-) (-) (- ) (-) (- ) (-) (- ) (-) (-) FMPS (R/W) (R/W) (R/W) (0) (0) (0) Notes: • ATD[2:0] setting is 7H on MB91461 and 5H on MB91F467R. • EQ[3:0] setting is FH on MB91461 and DH on MB91F467R. • FMWT2 is not available on MB91461. [bit31, bit30] WTP[1:0]: Wait cycles for FLASH in page access WTP is set to "11B" after reset. WTP controls the wait timing of the FLASH access in case of page hit for Page Mode FLASH. The WTP configuration is in units of clock cycles. The value of WTP should be set to the intra page access time (cycle time) of the FLASH memory in number of clock cycles, subtracted by one. The setting is used if the page size PS[2:0] is set different to 0. [bit29, bit28] WEXH[1:0]: Minimum WEX High timing requirement WEXH is set to "11B" after reset. The minimum high time duration of WEX is 5 cycles by initial value. Setting an other value reduces the WEX high time to 2 fixed cycles + WEXH. 212 CHAPTER 8 MEMORY CONTROLLER [bit27 to bit24] WTC[3:0]: Wait cycles for FLASH memory access WTC is set to "1111B" after reset. WTC controls the wait timing of the FLASH access. The WTC configuration is in units of clock cycles. The value of WTC should be set to the access time (cycle time) of the FLASH memory in number of clock cycles, subtracted by one. [bit23] FRAM: Wait cycles for F-bus general purpose RAM memory access FRAM is set to "0" after reset. This is a reserved bit. This version on MB91V460 has no configurable wait timing to F-bus RAM, it operates with fixed "0" wait states RAM access. [bit22 to bit20] ATD[2:0]: Duration of the ATDIN signal for FLASH memory access MB91461: ATD is set to "111B" after reset. ATD defaults to 4 clock cycles. MB91F467R: ATD is set to "101B" after reset. ATD defaults to 3 clock cycles. ATD controls the timing of the ATDIN signal for FLASH access. The ATD configuration is in units of half clock cycles. The effective high duration of ATDIN equals to tATDIN=(ATD+1) x 0.5 clock cycles. [bit19 to bit16] EQ[3:0]: Duration of the EQIN signal for FLASH memory access MB91461: EQ is set to "1111B" after reset. EQ defaults to 8 clock cycles. MB91F467R: EQ is set to "1101B" after reset. EQ defaults to 7 clock cycles. EQ controls the timing of the EQIN signal for FLASH access. The EQ configuration is in units of half clock cycles. The effective high duration of EQIN equals to tEQIN=(EQ+1) x 0.5 clock cycles. [bit14 to bit12] ALEH[2:0]: Duration of the ALEH time for FLASH memory access MB91461: not available MB91F467R: ALEH is set to "101B" after reset. ALEH defaults to 3 clock cycles. ALEH controls the timing of the ATDIN falling edge to EQIN rising edge for FLASH access. The EQ configuration is in units of half clock cycles. The effective duration of ALEH equals to tALEH=(ALEH+1) x 0.5 clock cycles. Note: ALEH[2:0] is updated automatically to the same value as ATD[2:0] when writing to ATD[2:0]. Usually the ALEH time equals the ATD time, so there is normally no reason to update ALEH[2:0] in particular. Even though it is possible to program ALEH[2:0] with a different value than ATD[2:0] by: • Writing a different value to ALEH[2:0] after writing to ATD[2:0], or • Setting the FMCR:LOCK bit to disable the auto update 213 CHAPTER 8 MEMORY CONTROLLER ● FLASH access cycle waveform Figure 8.3-1 Timing of a FLASH Access Cycle flash_start FMA ATDIN EQIN flash_wait DO tATD tALEH tEQ tWTC tRC Figure 8.3-1 shows the example of a FLASH access cycle. In the FMWT register the three parts of the FLASH timing tATD, tALEH, tEQ and tWTC can be configured independently. The table below lists the configuration values for this example. Symbol Length Setup tATD 1.5 cycles ATD=010B tALEH 1.5 cycles ALEH=010B tEQ 3 cycles EQ=0101B tWTC 6 cycles WTC=0110B The resulting FLASH access cycle (tRC) time is 7 cycles (WTC+1). [bit2 to bit0]: PS[2:0] - Page size definition for Page Mode FLASH PS is set to "000B" after reset. Page Mode FLASH is disabled by default. This setting defines the page size to 2PS in number of bytes. (Embedded FLASH memories on MB91F467R do not support page mode) 214 CHAPTER 8 MEMORY CONTROLLER ■ FLASH Memory Address Check Register (FMAC) FMAC [R] Address +0 +1 +2 +3 7008H -------- -0000000 00000000 00000000 This register captures the address at the begin of a FLASH access cycle for test purposes. The register could be read only. ■ Non-cacheable Area Definition The non-cacheable area definition registers FCHA0 and FCHA1 define the FLASH region not to be cached. Not used bits are read back as "0". The tables below define the initial values of the registers. The point defined by FCHA0 = 0 and mask bits off is located outside the FLASH region, thus initially the whole FLASH region will be cached. FCHA0 [R/W] Address +0 +1 +2 +3 700CH -------- -0000000 00000000 00000000 FCHA1 [R/W] Address +0 +1 +2 +3 7010H -------- -0000000 00000000 00000000 If the FCHCR_REN bit is cleared, the address range is defined by the address given by FCHA0, masked with the bits set to "1" in FCHA1. Example 1 (Point and mask range definition): - FCHCR_REN = 0 - FCHA0 = 000F:A300 - FCHA1 = 0000:FFFF The non-cacheable area is defined from 000F:0000H to 000F:FFFFH. Example 2 (Point to point range definition): - FCHCR_REN = 1 - FCHA0 = 000F:A300 - FCHA1 = 000F:F7FF The non-cacheable area is defined from 000F:A300H to 000F:F7FFH. 215 CHAPTER 8 MEMORY CONTROLLER 8.4 FLASH access timing settings This section explains the read/write timing settings of FLASH memory. The settings shown below are currently based on simulation results only and are subject to change after device evaluation. Please contact Fujitsu to check whether these settings are valid for your product. ■ Read Timing Settings Table 8.4-1 Read Timing Settings of FLASH Memory Core clock CLKB ATD ALEH EQ WEXH WTC 2MHz 000B 000B 0000B - 0001B 32MHz, 48MHz 000B 000B 0001B - 0010B 64MHz, 80MHz, 96MHz, 100MHz 001B 001B 0011B - 0100B Notes: • These settings are for FLASH memory synchronous read mode (FMCS:ASYNC=0). • The ALEH setting is the same as the ATD setting therefore it will be updated automatically when applying a new setting value to the FMWT:ATD[2:0] register. ■ Write Timing Settings Table 8.4-2 Write Timing Settings of FLASH Memory Core clock CLKB 216 ATD EQ ALEH WEXH WTC 2MHz 000B - - 00B 0011B 32MHz 001B - - 00B 0100B 48MHz 001B - - 00B 0101B 64MHz 001B - - 00B 0110B 80MHz, 96MHz 001B - - 00B 0111B 100MHz 001B - - 01B 1000B CHAPTER 8 MEMORY CONTROLLER Notes: • These settings are for FLASH memory synchronous write mode (FMCS:ASYNC=0). • Do not set less than 3 wait cycles in the FLASH memory synchronous write mode. • Writing to FLASH memory is only possible in 16 bit access mode (FMCS:RW16=1 and FMCR:RD64=0) or 32 bit access mode (FMCS:RW16=0 and FMCR:RD64=0). 217 CHAPTER 8 MEMORY CONTROLLER 218 CHAPTER 9 EXTERNAL BUS INTERFACE This chapter explains each function of the external bus interface. 9.1 Features of External Bus Interface 9.2 External Bus Interface Registers 9.3 Chip Select Area 9.4 Endian and Bus Access 9.5 Normal Bus Interface 9.6 Address/Data Multiplex Interface 9.7 DMA Access 9.8 Procedure for Setting Registers 219 CHAPTER 9 EXTERNAL BUS INTERFACE 9.1 Features of External Bus Interface This section explains the features of the external bus interface. ■ Features of External Bus Interface • Addresses of up to 24-bit length can be outputted. • Various types of external memory (8-bit/16-bit) can be directly connected and multiple access timings can be mixed and controlled. - Asynchronous SRAM and asynchronous ROM/FLASH memory (Multiple write strobe method) - Address/data multiplex bus (8-bit/16-bit width only) • Five independent banks (chip select areas) can be set, and chip select corresponding to each bank can be outputted. - CS0 to CS4 can be set to the space between "00040000H" and "00FFFFFFH" in units of 64 Kbytes to 2048 Mbytes. - Boundaries may be limited depending on the size of the area. • In each chip select area, the following functions can be set independently: - Enabling and disabling of the chip select area (Disabled areas cannot be accessed) - Setting of the access timing type such as support for various types of memory - Detailed access timing setting (Individual setting of the access type such as the wait cycle) - Setting of the data bus width (8-bit/16-bit) • A different detailed timing can be set for each access timing type. - For the same type of access timing, a different setting can be made in each chip select area. - Auto-wait can be set to up to 7 cycles. (Asynchronous SRAM, ROM, Flash and I/O area) - The bus cycle can be extended by external RDY input. (Asynchronous SRAM, ROM, Flash and I/O area) - Various types of idle/recovery cycles and setup delays can be inserted. 220 CHAPTER 9 EXTERNAL BUS INTERFACE ■ Block Diagram of External Bus Interface Figure 9.1-1 shows the block diagram of external bus interface. Figure 9.1-1 Block Diagram of External Bus Interface Internal Address Bus 32 Internal Data Bus 32 A-Out Write Buffer Switch Read Buffer Switch M U X External Data Bus Data Block Address Block +1 or +2 External Address Bus Address Buffer Comparator ASR ASZ External Pin Control All Block Control Register & Control CS0X to CS4X ASX, RDX WR0X, WR1X BRQ BGRNTX RDY SYSCLK 221 CHAPTER 9 EXTERNAL BUS INTERFACE ■ I/O Pins I/O pins are external bus interface pins. [Normal bus interface] A23 to A00, D31 to D16 (AD15 to AD00) CS0X, CS1X, CS2X, CS3X, CS4X ASX, SYSCLK, RDX, WR0X, WR1X, WEX RDY, BRQ, BGRNTX, MCLKE, MCLKI, MCLKO, BAAX note: It is time when it uses an external bus with MB91F467R and set FPR10_5 to "0", please when you do not use SDRAM. When this is set to "1", it is necessary to connect MCLKI with MCLKO. This necessity is not in MB91461. Moreover, there is MCLKE, MCLKI or neither MCLKO nor BAAX in MB91461. ■ Register List of External Bus Interface Figure 9.1-2 lists the register list of external bus interface. Figure 9.1-2 Register List of External Bus Interface Address bit 31 24 23 16 15 7 0 000640H ASR0 ACR0 000644H ASR1 ACR1 000648H ASR2 ACR2 00064CH ASR3 ACR3 000650H ASR4 ACR4 000660H AWR0 AWR1 000664H AWR2 AWR3 000668H AWR4 Reserved 000678H IOWR0 IOWR1 IOWR2 Reserved 000680H CSER CHER Reserved TCR 0007FCH Reserved MODR* Reserved Reserved Reserved: Reserved register. Be sure to set "0" at rewrite. *: MODR cannot be accessed from user programs. 222 8 CHAPTER 9 EXTERNAL BUS INTERFACE 9.2 External Bus Interface Registers This section explains the registers used in the external bus interface. ■ Overview of External Bus Interface Registers The following seven types of registers are used by the external bus interface: • Area Select Register (ASR0 to ASR4) • Area Configuration Register (ACR0 to ACR4) • Area Wait Register (AWR0 to AWR4) • I/O Wait Register for DMAC (IOWR0 to IOWR2) • Chip Select Enable Register (CSER) • CacHe Enable Register (CHER) • Terminal and Timing Control Register (TCR) 223 CHAPTER 9 EXTERNAL BUS INTERFACE 9.2.1 Area Select Register (ASR0 to ASR4) This section explains the details of area select registers. ■ Register Configuration of ASR0 to ASR4 (Area Select Register) Figure 9.2-1 shows the register configuration of ASR0 to ASR4 (area select register). Figure 9.2-1 Register Configuration of ASR0 to ASR4 (Area Select Register) ASR0 bit15 ... 8 7 6 ... 1 0 000640H A31 ... A24 A23 A22 ... A17 A16 ASR1 bit15 ... 8 7 6 1 0 000644H A31 ... A24 A23 A22 A17 A16 ASR2 bit15 ... 8 7 6 1 0 000648H A31 ... A24 A23 A22 A17 A16 ASR3 bit15 ... 8 7 6 1 0 00064CH A31 ... A24 A23 A22 A17 A16 ASR4 bit15 ... 8 7 6 1 0 00064CH A31 ... A24 A23 A22 A17 A16 ... ... ... ... Initial value At INIT At RST Access 0000H 0000H R/W XXXXH XXXXH R/W XXXXH XXXXH R/W XXXXH XXXXH R/W XXXXH XXXXH R/W [bit15 to bit0] A31 to A16: Area start address ASR0 to ASR4 (Area Select Registers 0 to 4) specify the start address of each chip select area for CS0X to CS4X. The start address can be set in the high-order 16 bits A[31:16]. Each chip select area starts with the address set in this register and covers the range set by ASZ[3:0] bits of the ACR0 to ACR4 registers. The boundary of each chip select area is specified by the setting of ASZ[3:0] bits of the ACR0 to ACR4 registers. For example, if an area of 1Mbyte is set by ASZ[3:0] bits, the low-order 4 bits of the ASR0 to ASR4 registers are ignored and only A[23:20] bits are valid. The ASR0 register is initialized to "0000H" by INIT or RST. ASR1 to ASR4 are not initialized by INIT or RST but become undefined. After starting LSI operation, be sure to set the corresponding ASR register by CSER register before enabling each chip select area. 224 CHAPTER 9 EXTERNAL BUS INTERFACE 9.2.2 Area Configuration Register (ACR0 to ACR4) This section explains the details of area configuration registers. ■ Register Configuration of Area Configuration Register (ACR0 to ACR3) Register configuration of ACR0 to ACR3 is as follows. Figure 9.2-2 Register Configuration of ACR0 to ACR3 (Area Configuration Register) ACR0 Higher 000642H ACR0 Lower 000643H ACR1 Higher 000646H ACR1 Lower 000647H ACR2 Higher 00064AH ACR2 Lower 00064BH ACR3 Higher 00064EH ACR3 Lower 00064FH ACR4 Higher 000652H ACR4 Lower 000653H bit15 14 13 12 11 10 9 8 6 5 SREN PFEN WREN bit15 14 13 4 0 12 R/W TYP3 TYP2 TYP1 TYP0 00000000B 00000000B R/W 3 11 2 10 1 9 6 5 4 3 2 1 8 14 13 12 11 10 9 6 5 4 3 2 1 14 13 12 11 10 9 6 5 4 3 2 1 14 13 12 11 10 9 6 5 4 3 2 1 R/W xxxxxxxxB xxxxxxxxB R/W xxxxxxxxB xxxxxxxxB R/W xxxxxxxxB xxxxxxxxB R/W xxxxxxxxB xxxxxxxxB R/W xxxxxxxxB xxxxxxxxB R/W xxxxxxxxB xxxxxxxxB R/W 8 ASZ3 ASZ2 ASZ1 ASZ0 DBW1 DBW0 BST1 BST0 bit7 xxxxxxxxB 0 SREN PFEN WREN LEND TYP3 TYP2 TYP1 TYP0 bit15 xxxxxxxxB 8 ASZ3 ASZ2 ASZ1 ASZ0 DBW1 DBW0 BST1 BST0 bit7 R/W 0 SREN PFEN WREN LEND TYP3 TYP2 TYP1 TYP0 bit15 xxxxxxxxB 8 ASZ3 ASZ2 ASZ1 ASZ0 DBW1 DBW0 BST1 BST0 bit7 xxxxxxxxB 0 SREN PFEN WREN LEND TYP3 TYP2 TYP1 TYP0 bit15 1111**00B 0 ASZ3 ASZ2 ASZ1 ASZ0 DBW1 DBW0 BST1 BST0 bit7 Access 1111**00B ASZ3 ASZ2 ASZ1 ASZ0 DBW1 DBW0 BST1 BST0 bit7 Initial value At INIT At RST 0 SREN PFEN WREN LEND TYP3 TYP2 TYP1 TYP0 ACR0 to ACR4 (Area Configuration Registers 0 to 4) set the functions of each chip select area. The same value of the WTH bit of mode vector is written to the initial value of DBW1, DBW0 bit of ACR0. 225 CHAPTER 9 EXTERNAL BUS INTERFACE [bit15 to bit12] ASZ3 to ASZ0 = Area Size bits [3:0] Table 9.2-1 lists the size of each chip select area by area size bits. Table 9.2-1 Size of Each Chip Select Area by Area Size Bits ASZ3 ASZ2 ASZ1 ASZ0 Size of each chip select area 0 0 0 0 64 Kbytes (00010000H byte, ASR A[31:16] bit specification is valid) 0 0 0 1 128 Kbytes (00020000H byte, ASR A[31:17] bit specification is valid) 0 0 1 0 256 Kbytes (00040000H byte, ASR A[31:18] bit specification is valid) 0 0 1 1 512 Kbytes (00080000H byte, ASR A[31:19] bit specification is valid) 0 1 0 0 1 Mbyte (00100000H byte, ASR A[31:20] bit specification is valid) 0 1 0 1 2 Mbytes (00200000H byte, ASR A[31:21] bit specification is valid) 0 1 1 0 4 Mbytes (00400000H byte, ASR A[31:22] bit specification is valid) 0 1 1 1 8 Mbytes (00800000H byte, ASR A[31:23] bit specification is valid) 1 0 0 0 16 Mbytes (01000000H byte, ASR A[31:24] bit specification is valid) 1 0 0 1 32 Mbytes (02000000H byte, ASR A[31:25] bit specification is valid) 1 0 1 0 64 Mbytes (04000000H byte, ASR A[31:26] bit specification is valid) 1 0 1 1 128 Mbytes (08000000H byte, ASR A[31:27] bit specification is valid) 1 1 0 0 256 Mbytes (10000000H byte, ASR A[31:28] bit specification is valid) 1 1 0 1 512 Mbytes (20000000H byte, ASR A[31:29] bit specification is valid) 1 1 1 0 1024 Mbytes (40000000H byte, ASR A[31:30] bit specification is valid) 1 1 1 1 2048 Mbytes (80000000H byte, ASR A[31] bit specification is valid) ASZ[3:0] are used to set the size of each area by changing the number of bits for address comparison with ASR. Thus, an ASR contains bits that are not compared. ASZ[3:0] bits of ACR0 are initialized to "1111B" by RST. Despite this setting, however, the CS0 area just after RST is exceptionally set from "00000000H" to "FFFFFFFFH" (setting of entire area). The entire area setting is cancelled after the first writing to ACR0 and an appropriate size is set as indicated in the above table. 226 CHAPTER 9 EXTERNAL BUS INTERFACE [bit11, bit10] DBW1, DBW0: Data Bus Width 1, 0 Table 9.2-2 lists the data bus width of each chip select area. Table 9.2-2 Data Bus Width of Each Chip Select Area DBW1 DBW0 Data bus width 0 0 8-bit 0 1 16-bit (halfwordaccess) 1 0 Reserved, Setting disabled 1 1 Reserved, Setting disabled (byteaccess) The same values as those of the WTH bits of the mode vector are written automatically to bits DBW1 and DBW0 of ACR0 during the reset sequence. [bit9, bit8] BST1, BST0: Burst Size 1, 0 Table 9.2-3 lists the burst size of each chip select area. Table 9.2-3 Burst Size of Each Chip Select Area BST1 BST0 Maximum burst size 0 0 1 (Single access) 0 1 2 bursts 1 0 4 bursts 1 1 8 bursts Areas with the burst size setting other than single access execute continuous burst access within the address boundary defined by the burst size only when prefetch access is executed or data with size over bus width is read. The maximum burst size shall not exceed 2 bursts in 16-bit bus width area. [bit7] SREN: ShaRed ENable Table 9.2-4 lists the enabling and disabling of BRQ/BGRNTX sharing in each chip select area. Table 9.2-4 Enabling and Disabling of BRQ/BGRNTX Sharing in Each Chip Select Area SREN Share enabled/disabled 0 BRQ/BGRNTX sharing disabled (CSnX does not become Hi-Z.) 1 BRQ/BGRNTX sharing enabled (CSnX becomes Hi-Z.) In sharing enabled areas, CSnX becomes Hi-Z when bus is open (when BGRNTX="L" outputting). In sharing disabled areas, CSnX does not become Hi-Z even when bus is open (when BGRNTX="L" outputting). Access strobe outputs (RDX, WR1X, WR0X) become Hi-Z only when sharing is enabled in all areas enabled by CSER. 227 CHAPTER 9 EXTERNAL BUS INTERFACE [bit6] PFEN: PreFetch ENable Table 9.2-5 lists the enabling and disabling of prefetch in each chip select area. Table 9.2-5 Enabling and Disabling of Prefetch in Each Chip Select Area PFEN Prefetch enabled/disabled 0 Prefetch disabled 1 Prefetch enabled When an area where prefetch is enabled is read, prefetch is performed to the subsequent address and the content is stored in a built-in prefetch buffer. When the internal bus accesses to the stored address, the prefetch data in the prefetch buffer is returned without executing external accesses. [bit5] WREN: WRite ENable Table 9.2-6 lists the enabling and disabling of writing to each chip select area. Table 9.2-6 Enabling and Disabling of Writing to Each Chip Select Area WREN Write enabled/disabled 0 Write disabled 1 Write enabled If an area where write operations are disabled is accessed for a write operation from the internal bus, the access is ignored and no external access is performed. Set "1" for the WREN bit of areas where write operations are required, such as data areas. [bit4] LEND: Little ENDian select Table 9.2-7 lists the byte ordering in each chip select area. Table 9.2-7 Byte Ordering in Each Chip Select Area LEND Byte ordering 0 Big endian 1 Little endian LEND bit of ACR0 is constantly set to "0" and so the byte ordering is always big endian. 228 CHAPTER 9 EXTERNAL BUS INTERFACE [bit3 to bit0] TYP[3:0]: TYPe select Table 9.2-7 lists the access type of each chip select area. Table 9.2-8 Access Type of Each Chip Select Area TYP3 TYP2 TYP1 TYP0 0 X X Normal access (Asynchronous SRAM, I/O, ROM/Flash) 1 X X Address data multiplex access (8/16-bit bus width only) X 0 Disable WAIT insertion by RDY pin X 1 Enable WAIT insertion by RDY pin 0 X Use the WR0X and WR1X pins as write strobes 1 X Setting disabled 0 Setting disabled 1 Setting disabled 0 X 1 Access type 0 0 0 1 0 Setting disabled 0 1 1 Setting disabled 1 0 0 Setting disabled 1 0 1 Setting disabled 1 1 0 Setting disabled 1 1 1 Mask area setting (The access type is the same as that of the overlapped area) * Set the access type in combination of each bit. *: CS area mask setting function If you want to define an area in where some of the operation settings are changed in a certain CS area (hereinafter referred to as the base setting area), you can set ACR:TYP[3:0]=1111B in the setting of another CS area so that the area can function as a mask setting area. If you do not use the mask setting function, disable the settings of any overlapping area over multiple CS areas. Access operations to the mask setting area are as follows: - CSX corresponding to a mask setting area is not asserted. - CSX corresponding to a base setting area is asserted. - For the following ACR settings, the settings on the mask setting area side become valid: bit11, bit10 (DBW1, DBW0): Bus width setting bit9, bit8 (BST1, BST0): Burst size setting bit7 (SREN): Sharing-enable setting bit6 (PFEN): Prefetch-enable setting bit5 (WREN): Write-enable setting (* For this setting only, a setting that is different from that of the base setting area is not allowed.) bit4 (LEND): Little endian setting 229 CHAPTER 9 EXTERNAL BUS INTERFACE - For the following ACR setting, the setting on the base setting area side becomes valid: bit3 to bit0 (TYP3 to TYP0): Access type setting - For the AWR setting, the setting on the mask setting area side becomes valid. - For the CHER setting, the setting on the mask setting area side becomes valid. A mask setting area can be set only within a part of another CS area (base setting area). You cannot set a mask setting area for an area without a base setting area. Also do not overlap mask setting areas. Use care when setting ASR and ACR:ASZ[1:0] bits. Notes: The following restrictions apply for [bit3 to bit0] TYP[3:0]: • A write-enable setting cannot be implemented by a mask. • Set the same write-enable setting for the base CS area and the mask setting area. • If write operations to a mask setting area are disabled, the area is not masked and operates as a base CS area. • If write operations to the base CS area are disabled but are enabled to the mask setting area, the area becomes no base setting area and malfunctions will occur. 230 CHAPTER 9 EXTERNAL BUS INTERFACE 9.2.3 Area Wait Register (AWR0 to AWR4) This section explains the details of area wait register. ■ Register Configuration of Area Wait Register (AWR0 to AWR4) Figure 9.2-3 shows the register configuration of AWR0 to AWR3. Figure 9.2-3 Register Configuration of AWR0 to AWR3 AWR0 Higher bit31 0000 0660H W15 AWR0 Lower bit23 0000 0661H W07 AWR1 Higher bit15 30 29 28 27 26 25 24 W14 W13 W12 W11 W10 W09 W08 22 21 20 19 18 17 16 W06 W05 W04 W03 W02 W01 W00 14 13 12 11 10 9 8 0000 0662H W15 W14 W13 W12 W11 W10 W09 AWR1 Lower bit7 6 5 4 3 2 1 0000 0663H W07 W06 W05 W04 W03 W02 W01 30 29 28 27 26 25 W14 W13 W12 W11 W10 W09 22 21 20 19 18 17 W06 W05 W04 W03 W02 W01 14 13 12 11 10 9 AWR2 Higher bit31 0000 0664H W15 AWR2 Lower bit23 0000 0665H W07 AWR3 Higher bit15 0000 0666H W15 W14 W13 W12 W11 W10 W09 AWR3 Lower bit7 6 5 4 3 2 1 0000 0667H W07 W06 W05 W04 W03 W02 W01 14 13 12 11 10 9 AWR4 Higher bit15 0000 0668H W15 W14 W13 W12 W11 W10 W09 AWR4 Lower bit7 6 5 4 3 2 1 0000 0669H W07 W06 W05 W04 W03 W02 W01 Initial value At INIT At RST Access 01111111B 01111111B R/W 11111011B 11111011B R/W W08 XXXXXXXXB XXXXXXXXB R/W 0 W00 XXXXXXXXB XXXXXXXXB R/W 24 W08 XXXXXXXXB XXXXXXXXB R/W 16 W00 XXXXXXXXB XXXXXXXXB R/W 8 W08 XXXXXXXXB XXXXXXXXB R/W 0 W00 XXXXXXXXB XXXXXXXXB R/W 8 W08 XXXXXXXXB XXXXXXXXB R/W 0 W00 XXXXXXXXB XXXXXXXXB R/W AWR0 to AWR4 specify various types of wait timing for each chip select area. The function of each bit changes according to the access type (TYP[3:0] bits) setting of the ACR0 to ACR4 registers. 231 CHAPTER 9 EXTERNAL BUS INTERFACE ■ Normal Access and Address/Data Multiplex Access A chip select area set with the following setting for the access type (TYP[3:0] bits) of ACR0 to ACR4 registers becomes the area either for normal access or address/data multiplex access operation. Table 9.2-9 Access Type TYP3 TYP2 TYP1 TYP0 Access type 0 0 X X Normal access (Asynchronous SRAM, I/O, ROM/Flash) 0 1 X X Address data multiplex access (8/16-bit bus width only) The functions of each bit in AWR0 to AWR3 for a normal access and address/data multiplex access area are shown below. Since the initial values of the registers other than AWR0 are undefined, set them before enabling each area by CSER register. [bit15 to bit12] W15 to W12: First access wait cycle These bits set the number of auto-wait cycles to be inserted into the first access cycle for each cycle. For cycles except burst access cycle, only this wait setting is used. The CS0 area is set to its initial value 7 (wait). The initial values of other areas are undefined. Table 9.2-10 First Access Wait Cycle W15 W14 W13 W12 First access wait cycle 0 0 0 0 Auto-wait cycle 0 0 0 0 1 Auto-wait cycle 1 ... 1 1 ... 1 1 Auto-wait cycle 15 [bit11 to bit8] W11 to W08: Inpage access wait cycle These bits set the number of auto-wait cycles of inpage access in burst access. These bits are valid only in burst access cycle. Table 9.2-11 Inpage Access Wait Cycle W11 W10 W09 W08 Inpage access wait cycle 0 0 0 0 Auto-wait cycle 0 0 0 0 1 Auto-wait cycle 1 ... 1 1 ... 1 1 Auto-wait cycle 15 Even if the same value is set to both first access wait cycle and inpage access wait cycle, the access time from the address in each access cycle is not the same (since the inpage access cycle includes address output delay). 232 CHAPTER 9 EXTERNAL BUS INTERFACE [bit7, bit6] W07, W06: Read → Write idle cycle The read → write idle cycle is set to prevent collision of read data and write data on the data bus when a write cycle follows a read cycle. During an idle cycle, all chip select signals are negated and the data pins maintain the Hi-Z state. If a write cycle follows a read cycle or an access operation to another chip select area occurs after a read cycle, the specified idle cycle is inserted. Table 9.2-12 Read → Write Idle Cycle Read → Write idle cycle W07 W06 0 0 0 cycle 0 1 1 cycle 1 0 2 cycles 1 1 3 cycles [bit5, bit4] W05, W04: Write recovery cycle The write recovery cycle is set to control the access to a device if the device has a limit for the access interval period after a write access. During a write recovery cycle, all chip select signals are negated and the data pins maintain the high impedance state. If the write recovery cycle is set to "1" or more, one or more write recovery cycles are always inserted after a write access. Table 9.2-13 Write Recovery Cycle W05 W04 Write recovery cycle 0 0 0 cycle 0 1 1 cycle 1 0 2 cycles 1 1 3 cycles 233 CHAPTER 9 EXTERNAL BUS INTERFACE [bit3] W03: WR1X, WR0X output timing selection The WR1X, WR0X output timing setting is used to select whether to use a write strobe output as an asynchronous strobe or as a synchronous write enable. Use it as an asynchronous strobe to support normal memory I/O, and use it as a synchronous enable to support clock synchronous memory I/O (such as ASIC built-in memory). Table 9.2-14 WR1X, WR0X Output Timing Selection W03 WR1X, WR0X output timing selection 0 SYSCLK synchronous write enable output (Valid from ASX="L") 1 Asynchronous write strobe output (Normal operation) When selecting synchronous write enable (AWR:W03 bit is "0"), its operations are described as follows: • Synchronous write enable output timing is the timing based on the assumption that the output is captured at the rising edge of the SYSCLK output of external memory access clock. The timing is different from that of asynchronous strobe output. • The WR1X, WR0X pin output asserts the synchronous write enable output from the timing when ASX pin output is asserted. When writing to external bus, the synchronous write enable output outputs "L". When reading from external bus, the synchronous write enable output outputs "H". • Write data is outputted from the external data output pin in the next cycle of the cycle in which a synchronous write enable output is asserted. • The read strobe output (RDX) functions as an asynchronous read strobe regardless of the WR1X, WR0X output timing setting. Use it for data I/O direction control as it is. • When using the synchronous write enable output, the following restrictions are applied: • Do not set the following additional wait settings: - CSX → RDX/WR1X,WR0X setup setting (Always write "0" for AWR:W01 bit.) - First access wait cycle setting (Always write "0000B" for AWR:W15 to W12 bits.) • Do not set the following access type settings (TYP[3:0] bits (bit[3:0]) of ACR register): - Setting that uses WR1X and WR0X as write strobes (Always write "0" for ACR:TYP1 bit.) - Address/data multiplex bus setting (Always write "0" for ACR:TYP2 bit.) - RDY input enable setting (Always write "0" for ACR:TYP0 bit.) • When using synchronous write enable output, always set the burst length to "1" (set "00B" for ACR:BST[1:0] bits). 234 CHAPTER 9 EXTERNAL BUS INTERFACE [bit2] W02: Address → CSX delay The address → CSX delay setting is set when a certain setup is required for the address when CSX falls, or when CSX edges are needed even for consecutive accesses to the same chip select area. Set the delay of CS0X to CS4X output from address or ASX output. Table 9.2-15 Address → CSX Delay Address → CSX delay W02 0 No delay 1 Delay If no delay is selected by setting "0", assertion of CS0X to CS4X starts at the same timing that ASX is asserted. If, at this point, consecutive accesses are made to the same chip select area, assertion of CS0X to CS4X may continue during both access operations without change. If delay is specified by selecting "1", assertion of CS0X to CS4X starts when the external memory clock SYSCLK output rises. If, at this point, consecutive accesses are made to the same chip select area, CS0X to CS4X negate timing occurs during both access operations. If CSX delay is selected, one setup cycle is inserted before asserting the read/write strobe after assertion of the delayed CSX (operation is the same as the CSX → RDX/WR1X,WR0X setup setting of W01). [bit1] W01: CSX → RDX/WR1X,WR0X setup extension cycle The CSX → RDX/WR1X,WR0X setup extension cycle is set to extend the period before the read/write strobe is asserted after CSX is asserted. At least one setup extension cycle is inserted before the read/ write strobe is asserted after CSX is asserted. Table 9.2-16 CSX → RDX/WR1X,WR0X Setup Extension Cycle CSX → RDX/WR1X,WR0X setup extension cycle W01 0 0 cycle 1 1 cycle If 0 cycle is selected by setting "0", RDX/WR1X,WR0X are outputted, at the fastest, from the rising of external memory clock SYSCLK output right after CSX assertion. Depending on the internal bus condition, WR0X and WR1X may be delayed one or more cycles. If 1 cycle is selected by setting "1", RDX/WR1X,WR0X are outputted with delay of one or more cycles. When making consecutive accesses within the same chip select area without negating CSX, this setup extension cycle is not inserted. If a setup extension cycle for determining the address is required, enable W02 bit and insert the address → CSX delay so that CSX is once negated for each access operation and this setup extension cycle is enabled. If CSX delay setting of W02 is inserted, this setup cycle becomes valid regardless of the W01 bit setting. 235 CHAPTER 9 EXTERNAL BUS INTERFACE [bit0] W00: RDX/WR1X,WR0X → CSX hold extension cycle The RDX/WR1X,WR0X → CSX hold extension cycle is set to extend the period before negating CSX after the read/write strobe is negated. One hold extension cycle is inserted before CSX is negated after the read/ write strobe is negated. Table 9.2-17 RDX/WR1X,WR0X → CSX Hold Extension Cycle RDX/WR1X,WR0X → CSX hold extension cycle W00 0 0 cycle 1 1 cycle If 0 cycle is selected by setting "0", CS0X to CS3X are negated after passing the hold delay from the rising edge of external memory clock SYSCLK output after RDX/WR1X,WR0X are negated. If 1 cycle is selected by setting "1", CS0X to CS4X are negated one cycle later. When making consecutive accesses within the same chip select area without negating CSX, this hold extension cycle is not inserted. If a hold extension cycle for determining the address is required, enable W02 bit and insert the address → CSX delay so that CSX is once negated for each access operation and this hold extension cycle is enabled. 236 CHAPTER 9 EXTERNAL BUS INTERFACE 9.2.4 I/O Wait Register for DMAC (IOWR0 to IOWR2) This section explains the details of I/O wait register. ■ Register Configuration of IOWR0 to IOWR2 Register configuration of IOWR0 to IOWR2 are as follows. Figure 9.2-4 Register Configuration of IOWR0 to IOWR2 IOWR0 bit31 30 29 28 27 0000 0678H RYE0 HLD0 WR01 WR00 IW03 IOWR1 bit23 22 21 20 19 0000 0679H RYE1 HLD1 WR11 WR10 IW13 IOWR2 bit15 14 13 12 11 0000 067AH RYE2 HLD2 WR21 WR20 IW23 26 25 24 IW02 IW01 IW00 18 17 16 IW12 IW11 IW10 10 9 8 IW22 IW21 IW20 Initial value At INIT At RST Access xxxxxxxxB xxxxxxxxB R/W xxxxxxxxB xxxxxxxxB R/W xxxxxxxxB xxxxxxxxB R/W [bit31, bit23, bit15] RYE0, RYE1, RYE2: RDY function setting (ReadY Enable 0, 1, 2) These bits are used to set wait control settings by RDYI for each ch.0 to ch.2 during DMA fly-by access. Table 9.2-18 RDY Function Setting RYEn RDY function setting 0 RDY input for I/O access is disabled 1 RDY input for I/O access is enabled. Setting "1" enables wait insertion by RDYI pin during a fly-by transfer in the corresponding channel. IOWRX and IORDX are extended until RDYI pin is enabled. In synchronization with that extension, RDX/WR1X,WR0X on the memory side are also extended. When RDY enable setting is set for the chip select area of the fly-by transfer target by ACR register, wait insertion by RDYI pin is enabled regardless of RYEn bit of the IOWRX side. Even when RDY disable setting is set for the chip select area of the fly-by transfer target by ACR register, wait insertion by RDYI pin is enabled only for fly-by access if RDY is enabled by RYEn bit of the IOWRX side. If RDY is enabled by fly-by write access to SDRAM, be sure to enable HLD bit before setting the hold wait. 237 CHAPTER 9 EXTERNAL BUS INTERFACE [bit30, bit22, bit14] HLD0, HLD1, HLD2: Hold wait setting These bits are used to control the hold cycle of read strobe signal at the transfer source access side during DMA fly-by access. Table 9.2-19 Hold Wait Setting HLDn Hold wait setting 0 Hold extension cycle is not inserted. 1 Hold extension cycle is inserted to extend read cycle by one cycle When "0" is set, a read strobe signal of the transfer source access side (RDX0 if memory → I/O, or IORDX if I/O → memory) and a write strobe signal (IOWRX if memory → I/O, or WRXO[3:0] or WEX if I/O → memory) are outputted at the same timing. When "1" is set, read strobe signal is outputted "1" cycle longer to the write strobe signal to ensure the hold time for transferring data at transfer source access side to the transfer target. If RDY is enabled by fly-by write access to SDRAM, be sure to enable HLD bit before setting the hold wait. [bit29, bit28, bit21, bit20, bit13, bit12] WR01, WR00, WR11, WR10, WR21, WR20: I/O idle cycle setting These bits are used to set the idle cycle setting for consecutive I/O accesses during DMA fly-by access. Table 9.2-20 I/O Idle Cycle Setting WRn1 WRn0 I/O idle cycle setting 0 0 0 cycle 0 1 1 cycle 1 0 2 cycles 1 1 3 cycles If setting to have one or more idle cycles, idle cycles of the set cycle number are inserted after I/O access during DMA fly-by access. During idle cycle, all CSXs and strobe outputs are negated and data pins become high impedance. 238 CHAPTER 9 EXTERNAL BUS INTERFACE [bit27 to bit24, bit19 to bit16, bit11 to bit8] IW03 to IW00, IW13 to IW10, IW23 to IW20: I/O wait cycle These bits are used to specify the auto-wait cycle in I/O access during DMA fly-by access. Table 9.2-21 I/O Wait Cycle IWn3 IWn2 IWn1 IWn0 I/O wait cycle 0 0 0 0 0 cycle 0 0 0 1 1 cycle ... 1 1 ... 1 1 15 cycles For the number of wait cycles to be inserted, the cycle number set in the IWnn bit setting of the I/O side or the cycle number set in the wait setting of the fly-by transfer target (such as memory), whichever is greater is used for data synchronization between the transfer source and transfer target. For this reason, more wait cycles than the cycle number set in the IWnn bit may be inserted. 239 CHAPTER 9 EXTERNAL BUS INTERFACE 9.2.5 Chip Select Enable Register (CSER) This section explains the details of chip select enable register. ■ Register Configuration of Chip Select Enable Register (CSER) Register configuration of CSER is as follows. Figure 9.2-5 Register Configuration of CSER Address: 0000 0680H bit31 30 29 28 Reserved Reserved Reserved 27 26 25 24 Initial value At INIT At RST CSE4 CSE3 CSE2 CSE1 CSE0 00000001B 00000001B Access R/W This register enables and disables each chip select area. [bit31 to bit29] Reserved: Reserved bits Be sure to set these bits to "000B". [bit28 to bit24] CSE4 to CSE0: Chip select area enable (Chip select enable 0 to 4) These bits are the chip select area enable bits for CS0X to CS4X. The initial value is "00001B", which is enabled only in the CS0 area. When "1" is written, a chip select area operates according to the settings of ASR0 to ASR4, ACR0 to ACR4, and AWR0 to AWR4. Before enabling, be sure to make all settings for the corresponding chip select areas. Table 9.2-22 Area Control CSE4 to CSE0 Area control 0 Disabled 1 Enabled Table 9.2-23 lists CSX corresponding to CSE bit. Table 9.2-23 CSX Corresponding to CSE Bit CSE bit 240 Corresponding CSX Bit [24]:CSE0 CS0X Bit [25]:CSE1 CS1X Bit [26]:CSE2 CS2X Bit [27]:CSE3 CS3X Bit [28]:CSE4 CS4X CHAPTER 9 EXTERNAL BUS INTERFACE 9.2.6 CacHe Enable Register (CHER) This section explains the details of cache enable register. ■ Register Configuration of Cache Enable Register (CHER) Figure 9.2-6 shows the register configuration of CacHe Enable Register (CHER). Figure 9.2-6 Register Configuration of CacHe Enable Register (CHER) Address: 000681H bit23 22 21 20 Reserved Reserved Reserved 19 18 17 16 Initial value At INIT At RST CHE4 CHE3 CHE2 CHE1 CHE0 11111111B 11111111B Access R/W CHER controls capturing the data read from each chip select area into the built-in cache. [bit20 to bit16] CHE4 to CHE0: Cache area setting (Cache Enable 4 to 0) These bits specify to enable or disable cache for each chip select area. Table 9.2-24 Cache Area Setting CHE4 to CHE0 Cache area setting 0 Non-cache area (Data read from this area is not stored in cache.) 1 Cache area (Data read from this area is stored in cache.) 241 CHAPTER 9 EXTERNAL BUS INTERFACE 9.2.7 Terminal and Timing Control Register (TCR) This section explains the details of terminal and timing control register. ■ Register Configuration of Terminal and Timing Control Register (TCR) Figure 9.2-7 Register Configuration of Terminal and Timing Control Register (TCR) Address: bit23 22 21 0000 0683H BREN PSUS PCLR 20 19 18 17 Reserved Reserved Reserved 16 Initial value At INIT At RST RDW1 RDW0 00000000B 0000XXXXB Access R/W The TCR controls functions relating to the external bus interface controller in general such as function settings and timing controls. [bit7] BREN: BRQ input enable setting (BRQ enable) This bit enables BRQ pin input to share an external bus. Table 9.2-25 BRQ Input Enable Setting BREN BRQ input enable setting 0 Bus is not shared by BRQ/BGRNTX. BRQ input is disabled. 1 Bus is shared by BRQ/BGRNTX. BRQ input is enabled. In the initial state ("0"), BRQ input is ignored. When "1" is set, after BRQ input becomes "H", the bus is opened (high impedance control) at the bus opening becomes possible, and BGRNTX is activated ("L" output). [bit6] PSUS: Prefetch suspension (Prefetch SUSpend) This bit controls temporary stop of prefetch to all areas. Table 9.2-26 Prefetch Control PSUS Prefetch control 0 Prefetch enabled 1 Prefetch suspended When "1" is set, a new prefetch operation will not be executed until "0" is written. In this period, contents in a prefetch buffer will not be erased unless any error occurs to the prefetch buffer. Before restarting prefetch, clear the prefetch buffer by using bit5:PCLR bit function. 242 CHAPTER 9 EXTERNAL BUS INTERFACE [bit5] PCLR: Prefetch buffer all clear (Prefetch buffer CleaR) This bit clears all prefetch buffer contents. Table 9.2-27 Prefetch Buffer Control PCLR Prefetch buffer control 0 Normal state 1 Prefetch buffer clear When writing "1", all prefetch buffer contents are cleared once. After buffer clear is completed, the bit value is automatically returned to "0". Set PSUS bit to suspend prefetch (set the bit to "1") before clearing buffer. (You can write "11B" to PSUS and PCLR bits at the same time.) [bit4 to bit2] Reserved: Reserved bits These are reserved bits. Be sure to set "0". [bit1, bit0] RDW[1:0]: Wail cycle reduction (ReDuce Wait cycle) For all chip select areas and I/O channels for fly-by, these bits reduce setting values of automatic access cycle wait only for the auto-wait cycle all at once without changing the setting values of AWR registers. The settings for the idle cycle, recovery cycle, setup cycle and hold cycle are not affected. Table 9.2-28 Wait Cycle Reduction RDW1 RDW0 Wait cycle reduction 0 0 Normal wait (Setting values of AWR0 to AWR4) 0 1 1/2 of the setting values of AWR0 to AWR4 (Right-shifted by 1 bit) 1 0 1/4 of the setting values of AWR0 to AWR4 (Right-shifted by 2 bits) 1 1 1/8 of the setting values of AWR0 to AWR4 (Right-shifted by 3 bits) This function is for preventing the excess access cycle wait during low-speed clock operations, such as while a base clock is low speed or a time division setting of the external bus clock is large. Normally in such a case, you have to rewrite all AWRs to change wait cycle settings. However, by using the RDW[1:0] bit function, only access cycle wait values can be reduced all at once without changing all other AWR settings and so they remain as high-speed clock settings. Be sure to reset RDW[1:0] bits to "00B" before changing the clock setting back to high-speed. 243 CHAPTER 9 EXTERNAL BUS INTERFACE 9.3 Chip Select Area In the external bus interface, a total of five chip select areas can be set. The address space of each area can be set in 4 GB space using ASR0 to ASR4 (Area Select Register) and ACR0 to ACR4 (Area Configuration Register). CS0X to CS4X can be set in the space between "00040000H" and "FFFFFFFFH" in units of 64 Kbytes to 2048 Mbytes. When bus access is made to an area specified by these registers, the corresponding chip select signals CS0X-CS4X become active ("L" output) during the access cycle. ■ Example of Setting ASR and ASZ[1:0] 1. ASR1=0001H ACR1 → ASZ[3:0]=0000B Chip select area 1 is assigned to "00100000H" to "0010FFFFH". 2. ASR2=0040H ACR2 → ASZ[3:0]=0100B Chip select area 2 is assigned to "00400000H" to "004FFFFFH". 3. ASR3=0081H ACR3 → ASZ[3:0]=0111B Chip select area 3 is assigned to "00800000H" to "00FFFFFFH". Since at this point 8 Mbytes is set for ACR → ASZ[3:0], the unit for boundary becomes 8 Mbytes and so ASR3[22:16] are ignored. Before writing to ACR0 is done after a reset, "00000000H" to "FFFFFFFFH" have been assigned to chip select area 0. Note: Set the chip select areas so that there is no overlap. 244 CHAPTER 9 EXTERNAL BUS INTERFACE Figure 9.3-1 shows the chip select area. Figure 9.3-1 Chip Select Area 00000000H 00000000H 00100000H Area 1 64 Kbytes 00400000H Area 2 1 Mbyte Area 0 00800000H 8 Mbytes Area 3 00FFFFFFH FFFFFFFFH FFFFFFFFH 245 CHAPTER 9 EXTERNAL BUS INTERFACE 9.4 Endian and Bus Access There is a one-to-one correspondence between the WR1X,WR0X control signal and the byte location on the data bus regardless of the data bus width. The following summarizes the location of bytes on the data bus used with the specified data bus width and the corresponding control signal for each bus mode. ■ Relation Ship Between Data Bus Width and Control Signal ● Control signal of normal bus interface Figure 9.4-1 shows the control signal of normal bus interface. Figure 9.4-1 Control Signal of Normal Bus Interface a)16-bit bus width Data bus D31 Control signal b) 8-bit bus width Data bus WR0X Control signal WR0X D24 WR1X D16 ● Control signal of Time division I/O interface Figure 9.4-2 shows the control signal of time division I/O interface. Figure 9.4-2 Control Signal of Time Division I/O Interface a)16-bit bus width Data bus D31 D16 246 b) 8-bit bus width Output address Control signal A15 to A08 WR0X A07 to A00 WR1X Data bus Output address A07 to A00 − − Control signal WR0X − CHAPTER 9 EXTERNAL BUS INTERFACE 9.4.1 Big Endian Bus Access MB91461/F467R allows you to switch between big endian and little endian for each chip select except CS0 area. When LEND bit of ACR register is set to "1", the area is treated as little endian. In normal operations, MB91461/F467R executes external bus access using big endian. ■ Data Format of Big Endian The relationship between the internal register and the external data bus is as follows. ● Word access (when LD, ST instruction executed) Figure 9.4-3 Word Access (When LD, ST Instruction Executed) Internal register D31 AA D23 BB D15 External bus D31 AA D23 BB D15 CC D7 DD D0 ● Halfword access (when LDUH, STH instruction executed) Figure 9.4-4 Halfword Access (When LDUH, STH Instruction Executed) a) Output address lower 00 Internal External register bus D31 D31 AA D23 D23 BB D15 D15 AA D7 BB D0 b) Output address lower 10 Internal External register bus D31 D31 AA D23 D23 BB D15 D15 AA D7 BB D0 247 CHAPTER 9 EXTERNAL BUS INTERFACE ● Byte access (when LDUB, STB instruction executed) Figure 9.4-5 Byte Access (When LDUB, STB Instruction Executed) a) Output address lower 00 Internal register D31 D23 b) Output address lower 01 External bus D31 AA D23 Internal register D31 c) Output address lower 10 External bus D31 D31 D23 D23 D23 Internal register External bus D31 AA D23 d) Output address lower 11 Internal register D31 D23 D23 AA D15 D15 D15 D7 AA D15 D15 D7 AA D15 D7 AA D0 D15 D15 D7 AA D0 AA D0 D0 ■ Data Bus Width ● 16-bit bus width Figure 9.4-6 16-bit Bus Width Internal register External bus Output address lower D31 D23 D15 D07 AA Read/Write BB 00 10 AA CC BB DD D31 D23 CC DD ● 8-bit bus width Figure 9.4-7 8-bit Bus Width Internal register External bus Output address lower D31 D23 D15 D07 248 AA BB CC DD Read/Write External bus D31 00 01 10 11 AA BB CC DD D31 CHAPTER 9 EXTERNAL BUS INTERFACE ■ External Bus Access External bus access (16-bit/8-bit bus width) is shown by the access type (word/half word/byte access) in Figure 9.4-8, Figure 9.4-9, Figure 9.4-10. Following are also shown in Figure 9.4-11, Figure 9.4-12, Figure 9.4-13. PA1/PA0 : Output A1/A0 : Lower 2 bits of address specified by program Lower 2 bits of output address : Top byte location of output address + : Data byte location to access (1) to (4) : Bus access count MB91461/F467R does not detect misalignment errors. Therefore, for word access, the lower two bits of the output address are always "00B" regardless of whether the lower two bits of address specified by the program are "00B", "01B", "10B" or "11B". For halfword access, the lower two bits of the output address are "00B" if the lower two bits specified by the program are "00B" or "01B", and are "10B" if "00B" or "01B". ● 16-bit bus width Figure 9.4-8 Word Access (a) PA1/PA0=00B → (1) Output A1/A0=00B (2) Output A1/A0=10B MSB (b) PA1/PA0=01B → (1) Output A1/A0=00B (2) Output A1/A0=10B (c) PA1/PA0=10B (d) PA1/PA0=11B → (1) Output A1/A0=00B → (1) Output A1/A0=00B (2) Output A1/A0=10B (2) Output A1/A0=10B LSB (1) ⇒ 00 01 (1) ⇒ 00 01 (1) ⇒ 00 01 (1) ⇒ 00 01 (2) ⇒ 10 11 (2) ⇒ 10 11 (2) ⇒ 10 11 (2) ⇒ 10 11 16-bit Figure 9.4-9 Half Word Access (a) PA1/PA0=00B → (1) Output A1/A0=00B (b) PA1/PA0=01B → (1) Output A1/A0=00B (c) PA1/PA0=10B (d) PA1/PA0=11B → (1) Output A1/A0=10B → (1) Output A1/A0=10B (1) ⇒ 00 01 (1) ⇒ 00 01 00 01 00 01 10 11 10 11 (1) ⇒ 10 11 (1) ⇒ 10 11 249 CHAPTER 9 EXTERNAL BUS INTERFACE Figure 9.4-10 Byte Access (a) PA1/PA0=00B → (1) Output A1/A0=00B (b) PA1/PA0=01B (c) PA1/PA0=10B → (1) Output A1/A0=01B → (1) Output A1/A0=10B → (1) Output A1/A0=11B (d) PA1/PA0=11B (1) ⇒ 00 01 (1) ⇒ 00 01 00 01 00 01 10 11 10 11 (1) ⇒ 10 11 (1) ⇒ 10 11 ● 8-bit bus width Figure 9.4-11 Word Access (a) PA1/PA0=00B → (1) Output A1/A0=00B (2) Output A1/A0=01B (3) Output A1/A0=10B (4) Output A1/A0=11B MSB (b) PA1/PA0=01B → (1) Output A1/A0=00B (2) Output A1/A0=01B (3) Output A1/A0=10B (4) Output A1/A0=11B (c) PA1/PA0=10B (d) PA1/PA0=11B → (1) Output A1/A0=00B → (1) Output A1/A0=00B (2) Output A1/A0=01B (2) Output A1/A0=01B (3) Output A1/A0=10B (3) Output A1/A0=10B (4) Output A1/A0=11B (4) Output A1/A0=11B LSB (1) ⇒ 00 (1) ⇒ 00 (1) ⇒ 00 (1) ⇒ 00 (2) ⇒ 01 (2) ⇒ 01 (2) ⇒ 01 (2) ⇒ 01 (3) ⇒ 10 (3) ⇒ 10 (3) ⇒ 10 (3) ⇒ 10 (4) ⇒ 11 (4) ⇒ 11 (4) ⇒ 11 (4) ⇒ 11 8-bit Figure 9.4-12 Half Word Access (a) PA1/PA0=00B → (1) Output A1/A0=00B (2) Output A1/A0=01B 250 (b) PA1/PA0=01B → (1) Output A1/A0=00B (2) Output A1/A0=01B (c) PA1/PA0=10B (d) PA1/PA0=11B → (1) Output A1/A0=10B → (1) Output A1/A0=10B (2) Output A1/A0=11B (2) Output A1/A0=11B (1) ⇒ 00 (1) ⇒ 00 00 00 (2) ⇒ 01 (2) ⇒ 01 01 01 10 10 (1) ⇒ 10 (1) ⇒ 10 11 11 (2) ⇒ 11 (2) ⇒ 11 CHAPTER 9 EXTERNAL BUS INTERFACE Figure 9.4-13 Byte Access (a) PA1/PA0=00B → (1) Output A1/A0=00B (b) PA1/PA0=01B → (1) Output A1/A0=01B (c) PA1/PA0=10B (d) PA1/PA0=11B → (1) Output A1/A0=10B → (1) Output A1/A0=11B (1) ⇒ 00 00 00 00 01 (1) ⇒ 01 01 01 10 10 (1) ⇒ 10 10 11 11 11 (1) ⇒ 11 ■ Example of Connection with External Devices Figure 9.4-14 Example of Connection with External Devices FR Core WR0X D31 to D24 WR1X D23 to D16 *: For an 8-bit device, a data bus on the MSB side is used. A23 to A00 A23 to A23 to A01 A00 0 D31 1 D24 D23 0 D16 16-bit device* D31 D24 8-bit device* ("0"/"1" Address lower 1 bit) 251 CHAPTER 9 EXTERNAL BUS INTERFACE 9.4.2 Little Endian Bus Access MB91461/F467R allow you to switch between big endian and little endian for each chip select except CS0 area. When LEND bit of ACR register is set to "1", the area is treated as little endian. By using bus access operations of the big endian, the little endian bus access of MB91461/F467R are realized by swapping data bus byte locations based on the bus width but basically using the same output address order and control signal output as for the big endian. When connecting, caution is demanded because the big endian area and little endian area need to be physically divided. ■ Difference Between Little Endian and Big Endian The followings explain the difference between little endian and big endian. • Output address order is the same for big endian and little endian. • Word access : Byte data on the MSB side corresponding to the big endian address A01,A00=00B becomes the byte data on the LSB side in the little endian. In a word access, all byte locations for the 4 bytes in a word are inverted. • Halfword access : Byte data on the MSB side corresponding to the big endian address A00 becomes the byte data on the LSB side in the little endian. In a halfword access, byte locations for the 2 bytes in a halfword are inverted. • Byte access : Byte locations are the same for big endian and little endian. ■ Restrictions on a Little Endian Area • If prefetch is enabled for a little endian area, be sure to use a word access to access to the area. If the data in a prefetch buffer is accessed with using an access other than word-length access, a correct endian conversion may not be performed and so wrong data will be read. This is due to hardware restrictions of endian conversion mechanism. • Do not set any instruction codes in a little endian area. 252 CHAPTER 9 EXTERNAL BUS INTERFACE ■ Data Format The relationship between the internal register and the external data bus is as follows. ● Word access (when LD, ST instruction executed) Figure 9.4-15 Word Access (When LD, ST Instruction Executed) Internal register D31 AA D23 BB D15 External bus D31 BB DD AA CC D23 D15 CC D7 DD D0 ● Halfword access (when LDUH, STH instruction executed) Figure 9.4-16 Halfword Access (When LDUH, STH Instruction Executed) a) Output address lower 00 Internal External register bus D31 D31 BB D23 D23 AA D15 D15 AA D7 BB D0 b) Output address lower 10 Internal External register bus D31 D31 BB D23 D23 AA D15 D15 AA D7 BB D0 ● Byte access (when LDUB, STB instruction executed) Figure 9.4-17 Byte Access (When LDUB, STB Instruction Executed) a) Output address lower 00 Internal register D31 D23 External bus D31 AA D23 b) Output address lower 01 Internal register D31 c) Output address lower 10 External bus D31 D31 D23 D23 D23 Internal register External bus D31 AA D23 d) Output address lower 11 Internal register D31 D23 D23 AA D15 D15 D7 D15 D0 AA D15 D7 AA D15 D15 D7 AA D0 External bus D31 D15 D7 AA D0 D15 AA D0 253 CHAPTER 9 EXTERNAL BUS INTERFACE ■ Data Bus Width ● 16-bit bus width Figure 9.4-18 16-bit Bus Width Internal register External bus Output address lower D31 D23 D15 D07 AA Read/Write BB 00 10 DD BB CC AA D31 D23 CC DD ● 8-bit bus width Figure 9.4-19 8-bit Bus Width Internal register External bus Output address lower D31 D23 D15 D07 254 AA BB CC DD Read/Write 00 01 10 11 DD CC BB AA D31 CHAPTER 9 EXTERNAL BUS INTERFACE ■ Example of Connection with External Devices ● 16-bit bus width Figure 9.4-20 16-bit Bus Width FR Core WR0X D31 to D24 WR1X D23 to D16 0 1 D31 D24 D23 Big Endian Area A31 to A01 1 D16 D31 0 D24 D23 D16 Little Endian Area 255 CHAPTER 9 EXTERNAL BUS INTERFACE ● 8-bit bus width Figure 9.4-21 8-bit Bus Width FR Core WR0X D31 to D24 D31 D24 Big Endian Area 256 A31 to A00 D31 D24 Little Endian Area CHAPTER 9 EXTERNAL BUS INTERFACE 9.4.3 Comparison Of External Accesses In Big Endian and Little Endian This section shows a comparison of big endian and little endian external access in word access, halfword access, and byte access for each bus width. These figures show that all the accesses become big endian in the internal register if an area is divided into a big endian area and a little endian area and the data bus is connected according to the examples for connecting to external devices shown in "9.4.1 Big Endian Bus Access" and "9.4.2 Little Endian Bus Access". ■ Word Access Table 9.4-1 Word Access (1 / 2) Bus width Big endian mode Little endian mode Internal register External pin Control pin Internal register External pin Control pin D31 address: "0" D31 AA BB D16 D31 WR0X address: "0" D31 BB AA WR1X D16 AA WR1X AA BB BB D00 D00 (1) (1) 16-bit bus width Internal register External pin Control pin D31 WR0X address: "2" D31 CC DD D16 Internal register External pin Control pin D31 WR0X address: "2" D31 DD CC WR1X D16 CC WR0X WR1X CC DD DD D00 D00 (1) (1) 257 CHAPTER 9 EXTERNAL BUS INTERFACE Table 9.4-1 Word Access (2 / 2) Bus width Big endian mode Little endian mode Internal register External pin Control pin Internal register External pin Control pin address: "0" "1" D31 D31 BB AA WR0X D24 D31 address: "0" "1" D31 AA BB D24 WR0X AA AA BB BB D00 D00 D00 (1) (1) (2) 8-bit bus width Internal register External pin Control pin address: "2" "3" D31 D31 CC DD WR0X D24 CC DD D00 (2) Internal register External pin Control pin address: "2" "3" D31 D31 DD CC WR0X D24 CC DD D00 D00 (1) (2) 258 D00 D00 (1) (2) CHAPTER 9 EXTERNAL BUS INTERFACE ■ Byte Access Table 9.4-2 Byte Access (1 / 2) Bus width Big endian mode Little endian mode Internal register External pin Control pin address: "0" D31 D31 AA WR0X Internal register External pin Control pin D31 address: "0" D31 AA WR0X D16 D16 AA AA D00 D00 (1) (1) Internal register External pin Control pin address: "1" D31 D31 BB D16 Internal register External pin Control pin address: "1" D31 D31 BB WR1X D16 WR1X BB BB D00 D00 (1) 16-bit bus width (1) Internal register External pin Control pin address: "2" D31 D31 CC WR0X Internal register External pin Control pin address: "2" D31 D31 CC WR0X D16 D16 CC CC D00 D00 (1) (1) Internal register External pin Control pin address: "3" D31 D31 Internal register External pin Control pin address: "3" D31 D31 DD D16 DD WR1X D16 DD WR1X DD D00 D00 (1) (1) 259 CHAPTER 9 EXTERNAL BUS INTERFACE Table 9.4-2 Byte Access (2 / 2) Bus width Big endian mode Little endian mode Internal register External pin Control pin address: "0" D31 D31 AA WR0X D24 Internal register External pin Control pin address: "0" D31 D31 AA WR0X D24 AA AA D00 D00 (1) (1) Internal register External pin Control pin address: "1" D31 D31 BB WR0X D24 Internal register External pin Control pin D31 D24 BB WR0X BB D00 D00 (1) 8-bit bus width Internal register External pin Control pin address: "2" D31 D31 CC WR0X D24 (1) Internal register External pin Control pin D31 CC address: "2" D31 CC D24 WR0X CC D00 D00 (1) (1) Internal register External pin Control pin address: "3" D31 D31 DD WR0X D24 Internal register External pin Control pin address: "3" D31 D31 DD WR0X D24 DD DD D00 D00 (1) 260 address: "1" D31 BB (1) CHAPTER 9 EXTERNAL BUS INTERFACE 9.5 Normal Bus Interface For normal bus interface, two clock cycles are the basic bus cycle for both read access and write access. ■ Basic Timing (for Consecutive Accesses) (TYP[3:0]=0000B, AWR=0008H) Figure 9.5-1 shows the basic timing for consecutive accesses. Figure 9.5-1 Basic Timing for Consecutive Accesses SYSCLK A23 to A00 #2 #1 ASX CS4X to CS0X RDX Read D31 to D16 #1 #2 WR1X, WR0X Write D31 to D16 #1 #2 261 CHAPTER 9 EXTERNAL BUS INTERFACE • ASX is asserted for one cycle in the bus access start cycle. • A[23:00] output the address of the location of the start byte in word/halfword/byte access from the bus access start cycle to the bus access end cycle. • If W02 bit of the AWR0 to AWR4 registers is "0", CS0X to CS3X are asserted at the same timing as ASX. For consecutive accesses, CS0X to CS4X are not negated. If W00 bit of the AWR register is "0", CS0X to CS4X are negated after the bus cycle ends. If the W00 bit is "1", CS0X to CS4X are negated after one cycle after bus access ends. • RDX, WR0X and WR1X are asserted from the 2nd cycle of the bus access. Negation occurs after the wait cycle of bits W15 to W12 of the AWR register is inserted. The timing of asserting RDX, WR0X and WR1X can be delayed by one cycle by setting W01 bit of the AWR register to "1". • For read access, D[31:16] are read when SYSCLK rises in the cycle in which the wait cycle ended after RDX was asserted. • For write access, data output to D[31:16] starts at the timing at which WR0X and WR1X are asserted. 262 CHAPTER 9 EXTERNAL BUS INTERFACE ■ Read → Write Timing (TYP[3:0]=0000B, AWR=0048H) Figure 9.5-2 shows read → write timing. Figure 9.5-2 Read → Write Timing Read Idle Write SYSCLK A23 to A00 ASX CS4X to CS0X RDX WR1X, WR0X D31 to D16 • Setting of W06 bits of the AWR register enables an insertion of 0 or 1 idle cycle. • Settings in the CS area on the read side are enabled. • This idle cycle is inserted if the next access after a read access is a write access or an access to another area. 263 CHAPTER 9 EXTERNAL BUS INTERFACE ■ Write → Write Timing (TYP[3:0]=0000B, AWR=0018H) Figure 9.5-3 shows write → write timing. Figure 9.5-3 Write → Write Timing Write Write recovery Write SYSCLK A23 to A00 ASX CS4X to CS0X WR1X, WR0X D31 to D16 • Setting of W04 bits of the AWR register enables an insertion of 0 or 1 write recovery cycle. • After all write cycles, recovery cycles are generated. • Write recovery cycles are also generated if a write access is divided by a access with the bus width wider than that specified. 264 CHAPTER 9 EXTERNAL BUS INTERFACE ■ Auto-wait Timing (TYP[3:0]=0000B, AWR=2008H) Figure 9.5-4 shows the auto-wait timing. Figure 9.5-4 Auto-Wait Timing Basic cycle Wait cycle SYSCLK A23 to A00 ASX CS4X to CS0X RDX Read D31 to D16 WR1X, WR0X Write D31 to D16 • Setting of W15 to W12 bits (first wait cycle) of the AWR register enables 0 to 15 auto-wait cycles to be set. • In the figure above, two auto-wait cycles are inserted, making a total of four cycles access. If auto-wait is set, the minimum number of bus cycles is 2 cycles + (first wait cycles). For a write operation, the minimum number of bus cycles may become longer depending on the internal state. 265 CHAPTER 9 EXTERNAL BUS INTERFACE ■ External Wait Timing (TYP[3:0]=0001B, AWR=2008H) Figure 9.5-5 shows external wait timing. Figure 9.5-5 External Wait Timing Basic cycle Auto-wait 2 cycles Wait cycle by RDY SYSCLK A23 to A00 ASX CS4X to CS0X RDX Read D31 to D16 WR1X, WR0X Write D31 to D16 RDY Cancel Wait Setting "1" for TYP0 bit of the ACR register to enable the external RDY input pin enables an insertion of the external wait cycle. In the figure above, because waiting using the auto-wait cycle is enabled, the section of the RDY pin indicated by hatching is disabled. The value of the RDY input pin is evaluated after the last cycle of the auto-wait cycle. Also, after a wait cycle is completed, the value of the RDY input pin is disabled until the next access cycle starts. 266 CHAPTER 9 EXTERNAL BUS INTERFACE ■ CSX Delay Setting (TYP[3:0]=0000B, AWR=000CH) Figure 9.5-6 shows the CSX delay setting. Figure 9.5-6 CSX Delay Setting SYSCLK A23 to A00 ASX CS4X to CS0X RDX Read D31 to D16 WR1X, WR0X Write D31 to D16 267 CHAPTER 9 EXTERNAL BUS INTERFACE ■ CSX → RDX/WR1X,WR0X Setup and RDX/WR1X,WR0X → CSX Hold Setting (TYP[3:0]=0000B, AWR=000BH) Figure 9.5-7 shows CSX → RDX/WR1X,WR0X setup and RDX/WR1X,WR0X → CSX hold settings. Figure 9.5-7 CSX → RDX/WR1X,WR0X Setup and RDX/WR1X,WR0X → CSX Hold Settings SYSCLK A23 to A00 ASX CS4X to CS0X CSX->RDX/WR1X,WR0X Delay RDX/WR1X,WR0X->CSX Delay RDX Read D31 to D16 WR1X, WR0X Write D31 to D16 • Setting "1" for W01 bit of the AWR register enables the CSX → RDX/WR1X,WR0X setup delay to be set. Set this bit to extend the period after chip select assertion until read/write strobe. • Setting "1" for W00 bit of the AWR register enables the RDX/WR1X,WR0X → CSX hold delay to be set. Set this bit to extend the period after read/write strobe negation until chip select negation. • The CSX → RDX/WR1X,WR0X setup delay (W01 bit) and RDX/WR1X,WR0X → CSX hold delay (W00 bit) can be set independently. • When making consecutive accesses within the same chip select area without negating the chip select, neither a CSX → RDX/WR1X,WR0X setup delay nor an RDX/WR1X,WR0X → CSX hold delay is inserted. • If a setup cycle from determining the address or a hold cycle for determining the address is needed, set "1" for the address → CSX delay setting (W02 bit of the AWR register). 268 CHAPTER 9 EXTERNAL BUS INTERFACE 9.6 Address/Data Multiplex Interface This section explains setting of the address/data multiplex interface. ■ Without External Wait (TYP[3:0]=0100B, AWR=0008H) Figure 9.6-1 shows the setting for the address/data multiplex interface with no external wait. Figure 9.6-1 Setting for the Address/Data Multiplex Interface without External Wait SYSCLK Address[23:0] A23 to A00 ASX CS4X to CS0X RDX Read D31 to D16 Address[15:0] Data [15:0] WR1X, WR0X Write D31 to D16 Address[15:0] Data[15:0] 269 CHAPTER 9 EXTERNAL BUS INTERFACE • Setting the ACR register to TYP[3:0]=01XXB enables the address/data multiplex interface to be set. • If the address/data multiplex interface is set, set 8-bit or 16-bit for the data bus width (DBW[1:0] bit). 32-bit width is not supported. • In the address/data multiplex interface, the total of 3 cycles of 2 address output cycles + 1 data cycle become the basic access cycle. • In the address output cycles, ASX is asserted as a output address latch enable signal. However, when CSX → RDX/WR1X,WR0X setup delay (AWR:W01) is set to "0", the multiplex address output cycle becomes one cycle only as shown in the figure above and the address cannot be directly latched at the rising edge of ASX. Therefore, fetch the address at the rising edge of SYSCLK of the cycle in which "L" is asserted to ASX. If you want to set the address to be directly latched at the rising edge of ASX, see "■ Setting of CSX → RDX/WR1X,WR0X Setup (TYP[3:0]=0101B, AWR=100BH)". • As with a normal interface, the address indicating the start of access is outputted to A[23:00] during the time division bus cycle. Use this setting if you want to use an address of 8/16 bits or more in the address/data multiplex interface. • As with the normal interface, auto-wait (AWR:W14 to AWR:W12), read → write idle cycle (AWR:W06), write recovery (AWR:W04), address → CSX delay (AWR:W02), CSX → RDX/ WR1X,WR0X setup delay (AWR:W01), and RDX/WR1X,WR0X → CSX hold delay (AWR:W00) can be set. 270 CHAPTER 9 EXTERNAL BUS INTERFACE ■ With External Wait (TYP[3:0]=0101B, AWR=1008H) Figure 9.6-2 shows the setting for the address/data multiplex interface with external wait. Figure 9.6-2 Setting for the Address/Data Multiplex Interface with External Wait SYSCLK Address[23:0] A23 to A00 ASX CS4X to CS0X RDX Read D31 to D16 Data [15:0] Address[15:0] WR1X, WR0X Write D31 to D16 Address[15:0] Data[15:0] RDY Setting the ACR register to TYP[3:0]=01X1B enables RDY input in the address/data multiplex interface. 271 CHAPTER 9 EXTERNAL BUS INTERFACE ■ Setting of CSX → RDX/WR1X,WR0X Setup (TYP[3:0]=0101B, AWR=100BH) Figure 9.6-3 shows setting of CSX → RDX/WR1X,WR0X setup. Figure 9.6-3 Setting of CSX → RDX/WR1X,WR0X Setup SYSCLK A23 to A00 Address[23:0] ASX CS4X to CS0X RDX Read D31 to D16 Address[15:0] Data [15:0] Address[15:0] Data[15:0] WR1X, WR0X Write D31 to D16 Setting "1" for the CSX → RDX/WR1X,WR0X setup delay (AWR:W01) enables the multiplex address output cycle to be extended by one cycle as shown in the above figure, allowing the address to be latched directly at the rising edge of ASX. Use this setting if you want to use ASX as an ALE (Address Latch Enable) strobe without using SYSCLK. 272 CHAPTER 9 EXTERNAL BUS INTERFACE 9.7 DMA Access This section explains setting of DMA access. ■ 2-cycle Transfer (The Timing is the Same as for Internal RAM → External I/O, RAM, External I/O, RAM → Internal RAM.) (TYP[3:0]=0000B, AWR=0008H) Figure 9.7-1 shows the setting of 2-cycle transfer. * When a wait is not set on the I/O side. Figure 9.7-1 Setting of 2-Cycle Transfer SYSCLK A23 to A00 I/O address ASX CS4X to CS0X (I/O side) WR1X, WR0X D31 to D16 Bus access is the same as that of the interface for non-DMA transfer. 273 CHAPTER 9 EXTERNAL BUS INTERFACE ■ 2-cycle Transfer (External → I/O) (TYP[3:0]=0000B, AWR=0008H) Figure 9.7-2 shows the setting of 2-cycle transfer (external → I/O). * When a wait is not set on the memory and I/O. Figure 9.7-2 Setting of 2-Cycle Transfer (External → I/O) MCLK A23 to A00 Memory address Idle I/O address ASX CS4X to CS0X RDX CS4X to CS0X WR1X, WR0X D31 to D16 Bus access is the same as that of the interface for non-DMAC transfer. 274 CHAPTER 9 EXTERNAL BUS INTERFACE ■ 2-cycle Transfer (I/O → External) (TYP[3:0]=0000B, AWR=0008H) Figure 9.7-3 shows the setting of 2-cycle transfer (I/O → external). * When a wait is not set on the memory and I/O. Figure 9.7-3 Setting of 2-Cycle Transfer (I/O → External) MCLK A23 to A00 I/O address Idle Memory address ASX CS4X to CS0X WR1X, WR0X CS4X to CS0X RDX D31 to D16 Bus access is the same as that of the interface for non-DMAC transfer. 275 CHAPTER 9 EXTERNAL BUS INTERFACE 9.8 Procedure for Setting Registers For setting procedure concerning with external bus interface, follow the principle described below. ■ Procedure for Setting External Bus Interface 1) Before rewriting the contents of a register, be sure to set the CSER register so that the corresponding area is not used ("0"). If you change the settings while "1" is set, access before and after the change cannot be guaranteed. 2) Use the following procedure to change a register: (1) Set "0" for the CSER bit corresponding to the applicable area. (2) Set both ASR and ACR at the same time using word access. To access to ASR and ACR using half word access, set ACR after setting ASR. (3) Set AWR. (4) Set the CSER bit corresponding to the applicable area. 3) The CS0X area is enabled after a reset is released. If the area is used as a program area, the register contents need to be rewritten while the CSER bit is "1". In this case, make the settings described in 2) and 3) above in the initial state with a low-speed internal clock. Then, switch the clock to a highspeed clock. 276 CHAPTER 10 I/O PORT This chapter describes I/O ports and the configuration and functions of the registers. 10.1 Overview of I/O Ports 10.2 Port Input Enable 10.3 I/O Port Data Register 10.4 Setting of Port Function Register 10.5 Selection of Pin Input Level 10.6 Pull-up and Pull-down Control Register 277 CHAPTER 10 I/O PORT 10.1 Overview of I/O Ports This section provides an overview of the I/O ports. ■ Basic Block Diagram of the I/O Port MB91461/F467R can be used as an I/O port if settings are made so that the external bus interfaces or peripherals corresponding to pins do not use the pins as input/output pins. Figure 10.1-1 shows the basic configuration of the I/O port. 278 CHAPTER 10 I/O PORT Figure 10.1-1 Basic Block Diagram of the I/O Port Port bus PILR EPILR External bus interface input Peripheral input CMOS PDRD read & Automotive & PDRD 0 CLKP CMOS hysteresis 1 & STOP or GPORTEN PDR read PPER PPCR Output driver 1. Peripheral output 2. Peripheral output P-ch Pull-up / down control Pin Output MUX PDR N-ch DDR PFR port direction control EPFR PODR PDR: PDRD: DDR: PFR: EPFR: PILR: EPILR: PPER: PPCR: Port data register Port data direct read register Data direction register Port function register Extra PFR port function register Port input level selection register Port input level selection register Port pull-up/-down enable register Port pull-up/-down control register Address 000H + PDR + #port (Port 00: 000H, port 01: 001H, etc.) Address = PDR + D00H Address = PDR + D40H Address = PDR + D80H Address = PDR + DC0H Address = PDR + E40H Address = PDR + E80H Address = PDR + EC0H Address = PDR + F00H 279 CHAPTER 10 I/O PORT ■ General Specification of Ports The following rules apply to all ports. • As for the port input, to prevent the penetration current being generated before the setting of the port with software, all initial values are set. After setting each port pin based on its function, the port input must be enabled using the global port enable (PORTEN.GPORTEN). See "10.2 Port Input Enable". (MB91461 is not provided with this register.) • For each port, the port data direct read register (PDRD) that samples pin data with CLKP is provided. This register is read only. • For each port, the data direction register (DDR) that switches port input/output direction is provided. All the ports become input (DDR=00H) after reset. - Port input mode (PFR = 0 and DDR = 0) PDRD read: Sampled pin data is read. PDR read: Sampled pin data is read. PDR write: PDR setting value is written. No effect on the pin value. - Port output mode (PFR = 0 and DDR = 1) PDRD read: Sampled pin data is read. PDR read: PDR register value is read. PDR write: PDR setting value is written to the corresponding external pin. • When a read-modify-write (RMW) instruction (bit operation) is executed, the PDR register always becomes read regardless of the data direction register (DDR). • The port function register (PFR) and the extra port function register (EPFR) is provided in a specified port. To enable the function determined by EPFR=1, PFR=1 also must be set. On MB91461, the operation with EPFR=1 and PFR=0 settings is the same as the one in the port input/output mode (reserved for future use). • For each port, the port input level register (PILR) that inputs the input level (CMOS hysteresis/ Automotive [/TTL]) bitwise is provided. The initial value differs for each port function. The input level can be set in any device mode. See "Table 10.5-2 Pin Input Level Selection Register Setting for MB91461". • A pull-up resistor and a pull-down resistor (50 kΩ) that are enabled by its own pull-up/pull-down enable register (PPER) and pull-up/pull-down control register (PPCR) bitwise are provided in a specified port. See "10.6 Pull-up and Pull-down Control Register". • For each port, one or two port function registers PFRs and (if needed) one extra PFR (EPFR) are provided. By combining together, they operate as up to 3 resource I/Os per pin. See "10.4 Setting of Port Function Register". • The port setting that is controlled by MD[2:0] pin and by the mode register MODR overwrites the setting in the port register. For example, the external bus mode overwrites the port register setting. External bus signal output can be disabled by setting the PFR of a pin to the port mode (PFR=0). • A resource input line is normally connected to a pin and is enabled by setting the appropriate function in the resource. There are some exceptions as shown in "10.4 Setting of Port Function Register". • An external interrupt input line is always connected to a pin and is enabled at the external interrupt unit. • In the STOP mode (with STCR:STOP setting and with no STCR:HIZ setting), all pins maintain its own state (input or output based on the setting before becoming STOP mode) and the input stages and lines are fixed internally to avoid crossing current. If the corresponding pin is set by using PFR = 1 setting and the corresponding external interrupt is enabled in the ENIR0 and ENIR1 registers, an external interrupt input pin is not fixed. Pull-up and pull-down are enabled. 280 CHAPTER 10 I/O PORT • In the STOP-HIZ mode (with STCR:STOP and STCR:HIZ settings), all pins are switched to input (high impedance state) and all the input stages and lines are fixed internally to avoid fluctuations. If the corresponding pin is set by using PFR = 1 setting and the corresponding external interrupt is enabled in the ENIR0 and ENIR1 registers, an external interrupt pin is not fixed. Pull-up and pull-down are disabled. • Resource output lines are enabled by setting the corresponding PFR/EPFR bits in the port. For details, see "10.4 Setting of Port Function Register". In addition, the LIN-UART output (SOT) must be enabled by setting the SOE bit in LIN-UART control. • Resource bidirectional signals (SCK of LIN-UART, etc.) are enabled by setting the corresponding PFR/ EPFR bits in the port. Signal direction is controlled by the resource settings such as the output enable bit. For details, see "10.4 Setting of Port Function Register". Notes: There is no register switched between general-purpose port input and peripheral input. The value input via an external pin is always passed to the general-purpose port and peripheral circuit. Even with the DDR output setting, the value output to the outside is always propagated to the general-purpose port and peripheral circuit. For use as a peripheral input, use DDR input and enable each peripheral’s input signal. 281 CHAPTER 10 I/O PORT 10.2 Port Input Enable This section describes the port input enable function. ■ PORTEN: Port Input Enable PORTEN Addrress bit7 6 5 4 3 2 1 0 initial 0498H - - - - - - CPORTEN GPORTEN ---- --00B - - - - - - R/W R/W All port inputs are disabled by initial value to avoid transverse current floating in the I/O input stages and the subsequent logic. After configuring all ports according to their functional specification (input level, output drive, pull-up or pull-down resistor, etc.) it is mandatory to globally enable the inputs by setting the port input enable bit. This register is not provided on MB91461. On MB91461, each port becomes the input enable state after reset. MB91V460 doesn't have this register either. Only MB91F467R has this register. Please set "1" to GPORTEN and CPORTEN when you use the port input function with MB91F467R. GPORTEN "0" - The inputs of all ports are disabled. "1" - The inputs of all ports are enabled. CPORTEN "0" - The inputs of the bootloader communication ports are disabled. "1" - The inputs of the bootloader communication ports are enabled. 282 CHAPTER 10 I/O PORT 10.3 I/O Port Data Register This section shows the port data register (PDR), data direction register (DDR) and port data direct read register (PDRD). ■ Port Data Register (PDR) This register stores output data of each port. Figure 10.3-1 The Configuration of Port Data Register (PDR) PDR00 PDR01 PDR05 PDR06 PDR07 PDR08 PDR09 PDR10 PDR11 PDR13 PDR14 PDR15 PDR16 PDR17 PDR18 PDR19 PDR20 PDR21 PDR22 PDR23 PDR24 PDR28 PDR29 Address 000000H 000001H 000005H 000006H 000007H 000008H 000009H 00000AH 00000BH 00000DH 00000EH 00000FH 000010H 000011H 000012H 000013H 000014H 000015H 000016H 000017H 000018H 00001CH 00001DH bit7 6 5 4 3 2 1 0 Initial value PDR00_7 PDR00_6 PDR00_5 PDR00_4 PDR00_3 PDR00_2 PDR00_1 PDR00_0 XXXXXXXXB PDR01_7 PDR01_6 PDR01_5 PDR01_4 PDR01_3 PDR01_2 PDR01_1 PDR01_0 XXXXXXXXB PDR05_7 PDR05_6 PDR05_5 PDR05_4 PDR05_3 PDR05_2 PDR05_1 PDR05_0 XXXXXXXXB PDR06_7 PDR06_6 PDR06_5 PDR06_4 PDR06_3 PDR06_2 PDR06_1 PDR06_0 XXXXXXXXB PDR07_7 PDR07_6 PDR07_5 PDR07_4 PDR07_3 PDR07_2 PDR07_1 PDR07_0 XXXXXXXXB PDR08_7 PDR08_6 PDR08_5 PDR08_4 − − − − − − PDR08_1 PDR08_0 PDR09_4 PDR09_3 PDR09_2 PDR09_1 PDR09_0 PDR10_6 PDR10_5 PDR10_4 PDR10_3 PDR10_2 PDR10_1 PDR10_0 − − − − − − − − − − − − − − PDR14_3 PDR14_2 PDR14_1 PDR14_0 − − − − PDR15_3 PDR15_2 PDR15_1 PDR15_0 PDR16_7 − − − − − PDR11_1 PDR11_0 PDR13_2 PDR13_1 PDR13_0 − − − PDR17_7 PDR17_6 PDR17_5 PDR17_4 PDR17_3 PDR17_2 PDR17_1 PDR17_0 − − − − − PDR18_2 PDR18_1 PDR18_0 − PDR19_6 PDR19_5 PDR19_4 − PDR19_2 PDR19_1 PDR19_0 − PDR20_6 PDR20_5 PDR20_4 − PDR20_2 PDR20_1 PDR20_0 − PDR21_6 PDR21_5 PDR21_4 − PDR21_2 PDR21_1 PDR21_0 PDR22_7 PDR22_6 PDR22_5 PDR22_4 PDR22_3 PDR22_2 − PDR23_6 − − PDR22_0 PDR23_4 PDR23_3 PDR23_2 PDR23_1 PDR23_0 PDR24_7 PDR24_6 PDR24_5 PDR24_4 PDR24_3 PDR24_2 PDR24_1 PDR24_0 − − − PDR28_4 PDR28_3 PDR28_2 PDR28_1 PDR28_0 PDR29_7 PDR29_6 PDR29_5 PDR29_4 PDR29_3 PDR29_2 PDR29_1 PDR29_0 R/W R/W R/W R/W R/W R/W R/W XXXX--XXB ---XXXXXB -XXXXXXXB ------XXB -----XXXB ----XXXXB ----XXXXB X-------B XXXXXXXXB -----XXXB -XXX-XXXB -XXX-XXXB -XXX-XXXB XXXXXX-XB -X-XXXXXB XXXXXXXXB ---XXXXXB XXXXXXXXB R/W PDR00 to PDR13 and PDR28_7 to PDR28_5 are not provided on MB91461. 283 CHAPTER 10 I/O PORT ■ Data Direction Register (DDR) This register sets I/O direction of each port. All ports become input mode after a reset. Figure 10.3-2 The Configuration of Data Direction Register (DDR) DDR00 DDR01 DDR05 DDR06 DDR07 DDR08 DDR09 DDR10 DDR11 DDR13 DDR14 DDR15 DDR16 DDR17 DDR18 DDR19 DDR20 DDR21 DDR22 DDR23 DDR24 DDR28 DDR29 Address 000D40H 000D41H 000D45H 000D46H 000D47H 000D48H 000D49H 000D4AH 000D4BH 000D4DH 000D4EH 000D4FH 000D50H 000D51H 000D52H 000D53H 000D54H 000D55H 000D56H 000D57H 000D58H 000D5CH 000D5DH bit7 6 5 4 3 2 1 0 DDR00_7 DDR00_6 DDR00_5 DDR00_4 DDR00_3 DDR00_2 DDR00_1 DDR00_0 DDR01_7 DDR01_6 DDR01_5 DDR01_4 DDR01_3 DDR01_2 DDR01_1 DDR01_0 DDR05_7 DDR05_6 DDR05_5 DDR05_4 DDR05_3 DDR05_2 DDR05_1 DDR05_0 DDR06_7 DDR06_6 DDR06_5 DDR06_4 DDR06_3 DDR06_2 DDR06_1 DDR06_0 DDR07_7 DDR07_6 DDR07_5 DDR07_4 DDR07_3 DDR07_2 DDR07_1 DDR07_0 DDR08_7 DDR08_6 DDR08_5 DDR08_4 - - - - - DDR08_1 DDR08_0 DDR09_4 DDR09_3 DDR09_2 DDR09_1 DDR09_0 DDR10_6 DDR10_5 DDR10_4 DDR10_3 DDR10_2 DDR10_1 DDR10_0 - - - - - - - - - - - - - - DDR14_3 DDR14_2 DDR14_1 DDR14_0 - - - - DDR15_3 DDR15_2 DDR15_1 DDR15_0 DDR16_7 - - - - - DDR11_1 DDR11_0 DDR13_2 DDR13_1 DDR13_0 - - - DDR17_7 DDR17_6 DDR17_5 DDR17_4 DDR17_3 DDR17_2 DDR17_1 DDR17_0 - - DDR18_2 DDR18_1 DDR18_0 - DDR19_6 DDR19_5 DDR19_4 - - - - DDR19_2 DDR19_1 DDR19_0 - DDR20_6 DDR20_5 DDR20_4 - DDR20_2 DDR20_1 DDR20_0 - DDR21_6 DDR21_5 DDR21_4 - DDR21_2 DDR21_1 DDR21_0 DDR22_7 DDR22_6 DDR22_5 DDR22_4 DDR22_3 DDR22_2 - DDR23_6 - - DDR22_0 DDR23_4 DDR23_3 DDR23_2 DDR23_1 DDR23_0 DDR24_7 DDR24_6 DDR24_5 DDR24_4 DDR24_3 DDR24_2 DDR24_1 DDR24_0 - - - DDR28_4 DDR28_3 DDR28_2 DDR28_1 DDR28_0 DDR29_7 DDR29_6 DDR29_5 DDR29_4 DDR29_3 DDR29_2 DDR29_1 DDR29_0 R/W R/W R/W R/W R/W R/W R/W R/W DDR00 to DDR13 and DDR28_7 to DDR28_5 are not provided on MB91461. 284 Initial value 00000000B 00000000B 00000000B 00000000B 00000000B 0000--00B ---00000B -0000000B ------00B -----000B ----0000B ----0000B 0-------B 00000000B -----000B -000-000B -000-000B -000-000B 000000-0B -0-00000B 00000000B ---00000B 00000000B CHAPTER 10 I/O PORT ■ Port Data Direct Read Register (PDRD) This register is a read-only register and is used to read the input value directly even if the port is in an output state. Figure 10.3-3 The Configuration of Input Port Direct Read Register (PDRD) PDRD00 PDRD01 PDRD05 PDRD06 PDRD07 PDRD08 PDRD09 PDRD10 PDRD11 PDRD13 PDRD14 PDRD15 PDRD16 PDRD17 PDRD18 PDRD19 PDRD20 PDRD21 PDRD22 PDRD23 PDRD24 PDRD28 PDRD29 Address 000D00H 000D01H 000D05H 000D06H 000D07H 000D08H 000D09H 000D0AH 000D0BH 000D0DH 000D0EH 000D0FH 000D10H 000D11H 000D12H 000D13H 000D14H 000D15H 000D16H 000D17H 000D18H 000D1CH 000D1DH bit7 6 5 4 3 2 1 0 PDRD00_7 PDRD00_6 PDRD00_5 PDRD00_4 PDRD00_3 PDRD00_2 PDRD00_1 PDRD00_0 PDRD01_7 PDRD01_6 PDRD01_5 PDRD01_4 PDRD01_3 PDRD01_2 PDRD01_1 PDRD01_0 PDRD05_7 PDRD05_6 PDRD05_5 PDRD05_4 PDRD05_3 PDRD05_2 PDRD05_1 PDRD05_0 PDRD06_7 PDRD06_6 PDRD06_5 PDRD06_4 PDRD06_3 PDRD06_2 PDRD06_1 PDRD06_0 PDRD07_7 PDRD07_6 PDRD07_5 PDRD07_4 PDRD07_3 PDRD07_2 PDRD07_1 PDRD07_0 PDRD08_7 PDRD08_6 PDRD08_5 PDRD08_4 - - - - - PDRD08_1 PDRD08_0 PDRD09_4 PDRD09_3 PDRD09_2 PDRD09_1 PDRD09_0 PDRD10_6 PDRD10_5 PDRD10_4 PDRD10_3 PDRD10_2 PDRD10_1 PDRD10_0 - - - - - - - - - - - - - - PDRD14_3 PDRD14_2 PDRD14_1 PDRD14_0 - - - - PDRD15_3 PDRD15_2 PDRD15_1 PDRD15_0 PDRD16_7 - - - - - PDRD11_1 PDRD11_0 PDRD13_2 PDRD13_1 PDRD13_0 - - - PDRD17_7 PDRD17_6 PDRD17_5 PDRD17_4 PDRD17_3 PDRD17_2 PDRD17_1 PDRD17_0 - - PDRD18_2 PDRD18_1 PDRD18_0 - PDRD19_6 PDRD19_5 PDRD19_4 - - - - PDRD19_2 PDRD19_1 PDRD19_0 - PDRD20_6 PDRD20_5 PDRD20_4 - PDRD20_2 PDRD20_1 PDRD20_0 - PDRD21_6 PDRD21_5 PDRD21_4 - PDRD21_2 PDRD21_1 PDRD21_0 PDRD22_7 PDRD22_6 PDRD22_5 PDRD22_4 PDRD22_3 PDRD22_2 - PDRD23_6 - - PDRD22_0 PDRD23_4 PDRD23_3 PDRD23_2 PDRD23_1 PDRD23_0 PDRD24_7 PDRD24_6 PDRD24_5 PDRD24_4 PDRD24_3 PDRD24_2 PDRD24_1 PDRD24_0 - - - PDRD28_4 PDRD28_3 PDRD28_2 PDRD28_1 PDRD28_0 PDRD29_7 PDRD29_6 PDRD29_5 PDRD29_4 PDRD29_3 PDRD29_2 PDRD29_1 PDRD29_0 R R R R R R R Initial value XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXX--XXB ---XXXXXB -XXXXXXXB ------XXB -----XXXB ----XXXXB ----XXXXB X-------B XXXXXXXXB -----XXXB -XXX-XXXB -XXX-XXXB -XXX-XXXB XXXXXX-XB -X-XXXXXB XXXXXXXXB ---XXXXXB XXXXXXXXB R PDR00 to PDR13 and PDR28_7 to PDR28_5 are not provided on MB91461. 285 CHAPTER 10 I/O PORT 10.4 Setting of Port Function Register This section explains the function of port function register. ■ Port 00 Port 00 is controlled by PFR00. When the PFR00 is "0", this port is used as a general-purpose port, and when it is "1", this port becomes an external bus pin (data pin). Figure 10.4-1 Configuration of Control Register (Port 00) PFR00 Address bit7 6 5 4 3 2 1 0 Initial value 000D80H PFR00_7 PFR00_6 PFR00_5 PFR00_4 PFR00_3 PFR00_2 PFR00_1 PFR00_0 11111111B R/W R/W R/W R/W R/W R/W R/W R/W Table 10.4-1 Function of Control Register (Port 00) Bit name PFR00_7 PFR00_6 PFR00_5 PFR00_4 PFR00_3 PFR00_2 PFR00_1 PFR00_0 286 Value Function 0B External pin is used as a general-purpose port (P00_7). 1B External pin is used as an external bus pin (D31). 0B External pin is used as a general-purpose port (P00_6). 1B External pin is used as an external bus pin (D30). 0B External pin is used as a general-purpose port (P00_5). 1B External pin is used as an external bus pin (D29). 0B External pin is used as a general-purpose port (P00_4). 1B External pin is used as an external bus pin (D28). 0B External pin is used as a general-purpose port (P00_3). 1B External pin is used as an external bus pin (D27). 0B External pin is used as a general-purpose port (P00_2). 1B External pin is used as an external bus pin (D26). 0B External pin is used as a general-purpose port (P00_1). 1B External pin is used as an external bus pin (D25). 0B External pin is used as a general-purpose port (P00_0). 1B External pin is used as an external bus pin (D24). CHAPTER 10 I/O PORT ■ Port 01 Port 01 is controlled by PFR01. When the PFR01 is "0", this port is used as a general-purpose port, and when it is "1", this port becomes an external bus pin (data pin). Figure 10.4-2 Configuration of Control Register (Port 01) PFR01 Address bit7 6 5 4 3 2 1 0 Initial value 000D81H PFR01_7 PFR01_6 PFR01_5 PFR01_4 PFR01_3 PFR01_2 PFR01_1 PFR01_0 11111111B R/W R/W R/W R/W R/W R/W R/W R/W Table 10.4-2 Function of Control Register (Port 01) Bit name PFR01_7 PFR01_6 PFR01_5 PFR01_4 PFR01_3 PFR01_2 PFR01_1 PFR01_0 Value Function 0B External pin is used as a general-purpose port (P01_7). 1B External pin is used as an external bus pin (D23). 0B External pin is used as a general-purpose port (P01_6). 1B External pin is used as an external bus pin (D22). 0B External pin is used as a general-purpose port (P01_5). 1B External pin is used as an external bus pin (D21). 0B External pin is used as a general-purpose port (P01_4). 1B External pin is used as an external bus pin (D20). 0B External pin is used as a general-purpose port (P01_3). 1B External pin is used as an external bus pin (D19). 0B External pin is used as a general-purpose port (P01_2). 1B External pin is used as an external bus pin (D18). 0B External pin is used as a general-purpose port (P01_1). 1B External pin is used as an external bus pin (D17). 0B External pin is used as a general-purpose port (P01_0). 1B External pin is used as an external bus pin (D16). 287 CHAPTER 10 I/O PORT ■ Port 05 Port 05 is controlled by PFR05. When the PFR05 is "0", this port is used as a general-purpose port, and when it is "1", this port becomes an external bus pin (address pin). Figure 10.4-3 Configuration of Control Register (Port 05) PFR05 Address bit7 6 5 4 3 2 1 0 Initial value 000D85H PFR05_7 PFR05_6 PFR05_5 PFR05_4 PFR05_3 PFR05_2 PFR05_1 PFR05_0 11111111B R/W R/W R/W R/W R/W R/W R/W R/W Table 10.4-3 Function of Control Register (Port 05) Bit name PFR05_7 PFR05_6 PFR05_5 PFR05_4 PFR05_3 PFR05_2 PFR05_1 PFR05_0 288 Value Function 0B External pin is used as a general-purpose port (P05_7). 1B External pin is used as an external bus pin (A23). 0B External pin is used as a general-purpose port (P05_6). 1B External pin is used as an external bus pin (A22). 0B External pin is used as a general-purpose port (P05_5). 1B External pin is used as an external bus pin (A21). 0B External pin is used as a general-purpose port (P05_4). 1B External pin is used as an external bus pin (A20). 0B External pin is used as a general-purpose port (P05_3). 1B External pin is used as an external bus pin (A19). 0B External pin is used as a general-purpose port (P05_2). 1B External pin is used as an external bus pin (A18). 0B External pin is used as a general-purpose port (P05_1). 1B External pin is used as an external bus pin (A17). 0B External pin is used as a general-purpose port (P05_0). 1B External pin is used as an external bus pin (A16). CHAPTER 10 I/O PORT ■ Port 06 Port 06 is controlled by PFR06. When the PFR06 is "0", this port is used as a general-purpose port, and when it is "1", this port becomes an external bus pin (address pin). Figure 10.4-4 Configuration of Control Register (Port 06) PFR06 Address bit7 6 5 4 3 2 1 0 Initial value 000D86H PFR06_7 PFR06_6 PFR06_5 PFR06_4 PFR06_3 PFR06_2 PFR06_1 PFR06_0 11111111B R/W R/W R/W R/W R/W R/W R/W R/W Table 10.4-4 Function of Control Register (Port 06) Bit name PFR06_7 PFR06_6 PFR06_5 PFR06_4 PFR06_3 PFR06_2 PFR06_1 PFR06_0 Value Function 0B External pin is used as a general-purpose port (P06_7). 1B External pin is used as an external bus pin (A15). 0B External pin is used as a general-purpose port (P06_6). 1B External pin is used as an external bus pin (A14). 0B External pin is used as a general-purpose port (P06_5). 1B External pin is used as an external bus pin (A13). 0B External pin is used as a general-purpose port (P06_4). 1B External pin is used as an external bus pin (A12). 0B External pin is used as a general-purpose port (P06_3). 1B External pin is used as an external bus pin (A11). 0B External pin is used as a general-purpose port (P06_2). 1B External pin is used as an external bus pin (A10). 0B External pin is used as a general-purpose port (P06_1). 1B External pin is used as an external bus pin (A9). 0B External pin is used as a general-purpose port (P06_0). 1B External pin is used as an external bus pin (A8). 289 CHAPTER 10 I/O PORT ■ Port 07 Port 07 is controlled by PFR07. When the PFR07 is "0", this port is used as a general-purpose port, and when it is "1", this port becomes an external bus pin (address pin). Figure 10.4-5 Configuration of Control Register (Port 07) PFR07 Address bit7 6 5 4 3 2 1 0 Initial value 000D87H PFR07_7 PFR07_6 PFR07_5 PFR07_4 PFR07_3 PFR07_2 PFR07_1 PFR07_0 11111111B R/W R/W R/W R/W R/W R/W R/W R/W Table 10.4-5 Function of Control Register (Port 07) Bit name PFR07_7 PFR07_6 PFR07_5 PFR07_4 PFR07_3 PFR07_2 PFR07_1 PFR07_0 290 Value Function 0B External pin is used as a general-purpose port (P07_7). 1B External pin is used as an external bus pin (A7). 0B External pin is used as a general-purpose port (P07_6). 1B External pin is used as an external bus pin (A6). 0B External pin is used as a general-purpose port (P07_5). 1B External pin is used as an external bus pin (A5). 0B External pin is used as a general-purpose port (P07_4). 1B External pin is used as an external bus pin (A4). 0B External pin is used as a general-purpose port (P07_3). 1B External pin is used as an external bus pin (A3). 0B External pin is used as a general-purpose port (P07_2). 1B External pin is used as an external bus pin (A2). 0B External pin is used as a general-purpose port (P07_1). 1B External pin is used as an external bus pin (A1). 0B External pin is used as a general-purpose port (P07_0). 1B External pin is used as an external bus pin (A0). CHAPTER 10 I/O PORT ■ Port 08 Port 08 is controlled by PFR08. When the PFR08 is "0", this port is used as a general-purpose port, and when it is "1", this port becomes an external bus pin (bus control pin). Figure 10.4-6 Configuration of Control Register (Port 08) PFR08 Address bit7 6 5 4 3 2 1 0 Initial value 000D88H PFR08_7 PFR08_6 PFR08_5 PFR08_4 PFR08_3 PFR08_2 PFR08_1 PFR08_0 11111111B R/W R/W R/W R/W R/W R/W R/W R/W Table 10.4-6 Function of Control Register (Port 08) Bit name PFR08_7 PFR08_6 PFR08_5 PFR08_4 PFR08_1 PFR08_0 Value Function 0B External pin is used as a general-purpose port (P08_7). 1B External pin is used as an external bus pin (RDY). 0B External pin is used as a general-purpose port (P08_6). 1B External pin is used as an external bus pin (BRQ). 0B External pin is used as a general-purpose port (P08_5). 1B External pin is used as an external bus pin (BGRNTX). 0B External pin is used as a general-purpose port (P08_4). 1B External pin is used as an external bus pin (RDX). 0B External pin is used as a general-purpose port (P08_1). 1B External pin is used as an external bus pin (WR1X). 0B External pin is used as a general-purpose port (P08_0). 1B External pin is used as an external bus pin (WR0X). 291 CHAPTER 10 I/O PORT ■ Port 09 Port 09 is controlled by PFR09. When the PFR09 is "0", this port is used as a general-purpose port, and when it is "1", this port becomes an external bus pin (chip select pin). Figure 10.4-7 Configuration of Control Register (Port 09) PFR09 Address 000D89H bit7 - 6 - 5 - 4 3 2 1 R/W R/W R/W R/W Table 10.4-7 Function of Control Register (Port 09) Bit name PFR09_4 PFR09_3 PFR09_2 PFR09_1 PFR09_0 292 Value 0 Initial value PFR09_4 PFR09_3 PFR09_2 PFR09_1 PFR09_0 ---11111B Function 0B External pin is used as a general-purpose port (P09_4). 1B External pin is used as an external bus pin (CS4X). 0B External pin is used as a general-purpose port (P09_3). 1B External pin is used as an external bus pin (CS3X). 0B External pin is used as a general-purpose port (P09_2). 1B External pin is used as an external bus pin (CS2X). 0B External pin is used as a general-purpose port (P09_1). 1B External pin is used as an external bus pin (CS1X). 0B External pin is used as a general-purpose port (P09_0). 1B External pin is used as an external bus pin (CS0X). R/W CHAPTER 10 I/O PORT ■ Port 10 Port 10 is controlled by PFR10 and EPFR10. When the PFR10 is "0", this port is used as a general-purpose port, and when it is "1", this port becomes an external bus pin (bus control pin). Figure 10.4-8 Configuration of Control Register (Port 10) Address PFR10 000D8AH EPFR10 000DCAH bit7 - 6 5 4 3 2 1 0 Initial value PFR10_6 PFR10_5 PFR10_4 PFR10_3 PFR10_2 PFR10_1 PFR10_0 -1111111B - - − R/W EPFR10_5 EPFR10_4 R/W R/W - - - EPFR10_0 R/W R/W R/W R/W --00---0B Table 10.4-8 Function of Control Register (Port 10) Bit name PFR10_6 Value 0B External pin is used as a general-purpose port (P10_6). 1B External pin is used as an external bus pin (MCLKE). 00B PFR10_5/EPFR10_5(*) 01B PFR10_3 PFR10_2 PFR10_1 External pin is used as an external bus pin (MCLKI). 11B External pin is used as an external bus pin (MCLKI reverse input). 01B External pin is used as a general-purpose port (P10_4). 10B External pin is used as an external bus pin (MCLKO). 11B External pin is used as an external bus pin (MCLKO reverse input). 0B External pin is used as a general-purpose port (P10_3). 1B External pin is used as an external bus pin (WEX). 0B External pin is used as a general-purpose port (P10_2). 1B External pin is used as an external bus pin (BAAX). 0B External pin is used as a general-purpose port (P10_1). 1B External pin is used as an external bus pin (ASX). 00B PFR10_0/EPFR10_0 External pin is used as a general-purpose port (P10_5). 10B 00B PFR10_4/EPFR10_4 Function 01B External pin is used as a general-purpose port (P10_0). 10B External pin is used as an external bus pin (SYSCLK). 11B External pin is used as an external bus pin (SYSCLK reverse input). (*) Please set PFR10_5 to "0" when not using SDRAM with MB91F467R. (recommendation) 293 CHAPTER 10 I/O PORT ■ Port 11 Port 11 is controlled by PFR11. When the PFR11 is "0", this port is used as a general-purpose port, and when it is "1", this port becomes an external bus pin (DMA control pin). Figure 10.4-9 Configuration of Control Register (Port 11) PFR11 Address 000D8BH bit7 - 6 - 5 - 4 - 3 - 2 - 1 R/W Table 10.4-9 Function of Control Register (Port 11) Bit name PFR11_1 PFR11_0 294 Value 0 PFR11_1 PFR11_0 Function 0B External pin is used as a general-purpose port (P11_1). 1B External pin is used as a DMA control pin (IOWRX). 0B External pin is used as a general-purpose port (P11_0). 1B External pin is used as a DMA control pin (IORDX). R/W Initial value ------00B CHAPTER 10 I/O PORT ■ Port 13 Port 13 is controlled by PFR13 and EPFR13. When the PFR13 is "0", this port is used as a general-purpose port, and when it is "1", this port becomes an external bus pin (DMA control pin). Figure 10.4-10 Configuration of Control Register (Port 13) Address PFR13 000D8DH EPFR13 000DCDH bit7 6 5 4 3 - - - - - PFR13_2 PFR13_1 PFR13_0 2 1 0 - - - - - EPFR13_2 - - − − − − − R/W R/W R/W Initial value -----000B -----0--B Table 10.4-10 Function of Control Register (Port 13) Bit name Value 00B PFR13_2/EPFR13_2 PFR13_1 PFR13_0 01B Function External pin is used as a general-purpose port (P13_2). 10B External pin is used as a DMA control pin (DEOTX0 input). 11B External pin is used as a DMA control pin (DEOP0 output). 0B External pin is used as a general-purpose port (P13_1). 1B External pin is used as a DMA control pin (DACK0X output). 0B External pin is used as a general-purpose port (P13_0). 1B External pin is used as a DMA control pin (DREQ0 input). 295 CHAPTER 10 I/O PORT ■ Port 14 Port 14 is controlled by PFR14 and EPFR14. When the corresponding bit of PFR14 is "0", the pin is used as a general-purpose port, and when it is "1", the external pin becomes a peripheral input. Input selection to ICU (Input Capture Unit) is made by a combination of PFR and EPFR. Figure 10.4-11 Configuration of Control Register (Port 14) Address PFR14 000D8EH EPFR14 000DCEH 296 bit7 6 5 4 − − − − PFR14_3 PFR14_2 PFR14_1 PFR14_0 ----0000B 3 − − − − EPFR14_3 EPFR14_2 EPFR14_1 EPFR14_0 − − − − R/W 2 R/W 1 R/W 0 R/W Initial value ----0000B CHAPTER 10 I/O PORT Table 10.4-11 Function of Control Register (Port 14) Bit name Value 00B 01B PFR14_3/EPFR14_3 10B 11B Input is made from the external pin to the following two: • External trigger input of reload timer 3 • External trigger input of PPG3 LSYN output of LIN-UART3 is connected to internal ICU3 input. 00B External pin is used as a general-purpose port (P14_2). * LSYN output of LIN-UART2 is connected to ICU2 input. 10B Input is made from the external pin to the following three: • ICU2 input • External trigger input of reload timer 2 • External trigger input of PPG2 11B Input is made from the external pin to the following two: • External trigger input of reload timer 2 • External trigger input of PPG2 LSYN output of LIN-UART2 is connected to ICU2 input. 00B External pin is used as a general-purpose port (P14_1). * LSYN output of LIN-UART1 is connected to ICU1 input. 01B PFR14_1/EPFR14_1 10B Input is made from the external pin to the following three: • ICU1 input • External trigger input of reload timer 1 • External trigger input of PPG1 11B Input is made from the external pin to the following two: • External trigger input of reload timer 1 • External trigger input of PPG1 LSYN output of LIN-UART1 is connected to ICU1 input. 00B External pin is used as a general-purpose port (P14_0). LSYN output of LIN-UART0 is connected to ICU0 input. 01B PFR14_0/EPFR14_0 External pin is used as a general-purpose port (P14_3). * LSYN output of LIN-UART3 is connected to ICU3 input. Measured LSYN pulse width in LIN communication can be used to detect the baud rate in LIN slave operation. Input is made from the external pin to the following three: • ICU3 input • External trigger input of reload timer 3 • External trigger input of PPG3 01B PFR14_2/EPFR14_2 Function 10B Input is made from the external pin to the following three: • ICU0 input • External trigger input of reload timer 0 • External trigger input of PPG0 11B Input is made from the external pin to the following two: • External trigger input of reload timer 0 • External trigger input of PPG0 LSYN output of LIN-UART0 is connected to ICU0 input. *: Even if a port is selected, reload timer trigger input and PPG trigger input are enabled. 297 CHAPTER 10 I/O PORT ■ Port 15 Port 15 is controlled by PFR15 and EPFR15. When the PFR is "0", this port is used as a general-purpose port, and when it is "1", this port becomes an output pin for peripheral macro (OCU or reload timer). Figure 10.4-12 Configuration of Control Register (Port 15) Address PFR15 000D8FH EPFR15 000DCFH bit7 6 5 4 − − − − PFR15_3 PFR15_2 PFR15_1 PFR15_0 ----0000B 3 − − − − EPFR15_3 EPFR15_2 EPFR15_1 EPFR15_0 − − − − R/W 2 R/W 1 R/W 0 R/W Table 10.4-12 Function of Control Register (Port 15) Bit name PFR15_3/EPFR15_3 PFR15_2/EPFR15_2 PFR15_1/EPFR15_1 PFR15_0/EPFR15_0 298 Value Function 0XB P15_3: External pin is used as a general-purpose port (P15_3). 10B OCU3: External pin is used as OCU3 output. 11B TOT3: External pin is used as reload timer 3 output. 0XB P15_2: External pin is used as a general-purpose port (P15_2). 10B OCU2: External pin is used as OCU2 output. 11B TOT2: External pin is used as reload timer 2 output. 0XB P15_1: External pin is used as a general-purpose port (P15_1). 10B OCU1: External pin is used as OCU1 output. 11B TOT1: External pin is used as reload timer 1 output. 0XB P15_0: External pin is used as a general-purpose port (P15_0). 10B OCU0: External pin is used as OCU0 output. 11B TOT0: External pin is used as reload timer 0 output. Initial value ----0000B CHAPTER 10 I/O PORT ■ Port 16 Port 16 is controlled by PFR16 and EPFR16. Figure 10.4-13 Configuration of Control Register (Port 16) Address PFR16 000D90H EPFR16 000DD0H bit7 6 5 4 PFR16_7 − − − EPFR16_7 − − − R/W − − − 3 2 1 0 − − − − Initial value 0-------B 0-------B Table 10.4-13 Function of Control Register (Port 16) Bit name Value PFR16_7/EPFR16_7 Function 0XB P16_7: External pin is used as a general-purpose port (P16_7). 10B Setting is disabled. 1XB ATGX: External pin is used as ATGX input. * *: When using a peripheral as an input, the input is enabled even a general-purpose port is selected. ■ Port 17 Port 17 is controlled by PFR17. Figure 10.4-14 Configuration of Control Register (Port 17) PFR17 Address bit7 6 5 4 3 2 1 0 Initial value 000D91H PFR17_7 PFR17_6 PFR17_5 PFR17_4 PFR17_3 PFR17_2 PFR17_1 PFR17_0 00000000B R/W R/W R/W R/W R/W R/W R/W R/W Table 10.4-14 Function of Control Register (Port 17) Bit name PFR17_7 PFR17_6 PFR17_5 PFR17_4 PFR17_3 PFR17_2 PFR17_1 PFR17_0 Value 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Function P17_7: External pin is used as a general-purpose port (P17_7). PPG7: Used as PPG output (PPG7). P17_6: External pin is used as a general-purpose port (P17_6). PPG6: Used as PPG output (PPG6). P17_5: External pin is used as a general-purpose port (P17_5). PPG5: Used as PPG output (PPG5). P17_4: External pin is used as a general-purpose port (P17_4). PPG4: Used as PPG output (PPG4). P17_3: External pin is used as a general-purpose port (P17_3). PPG3: Used as PPG output (PPG3). P17_2: External pin is used as a general-purpose port (P17_2). PPG2: Used as PPG output (PPG2). P17_1: External pin is used as a general-purpose port (P17_1). PPG1: Used as PPG output (PPG1). P17_0: External pin is used as a general-purpose port (P17_0). PPG0: Used as PPG output (PPG0). 299 CHAPTER 10 I/O PORT ■ Port 18 Port 18 is controlled by PFR18. Figure 10.4-15 Configuration of Control Register (Port 18) Address PFR18 000D92H EPFR18 000DD2H bit7 6 5 4 3 − − − − − PFR18_2 PFR18_1 PFR18_0 2 1 0 − − − − − EPFR18_2 - - − − − − − R/W R/W R/W Initial value -----000B -----0--B Table 10.4-15 Function of Control Register (Port 18) Bit name PFR18_2/EPFR18_2 PFR18_1 PFR18_0 Value Function 0XB P18_2: External pin is used as a general-purpose port (P18_2). 10B SCK6: Used as SCK of LIN-UART6. When using as SCK, set the I/O setting by SCKE bit of LIN-UART serial mode register. * 11B Setting is disabled. 0B P18_1: External pin is used as a general-purpose port (P18_1). 1B SOT6: Used as SOT of LIN-UART6. When using as SOT output, set SOE bit of LIN-UART serial mode register to "1". 0B P18_0: External pin is used as a general-purpose port (P18_0). 1B SIN6: Used as SIN of LIN-UART6. * *: When using a peripheral as an input, the input is enabled even a general-purpose port is selected. 300 CHAPTER 10 I/O PORT ■ Port 19 Port 19 is controlled by PFR19. Figure 10.4-16 Configuration of Control Register (Port 19) Address PFR19 000D93H EPFR19 000DD3H bit7 6 5 4 3 2 1 0 − PFR19_6 PFR19_5 PFR19_4 − PFR19_2 PFR19_1 PFR19_0 − EPFR19_6 - - − EPFR19_2 EPFR19_1 EPFR19_0 R/W − − R/W R/W R/W R/W Initial value -000-000B -0---0---B R/W Table 10.4-16 Function of Control Register (Port 19) Bit name PFR19_6/EPFR19_6 PFR19_5 PFR19_4 PFR19_2/EPFR19_2 PFR19_1 PFR19_0 Value Function 0XB P19_6: External pin is used as a general-purpose port (P19_6). 10B SCK5: Used as SCK of LIN-UART5. When using as SCK, set the I/O setting by SCKE bit of LIN-UART serial mode register. * 11B Setting is disabled. 0B P19_5: External pin is used as a general-purpose port (P19_5). 1B SOT5: Used as SOT of LIN-UART5. When using as SOT output, set SOE bit of LIN-UART serial mode register to "1". 0B P19_4: External pin is used as a general-purpose port (P19_4). 1B SIN5: Used as SIN of LIN-UART5. X0B P19_2: External pin is used as a general-purpose port (P19_2). 10B SCK4: Used as SCK of LIN-UART4. When using as SCK, set the I/O setting by SCKE bit of LIN-UART serial mode register. * 11B Setting is disabled. 0B P19_1: External pin is used as a general-purpose port (P19_1). 1B SOT4: Used as SOT of LIN-UART4. When using as SOT output, set SOE bit of LIN-UART serial mode register to "1". 0B P19_0: External pin is used as a general-purpose port (P19_0). 1B SIN4: Used as SIN of LIN-UART4. * *: When using a peripheral as an input, the input is enabled even a general-purpose port is selected. 301 CHAPTER 10 I/O PORT ■ Port 20 Port 20 is controlled by PFR20 and EPFR20. Figure 10.4-17 Configuration of Control Register (Port 20) Address PFR20 000D94H EPFR20 000DD4H bit7 6 5 4 3 2 1 0 − PFR20_6 PFR20_5 PFR20_4 − PFR20_2 PFR20_1 PFR20_0 − EPFR20_6 EPFR20_5 EPFR20_4 − EPFR20_2 EPFR20_1 EPFR20_0 − R/W R/W R/W − R/W R/W Initial value -000-000B -000-000B R/W Table 10.4-17 Function of Control Register (Port 20) Bit name PFR20_6/EPFR20_6 PFR20_5/EPFR20_5 PFR20_4/EPFR20_4 PFR20_2/EPFR20_2 PFR20_1/EPFR20_1 PFR20_0/EPFR20_0 Value Function 0XB P20_6: External pin is used as a general-purpose port. 10B SCK3: Used as SCK of LIN-UART3. When using as SCK, set the I/O setting by SCKE bit of LIN-UART serial mode register. *1 11B FRCK3: Used as CK of free-run timer 3. *2 0XB P20_5: External pin is used as a general-purpose port. 10B SOT3: Used as SOT of LIN-UART3. When using as SOT output, set SOE bit of LIN-UART serial mode register to "1". 11B Setting is disabled. 0XB P20_4: External pin is used as a general-purpose port. 10B SIN3: Used as SIN of LIN-UART3. *1 11B Setting is disabled. 0XB P20_2: External pin is used as a general-purpose port. 10B SCK2: Used as SCK of LIN-UART2. When using as SCK, set the I/O setting by SCKE bit of LIN-UART serial mode register. *1 11B FRCK3: Used as CK of free-run timer3. *2 0XB P20_1: External pin is used as a general-purpose port. 10B SOT2: Used as SOT of LIN-UART2. When using as SOT output, set SOE bit of LIN-UART serial mode register to "1". 11B Setting is disabled. 0XB P20_0: External pin is used as a general-purpose port. 10B SIN2: Used as SIN of LIN-UART2. *1 11B Setting is disabled. *1: When using a peripheral as an input, the input is enabled even a general-purpose port is selected. *2: Input clock of free-run timer (FRCKx) is always inputted regardless of PFR and EPFR settings. 302 CHAPTER 10 I/O PORT ■ Port 21 Port 21 is controlled by PFR21 and EPFR21. Figure 10.4-18 Configuration of Control Register (Port 21) Address PFR21 000D95H EPFR21 000DD5H bit7 6 5 4 3 2 1 0 − PFR21_6 PFR21_5 PFR21_4 − PFR21_2 PFR21_1 PFR21_0 − EPFR21_6 EPFR21_5 EPFR21_4 − EPFR21_2 EPFR21_1 EPFR21_0 − R/W R/W R/W − R/W R/W Initial value -000-000B -000-000B R/W Table 10.4-18 Function of Control Register (Port 21) Bit name PFR21_6/EPFR21_6 PFR21_5/EPFR21_5 PFR21_4/EPFR21_4 PFR21_2/EPFR21_2 PFR21_1/EPFR21_1 PFR21_0/EPFR21_0 Value Function 0XB P21_6: External pin is used as a general-purpose port. 10B SCK1: Used as SCK of LIN-UART1. When using as SCK, set the I/O setting by SCKE bit of LIN-UART serial mode register. *1 11B FRCK1: Used as CK of free-run timer 1. *2 0XB P21_5: External pin is used as a general-purpose port. 10B SOT1: Used as SOT of LIN-UART1. When using as SOT output, set SOE bit of LIN-UART serial mode register to "1". 11B Setting is disabled. 0XB P21_4: External pin is used as a general-purpose port. 10B SIN1: Used as SIN of LIN-UART1. *1 11B Setting is disabled. 0XB P21_2: External pin is used as a general-purpose port. 10B SCK0: Used as SCK of LIN-UART0. When using as SCK, set the I/O setting by SCKE bit of LIN-UART serial mode register. *1 11B FRCK0: Used as CK of free-run timer 0. *2 0XB P21_1: External pin is used as a general-purpose port. 10B SOT0: Used as SOT of LIN-UART0. When using as SOT output, set SOE bit of LIN-UART serial mode register to "1". 11B Setting is disabled. 0XB P21_0: External pin is used as a general-purpose port. 10B SIN0: Used as SIN of LIN-UART0. *1 11B Setting is disabled. *1: When using a peripheral as an input, the input is enabled even a general-purpose port is selected. *2: Input clock of free-run timer (FRCKx) is always inputted regardless of PFR and EPFR settings. 303 CHAPTER 10 I/O PORT ■ Port 22 Port 22 is controlled by PFR22. In normal operation, interrupt inputs (INT15, INT14, INT13, and INT12) are inputted regardless of PFR setting. In STOP mode, the input to internal INT input is as follows: • When PFR=0: "0" is inputted to internal INT input by internal STOP mode signal. • When PFR=1: The value of the external pin is inputted to internal INT input. Therefore, for the interrupts used for canceling STOP mode, PFR must be set to "1" before executing STOP mode. For the interrupts not used for canceling STOP mode, some cautions such as setting to inactive by external interrupt registers or setting PFR to "1" and processing by the external pins are needed. Figure 10.4-19 Configuration of Control Register (Port 22) PFR22 Address bit7 6 5 4 3 2 000D96H PFR22_7 PFR22_6 PFR22_5 PFR22_4 PFR22_3 PFR22_2 R/W R/W R/W R/W R/W R/W Table 10.4-19 Function of Control Register (Port 22) Bit name PFR22_7 Value 0 P22_7: External pin is used as a general-purpose port. 1 SCL1: Used as SCL I/O of I2C_1. 0 P22_6: External pin is used as a general-purpose port. INT15: Input to INT15. 1 SDA1: Used as SDA I/O of I2C_1. INT15: Input to INT15. Set "1" when using INT15 for canceling STOP mode. 0 P22_5: External pin is used as a general-purpose port. 1 SCL0: Used as SCL I/O of I2C_0. 0 P22_4: External pin is used as a general-purpose port. INT14: Input to INT14. 1 SDA0: Used as SDA I/O of I2C_0. INT14: Input to INT14. Set "1" when using INT14 for canceling STOP mode. 0 P22_3: External pin is used as a general-purpose port. 1 Setting is disabled. 0 P22_2: External pin is used as a general-purpose port. INT13: Input to INT13. 1 IINT13: Input to INT13. Set "1" when using INT13 for canceling STOP mode. 0 P22_0: External pin is used as a general-purpose port. INT12: Input to INT12. 1 INT12: Input to INT12. Set "1" when using INT12 for canceling STOP mode. PFR22_6 PFR22_5 PFR22_4 PFR22_3 PFR22_2 PFR22_0 304 Function 1 − − 0 Initial value PFR22_0 000000-0B R/W CHAPTER 10 I/O PORT ■ Port 23 Port 23 is controlled by PFR23. In normal operation, interrupt inputs (INT11, INT10, INT9, and INT8) are inputted regardless of PFR setting. In STOP mode, the input to internal INT input is as follows: • When PFR=0: "0" is inputted to internal INT input by internal STOP mode signal. • When PFR=1: The value of the external pin is inputted to internal INT input. Therefore, for the interrupts used for canceling STOP mode, PFR must be set to "1" before executing STOP mode. For the interrupts not used for canceling STOP mode, some cautions such as setting to inactive by external interrupt registers or setting PFR to "1" and processing by the external pins are needed. Figure 10.4-20 Configuration of Control Register (Port 23) PFR23 Address 000D97H bit7 6 5 − PFR23_6 − − R/W − 4 3 2 1 0 Initial value PFR23_4 PFR23_3 PFR23_2 PFR23_1 PFR23_0 -0-00000B R/W R/W R/W R/W R/W Table 10.4-20 Function of Control Register (Port 23) Bit name Value 0 P23_6: External pin is used as a general-purpose port. INT11: Input to INT11. 1 INT11: Input to INT11. Set "1" when using INT11 for canceling STOP mode. 0 P23_4: External pin is used as a general-purpose port. INT10: Input to INT10. 1 INT10: Input to INT10. Set "1" when using INT10 for canceling STOP mode. 0 P23_3: External pin is used as a general-purpose port. 1 TX1: Used as TX of CAN1. 0 P23_2: External pin is used as a general-purpose port. RX1: Input to RX of CAN1. INT9: Input to INT9. 1 RX1: Input to RX of CAN1. INT9: Input to INT9. Set "1" when using INT9 for canceling STOP mode. 0 P23_1: External pin is used as a general-purpose port. 1 TX0: Used as TX of CAN0. 0 P23_0: External pin is used as a general-purpose port. RX0: Input to RX of CAN0. INT8: Input to INT8. 1 X0: Input to RX of CAN0. INT8: Input to INT8. Set "1" when using INT8 for canceling STOP mode. PFR23_6 PFR23_4 PFR23_3 PFR23_2 PFR23_1 Function PFR23_0 305 CHAPTER 10 I/O PORT ■ Port 24 Port 24 is controlled by PFR24. In normal operation, interrupt inputs (INT7, INT6, INT5, INT4, INT3, INT2, INT1 and INT0) are inputted regardless of PFR setting. In STOP mode, the input to internal INT input is as follows: • When PFR=0: "0" is inputted to internal INT input by internal STOP mode signal. • When PFR=1: The value of the external pin is inputted to internal INT input. Therefore, for the interrupts used for canceling STOP mode, PFR must be set to "1" before executing STOP mode. For the interrupts not used for canceling STOP mode, some cautions such as setting to inactive by external interrupt registers or setting PFR to "1" and processing by the external pins are needed. Figure 10.4-21 Configuration of Control Register (Port 24) PFR24 306 Address bit7 6 5 4 3 2 1 0 Initial value 000D98H PFR24_7 PFR24_6 PFR24_5 PFR24_4 PFR24_3 PFR24_2 PFR24_1 PFR24_0 00000000B R/W R/W R/W R/W R/W R/W R/W R/W CHAPTER 10 I/O PORT Table 10.4-21 Function of Control Register (Port 24) Bit name Value Function 0 P24_7: External pin is used as a general-purpose port. INT7: Input to INT7. 1 INT7: Input to INT7. Set "1" when using INT7 for canceling STOP mode. 0 P24_6: External pin is used as a general-purpose port. INT6: Input to INT6. 1 INT6: Input to INT6. Set "1" when using INT6 for canceling STOP mode. 0 P24_5: External pin is used as a general-purpose port. INT5: Input to INT5. 1 SCL2: Used as SCL of I2C_2. INT5: Input to INT5. Set "1" when using INT5 for canceling STOP mode. 0 P24_4: External pin is used as a general-purpose port. INT4: Input to INT4. 1 SDA2: Used as SDA of I2C_2. INT4: Input to INT4. Set "1" when using INT4 for canceling STOP mode. 0 P24_3: External pin is used as a general-purpose port. INT3: Input to INT3. 1 INT3: Input to INT3. Set "1" when using INT3 for canceling STOP mode. 0 P24_2: External pin is used as a general-purpose port. INT2: Input to INT2. 1 INT2: Input to INT2. Set "1" when using INT2 for canceling STOP mode. 0 P24_1: External pin is used as a general-purpose port. INT1: Input to INT1. 1 IINT1: Input to INT1. Set "1" when using INT1 for canceling STOP mode. 0 P24_0: External pin is used as a general-purpose port. INT0: Input to INT0. 1 INT0: Input to INT0. Set "1" when using INT0 for canceling STOP mode. PFR24_7 PFR24_6 PFR24_5 PFR24_4 PFR24_3 PFR24_2 PFR24_1 PFR24_0 307 CHAPTER 10 I/O PORT ■ Port 28 Since port 28 is also used as an input of A/D converter, set the corresponding bit of ADER (analog input enable register) as well as the corresponding bit of PFR28 to "0" to use as a general-purpose port. Figure 10.4-22 Configuration of Control Register (Port 28) MB91461 Address bit PFR28 000D9CH ADERL 0001A2H high byte 7 6 5 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 4 3 2 1 0 Initial value PFR28_4 PFR28_3 PFR28_2 PFR28_1 PFR28_0 00000000B ADE12 ADE11 ADE10 R/W R/W R/W ADE9 R/W ADE8 R/W 00000000B MB91F467R Address bit 7 6 5 4 3 2 1 0 Initial value PFR28 000D9CH PFR28_7 PFR28_6 PFR28_5 PFR28_4 PFR28_3 PFR28_2 PFR28_1 PFR28_0 00000000B ADERL 0001A2H ADE15 ADE14 ADE13 ADE12 ADE11 ADE10 ADE9 ADE8 00000000B high byte R/W R/W R/W R/W R/W R/W R/W R/W Table 10.4-22 Function of Control Register (Port 28) Bit name Value 00B PFR28_7/ ADE15* PFR28_6 / ADE14* PFR28_5 / ADE13* PFR28_4 / ADE12 PFR28_3 / ADE11 PFR28_2 / ADE10 PFR28_1 / ADE9 PFR28_0 / ADE8 01B, 10B P28_7: External pin is used as a general-purpose port. Setting is disabled. 11B AN15: Used as an analog input of A/D converter. 00B P28_6: External pin is used as a general-purpose port. 01B, 10B Setting is disabled. 11B AN14: Used as an analog input of A/D converter. 00B P28_5: External pin is used as a general-purpose port. 01B, 10B Setting is disabled. 11B AN13: Used as an analog input of A/D converter. 00B P28_4: External pin is used as a general-purpose port. 01B, 10B Setting is disabled. 11B AN12: Used as an analog input of A/D converter. 00B P28_3: External pin is used as a general-purpose port. 01B, 10B Setting is disabled. 11B AN11: Used as an analog input of A/D converter. 00B P28_2: External pin is used as a general-purpose port. 01B, 10B Setting is disabled. 11B AN10: Used as an analog input of A/D converter. 00B P28_1: External pin is used as a general-purpose port. 01B, 10B Setting is disabled. 11B AN9: Used as an analog input of A/D converter. 00B P28_0: External pin is used as a general-purpose port. 01B, 10B 11B *: These are applied only for MB91F467R. 308 Function Setting is disabled. AN8: Used as an analog input of A/D converter. CHAPTER 10 I/O PORT ■ Port 29 Since port 29 is also used as an input of A/D converter, set the corresponding bit of ADER (analog input enable register) as well as the corresponding bit of PFR29 to "0" to use as a general-purpose port. Figure 10.4-23 Configuration of Control Register (Port 29) Address bit7 6 5 4 3 2 1 0 Initial value PFR29 000D9DH PFR29_7 PFR29_6 PFR29_5 PFR29_4 PFR29_3 PFR29_2 PFR29_1 PFR29_0 00000000B ADE6 ADE5 ADE4 ADE3 ADE2 ADE1 ADE0 00000000B ADERL 0001A3H ADE7 low_byte R/W R/W R/W R/W R/W R/W R/W R/W Table 10.4-23 Function of Control Register (Port 29) Bit name Value 00B PFR29_7 / ADE7 PFR29_6 / ADE6 PFR29_5 / ADE5 PFR29_4 / ADE4 PFR29_3 / ADE3 PFR29_2 / ADE2 PFR29_1 / ADE1 PFR29_0 / ADE0 01B, 10B Function P29_7: External pin is used as a general-purpose port. Setting is disabled. 11B AN7: Used as an analog input of A/D converter. 00B P29_6: External pin is used as a general-purpose port. 01B, 10B Setting is disabled. 11B AN6: Used as an analog input of A/D converter. 00B P29_5: External pin is used as a general-purpose port. 01B, 10B Setting is disabled. 11B AN5: Used as an analog input of A/D converter. 00B P29_4: External pin is used as a general-purpose port. 01B, 10B Setting is disabled. 11B AN4: Used as an analog input of A/D converter. 00B P29_3: External pin is used as a general-purpose port. 01B, 10B Setting is disabled. 11B AN3: Used as an analog input of A/D converter. 00B P29_2: External pin is used as a general-purpose port. 01B, 10B Setting is disabled. 11B AN2: Used as an analog input of A/D converter. 00B P29_1: External pin is used as a general-purpose port. 01B, 10B Setting is disabled. 11B AN1: Used as an analog input of A/D converter. 00B P29_0: External pin is used as a general-purpose port. 01B, 10B 11B Setting is disabled. AN0: Used as an analog input of A/D converter. 309 CHAPTER 10 I/O PORT 10.5 Selection of Pin Input Level Input level of the pins can be selected by setting registers. ■ Pin Input Level Table 10.5-1 shows the input levels. Table 10.5-1 Input Level VIL VIH CMOS VIL = 0.3 × VDD VIH = 0.7 × VDD CMOS Schmitt trigger 1 VIL = 0.3 × VDD VIH = 0.7 × VDD CMOS Schmitt trigger 2 VIL = 0.2 × VDD VIH = 0.8 × VDD Automotive VIL = 0.5 × VDD VIH = 0.8 × VDD Name ■ Selection of Pin Input Level Selection of input level for each pin is performed using the pin input level selection registers (PILR, EPIRL). Table 10.5-2, Table 10.5-3, Table 10.5-4, Table 10.5-5 and Table 10.5-6 shows the settings of the pin input level selection registers. Table 10.5-2 Pin Input Level Selection Register Setting for MB91461 PILRxy Pin input level 0 [Initial Value] CMOS Schmitt trigger1 1 CMOS Schmitt trigger2 Table 10.5-3 Pin Input Level Selection Register Setting for MB91F467RA (5V Pins) PILRxy EPILRxy Pin input level 0 [Initial Value] 0 [Initial Value] 0 1 Automotive 1 0 CMOS Schmitt trigger2 1 1 Setting is disable. CMOS Schmitt trigger1 The applied pins are 5V withstand voltage pins (pins 2, 3, 119 to 126, 134 to 145, 148 to 160, and 163 to 175). 310 CHAPTER 10 I/O PORT Table 10.5-4 Pin Input Level Selection Register Setting for MB91F467RB (5V Pins) PILRxy EPILRxy Pin input level 0 [Initial Value] 0 [Initial Value] 0 1 Setting is disable. 1 0 Automotive 1 1 CMOS Schmitt trigger2 CMOS Schmitt trigger1 The applied pins are 5V withstand voltage pins (pins 2, 3, 119 to 126, 134 to 145, 148 to 160, and 163 to 175). Table 10.5-5 Pin Input Level Selection Register Setting for MB91F467R (I2C Pins) PILRxy 0 [Initial Value] 1 Pin input level CMOS CMOS Schmitt trigger1 The applied pins are pins 4 to 7, 117, and 118. Table 10.5-6 Pin Input Level Selection Register Setting for MB91F467R (3.3V Pins) PILRxy 0 [Initial Value] 1 Pin input level CMOS CMOS Schmitt trigger2 The applied pins are pins 8 to 10, 15 to 35, 46 to 56, 59 to 72, 75 to 87, and 90 to 113. It doesn't depend on the value of PILR in MB91V460 and it becomes CMOS Schmitt trigger input. (VIL = 0.3 × VDD/VIH = 0.7 × VDD) 311 CHAPTER 10 I/O PORT Figure 10.5-1 The Structure of Selection of Pin Input Level PILR00 PILR01 PILR05 PILR06 PILR07 PILR08 PILR09 PILR10 PILR11 PILR13 PILR14 PILR15 PILR16 PILR17 PILR18 PILR19 PILR20 PILR21 PILR22 PILR23 PILR24 PILR28 PILR29 Address 000E40H 000E41H 000E45H 000E46H 000E47H 000E48H 000E49H 000E4AH 000E4BH 000E4DH 000E4EH 000E4FH 000E50H 000E51H 000E52H 000E53H 000E54H 000E55H 000E56H 000E57H 000E58H 000E5CH 000E5DH bit7 6 5 4 3 2 1 0 Initial value PILR00_7 PILR00_6 PILR00_5 PILR00_4 PILR00_3 PILR00_2 PILR00_1 PILR00_0 00000000B PILR01_7 PILR01_6 PILR01_5 PILR01_4 PILR01_3 PILR01_2 PILR01_1 PILR01_0 00000000B PILR05_7 PILR05_6 PILR05_5 PILR05_4 PILR05_3 PILR05_2 PILR05_1 PILR05_0 00000000B PILR06_7 PILR06_6 PILR06_5 PILR06_4 PILR06_3 PILR06_2 PILR06_1 PILR06_0 00000000B PILR07_7 PILR07_6 PILR07_5 PILR07_4 PILR07_3 PILR07_2 PILR07_1 PILR07_0 00000000B PILR08_7 PILR08_6 PILR08_5 PILR08_4 - - - - - PILR08_1 PILR08_0 0000--00B PILR09_4 PILR09_3 PILR09_2 PILR09_1 PILR09_0 ---00000B PILR10_6 PILR10_5 PILR10_4 PILR10_3 PILR10_2 PILR10_1 PILR10_0 -0000000B PILR11_1 PILR11_0 ------00B - - - - - - - - PILR14_3 PILR14_2 PILR14_1 PILR14_0 - - - - - PILR15_3 PILR15_2 PILR15_1 PILR15_0 PILR16_7 - - - - PILR13_2 PILR13_1 PILR13_0 - - - PILR17_7 PILR17_6 PILR17_5 PILR17_4 PILR17_3 PILR17_2 PILR17_1 PILR17_0 - - - - - PILR18_2 PILR18_1 PILR18_0 - PILR19_6 PILR19_5 PILR19_4 - PILR19_2 PILR19_1 PILR19_0 - PILR20_6 PILR20_5 PILR20_4 - PILR20_2 PILR20_1 PILR20_0 - PILR21_6 PILR21_5 PILR21_4 - PILR21_2 PILR21_1 PILR21_0 PILR22_7 PILR22_6 PILR22_5 PILR22_4 PILR22_3 PILR22_2 - PILR23_6 - - PILR22_0 PILR23_4 PILR23_3 PILR23_2 PILR23_1 PILR23_0 PILR24_7 PILR24_6 PILR24_5 PILR24_4 PILR24_3 PILR24_2 PILR24_1 PILR24_0 - - - PILR28_4 PILR28_3 PILR28_2 PILR28_1 PILR28_0 PILR29_7 PILR29_6 PILR29_5 PILR29_4 PILR29_3 PILR29_2 PILR29_1 PILR29_0 R/W R/W R/W R/W R/W R/W R/W -----000B ----0000B ----0000B 0-------B 00000000B -----000B -000-000B -000-000B -000-000B ----00-0B -0-00000B 00--0000B ---00000B 00000000B R/W PLR00 to PLR13 and PILR28_7 to PILR28_5 are not provided on MB91461. Figure 10.5-2 Extended Pin Input Level Selection Registers Address EPILR14 000E8EH EPILR15 000E8FH EPILR17 000E91H EPILR18 000E92H EPILR19 000E93H EPILR20 000E94H EPILR21 000E95H EPILR22 000E96H EPILR23 000E97H EPILR24 000E98H bit7 6 5 4 − − − − EPILR14_3 EPILR14_2 EPILR14_1 EPILR14_0 − − − − EPILR15_3 EPILR15_2 EPILR15_1 EPILR15_0 − − − − EPILR17_3 EPILR17_2 EPILR17_1 EPILR17_0 − − − − 2 1 0 − EPILR18_2 EPILR18_1 EPILR18_0 − EPILR19_6 EPILR19_5 EPILR19_4 − EPILR19_2 EPILR19_1 EPILR19_0 − EPILR20_6 EPILR20_5 EPILR20_4 − EPILR20_2 EPILR20_1 EPILR20_0 − EPILR21_6 EPILR21_5 EPILR21_4 − EPILR21_2 EPILR21_1 EPILR21_0 − − − − EPILR23_6 − EPILR24_7 EPILR24_6 R/W R/W − EPILR22_3 EPILR22_2 − EPILR22_0 EPILR23_4 EPILR23_3 EPILR23_2 EPILR23_1 EPILR23_0 − − R/W R/W EPILR register is not provided on MB91461. 312 3 EPILR24_3 EPILR24_2 EPILR24_1 EPILR24_0 R/W R/W R/W R/W Initial value ----0000B ----0000B 00000000B -----000B -000-000B -000-000B -000-000B ----00-0B -0-00000B 00--0000B CHAPTER 10 I/O PORT 10.6 Pull-up and Pull-down Control Register The pin has a function that adds the pull-up or pull-down of 50 kΩ. This function can be controlled by software in unit of a bit. ■ Pull-up and Pull-down Control The pull-up and pull-down functions are enabled by the port pull-up and pull-down enable register (PPER), and the pull-up and pull-down are controlled by the port pull-up and pull-down control register (PPCR). The pull-up or pull-down of the pin is automatically disabled in the following conditions: • Port is in the output state. • In STOP mode ■ Port Pull-up and Pull-down Enable Register Table 10.6-1 shows the setting of port pull-up and pull-down enable register. Ports also used as I2C interface and ports also used as A/D converter input do not have pull-up and pulldown controls. Table 10.6-1 Setting of Port Pull-up and Pull-down Enable Register Port pull-up and pull-down enable register Bit PPERxy 0 [Initial value] 1 Pull-up and pull-down are invalid. Pull-up and pull-down are valid. 313 CHAPTER 10 I/O PORT Figure 10.6-1 The Configuration of Port Pull-up and Pull-down Enable Register PPER00 PPER01 PPER05 PPER06 PPER07 PPER08 PPER09 PPER10 PPER11 PPER13 PPER14 PPER15 PPER16 PPER17 PPER18 PPER19 PPER20 PPER21 PPER22 PPER23 PPER24 PPER28 PPER29 Address 000EC0H 000EC1H 000EC5H 000EC6H 000EC7H 000EC8H 000EC9H 000ECAH 000ECBH 000ECDH 000ECEH 000ECFH 000ED0H 000ED1H 000ED2H 000ED3H 000ED4H 000ED5H 000ED6H 000ED7H 000ED8H 000EDCH 000EDDH bit7 5 4 3 2 1 0 PPER01_7 PPER01_6 PPER01_5 PPER01_4 PPER01_3 PPER01_2 PPER01_1 PPER01_0 PPER05_7 PPER05_6 PPER05_5 PPER05_4 PPER05_3 PPER05_2 PPER05_1 PPER05_0 PPER06_7 PPER06_6 PPER06_5 PPER06_4 PPER06_3 PPER06_2 PPER06_1 PPER06_0 PPER07_7 PPER07_6 PPER07_5 PPER07_4 PPER07_3 PPER07_2 PPER07_1 PPER07_0 PPER08_7 PPER08_6 PPER08_5 PPER08_4 - - - - - PPER08_1 PPER08_0 PPER09_4 PPER09_3 PPER09_2 PPER09_1 PPER09_0 PPER10_6 PPER10_5 PPER10_4 PPER10_3 PPER10_2 PPER10_1 PPER10_0 - - - - - - - - - - - - - - PPER14_3 PPER14_2 PPER14_1 PPER14_0 - - - - PPER15_3 PPER15_2 PPER15_1 PPER15_0 PPER16_7 - - - - - PPER11_1 PPER11_0 PPER13_2 PPER13_1 PPER13_0 - - - PPER17_7 PPER17_6 PPER17_5 PPER17_4 PPER17_3 PPER17_2 PPER17_1 PPER17_0 - - - - - PPER18_2 PPER18_1 PPER18_0 - PPER19_6 PPER19_5 PPER19_4 - PPER19_2 PPER19_1 PPER19_0 - PPER20_6 PPER20_5 PPER20_4 - PPER20_2 PPER20_1 PPER20_0 - PPER21_6 PPER21_5 PPER21_4 - PPER21_2 PPER21_1 PPER21_0 - - - - PPER23_6 - PPER24_7 PPER24_6 - - PPER22_3 PPER22_2 - PPER22_0 PPER23_4 PPER23_3 PPER23_2 PPER23_1 PPER23_0 - PPER24_3 PPER24_2 PPER24_1 PPER24_0 PPER28_7 PPER28_6 PPER28_5 PPER28_4 PPER28_3 PPER28_2 PPER28_1 PPER28_0 PPER29_7 PPER29_6 PPER29_5 PPER29_4 PPER29_3 PPER29_2 PPER29_1 PPER29_0 R/W 314 6 PPER00_7 PPER00_6 PPER00_5 PPER00_4 PPER00_3 PPER00_2 PPER00_1 PPER00_0 R/W R/W R/W R/W R/W R/W R/W Initial value 00000000B 00000000B 00000000B 00000000B 00000000B 0000--00B ---00000B -0000000B ------00B -----000B ----0000B ----0000B 0-------B 00000000B -----000B -000-000B -000-000B -000-000B ----00-0B -0-00000B 00--0000B 00000000B 00000000B CHAPTER 10 I/O PORT ■ Port Pull-up and Pull-down Control Register Table 10.6-2 shows the setting of port pull-up and pull-down control register. The set value of each bit is enabled only when the corresponding PPER is set. Ports also used as I2C interface and ports also used as A/D converter input do not have pull-up and pulldown controls. Table 10.6-2 Setting of Port Pull-up and Pull-down Control Register Port pull-up and pull-down control register Bit PPCRxy 0 1 [Initial value] Pull-down Pull-up Figure 10.6-2 The Configuration of Port Pull-up and Pull-down Control Register PPCR00 PPCR01 PPCR05 PPCR06 PPCR07 PPCR08 PPCR09 PPCR10 PPCR11 PPCR13 PPCR14 PPCR15 PPCR16 PPCR17 PPCR18 PPCR19 PPCR20 PPCR21 PPCR22 PPCR23 PPCR24 PPCR28 PPCR29 Address 000F00H 000F01H 000F05H 000F06H 000F07H 000F08H 000F09H 000F0AH 000F0BH 000F0DH 000F0EH 000F0FH 000F10H 000F11H 000F12H 000F13H 000F14H 000F15H 000F16H 000F17H 000F18H 000F1CH 000F1DH bit7 6 5 4 3 2 1 0 PPCR00_7 PPCR00_6 PPCR00_5 PPCR00_4 PPCR00_3 PPCR00_2 PPCR00_1 PPCR00_0 PPCR01_7 PPCR01_6 PPCR01_5 PPCR01_4 PPCR01_3 PPCR01_2 PPCR01_1 PPCR01_0 PPCR05_7 PPCR05_6 PPCR05_5 PPCR05_4 PPCR05_3 PPCR05_2 PPCR05_1 PPCR05_0 PPCR06_7 PPCR06_6 PPCR06_5 PPCR06_4 PPCR06_3 PPCR06_2 PPCR06_1 PPCR06_0 PPCR07_7 PPCR07_6 PPCR07_5 PPCR07_4 PPCR07_3 PPCR07_2 PPCR07_1 PPCR07_0 PPCR08_7 PPCR08_6 PPCR08_5 PPCR08_4 - - - - - PPCR08_1 PPCR08_0 PPCR09_4 PPCR09_3 PPCR09_2 PPCR09_1 PPCR09_0 PPCR10_6 PPCR10_5 PPCR10_4 PPCR10_3 PPCR10_2 PPCR10_1 PPCR10_0 - - - - - - - - - - - - - - PPCR14_3 PPCR14_2 PPCR14_1 PPCR14_0 - - - - PPCR15_3 PPCR15_2 PPCR15_1 PPCR15_0 PPCR16_7 - - - - - PPCR11_1 PPCR11_0 PPCR13_2 PPCR13_1 PPCR13_0 - - - PPCR17_7 PPCR17_6 PPCR17_5 PPCR17_4 PPCR17_3 PPCR17_2 PPCR17_1 PPCR17_0 - - PPCR18_2 PPCR18_1 PPCR18_0 - PPCR19_6 PPCR19_5 PPCR19_4 - - - PPCR19_2 PPCR19_1 PPCR19_0 - PPCR20_6 PPCR20_5 PPCR20_4 - PPCR20_2 PPCR20_1 PPCR20_0 - PPCR21_6 PPCR21_5 PPCR21_4 - PPCR21_2 PPCR21_1 PPCR21_0 - - - - PPCR23_6 - PPCR24_7 PPCR24_6 - - - PPCR22_3 PPCR22_2 - PPCR22_0 PPCR23_4 PPCR23_3 PPCR23_2 PPCR23_1 PPCR23_0 - PPCR24_3 PPCR24_2 PPCR24_1 PPCR24_0 PPCR28_7 PPCR28_6 PPCR28_5 PPCR28_4 PPCR28_3 PPCR28_2 PPCR28_1 PPCR28_0 PPCR29_7 PPCR29_6 PPCR29_5 PPCR29_4 PPCR29_3 PPCR29_2 PPCR29_1 PPCR29_0 R/W R/W R/W R/W R/W R/W R/W Initial value 11111111B 11111111B 11111111B 11111111B 11111111B 1111--11B ---11111B -1111111B ------11B -----111B ----1111B ----1111B 1-------B 11111111B -----111B -111-111B -111-111B -111-111B ----11-1B -1-11111B 11--1111B 11111111B 11111111B R/W Note: For the period that pull-up or pull-down is allowed (PPER=1), write access to the PPCR is invalid and the register value is not updated. Changing the set value of the PPCR is valid only when the corresponding PPER is "0". 315 CHAPTER 10 I/O PORT 316 CHAPTER 11 INTERRUPT CONTROLLER This chapter describes the overview of the interrupt controller, configuration and functions of the registers, and interrupt controller operation. 11.1 Overview of the Interrupt Controller 11.2 Interrupt Controller Registers 11.3 Interrupt Controller Operation 317 CHAPTER 11 INTERRUPT CONTROLLER 11.1 Overview of the Interrupt Controller The interrupt controller controls interrupt acceptance and arbitration processing. ■ Hardware Configuration of the Interrupt Controller This module consists of the following components: • ICR register • Interrupt priority decision circuit • Interrupt level and interrupt number (vector) generator • Hold request cancellation request generator ■ Main Functions of the Interrupt Controller This module has the following main functions: • Detecting NMI requests and interrupt requests • Deciding priority (using a level or number) • Passing (to the CPU) an interrupt level of the interrupt factor based on the priority decision • Passing (to the CPU) an interrupt number of the interrupt factor based on the priority decision • Instructing for return from stop mode due to the occurrence of an interrupt with an NMI/interrupt level other than "11111B" (to CPU) • Generating a hold request cancellation request for the bus master 318 CHAPTER 11 INTERRUPT CONTROLLER ■ Interrupt Controller Registers Figure 11.1-1 shows the interrupt controller registers. Figure 11.1-1 Interrupt Controller Registers Register Address bit7 6 5 4 3 2 1 0 ICR00 000440H − − − ICR4 ICR3 ICR2 ICR1 ICR0 ICR01 000441H − − − ICR4 ICR3 ICR2 ICR1 ICR0 ICR02 000442H − − − ICR4 ICR3 ICR2 ICR1 ICR0 ICR03 000443H − − − ICR4 ICR3 ICR2 ICR1 ICR0 ICR04 000444H − − − ICR4 ICR3 ICR2 ICR1 ICR0 ICR05 000445H − − − ICR4 ICR3 ICR2 ICR1 ICR0 ICR06 000446H − − − ICR4 ICR3 ICR2 ICR1 ICR0 ICR07 000447H − − − ICR4 ICR3 ICR2 ICR1 ICR0 ICR08 000448H − − − ICR4 ICR3 ICR2 ICR1 ICR0 ICR09 000449H − − − ICR4 ICR3 ICR2 ICR1 ICR0 ICR10 00044AH − − − ICR4 ICR3 ICR2 ICR1 ICR0 ICR11 00044BH − − − ICR4 ICR3 ICR2 ICR1 ICR0 ICR12 00044CH − − − ICR4 ICR3 ICR2 ICR1 ICR0 ICR13 00044DH − − − ICR4 ICR3 ICR2 ICR1 ICR0 ICR14 00044EH − − − ICR4 ICR3 ICR2 ICR1 ICR0 ICR15 00044FH − − − ICR4 ICR3 ICR2 ICR1 ICR0 ICR16 000450H − − − ICR4 ICR3 ICR2 ICR1 ICR0 ICR17 000451H − − − ICR4 ICR3 ICR2 ICR1 ICR0 ICR18 000452H − − − ICR4 ICR3 ICR2 ICR1 ICR0 ICR19 000453H − − − ICR4 ICR3 ICR2 ICR1 ICR0 ICR20 000454H − − − ICR4 ICR3 ICR2 ICR1 ICR0 ICR21 000455H − − − ICR4 ICR3 ICR2 ICR1 ICR0 ICR22 000456H − − − ICR4 ICR3 ICR2 ICR1 ICR0 ICR23 000457H − − − ICR4 ICR3 ICR2 ICR1 ICR0 ICR24 000458H − − − ICR4 ICR3 ICR2 ICR1 ICR0 ICR25 000459H − − − ICR4 ICR3 ICR2 ICR1 ICR0 ICR26 00045AH − − − ICR4 ICR3 ICR2 ICR1 ICR0 ICR27 00045BH − − − ICR4 ICR3 ICR2 ICR1 ICR0 ICR28 00045CH − − − ICR4 ICR3 ICR2 ICR1 ICR0 ICR29 00045DH − − − ICR4 ICR3 ICR2 ICR1 ICR0 ICR30 00045EH − − − ICR4 ICR3 ICR2 ICR1 ICR0 ICR31 00045FH − − − ICR4 ICR3 ICR2 ICR1 ICR0 ICR32 000460H − − − ICR4 ICR3 ICR2 ICR1 ICR0 ICR33 000461H − − − ICR4 ICR3 ICR2 ICR1 ICR0 ICR34 000462H − − − ICR4 ICR3 ICR2 ICR1 ICR0 ICR35 000463H − − − ICR4 ICR3 ICR2 ICR1 ICR0 ICR36 000464H − − − ICR4 ICR3 ICR2 ICR1 ICR0 (Continued) 319 CHAPTER 11 INTERRUPT CONTROLLER (Continued) Register Address bit7 6 5 4 3 2 1 0 ICR37 000465H − − − ICR4 ICR3 ICR2 ICR1 ICR0 ICR38 000466H − − − ICR4 ICR3 ICR2 ICR1 ICR0 ICR39 000467H − − − ICR4 ICR3 ICR2 ICR1 ICR0 ICR40 000468H − − − ICR4 ICR3 ICR2 ICR1 ICR0 ICR41 000469H − − − ICR4 ICR3 ICR2 ICR1 ICR0 ICR42 00046AH − − − ICR4 ICR3 ICR2 ICR1 ICR0 ICR43 00046BH − − − ICR4 ICR3 ICR2 ICR1 ICR0 ICR44 00046CH − − − ICR4 ICR3 ICR2 ICR1 ICR0 ICR45 00046DH − − − ICR4 ICR3 ICR2 ICR1 ICR0 ICR46 00046EH − − − ICR4 ICR3 ICR2 ICR1 ICR0 ICR47 00046FH − − − ICR4 ICR3 ICR2 ICR1 ICR0 ICR48 000470H − − − ICR4 ICR3 ICR2 ICR1 ICR0 ICR49 000471H − − − ICR4 ICR3 ICR2 ICR1 ICR0 ICR50 000472H − − − ICR4 ICR3 ICR2 ICR1 ICR0 ICR51 000473H − − − ICR4 ICR3 ICR2 ICR1 ICR0 ICR52 000474H − − − ICR4 ICR3 ICR2 ICR1 ICR0 ICR53 000475H − − − ICR4 ICR3 ICR2 ICR1 ICR0 ICR54 000476H − − − ICR4 ICR3 ICR2 ICR1 ICR0 ICR55 000477H − − − ICR4 ICR3 ICR2 ICR1 ICR0 ICR56 000478H − − − ICR4 ICR3 ICR2 ICR1 ICR0 ICR57 000479H − − − ICR4 ICR3 ICR2 ICR1 ICR0 ICR58 00047AH − − − ICR4 ICR3 ICR2 ICR1 ICR0 ICR59 00047BH − − − ICR4 ICR3 ICR2 ICR1 ICR0 ICR60 00047CH − − − ICR4 ICR3 ICR2 ICR1 ICR0 ICR61 00047DH − − − ICR4 ICR3 ICR2 ICR1 ICR0 ICR62 00047EH − − − ICR4 ICR3 ICR2 ICR1 ICR0 ICR63 00047FH − − − ICR4 ICR3 ICR2 ICR1 ICR0 R R/W R/W R/W R/W Register Address bit7 6 5 4 3 2 1 0 HRCL 000045H MHALTI − − LVL4 LVL3 LVL2 LVL1 LVL0 R R/W R/W R/W R/W R/W 320 CHAPTER 11 INTERRUPT CONTROLLER ■ Block Diagram of the Interrupt Controller Figure 11.1-2 shows a block diagram of the interrupt controller. Figure 11.1-2 Block Diagram of the Interrupt Controller UNMI WAKEUP ("1" when level ≠ 11111B) Priority decision NMI processing Level4 to Level0 5 Level and vector generation Level decision RI00 · · · RI63 ( DLYIRQ) ICR00 · · · ICR63 Vector decision 6 HLDREQ cancellation request MHALTI VCT5 to VCT0 R-bus 321 CHAPTER 11 INTERRUPT CONTROLLER 11.2 Interrupt Controller Registers This section describes the configuration and functions of the interrupt controller registers. ■ Details of the Interrupt Controller Registers The interrupt controller has the following two registers: • Interrupt Control Register (ICR) • HRCL (Hold Request Cancellation Request Register) 322 CHAPTER 11 INTERRUPT CONTROLLER 11.2.1 Interrupt Control Register (ICR) An interrupt control register (ICR) is provided for each of the interrupt input and sets the interrupt level of the corresponding interrupt request. ■ Bit Configuration of the Interrupt Control Register (ICR) The following shows the bit configuration of the interrupt control register (ICR). Figure 11.2-1 Bit Configuration of the Interrupt Control Register (ICR) bit 7 6 5 4 3 2 1 0 Initial value Address: ch.00 000440H ch.63 00047FH − − − ICR4 ICR3 ICR2 ICR1 ICR0 ---11111B R R/W R/W R/W R/W [bit4 to bit0] ICR4 to ICR0 These interrupt level setting bits specify the interrupt level of the corresponding interrupt request. If an interrupt level defined in this register is higher than the level mask value defined in the ILM register of the CPU, the interrupt request is masked by the CPU. These bits are initialized to "11111B" by reset. Table 11.2-1 shows the relationship between available interrupt level setting bits and interrupt levels. Table 11.2-1 Relationship Between Available Interrupt Level Setting Bits and Interrupt Levels ICR4* ICR3 ICR2 ICR1 ICR0 0 0 0 0 0 0 0 1 1 1 0 14 0 1 1 1 1 15 1 0 0 0 0 16 1 0 0 0 1 17 1 0 0 1 0 18 1 0 0 1 1 19 1 0 1 0 0 20 1 0 1 0 1 21 1 0 1 1 0 22 1 0 1 1 1 23 1 1 0 0 0 24 1 1 0 0 1 25 1 1 0 1 0 26 1 1 0 1 1 27 1 1 1 0 0 28 1 1 1 0 1 29 1 1 1 1 0 30 1 1 1 1 1 31 *: ICR4 is always "1". "0" cannot be written to this bit. Interrupt level Reserved by system NMI Maximum level can be set (High) (Low) Interrupt disabled 323 CHAPTER 11 INTERRUPT CONTROLLER 11.2.2 HRCL (Hold Request Cancellation Request Register) HRCL is a level setting register used to generate a hold request cancellation request. ■ Bit Configuration of the Hold Request Cancellation Request Register (HRCL) The following shows the bit configuration of the hold request cancellation request register (HRCL). Figure 11.2-2 Bit Configuration of the Hold Request Cancellation Request Register (HRCL) HRCL bit Address: 000039H 7 6 5 4 3 2 1 0 Initial value MHALTI − − LVL4 LVL3 LVL2 LVL1 LVL0 0--11111B R R/W R/W R/W R/W R/W [bit7] MHALTI MHALTI is the DMA transfer suppression bit controlled by an NMI request. An NMI request sets this bit to "1". Write "0" to this bit to clear it. At the end of an NMI routine, clear this bit in the same way as a normal interrupt routine. [bit4 to bit0] LVL4 to LVL0 These bits set the interrupt level used to issue a hold request cancellation request to the bus master. If an interrupt request with a higher level than the level defined in the HRCL register occurs, a hold request cancellation request is issued to the bus master. The LVL4 bit is fixed to "1" and "0" cannot be written to this bit. 324 CHAPTER 11 INTERRUPT CONTROLLER 11.3 Interrupt Controller Operation This section describes the operation of the interrupt controller. ■ Priority Decision The interrupt controller selects the interrupt factor with the highest priority from among those that occur simultaneously and outputs the interrupt level and the interrupt number of that factor to the CPU. The following shows the priority decision criteria for interrupt factor: 1) NMI 2) Factor that meets the following conditions: - Factor with a value other than 31 for the interrupt level (31 means interrupt is disabled.) - Factor with the smallest value for the interrupt level - Factor with the smallest interrupt number among those satisfy the both conditions above If no interrupt factor is selected according to the above decision criteria, 31 (11111B) is outputted as the interrupt level. The interrupt number at this time is undefined. Table 11.3-1 shows the relationship among the interrupt factors, interrupt numbers, and interrupt levels. Table 11.3-1 Relationship Among Interrupt Factors, Interrupt Numbers, and Interrupt Levels (1 / 6) Interrupt number Interrupt factor Interrupt level Register address Offset TBR default address Resource Number * Decimal Hexadecimal Setting register Reset 0 00H − − 3FCH 000FFFFCH − Mode vector 1 01H − − 3F8H 000FFFF8H − Reserved by system 2 02H − − 3F4H 000FFFF4H − Reserved by system 3 03H − − 3F0H 000FFFF0H − Reserved by system 4 04H − − 3ECH 000FFFECH − Reserved by system (UDSU) 5 05H − − 3E8H 000FFFE8H − Reserved by system (UDSU) 6 06H − − 3E4H 000FFFE4H − Coprocessor absent trap 7 07H − − 3E0H 000FFFE0H − Coprocessor error trap 8 08H − − 3DCH 000FFFDCH − INTE instruction 9 09H − − 3D8H 000FFFD8H − Reserved by system 10 0AH − − 3D4H 000FFFD4H − Reserved by system 11 0BH − − 3D0H 000FFFD0H − Step trace trap 12 0CH − − 3CCH 000FFFCCH − NMI request (tool) 13 0DH − − 3C8H 000FFFC8H − 325 CHAPTER 11 INTERRUPT CONTROLLER Table 11.3-1 Relationship Among Interrupt Factors, Interrupt Numbers, and Interrupt Levels (2 / 6) Interrupt number Interrupt factor Interrupt level TBR default address Resource Number * Decimal Hexadecimal Undefined instruction exception 14 0EH − − 3C4H 000FFFC4H − NMI request 15 0FH 15(F) Fixed 15(F) Fixed 3C0H 000FFFC0H − External interrupt 0 16 10H 000FFFBCH 0 17 11H 440H 3BCH External interrupt 1 ICR00 3B8H 000FFFB8H 1 External interrupt 2 18 12H 000FFFB4H 2 19 13H 441H 3B4H External interrupt 3 ICR01 3B0H 000FFFB0H 3 External interrupt 4 20 14H 000FFFACH − 21 15H 442H 3ACH External interrupt 5 ICR02 3A8H 000FFFA8H − External interrupt 6 22 16H 000FFFA4H − 23 17H 443H 3A4H External interrupt 7 ICR03 3A0H 000FFFA0H − External interrupt 8 24 18H 000FFF9CH − 25 19H 444H 39CH External interrupt 9 ICR04 398H 000FFF98H − External interrupt 10 26 1AH 000FFF94H − 27 1BH 445H 394H External interrupt 11 ICR05 390H 000FFF90H − External interrupt 12 28 1CH 000FFF8CH − 29 1DH 446H 38CH External interrupt 13 ICR06 388H 000FFF88H − External interrupt 14 30 1EH 000FFF84H − 31 1FH 447H 384H External interrupt 15 ICR07 380H 000FFF80H − Reload timer 0 32 20H 000FFF7CH 4 33 21H 448H 37CH Reload timer 1 ICR08 378H 000FFF78H 5 Reload timer 2 34 22H 000FFF74H − 35 23H 449H 374H Reload timer 3 ICR09 370H 000FFF70H − Reserved by system 36 24H 000FFF6CH − 37 25H 44AH 36CH Reserved by system ICR10 368H 000FFF68H − Reserved by system 38 26H 000FFF64H − 39 27H 44BH 364H Reload timer 7 ICR11 360H 000FFF60H − Free-run timer 0 40 28H 000FFF5CH − 41 29H 44CH 35CH Free-run timer 1 ICR12 358H 000FFF58H − 326 Register address Offset Setting register CHAPTER 11 INTERRUPT CONTROLLER Table 11.3-1 Relationship Among Interrupt Factors, Interrupt Numbers, and Interrupt Levels (3 / 6) Interrupt number Interrupt factor Decimal Hexadecimal Free-run timer 2 42 2AH Free-run timer 3 43 2BH Reserved by system 44 2CH Reserved by system 45 2DH Reserved by system 46 2EH Reserved by system 47 2FH CAN 0 48 30H CAN 1 49 31H Reserved by system 50 32H Reserved by system 51 33H Reserved by system 52 34H Reserved by system 53 35H LIN-UART 0 RX 54 36H LIN-UART 0 TX 55 37H LIN-UART 1 RX 56 38H LIN-UART 1 TX 57 39H LIN-UART 2 RX 58 3AH LIN-UART 2 TX 59 3BH LIN-UART 3 RX 60 3CH LIN-UART 3 TX 61 3DH Reserved by system 62 3EH Delayed interrupt 63 3FH Reserved by system 64 40H Reserved by system 65 41H LIN-UART 4 RX 66 42H LIN-UART 4 TX 67 43H LIN-UART 5 RX 68 44H LIN-UART 5 TX 69 45H Interrupt level Setting register Register address ICR13 44DH ICR14 44EH ICR15 44FH ICR16 450H ICR17 451H ICR18 452H ICR19 453H ICR20 454H ICR21 455H ICR22 456H ICR23 457H (ICR24) 458H ICR25 459H ICR26 45AH Offset TBR default address Resource Number * 354H 000FFF54H − 350H 000FFF50H − 34CH 000FFF4CH − 348H 000FFF48H − 344H 000FFF44H − 340H 000FFF40H − 33CH 000FFF3CH − 338H 000FFF38H − 334H 000FFF34H − 330H 000FFF30H − 32CH 000FFF2CH − 328H 000FFF28H − 324H 000FFF24H 6 320H 000FFF20H 7 31CH 000FFF1CH 8 318H 000FFF18H 9 314H 000FFF14H − 310H 000FFF10H − 30CH 000FFF0CH − 308H 000FFF08H − 304H 000FFF04H − 300H 000FFF00H − 2FCH 000FFEFCH − 2F8H 000FFEF8H − 2F4H 000FFEF4H 10 2F0H 000FFEF0H 11 2ECH 000FFEECH 12 2E8H 000FFEE8H 13 327 CHAPTER 11 INTERRUPT CONTROLLER Table 11.3-1 Relationship Among Interrupt Factors, Interrupt Numbers, and Interrupt Levels (4 / 6) Interrupt number Interrupt factor Decimal Hexadecimal LIN-USART 6 RX 70 46H LIN-USART 6 TX 71 47H Reserved by system 72 48H Reserved by system 73 49H I2C_0 / I2C_2 74 4AH I2C_1 / I2C_3 75 4BH Reserved by system 76 4CH Reserved by system 77 4DH Reserved by system 78 4EH Reserved by system 79 4FH Reserved by system 80 50H Reserved by system 81 51H Reserved by system 82 52H Reserved by system 83 53H Reserved by system 84 54H Reserved by system 85 55H Reserved by system 86 56H Reserved by system 87 57H Reserved by system 88 58H Reserved by system 89 59H Reserved by system 90 5AH Reserved by system 91 5BH Input capture 0 92 5CH Input capture 1 93 5DH Input capture 2 94 5EH Input capture 3 95 5FH Reserved by system 96 60H Reserved by system 97 61H 328 Interrupt level Setting register Register address ICR27 45BH ICR28 45CH ICR29 45DH ICR30 45EH ICR31 45FH ICR32 460H ICR33 461H ICR34 462H ICR35 463H ICR36 464H ICR37 465H ICR38 566H ICR39 467H ICR40 468H Offset TBR default address Resource Number * 2E4H 000FFEE4H − 2E0H 000FFEE0H − 2DCH 000FFEDCH − 2D8H 000FFED8H − 2D4H 000FFED4H − 2D0H 000FFED0H − 2CCH 000FFECCH − 2C8H 000FFEC8H − 2C4H 000FFEC4H − 2C0H 000FFEC0H − 2BCH 000FFEBCH − 2B8H 000FFEB8H − 2B4H 000FFEB4H − 2B0H 000FFEB0H − 2ACH 000FFEACH − 2A8H 000FFEA8H − 2A4H 000FFEA4H − 2A0H 000FFEA0H − 29CH 000FFE9CH − 298H 000FFE98H − 294H 000FFE94H − 290H 000FFE90H − 28CH 000FFE8CH − 288H 000FFE88H − 284H 000FFE84H − 280H 000FFE80H − 27CH 000FFE7CH − 278H 000FFE78H − CHAPTER 11 INTERRUPT CONTROLLER Table 11.3-1 Relationship Among Interrupt Factors, Interrupt Numbers, and Interrupt Levels (5 / 6) Interrupt number Interrupt factor Decimal Hexadecimal Reserved by system 98 62H Reserved by system 99 63H Output capture 0 100 64H Output capture 1 101 65H Output capture 2 102 66H Output capture 3 103 67H Reserved by system 104 68H Reserved by system 105 69H Reserved by system 106 6AH Reserved by system 107 6BH Reserved by system 108 6CH Reserved by system 109 6DH Reserved by system 110 6EH Reserved by system 111 6FH PPG0 112 70H PPG1 113 71H PPG2 114 72H PPG3 115 73H PPG4 116 74H PPG5 117 75H PPG6 118 76H PPG7 119 77H Reserved by system 120 78H Reserved by system 121 79H Reserved by system 122 7AH Reserved by system 123 7BH Reserved by system 124 7CH Reserved by system 125 7DH Interrupt level Setting register Register address ICR41 469H ICR42 46AH ICR43 46BH ICR44 46CH ICR45 46DH ICR46 46EH ICR47 46FH ICR48 470H ICR49 471H ICR50 472H ICR51 473H ICR52 474H ICR53 475H ICR54 476H Offset TBR default address Resource Number * 274H 000FFE74H − 270H 000FFE70H − 26CH 000FFE6CH − 268H 000FFE68H − 264H 000FFE64H − 260H 000FFE60H − 25CH 000FFE5CH − 258H 000FFE58H − 254H 000FFE54H − 250H 000FFE50H − 24CH 000FFE4CH − 248H 000FFE48H − 244H 000FFE44H − 240H 000FFE40H − 23CH 000FFE3CH 15 238H 000FFE38H − 234H 000FFE34H − 230H 000FFE30H − 22CH 000FFE2CH − 228H 000FFE28H − 224H 000FFE24H − 220H 000FFE20H − 21CH 000FFE1CH − 218H 000FFE18H − 214H 000FFE14H − 210H 000FFE10H − 20CH 000FFE0CH − 208H 000FFE08H − 329 CHAPTER 11 INTERRUPT CONTROLLER Table 11.3-1 Relationship Among Interrupt Factors, Interrupt Numbers, and Interrupt Levels (6 / 6) Interrupt number Interrupt factor Decimal Hexadecimal Reserved by system 126 7EH Reserved by system 127 7FH Reserved by system 128 80H Reserved by system 129 81H Reserved by system 130 82H Reserved by system 131 83H Real time clock 132 84 Clock calibration * 133 85H A/D converter 0 134 85 Reserved by system 135 87H Reserved by system 136 88H Reserved by system 137 89H Reserved by system 138 8AH Reserved by system 139 8BH Time base overflow 140 8CH PLL clock gear 141 8DH DMA controller 142 8EH Interrupt level Setting register Register address ICR55 477H ICR56 478H ICR57 479H ICR58 47AH ICR59 47BH ICR60 47CH ICR61 47DH ICR62 47EH ICR63 47FH Offset TBR default address Resource Number * 204H 000FFE04H − 200H 000FFE00H − 1FCH 000FFDFCH − 1F8H 000FFDF8H − 1F4H 000FFDF4H − 1F0H 000FFDF0H − 1ECH 000FFDECH − 1E8H 000FFDE8H − 1E4H 000FFDE4H 14 1E0H 000FFDE0H − 1DCH 000FFDDCH − 1D8H 000FFDD8H − 1D4H 000FFDD4H − 1D0H 000FFDD0H − 1CCH 000FFDCCH − 1C8H 000FFDC8H − 1C4H 000FFDC4H − 1C0H 000FFDC0H − Main/sub oscillation stabilization wait 143 8FH Reserved by system 144 90H − − 1BCH 000FFDBCH − Use in INT instruction 145 : 255 91H : FFH − − 1B8H : 000H 000FFDB8H : 000FFC00H − *: Clock Calibration cannot be used with MB91461. 330 CHAPTER 11 INTERRUPT CONTROLLER ■ NMI (Non Maskable Interrupt) NMI has the highest priority among the interrupt factors handled by this module. Therefore, NMI is always selected if it occurs at the same time as other interrupt factors do. ● NMI generation If an NMI occurs, the following information is reported to the CPU: • Interrupt level: 15 (01111B) • Interrupt number: 15 (0001111B) ● NMI detection The external interrupt and NMI module sets and detects the NMI. This module only generates an interrupt level, interrupt number, and MHALTI in response to an NMI request. ● DMA transfer suppression by NMI If an NMI request is generated, the MHALTI bit of the HRCL register is set to "1" to suppress DMA transfer. To cancel the suppression of DMA transfer, clear the MHALTI bit to "0" at the end of the NMI routine. ■ Hold Request Cancellation Request If an interrupt with a high priority is processed during CPU hold (during DMA transfer), the device that has generated the hold request must cancel the request. Set the interrupt level used as the criterion of generating a cancellation request in the HRCL register. ● Generation criteria If an interrupt factor with a higher interrupt level than the level defined in the HRCL register is generated, a hold request cancellation request is generated. HRCL register interrupt level > Interrupt level after a priority decision → Cancellation request is generated HRCL register interrupt level ≤ Interrupt level after a priority decision → Cancellation request is not generated Unless the interrupt factor that has caused the cancellation request is cleared, the cancellation request remains valid and so no DMA transfer occurs as a result. Be sure to clear the corresponding interrupt factor. If an NMI is used, the cancellation request is valid because the MHALTI bit of the HRCL register is "1". 331 CHAPTER 11 INTERRUPT CONTROLLER ● Available setting levels Values that can be set in the HRCL register range from "10000B" to "11111B", which is the same range as for the ICR. If this register is set to "11111B", a cancellation request is issued for all the interrupt levels. If this register is set to "10000B", a cancellation request is issued only for an NMI. Table 11.3-2 shows the settings of interrupt levels for the hold request cancellation request generation. Table 11.3-2 Settings of Interrupt Levels for the Hold Request Cancellation Request Generation 16 NMI only 17 NMI, Interrupt level 16 18 NMI, Interrupt levels 16 and 17 ··· Interrupt level for cancellation request generation ··· HRCL register 31 NMI, Interrupt levels 16 to 30 [Initial value] After a reset, DMA transfer is suppressed at any interrupt levels. Since DMA transfer cannot be performed if an interrupt has been occurred, be sure to set the HRCL register to the appropriate value. ■ Return from Standby Mode (Sleep/Stop) This module implements a function that causes a return from stop mode if an interrupt request occurs. If at least one interrupt request that includes NMI from the peripheral is generated (with an interrupt level other than "11111B"), a return request from stop mode is generated for the clock controller. Since the priority decision unit restarts operation when a clock is supplied after returning from stop, the CPU executes instructions until the result of the priority decision unit is obtained. The same operation occurs for a return from the sleep state. Registers in this module can be accessed even in the sleep state. Notes: • A return from shutdown mode by NMI request is not supported. • A return from stop mode by NMI request can be possible. However, be sure to set NMI so that valid inputs in the stop state can be detected. • Set an interrupt level to "11111B" in the corresponding peripheral control register for an interrupt factor that you do not want to cause a return from stop or sleep. 332 CHAPTER 11 INTERRUPT CONTROLLER ■ Example of Using the Hold Request Cancellation Request Function (HRCL) To allow the CPU to perform high-priority processing during DMA transfer, cancel a hold request to the DMA and clear the hold state. In this example, an interrupt is used to cancel a hold request to the DMA, allowing the CPU to perform priority operations. ● Control register 1) HRCL (Hold request cancellation level setting register): This module: If an interrupt with a higher interrupt level than the level defined in this register occurs, a hold request cancellation request is issued to DMA. This register sets the level to be used as the criterion for this purpose. 2) ICR: This module: This register sets a higher level than the level in the HRCL register for the ICR corresponding to the interrupt factor to be used. ● Hardware configuration Figure 11.3-1 shows the flow of each signal for hold request. Figure 11.3-1 Flow of Each Signal for Hold Request This module IRQ Bus access request MHALTI I-unit DHREQ DMA B-unit DHREQ: D-bus hold request CPU DHACK: D-bus hold acknowledge (ICR) IRQ: (HRCL) DHACK Interrupt request MHALTI: Hold request cancellation request ● Sequence Figure 11.3-2 shows the interrupt level HRCL < ICR (LEVEL). Figure 11.3-2 Interrupt Level HRCL < ICR (LEVEL) RUN CPU Bus access request Interrupt processing (1) (2) Bus hold (DMA transfer) Example of interrupt routine (1) Interrupt factor clear ··· DHREQ Bus hold DHACK (2) RETI IRQ LEVEL MHALTI 333 CHAPTER 11 INTERRUPT CONTROLLER If an interrupt request occurs, the interrupt level changes and if the interrupt level is higher than the level defined in the HRCL register, MHALTI becomes "H" level for DMA. This causes DMA to cancel an access request and the CPU to return from the hold state to perform the interrupt processing. Figure 11.3-3 shows the INTC-3 interrupt level HRCL < ICR (interrupt I) < ICR (interrupt II). Figure 11.3-3 INTC-3 Interrupt Level HRCL < ICR (Interrupt I) < ICR (Interrupt II) RUN Bus hold CPU Interrupt processing II Interrupt I (3) (4) Interrupt processing I (1) Bus hold (DMA transfer) (2) Bus access request DHREQ DHACK IRQ1 IRQ2 LEVEL MHALTI [Example of interrupt routine] (1), (3) Interrupt factor clear to (2), (4) RETI The above example shows a case that an interrupt with a higher priority occurs while interrupt routine I is being executed. While the interrupt with a higher level than the level in the HRCL register is occurring, DHREQ is kept at a low level. Note: Be especially careful about the relationship between interrupt levels to be defined in the HRCL and ICR. 334 CHAPTER 12 EXTERNAL INTERRUPT CONTROLLER This chapter describes the overview of the external interrupt controller, configuration and functions of the registers and external interrupt controller operation. 12.1 Overview of the External Interrupt Controller 12.2 External Interrupt Controller Registers 12.3 Operation of the External Interrupt Controller 335 CHAPTER 12 EXTERNAL INTERRUPT CONTROLLER 12.1 Overview of the External Interrupt Controller The external interrupt controller is a block that controls external interrupt requests inputted to INT pin. The type can be selected from the following four types as the request level/edge to be detected. • "H" level • "L" level • Rising edge • Falling edge ■ List of the External Interrupt Controller Registers External interrupt controller registers are shows as follows. Figure 12.1-1 Bit Configuration of External Interrupt Controller Registers bit bit bit bit 336 7 6 5 4 3 2 1 0 EN7 EN6 EN5 EN4 EN3 EN2 EN1 EN0 15 14 13 12 11 10 9 8 ER7 ER6 ER5 ER4 ER3 ER2 ER1 ER0 7 6 5 4 3 2 1 0 LB3 LA3 LB2 LA2 LB1 LA1 LB0 LA0 15 14 13 12 11 10 9 8 LB7 LA7 LB6 LA6 LB5 LA5 LB4 LA4 External interrupt enable register (ENIR) External interrupt factor register (EIRR) Request level setting register (ELVR) CHAPTER 12 EXTERNAL INTERRUPT CONTROLLER ■ Block Diagram of the External Interrupt Controller Figure 12.1-2 shows a block diagram of the external interrupt controller. Figure 12.1-2 Block Diagram of the External Interrupt Controller R-bus 8 Interrupt request 17 Interrupt enable register Gate 17 Factor F/F Edge detection circuit INT0 to INT15 NMI 8 Interrupt factor register 16 Request level setting register 337 CHAPTER 12 EXTERNAL INTERRUPT CONTROLLER 12.2 External Interrupt Controller Registers This section describes the configuration and functions of the external interrupt controller registers. ■ Details of External Interrupt Controller Registers The external interruption controller registers are the following three types: • External Interrupt Enable Register (ENIR) • External Interrupt Factor Register (EIRR) • External Interrupt Request Level Setting Register (ELVR) 338 CHAPTER 12 EXTERNAL INTERRUPT CONTROLLER 12.2.1 External Interrupt Enable Register (ENIR) ENIR controls the masking of external interrupt request output. ■ Bit Configuration of ENIR Figure 12.2-1 shows the bit configuration of the interrupt enable register. Figure 12.2-1 Bit Configuration of the Interrupt Enable Register bit 7 6 5 4 3 2 1 0 ENIR0 Address: 000031H EN7 EN6 EN5 EN4 EN3 EN2 EN1 EN0 bit 7 6 5 4 3 2 1 0 ENIR1 Address: 000035H EN15 EN14 EN13 EN12 EN11 EN10 EN9 EN8 Initial value 00000000B [R/W] 00000000B [R/W] The interrupt request output corresponding to the bit to which "1" is written in this register is enabled (INT0 enabling is controlled by EN0), and a request is outputted to the interrupt controller. The pin corresponding to the bit to which "0" is written holds the interrupt factor but does not generate a request to the interrupt controller. 339 CHAPTER 12 EXTERNAL INTERRUPT CONTROLLER 12.2.2 External Interrupt Factor Register (EIRR) EIRR indicates the presence of the corresponding external interrupt request when reading this register, and clears the contents of the flip-flop indicating this interrupt request when writing to this register. ■ Bit Configuration of EIRR Bit configuration of the external interrupt factor register is as follows. Figure 12.2-2 Bit Configuration of the External Interrupt Factor Register bit 15 14 13 12 11 10 9 8 EIRR0 Address: 000030H ER7 ER6 ER5 ER4 ER3 ER2 ER1 ER0 bit 15 14 13 12 11 10 9 8 EIRR1 Address: 000034H ER15 ER14 ER13 ER12 ER11 ER10 ER9 ER8 Initial value 00000000B [R/W] 00000000B [R/W] When this EIRR register is read, the operation becomes as follows depending on the value. If the read value of this EIRR register is "1", there is an external interrupt request at the pin corresponding to the bit. When "0" is written to this register, the request flip-flop of the corresponding bit is cleared. Writing "1" is invalid. For a read by a read-modify-write (RMW) instruction, "1" is read. 340 CHAPTER 12 EXTERNAL INTERRUPT CONTROLLER 12.2.3 External Interrupt Request Level Setting Register (ELVR) ELVR is the register that selects a request detection. ■ Bit Configuration of ELVR Bit configuration of the external interrupt request level setting is as follows. Figure 12.2-3 Bit Configuration of the External Interrupt Request Level Setting bit 7 ELVR0 Address: 000032H LB3 bit 15 000033H LB7 6 5 4 3 2 1 0 Initial value LA3 LB2 LA2 LB1 LA1 LB0 LA0 00000000B 14 13 12 11 10 9 8 Initial value LA7 LB6 LA6 LB5 LA5 LB4 LA4 00000000B [R/W] bit 7 6 5 4 3 ELVR1 Address: 000036H LB11 LA11 LB10 LA10 LB9 2 1 0 LA9 LB8 LA8 bit 15 14 13 12 11 10 9 8 000037H LB15 LA15 LB14 LA14 LB13 LA13 LB12 LA12 Initial value 00000000B Initial value 00000000B [R/W] In ELVR, two bits each are assigned to each interrupt channel and the setting is as shown below. Even though each bit of the EIRR is cleared while the request input is level-base operation, the corresponding bit is set again as long as the input is at active level. Table 12.2-1 shows the assignment of ELVR. Table 12.2-1 Assignment of ELVR LBx, LAx Operation 00B Detecting a request with "L" level [Initial value] 01B Detecting a request with "H" level 10B Detecting a request with rising edge 11B Detecting a request with falling edge Notes: • Edge detection cannot be set for the interrupts that cause return from the STOP mode and the shut-down mode. • If external interrupt request level is changed, internal interrupt request may be occurred. So clear the external interrupt register (EIRR) after changing the external interrupt request level. When you want to clear the external interrupt request level register once. 341 CHAPTER 12 EXTERNAL INTERRUPT CONTROLLER 12.3 Operation of the External Interrupt Controller This section explains the operation of the external interruption controller. ■ External Interrupt Operation After a request level and an enable register are set, if a request set in the ELVR register is inputted to the corresponding pin, this module generates an interrupt request signal to the interrupt controller. When priorities of the interrupts generated simultaneously in the interrupt controller is determined and if the priority of the interrupt from this resource is the highest, the corresponding interrupt is generated. Figure 12.3-1 shows the external interrupt operation. Figure 12.3-1 External Interrupt Operation External interrupt ELVR Resource request Interrupt controller ICR Y Y EIRR ENIR CPU IL CMP ICR X X CMP ILM Factor ■ Operation Procedure of External Interrupt Use the following procedure to set registers located in the external interrupt controller: 1. Set the port to be used as a external interrupt input and shared general-purpose I/O port to input port. 2. Disable the target bit in the interrupt enable register (ENIR). 3. Set the target bit in the external interrupt request level setting register (ELVR). 4. Read the external interrupt request level setting register (ELVR). 5. Clear the target bit in the external interrupt source register (EIRR). 6. Enable the target bit in the interrupt enable register (ENIR). (Simultaneous writing of 16-bit data is supported for steps 5) and 6)). Before setting registers in this module, be sure to disable the enable register. In addition, before enabling the enable register, be sure to clear the factor register. This procedure is required to prevent an interrupt factor from occurring by mistake while a register is being set or an interrupt is enabled. 342 CHAPTER 12 EXTERNAL INTERRUPT CONTROLLER ■ External Interrupt Request Level If the request level is an edge request, a pulse width of at least three machine cycles (peripheral clock machine cycles) is required to detect an edge. If the request input level is a level setting, even when a request input arrives from the outside and is then cancelled, the request to the interrupt controller remains valid because a factor holding circuit exists internally. The factor register must be cleared to cancel the request to the interrupt controller. Figure 12.3-2 shows the clearing of the factor holding circuit when a level is set. Figure 12.3-2 Clearing of the Factor Holding Circuit When a Level is Set Interrupt input Level detection Factor F/F (Factor holding circuit) Enable gate Interrupt controller Continuing to hold a factor unless cleared Figure 12.3-3 shows the interrupt factor and the interrupt request to the interrupt controller when interrupt is enabled. Figure 12.3-3 Interrupt Factor and Interrupt Request to the Interrupt Controller When Interrupt is Enabled Interrupt input "H" level Interrupt request to interrupt controller Becoming invalid by clearing factor F/F 343 CHAPTER 12 EXTERNAL INTERRUPT CONTROLLER ■ Precautions when Returning from STOP State Using External Interrupt The external interrupt signal that is initially input to the INT pin in a STOP state is input asynchronously, allowing the device to return from the STOP state. Note, however, that there are periods from the release of the STOP state till the end of the oscillation stabilization wait time, in such periods the input of other external interrupt signals cannot be identified (period of b + c + d in Figure 12.3-4). This is because the external input signal after the release of STOP mode is synchronized with the internal clock; consequently, the corresponding interrupt source cannot be retained while the clock is still unstable. Therefore, input an external interrupt signal after the oscillation stabilization wait time has passed, when inputting an external interrupt after the release of STOP mode. Figure 12.3-4 Operational Sequence for Returning from STOP State by External Interrupt INT1 INT0 Internal STOP "L" s "H" Regulator Internal operation (RUN) Implement command (RUN) X0 Internal clock Interrupt flag clear INTR0 INTE0 "1" (Set to enable before switching to STOP mode) INTR1 INTE1 "1" enable (Set before switching to STOP mode) (e)RUN (a) STOP (b) Regulator stabilization wait time (d) Oscillation stabilization time (c) Oscillator oscillation time 344 CHAPTER 12 EXTERNAL INTERRUPT CONTROLLER ■ Operation when Recovering from STOP Mode The operation when recovery from STOP mode is triggered by an external interrupt from an operating circuit is as follows. ● Processing prior to entering STOP mode Setting External Interrupt Route It is necessary to permit the interrupt input route for release STOP status before the device transits to STOP status. These configuration are made using the EISSR register. Under normal conditions (i.e., any status other than STOP), the interrupt input route is permitted, so there is no need for special recognition. In STOP status, however, the input path is controlled by the EISSR register value. External Interrupt Inputs If recovering from STOP status, the external interrupt signals send an input signal asynchronously. When this interrupt signal is asserted, the internal STOP signal is immediately turned OFF. At the same time, the external interrupt circuit is switched so as to synchronize other level interrupt inputs. ● Regulator stabilization wait time The mechanism for switching from the regulator used during STOP mode to the regulator used during RUN mode is invoked when the internal STOP signal is fallen. As misoperation may occur if internal operation starts before the voltage output of the RUN mode regulator has stabilized, a delay time is used to wait for the internal output voltage to stabilize. The clock remains halted during this time. ● Oscillator startup time The clock oscillation starts after the regulator stabilization delay time elapses. The startup time of the oscillator depends on the type of oscillator used. ● Oscillation stabilization wait time After the oscillator startup time elapses, the device waits for the oscillation stabilization wait time which is generated internally. This time is specified by the OS1 and OS0 bits in the standby control register. After the oscillation stabilization wait time elapses, the internal clock supply starts and execution of the interrupt handler for the external interrupt starts. At the same time the external interrupts other than the return source from STOP mode become able to be received. Note: When "H" was input externally to INT0 through INT15 and the following operation is conducted, the request flag EIRR will be set even if "L" is not input externally: 1. An interrupt pin is set with PFR. 2. The interrupt detection level is set to "L". 3. An interrupt is enabled. To avoid this, clear EIRR between steps 2. and 3. 345 CHAPTER 12 EXTERNAL INTERRUPT CONTROLLER 346 CHAPTER 13 MPU / EDSU This chapter describes the memory protection features and embedded debug support features. 13.1 Overview 13.2 Break Functions 13.3 EDSU Registers 13.4 Quick Reference 347 CHAPTER 13 MPU / EDSU 13.1 Overview The memory protection unit (MPU) and the embedded debug support unit (EDSU) are installed on MB91F467R. These features are not provided on MB91461. Note: The MPU/EDSU module features a clock disable function. For enabling the MPU/EDSU module it is necessary to set the EDSUEN bit in the CSCFG register. The MPU/EDSU is scalable in units of "Comparator Groups". The number of this Groups can be defined from up to eight. Features of Comparator Group are listed below: • A total number of 4 Breakpoints, could be programmed to: - 4 Instruction Address Breakpoints - 4 Operand Address Breakpoints (programmable on datasize and access type) - 2 Operand Address Breakpoints and 2 Instruction Address Breakpoints - 2 Operand Address Breakpoints and 2 Data Value Breakpoints • 2 Masks possible to assign (reduces the number of breakpoints) • 2 Range Functions • Break Trigger programmable on resource interrupts • MPU functionality - User and SuperVisor permission for read/write/execute - Default permissions for the whole MCU address range - Permission definition for two address ranges per Comparator Group (8 Groups result in 16 MPU Channels) - Can detect DMA accesses on the D-bus and Resource address regions - Register set is locked in User mode - Dynamic configuration possible, privileged configuration with INT #5 is not interruptible - A permission violation causes an MPUPV trap • Capture register for Instruction Address and Operand Address (for MPU and Operand Break) • Capture information for MPU channel index, DMA flag, Operand Size and Access Type 348 CHAPTER 13 MPU / EDSU 13.2 Break Functions This chapter describes each breakpoint and embedded debug support features. One Comparator Group offers up to 4 Breakpoints. One Group consists of two full-featured range comparators with the option to use two point registers as mask information. The following features could be partially mixed-up: ■ Features ● Instruction Address Breakpoints Up to 4 instruction address breakpoints can be defined. Two instruction breakpoints can be masked. The other two registers can operate as mask registers then. Also maskable is a break address range made with two points and one mask register. Two absolute address ranges for instruction breakpoints can be defined where 2 or 4 out of 4 instruction breakpoint registers are assigned for the range. ● Operand Address Breakpoints Up to 4 operand address breakpoints can be defined. Two operand breakpoints can be masked. The other two registers can operate as mask registers then. Also maskable is a break address range made with two points and one mask register. Two absolute address ranges for operand breakpoints can be defined where 2 or 4 out of 4 operand breakpoint registers are assigned for the range. Operand breaks can be selected for datasizes: byte, halfword and word on access types: read, read-modifywrite (RMW) instruction and write. ● Operand Data Value Breakpoints Up to 2 operand data value breakpoints can be defined. The definition of one data value range is possible. One data value breakpoint can be masked by defining the other point as mask register. The Operand Address and Data Value Breakpoints can be switched to a combined trigger condition. ● Memory protection Two channels/ranges could be defined to operate in memory protection mode. Possible is the protection of two Operand Address ranges, two Instruction Address Ranges or a combination of one Operand and one Instruction Address range. Read/write or execute permissions could be defined for each channel, both for the normal User and the SuperVisor mode. 349 CHAPTER 13 MPU / EDSU 13.2.1 Instruction Address Break Four breakpoints or less can be defined in the instruction address break. This section describes the setting of the instruction address break. The instruction address break is the most basic break that occurs when an instruction is fetched at the address specified by the break address data registers BAD[3:0]. Setting the CTC[1:0] bits of the control register BCR0 to "00B" provides this mode. The bits EP[3:0] in BCR0 enable the break points. Up to 4 instruction breakpoints from channels 0 to 3 can be set. All instruction break events are ORed into instruction break exception requests to the CPU. ■ Mask Register Setting 2 of the break address data registers can operate as mask registers (BAD0, BAD2) for masking the instruction address which is being fetched. Mask register BAD0 can be assigned either to BAD1 (same channel) or BAD2/BAD3 (opposite channel), mask register BAD2 can be assigned either to BAD3 or BAD0/BAD1. Normally Instruction break address and mask information reside in the same channel. So BAD3 contains the instruction break address and BAD2 the address mask information. The channel is enabled with EP3. The same applies for channel BAD1 (address), BAD0 (mask) and EP1 (enable). BAD2 retains the instruction address information and cannot carry the address mask. In this case, the mask information is retrieved from the register BAD0 by enabling point 2 (EP2) or the range function (ER1). The same applies for EP0 and ER0: The mask information is retrieved from the register BAD2. Example: CTC00: Type: Instruction Address Break EP11: Enable break point address BAD1 EM01: Set mask BAD0 for break address BAD1 BAD1 12345678H: Set break address BAD0 00000FFFH: Set break mask Break occurs at 12345000H to 12345FFFH On break at BAD[3:0] the respective flags BD[3:0] in the break interrupt request register BIRQ will be set to "1". They have to be reset by software in the instruction break routine. 350 CHAPTER 13 MPU / EDSU ■ Address Range Match Function Setting Channels 0 and 1 (BAD0, BAD1) function as address range match when setting the ER0 bit of the control register BCR0 to "1". BAD0 is the lower address and BAD1 is the upper address for address comparison. The mask register BAD2 will mask both channels 0 and 1, if the mask feature is enabled by EM0 = 1. Alternatively, channels 2 and 3 (BAD2, BAD3) function as address range match when setting the ER1 bit of the control register BCR0 to "1". BAD2 is the lower address and BAD3 is the upper address for address comparison. The mask register BAD0 will mask both channels 2 and 3, if the mask feature is enabled by EM1 = 1. Example: CTC00: Type: Instruction Address Break EP01: Enable break point address BAD0 EP11: Enable break point address BAD1 ER01: Enable address range function on BAD0, BAD1 EM01: Set mask BAD0 of break address BAD1 BAD0 12345200H: Set lower break address BAD1 12345300H: Set upper break address BAD2 F0000000H: Set break mask Break occurs at 02345200H to 02345300H, or at 12345200H to 12345300H, or at 22345200H to 22345300H, etc. The resulting setting of the BD[1:0] status bits indicates the point, respective the area in which the break has occurred. Table 13.2-1 Instruction Break Detection Status Bits (BD) BD1 BD0 Break detection address 0 1 Match on start point (instruction address = 12345200H or instruction address = 22345200H etc.) 1 0 Match on end point (instruction address = 12345300H or instruction address = 22345300H etc.) 1 1 Match on range (12345200H < instruction address < 12345300H or 22345200H < instruction address < 22345300H etc.) In the instruction address break mode the following important point has to be considered: To precisely determine the instruction address where a break occurs, use the PC value saved on the stack during entry to the instruction break interrupt service routine. 351 CHAPTER 13 MPU / EDSU 13.2.2 Operand Address Break Four breakpoints or less can be defined in the operand address break point. This section describes the setting of the operand address break. The operand address break causes a break for the data access address which can be specified by the operand address break registers BAD[3:0]. Setting the CTC[1:0] bits of the control register BCR0 to "01B" provides this mode. The bits EP[3:0] in BCR0 enable the break points. Up to 4 breakpoints from channels 0 to 3 can be set. All operand break events are ORed into a operand break exception interrupt request to the CPU. Example: CTC01: Type: Operand Address Break EP11: Enable break point address BAD0 EM01: Enable break point address BAD1 BAD1 12345678H: Set break address BAD0 00000FFFH: Set break mask Break occurs at 12345000H to 12345FFFH On break at BAD[3:0] the respective flags BD[3:0] in the break interrupt request register BIRQ will be set to "1". They have to be reset by software in the operand break exception routine. ■ Address Range Match Function Setting Channels 0 and 1 (BAD0, BAD1) function as address range match when setting the ER0 bit of the control register BCR0 to "1". BAD0 is the lower address and BAD1 is the upper address for address comparison. The mask register BAD2 will mask both channels 0 and 1, if the mask feature is enabled by EM0 = 1. Alternatively, channels 2 and 3 (BAD2, BAD3) function as address range match when setting the ER1 bit of the control register BCR0 to "1". BAD2 is the lower address and BAD3 is the upper address for address comparison. The mask register BAD0 will mask both channels 2 and 3, if the mask feature is enabled by EM1 = 1. Example: CTC01: Type: Operand Address Break EP01: Enable break point on BAD0 EP11: Enable break point on BAD1 ER01: Enable address range function on BAD0, BAD1 EM01: Enable address mask function on BAD0, BAD1 BAD0 12345200H: Set lower break address BAD1 12345300H: Set upper break address BAD2 F0000000H: Set break mask 352 CHAPTER 13 MPU / EDSU Break occurs at 02345200H to 02345300H, or at 12345200H to 12345300H, or at 22345200H to 22345300H, etc. The resulting setting of the BD[1:0] status bits indicates the point, respective the area in which the break has occurred. Table 13.2-2 Operand Break Detection Status Bits (BD) BD1 BD0 Break detection address 0 1 Match on start point (operand address = 12345200H or operand address = 22345200H etc.) 1 0 Match on end point (operand address = 12345300H or operand address = 22345300H etc.) 1 1 Match on range (12345200H < operand address < 12345300H or 22345200H < operand address < 22345300H etc.) The access data length and read/write break attributes can also be specified by bits OBS[1:0] and OBT[1:0] of the control register BCR0. When the mask function is disabled by setting EM1 = EM0 = 0 (all bits effective), the relationship between breakpoint setting, and break by access address is shown below: Table 13.2-3 Operand Size and Operand Address Relations Access data length 8bit 16bit 32bit Access address Address set in BOA0, BOA1 4n + 0 4n + 1 4n + 2 4n + 3 4n + 0 Hit - - - 4n + 1 - Hit - - 4n + 2 - - Hit - 4n + 3 - - - Hit 4n + 0 Hit Hit - - 4n + 1 Hit Hit - - 4n + 2 - - Hit Hit 4n + 3 - - Hit Hit 4n + 0 Hit Hit Hit Hit 4n + 1 Hit Hit Hit Hit 4n + 2 Hit Hit Hit Hit 4n + 3 Hit Hit Hit Hit In Operand address break mode the Operand Address, causing the break is captured in the BOAC register. Additional BIAC holds the instruction address of the instruction, which was executed one cycle before the break causing data operation. This is normally the instruction, which has caused the data transfer. 353 CHAPTER 13 MPU / EDSU In the operand address break the following important points have to be considered: 1. In the FR family architecture, if data access is performed with misalignment, the lower address bit 0 will be ignored for halfword and the lower address bits 0 and 1 for word access. The mask register could be programmed accordingly. 2. The EDSU operand break does not always occur immediately after completion of execution of the instruction causing the break event. 3. Please see also information at "13.2.4 Using Operand with Data Break". 354 CHAPTER 13 MPU / EDSU 13.2.3 Data Value Break Two breakpoints or less can be defined in the data value break point. This section describes the setting of the data value break point. The data value break causes a break if specified data is read or written at a data access to an address specified by the CPU. The data can be specified by the data value break registers BAD0 and BAD1. Setting the CTC[1:0] bits of the control register BCR0 to "11B" provides this mode. The bits EP0 and EP1 in BCR0 enable the break condition. Up to 2 break points from channels 0 to 1 can be set. All data value break events are ORed into a operand break exception to the CPU. 1 mask register (BAD0) is available for masking the data value (stored in BAD1) and 1 mask register (BAD2) is available for masking the operand address (BAD3) which is being accessed. Mask registers BAD2 and BAD0 can be enabled with EM1 and EM0. The data on which a break should be executed must be masked by a data-mask on the bus, requiring 32-bit setting considering the address and data length (see Table 13.2-4 ). This is required due to the byte position of the operand is dependent from the operand address. The setting of data length of the control register BCR0:OBS[1:0] could be configured to all ignored. The data length is controllable by mask setting to the BAD0 register implicitly. On break at BAD[1:0] the respective flags BD[1:0] in the break interrupt request register BIRQ will be set to "1". They have to be reset by software in the operand break exception routine. In Operand data value break the Operand Address, causing the break is captured in the BOAC register. Additional BIAC holds the address of the instruction, which was executed one cycle before the break causing data operation. This is normally the instruction, which has caused the data transfer. In the data value break mode the following important points have to be considered: 1. The data value break is also executed for matching DMA transfers. This could lead to unexpected behavior due to parallel processes. The filter bits FDMA and FCPU could be set for dedicated investigations. 2. The EDSU data break does not always occur immediately after completion of execution of the instruction causing the break event. 3. Please see also information at "13.2.4 Using Operand with Data Break". 355 CHAPTER 13 MPU / EDSU Table 13.2-4 Relation between BAD Register and Mask Access data length 8bit 16bit 32bit Address set to BAD3/BAD2 MASK set to BAD0 Position of valid data in BAD1/BAD0 (indicated by *) 4n + 0 00FFFFFFH **-- ---- 4n + 1 FF00FFFFH --** ---- 4n + 2 FFFF00FFH ---- **-- 4n + 3 FFFFFF00H ---- --** 4n + 0 0000FFFFH **** ---- 4n + 1 0000FFFFH **** ---- 4n + 2 FFFF0000H ---- **** 4n + 3 FFFF0000H ---- **** 4n + 0 00000000H **** **** 4n + 1 00000000H **** **** 4n + 2 00000000H **** **** 4n + 3 00000000H **** **** Remarks − Possibly intended to use address mask in BAD3 for address bit0 Possibly intended to use address mask in BAD3 for address bit1 and bit0; Data mask not required, two channels could be used Note: 1. The mask values for the BAD0 register in the table are a minimum set of bits. Setting more masking bits permits masking bits not needed to be compared with transfer data. 2. "Position of valid data in BAD1, BAD0" provides an 8-bit hexadecimal image for MSB on the left and LSB on the right. Data at bit positions indicated by * in the BAD1, BAD0 registers is compared with data on the data bus, according to the access data length and access address. 356 CHAPTER 13 MPU / EDSU 13.2.4 Using Operand with Data Break This section describes the setting when the data value break is used together with the operand address break. By setting the combination of EP3 and EP1, or the combination of EP2 and EP0, or both combinations, and then setting CTC = 11B and COMB = 1, the data value break can be used together with the operand address break. In other words: a break in channel 0 will occur at a match on operand address in BAD2 and a match on data value in BAD0. A break in channel 1 will occur at a match on operand address in BAD3 and a match on data value in BAD1. It is not possible to mix them vice versa. On break both BD0 and BD2, respective BD1 and BD3 are set. They have to be reset by software in the operand break exception routine. Table 13.2-5 Operand Address and Data Value Break Combinations EP3/EP2 EP1/EP0 COMB Function 0 0 0 No break detection 0 1 0 Independent data break (match value on any operand address) 1 0 0 Independent Operand break (match operand address) 1 1 0 Independent Data break and Operand break 0 0 1 No break detection 0 1 1 No break detection 1 0 1 No break detection 1 1 1 Data value break (match both operand address and value) 357 CHAPTER 13 MPU / EDSU 13.2.5 Memory Protection This section describes the memory protection. Due to the availability of address range comparators for the operand and instruction addresses the wish is obvious, to use the same comparator hardware as a memory protection unit (MPU). Following table list the possible type configurations and its feasibility to be used for memory protection. The number of break points and MPU channels is valid for 8 comparator groups implemented. Table 13.2-6 Comparator Type Configuration CTC CMP1 Input CMP0 Input Max. Break Points (MPE=0) 00 IA IA 32 Instruction breaks 16 ranges with execute permissions 01 OA OA 32 Operand breaks 16 ranges with read/write permissions 10 OA IA 16 + 16 IA/OA breaks 8 ranges with read/write and execute permissions or 8+8 independent ranges 11 OA DT 16 data value breaks - Max. MPU Channels (MPE=1) In addition to the existing functions, there is an extended function to allow users to read/write/set permissions to the operand break size including the read-modify-write (RMW) instruction or to the bus corresponding to the OBS/OBT type. Permissions can be set for the comparator channel CMP1 and CMP0 separately, indicated by the symbol index. Table 13.2-7 Meaning of the Permission Config Bits Symbol Data Mode (OA) Instruction Mode (IA) SRX[1:0] SuperVisor Read permission SuperVisor execute permission SW[1:0] SuperVisor Write permission - URX[1:0] User Read permission User execute permission UW[1:0] User Write permission - At each time an instruction is executed or an operand is accessed, the actual valid permissions were evaluated. This setting is divided into operand access (OA-based) and code execution (IA-based). For each part the highest priority region hit is searched for. The highest channel number has the highest priority. If a channel hit was found, the permissions defined for this channel will apply. If no channel hit was detected, the default permissions apply. After the permissions are set (valid for actual instruction if there is a data access.) the accesses were checked. If the execute permission is not set or if the read or write permissions do not fit to the type of the actual access, a protection violation will be indicated. This causes a CPU trap to the memory protection violation MPUPV handler routine. The CPU switches directly to SuperVisor mode in this case. 358 CHAPTER 13 MPU / EDSU The config register space of the EDSU is protected against random access in User mode. Only in SuperVisor mode or Emulation mode the register file enables write access. In this interruption, a system interrupt INT #5 was defined, which switches in SuperVisor mode (SV bit remains set during the execution of the INT #5-ISR). Except debugger interrupts by the emulator and NMI the SuperVisor ISR is not interruptible. Exceptions caused by the memory protection and the break unit for debugging are separated. In that way the memory protection functionality can be debugged itself. 359 CHAPTER 13 MPU / EDSU 13.2.6 Break Factors This section describes the relation between the break factor and the interruption vector. Summary of the internal break factors and the executed events: Break on instruction address → Causes Instruction Break Break on operand address → Causes Operand Break Break on data value → Causes Operand Break Resource Interrupt (BREAK) → Causes Tool NMI Step Trace Trap → Causes Step Trace Trap Execution of the INTE instr. → Causes INTE Execution of INT #5 → CPU SuperVisor Mode Memory protection exception → Causes MPUPV Trap Table 13.2-8 Interrupt Numbers and Interrupt Vectors of Break Factors Interrupt number Interrupt Interrupt level Interrupt vector Decimal Hexadecimal Setting Register Register address Offset Default Vector address CPU supervisor mode (INT #5 instruction) 5 05 - - 3E8H 000FFFE8H Memory protection exception 6 06 - - 3E4H 000FFFE4H INTE instruction 9 09 - - 3D8H 000FFFD8H Instruction break exception 10 0A - - 3D4H 000FFFD4H Operand break exception 11 0B - - 3D0H 000FFFD0H Step trace trap 12 0C - - 3CCH 000FFFCCH NMI interrupt (tool) 13 0D - - 3C8H 000FFFC8H 360 CHAPTER 13 MPU / EDSU 13.3 EDSU Registers This section describes the bit configuration and functions of the EDSU registers. Table 13.3-1 Lists of EDSU Registers (1 / 3) Register Address Block +0 +1 +2 F000H BCTRL [R/W] -------- -------- 11111100 00000000 F004H BSTAT [R/W0]* -------- -----000 00000000 10--0000 F008H BIAC [R] 00000000 00000000 00000000 00000000 F00CH BOAC [R] 00000000 00000000 00000000 00000000 F010H BIRQ [R/W] 00000000 00000000 00000000 00000000 F014H to F01FH reserved - F020H BCR0 [R/W] -------- 00000000 00000000 00000000 F024H BCR1 [R/W] -------- 00000000 00000000 00000000 F028H BCR2 [R/W] -------- 00000000 00000000 00000000 F02CH BCR3 [R/W] -------- 00000000 00000000 00000000 F030H BCR4 [R/W] -------- 00000000 00000000 00000000 F034H BCR5 [R/W] -------- 00000000 00000000 00000000 F038H BCR6 [R/W] -------- 00000000 00000000 00000000 F03CH BCR7 [R/W] -------- 00000000 00000000 00000000 F040H to F07FH +3 EDSU reserved - 361 CHAPTER 13 MPU / EDSU Table 13.3-1 Lists of EDSU Registers (2 / 3) Register Address Block +0 +1 +2 +3 F080H BAD0 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX F084H BAD1 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX F088H BAD2 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX F08CH BAD3 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX F090H BAD4 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX F094H BAD5 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX F098H BAD6 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX F09CH BAD7 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX F0A0H BAD8 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX F0A4H BAD9 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX F0A8H BAD10 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX F0ACH BAD11 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX F0B0H BAD12 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX F0B4H BAD13 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX F0B8H BAD14 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX F0BCH BAD15 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 362 EDSU CHAPTER 13 MPU / EDSU Table 13.3-1 Lists of EDSU Registers (3 / 3) Register Address Block +0 +1 +2 +3 F0C0H BAD16 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX F0C4H BAD17 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX F0C8H BAD18 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX F0CCH BAD19 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX F0D0H BAD20 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX F0D4H BAD21 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX F0D8H BAD22 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX F0DCH BAD23 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX F0E0H BAD24 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX F0E4H BAD25 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX F0E8H BAD26 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX F0ECH BAD27 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX F0F0H BAD28 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX F0F4H BAD29 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX F0F8H BAD30 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX F0FCH BAD31 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX EDSU *: Read returns "1". For write only "0" (clear) is supported. Note: Read and write access to all registers is byte, halfword and word. 363 CHAPTER 13 MPU / EDSU 13.3.1 EDSU Control Register (BCTRL) This section describes the bit configuration and functions of the EDSU control register (BCTRL). Figure 13.3-1 Bit Configuration of EDSU Control Register (BCTRL) EDSU Control Register byte 2 bit 15 14 13 12 11 10 9 8 SR SW SX UR UW UX FCPU FDMA Address: F002H Read/write → (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (1) (1) (1) (1) (1) (1) (0) (0) Initial value → bit EDSU Control Register byte 3 Address: F003H Read/write → Initial value → 7 6 EEMM PFD 5 4 SINT1 SINT0 3 2 − EINT0 1 0 EINTT EINTR (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (0) (0) (0) (0) (0) (0) (0) (0) The default permission register defines the lowest priority access permissions for the whole memory and I/O address range of the MCU. Lowest priority means, that the access take effect for all address regions, which are NOT covered by any dedicated channel configuration, operating in MPU mode. Read, write and execute permissions could be defined for the super visor mode (SV=1) and the normal user mode (SV=0). The super visor mode (SV) is indicated by bit 6 of the CCR in the program status word of the CPU. After the INIT condition all permissions are set (access allowed). [bit15] SR: Super visor Read permission register 0 Super visor is not permitted to read data 1 Super visor is permitted to read data (Initial value) [bit14] SW: Super visor Write permission register 0 Super visor is not permitted to write data 1 Super visor is permitted to write data (Initial value) [bit13] SX: Super visor eXecute permission register 364 0 Super visor is not permitted to execute code 1 Super visor is permitted to execute code (Initial value) CHAPTER 13 MPU / EDSU [bit12] UR: User Read permission register 0 User is not permitted to read data 1 User is permitted to read data (Initial value) [bit11] UW: User Write permission register 0 User is not permitted to write data 1 User is permitted to write data (Initial value) [bit10] UX: User eXecute permission register 0 User is not permitted to execute code 1 User is permitted to execute code (Initial value) CPU and DMA Filter Option Register [bit9] FCPU: Filter CPU access 0 Trigger on CPU accesses (Initial value) 1 Do not trigger on CPU accesses FCPU controls the filter operation for CPU accesses triggered by operand compare channels (Operand address break, data value break and memory data protection). If FCPU is set to "1", all CPU accesses are masked out. If set to "0" CPU accesses can cause break function. [bit8] FDMA: Filter DMA access 0 Trigger on DMA accesses (Initial value) 1 Do not trigger on DMA accesses FDMA controls the filter operation for DMA accesses triggered by operand compare channels (Operand address break, data value break and memory data protection). If FDMA is set to "1", all DMA accesses are masked out. If set to "0" DMA accesses can cause break function. Note: Only DMA accesses over D-bus were detected. The operands for DMA trigger condition have to be located in the D-bus address area. Otherwise the DMA transfer could not be recognized by the EDSU. This function was mainly intended to disable the trigger on DMA accesses (filter out the operand change condition by DMA). 365 CHAPTER 13 MPU / EDSU [bit7] EEMM: Enable Emulation Mode 0 Disable emulation mode (Initial value) 1 Enable emulation mode If EEMM is set to "1" then the emulation mode is entered during Step Trace Mode and EDSU exceptions Instruction Break, Operand Break and Tool NMI. During emulation mode the Watchdog Timer (WDT) is disabled. EDSU triggered emulation mode is left with the RETI instruction. Set to "0" disables emulation mode function. The WDT is not stopped during Step Trace and EDSU exceptions. [bit6] PFD: Phantom Filter Disable 0 Instruction break detection uses phantom filter (Initial value) 1 Phantome Filter disabled The initial value (PFD = 0) is used to filter out any apparent interrupts or wrong bits. • The instruction fetched, after RETI was executed, is normally the instruction on which the break point was set. Fetch is repeated after processing the breakpoint handler ISR before executing the instruction at the break point. The filter avoids that the trigger of the break condition will be repeated. • Not granted Instruction Break exceptions are timed out - Pre-fetched, but not executed commands - Commands after delayed slot instruction • Consecutive break conditions which are pre-fetched are not allowed to set flags. Only the instruction at which the break condition occurs at first time can set status bits accordingly. • Nested Instruction breaks are not allowed (break within the break handler ISR) [bit5, bit4] SINT[1:0]: Select resource INTerrupt source SINT[1:0] MB91461 Resource 00 Tool NMI by interrupt on source 0 selected (default) UART0 RX / UART0 TX 01 Tool NMI by interrupt on source 1 selected UART1 RX / UART1 TX 10 Tool NMI by interrupt on source 2 selected UART08 RX / TX 11 Tool NMI by interrupt on source 3 selected CAN0 / CAN1 SINT[1:0] MB91F467R Resource 00 Tool NMI by interrupt on source 0 selected (default) UART00 RX / TX 01 Tool NMI by interrupt on source 1 selected UART01 RX / TX 10 Tool NMI by interrupt on source 2 selected UART02 RX / TX 11 Tool NMI by interrupt on source 3 selected CAN0 / CAN1 SINT1 and SINT0 select the active resource interrupt source. 366 CHAPTER 13 MPU / EDSU [bit2] EINT0: Enable extended INTerrupt 0 0 Disable extended interrupt source 0 (Initial value) 1 Enable extended interrupt source 0 If EINT0 is set to "1" then a Tool NMI will be generated on an extended interrupt event at source channel 0. Set to "0" disables this function. Note: EINT1 and EINT0 can be used for indicating a signal line event which can be used for generating a BREAK function. The sources of these interrupts are hardwired in the MCU and can be for example: external interrupt ports, general purpose I/O port pins, other resources, etc. This has to be defined in the device specification. [bit1] EINTT: Enable INTerrupt on Transmit 0 Disable transmit interrupt source channels 0 to 3 (Initial value) 1 Enable transmit interrupt source channels 0 to 3 If EINTT is set to "1" then a Tool NMI will be generated on a transmit interrupt event at source channels 0 to 3 set by TXINT[1:0]. Setting EINTT to "0" disables this function. Note: If SINT[1:0] is set to "11B" this bit enables the interrupt of CAN channel 1 (CAN has one interrupt request for both reception and transmission). [bit0] EINTR: Enable INTerrupt on Receive 0 Disable receive interrupt source channels 0 to 3 (Initial value) 1 Enable receive interrupt source channels 0 to 3 If EINTR is set to "1" then a Tool NMI will be generated on a receive interrupt event at source channels 0 to 3 set by RXINT[1:0]. Setting EINTR to "0" disables this function. Note: If SINT[1:0] is set to "11B" this bit enables the interrupt of CAN channel 0 (CAN has one interrupt request for both reception and transmission). 367 CHAPTER 13 MPU / EDSU 13.3.2 EDSU Status Register (BSTAT) This section describes the bit configuration and functions of the EDSU status register (BSTAT). Figure 13.3-2 Bit Configuration of EDSU Status Register (BSTAT) EDSU Status Register byte 2 bit Address: F006H Read/write → Initial value → bit EDSU Status Register byte 3 Address: F007H Read/write → Initial value → 15 14 13 12 11 10 9 8 IDX4 IDX3 IDX2 IDX1 IDX0 CDMA CSZ1 CSZ0 (R) (0) (R) (0) (R) (0) (R) (0) (R) (0) (R) (0) (R) (0) (R) (0) 7 6 5 4 3 2 1 0 PV RST INT1 INT0 INTT INTR (R) (0) (R) (0) CRW1 CRW0 (R ) (0) (R ) (0) (R/W) (R/W) (R/W) (R/W) (0) (1) (0) (0) [bit15 to bit11] IDX[4:0]: Channel Index Indication of MPUPV Trigger In the case of triggering a memory protection violation (MPUPV), the index of the channel pair 0 to 15 is saved in The IDX register, which caused the trigger. The channel pairs are normally used as range comparators. If no MPU channel has detected a hit on its address range, the default permissions apply. If the default permissions are violated, IDX is set to the value 16 (overrun). If the permissions of a matching MPU channel are violated, IDX shows the index of the appropriate break detection bits BIRQ_BD[31:0]. The break detection bits belonging to this comparator are BD[2 x IDX] and BD[2 x IDX+1]. In case of multiple range hits and/or trigger conditions, the channel with the highest priority trigger condition is indicated by IDX[4:0]. The priority raises with the channel index. IDX 0XXXXB 10000B Description Points to the channel number of the last protection violation The last protection violation was caused by the violation of the default permissions The channel index indication register is read only. [bit10] CDMA: Capture DMA Indication 368 0 The operand access was executed by the CPU 1 The operand access was executed by the DMA controller CHAPTER 13 MPU / EDSU [bit9, bit8] CSZ[1:0]: - Capture Operand Size 00 The operand has a bit size of 8 01 The operand has a bit size of 16 10 The operand has a bit size of 32 11 Reserved [bit7, bit6] CRW[1:0]: Capture Operand Access Type 00 The operand has been read 01 The operand has been read by read-modify-write (RMW) instruction 10 The operand has been written 11 no operand access [bit5] PV: Protection Violation Detection 0 There was no protection violation on read, write and execute permissions 1 A protection violation (MPUPV) has been occurred If PV is set "1" after a protection violation, a MPUPV trap is indicated to the CPU. The occurrence of a protection violation means, that there was a read or write access to a defined address region, which was not permitted or instruction was executed without execute permissions for this address region. As consequence the CPU switches to super visor mode (SV=1) and calls the handler routine for interrupt number #6 (see Table 13.2-8 ). This bit should be cleared by writing "0" in the MPUPV trap handler routine. [bit4] RST: Operation Initialization Reset (RST) Detection The reset operation of FR family is divided into two levels, setting initialization reset (INIT) and operation initialization reset (RST). When INIT occurs, RST occurs at the same time implicitly. 0 Operation Reset was not triggered since last BSTAT read or clear 1 Operation Reset was triggered since last BSTAT read or clear The RST bit is read only, any write access to this bit will be ignored. RST is cleared after BSTAT is read (read from any byte address within the 32 bit word). RST has same behavior for read and readmodify-write (RMW) instruction. The RST bit can be used for reset detection. It is set in any case of operation initialization reset is triggered. Debug monitor software can use this to detect if the communication device to the debugger front end needs to be re-configured after an operation reset. This is important for debugging of boot procedures and soft reset handling. After reading the EDSU status word the RST bit is cleared automatically. 369 CHAPTER 13 MPU / EDSU [bit3] INT1: INTerrupt of extended source 1 0 Interrupt on extended source channel 1 not detected (Initial value) 1 Interrupt on extended source channel 1 detected INT1 reflects the status of the extended interrupt source channel 1. It is set to "1" if a high level on the extended interrupt signal line has been occurred. This setting is stored until cleared by software. Writing "0" resets the INT1 bit to "0". Writing "1" to this bit is ignored. On a read-modify-write (RMW) instruction INT1 is read as "1". [bit2] INT0: INTerrupt of extended source 0 0 Interrupt on extended source channel 0 not detected (Initial value) 1 Interrupt on extended source channel 0 detected INT0 reflects the status of the extended interrupt source channel 0. It is set to "1" if a high level on the extended interrupt signal line has been occurred. This setting is stored until cleared by software. Writing "0" resets the INT0 bit to "0". Writing "1" to this bit is ignored. On a read-modify-write (RMW) instruction INT0 is read as "1". [bit1] INTT: INTerrupt of Transmit source 0 Interrupt on transmit source not detected (Initial value) 1 Interrupt on transmit source channel detected INTT reflects the status of the transmit interrupt source channels 0 to 3 (can be selected by TXINT[1:0]). It is set to "1" on a high level on the transmit interrupt signal line and "0" on a low level on the signal line. This bit is read-only. It can be set to "0" by clearing the appropriate interrupt bit in the selected resource. Note: If SINT[1:0] is set to "11B" this bit indicates the interrupt of CAN channel 1 (CAN has one interrupt request for both reception and transmission). 370 CHAPTER 13 MPU / EDSU [bit0] INTR: INTerrupt of Receive source 0 Interrupt on receive source not detected (Initial value) 1 Interrupt on receive source channel detected INTR reflects the status of the receive interrupt source channels 0 to 3 (can be selected by RXINT[1:0]). It is set to "1" on a high level on the receive interrupt signal line and "0" on a low level on the signal line. This bit is read-only. It can be set to "0" by clearing the appropriate interrupt bit in the selected resource. Note: If SINT[1:0] is set to "11B" this bit indicates the interrupt of CAN channel 1 (CAN has one interrupt request for both reception and transmission). 371 CHAPTER 13 MPU / EDSU 13.3.3 EDSU Break Detection Interrupt Request Register (BIRQ) This section describes the bit configuration and functions of the EDSU break detection interrupt request register (BIRQ). This register collects all break detection bits of all channels, regardless of the type configuration of each channel. The implementation consists of 8 groups of channels, that are 32 single point channels totally. Each group of channels consists of 4 channels and 4 bits for break detection in the BIRQ register. Each group has two comparator pairs. Each pair consists of two point comparators which could build a range comparator by setting the range enable bit. Such a range comparator pair is connected to the instruction address, operand address or the data value information - selected by the comparator type configuration. For detection of combined operand address and data value breaks two of such comparator pairs are combined together. Than the break detection (BD) bits are set only if both conditions are matching simultaneously. [bit31:0] BD[31:0]: Break Detection register 0 Break factor not detected (Initial value) 1 Break factor detected on channel according the bit position [31:0] BD[31:0] reflects the status of the break detection. It is set to "1" at match with BAD31 to BAD0 accordingly (and if the mask condition is satisfied, if enabled by EM1/EM0). For bit pairs [31:30], [29:28], ..., [1:0] range matches could apply, if the range function using two points is enabled by ER1/ ER0. Break factors could be • instruction address break • operand address break • data value break • combined operand address and data value break • memory protection violation Writing "0" resets the BD[31:0] bits to "0". Writing "1" to these bits is ignored. On a read-modify-write (RMW) instruction all BD bits are read as "1". BD1/BD0 setting at enabled address range function (also valid for the other pairs of BD bits in neighbourhood): 372 CHAPTER 13 MPU / EDSU If the operand address range function is enabled with ER0 in addition to the point enables EP1 and EP0, then the BD1 and BD0 detection bits are set in the following manner: Table 13.3-2 BD Coding for Match on Start/Endpoint or Range BD1 BD0 Compare value: Instruction, Operand Address, Data Value 0 0 No match (Initial value) 0 1 Match on point (compare value == BAD0) 1 0 Match on point (compare value == BAD1) 1 1 Match on range (BAD0 < compare value < BAD1) 373 CHAPTER 13 MPU / EDSU 13.3.4 EDSU Channel Configuration Register (BCR0 to BCR7) This section describes the bit configuration and functions of the EDSU channel configuration register (BCR0 to BCR7). Figure 13.3-3 Bit Configuration of EDSU Channel Configuration Register (BCR0 to BCR7) EDSU Ch. Config Register 0, byte 0 bit Address: F020H Read/write → Initial value → EDSU Ch. Config Register 0, byte 1 bit Address: F021H Read/write → Initial value → EDSU Ch. Config Register 0, byte 2 bit Address: F022H 31 30 29 28 27 26 25 24 - - - - - - - - (-) (X) (-) (X) (-) (X) (-) (X) (-) (X) (-) (X) (-) (X) (-) (X) 23 22 21 20 19 18 17 16 SRX1 SW1 SRX0 SW0 URX1 UW1 URX0 UW0 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (0) (0) (0) (0) (0) (0) (0) (0) 15 14 13 12 11 10 9 8 MPE COMB CTC1 CTC0 OBS1 OBS0 OBT1 OBT0 Read/write → (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (0) (0) (0) (0) (0) (0) (0) Initial value → (0) EDSU Ch. Config Register 0, byte 3 bit Address: F023H Read/write → Initial value → 7 6 5 4 3 2 1 0 EP3 EP2 EP1 EP0 EM1 EM0 ER1 ER0 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (0) (0) (0) (0) (0) (0) (0) (0) For each group of four channels channel configuration register (BCR0 to BCR7) is implemented. The following table shows the channel configuration, break point address/data registers and break detection bits belong together. Table 13.3-3 Relationship of BCR, BAD and BIRQ Registers (1 / 2) Group Config BCR0 374 Address/Data BADx Usage Point BAD0 Point0, Mask0 EP0 BAD1 Point1 EP1 BAD2 Point2, Mask1 EP2 BAD3 Point3 EP3 Mask Combination EM0 range 0 ER0 EM1 range 1 ER1 BIRQ OA0 BD0 OA1 BD1 DT0 BD2 DT1 BD3 CHAPTER 13 MPU / EDSU Table 13.3-3 Relationship of BCR, BAD and BIRQ Registers (2 / 2) Group Config BCR1 BCR2 BCR3 BCR4 BCR5 BCR6 BCR7 Address/Data BADx Usage Point BAD4 Point0, Mask0 EP0 BAD5 Point1 EP1 BAD6 Point2, Mask1 EP2 BAD7 Point3 EP3 BAD8 Point0, Mask0 EP0 BAD9 Point1 EP1 BAD10 Point2, Mask1 EP2 BAD11 Point3 EP3 BAD12 Point0, Mask0 EP0 BAD13 Point1 EP1 BAD14 Point2, Mask1 EP2 BAD15 Point3 EP3 BAD16 Point0, Mask0 EP0 BAD17 Point1 EP1 BAD18 Point2, Mask1 EP2 BAD19 Point3 EP3 BAD20 Point0, Mask0 EP0 BAD21 Point1 EP1 BAD22 Point2, Mask1 EP2 BAD23 Point3 EP3 BAD24 Point0, Mask0 EP0 BAD25 Point1 EP1 BAD26 Point2, Mask1 EP2 BAD27 Point3 EP3 BAD28 Point0, Mask0 EP0 BAD29 Point1 EP1 BAD30 Point2, Mask1 EP2 BAD31 Point3 EP3 Mask Combination BIRQ OA0 BD4 OA1 BD5 range 1 ER1 DT0 BD6 DT1 BD7 EM0 range 0 ER0 OA0 BD8 OA1 BD9 EM1 range 1 ER1 DT0 BD10 DT1 BD11 EM0 range 0 ER0 OA0 BD12 OA1 BD13 EM1 range 1 ER1 DT0 BD14 DT1 BD15 EM0 range 0 ER0 OA0 BD16 OA1 BD17 EM1 range 1 ER1 DT0 BD18 DT1 BD19 EM0 range 0 ER0 OA0 BD20 OA1 BD21 EM1 range 1 ER1 DT0 BD22 DT1 BD23 EM0 range 0 ER0 OA0 BD24 OA1 BD25 EM1 range 1 ER1 DT0 BD26 DT1 BD27 EM0 range 0 ER0 OA0 BD28 OA1 BD29 EM1 range 1 ER1 DT0 BD30 DT1 BD31 EM0 range 0 ER0 EM1 375 CHAPTER 13 MPU / EDSU The permission definition registers are valid only for the group of channels operating in MPU mode. This is the case if MPE is set to "1". If the group does not operate in MPU mode, the permission configuration is not required (don’t care). Normally MPU channels operate in range mode for the address definitions. The type of the permission, which could be set-up, depends on the comparator type configuration (CTC) for each comparator pair. MPU channels could be configured either to check instruction addresses (IA) or operand addresses (OA). IA ranges could be used to define execute permissions. OA ranges could be used to define read and write permissions. The comparator type for MPU usage could be set to • CTC=0: both IA ranges define execute permissions • CTC=1: both OA ranges define read/write permissions • CTC=2: IA range 0 defines execute permissions and OA range 1 defines read/write permissions. Data value (DT) detection by setting CTC=3 is not possible to use in MPU mode. Permission configurations exist for read, write and execute for two CPU modes, the super visor mode and the user mode. Super visor permissions are valid for SV=1 and user permissions are set by SV=0. [bit23] SRX1: Super visor Read/eXecute permission register for range 1 Setting valid for CTC = 0 (Instruction address range comparator): 0 Super visor has no execute permission on address range 1 (Initial value) 1 Super visor has execute permission on address range 1 Setting valid for CTC = 1 or CTC = 2 (Operand address range comparator): 0 Super visor has no read permission on address range 1 (Initial value) 1 Super visor has read permission on address range 1 [bit22] SW1: Super visor Write permission register for range 1 Setting valid for CTC = 1 or CTC = 2 (Operand address range comparator): 0 Super visor has no write permission on address range 1 (Initial value) 1 Super visor has write permission on address range 1 [bit21] SRX0: Super visor Read/eXecute permission register for range 0 Setting valid for CTC = 0 or CTC = 2 (Instruction address range comparator): 0 Super visor has no execute permission on address range 0 (Initial value) 1 Super visor has execute permission on address range 0 Setting valid for CTC = 1 (Operand address range comparator): 376 0 Super visor has no read permission on address range 0 (Initial value) 1 Super visor has read permission on address range 0 CHAPTER 13 MPU / EDSU [bit20] SW1: Super visor Write permission register for range 0 Setting valid for CTC = 1 (Operand address range comparator): 0 Super visor has no write permission on address range 0 (Initial value) 1 Super visor has write permission on address range 0 [bit19] URX1: User Read/eXecute permission register for range 1 Setting valid for CTC = 0 (Instruction address range comparator): 0 User has no execute permission on address range 1 (Initial value) 1 User has execute permission on address range 1 Setting valid for CTC = 1 or CTC = 2 (Operand address range comparator): 0 User has no read permission on address range 1 (Initial value) 1 User has read permission on address range 1 [bit18] UW1: User Write permission register for range 1 Setting valid for CTC = 1 or CTC = 2 (Operand address range comparator): 0 User has no write permission on address range 1 (Initial value) 1 User has write permission on address range 1 [bit17] URX0: User Read/eXecute permission register for range 0 Setting valid for CTC = 0 or CTC = 2 (Instruction address range comparator): 0 User has no execute permission on address range 0 (Initial value) 1 User has execute permission on address range 0 Setting valid for CTC = 1 (Operand address range comparator): 0 User has no read permission on address range 0 (Initial value) 1 User has read permission on address range 0 [bit16] UW1: User Write permission register for range 0 Setting valid for CTC = 1 (Operand address range comparator): 0 User has no write permission on address range 0 (Initial value) 1 User has write permission on address range 0 377 CHAPTER 13 MPU / EDSU [bit15] MPE: Memory Protection Enable 0 The group of channels operates as a debug interface and defines break points (Initial value) 1 The group of channels operates in the memory protection mode Some restrictions apply with the setting of the MPE bit. MPE=0 (break unit): permission registers are don’t care (BCRx bits [23:16]) MPE=1 (memory protection unit): OBS and OBT should be set to "11B" (BCRx bits [11:8], any size and any type) CTC should not be set to "11B" (BCRx bits [13:12], data value check not supported in this mode) [bit14] COMB: Channel Combination Enable 0 No combination between channels (Initial value) 1 Combination between channels is effective Depending on the MPE configuration bit the COMB feature has different meaning. (A) COMB=1 and MPE=0 (break unit, combined operand address and data value break): The break detection conditions are combined before setting the BIRQ_BD bits and signalizing an operand break condition. Setting the COMB bit is required for defining a data value break on a specific operand address. If the COMB bit is set to "1", both conditions, matching operand address (OA) and matching data value (DT), are required to be true. Setting the COMB bit makes only sense in the OA/ DT mode, defined by CTC=11B. The AND-combination is effective between channels 3 (OA1) and 1 (DT1) and between channels 2 (OA0) and 0 (DT0). It is assumed that no range operation is defined (ER1=ER0=0). BIRQ_BD3 = BIRQ_BD1 = BD3 && BD1; BIRQ_BD2 = BIRQ_BD0 = BD2 && BD0; If channels 3 and 2 define an operand address range (OA1:OA0) by setting ER1=1 and/or channels 1 and 0 define a data value range (DT1:DT0) by setting ER0=1, the break detection bits of each channel are AND-combined with the ORed channels of the opposite range comparator break detection outputs. BIRQ_BD3 = BD3 && (BD1 || BD0); BIRQ_BD2 = BD2 && (BD1 || BD0); BIRQ_BD1 = BD1 && (BD3 || BD2); BIRQ_BD0 = BD0 && (BD3 || BD2); This offers the same interpretation of the BIRQ break reduction bits (see Table 13.3-2 for coding of match on start point, range or end point) as it would be the case for range detection with COMB=0. BD3 and BD2 hold the coding for the operand address (OA) match, whereas BD1 and BD0 hold the coding for the data value (DT) match. The COMB bit set to "1" ensures that both conditions, the OA match and the DT match must be true to set the appropriate BD bit in the end. If the COMB bit is set to "0" all break detection bits are passed to the BIRQ register in it’s original form. The comparator channels match conditions are independent from each other. 378 CHAPTER 13 MPU / EDSU (B) COMB=1 and MPE=1 (memory protection unit, combined read/write/execute permissions on single range): In memory protection mode the COMB bit has the meaning of combined data read/write and code execute permissions, set for the same address range. The setting is only meaningful for the combination of operand address (OA) comparators on channels 3 and 2 and instruction address (IA) comparators on channels 1 and 2 in the mode CTC=2. The COMB bit set to "1" causes the IA comparator CMP0 to use the same BADx point definitions as the OA comparator CMP1. Point 3 and Point 2 define the address range for both comparators CMP0 and CMP1. This has the effect that the entry of Point 0/Mask 0 is not allocated for the Point set-up and could be used for masking either one or both comparators. The Point 1 entry is not usable in this case. If the COMB bit is set to "0" both comparators have independent address configurations. The comparators can either define read/write permissions for data protection or define execute permissions for code protection. Each comparator can define an address region by a range between two points (ER=1) or by one point with a mask (EM=1). [bit13, bit12] CTC[1:0]: Comparator Type Config CTC CMP1 CMP0 Break Function MPU Function 00B IA IA 4 instruction break points 2 regions for code protection (Execution permissions) 01B OA OA 4 operand break points 2 regions for data protection (Read/write permissions) 10B OA IA 2 instruction break points + 2 operand break points 1 region for code protection (Execution permissions) and 1 region for data protection (Read/write permissions) or 1 region for combined code and data protection (Read/write/execution permissions) 11B OA DT 2 operand break points + 2 data value breaks, normally with combination not applicable Each channel contains 2 range comparator blocks. Each comparator block can detect a range hit between two points or two independent point hits. The point configuration is stored in dedicated BADx registers for each channel (4 BADx registers for each group of channels). The comparator type configuration (CTC) controls the input multiplexing of the compare value for each of the two range comparator blocks CMP1 and CMP0. CMP1 combines the break detection channels 3 and 2. The compare value for CMP1 can be assigned either to the instruction address (IA) or to the operand address (OA). CMP0 combines the break detection channels 1 and 0. The compare value for CMP0 can be assigned to the instruction address (IA), to the operand address (OA) or to the data value (DT). The table above defines the input compare values for CMP1 and CMP0, depending on the CTC setting. In addition a mask for each comparator block could be defined. In this case the BADx register, which contains the mask information, is not available for the point configuration. Thus the usage of the mask feature restricts the number of points or channels, which are available in total. 379 CHAPTER 13 MPU / EDSU [bit11 to bit8] OBS[1:0], OBT[1:0]: Operand Break Size / Operand Break Type register 1 OBS1 OBS0 0 0 0 Data size OBT1 OBT0 Access type Byte (Initial value) 0 0 Read (Initial value) 1 Halfword 0 1 Read-modify-write (RMW) instruction 1 0 Word 1 0 Write 1 1 All (Byte, Hword, Word) 1 1 All (Read, RMW, Write) The operand break size register OBS configures the datasize and the operand break type register OBT configures the access type if the channel is configured to operand address break or data value break detection. Setting to "11B" in datasize will cause detection of byte, halfword and word data sizes. Setting to "11B" in access type will cause detection of Read, Read-modify-write (RMW) instruction and Write access types. [bit7] EP3: Enable break Point 3 register 0 Break point 3 register is disabled (Initial value) 1 Break point 3 register is enabled If EP3 is enabled then the input value of CMP1 will be compared with the point 3 register content (BAD index = 3+group offset, BAD3 for group 0 channel 3, BAD7 for group 1 channel 3, ...). The input value and the point value is masked if the mask function is enabled by EM1. On a compare match a break exception will be executed. CTC and MPE control the selection of the input value and the type of the break exception. [bit6] EP2: Enable break Point 2 register 0 Break point 2 register is disabled (Initial value) 1 Break point 2 register is enabled If EP2 is enabled then the input value of CMP1 will be compared with the point 2 register content (BAD index = 2+group offset, BAD2 for group 0 channel 2, BAD6 for group 1 channel 2, ...). The input value and the point value is masked if the mask function is enabled by EM1. On a compare match a break exception will be executed. CTC and MPE control the selection of the input value and the type of the break exception. EP2 controls in addition to enabling and allocating point 2 the selection of the mask register. Point 2 is also the initial value setting address for storing the CMP1 mask value. But, if point 2 is enabled, the mask could not be stored there and the mask input of CMP1 switches to point 0 (to the opposite comparator). 380 CHAPTER 13 MPU / EDSU [bit5] EP1: Enable break Point 1 register 0 Break point 1 register is disabled (Initial value) 1 Break point 1 register is enabled If EP1 is enabled then the input value of CMP0 will be compared with the point 1 register content (BAD index = 1+group offset, BAD1 for group 0 channel 1, BAD5 for group 1 channel 1, ...). The input value and the point value is masked if the mask function is enabled by EM0. On a compare match a break exception will be executed. CTC and MPE control the selection of the input value and the type of the break exception. [bit4] EP0: Enable break Point 0 register 0 Break point 0 register is disabled (Initial value) 1 Break point 0 register is enabled If EP0 is enabled then the input value of CMP0 will be compared with the point 0 register content (BAD index = 0+group offset, BAD0 for group 0 channel 0, BAD4 for group 1 channel 0, ...). The input value and the point value is masked if the mask function is enabled by EM0. On a compare match a break exception will be executed. CTC and MPE control the selection of the input value and the type of the break exception. EP0 controls in addition to enabling and allocating point 0 the selection of the mask register. Point 0 is also the initial value setting address for storing the CMP0 mask value. But, if point 0 is enabled, the mask could not be stored there and the mask input of CMP0 switches to point 2 (to the opposite comparator). If memory protection is enabled (MPE=1) in conjunction with the combination bit set (COMB=1), the address range is defined by point 3 and point 2 and is valid for both comparators COMB1 and COMB0. So the points 1 and 0 are not required for the range definition of CMP0, independent from the point enable EP0 and EP1, which normally are set in this case. Thus point 0 could be used for storing the mask value for both comparators CMP1 and CMP0 and the exception described in the paragraph above did not apply for this case. [bit3] EM1: Enable Mask for CMP1 0 Mask function for CMP1 is disabled (Initial value) 1 Mask function for CMP1 is enabled If EM1 is enabled the comparator CMP1 matches only these bit positions, which are set to "0" and are not masked by the mask register. All inputs for points and the compare value itself are OR-combined with the value from the mask register. The compare operations point match or range detection are derived based on these OR-masked values. The selection of the appropriate BADx register (point 2 or 0) for the mask value depends on EP2 and ER1. If at least one of both bits are enabled, the mask usage switches to point 0 due to the allocation of point 2. Otherwise the default mask stored in point 2 applies for CMP1. 381 CHAPTER 13 MPU / EDSU [bit2] EM0: Enable Mask for CMP0 0 Mask function for CMP0 is disabled (Initial value) 1 Mask function for CMP0 is enabled If EM0 is enabled the comparator CMP0 matches only these bit positions, which are set to "0" and are not masked by the mask register. All inputs for points and the compare value itself are OR-combined with the value from the mask register. The compare operations point match or range detection are derived based on these OR-masked values. The selection of the appropriate BADx register (point 0 or 2) for the mask value depends on EP0 and ER0. If at least one of both bits are enabled, the mask usage switches to point 2 due to the allocation of point 0. Otherwise the default mask stored in point 0 applies for CMP0. If MPE=1 and COMB=1 the mask is taken from point 0, regardless of the setting of EP0 and ER0. [bit1] ER1: Enable Range for CMP1 0 Range detection CMP1 (channels 2-3) is disabled (Initial value) 1 Range detection CMP1 (channels 2-3) is enabled If ER1 is enabled then the registers BADx, point 3 and point 2 will be used for range comparison: Point 2 <= Compare Value <= Point 3If a mask is set with EM1 then both point registers will be masked with the mask register content. Point 3 and Point 2 are taken from BAD[x+3] and BAD[x+2], the mask is stored in Point 0, BAD[x+0]. The "x" is the group offset and calculates by the group index multiplied with 4. [bit0] ER0: Enable Range for CMP0 0 Range detection CMP0 (channels 0-1) is disabled (Initial value) 1 Range detection CMP0 (channels 0-1) is enabled If ER0 is enabled then the registers BADx, point 1 and point 0 will be used for range comparison: Point 0 <= Compare Value <= Point 1. If a mask is set with EM0 then both point registers will be masked with the mask register content. In the special case of MPE=1 together with COMB=1, Point 1 and Point 0 are taken from the opposite channel BAD[x+3] and BAD[x+2] and the mask is stored in Point 0, BAD[x+0]. Otherwise Point 1 and Point 0 are taken from BAD[x+1] and BAD[x+0], the mask is stored in Point 2, BAD[x+2]. The "x" is the group offset and calculates by the group index multiplied with 4. 382 CHAPTER 13 MPU / EDSU 13.3.5 Break Address/Data Register (BAD0 to BAD31) This section describes the bit configuration and functions of the break address/data register (BAD0 to BAD31). The BADx registers define 32 break point addresses, data values or mask information for the 8 groups of channels. For each group of channels there are 4 dedicated BAD registers. BAD0, BAD1, BAD2 and BAD3 belong to Group 0, BAD4, BAD5, BAD6 and BAD7 belong to Group 1 and so on. The functionality described below for the registers of group 0 is representative for all the other groups too. The index of the BADx registers has to be incremented by 4 for each of the next group indexes. ● BADn (n = 0, 4, 8, 12, 16, 20, 24, 28) This register sets the 32 bit comparison value for break point 0 of CMP0. In range mode (set with ER0) the register value of BAD0 functions as lower address limit. In addition BAD0 could be used as mask register. In the special case of MPE=1 and COMB=1 BAD0 is not used for the point definition. CMP0 gets its point configuration then from BAD2. ● BADn (n = 1, 5, 9, 13, 17, 21, 25, 29) This register sets the 32 bit comparison value for break point 1 of CMP0. In range mode (set with ER0) the register value of BAD1 functions as upper address limit. In the special case of MPE=1 and COMB=1 BAD1 is not used for the point definition. CMP0 gets its point configuration then from BAD3. ● BADn (n = 2, 6, 10, 14, 18, 22, 30) This register sets the 32 bit comparison value for break point 2 of CMP1. In range mode (set with ER1) the register value of BAD2 functions as lower address limit. In addition BAD2 could be used as mask register. ● BADn (n = 3, 7, 11, 15, 19, 23, 27, 31) This register sets the 32 bit comparison value for break point 3 of CMP1. In range mode (set with ER1) the register value of BAD3 functions as upper address limit. 383 CHAPTER 13 MPU / EDSU 13.4 Quick Reference Quick Reference and comparator of EDSU register is shown bellow. 384 F0FCH BAD31 F0F8H BAD30 F0F4H BAD29 F0F0H BAD28 ... F08CH BAD3 F088H BAD2 F084H BAD1 F080H BAD0 F03CH BCR7 ... F020H BCR0 F010H BIRQ F00CH BOAC F008H BIAC 16 IDX3 ro ro SW IDX4 SR 15 ro IDX2 SX ro IDX1 UR UW point 3 point 2 / mask 1 point 1 point 0 / mask 0 point 3 point 2 / mask 1 point 1 point 0 / mask 0 SRX1 SW1 SRX1 SW1 SRX0 SW0 URX1 UW1 URX0 UW0 SRX0 SW0 URX1 UW1 URX0 UW0 7 ro ro 0 BD8 ro MPE COMB CTC1 CTC0 OBS1 OBS0 OBT1 OBT0 CMP1: IA, OA, OA, OA8, 16, 32, alll r, rmw, w, all CMP0: IA, OA, IA, DT MPE COMB CTC1 CTC0 OBS1 OBS0 OBT1 OBT0 BD9 ro EP3 EP3 BD7 ro EP2 EP2 BD6 ro EP1 EP1 BD5 PV EP0 EP0 BD4 ro/ac RST EM1 EM1 BD3 INT1 UART0, 1, 2, CAN EM0 EM0 BD2 INT0 Device select (Rst) (Breakx) ER1 ER1 BD1 ro INTT ER0 ER0 BD0 ro INTR FCPU FDMA EEMM PFD SINT1 SINT0 EINT1 EINT0 EINTT EINTR 8 IDX0 CDMA CSZ1 CSZ0 CRW1 CRW0 UW BD31 BD30 BD29 BD28 BD27 BD26 BD25 BD24 BD23 BD22 BD21 BD20 BD19 BD18 BD17 BD16 BD15 BD14 BD13 BD12 BD11 BD10 ro ro: read only 23 ac: auto clear 24 F004H ro 31 BSTAT F000H BCTRL CHAPTER 13 MPU / EDSU Figure 13.4-1 Register Quick Reference 385 CHAPTER 13 MPU / EDSU Figure 13.4-2 Comparator Group Structure (Drawn for Two Groups) BCR1 BCR1 OBS1 OBS-Match BAD7 Point3 BAD6 Point2 IA/OA BD3 BD7 Mask1 CMP1 BD2 BD6 CTC IA OA Value BAD5 Point1 BAD4 Point0 IA/OA/DT BD1 BD5 Mask0 CMP0 BD0 BD4 CTC IA OA DT Value BCR0 BCR0 OBS0 OBS-Match BAD3 Point3 BAD2 Point2 IA/OA BD3 BD3 Mask1 CMP1 BD2 BD2 CTC IA OA Value Comparator GROUP 0 386 Point1 BAD0 Point0 IA/OA/DT BD1 BD1 Mask0 CMP0 BD0 BD0 CTC IA OA DT BAD1 Value Break Detection Evaluation Comparator GROUP 1 CHAPTER 14 REALOS RELATED HARDWARE This chapter describes overview, configurations/ functions of registers, and operations of REALOS. 14.1 Delayed Interrupt Module 14.2 Bit Search Module 387 CHAPTER 14 REALOS RELATED HARDWARE 14.1 Delayed Interrupt Module This section describes the overview of the delayed interrupt module, configuration and functions of the register, and delayed interrupt module operation. ■ Overview of the Delayed Interrupt Module The delayed interrupt module is used to generate interrupts for switching tasks. By using this module, an interrupt request for the CPU can be generated or cancelled from a software program. 388 CHAPTER 14 REALOS RELATED HARDWARE 14.1.1 Overview of Delayed Interrupt Module This section describes the register list, details and operation of the delayed interrupt module. ■ Register List of Delayed Interrupt Module A register list of the delayed interrupt module is as follows. Figure 14.1-1 Bit Configuration of Delayed Interrupt Module bit Address: 000038H 7 6 5 4 3 2 1 0 − − − − − − − DLYI [R/W] DICR ■ Block Diagram of Delayed Interrupt Module Figure 14.1-2 shows the block diagram of the delayed interrupt module. Figure 14.1-2 Block Diagram of the Delayed Interrupt Module R-bus Interrupt request DLYI 389 CHAPTER 14 REALOS RELATED HARDWARE 14.1.2 Delayed Interrupt Module Register This section describes the configuration and functions of the delayed interrupt module register. ■ DICR (Delayed Interrupt Module Register) DICR is a register that controls delayed interrupts. The following shows the bit configuration of the delayed interrupt module register (DICR). Figure 14.1-3 Bit Configuration of the Delayed Interrupt Module Register (DICR) bit Address: 000038H 7 6 5 4 3 2 1 0 − − − − − − − DLYI [R/W] -------0B (Initial value) [bit0] DLYI Table 14.1-1 DLYI DLYI Description 0 Delayed interrupt factor is cancelled. No request exists. [Initial value] 1 Delayed interrupt factor is generated. This bit controls the generation and cancellation of the corresponding interrupt factors. 390 CHAPTER 14 REALOS RELATED HARDWARE 14.1.3 Operation of the Delayed Interrupt Module The delayed interrupt is used to generate an interrupt for switching tasks. By using this function, an interrupt request for the CPU can be generated and cancelled from a software program. ■ Interrupt Number The delayed interrupt is assigned to the interrupt factor corresponding to the largest interrupt number. On MB91461/F467R, the delayed interrupt is assigned to the interrupt number 63 (3FH). ■ DLYI Bit of DICR Writing "1" to this bit generates a delayed interrupt factor. Writing "0" to it cancels a delayed interrupt factor. This bit is the same as the interrupt factor flag for a normal interrupt. Therefore, clear this bit and switch tasks together in the interrupt routine. 391 CHAPTER 14 REALOS RELATED HARDWARE 14.2 Bit Search Module This section describes the overview of the bit search module, configuration and functions of the registers, and bit search module operation. ■ Overview of the Bit Search Module The bit search module searches for "0", "1", or any changed points in the data written to the input register and then returns the detected bit locations. 392 CHAPTER 14 REALOS RELATED HARDWARE 14.2.1 Overview of Bit Search Module This section describes the configuration and functions of the bit search module registers. ■ Register List of Bit Search Module Figure 14.2-1 shows the register list of the bit search module. Figure 14.2-1 Bit Configuration of Register List of Bit Search Module bit 31 0 Address: 0003F0H BSD0 0-detection data register Address: 0003F4H BSD1 1-detection data register Address: 0003F8H BSDC Changed point detection data register Address: 0003FCH BSRR Detection result register ■ Block Diagram of Bit Search Module Figure 14.2-2 shows the block diagram of the bit search module. Figure 14.2-2 Block Diagram of the Bit Search Module D-bus Input latch Address decoder Detection mode Making data of 1 detection Bit search circuit Search result 393 CHAPTER 14 REALOS RELATED HARDWARE 14.2.2 Bit Search Module Registers This section describes the configuration and functions of the bit search module registers. ■ 0-detection Data Register (BSD0) This register detects 0 in the written value. Figure 14.2-3 shows the register configuration of the 0-detection data register (BSD0). Figure 14.2-3 The Register Configuration of the 0-detection Data Register (BSD0) bit 31 0 000003F0H → Write only → Undefined R/W Initial value The initial value at a reset is undefined. The read value is undefined. Use a 32-bit length data transfer instruction for data transfer. (Do not use 8-bit or 16-bit length data transfer instruction.) ■ 1-detection Data Register (BSD1) Figure 14.2-4 shows the register configuration of the 1-detectoin data register (BSD1). Figure 14.2-4 The Register Configuration of the 1-detectoin Data Register (BSD1) bit 31 0 000003F4H R/W Initial value → Readable/Writable → Undefined Use a 32-bit length data transfer instruction for data transfer. (Do not use 8-bit or 16-bit length data transfer instruction.) • Writing: "1" is detected in the written value. • Reading: Saved data of the internal state in the bit search module is read. This register is used to save and restore the original state when the bit search module is used by an interrupt handler, etc. Even if data is written to the 0-detection data register or changed point detection data register, the data can be saved and restored by using only the 1-detection data register. The initial value at a reset is undefined. 394 CHAPTER 14 REALOS RELATED HARDWARE ■ Changed Point Detection Data Register (BSDC) A changed point is detected in the written value. Figure 14.2-5 shows the register configuration of the changed point detection data register (BSDC). Figure 14.2-5 The Register Configuration of the Changed Point Detection Data Register (BSDC) bit 31 0 000003F8H → Write only → Undefined R/W Initial value The initial value at a reset is undefined. The read value is undefined. Use a 32-bit length data transfer instruction for data transfer. (Do not use 8-bit or 16-bit length data transfer instruction.) ■ Detection Result Register (BSRR) The result of 0 detection, 1 detection, or changed point detection is read. The data register written last is used to determine which detection result to be read. Figure 14.2-6 shows the register configuration of the detection result register (BSRR). Figure 14.2-6 The Register Configuration of the Detection Result Register (BSRR) bit 31 0 000003FCH R/W Initial value → Read only → Undefined 395 CHAPTER 14 REALOS RELATED HARDWARE 14.2.3 Operation of the Bit Search Module This section explains the operation of the bit search module. ■ 0 Detection The bit search module scans data written to the 0-detection data register from MSB to LSB and returns the location where the first "0" is detected. The detection result can be obtained by reading the detection result register. The relationship between the detected location and the return value is given in Table 14.2-1. If a "0" is not found (that is, the value is "FFFFFFFFH"), the value 32 is returned as the search result. [Execution example] Write data Read value (decimal) 11111111111111111111000000000000B ("FFFFF000H") → 20 11111000010010011110000010101010B ("F849E0AAH") → 5 10000000000000101010101010101010B ("8002AAAAH") → 1 11111111111111111111111111111111B ("FFFFFFFFH") → 32 ■ 1 Detection The bit search module scans data written to the 1-detection data register from MSB to LSB and returns the location where the first "1" is detected. The detection result can be obtained by reading the detection result register. The relationship between the detected location and the return value is given in Table 14.2-1. If a "1" is not found (that is, the value is "00000000H"), the value 32 is returned as the search result. [Execution example] Write data 396 Read value (decimal) 00100000000000000000000000000000B ("20000000H") → 2 00000001001000110100010101100111B ("01234567H") → 7 00000000000000111111111111111111B ("0003FFFFH") → 14 00000000000000000000000000000001B ("00000001H") → 31 00000000000000000000000000000000B ("00000000H") → 32 CHAPTER 14 REALOS RELATED HARDWARE ■ Changed Point Detection The bit search module scans data written to the changed point detection data register from bit30 to the LSB, and compares with the MSB value. The first location where a value that is different from that of the MSB is detected is returned. The detection result can be obtained by reading the detection result register. The relationship between the detected location and the return value is given in Table 14.2-1. If a changed point is not detected, 32 is returned. In changed point detection, 0 is never returned as a result. [Execution example] Write data Read value (decimal) 00100000000000000000000000000000B ("20000000H") → 2 00000001001000110100010101100111B ("01234567H") → 7 00000000000000111111111111111111B ("0003FFFFH") → 14 00000000000000000000000000000001B ("00000001H") → 31 00000000000000000000000000000000B ("00000000H") → 32 11111111111111111111000000000000B ("FFFFF000H") → 20 11111000010010011110000010101010B ("F849E0AAH") → 5 10000000000000101010101010101010B ("8002AAAAH") → 1 11111111111111111111111111111111B ("FFFFFFFFH") → 32 Table 14.2-1 lists the bit locations and return values (decimal). Table 14.2-1 Bit Locations and Return Values (Decimal) Detected bit location Return value Detected bit location Return value Detected bit location Return value Detected bit location Return value 31 0 23 8 15 16 7 24 30 1 22 9 14 17 6 25 29 2 21 10 13 18 5 26 28 3 20 11 12 19 4 27 27 4 19 12 11 20 3 28 26 5 18 13 10 21 2 29 25 6 17 14 9 22 1 30 24 7 16 15 8 23 0 31 Not exist 32 397 CHAPTER 14 REALOS RELATED HARDWARE ■ Save and Restore Processing If it is necessary to save and restore the internal state of the bit search module, such as when the bit search module is used in an interrupt handler, use the following procedure: 1) Read the 1-detection data register and save its contents (save). 2) Use the bit search module. 3) Write the data saved in 1) to the 1-detection data register (restore). With the above operation, the value obtained when the detection result register is read the next time corresponds to the value written to the bit search module before 1). If the data register written last is the 0-detection data register or changed point detection data register, the value is restored correctly with the above procedure. 398 CHAPTER 15 DMAC (DMA CONTROLLER) This chapter describes the overview of the DMAC, configuration and functions of the registers, and DMAC operation. 15.1 Overview of DMAC (DMA Controller) 15.2 Detailed Explanation of the DMAC (DMA Controller) Registers 15.3 Explanation of the DMAC (DMA Controller) Operation 15.4 Operational Flow of DMAC (DMA Controller) 15.5 Data Path of DMAC (DMA Controller) 399 CHAPTER 15 DMAC (DMA CONTROLLER) 15.1 Overview of DMAC (DMA Controller) DMAC (DMA Controller) is used to implement DMA (Direct Memory Access) transfer in FR family devices. By using DMA transfer controlled by DMAC (DMA Controller), various types of data transfer can be performed at high-speed without using the CPU and so the system performance is improved. ■ Hardware Configuration of DMAC The DMAC (DMA Controller) consists of the following main components: • Five independent DMA channels • Independent access control circuit for five channels • 32-bit address register (reload selectable: ch.0 to ch.5) • 16-bit transfer count register (reload selectable: one per channel) • 4-bit block count register (one per channel) • 2-cycle transfer ■ Main Function of DMAC The following are the main functions related to data transfer by the DMA controller (DMAC): ● Independent data transfer can be performed for multiple channels (5ch) • Priority (ch.0 > ch.1 > ch.2 > ch.3 > ch.4) • The priority can be switched between ch.0 and ch.1. • DMAC activation factor - Request from built-in peripheral (shares interrupt requests, including the external interrupts) - Software request (register write) • Transfer mode - Burst transfer, step transfer, and block transfer - Addressing mode: 32-bit addressing (increment/decrement/fixed: the address increment/decrement range is fixed to ± 1, 2, and 4) - Data types: Byte, halfword, and word length - Selectable from single-shot or reload 400 CHAPTER 15 DMAC (DMA CONTROLLER) ■ Overview of the DMAC Registers Figure 15.1-1 lists the overview of the DMAC registers. Figure 15.1-1 Overview of DMAC Registers ch.0 control/status register A DMACA0 bit 31 000200H ch.0 control/status register B DMACB0 000204H ch.1 control/status register A DMACA1 000208H ch.1 control/status register B DMACB1 00020CH ch.2 control/status register A DMACA2 000210H ch.2 control/status register B DMACB2 000214H ch.3 control/status register A DMACA3 000218H ch.3 control/status register B DMACB3 00021CH ch.4 control/status register A DMACA4 000220H ch.4 control/status register B DMACB4 000224H All-channel control register DMACR 000240H bit 31 DMASA0 001000H ch.0 transfer destination address setting register DMADA0 001004H ch.1 transfer source address setting register DMASA1 001008H ch.1 transfer destination address setting register DMADA1 00100CH ch.2 transfer source address setting register DMASA2 001010H ch.2 transfer destination address setting register DMADA2 001014H ch.3 transfer source address setting register DMASA3 001018H ch.3 transfer destination address setting register DMADA3 00101CH ch.4 transfer source address setting register DMASA4 001020H ch.4 transfer destination address setting register DMADA4 001024H ch.0 transfer source address setting register 24 23 16 20 19 15 8 7 0 0 401 CHAPTER 15 DMAC (DMA CONTROLLER) ■ Block Diagram of DMAC Figure 15.1-2 shows the block diagram of the DMAC. Figure 15.1-2 Block Diagram of DMAC Write back Counter DMA transfer request to bus controller Buffer Selector DTC 2-stage register DTCR DMA activation factor select circuit & request reception control Peripheral activation request/stop input External pin activation request/stop input Counter DSS[3:0] Priority level circuit Buffer Selector Write back IRQ[4:0] Peripheral interrupt clear MCLREQ DDN register DSAD 2-stage register SADM,SASZ[7:0] SADR DDAD 2-stage register DADM,DASZ[7:0] DADR X-bus TYPE.MOD,WS Bus control section Selector Status transition circuit Write back Selector Counter buffer Counter buffer Address 402 BLK register DMA controller Access To interrupt controller ERIE,EDIE Selector Read/write control DDN Address counter To bus controller Bus control section Read Write CHAPTER 15 DMAC (DMA CONTROLLER) 15.2 Detailed Explanation of the DMAC (DMA Controller) Registers This section explains details of each register of DMAC. ■ Notes on Setting Registers Some bits in the DMAC may only be set when the DMA is stopped. If set during operation (transfer), correct operation cannot be guaranteed. An asterisk (*) indicates bits that will affect operation if set during DMAC transfer. Rewrite this bit while DMAC transfer is stopped (in a state where activation is disabled or the transfer is temporarily stopped). Values set while DMA transfer activation is disabled (DMACR:DMAE=0 or DMACA:DENB=0) become valid when DMA activation is enabled. Values set while DMA transfer is temporarily stopped (DMACR:DMAH[3:0] ≠ 0000B or DMACA: PAUS=1) become valid when the temporary stop is cancelled. 403 CHAPTER 15 DMAC (DMA CONTROLLER) 15.2.1 DMAC-ch.0, ch.1, ch.2, ch.3, ch.4 Control/Status Registers A DMACA0 to DMACA4 are registers that control the operation of each channel of DMAC. Each register is set independently for each channel. ■ Bit Function of DMACA0 to DMACA4 Figure 15.2-1 shows the bit function of DMACA0 to DMACA4. Figure 15.2-1 Bit Function of DMACA0 to DMACA4 bit 31 30 29 28 27 DENB PAUS STRG bit 15 14 13 26 25 24 23 IS [4 : 0] 11 11 10 22 21 20 19 Reserved 9 8 7 6 5 18 17 16 BLK [3 : 0] 4 3 2 1 0 DTC [15 : 0] (Initial value: 00000000H) [bit31] DENB (Dma ENaBle): DMA operation enable bit This bit enables or disables DMA transfer activation for each transfer channel. Once a channel is enabled, DMA transfer starts when a generated transfer request is accepted. All transfer requests that are generated for a channel where the activation is disabled become invalid. When the specified number of transfers on an activated channel has been completed, this bit is set to "0" and the transfer stops. The transfer can be forced to stop by writing "0" to this bit. Be sure to stop a transfer forcibly ("0" write) only after temporarily stopping DMA using the PAUS bit [bit30: DMACA]. If the transfer is forced to stop without temporarily stopping DMA, DMA stops but the transferred data cannot be guaranteed. Check whether DMA is stopped using the DSS[2:0] bits (bit18 to bit16: DMACB). Table 15.2-1 DMA Operation Enable Bit DENB Function 0 DMA operation is disabled on the corresponding channel. [Initial value] 1 DMA operation is enabled on the corresponding channel. • At a reset or when a stop request is accepted: Initialized to "0". • Read/write is enabled. If the operation of all channels is disabled by bit31: DMAE bit of the DMAC all-channel control register DMACR, writing "1" to this bit is disabled and the stopped state is maintained. If the operation is disabled by the above bit while the operation is enabled by this bit, this bit becomes "0" and the transfer is stopped (forced stop). 404 CHAPTER 15 DMAC (DMA CONTROLLER) [bit30] PAUS (PAUSe): Temporary stop instruction This bit controls temporary stop of DMA transfer for the corresponding channel. If this bit is set, DMA transfer is not performed until this bit is cleared. (While DMA is stopped, DSS bits become "1XXB"). If this bit is set before DMA activation and then DMA is activated, DMA remains paused. New transfer requests that occur while this bit is set are accepted, but no transfer starts until this bit is cleared (See "15.3.10 Transfer Request Acceptance and Transfer"). Table 15.2-2 Temporary Stop Instruction PAUS Function 0 DMA operation is enabled on the corresponding channel. [Initial value] 1 DMA operation is temporarily stopped on the corresponding channel. • At a reset: Initialized to "0". • Read/write is enabled. [bit29] STRG (Software TRiGger): Transfer request This bit generates a DMA transfer request for the corresponding channel. Writing "1" to this bit generates a transfer request after writing to the register is completed, and the transfer on the corresponding channel is started. However, if the corresponding channel is not activated, writing to this bit is ignored. Table 15.2-3 Transfer Request Bit STRG Function 0 Invalid [Initial value] 1 DMA activation request • At a reset: Initialized to "0". • Read value is always "0". • Only write value "1" is valid, and "0" has no effect on the operation. Note: If a transfer request is set by this bit transfer is activated by writing the DMAE bit, the transfer request is valid and transfer starts. If this bit is written at the same time as the PAUS bit is writing as "1", the transfer request is valid but DMA transfer does not start until the PAUS bit is cleared to "0". 405 CHAPTER 15 DMAC (DMA CONTROLLER) [bit28 to bit24] IS4 to IS0 (Input Select)*: Transfer factor selection These bits select the factor of a transfer request as shown below. However, the software transfer request triggered by the STRG bit function remains valid regardless of this setting. Table 15.2-4 Transfer Factor Selection IS (Input Source) Function Transfer stop request 00000B Software transfer request only 00001B to 01101B Setting disabled 01110B External pin (DREQ) "H" level or ↑ edge 01111B External pin (DREQ) "L" level or ↓ edge 10000B External interrupt 0 − 10001B External interrupt 1 − 10010B External interrupt 2 − 10011B External interrupt 3 − 10100B Reload timer 0 − 10101B Reload timer 1 − 10110B LIN-UART0 RX (Reception completed) 10111B LIN-UART0 TX (Transmission completed) 11000B LIN-UART1 RX (Reception completed) 11001B LIN-UART1 TX (Transmission completed) 11010B LIN-UART4 RX (Reception completed) 11011B LIN-UART4 TX (Transmission completed) 11100B LIN-UART5 RX (Reception completed) 11101B LIN-UART5 TX (Transmission completed) − 11110B A/D converter − 11111B PPG0 − − Yes − Yes − Yes − Yes • At a reset: Initialized to "00000B". • Read/write is enabled. If DMA activation by peripheral function interrupt is set (IS=1XXXXB), disable interrupts of the selected function with the ICR register. When the DMA transfer is activated by the software transfer request while the DMA activation by the interrupt of the peripheral function is set, the factor is cleared to the corresponding peripherals after transfer ends. Therefore, since there is a possibility of clearing an original transfer request, do not start by the software transfer request when the DMA transfer by the interrupt of the peripheral function is set. 406 CHAPTER 15 DMAC (DMA CONTROLLER) [bit23 to bit20] Reserved: Reserved bits Read value is fixed to "0000B". Writing to these bits is invalid. [bit19 to bit16] BLK3 to BLK0 (BLocK size): Block size specification These bits specify the size for block transfer for the corresponding channel. The value specified by these bits becomes the number of words in one transfer unit (more exactly, the repetition count of the data width setting). Be sure to set "01H" (size 1) when not performing block transfer. Table 15.2-5 Block Size Specification BLK XXXXB Function Block size specified for the corresponding channel • At a reset: Initialized to "0000B". • Read/write is enabled. • If "0" is specified for all bits, the block size becomes 16 words. • Reading always returns the block size (reload value). [bit15 to bit00] DTC15 to DTC0 (Dma Terminal Count register)*: Transfer count register This register stores the number of transfers performed. Each register consists of 16-bit length. All registers have a dedicated reload register. When using it on channels that allow the transfer count register to be reloaded, the initial setting value is automatically returned to the register when the transfer completes. Table 15.2-6 Transfer Count Register DTC XXXXH Function Transfer number specified for the corresponding channel When DMA transfer starts, the data in this register is stored in the counter buffer in the dedicated DMA transfer counter and the value is counted -1 (decremented) by one after each transfer. When DMA transfer completes, the value of the counter buffer is written back to this register and the DMA operation ends. Thus, the transfer number specification value cannot be read during DMA operation. • At a reset: Initialized to "0000H". • Read/write is enabled. For DTC access, be sure to use halfword length or word length access. • Reading the register returns the counter value. The reload value cannot be read. 407 CHAPTER 15 DMAC (DMA CONTROLLER) 15.2.2 DMAC-ch.0, ch.1, ch.2, ch.3, ch.4 Control/Status Registers B DMACB0 to DMACB4 are registers that control the operation of each channel of DMAC. Each register is set independently for each channel. ■ Bit Function of DMACB0 to DMACB4 Figure 15.2-2 shows the bit function of DMACB0 to DMACB4. Figure 15.2-2 Bit Function of DMACB0 to DMACB4 bit 31 30 29 28 TYPE [1 : 0] MOD [1 : 0] bit 15 14 13 11 27 26 25 24 23 22 21 20 19 18 WS [1 : 0] SADM DADM DTCR SADR DADR ERIE EDIE 11 10 9 8 7 6 5 SASZ [7 : 0] 4 3 17 16 DSS [2 : 0] 2 1 0 DASZ [7 : 0] (Initial value: 00000000_00000000_XXXXXXXX_XXXXXXXXB) [bit31, bit30] TYPE1, TYPE0 (TYPE)*: Transfer type setting These bits specify the operation type of the corresponding channel as described below. 2-cycle transfer mode: This mode sets the transfer source address (DMASA) and transfer destination address (DMADA) and performs a transfer by repeating the read operation and write operation for the number of times specified by the transfer count. Table 15.2-7 Transfer Type Setting TYPE Function 00B 2-cycle transfer [Initial value] 01B Setting disabled 10B Setting disabled 11B Setting disabled • At a reset: Initialized to "00B". • Read/write is enabled. • Always set these bits to "00B". 408 CHAPTER 15 DMAC (DMA CONTROLLER) [bit29, bit28] MOD1, MOD0 (MODe)*: Transfer mode setting These bits set the operating mode of the correspondence channel as follows. Table 15.2-8 Transfer Mode Setting MOD Function 00B Block/step transfer mode [Initial value] 01B Burst transfer mode 10B Setting disabled 11B Setting disabled • At a reset: Initialized to "00B". • Read/write is enabled. [bit27, bit26] WS1, WS0 (Word Size): Transfer data width selection These bits select the transfer data width for the corresponding channel. The specified number of transfers is performed in units of the data width specified in this register. Table 15.2-9 Transfer Data Width Selection WS Function 00B BYTE unit transfer [Initial value] 01B HALF-WORD unit transfer 10B WORD width unit transfer 11B Setting disabled • At a reset: Initialized to "00B". • Read/write is enabled. [bit25] SADM (Source-ADdr, count-Mode select)*: Transfer source address count mode specification This bit specifies the address process for each transfer of the transfer source address for the corresponding channel. An address increment is added or an address decrement is subtracted after each transfer operation according to the specified transfer source address count width (SASZ). When the transfer is completed, the next access address is written to the corresponding address register (DMASA). As a result, the transfer source address register is not updated until DMA transfer is completed. To fix the address, set this bit to "0" or "1", and set the address count widths (SASZ and DASZ) to "0". Table 15.2-10 Transfer Source Address Count Mode Specification SADM Function 0 Transfer source address is incremented. [Initial value] 1 Transfer source address is decremented. • At a reset: Initialized to "0". • Read/write is enabled. 409 CHAPTER 15 DMAC (DMA CONTROLLER) [bit24] DADM (Destination-ADdr, Count-Mode select)*: Transfer destination address count mode specification This bit specifies the address process for each transfer of the transfer destination address for the corresponding channel. An address increment is added or an address decrement is subtracted after each transfer operation according to the specified transfer destination address count width (DASZ). When the transfer is completed, the next access address is written to the corresponding address register (DMADA). As a result, the transfer destination address register is not updated until the DMA transfer is completed. To fix the address, set this bit to "0" or "1", and set the address count widths (SASZ and DASZ) to "0". Table 15.2-11 Transfer Destination Address Count Mode Specification DADM Function 0 Transfer destination address is incremented. [Initial value] 1 Transfer destination address is decremented. • At a reset: Initialized to "0". • Read/write is enabled. [bit23] DTCR (DTC-reg, Reload)*: Transfer count register reload specification This bit controls the reload function for the transfer count register in the corresponding channel. If reloading operation is enabled by this bit, the count register value is restored to its initial value after transfer is completed, then DMAC stops and enters the wait state for a new transfer request (activation request by STRG or IS setting). (If this bit is "1", DENB bit is not cleared.) Transfer is forcibly stopped when DENB=0 or DMAE=0 is set. If reload operation of the transfer counter is disabled, a single-shot operation that stops when transfer is completed is performed even if reloading is specified in the address register. In this case, the DENB bit is cleared. Table 15.2-12 Transfer Count Register Reload Specification DTCR Function 0 Transfer count register reloading is disabled. [Initial value] 1 Transfer count register reloading is enabled. • At a reset: Initialized to "0". • Read/write is enabled. 410 CHAPTER 15 DMAC (DMA CONTROLLER) [bit22] SADR (Source-ADdr.-reg, Reload)*: Transfer source address register reload specification This bit controls the reload function for the transfer source address register in the corresponding channel. When reloading operation is enabled by this bit, the transfer source address register value is restored to its initial value after transfer is completed. If reload operation of the transfer counter is disabled, a single-shot operation that stops when transfer is completed is performed even if reloading is specified in the address register. In this case, the address register value stops at a state that the initial value is reloaded. When this bit disables reloading, the value of the address register when transfer is completed is the next access address of the last address (that is, if incrementing is specified, the incremented address). Table 15.2-13 Transfer Source Address Register Reload Specification SADR Function 0 Transfer source address register reloading is disabled. [Initial value] 1 Transfer source address register reloading is enabled. • At a reset: Initialized to "0". • Read/write is enabled. [bit21] DADR (Dest.-ADdr.-reg, Reload)*: Transfer destination address register reload specification This bit controls the reload function for the transfer destination address register in the corresponding channel. When reloading is enabled by this bit, the transfer destination address register value is restored to its initial value after transfer is completed. The details of other functions are the same as those described for bit22:SADR. Table 15.2-14 Transfer Destination Address Register Reload Specification DADR Function 0 Transfer destination address register reloading is disabled. [Initial value] 1 Transfer destination address register reloading is enabled. • At a reset: Initialized to "0". • Read/write is enabled. 411 CHAPTER 15 DMAC (DMA CONTROLLER) [bit20] ERIE (ERror Interrupt Enable)*: Error interrupt output enable This bit controls the generation of an interrupt for termination when an error occurs. The content of the error is indicated in DSS2 to DSS0. Note that an interrupt occurs only for specific termination factors and not for all termination factors. (Refer to description of bits DSS2 to DSS0.) Table 15.2-15 Error Interrupt Output Enable ERIE Function 0 Error interrupt request output is disabled. [Initial value] 1 Error interrupt request output is enabled. • At a reset: Initialized to "0". • Read/write is enabled. [bit19] EDIE (EnD Interrupt Enable)*: End interrupt output enable This bit controls the generation of an interrupt when transfer ends normally. Table 15.2-16 End Interrupt Output Enable EDIE Function 0 End interrupt request output is disabled. [Initial value] 1 End interrupt request output is enabled. • At a reset: Initialized to "0". • Read/write is enabled. [bit18 to bit16] DSS2 to DSS0 (Dma Stop Status)*: Transfer stop factor indication These bits indicate a code (exit code) of 3 bits that indicates the factor of stopping or termination of DMA transfer on the corresponding channel. The exit codes are as follows. Table 15.2-17 Transfer Stop Factor Indication DSS 000B Function Initial value X01B Interrupt generation None - None X10B Transfer stop request Error X11B Normal end End 1XXB DMA temporary stop (by DMAH bit, PAUS bit, and interrupts, etc.) None The transfer stop request is only set when a request from a peripheral circuit is used. The "interrupt generation" column indicates the type of interrupt requests that can be generated. • At a reset: Initialized to "000B". • Writing "000B" clears these bits. • Although read/write is enabled, only writing "000B" is valid. 412 CHAPTER 15 DMAC (DMA CONTROLLER) [bit15 to bit8] SASZ7 to SASZ0 (Source Addr count SiZe)*: Transfer source address count size specification These bits specify increment/decrement width for each transfer of each transfer source address (DMASA) for the corresponding channel. The value set by these bits becomes the address increment/ decrement width for each transfer unit. The address increment/decrement width is complied with the specification of the transfer source address count mode (SADM). Table 15.2-18 Transfer Source Address Count Size Specification SASZ Function 00H Address fixed 01H Byte unit transfer 02H Halfword unit transfer 04H Word unit transfer Others Setting disabled • At a reset: Initialized to "00000000B". • Read/write is enabled. • If setting other than a fixed address, be sure to set the same transfer unit as the transfer data width (WS). [bit7 to bit0] DASZ7 to DASZ0 (Des Addr count SiZe)*: Transfer destination address count size specification These bits specify increment/decrement width for each transfer of each transfer destination address (DMADA) for the corresponding channel. The value set by these bits becomes the address increment/ decrement width for each transfer unit. The address increment/decrement width is complied with the specification of the transfer destination address count mode (DADM). Table 15.2-19 Transfer Destination Address Count Size Specification DASZ Function 00H Address fixed 01H Byte unit transfer 02H Halfword unit transfer 04H Word unit transfer Others Setting disabled • At a reset: Initialized to "00000000B". • Read/write is enabled. • If setting other than a fixed address, be sure to set the same transfer unit as the transfer data width (WS). 413 CHAPTER 15 DMAC (DMA CONTROLLER) 15.2.3 DMAC-ch.0, ch.1, ch.2, ch.3, ch.4 Transfer Source/ Transfer Destination Address Setting Registers DMASA0 to DMASA4 / DMADA0 to DMADA4 are registers that control the operation of each channel of DMAC. Each register is set independently for each channel. ■ Bit Configuration of DMASA0 to DMASA4 / DMADA0 to DMADA4 Each bit function of DMASA0 to DMASA4 / DMADA0 to DMADA4 is indicated as follows. Figure 15.2-3 Bit Function of DMASA0 to DMASA4 / DMADA0 to DMADA4 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 6 5 4 3 2 1 0 22 21 20 19 18 17 16 6 5 4 3 2 1 0 DMASA [31 : 16] bit 15 14 13 11 11 10 9 8 7 DMASA [15 : 0] (Initial value: XXXXXXXXH) bit 31 30 29 28 27 26 25 24 23 DMADA [31 : 16] bit 15 14 13 11 11 10 9 8 7 DMADA [15 : 0] (Initial value: 00000000H) These registers store the transfer source and destination addresses. These are composed of 32-bit length. [bit31 to bit0] DMASA31 to DMASA0 (DMA Source Addr)*: Transfer source address setting These bits set the transfer source address. 414 CHAPTER 15 DMAC (DMA CONTROLLER) [bit31 to bit0] DMADA31 to DMADA0 (DMA Destination Addr)*: Transfer destination address setting These bits set the transfer destination address. When the DMA transfer is activated, the data of this register is stored in the counter buffer of a dedicated DMA address counter and address count is performed for each transfer based on the setting. When the DMA transfer is completed, the contents of the counter buffer are written back to this register and then DMA ends. Thus, the address counter value cannot be read during DMA operation. All registers have a dedicated reload register. When used on channels for which reloading the transfer source and destination address registers is enabled, the register is automatically reloaded with its initial value when transfer completes. In this case, other address registers are not affected. • At a reset: Initialized to "00000000H". • Read/write is enabled. Be sure to access to this register with 32-bit data. • During transfer, reading returns the previous address value before transfer starts. After transfer completes, reading returns the next access address value. The reload value cannot be read. Therefore, the transfer address cannot be read in real time. • Set "0" for a nonexistent upper bit. Note: Do not set DMAC’s own registers in this register. Performing DMA transfer to DMAC’s own registers is not allowed. 415 CHAPTER 15 DMAC (DMA CONTROLLER) 15.2.4 DMAC-ch.0, ch.1, ch.2, ch.3, ch.4 DMAC All-Channel Control Register DMACR controls the operation of all the five DMAC channels. Be sure to access to this register using byte length. ■ Bit Configuration of DMACR Figure 15.2-4 shows the bit function of DMACR. Figure 15.2-4 Bit Function of DMACR bit bit 31 30 29 28 DMAE 27 26 25 − − PM01 15 14 13 11 11 10 9 − − − − − − − 24 23 22 21 20 19 18 17 16 − − − − − − − − 8 7 6 5 4 3 2 1 0 − − − − − − − − − DMAH [3 : 0] (Initial value: 0XX00000_XXXXXXXX_XXXXXXXX_XXXXXXXXB) [bit31] DMAE (DMA Enable): DMA operation enable This bit controls operation for all DMA channels. If DMA operation is disabled by this bit, transfer operations on all channels are disabled regardless of the start/stop settings for each channel and the operating status. Any requests on channels where transfer is in progress are cancelled and transfer stops at the block boundary. In a disabled state, all activation operations to each channel are ignored. If this bit enables DMA operation, start/stop operations are enabled for all channels. Enabling DMA operation by this bit itself does not start transfer for each channel. DMA operation can be forced to stop by writing "0" to this bit. However, be sure to use forced stop ("0" write) only after temporarily stopping DMA using the DMAH[3:0] bits (bit27 to bit24: DMACR). If forced stopping is carried out without temporarily stopping DMA, DMA stops but the transfer data cannot be guaranteed. Check whether DMA is stopped using the DSS[2:0] bits (bit18 to bit16: DMACB). Table 15.2-20 DMA Operation Enable DMAE Function 0 DMA operation is disabled on all channels. [Initial value] 1 DMA operation is enabled on all channels. • At a reset: Initialized to "0". • Read/write is enabled. 416 CHAPTER 15 DMAC (DMA CONTROLLER) [bit28] PM01 (Priority Mode ch.0, ch.1 robin): Channel priority rotation This bit is set to switch priority for each transfer between ch.0 and ch.1. Table 15.2-21 Channel Priority Rotation PM01 Function 0 Priority is fixed. (ch.0 > ch.1) [Initial value] 1 Priority is switched. (ch.1 > ch.0) • At a reset: Initialized to "0". • Read/write is enabled. [bit27 to bit24] DMAH3 to DMAH0 (DMA Halt): DMA temporary stop These bits stop temporarily DAM transfer for all DMA channels. Setting these bits stops DMA transfer on all channels until the bits are cleared again. If these bits are set before enabling DMA, all channels remain paused. Any transfer requests that occur for channels where DMA transfer is enabled (DENB=1) while these bits are set are valid but transfer does not start until the bits are cleared. Table 15.2-22 DMA Temporary Stop DMAH 0000B Other than 0000B Function DMA operation is enabled on all channels. [Initial value] DMA is temporarily stopped. • At a reset: Initialized to "0". • Read/write is enabled. [bit30, bit29, bit23 to bit0] −: Reserved bits Read value is undefined. 417 CHAPTER 15 DMAC (DMA CONTROLLER) 15.3 Explanation of the DMAC (DMA Controller) Operation This section explains the operational overview, details of the transfer request setting, transfer sequence and operation of DMAC. ■ Overview of the DMAC This block built into FR family devices is a multi-functional DMA controller and controls data transfer at high speed without using CPU instruction operations. 418 CHAPTER 15 DMAC (DMA CONTROLLER) 15.3.1 Operational Overview of DMAC (DMA Controller) This section explains the operational overview of DAMC. ■ Main Operations of DMAC The operation of each function can be set independently for each transfer channel. After each channel is enabled, the channel does not actually start transfer until the specified transfer request is detected. On detecting a transfer request, the DMAC outputs a DMA transfer request to the bus controller and starts transfer on receiving bus access rights from the bus controller. The transfer is carried out based on a sequence of the mode settings set independently for each channel. ■ Transfer Mode Each DMA channel performs transfer operation according to the transfer mode set by the MOD[1:0] bits of its DMACB register. ● Block/step transfer Only a single block transfer unit is transferred in response to one transfer request. DMA then stops requesting the bus controller for transfer until the next transfer request is accepted. One block transfer unit: Specified block size (DMACA:BLK[3:0]). ● Burst transfer With one transfer request, the transfer continues until the specified number of transfers is completed. Specified number of transfers: Block size × transfer count (DMACA:BLK[3:0] × DMACA:DTC[15:0]) ■ Transfer Type ● 2-cycle transfer (Normal transfer) The DMA controller operates a read operation and a write operation as one unit of operation. The DMAC reads the data from the address in the transfer source register and then writes it to the address in the transfer destination register. 419 CHAPTER 15 DMAC (DMA CONTROLLER) ■ Transfer Address The following types of addressing are available and can be set independently for each channel transfer source and transfer destination. ● Specifying the address for 2-cycle transfer The value read from a register (DMASA, DMADA) in which an address has been set in advance is used as the address for access. After accepting a transfer request, DMA stores the address from the register in the temporary storage buffer and then starts transfer. After each transfer (access), the address counter is used to generate the next access address (incremented, decremented, or fixed can be selected) and this new address is returned to the temporary storage buffer. The contents of the temporary storage buffer are written back to the register (DMASA, DMADA) after each block transfer unit is completed. Therefore, the address register (DMASA, DMADA) value is updated only by each block transfer unit, and so the address during transfer cannot be read in real time. ■ Number of Transfers and End of Transfer ● Number of transfers The transfer count register is decremented (-1) after transfer of each block completes. When the transfer count register reaches "0" indicating that the specified number of transfers have been performed, the DMAC displays the exit code and then stops or restarts. Like the address registers, the transfer count register is only updated after each block is transferred. If reloading the transfer count register is disabled, transfer ends. If enabled, the register is initialized with its initial value and the DMAC enters a wait state for transfer (DMACB:DTCR). ● End of transfer Factors for the transfer end are shown below. When transfer ends, a factor is indicated as the exit code (DMACB:DSS[2:0]). • End of the specified transfer number (DMACA:BLK[3:0] × DMACA:DTC[15:0]) → Normal end • A transfer stop request is generated from a peripheral circuit → Error • An address error is generated → Error • A reset is generated → Reset A transfer stop factor indication (DSS) is displayed and a transfer end interrupt/error interrupt can be generated for each end factor. 420 CHAPTER 15 DMAC (DMA CONTROLLER) 15.3.2 Transfer Request Setting The following two types of transfer requests can be used to start DMA transfer. • Built-in peripheral request • Software request Software requests can always be used regardless of the settings of other requests. ■ Internal Peripheral Request The transfer request is generated by an interrupt from a built-in peripheral circuit. For each channel, set which peripheral interrupt is used to generate a transfer request (DMACA:IS[4:0]=1XXXXB). This request and an external transfer request cannot be used at the same time. Note: Because an interrupt request used in a transfer request can be seen as an interrupt request to the CPU, disable interrupts in the interrupt controller setting (ICR register). ■ Software Request Writing to the trigger bit in the register generates the transfer request (DMACA:STRG). This request can be used independently from the above transfer request at any time. If a software request occurs concurrently with activation (enabling transfer), a DMA transfer request is outputted to the bus controller immediately and then transfer starts. 421 CHAPTER 15 DMAC (DMA CONTROLLER) 15.3.3 Transfer Sequence The transfer type and the transfer mode that determine the operation sequence after DMA transfer activation can be set independently for each channel (DMACB:TYPE[1:0] and MOD[1:0] settings). ■ Selecting Transfer Sequence The following sequences can be selected by register settings: • Burst 2-cycle transfer • Block/step 2-cycle transfer ■ Burst 2-cycle Transfer The specified number of transfers is performed for each transfer factor. For a 2-cycle transfer, 32-bit area can be specified for a transfer source/transfer destination address. A peripheral transfer request or a software transfer request can be specified as a transfer factor. Table 15.3-1 lists the specifiable transfer address for burst 2-cycle transfer. Table 15.3-1 Specifiable Transfer Address for Burst 2-Cycle Transfer Transfer source address specification Direction Transfer destination address specification All 32-bit areas specifiable → All 32-bit areas specifiable [Characteristics of burst transfer] • Each time a transfer request is received, transfer continues until the transfer count register reaches "0". The number of transfers is the block size × the number of transfers (DMACA:BLK[3:0] × DMACA:DTC[15:0]). • If a transfer request is generated once again during a transfer, the request is ignored. • When the reload function is enabled for the transfer count register, a subsequent transfer request is accepted after transfer completes. • If a transfer request for another channel with a higher priority is received during transfer, the channel is switched at the boundary of the block transfer unit and it will not be returned until the transfer request for the channel is cleared. Figure 15.3-1shows the example of burst transfer. Figure 15.3-1 Example of Burst Transfer Transfer request ↑ (edge) Bus operation Transfer number CPU SA DA 4 SA DA 3 SA DA 2 SA DA 1 Transfer end (Example of burst transfer with external pin rising edge activation, block number=1, and transfer number=4) 422 CPU 0 CHAPTER 15 DMAC (DMA CONTROLLER) ■ Step/Block Transfer 2-cycle Transfer For a step/block transfer (transfer for each transfer request is performed as many times as the specified block count), 32-bit area can be specified as the transfer source/transfer destination address. Table 15.3-2 shows the specifiable transfer addresses for step/block transfer 2-cycle transfer. Table 15.3-2 Specifiable Transfer Addresses for Step/Block Transfer 2-Cycle Transfer Transfer source address specification Direction Transfer destination address specification All 32-bit areas specifiable → All 32-bit areas specifiable ■ Step Transfer If "1" is set for the block size, a step transfer sequence is selected. [Characteristics of step transfer] • If a transfer request is received, the transfer request is cleared after one transfer operation and then the transfer is stopped. (The DMA transfer request to the bus controller is canceled.) • If a transfer request is generated once again during a transfer, the request is ignored. • If a transfer request for another channel with a higher priority is received during transfer, the channel is switched after the transfer is stopped and then restarted. For step transfer, priority is only meaningful for the case when transfer requests are generated simultaneously. ■ Block Transfer If a value other than "1" is specified for the block size, a block transfer sequence is selected. [Characteristics of block transfer] Except that each transfer consists of multiple transfer cycles (specified by the number of blocks), the operation is the same as for step transfer. Figure 15.3-2 shows the example of block transfer. Figure 15.3-2 Example of Block Transfer Transfer request ↑ (edge) Bus operation Block number Transfer number CPU SA DA SA 2 DA 1 2 CPU 0 SA DA SA DA 1 2 1 Transfer end (Example of block transfer with external pin rising edge activation, block number=2, and transfer number=2) 423 CHAPTER 15 DMAC (DMA CONTROLLER) 15.3.4 DMA Transfer in General This section explains the DMA transfer operation. ■ Block Size The unit of transfer data is the collection of data of as many as the number set in the block size setting register (× data width). Since the data to be transferred in one transfer cycle is fixed to the value specified by the data width, one transfer unit consists of the number of transfer cycles for the specified block size. During a transfer, if a transfer request with higher priority is accepted or if a transfer temporary stop request is generated, the transfer stops only at the transfer unit boundary whether or not the transfer is a block transfer. Although this prevents data in the data block from undesirable splitting or temporary stopping, it may cause the response to be slower if the block size is large. Transfer stops immediately only when a reset occurs, in which case the data being transferred cannot be guaranteed. ■ Reload Operation In this module, the following three types of reload function are available to be set for each channel: (1) Transfer count register reload function After transfer is performed the specified number of times, the initial value is set in the transfer count register again and waiting for an activation request. Use this setting to perform any of the transfer sequences repeatedly. If reloading is not enabled, the count register remains at "0" after the specified number of transfers is completed and no further transfers are performed. (2) Transfer source address register reload function After transfer is performed the specified number of times, the initial value is set in the transfer source address register again. Use this setting if repeatedly performing a transfer from a fixed area in the transfer source address area. If reloading is not enabled, after the specified number of transfers is completed, the value in the transfer source address register becomes the next address. Use this setting if the address area is not fixed. (3) Transfer destination address register reload function After transfer is performed the specified number of times, the initial value is set in the transfer destination address register again. Use this setting if repeatedly performing a transfer to a fixed area in the transfer destination address area. (Other features are the same as (2).) Enabling the reload functions for transfer source and destination address registers by itself does not cause transfer to restart after the specified number of transfers is completed. It only causes the address registers to be reloaded with their initial values. 424 CHAPTER 15 DMAC (DMA CONTROLLER) [Special case of operation mode and reload operation] When a transfer is executed in the continuous transfer mode by external pin input level detection, if a reload function of the transfer count register is used, the transfer is continued by reloading without stopping even if the transfer is completed while input is continued. If you want to stop the transfer at the end of transfer and restart it from the input detection, do not set a reload setting. When using burst, block, or step transfer modes, transfer is suspended once after the reload is performed at the end of the transfer operation, and no further transfer is performed until a new transfer request input is detected. 425 CHAPTER 15 DMAC (DMA CONTROLLER) 15.3.5 Addressing Mode The transfer destination address and transfer source address are specified independently for each transfer channel. The specification method is explained below. Use transfer sequence to specify addresses. ■ Address Register Specification In 2-cycle transfer mode, set the transfer source address in the transfer source address setting register (DMASA) and the transfer destination address in the transfer destination address setting register (DMADA). [Features of the address register] 32-bit length register [Function of the address register] • The registers are read each time an access is performed and outputted to the address bus. • The address counter is used to calculate the address for the next access at the same time and the address register is updated by the address of the result of this calculation. • The address calculation is selected from either incrementing or decrementing calculation independently for each channel, transfer source, and transfer destination. The width of the address increment or decrement is specified by the address count size specification register values (DMACB: SASZ, DASZ). • When the reload function is not enabled for an address register, address of the result of the address calculation remains in the register after the transfer ends. • If the reload function is enabled, the initial value of the address is reloaded. Reference: If an overflow or underflow occurs as a result of 32-bit length address calculation, the result is detected as an address error and a transfer on the corresponding channel is stopped. (Refer to "Table 15.2-17"). Notes: • Do not set addresses of DMAC’s own registers in the address registers. • Do not transfer to DMAC’s own registers by the DMAC. 426 CHAPTER 15 DMAC (DMA CONTROLLER) 15.3.6 Data Types Select the data length (data width) to be transferred in one transfer operation from the following: • Byte • Halfword • Word ■ Access Address Since the word boundary specification is also observed in DMA transfer, different low-order bits are ignored if an address with a different data length is specified for the transfer destination/transfer source address. • Word: The actual access address is a 4-byte length starting with "00B" in the lowest 2 bits. • Halfword: The actual access address is a 2-byte length starting with "0B" in the lowest 1 bit. • Byte: The actual access address and the addressing are the same. If the lowest-order bits in the transfer source address and transfer destination address are different, the addresses as set are outputted on the internal address bus. However, each transfer target on the bus is accessed after the addresses are corrected according to the above rules. 427 CHAPTER 15 DMAC (DMA CONTROLLER) 15.3.7 Transfer Number Control The transfer number is specified within the range of the maximum 16-bit length (1 to 65536 times). Set the number of transfers in the transfer count register (DMACA:DTC). ■ Transfer Count Register and Reload Operation The register value is stored in a temporary storage buffer when transfer starts, and is decremented by the transfer counter. When the counter value becomes "0", it is detected as the end of transfer for the specified count, and the transfer on the channel is stopped or waiting for a restart request (when reload is specified). [Features of transfer count registers] • Each register has 16-bit length. • Each register has a dedicated reload register. • Setting the register value to "0" results in transfer being performed 65536 times. [Reload operation] • Register has a reload function and the reload function is valid only if it is enabled. • The initial value of the count register is saved in the reload register when transfer is activated. • Once the count of the transfer counter reaches to "0", a signal indicating transfer completion is outputted as well as the initial value is read from the reload register and written to the count register. 428 CHAPTER 15 DMAC (DMA CONTROLLER) 15.3.8 CPU Control When a DMA transfer request is accepted, DMA issues a transfer request to the bus controller. The bus controller passes the right to use the internal bus to DMA at a break in bus operation and DMA transfer starts. ■ DMA Transfer and Interrupts During DMA transfer, if an NMI request or an interrupt request with a higher level than the hold suppress level set by the HRCL register of the interrupt controller occurs, DMAC temporarily cancels the transfer request to the bus controller at a transfer unit boundary (one block) and temporarily stops the transfer until the interrupt request is cleared. In the meantime, the transfer request is retained internally. After the interrupt request is cleared, DMAC issues a transfer request to the bus controller again to acquire the right to use the bus and then restarts DMA transfer. If an interrupt level is lower than the level set by the HRCL register, interrupt requests are not accepted until DMA transfer ends. If a DMA transfer request is generated during an interrupt processing with a lower level than the level of the HRCL setting value, the transfer request is accepted and the interrupt processing operation is stopped until the transfer ends. In the default setting, DMA transfer request level is set to the lowest level, in which the transfer is stopped for all the interrupt requests and the interrupt processing is prioritized. ■ DMA Suppression When an interrupt source with a higher priority occurs during DMA transfer, an FR family device interrupts the DMA transfer and branches to the relevant interrupt routine. This feature is valid as long as there are any interrupt requests. When all interrupt factors are cleared, the suppression feature no longer works and the DMA transfer is restarted by the interrupt processing routine. Thus, if you want to suppress restart of DMA transfer after clearing interrupt factors in the interrupt factor processing routine at a level that interrupts DMA transfer, use the DMA suppression function. The DMA suppression function is activated by writing a non-zero value to the DMAH[3:0] bits in the DMA all-channel control register and is stopped by setting the bits to "0". This function is mainly used in the interrupt processing routines. Before the interrupt factors are cleared in an interrupt processing routine, the content of DMA suppression register is incremented by 1. By doing this, no DMA transfer will not be performed from then on. After interrupt processing, the contents of DMAH[3:0] bits is decremented by 1 before returning. If multiple interrupts have occurred, DMA transfer continues to be suppressed since the contents of DMAH[3:0] bits do not become "0" yet. If a single interrupt has occurred, the contents of DMAH[3:0] bits become "0" and so the DMA requests are then enabled immediately. Note: • Since the register has only four bits, this function cannot be used for multiple interrupts exceeding 15 levels. • Be sure to assign the priority of the DMA tasks at a level that is at least 15 levels higher than other interrupt levels. 429 CHAPTER 15 DMAC (DMA CONTROLLER) 15.3.9 Starting Operation Starting of DMA transfer is controlled independently for each channel, but before transfer starts, the operation of all channels needs to be enabled. ■ Enabling Operations for All Channels Before activated in each DMAC channel, operation for all channels needs to be enabled in advance with the DMA operation enable bit (DMACR:DMAE). All start settings and transfer requests that occurred before operation is enabled become invalid. ■ Starting Transfer The transfer operation can be started by the operation enable bit of the control register for each channel. If a transfer request to an activated channel is accepted, the DMA transfer operation is started in the specified mode. ■ Starting from Temporary Stop State If a temporary stop occurs before starting with channel-by-channel or all-channel control, the temporary stop state is maintained even though the transfer operation is started. If transfer requests occur in this period, they are accepted and retained. A transfer is started from the point where a temporary stop is cancelled. 430 CHAPTER 15 DMAC (DMA CONTROLLER) 15.3.10 Transfer Request Acceptance and Transfer This section explains the acceptance of transfer request and the contents of transfer. ■ Transfer Request Acceptance and the Transfer Sampling for transfer requests set for each channel starts after starting. When activation of peripheral interrupts is selected, the DMAC continues the transfer operation until the transfer request is cleared. If it is cleared, the transfer is stopped in each transfer unit (activation of peripheral interrupts). Since peripheral interrupts are handled as level detections, the interrupt needs to be generated using interrupt clear by DMA. Transfer requests are always accepted while requests for other channels are being accepted and the transfer is being performed. The channel that will be used for transfer is determined for each transfer unit by checking the priority. 431 CHAPTER 15 DMAC (DMA CONTROLLER) 15.3.11 Clearing Peripheral Interrupts by DMA This DMA has a function that clears peripheral interrupts. This function works when peripheral interrupt is selected as the DMA activation factor (when IS[4:0]= 1XXXXB). Peripheral interrupts are cleared only for the set activation factors. That is, only the peripheral functions set by IS[4:0] are cleared. ■ Timing for Clearing an Interrupt by DMA The timing for clearing an interrupt depends on the transfer mode. (See section "15.4 Operational Flow of DMAC (DMA Controller)"). [Block/step transfer] If block transfer is selected, a clear signal is generated after one block (step) transfer. [Burst transfer] If burst transfer is selected, a clear signal is generated after transfer is performed the specified number of times. 432 CHAPTER 15 DMAC (DMA CONTROLLER) 15.3.12 Temporary Stop This section explains the case when the DMA transfer stops temporarily. ■ Setting of Temporary Stop by Writing to the Control Register (Set Independently for Each Channel or All Channels Simultaneously) If temporary stop is set using a temporary stop bit, transfer on the corresponding channel is stopped until cancellation setting of the temporary stop is set again. Temporary stop can be checked by DSS bits. Transfer is restarted when temporary stop is canceled. ■ NMI/Hold Suppression Level Interrupt Processing If an NMI request or an interrupt request with a higher level than the hold suppression level occurs, all channels on which transfer is in progress are temporarily stopped at the boundary of the transfer unit and the bus right is opened to give priority to NMI/interrupt processing. Transfer requests accepted during NMI/interrupt processing are retained, and wait for the completion of NMI processing. Channels for which requests are retained restart transfer after NMI/interrupt processing is completed. 433 CHAPTER 15 DMAC (DMA CONTROLLER) 15.3.13 Operation End/Stop The end of DMA transfer is controlled independently for each channel. It is also possible to disable operation for all channels at once. ■ End of Transfer If reload operation is disabled, transfer is stopped after the transfer count register becomes "0", then "Normal end" is displayed as the exit code, and all subsequent transfer requests are disabled. (DMACA:DENB bit is cleared.) If reload operation is enabled, the initial value is reloaded after the transfer count register becomes "0", then "Normal end" is displayed as the exit code, and the state enters a wait state for transfer requests once again. (DMACA:DENB bit is not cleared.) ■ Disabling All Channels If the operation of all channels is disabled with the DMA operation enable bit DMAE, all DMAC operations, including operations on active channels, are stopped. Then, even if the operation of all channels is enabled again, no transfer is performed unless each channel is restarted individually. In this case, no interrupt occurs. 434 CHAPTER 15 DMAC (DMA CONTROLLER) 15.3.14 Error Stop In addition to normal end by the completion of transfer for the number of times specified, stopping by various types of errors and forced stopping are provided. ■ Transfer Stop Requests from Peripheral Circuits Depending on the peripheral circuit that outputs a transfer request, a transfer stop request is issued when an error is detected (Example: Error when data is received at or sent from a communications system peripheral). The DMAC, when it receives such a transfer stop request, displays "Transfer stop request" as the exit code and stops the transfer on the corresponding channel. ■ Occurrence of an Address Error If an inappropriate addressing is executed in each addressing mode, an address error is detected (An "inappropriate addressing" is, for example, "a case if an overflow or underflow occurs in the address counter when a 32-bit address is specified"). If an address error is detected, "Address error occurs" is displayed as the exit code and the transfer on the corresponding channel is stopped. 435 CHAPTER 15 DMAC (DMA CONTROLLER) 15.3.15 DMAC Interrupt Control DMAC interrupt control can output interrupts for each DMAC channel independently from peripheral interrupts that become transfer requests. ■ Interrupts That DMAC Interrupt Control can Output • Transfer end interrupt: Occurs only when operation ends normally. • Error interrupt: Transfer stop request from peripheral circuit (error due to a peripheral) Occurrence of address error (error due to software) All of these interrupts are outputted according to the content of the exit code. An interrupt request can be cleared by writing "000B" to DSS2 to DSS0 (exit code) of DMACS. Be sure to clear the exit code by writing "000B" before restarting. If reload operation is enabled, the transfer is automatically restarted. At this point, however, the exit code is not cleared and is retained until a new exit code is written when the next transfer ends. Since only one end factor can be displayed in an exit code, the result after evaluating the priority is displayed when multiple factors occur simultaneously. The interrupt that occurs at this point complies with the displayed exit code. The following shows the priority in order of descending priority for displaying exit codes: • Reset • Clearing by writing "000B" • Peripheral stop request • Normal end • Stopping by detecting address error • Channel selection and control 436 CHAPTER 15 DMAC (DMA CONTROLLER) 15.3.16 DMA Transfer during Sleep Mode The DMAC can also operate in sleep mode. This section explains the DMA transfer in a sleep state. ■ Notes on DMA Transfer in Sleep Mode If DMA transfer during a sleep mode, ensure the following points: • Since the CPU is stopped, DMAC registers cannot be rewritten. Make settings before the device enters sleep mode. • The sleep mode is cancelled by an interrupt. Thus, if a peripheral interrupt is selected as a DMAC activation factor, interrupts must be disabled by the interrupt controller. Similarly, if you do not want to cancel the sleep mode by a DMAC end interrupt, disable DMAC end interrupts. 437 CHAPTER 15 DMAC (DMA CONTROLLER) 15.3.17 Channel Selection and Control Up to five channels can be simultaneously set as transfer channels. In general, an independent function can be set for each channel. ■ Priority Among Channels Since DMA transfer is allowed only in one channel at a time, priority must be set for the channels. Two modes, fixed and rotation, are provided as the priority settings and can be selected for each channel group (Refer to "■ Channel Group"). ● Fixed mode The priority is fixed by channel number in ascending order. (ch.0 > ch.1 > ch.2 > ch.3 > ch.4) If a transfer request with a higher priority is accepted during a transfer, the transfer channel is switched to the channel with the higher priority when the transfer for the transfer unit (number set in the block size specification register × data width) ends. When higher priority transfer is completed, transfer is restarted on the previous channel. Figure 15.3-3 shows the DMA transfer in fixed mode. Figure 15.3-3 DMA Transfer in Fixed Mode ch.0 transfer request ch.1 transfer request Bus operation CPU SA Transfer channel DA SA ch.1 DA SA ch.0 DA SA ch.0 DA CPU ch.1 ch.0 transfer end ch.1 transfer end ● Rotation mode (between ch.0 and ch.1 only) The initial state after operation is enabled is set to the same order as fixed mode, but the priorities of the channels are reversed at the end of each transfer operation. Thus, if more than one transfer request is outputted at the same time, the channel is switched per each transfer unit. This mode is effective when continuous/burst transfer is set. Figure 15.3-4 shows the DMA transfer operation in rotation mode. Figure 15.3-4 DMA Transfer in Rotation Mode ch.0 transfer request ch.1 transfer request Bus operation Transfer channel ch.0 transfer end ch.1 transfer end 438 CPU SA DA ch.1 SA DA ch.0 SA DA ch.1 SA DA ch.0 CPU CHAPTER 15 DMAC (DMA CONTROLLER) ■ Channel Group Set the selection of priority as the unit explained in the table below. Table 15.3-3 shows the DMA priority selection setting. Table 15.3-3 DMA Priority Selection Setting Mode Priority Remarks Fixed ch.0 > ch.1 − Rotation ch.0 > ch.1 ↑↓ ch.0 < ch.1 The initial state is shown in the upper row. If transfer occurs in the state of the upper row, the priority is inverted. 439 CHAPTER 15 DMAC (DMA CONTROLLER) 15.4 Operational Flow of DMAC (DMA Controller) Figure 15.4-1 and Figure 15.4-2 show operational flows of DMA transfer. ■ Operational Flow of Block Transfer Figure 15.4-1 Block Transfer DMA stop DENB=>0 DENB=1 Activation request wait Reload enabled Activation request Initial address, transfer number, block number loading Transfer source address access address calculation Access is executed only once when accessing by fly-by. Transfer destination address access address calculation BLK=0 Only when peripheral interrupt activation factor is selected. Address, transfer number, block number writing back Interrupt clear is generated. Interrupt clear DTC=0 DMA transfer end DMA interrupt is generated. Block transfer • Activation is enabled by all activation factors (select). • Access is enabled to all areas. • Block number is settable. • Interrupt clear is issued after the completion of block number. • DMA interrupt is issued after the completion of specified transfer number. 440 CHAPTER 15 DMAC (DMA CONTROLLER) ■ Operational Flow of Burst Transfer Figure 15.4-2 Burst Transfer DMA stop DENB=>0 DENB=1 Reload enabled Activation request wait Initial address, transfer number, block number loading Transfer source address access address calculation Access is executed only once when accessing by fly-by. Transfer destination address access address calculation BLK=0 DTC=0 Address, transfer number, block number writing back Only when peripheral interrupt activation factor is selected. Interrupt clear Interrupt clear is generated. DMA transfer end DMA interrupt is generated. Burst transfer • Activation is enabled by all activation factors (select). • Access is enabled to all areas. • Block number is settable. • DMA interrupt is issued after the completion of specified transfer number. 441 CHAPTER 15 DMAC (DMA CONTROLLER) 15.5 Data Path of DMAC (DMA Controller) This section shows data paths for each transfer. ■ Data Paths During 2-cycle Transfer Figure 15.5-1 to Figure 15.5-6 show data paths during 2-cycle transfer. Figure 15.5-1 External Area → External Area Transfer Read cycle CPU I-bus X-bus Bus controller D-bus MB91xxx DMAC Write cycle I-bus CPU DMAC External bus I/F MB91xxx Data buffer X-bus Bus controller D-bus Data buffer F-bus RAM External bus I/F External Area ⇒ External Area Transfer F-bus I/O RAM I/O Figure 15.5-2 External Area → Internal RAM Area Transfer Read cycle CPU I-bus X-bus Bus controller D-bus Data buffer MB91xxx DMAC Write cycle I-bus X-bus Bus controller D-bus Data buffer F-bus RAM 442 F-bus I/O RAM I/O External bus I/F DMAC CPU MB91xxx External bus I/F External Area ⇒ Internal RAM Area Transfer CHAPTER 15 DMAC (DMA CONTROLLER) Figure 15.5-3 External Area → Built-in I/O Area Transfer Read cycle CPU I-bus X-bus Bus controller D-bus MB91xxx DMAC Write cycle I-bus Data buffer X-bus Bus controller D-bus Data buffer F-bus RAM External bus I/F DMAC CPU MB91xxx External bus I/F External Area ⇒ Built-in I/O Area Transfer F-bus RAM I/O I/O Figure 15.5-4 Built-in I/O Area → Built-in RAM Area Transfer Read cycle CPU I-bus X-bus Bus controller D-bus Data buffer MB91xxx DMAC Write cycle I-bus X-bus Bus controller D-bus F-bus RAM External bus I/F DMAC CPU MB91xxx External bus I/F Built-in I/O Area ⇒ Built-in RAM Area Transfer F-bus I/O RAM I/O 443 CHAPTER 15 DMAC (DMA CONTROLLER) Figure 15.5-5 Internal RAM Area → External Area Transfer Read cycle CPU I-bus X-bus Bus controller Data buffer D-bus MB91xxx DMAC Write cycle I-bus X-bus Bus controller D-bus Data buffer F-bus RAM External bus I/F DMAC CPU MB91xxx External bus I/F Internal RAM Area ⇒ External Area Transfer F-bus RAM I/O I/O Figure 15.5-6 Internal RAM Area → Built-in I/O Area Transfer Read cycle X-bus CPU I-bus Bus controller D-bus Data buffer MB91xxx DMAC Write cycle X-bus I-bus Bus controller D-bus Data buffer F-bus RAM 444 I/O F-bus RAM I/O External bus I/F DMAC CPU MB91xxx External bus I/F Internal RAM Area ⇒ Built-in I/O Area Transfer CHAPTER 16 CAN CONTROLLER This chapter describes the functions and operations of the CAN controller. 16.1 Features of CAN 16.2 CAN Block Diagram 16.3 CAN Registers 16.4 CAN Register Functions 16.5 CAN Controller Functions 445 CHAPTER 16 CAN CONTROLLER 16.1 Features of CAN CAN conforms to the CAN Protocol Version 2.0A/B, which is a standard protocol for serial communication. It is widely used in industrial fields including automobile and factory automation. ■ Features of CAN CAN has the following features: • Support for the CAN Protocol Version 2.0A/B • Support for bit rates up to 1 Mbps • Identification mask for each message object • Support for the programmable FIFO mode • Maskable interrupt • Support for the programmable loop-back mode for self test operation • Reading/writing from/to the message buffer through the interface register 446 CHAPTER 16 CAN CONTROLLER 16.2 CAN Block Diagram Figure 16.2-1 shows the CAN block diagram. Figure 16.2-1 CAN Block Diagram CAN_TX CAN_RX C_CAN Message handler CAN controller Message RAM Register group Interrupt DataOUT DataIN Address[7:0] Control Reset Clock CPU interface ■ CAN Controller Controls the serial register for serial/parallel conversion used for transferring the CAN protocol and transmission/reception messages. ■ Message RAM Stores message objects. ■ Register Group All registers used in CAN. ■ Message Handler Controls the message RAM and CAN controller. ■ CPU Interface Controls the interface of the FR family internal bus. 447 CHAPTER 16 CAN CONTROLLER 16.3 CAN Registers CAN has the following registers: • CAN control register (CTRLR) • CAN status register (STATR) • CAN error counter (ERRCNT) • CAN bit timing register (BTR) • CAN interrupt register (INTR) • CAN test register (TESTR) • CAN prescaler expansion register (BRPE) • IFx command request register (IFxCREQ) • IFx command mask register (IFxCMSK) • IFx mask registers 1, 2 (IFxMSK1, IFxMSK2) • IFx arbitration registers 1, 2 (IFxARB1, IFxARB2) • IFx message control register (IFxMCTR) • IFx data registers A1, A2, B1, B2 (IFxDTA1, IFxDTA2, IFxDTB1, IFxDTB2) • CAN transmission request registers 1, 2 (TREQR1, TREQR2) • CAN New Data registers 1, 2 (NEWDT1, NEWDT2) • CAN interrupt pending registers 1, 2 (INTPND1, INTPND2) • CAN message validation registers 1, 2 (MSGVAL1, MSGVAL2) • CAN clock prescaler register (CANPRE) 448 CHAPTER 16 CAN CONTROLLER ■ List of the General Control Registers Table 16.3-1 List of General Control Registers Register Address Comment +0 +1 CAN control register Base-addr + 00H Initial value Initial value Initial value CAN status register bit7 to bit0 bit15 to bit8 bit7 to bit0 Reserved CTRLR Reserved STATR 00000000B 00000001B 00000000B 00000000B CAN bit timing register bit15 to bit8 bit7 to bit0 bit15 to bit8 bit7 to bit0 RP, REC[6:0] TEC[7:0] TSeg2[2:0], TSeg1[3:0] SJW[1:0], BRP[5:0] 00000000B 00000000B 00100011B 00000001B CAN interrupt register Base-addr + 08H +3 bit15 to bit8 CAN error counter Base-addr + 04H +2 CAN test register bit15 to bit8 bit7 to bit0 bit15 to bit8 bit7 to bit0 IntId15 to IntId8 IntId7 to IntId0 Reserved TESTR 00000000B 00000000B 00000000B 00000000B r0000000B CAN prescaler expansion register Base-addr + 0CH Initial value Reserved bit15 to bit8 bit7 to bit0 bit15 to bit8 bit7 to bit0 Reserved BRP3 to BRP0 Reserved Reserved 00000000B 00000000B 00000000B 00000000B − The error counter is read only. The bit timing register is set to be writable by setting CCE. The interrupt register is read only. The test register is set to be usable by setting TSET. Value "r" in TESTR indicates the value of the CAN_RX pin. The prescaler expansion register is set to be writable by setting CCE. 449 CHAPTER 16 CAN CONTROLLER ■ List of the Message Interface Registers Table 16.3-2 List of Message Interface Registers (1 / 2) Register Address Comment +0 +1 IF1 command request register Base-addr + 10H Initial value Initial value Initial value IF1 command mask register bit7 to bit0 bit15 to bit8 bit7 to bit0 BUSY Mess. No. 5 to 0 Reserved IF1CMSK 00000000B 00000001B 00000000B 00000000B bit7 to bit0 bit15 to bit8 bit7 to bit0 MXtd. MDir, Msk28 to Msk24 Msk23 to Msk16 Msk15 to Msk8 Msk7 to Msk0 11111111B 11111111B 11111111B 11111111B Initial value bit15 to bit8 bit7 to bit0 bit15 to bit8 bit7 to bit0 MsgVal, Xtd, Dir, ID28 to ID24 ID23 to ID16 ID15 to ID8 ID7 to ID0 00000000B 00000000B 00000000B 00000000B Base-addr + 20H Initial value bit7 to bit0 bit15 to bit8 bit7 to bit0 IF1MCTR IF1MCTR Reserved Reserved 00000000B 00000000B 00000000B 00000000B Base-addr + 24H Initial value bit15 to bit8 bit7 to bit0 bit15 to bit8 Data[0] Data[1] Data[2] Data[3] 00000000B 00000000B 00000000B 00000000B Initial value bit15 to bit8 bit7 to bit0 bit15 to bit8 Data[4] Data[5] Data[6] Data[7] 00000000B 00000000B 00000000B 00000000B Initial value 450 IF1 data register A1 bit15 to bit8 bit7 to bit0 bit15 to bit8 bit7 to bit0 Data[3] Data[2] Data[1] Data[0] 00000000B 00000000B 00000000B 00000000B IF1 data register B2 Base-addr + 34H IF1 data register B2 bit7 to bit0 IF1 data register A2 Base-addr + 30H IF1 data register A2 bit7 to bit0 IF1 data register B1 − Reserved bit15 to bit8 IF1 data register A1 − IF1 arbitration register 1 IF1 message control register Base-addr + 1CH − IF1 mask register 1 bit15 to bit8 IF1 arbitration register 2 Base-addr + 18H +3 bit15 to bit8 IF1 mask register 2 Base-addr + 14H +2 IF1 data register B1 bit15 to bit8 bit7 to bit0 bit15 to bit8 bit7 to bit0 Data[7] Data[6] Data[5] Data[4] 00000000B 00000000B 00000000B 00000000B − Big endian byte Big endian byte Little endian byte Little endian byte CHAPTER 16 CAN CONTROLLER Table 16.3-2 List of Message Interface Registers (2 / 2) Register Address Comment +0 +1 IF2 command request register Base-addr + 40H Initial value Initial value Initial value IF2 command mask register bit7 to bit0 bit15 to bit8 bit7 to bit0 BUSY Mess. No. 5 to 0 Reserved IF2CMSK 00000000B 00000001B 00000000B 00000000B bit7 to bit0 bit15 to bit8 bit7 to bit0 MXtd. MDir, Msk28 to Msk24 Msk23 to Msk16 Msk15 to Msk8 Msk7 to Msk0 11111111B 11111111B 11111111B 11111111B Initial value bit15 to bit8 bit7 to bit0 bit15 to bit8 bit7 to bit0 IF2MCTR IF2MCTR Reserved Reserved 00000000B 00000000B 00000000B 00000000B Base-addr + 50H Initial value bit7 to bit0 bit15 to bit8 bit7 to bit0 IF2MCTR IF2MCTR Reserved Reserved 00000000B 00000000B 00000000B 00000000B Base-addr + 54H Initial value bit15 to bit8 bit7 to bit0 bit15 to bit8 Data[0] Data[1] Data[2] Data[3] 00000000B 00000000B 00000000B 00000000B Initial value bit15 to bit8 bit7 to bit0 bit15 to bit8 Data[4] Data[5] Data[6] Data[7] 00000000B 00000000B 00000000B 00000000B Initial value IF2 data register A1 bit15 to bit8 bit7 to bit0 bit15 to bit8 bit7 to bit0 Data[3] Data[2] Data[1] Data[0] 00000000B 00000000B 00000000B 00000000B IF2 data register B2 Base-addr + 64H IF2 data register B2 bit7 to bit0 IF2 data register A2 Base-addr + 60H IF2 data register A2 bit7 to bit0 IF2 data register B1 − Reserved bit15 to bit8 IF2 data register A1 − IF2 arbitration register 1 IF2 message control register Base-addr + 4CH − IF2 mask register 1 bit15 to bit8 IF2 arbitration register 2 Base-addr + 48H +3 bit15 to bit8 IF2 mask register 2 Base-addr + 44H +2 IF2 data register B1 bit15 to bit8 bit7 to bit0 bit15 to bit8 bit7 to bit0 Data[7] Data[6] Data[5] Data[4] 00000000B 00000000B 00000000B 00000000B − Big endian byte Big endian byte Little endian byte Little endian byte 451 CHAPTER 16 CAN CONTROLLER ■ List of the Message Handler Registers Table 16.3-3 List of Message Handler Registers (1 / 2) Register Address Comment +0 +1 CAN transmission request register 2 Base-addr + 80H Initial value Initial value Initial value bit15 to bit8 bit7 to bit0 TxRqst32 to TxRqst25 TxRqst24 to TxRqst17 TxRqst16 to TxRqst9 TxRqst8 to TxRqst1 00000000B 00000000B 00000000B 00000000B Initial value Base-addr + 98H Base-addr + A0H Initial value 452 CAN transmission request register 3 bit15 to bit8 bit7 to bit0 bit15 to bit8 bit7 to bit0 TxRqst64 to TxRqst57 TxRqst56 to TxRqst49 TxRqst48 to TxRqst41 TxRqst40 to TxRqst33 00000000B 00000000B 00000000B 00000000B CAN data update register 1 bit15 to bit8 bit7 to bit0 bit15 to bit8 bit7 to bit0 NewDat32 to NewDat25 NewDat24 to NewDat17 NewDat16 to NewDat9 NewDat8 to NewDat1 00000000B 00000000B 00000000B 00000000B CAN data update register 4 Base-addr + 94H CAN transmission request register 1 bit7 to bit0 CAN data update register 2 Base-addr + 90H +3 bit15 to bit8 CAN transmission request register 4 Base-addr + 84H +2 CAN data update register 3 bit15 to bit8 bit7 to bit0 bit15 to bit8 bit7 to bit0 NewDat64 to NewDat57 NewDat56 to NewDat49 NewDat49 to NewDat41 NewDat40 to NewDat33 00000000B 00000000B 00000000B 00000000B Reserved (used when the number of message buffers is 65 or more) CAN interrupt pending register 2 CAN interrupt pending register 1 bit15 to bit8 bit7 to bit0 bit15 to bit8 bit7 to bit0 IntPnd32 to IntPnd25 IntPnd24 to IntPnd17 IntPnd16 to IntPnd9 IntPnd8 to IntPnd1 00000000B 00000000B 00000000B 00000000B The transmission request register is read only. The transmission request register is read only. (ch.1 of MB91F467R) The data update register is read only. The data update register is read only. (ch.1 of MB91F467R) − The interrupt pending register is read only. CHAPTER 16 CAN CONTROLLER Table 16.3-3 List of Message Handler Registers (2 / 2) Register Address Comment +0 Base-addr + A4H Initial value Base-addr + A8H +1 CAN interrupt pending register 3 bit15 to bit8 bit7 to bit0 bit15 to bit8 bit7 to bit0 IntPnd64 to IntPnd57 IntPnd56 to IntPnd49 IntPnd48 to IntPnd41 IntPnd41 to IntPnd33 00000000B 00000000B 00000000B 00000000B Reserved (used when the number of message buffers is 65 or more) Base-addr + B8H CAN message validation register 1 bit15 to bit8 bit7 to bit0 bit15 to bit8 bit7 to bit0 MsgVal32 to MsgVal25 MsgVal24 to MsgVal17 MsgVal16 to MsgVal9 MsgVal8 to MsgVal1 00000000B 00000000B 00000000B 00000000B CAN message validation register 4 Base-addr +B4H +3 CAN interrupt pending register 4 CAN message validation register 2 Base-addr +B0H +2 CAN message validation register 3 bit15 to bit8 bit7 to bit0 bit15 to bit8 bit7 to bit0 MsgVal64 to MsgVal57 MsgVal56 to MsgVal49 MsgVal48 to MsgVal41 MsgVal40 to MsgVal33 00000000B 00000000B 00000000B 00000000B Reserved (used when the number of message buffers is 65 or more) The interrupt pending register is read only. (ch.1 of MB91F467R) − The message validation register is read only. The message validation register is read only. (ch.1 of MB91F467R) − 453 CHAPTER 16 CAN CONTROLLER ■ Clock Prescaler Register Table 16.3-4 Clock Prescaler Register Register Address 0004C0H Initial value 454 Comment +0 +1 +2 +3 CAN prescaler register − − − bit3 to bit0 − − − CANPRE[3:0] − − − 00000000B − − − CAN prescaler CHAPTER 16 CAN CONTROLLER 16.4 CAN Register Functions Address space of 256 bytes (64 words) is assigned to the CAN registers. The CPU accesses to the message RAM via the message interface register. This section lists the CAN registers and their detailed functions. ■ General Control Registers • CAN control register (CTRLR) • CAN status register (STATR) • CAN error counter (ERRCNT) • CAN bit timing register (BTR) • CAN interrupt register (INTR) • CAN test register (TESTR) • CAN prescaler expansion register (BRPER) ■ Message Interface Registers • IFx command request register (IFxCREQ) • IFx command mask register (IFxCMSK) • IFx mask registers 1, 2 (IFxMSK1, IFxMSK2) • IFx arbitration registers 1, 2 (IFxARB1, IFxARB2) • IFx message control register (IFxMCTR) • IFx data registers A1, A2, B1, B2 (IFxDTA1, IFxDTA2, IFxDTB1, IFxDTB2) ■ Message Handler Registers • CAN transmission request registers 1, 2 (TREQR1, TREQR2) • CAN data update registers 1, 2 (NEWDT1, NEWDT2) • CAN interrupt pending registers 1, 2 (INTPND1, INTPND2) • CAN message validation registers 1, 2 (MSGVAL1, MSGVAL2) ■ Prescaler Register CAN clock prescaler register (CANPRE) 455 CHAPTER 16 CAN CONTROLLER 16.4.1 General Control Register The general control registers control the CAN protocol and operation mode, and provide status information. ■ General Control Registers • CAN control register (CTRLR) • CAN status register (STATR) • CAN error counter (ERRCNT) • CAN bit timing register (BTR) • CAN interrupt register (INTR) • CAN test register (TESTR) • CAN prescaler expansion register (BRPER) 456 CHAPTER 16 CAN CONTROLLER 16.4.1.1 CAN Control Register (CTRLR) The CAN control register (CTRLR) controls the operation mode of the CAN controller. ■ Register Configuration Figure 16.4-1 Bit Configuration of CAN Control Register (CTRLR) CAN control register (High-order byte) bit Address: Base+00H Read/Write → Initial value → 15 14 13 12 11 10 9 8 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved (R) (0) (R) (0) (R) (0) (R) (0) (R) (0) (R) (0) (R) (0) (R) (0) CAN control register (Low-order byte) bit 7 Address: Base+01H Test Read/Write → (R/W) Initial value → (0) 6 5 4 3 2 1 0 CCE (R/W) (0) DAR (R/W) (0) Reserved EIE (R/W) (0) SIE (R/W) (0) IE (R/W) (0) Init (R/W) (0) (R/W) (0) ■ Register Functions [bit15 to bit8] Reserved: Reserved bits "00000000B" is read from these bits. To write a value to these bits, set "00000000B". [bit7] Test: Test mode enable bit Table 16.4-1 Test Mode Enable Bit Test Function 0 Normal operation [Initial value] 1 Test mode [bit6] CCE: Bit timing register writing enable bit Table 16.4-2 Bit Timing Register Writing Enable Bit CCE Function 0 Disables writing to the CAN bit timing register and CAN prescaler expansion register. [Initial value] 1 Enables writing to the CAN bit timing register and CAN prescaler expansion register. This setting is valid when the Init bit is "1". 457 CHAPTER 16 CAN CONTROLLER [bit5] DAR: Automatic re-transmission disable bit Table 16.4-3 Automatic Re-transmission Disable Bit DAR Function 0 Enables automatic re-transmission of a message when arbitration is lost or an error is detected. [Initial value] 1 Disables automatic re-transmission of a message. Based on the CAN specification (Refer to "ISO11898, 6.3.3 Recovery Management"), the CAN controller automatically re-transmits a frame when arbitration is lost or an error is detected during transmission. To enable the automatic re-transmission, reset the DAR bit to "0". To operate CAN in the Time Triggered CAN (TTCAN, refer to "ISO11898-1") environment, you need to set the DAR bit to "1". In the mode where the DAR bit is set to "1", the operations of the TxRqst and NewDat bits in the message object change as follows (For the message object, refer to "16.4.3 Message Object".): • When frame transmission starts, the TxRqst bit in the message object is reset to "0", whereas the NewDat bit remains to be set. • When frame transmission finishes successfully, NewDat is reset to "0". • When an arbitration loss or an error is found in the transmission, NewDat remains to be set. To resume transmission, you need to set TxRqst to "1" from the CPU. [bit4] Reserved: Reserved bit "0" is read from this bit. To write a value to this bit, set "0". [bit3] EIE: Error interrupt code enable bit Table 16.4-4 Error Interrupt Code Enable Bit 458 EIE Function 0 Disables the setting of the interrupt code to the CAN interrupt register according to the change in the BOff or EWarn bit in the CAN status register. [Initial value] 1 Enables the setting of the status interrupt code to the CAN interrupt register according to the change in the BOff or EWarn bit in the CAN status register. CHAPTER 16 CAN CONTROLLER [bit2] SIE: Status interrupt code enable bit Table 16.4-5 Status Interrupt Code Enable Bit SIE Function 0 Disables the setting of the interrupt code to the CAN interrupt register according to the change in the TxOk, RxOk, or LEC bit in the CAN status register. [Initial value] 1 Enables the setting of the status interrupt code to the CAN interrupt register according to the change in the TxOk, RxOk, or LEC bit in the CAN status register. The change in the TxOk, RxOk, or LEC bit which occurred due to the writing from the CPU is not set in the CAN interrupt register. [bit1] IE: Interrupt enable bit Table 16.4-6 Interrupt Enable Bit IE Function 0 Disables the occurrence of an interrupt. [Initial value] 1 Enables the occurrence of an interrupt. [bit0] Init: Initialization bit Table 16.4-7 Initialization Bit Init Function 0 Enables the operation of the CAN controller. 1 Perform initialization. [Initial value] • The bus-off recovery sequence (Refer to "CAN specification Rev. 2.0".) cannot be shortened by setting/canceling the Init bit. When the device is set to bus-off, the CAN controller itself sets the Init bit to "1" to stop all the bus operations. When the Init bit is cleared to "0" in the bus-off status, the bus operation will be stopped until bus idle occurs 129 times continuously (11-bit recessive is counted as one.). The error counter will be reset after the execution of the bus-off recovery sequence. • Start writing to the CAN bit timing register after setting the Init and CCE bits to "1". • Before changing to the low-power consumption mode (stop mode or clock mode), write "1" to the INIT bit to initialize the CAN controller. • To use the CAN prescaler to change the division ratio of the clock which is provided to the CAN interface (CAN clock), set the INIT bit to "1" before changing the setting of the CAN prescaler register. 459 CHAPTER 16 CAN CONTROLLER 16.4.1.2 CAN Status Register (STATR) The CAN status register (STATR) indicates the CAN status and CAN bus status. ■ Register Configuration Figure 16.4-2 Bit Configuration of CAN Status Register (STATR) CAN status register (High-order byte) bit Address: Base+02H Read/Write → Initial value → 15 14 13 12 11 10 9 8 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved (R) (0) (R) (0) (R) (0) (R) (0) (R) (0) (R) (0) (R) (0) (R) (0) 6 5 4 3 2 1 0 TxOk (R/W) (0) (R/W) (0) LEC (R/W) (0) (R/W) (0) CAN status register (Low-order byte) bit Address: Base+03H Read/Write → Initial value → 7 BOff (R) (0) EWarn EPass RxOk (R) (R) (R/W) (0) (0) (0) ■ Register Functions [bit15 to bit8] Reserved: Reserved bits "0" is read from these bits. To write a value to this bit, set "0". [bit7] BOff: Bus-off bit Table 16.4-8 Bus-off Bit BOff Function 0 The CAN controller is not in the bus-off status (Bus Active). [Initial value] 1 The CAN controller is in the bus-off status. [bit6] EWarn: Warning bit Table 16.4-9 Warning Bit EWarn 460 Function 0 Both the transmission and reception counters show a value lower than 96. [Initial value] 1 Either the transmission or reception counter shows a value 96 or higher. CHAPTER 16 CAN CONTROLLER [bit5] EPass: Error passive bit Table 16.4-10 Error Passive Bit EPass Function 0 Both the transmission and reception counters show a value lower than 128 (Error Active status). [Initial value] 1 The reception counter shows RP bit=1, and the transmission counter shows a value 128 or higher (Error Passive status). [bit4] RxOk: Message reception OK bit Table 16.4-11 Message Reception OK Bit RxOk Function 0 The message reception is abnormal or in a bus idle status. [Initial value] 1 The message reception is normal. [bit3] TxOk: Message transmission OK bit Table 16.4-12 Message Transmission OK Bit TxOk Function 0 The message transmission is abnormal or in a bus idle status. [Initial value] 1 The message transmission is normal. Note: The RxOk and TxOk bits can be reset by the CPU only. 461 CHAPTER 16 CAN CONTROLLER [bit2 to bit0] LEC: Last error code bit Table 16.4-13 Last Error Code Bit LEC 000B 001B 010B 011B 100B Status Normal Indicates that the message is transmitted or received normally. [Initial value] Stuff error Indicates that dominant or recessive was detected in the message for 6 bits or more consecutively. Form error Indicates that the fixed format section of the reception frame was received in error. Ack error Indicates that the transmission message was not acknowledged by other nodes. Bit1 error Indicates that dominant was detected in the transmission data of a message other than the arbitration field even after recessive was transmitted. Bit0 error Indicates that recessive was detected in the transmission data of a message even after dominant was transmitted. During the bus recovery, this bit is set every time 11-bit recessive is detected. Reading this bit allows monitoring of the bus recovery sequence. CRC error Indicates that the CRC data in the received message did not match with the calculation result of the CRC data. Undetected When the read value of the LEC bit is "111B" after writing "111B" to the LEC bit from the CPU, it indicates that no transmission/reception was made during the period. (Bus Idle status) 101B 110B 111B Function The LEC bit retains the code which indicates the last error occurred on the CAN bus. When the transfer of a message (reception/transmission) is complete without an error, this bit is set to "000B". The undetected code "111B" should be set by the CPU in order to check code updating. • The status interrupt code (8000H) is set to the CAN interrupt register when the BOff or EWarn bit changes while the EIE bit is "1", or when one of the RxOk, TxOk, and LEC bits changes while the SIE bit is "1". • Since the RxOk and TxOk bits are updated by writing to the CPU, the RxOK and TxOK bits set by the CAN controller are not retained. To use the RxOk and TxOk bits, clear them within (45 × BT) hours after either of RxOk or TxOk bit is set to "1". "BT" represents one bit time. • When the SIE bit is set to "1" and an interrupt occurs due to the change of the LEC bit, do not write a value to the CAN status register. • Such interrupt will not occur due to the change of the EPass bit or the writing by the CPU to the RxOk, TxOk, or LEC bit. • Even when the BOff bit or EPass bit is set to "1", the EWarn bit is set to "1". • Reading this register clears the status interrupt code ("8000H") of the CAN interrupt register. 462 CHAPTER 16 CAN CONTROLLER 16.4.1.3 CAN Error Counter (ERRCNT) The CAN error counter (ERRCNT) shows the reception error passive display as well as the reception and transmission error counters. ■ Register Configuration Figure 16.4-3 Bit Configuration of CAN Error Counter (ERRCNT) CAN error counter register (High-order byte) bit 15 14 13 12 11 10 9 8 Address: Base+04H Read/Write → Initial value → RP (R) (0) (R) (0) (R) (0) REC6 to REC0 (R) (R) (R) (0) (0) (0) (R) (0) (R) (0) 2 1 0 (R) (0) (R) (0) (R) (0) CAN error counter register (Low-order byte) bit Address: Base+05H Read/Write → Initial value → 7 (R) (0) 6 (R) (0) 5 (R) (0) 4 3 TEC7 to TEC0 (R) (R) (0) (0) ■ Register Functions [bit15] RP: Reception error passive display Table 16.4-14 Reception Error Passive Display RP Function 0 The reception error counter is not in the error passive status of the CAN specification. [Initial value] 1 The reception error counter is in the error passive status of the CAN specification. [bit14 to bit8] REC6 to REC0: Reception error counter The value of the reception error counter. The range of the value is 0 to 127. [bit7 to bit0] TEC7 to TEC0: Transmission error counter The value of the transmission error counter. The range of the value is 0 to 255. 463 CHAPTER 16 CAN CONTROLLER 16.4.1.4 CAN Bit Timing Register (BTR) The CAN bit timing register (BTR) sets the prescaler and bit timing. ■ Register Configuration Figure 16.4-4 Bit Configuration of CAN Bit Timing Register (BTR) CAN bit timing register (High-order byte) bit Address: Base+06H Read/Write → Initial value → 15 14 Reserved (R) (0) (R/W) (0) 13 12 TSeg2 (R/W) (R/W) (1) (0) 11 10 9 (R) (0) TSeg1 (R) (R) (0) (1) 8 (R) (1) CAN bit timing register (Low-order byte) bit 7 6 Address: Base+07H SJW Read/Write → (R/W) (R/W) Initial value → (0) (0) 5 (R/W) (0) 4 (R/W) (0) 3 2 BRP (R/W) (R/W) (0) (0) 1 0 (R/W) (0) (R/W) (1) The CAN bit timing register and CAN prescaler expansion register must be set while the CCE and Init bits in the CAN control register are set to "1". 464 CHAPTER 16 CAN CONTROLLER ■ Register Functions [bit15] Reserved: Reserved bit "0" is read from this bit. To write a value to this bit, set "0". [bit14 to bit12] TSeg2: Time segment 2 setting bit The valid setting values are 0 to 7. The value of TSeg2+1 will be time segment 2. Time segment 2 corresponds to the phase buffer segment (PHASE_SEG2) of the CAN specification. [bit11 to bit8] TSeg1: Time segment 1 setting bit The valid setting values are 1 to 15. Setting "0" is prohibited. The value of TSeg1+1 will be time segment 1. Time segment 1 corresponds to the propagation segment (PROP_SEG) + phase buffer segment 1 (PHASE_SEG1) of the CAN specification. [bit7, bit6] SJW: Resynchronization jump width setting bit The valid setting values are 0 to 3. The value of SJW+1 will be the resynchronization jump width. [bit5 to bit0] BRP: Baud rate prescaler setting bit The valid setting values are 0 to 63. The value of BRP+1 will be the baud rate prescaler. The frequency of the CAN clock (fsys) is divided to determine the basic unit hour (tq) of the CAN controller. 465 CHAPTER 16 CAN CONTROLLER 16.4.1.5 CAN Interrupt Register (INTR) The CAN interrupt register (INTR) shows the message interrupt code and status interrupt code. ■ Register Configuration Figure 16.4-5 Bit Configuration of CAN Interrupt Register (INTR) CAN interrupt register (High-order byte) bit 15 14 13 Address: Base+08H Read/Write → Initial value → (R) (0) (R) (0) (R) (0) 12 11 IntId15 to IntId8 (R) (R) (0) (0) 10 9 8 (R) (0) (R) (0) (R) (0) 2 1 0 (R) (0) (R) (0) (R) (0) CAN interrupt register (Low-order byte) bit Address: Base+09H Read/Write → Initial value → 466 7 (R) (0) 6 (R) (0) 5 (R) (0) 4 3 IntId7 to IntId0 (R) (R) (0) (0) CHAPTER 16 CAN CONTROLLER ■ Register Functions Table 16.4-15 Functions of CAN Interrupt Register (INTR) IntId Function 0000H No interrupt 0001H to 0040H Message interrupt code (The interrupt factor is the message object No.) (0021H to 0040H are available only for MB91F467R ch.1.) 0041H to 7FFFH Not used 8000H Status interrupt code (Interrupt by the change of the CAN status register.) 8001H to FFFFH Not used When two or more interrupt codes are pending, the CAN interrupt register indicates the interrupt code of the highest priority. Even if an interrupt code has been set to the CAN interrupt register, when an interrupt code of higher priority is generated, the CAN interrupt register is updated to the interrupt code of higher priority. The interrupt code of the highest priority is the status interrupt code ("8000H"), followed by the message interrupt codes ("0001H", "0002H", "0003H", ... , "0020H"). When the IntId bit is set to a value other than 0000H, and the IE bit in the CAN control register is set to "1", the interrupt signal to the CPU becomes valid. When the value of the IntId bit is set to "0000H" (the interrupt factor is reset) or the IE bit in the CAN control register is reset to "0", the interrupt signal becomes invalid. When the IntPnd bit in the corresponding message object (For details of the message object, refer to "16.4.3 Message Object".) is cleared to "0", the message interrupt code is cleared. The status interrupt code is cleared when the CAN status register is read. 467 CHAPTER 16 CAN CONTROLLER 16.4.1.6 CAN Test Register (TESTR) The CAN test register (TESR) sets the test mode and monitors the RX pin. Refer to "16.5.7 Test Mode" for the operation. ■ Register Configuration Figure 16.4-6 Bit Configuration of CAN Test Register (TESTR) CAN test register (High-order byte) bit Address: Base+0AH Read/Write → Initial value → 15 14 13 12 11 10 9 8 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved (R) (0) (R) (0) (R) (0) (R) (0) (R) (0) (R) (0) (R) (0) (R) (0) 1 0 CAN test register (Low-order byte) bit Address: Base+0BH Read/Write → Initial value → 7 6 5 4 3 2 Rx (R) (r) Tx1 (R/W) (0) Tx0 (R/W) (0) LBack (R/W) (0) Silent (R/W) (0) Basic (R/W) (0) Reserved Reserved (R) (0) (R) (0) The initial value of the Rx in bit7 (r) shows the level on the CAN bus. To write a value to the CAN test register (TESTR), do it after setting the Test bit in the CAN control register (CTRLR) to "1". The test mode is enabled when the Test bit in the CAN control register is set to "1". If the Test bit in the CAN control register is set to "0" during the test mode, the test mode is switched to the normal mode. ■ Register Functions [bit15 to bit8] Reserved: Reserved bits "00000000B" is read from these bits. To write a value to these bits, set "00000000B". [bit7] Rx: Rx pin monitor bit Table 16.4-16 Rx Pin Monitor Bit Rx 468 Function 0 Indicates that the CAN bus is dominant. 1 Indicates that the CAN bus is recessive. CHAPTER 16 CAN CONTROLLER [bit6, bit5] Tx1, Tx0: TX pin control bit Table 16.4-17 TX Pin Control Bit Tx1, Tx0 Function 00B Normal operation [Initial value] 01B A sampling point is output to the Tx pin. 10B Dominant is output to the Tx pin. 11B Recessive is output to the Tx pin. If the Tx bit is set to a value other than "00B", the message cannot be transmitted. [bit4] LBack: Loop-back mode Table 16.4-18 Loop-back Mode LBack Function 0 Disables the loop-back mode. [Initial value] 1 Enables the loop-back mode. [bit3] Silent: Silent mode Table 16.4-19 Silent Mode Silent Function 0 Disables the silent mode. [Initial value] 1 Enables the silent mode. [bit2] Basic: Basic mode Table 16.4-20 Basic Mode Basic Function 0 Disables the basic mode. [Initial value] 1 Enables the basic mode. The IF1 register is used as a transmission message, and the IF2 register is used as a reception message. [bit1, bit0] Reserved: Reserved bits "00B" is read from these bits. To write a value to these bits, set "00B". 469 CHAPTER 16 CAN CONTROLLER 16.4.1.7 CAN Prescaler Expansion Register (BRPER) When the CAN prescaler expansion register (BRPER) is combined with the prescaler specified with the CAN bit timing register, the prescaler used by the CAN controller is expanded. ■ Register Configuration Figure 16.4-7 Bit Configuration of CAN Prescaler Expansion Register (BRPER) CAN prescaler expansion register (High-order byte) bit Address: Base+0CH Read/Write → Initial value → 15 14 13 12 11 10 9 8 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved (R) (0) (R) (0) (R) (0) (R) (0) (R) (0) (R) (0) (R) (0) (R) (0) 4 3 2 1 0 CAN prescaler expansion register (Low-order byte) bit Address: Base+0DH Read/Write → Initial value → 7 6 5 Reserved Reserved Reserved Reserved (R) (0) (R) (0) (R) (0) (R) (0) (R/W) (0) BRPE (R/W) (R/W) (0) (0) (R/W) (0) ■ Register Functions [bit15 to bit4] Reserved: Reserved bits "000000000000B" is read from these bits. To write a value to these bits, set "000000000000B". [bit3 to bit0] BRPE: Baud rate prescaler expansion bit Combining BRP of the CAN bit timing register with BRPE allows the expansion of the baud rate prescaler to 1023 at maximum. The value of "{BRPE (MSB:4 bits), BRP (LSB:6 bits)} + 1" will be the prescaler value of the CAN controller. 470 CHAPTER 16 CAN CONTROLLER 16.4.2 Message Interface Register Two sets of message interface registers are available to control the access from the CPU to the message RAM. There are two sets of message interface registers used to control the access from the CPU to the message RAM. These two sets of registers avoid the conflict of the access from the CPU and CAN controller to the message RAM by buffering the transferred (or to-be-transferred) data (message object). The message objects are transferred simultaneously between the message interface register and the message RAM (For details of the message objects, refer to "16.4.3 Message Object".). Except for the basic test mode, the functions of the two sets of message interface registers are identical and can be operated independently. For example, message interface register IF2 can be used for reading from the message RAM, while message interface register IF1 is used for writing to the message RAM. Table 16.4-21 shows the two sets of message interface registers. The message interface register consists of command registers (command request and command mask registers) and message buffer register controlled by the command registers (mask, arbitration, message control, and data registers). The command mask register indicates the direction of the data transfer and which part of the message object is transferred. The command request register selects a message No. and performs the operation specified with the command mask register. Table 16.4-21 Message Interface Registers IF1 and IF2 Address IF1 register set Address IF2 register set Base + 10H IF1 command request Base + 40H IF2 command request Base + 12H IF1 command mask Base + 42H IF2 command mask Base + 14H IF1 mask 2 Base + 44H IF2 mask 2 Base + 16H IF1 mask 1 Base + 46H IF2 mask 1 Base + 18H IF1 arbitration 2 Base + 48H IF2 arbitration 2 Base + 1AH IF1 arbitration 1 Base + 4AH IF2 arbitration 1 Base + 1CH IF1 message control Base + 4CH IF2 message control Base + 20H IF1 data A1 Base + 50H IF2 data A1 Base + 22H IF1 data A2 Base + 52H IF2 data A2 Base + 24H IF1 data B1 Base + 54H IF2 data B1 Base + 26H IF1 data B2 Base + 56H IF2 data B2 471 CHAPTER 16 CAN CONTROLLER 16.4.2.1 IFx Command Request Register (IFxCREQ) The IFx command request register (IFxCREQ) selects the message No. of the message RAM, and controls the message transfer between the message RAM and message buffer registers. In the basic test mode, IF1 is used for transmission control, and IF2 is used for reception control. ■ Register Configuration Figure 16.4-8 Bit Configuration of IFx Command Request Register (IFxCREQ) IFx command request register (High-order byte) Address: Base+10H bit15 14 13 Base+40H BUSY Reserved Reserved Read/Write → (R/W) Initial value → (0) (R) (0) (R) (0) IFx command request register (Low-order byte) Address: Base+11H bit7 6 5 Base+41H Reserved Read/Write → (R/W) Initial value → (0) (R/W) (0) (R/W) (0) 12 11 10 9 8 Reserved Reserved Reserved Reserved Reserved (R) (0) (R) (0) (R) (0) (R) (0) (R) (0) 4 3 2 1 0 (R/W) (0) (R/W) (0) Message Number (R/W) (R/W) (R/W) (0) (0) (0) ■ Register Functions As soon as a message No. is written to the IFx command request register, message transfer starts between the message RAM and message buffer registers (mask, arbitration, message control, and data registers). This writing operation sets the BUSY bit to "1" to indicate the transfer is being processed. When the transfer finishes, the BUSY bit is reset to "0". When the CPU makes access to the message interface register while the BUSY bit is "1", the CPU is set to wait until the BUSY bit is set to "0" (for 3- to 6-cycle period counted by the clock after the command request register is written). The usage of the BUSY bit is different in the basic test mode. The IF1 command request register is used as a transmission message. When the BUSY bit is set to "1", the register directs to start message transmission. When the message transfer finishes successfully, the BUSY bit is reset to "0". The message transfer can be discontinued any time by resetting the BUSY bit to "0". The IF2 command request register is used as a reception message. When the BUSY bit is set to "1", the received message is stored into the IF2 message interface register. 472 CHAPTER 16 CAN CONTROLLER [bit15] BUSY: Busy flag bit • In the mode other than the basic test mode Table 16.4-22 Busy Flag Bit BUSY Function 0 Indicates that data transfer is not performed between the message interface register and message RAM. [Initial value] 1 Indicates that data transfer is being performed between the message interface register and message RAM. • In the basic test mode - IF1 command request register Table 16.4-23 Busy Flag Bit BUSY Function 0 Disables message transmission. 1 Enables message transmission. - IF2 command request register Table 16.4-24 Busy Flag Bit BUSY Function 0 Disables message reception. 1 Enables message reception. The BUSY bit is readable and writable. In the mode other than the basic test mode, writing any value to this bit does not affect the operation (For details of the basic mode, refer to "16.5.7 Test Mode"). [bit14 to bit7] Reserved: Reserved bits "00000000B" is read from these bits. To write a value to these bits, set "00000000B". 473 CHAPTER 16 CAN CONTROLLER [bit5 to bit0] Message Number: Message No. (ch.0 of MB91461, MB91F467R) Table 16.4-25 Message No. (ch.0 of MB91461, MB91F467R) Message Number Function 00H Setting disabled. When this value is set, it is interpreted as "20H", and message "20H" will be read. 01H to 20H The specified message No. will be processed. 21H to 3FH Setting disabled. When one of these values is set, it is interpreted as "01H" to "1FH", and the message of the corresponding number will be read. [bit6 to bit0] Message Number: Message No. (ch.1 of MB91F467R) Table 16.4-26 Message No. (ch.1 of MB91F467R) Message Number 474 Function 00H Setting disabled. When this value is set, it is interpreted as "20H", and message "20H" will be read. 01H to 40H The specified message No. will be processed. 41H to 7FH Setting disabled. When one of these values is set, it is interpreted as "01H" to "3FH", and the message of the corresponding number will be read. CHAPTER 16 CAN CONTROLLER 16.4.2.2 IFx Command Mask Register (IFxCMSK) The IFx command mask register (IFxCMSK) controls the direction of the data transfer between the message interface register and message RAM, and specifies the data to be updated. In the basic test mode, the setting of this register is invalid. ■ Register Configuration Figure 16.4-9 Bit Configuration of IFx Command Mask Register (IFxCMSK) IFx command mask register (High-order byte) Address: Base+12H bit15 14 13 Base+42H Reserved Reserved Reserved Read/Write → Initial value → (R) (0) (R) (0) (R/W) (0) (R/W) (0) 11 10 9 8 Reserved Reserved Reserved Reserved Reserved (R) (0) IFx command mask register (Low-order byte) Address: Base+13H bit7 6 5 Base+43H WR/RD Mask Arb Read/Write → (R/W) Initial value → (0) 12 (R) (0) (R) (0) (R) (0) (R) (0) (R) (0) 4 3 2 1 0 Control CIP TxRqst/ NewDat Data A Data B (R/W) (0) (R/W) (0) (R/W) (0) (R/W) (0) (R/W) (0) In the basic test mode, the setting of this register is invalid. ■ Register Functions [bit15 to bit8] Reserved: Reserved bits "00000000B" is read from these bits. To write a value to these bits, set "00000000B". [bit7] WR/RD: Write/read control bit Table 16.4-27 Write/read Control Bit WR/RD Function 0 Indicates that data is read from the message RAM. The reading from the message RAM is triggered by writing a message No. to the IFx command request register. The data read from the message RAM depends on the settings of the Mask, Arb, Control, CIP, TxRqst/NewDat, Data A, and Data B bits. [Initial value] 1 Indicates that data is written to the message RAM. The writing to the message RAM is triggered by writing a message No. to the IFx command request register. The data written to the message RAM depends on the settings of the Mask, Arb, Control, CIP, TxRqst/NewDat, Data A, and Data B bits. 475 CHAPTER 16 CAN CONTROLLER After reset, the data in the message RAM is indeterminate. It is prohibited to read the data in the message RAM when the data is indeterminate. The meanings of bit6 to bit0 of the IFx command mask register vary depending on the transfer direction setting (WR/RD bit). ● When the transfer direction is "write" (WR/RD=1) [bit6] Mask: Mask data update bit Table 16.4-28 Mask Data Update Bit Mask Function 0 Do not update the mask data (ID mask + MDir + MXtd) of the message object.* [Initial value] 1 Update the mask data (ID mask + MDir + MXtd) of the message object.* *: Refer to "16.4.3 Message Object". [bit5] Arb: Arbitration data update bit Table 16.4-29 Arbitration Data Update Bit Arb Function 0 Do not update the arbitration data (ID + Dir + Xtd + MsgVal) of the message object.* [Initial value] 1 Update the arbitration data (ID + Dir + Xtd + MsgVal) of the message object.* *: Refer to "16.4.3 Message Object". [bit4] Control: Control data update bit Table 16.4-30 Control Data Update Bit Control Function 0 Do not update the control data (IFx message control register) of the message object.* [Initial value] 1 Update the control data (IFx message control register) of the message object.* *: Refer to "16.4.3 Message Object". [bit3] CIP: Interrupt clear bit Setting either "0" or "1" to this bit does not affect the operation of the CAN controller. 476 CHAPTER 16 CAN CONTROLLER [bit2] TxRqst/NewDat: Message transmission request bit Table 16.4-31 Message Transmission Request Bit TxRqst/NewDat Function 0 Set "0" to the TxRqst bits in the message object* and the CAN transmission request register. [Initial value] 1 Set "1" to the TxRqst bits in the message object* and the CAN transmission request register. (Transmission request) *: Refer to "16.4.3 Message Object". When the TxRqst/NewDat bit in the IFx command mask register is set to "1", the setting of the TxRqst bit in the IFx message control register is invalid. [bit1] Data A: Data0 to Data3 update bit Table 16.4-32 Data0 to Data3 Update Bit Data A Function 0 Do not update data 0 to 3 of the message object.* [Initial value] 1 Update data 0 to 3 of the message object.* *: Refer to "16.4.3 Message Object". [bit0] Data B: Data4 to Data7 update bit Table 16.4-33 Data4 to Data7 Update Bit Data B Function 0 Do not update data 4 to 7 of the message object.* [Initial value] 1 Update data 4 to 7 of the message object.* *: Refer to "16.4.3 Message Object". 477 CHAPTER 16 CAN CONTROLLER ● When the transfer direction is "read" (WR/RD=0) The IntPnd and NewDat bits can be reset to "0" by the read access to the message object. In the IntPnd and NewDat bits in the IFx message control register, however, the values of IntPnd and NewDat bits before the reset by the read access are stored. These settings are invalid in the basic test mode. [bit6] Mask: Mask data update bit Table 16.4-34 Mask Data Update Bit Mask Function 0 Do not transfer data (ID mask + MDir + MXtd) from the message object * to IFx mask register 1/2. [Initial value] 1 Transfer data (ID mask + MDir + MXtd) from the message object * to IFx mask register 1/2. *: Refer to "16.4.3 Message Object". [bit5] Arb: Arbitration data update bit Table 16.4-35 Arbitration Data Update Bit Arb Function 0 Do not transfer data (ID + Dir + Xtd + MsgVal) from the message object * to IFx arbitration register 1/2. [Initial value] 1 Transfer data (ID + Dir + Xtd + MsgVal) from the message object * to IFx arbitration register 1/2. *: Refer to "16.4.3 Message Object". [bit4] Control: Control data update bit Table 16.4-36 Control Data Update Bit Control 478 Function 0 Do not transfer data from the message object * to the IFx message control register. [Initial value] 1 Transfer data from the message object * to the IFx message control register. CHAPTER 16 CAN CONTROLLER [bit3] CIP: Interrupt clear bit Table 16.4-37 Interrupt Clear Bit CIP Function 0 Retain the IntPnd bits in the message object * and the CAN interrupt pending register. [Initial value] 1 Clear the IntPnd bits in the message object * and the CAN interrupt pending register to "0". *: Refer to "16.4.3 Message Object". [bit2] TxRqst/NewDat: Data update bit Table 16.4-38 Data Update Bit TxRqst/NewDat Function 0 Retain the NewDat bits in the message object * and the CAN data update register. [Initial value] 1 Clear the NewDat bits in the message object * and the CAN data update register to "0". *: Refer to "16.4.3 Message Object". [bit1] Data A: Data0 to Data3 update bit Table 16.4-39 Data0 to Data3 Update Bit Data A Function 0 Retain the data of the message object * and CAN data register A1/A2. [Initial value] 1 Update the data of the message object * and CAN data register A1/A2. *: Refer to "16.4.3 Message Object". [bit0] Data B: Data4 to Data7 update bit Table 16.4-40 Data4 to Data7 Update Bit Data B Function 0 Retain the data of the message object * and CAN data register B1/B2. [Initial value] 1 Update the data of the message object * and CAN data register B1/B2. *: Refer to "16.4.3 Message Object". 479 CHAPTER 16 CAN CONTROLLER 16.4.2.3 IFx Mask Registers 1, 2 (IFxMSK1, IFxMSK2) The IFx mask registers (IFxMSK1, IFxMSK2) are used to write/read the message object mask data to/from the message RAM. In the basic test mode, the mask data being set is invalid. For the functions of each bit, refer to "16.4.3 Message Object". ■ Register Configuration Figure 16.4-10 Bit Configuration of IFx Mask Registers 1, 2 (IFxMSK1, IFxMSK2) IFx mask register 2 (High-order byte) Address: Base+14H bit15 14 Base+44H MXtd MDir Read/Write → (R/W) Initial value → (1) (R/W) (1) IFx mask register 2 (Low-order byte) Address: Base+15H bit7 6 Base+45H Read/Write → (R/W) Initial value → (1) (R/W) (1) IFx mask register 1 (High-order byte) Address: Base+16H bit15 14 Base+46H Read/Write → (R/W) Initial value → (1) (R/W) (1) IFx mask register 1 (Low-order byte) Address: Base+17H bit7 6 Base+47H Read/Write → (R/W) Initial value → (1) (R/W) (1) 13 12 Reserved (R) (1) (R/W) (1) 5 4 (R/W) (1) 13 (R/W) (1) 5 (R/W) (1) 11 10 Msk28 to Msk24 (R/W) (R/W) (R/W) (1) (1) (1) 3 2 11 3 Msk7 to Msk0 (R/W) (R/W) (1) (1) (R/W) (1) 0 (R/W) (1) (R/W) (1) 9 8 (R/W) (1) (R/W) (1) 2 1 0 (R/W) (1) (R/W) (1) (R/W) (1) 10 Msk15 to Msk8 (R/W) (R/W) (R/W) (1) (1) (1) 4 8 1 Msk23 to Msk16 (R/W) (R/W) (R/W) (1) (1) (1) 12 9 For the description of each bit in the IFx mask register, refer to "16.4.3 Message Object". "1" is read from the reserved bit in the register (bit13 of IFx mask register 2). To write a value to this bit, write "1". 480 CHAPTER 16 CAN CONTROLLER 16.4.2.4 IFx Arbitration Registers 1, 2 (IFxARB1, IFxARB2) The IFx arbitration registers (IFxARB1, IFxARB2) are used to write/read the message object arbitration data to/from the message RAM. The setting of this register is invalid in the basic test mode. For the functions of each bit, refer to "16.4.3 Message Object". ■ Register Configuration Figure 16.4-11 Bit Configuration of IFx Arbitration Registers 1, 2 (IFxARB1, IFxARB2) IFx arbitration register 2 (High-order byte) Address: Base+18H bit15 14 Base+48H MsgVal Xtd Read/Write → (R/W) Initial value → (0) (R/W) (0) IFx arbitration register 2 (Low-order byte) Address: Base+19H bit7 6 Base+49H Read/Write → (R/W) Initial value → (0) (R/W) (0) IFx arbitration register 1 (High-order byte) Address: Base+1AH bit15 14 Base+4AH Read/Write → (R/W) Initial value → (0) (R/W) (0) IFx arbitration register 1 (Low-order byte) Address: Base+1BH bit7 6 Base+4BH Read/Write → (R/W) Initial value → (0) (R/W) (0) 13 12 Dir (R/W) (0) (R/W) (0) 5 4 (R/W) (0) 13 (R/W) (0) 5 (R/W) (0) 11 3 11 ID15 to ID8 (R/W) (R/W) (0) (0) 4 9 ID28 to ID24 (R/W) (R/W) (R/W) (0) (0) (0) ID23 to ID16 (R/W) (R/W) (0) (0) 12 10 3 ID7 to ID0 (R/W) (R/W) (0) (0) 8 (R/W) (0) 2 1 0 (R/W) (0) (R/W) (0) (R/W) (0) 10 9 8 (R/W) (0) (R/W) (0) (R/W) (0) 2 1 0 (R/W) (0) (R/W) (0) (R/W) (0) For the description of each bit in the IFx arbitration register, refer to "16.4.3 Message Object". When the MsgVal bit in the message object is cleared to "0" during transmission, the TxOk bit in the CAN status register is set to "1" at the completion of the transmission. However, the TxRqst bits in the message object and the CAN transmission request register are not cleared to "0". In such a case, use the message interface register to clear the TxRqst bits to "0". 481 CHAPTER 16 CAN CONTROLLER 16.4.2.5 IFx Message Control Register (IFxMCTR) The IFx message control register (IFxMCTR) is used to write/read the message object control data to/from the message RAM. In the basic test mode, the IF1 message control register is disabled. The NewDat and MsgLst bits in the IF2 message control register operate normally, and the DLC bit shows DLC of the received message. The other control bits operate as invalid ("0"). For the functions of each bit, refer to "16.4.3 Message Object". ■ Register Configuration Figure 16.4-12 Bit Configuration of IFx Message Control Register (IFxMCTR) IFx message control register (High-order byte) Address: Base+1CH bit15 14 13 12 11 Base+4CH NewDat MsgLst IntPnd UMask TxIE Read/Write → (R/W) (R/W) (R/W) (R/W) (R/W) Initial value → (0) (0) (0) (0) (0) IFx message control register (Low-order byte) Address: Base+1DH bit7 6 5 Base+4DH EoB Reserved Reserved Read/Write → (R/W) Initial value → (0) (R) (0) (R) (0) 4 3 Reserved (R) (0) (R/W) (0) 10 9 8 RxIE RmtEn TxRqst (R/W) (R/W) (R/W) (0) (0) (0) 2 1 DLC3 to DLC0 (R/W) (R/W) (0) (0) 0 (R/W) (0) For the description of each bit in the IFx message control register, refer to "16.4.3 Message Object". The TxRqst, NewDat, and IntPnd bits operate as follows depending on the setting of the WR/RD bit in the IFx command mask register. ● When the transfer direction is "write" (IFx command mask register: WR/RD=1) The TxRqst bit in this register is enabled only when the TxRqst/NewDat bit in the IFx command mask register is set to "0". ● When the transfer direction is "read" (IFx command mask register: WR/RD=0) When the CIP bit in the IFx command mask register is set to "1", and the IntPnd bits in the message object and CAN interrupt pending register are reset by writing a message No. to the IFx command request register, the value of the IntPnd bit before the reset is stored in this register. When the TxRqst/NewDat bit in the IFx command mask register is set to "1", and the NewDat bits in the message object and CAN data update register are reset by writing a message No. to the IFx command request register, the value of the NewDat bit before the reset is stored in this register. 482 CHAPTER 16 CAN CONTROLLER 16.4.2.6 IFx Data Registers A1, A2, B1, B2 (IFxDTA1, IFxDTA2, IFxDTB1, IFxDTB2) The IFx data registers (IFxDTA1, IFxDTA2, IFxDTAB1, IFXDTB2) are used to write/read the message object's transmission data to/from the message RAM. These registers are used for the transmission of data frames only, and not used for the transmission of remote frames. ■ Register Configuration Table 16.4-41 Register Configuration addr+0 addr+1 addr+2 addr+3 IFx message data register A1 (Address: 20H & 50H) Data (0) Data (1) - - IFx message data register A2 (Address: 22H & 52H) - - Data (2) Data (3) IFx message data register B1 (Address: 24H & 54H) Data (4) Data (5) - - Data (6) Data (7) IFx message data register B2 (Address: 26H & 56H) IFx message data register A2 (Address: 30H & 60H) Data (3) Data (2) - - IFx message data register A1 (Address: 32H & 62H) - - Data (1) Data (0) IFx message data register B2 (Address: 34H & 64H) Data (7) Data (6) - - IFx message data register B1 (Address: 36H & 66H) - - Data (5) Data (4) Figure 16.4-13 Bit Configuration of IFx Data Register IFx data register bit 15 7 Read/Write → (R/W) Initial value → (0) 14 6 (R/W) (0) 13 5 (R/W) (0) 12 4 11 3 Data (R/W) (R/W) (0) (0) 10 2 9 1 8 0 (R/W) (0) (R/W) (0) (R/W) (0) ■ Register Functions ● Transmission message data setting The setting data is sent from MSB (bit7, bit15), and in the order of Data (0), Data (1), ... , Data (7). ● Reception message data The reception message data is stored from MSB (bit7, bit15), and in the order of Data (0), Data (1), ... , Data (7). If the reception message data is less than 8 bytes, the data stored in the remaining byte(s) in the data register will be indeterminate. The data transfer to the message object is processed in the unit of 4 bytes of Data A or Data B. Consequently, it is impossible to update only the part of data in the 4 bytes. 483 CHAPTER 16 CAN CONTROLLER 16.4.3 Message Object The message RAM contains 32 (128 in some types) message objects. To avoid the conflict of the accesses from the CPU and CAN controller to the message RAM, the CPU cannot directly access to the message object. These accesses are made via the IFx message interface register. This section describes the configuration and functions of the message object. ■ Configuration of the Message Object Table 16.4-42 Message Object UMask Msk28 to Msk0 MsgVal ID28 to ID0 MXtd MDir Xtd Dir EoB NewDat DLC3 to Data0 DLC0 Data1 MsgLst RxIE TxIE IntPnd RmtEn TxRqst Data2 Data3 Data4 Data5 Data6 Data7 Note: The message object cannot be initialized by setting the Init bit in the CAN control register or by hardware reset. After using hardware reset, cancel the reset and then initialize the message RAM by the CPU or set MsgVal of the message RAM to "0". ■ Functions of the Message Object The ID28 to ID0, Xtd, and Dir bits are used to specify the ID and message type when a message is sent. When a message is received, they are used by the acceptance filter together with the Msk28 to Msk0, MXtd, and MDir bits. The data frame or remote frame which passed the acceptance filter is stored in the message object. The value of Xtd expresses that the frame is an expansion frame or a standard frame. When Xtd is "1", 29-bit ID (expansion frame) is received. When Xtd is "0", 11-bit ID (standard frame) is received. If the received data frame or remote frame matches with one or more message objects, it is stored in the matching message object which has the smallest message No. For details, refer to "Acceptance filter for reception messages" in "16.5.3 Message Reception Operation". 484 CHAPTER 16 CAN CONTROLLER MsgVal: Message validation bit Table 16.4-43 Message Validation Bit MsgVal Function 0 The message object is invalid. The message cannot be transmitted or received. 1 The message object is valid. The message can be transmitted or received. • During the initialization process before the Init bit in the CAN control register is reset to "0", reset the MsgVal bits in all unused message objects from the CPU. • Be sure to reset the MsgVal bit to "0" before changing the values of ID28 to ID0, Xtd, Dir, and DLC3 to DLC0, or when the message object is not required. • When the MsgVal bit is cleared to "0" during transmission, the TxOk bit in the CAN status register is set to "1" at the completion of the transmission. However, the TxRqst bits in the message object and the CAN transmission request register are not cleared to "0". In such a case, use the message interface register to clear the TxRqst bits to "0". UMask: Acceptance mask enable bit Table 16.4-44 Acceptance Mask Enable Bit UMask Function 0 Do not use Msk28 to Msk0, MXtd, and MDir. 1 Use Msk28 to Msk0, MXtd, and MDir. • Change the UMask bit when the Init bit in the CAN control register is "1", or when the MsgVal bit is "0". • When the Dir bit is "1" and the RmtEn bit is "0", the operation varies depending on the UMask setting. • When UMask is set to "1", TxRqst bit is reset to "0" after a remote frame which passed the acceptance filter is received. The received ID, IDE, RTR, and DLC are stored in the message object, the NewDat bit is set to "1", and the data is not changed (The remote frame is treated as if it is a data frame). • When UMask is "0", the value of the TxRqst bit is retained even when a remote frame is received. The remote frame is ignored. ID28 to ID0: Message ID Table 16.4-45 Message ID ID28 to ID0 Function ID28 to ID0 Specifies 29-bit ID (expansion frame). ID28 to ID18 Specifies 11-bit ID (standard frame). 485 CHAPTER 16 CAN CONTROLLER Msk28 to Msk0: ID mask Table 16.4-46 ID Mask Msk Function 0 Mask the bit which corresponds to the ID of the message object. 1 Do not mask the bit which corresponds to the ID of the message object. When 11-bit ID (standard frame) is specified to the message object, the ID of the received data frame is written to ID28 to ID18. Msk 28 to Msk 18 are used for the ID mask. Xtd: Expansion ID enable bit Table 16.4-47 Expansion ID Enable Bit Xtd Function 0 The message object is 11-bit ID (standard frame). 1 The message object is 29-bit ID (expansion frame). MXtd: Expansion ID mask bit Table 16.4-48 Expansion ID Mask Bit MXtd Function 0 Mask the expansion ID bit (IDE) by the acceptance filter. 1 Do not mask the expansion ID bit (IDE) by the acceptance filter. Dir: Message direction bit Table 16.4-49 Message Direction Bit Dir 486 Function 0 Indicates the direction of the reception. When TxRqst is set to "1", a remote frame is transmitted. When TxRqst is set to "0", the data frame which passed the acceptance filter is received. 1 Indicates the direction of the transmission. When TxRqst is set to "1", a data frame is transmitted. When TxRqst is set to "0" and RmtEn is set to "1", the remote frame which passed the acceptance filter is received, and TxRqst is set to "1" by the CAN controller itself. CHAPTER 16 CAN CONTROLLER MDir: Message direction mask bit Table 16.4-50 Message Direction Mask Bit MDir Function 0 Mask the message direction bit (Dir) by the acceptance filter. 1 Do not mask the message direction bit (Dir) by the acceptance filter. Note: Set the MDir bit to "1" at all times. EoB: End of buffer bit (For details, refer to "16.5.4 FIFO Buffer Function".) Table 16.4-51 End of Buffer Bit EoB Function 0 The message object is used as an FIFO buffer, and it is not the final message. 1 The message object is single or the final message object in an FIFO buffer. The EoB bit is used to configure an FIFO buffer of 2 to 32 messages. To use a single message object (do not use FIFO), be sure to set the EoB bit to "1". NewDat: Data update bit Table 16.4-52 Data Update Bit NewDat Function 0 No valid data exists. 1 Valid data exists. MsgLst: Message lost Table 16.4-53 Message Lost MsgLst Function 0 Message was not lost. 1 Message was lost. The MsgLst bit is enabled only when the Dir bit is set to "0" (reception). 487 CHAPTER 16 CAN CONTROLLER RxIE: Reception interrupt flag enable bit Table 16.4-54 Reception Interrupt Flag Enable Bit RxIE Function 0 Do not change the value of IntPnd after a successful frame reception. 1 Set IntPnd to "1" after a successful frame reception. TxIE: Transmission interrupt flag enable bit Table 16.4-55 Transmission Interrupt Flag Enable Bit TxIE Function 0 Do not change the value of IntPnd after a successful frame transmission. 1 Set IntPnd to "1" after a successful frame transmission. IntPnd: Interrupt pending bit Table 16.4-56 Interrupt Pending Bit IntPnd Function 0 No interrupt factor exists. 1 Interrupt factor exists. If there is no other interrupts which have higher priority, the IntId bit in the CAN interrupt register points to this message object. RmtEn: Remote enable Table 16.4-57 Remote Enable RmtEn Function 0 The value of TxRqst is not changed when a remote frame is received. 1 TxRqst is set to "1" when the Dir bit is "1" and a remote frame is received. When the Dir bit is "1" and the RmtEn bit is "0", the operation varies depending on the UMask setting. • When UMask is set to "1", TxRqst bit is reset to "0" after a remote frame which passed the acceptance filter is received. The received ID, IDE, RTR, and DLC are stored in the message object, the NewDat bit is set to "1", and the data is not changed. (The remote frame is treated as if it is a data frame.) • When UMask is "0", the value of the TxRqst bit is retained even when a remote frame is received. The remote frame is ignored. 488 CHAPTER 16 CAN CONTROLLER TxRqst: Transmission request bit Table 16.4-58 Transmission Request Bit TxRqst Function 0 Transmission idle status (neither during transmission nor in the transmission standby status). 1 During transmission or in the transmission standby status. DLC3 to DLC0: Data length code Table 16.4-59 Data Length Code DLC3 to DLC0 Function 0 to 8 The data frame length is 0 to 8 bytes. 9 to 15 Setting disabled. Setting these values is assumed to be 8-byte length. When a data frame is received, the DLC bit stores the received DLC. Data0 to Data7: Data0 to Data7 Table 16.4-60 Data0 to Data7 Data0 to Data7 Function Data 0 The 1st data byte of a CAN data frame Data 1 The 2nd data byte of a CAN data frame Data 2 The 3rd data byte of a CAN data frame Data 3 The 4th data byte of a CAN data frame Data 4 The 5th data byte of a CAN data frame Data 5 The 6th data byte of a CAN data frame Data 6 The 7th data byte of a CAN data frame Data 7 The 8th data byte of a CAN data frame • The serial output to the CAN bus is output from MSB (bit7 or bit15). • If the reception message data is less than 8 bytes, the data stored in the remaining byte(s) in the data register will be indeterminate. • The data transfer to the message object is processed in the unit of 4 bytes of Data A or Data B. Consequently, it is impossible to update only the part of data in the 4 bytes. 489 CHAPTER 16 CAN CONTROLLER 16.4.4 Message Handler Register All message handler registers are read only. The TxRqst, NewDat, IntPnd, MsgVal, and IntId bits in the message object show the status of the object. ■ Message Handler Register • CAN transmission request registers 1, 2 (TREQR1, TREQR2) • CAN data update registers 1, 2 (NEWDT1, NEWDT2) • CAN interrupt pending registers 1, 2 (INTPND1, INTPND2) • CAN message validation registers 1, 2 (MSGVAL1, MSGVAL2) 490 CHAPTER 16 CAN CONTROLLER 16.4.4.1 CAN Transmission Request Register (TREQR1, TREQR2) The CAN transmission request register (TREQR1, TREQR2) shows the status of the TxRqst bit in every message object. By reading the TxRqst bit, you can check which message object has a pending transmission request. ■ Register Configuration Figure 16.4-14 Bit Configuration of CAN Transmission Request Register (TREQR1, TREQR2) CAN transmission request register 2 (High-order byte) bit Address: Base+80H Read/Write → Initial value → 15 14 13 12 11 10 (R) (0) (R) (0) TxRqst32 to TxRqst25 (R) (R) (R) (R) (0) (0) (0) (0) 9 8 (R) (0) (R) (0) 1 0 (R) (0) (R) (0) 9 8 (R) (0) (R) (0) 1 0 (R) (0) (R) (0) CAN transmission request register 2 (Low-order byte) bit Address: Base+81H Read/Write → Initial value → 7 6 (R) (0) (R) (0) 5 4 3 2 TxRqst24 to TxRqst17 (R) (R) (R) (R) (0) (0) (0) (0) CAN transmission request register 1 (High-order byte) bit Address: Base+82H Read/Write → Initial value → 15 14 13 (R) (0) (R) (0) (R) (0) 12 11 10 TxRqst16 to TxRqst9 (R) (R) (R) (0) (0) (0) CAN transmission request register 1 (Low-order byte) bit Address: Base+83H Read/Write → Initial value → 7 (R) (0) 6 (R) (0) 5 4 3 2 TxRqst8 to TxRqst1 (R) (R) (R) (R) (0) (0) (0) (0) 491 CHAPTER 16 CAN CONTROLLER ■ Register Functions TxRqst32 to TxRqst1: Transmission request bit Table 16.4-61 Transmission Request Bit TxRqst Function 0 Transmission idle status (neither during transmission nor in the transmission standby status). 1 During transmission or in the transmission standby status. The set/reset condition of the TxRqst bit is as follows: • Set condition - When the IFx command mask register’s WR/RD is set to "1", and its TxRqst is set to "1", the TxRqst bit in a specific object can be set by writing a message No. to the IFx command request register. - When the IFx command mask register’s WR/RD is set to "1", its TxRqst is set to "0", and the IFx message control register’s TxRqst is set to "1", the TxRqst bit in a specific object can be set by writing a message No. to the IFx command request register. - The TxRqst bit is set when the Dir bit is set to "1", the RmtEn bit to "1", and a remote frame which passed the acceptance filter is received. • Reset condition - When the IFx command mask register’s WR/RD is set to "1", its TxRqst is set to "0", and the IFx message control register’s TxRqst is set to "0", the TxRqst bit in a specific object can be reset by writing a message No. to the IFx command request register. - The TxRqst bit is reset when the frame transmission finishes successfully. - When Dir is set to "1", RmtEn is set to "0", and UMask is set to "1", the TxRqst bit is reset by the reception of a remote frame which passed the acceptance filter. MB91F467R ch.1 has the following registers. Table 16.4-62 Ch.1 Transmission Request Bits (only MB91F467R) 492 Register name Configuration bit addr + 0 addr + 1 addr + 2 addr + 3 TREQR4, TREQR3 TxRqst64 to TxRqst33 (address 84H) TxRqst64 to TxRqst57 TxRqst56 to TxRqst49 TxRqst48 to TxRqst41 TxRqst40 to TxRqst33 CHAPTER 16 CAN CONTROLLER 16.4.4.2 CAN Data Update Register (NEWDT1, NEWDT2) The CAN data update register (NEWDT1, NEWDT2) shows the status of the NewDat bit in every message object. By reading the NewDat bit, you can check which message object has an updated data. ■ Register Configuration Figure 16.4-15 Bit Configuration of CAN Data Update Register (NEWDT1, NEWDT2) CAN data update register 2 (High-order byte) bit Address: Base+90H Read/Write → Initial value → 15 14 13 12 11 10 (R) (0) (R) (0) NewDat32 to NewDat25 (R) (R) (R) (R) (0) (0) (0) (0) 9 8 (R) (0) (R) (0) 1 0 (R) (0) (R) (0) 9 8 (R) (0) (R) (0) 1 0 (R) (0) (R) (0) CAN data update register 2 (Low-order byte) bit Address: Base+91H Read/Write → Initial value → 7 6 (R) (0) (R) (0) 5 4 3 2 NewDat24 to NewDat17 (R) (R) (R) (R) (0) (0) (0) (0) CAN data update register 1 (High-order byte) bit Address: Base+92H Read/Write → Initial value → 15 14 13 12 11 10 (R) (0) (R) (0) NewDat16 to NewDat9 (R) (R) (R) (R) (0) (0) (0) (0) CAN data update register 1 (Low-order byte) bit Address: Base+93H Read/Write → Initial value → 7 6 5 (R) (0) (R) (0) (R) (0) 4 3 2 NewDat8 to NewDat1 (R) (R) (R) (0) (0) (0) 493 CHAPTER 16 CAN CONTROLLER ■ Register Functions NewDat32 to NewDat1: Data update bit Table 16.4-63 Data Update Bit NewDat32 to NewDat1 Function 0 No valid data exists. 1 Valid data exists. The set/reset condition of the NewDat bit is as follows: • Set condition - When the IFx command mask register’s WR/RD is set to "1", and the IFx message control register’s NewDat is set to "1", the NewDat bit in a specific object can be set by writing a message No. to the IFx command request register. - The NewDat bit is set when a data frame which passed the acceptance filter is received. - When Dir is set to "1", RmtEn is set to "0", and UMask is set to "1", the NewDat bit is set by the reception of a remote frame which passed the acceptance filter. • Reset condition - When the IFx command mask register’s WR/RD is set to "0", and its NewDat is set to "1", the NewDat bit in a specific object can be reset and by writing a message No. to the IFx command request register. - When the IFx command mask register’s WR/RD to "1", and the IFx message control register’s NewDat is set to "0", the NewDat bit in a specific object can be reset by writing a message No. to the IFx command request register. - The NewDat bit is reset after data has been transferred to the transmitting shift register (internal register). MB91F467R ch.1 has the following registers. Table 16.4-64 Ch.1 Data Update Bits (only MB91F467R) 494 Register name Configuration bit addr + 0 addr + 1 addr + 2 addr + 3 NEWDT4, NEWDT3 NewDat64 to NewDat33 (address 94H) NewDat64 to NewDat57 NewDat56 to NewDat49 NewDat48 to NewDat41 NewDat40 to NewDat33 CHAPTER 16 CAN CONTROLLER 16.4.4.3 CAN Interrupt Pending Register (INTPND1, INTPND2) The CAN interrupt pending register (INTPND1, INTPND2) shows the status of the IntPnd bit in every message object. By reading the IntPnd bit, you can check which message object has a pending interrupt. ■ Register Configuration Figure 16.4-16 Bit Configuration of CAN Interrupt Pending Register (INTPND1, INTPND2) CAN interrupt pending register 2 (High-order byte) bit Address: Base+A0H Read/Write → Initial value → 15 14 13 (R) (0) (R) (0) (R) (0) 12 11 10 IntPnd32 to IntPnd25 (R) (R) (R) (0) (0) (0) 9 8 (R) (0) (R) (0) 1 0 (R) (0) (R) (0) 9 8 (R) (0) (R) (0) 1 0 (R) (0) (R) (0) CAN interrupt pending register 2 (Low-order byte) bit Address: Base+A1H Read/Write → Initial value → 7 6 5 (R) (0) (R) (0) (R) (0) 4 3 2 IntPnd24 to IntPnd17 (R) (R) (R) (0) (0) (0) CAN interrupt pending register 1 (High-order byte) bit Address: Base+A2H Read/Write → Initial value → 15 14 13 (R) (0) (R) (0) (R) (0) 12 11 10 IntPnd16 to IntPnd9 (R) (R) (R) (0) (0) (0) CAN interrupt pending register 1 (Low-order byte) bit Address: Base+A3H Read/Write → Initial value → 7 6 5 (R) (0) (R) (0) (R) (0) 4 3 2 IntPnd8 to IntPnd1 (R) (R) (R) (0) (0) (0) 495 CHAPTER 16 CAN CONTROLLER ■ Register Functions IntPnd32 to IntPnd1: Interrupt pending bit Table 16.4-65 Interrupt Pending Bit IntPnd32 to IntPnd1 Function 0 No interrupt factor exists. 1 Interrupt factor exists. The set/reset condition of the IntPnd bit is as follows: • Set condition - When TxIE is set to "1", this bit is set by the successful completion of frame transmission. - When RxIE is set to "1", this bit is set by the successful completion of the reception of a frame which passed the acceptance filter. • Reset condition - When the IFx command mask register’s WR/RD is set to "1", and its IntPnd is set to "1", the IntPnd bit in a specific object can be reset by writing a message No. to the IFx command request register. Channel 1 on MB91F467R has the following registers. Table 16.4-66 Ch.1 Interrupt Pending Bits (only MB91F467R) 496 Register name Configuration bit addr + 0 addr + 1 addr + 2 addr + 3 INTPND4, INTPND3 IntPnd64 to IntPnd33 (address A4H) IntPnd64 to IntPnd57 IntPnd56 to IntPnd49 IntPnd48 to IntPnd41 IntPnd40 to IntPnd33 CHAPTER 16 CAN CONTROLLER 16.4.4.4 CAN Message Validation Register (MSGVAL1, MSGVAL2) The CAN message validation register (MSGVAL1, MSGVAL2) shows the status of the MsgVal bit in every message object. By reading the MsgVal bit, you can check which message object is valid. ■ Register Configuration Figure 16.4-17 Bit Configuration of CAN Message Validation Register (MSGVAL1, MSGVAL2) CAN message validation register 2 (High-order byte) bit Address: Base+B0H Read/Write → Initial value → 15 14 13 12 11 10 (R) (0) (R) (0) MsgVal32 to MsgVal25 (R) (R) (R) (R) (0) (0) (0) (0) 9 8 (R) (0) (R) (0) 1 0 (R) (0) (R) (0) 9 8 (R) (0) (R) (0) 1 0 (R) (0) (R) (0) CAN message validation register 2 (Low-order byte) bit Address: Base+B1H Read/Write → Initial value → 7 6 (R) (0) (R) (0) 5 4 3 2 MsgVal24 to MsgVal17 (R) (R) (R) (R) (0) (0) (0) (0) CAN message validation register 1 (High-order byte) bit Address: Base+B2H Read/Write → Initial value → 15 14 13 (R) (0) (R) (0) (R) (0) 12 11 10 MsgVal16 to MsgVal9 (R) (R) (R) (0) (0) (0) CAN message validation register 1 (Low-order byte) bit Address: Base+B3H Read/Write → Initial value → 7 (R) (0) 6 (R) (0) 5 4 3 2 MsgVal8 to MsgVal1 (R) (R) (R) (R) (0) (0) (0) (0) 497 CHAPTER 16 CAN CONTROLLER ■ Register Functions MsgVal32 to MsgVal1: Message validation bit Table 16.4-67 Message Validation Bit MsgVal32 to MsgVal1 Function 0 The message object is invalid. The message cannot be transmitted or received. 1 The message object is valid. The message can be transmitted or received. The set/reset condition of the MsgVal bit is as follows: • Set condition The MsgVal bit in a specific object can be set by setting IFx arbitration register 2’s MsgVal to "1" and writing a message No. to the IFx command request register. • Reset condition The MsgVal bit in a specific object can be reset by setting IFx arbitration register 2’s MsgVal to "0" and writing a message No. to the IFx command request register. Channel 1 on MB91F467R has the following registers. Table 16.4-68 Ch.1 Message Validation Bits (only MB91F467R) 498 Register name Configuration bit addr + 0 addr + 1 addr + 2 addr + 3 MSGVAL4, MSGVAL3 MsgVal64 to MsgVal33 (address A4H) MsgVal64 to MsgVal57 MsgVal56 to MsgVal49 MsgVal48 to MsgVal41 MsgVal40 to MsgVal33 CHAPTER 16 CAN CONTROLLER 16.4.5 CAN Prescaler Register (CANPRE) The CAN prescaler register (CANPRE) selects the clock source for the CAN prescaler and defines the division ratio of the CAN clock provided to the CAN interface. Before changing the value of this register, set the initialization bit (Init) of the CAN control register (CTRLR) to "1" and stop the operation of all buses. ■ Register Configuration Figure 16.4-18 Bit Configuration of CAN Prescaler Register (CANPRE) CAN prescaler register bit Address: ch.0 00C000H ch.1 00C100H Read/Write → Initial value → 15 14 13 12 Reserved Reserved CPCKS1 CPCKS0 (R) (0) (R) (0) (R/W) (0) (R/W) (0) 11 10 9 8 DVC3 DVC2 DVC1 DVC0 (R/W) (0) (R/W) (0) (R/W) (0) (R/W) (0) ■ Register Functions [bit15, bit14] Reserved: Reserved bits "00B" is read from these bits. Writing to these bits is not reflected to the register. [bit13, bit12] CPCKS1, CPCKS0: CAN prescaler clock source selection bit Table 16.4-69 CAN Prescaler Clock Source Selection Bit CPCKS[1:0] CAN prescaler clock source 00B CPU clock (80 MHz max.) [Initial value] 01B PLL output (200 MHz max.) 10B Setting disabled. 11B Source oscillation clock (20 MHz max.) 499 CHAPTER 16 CAN CONTROLLER [bit11 to bit8] DVC3 to DVC0: CAN clock setting bit Table 16.4-70 CAN Clock Setting Bit DVC3 to DVC0 CAN clock 0000B Select a 1/1 cycle of the prescaler clock source. [Initial value] 0001B Select a 1/2 cycle of the prescaler clock source. 0010B Select a 1/3 cycle of the prescaler clock source. : : 1110B Select a 1/15 cycle of the prescaler clock source. 1111B Select a 1/16 cycle of the prescaler clock source. • Before changing the value of the CAN prescaler setting bit, set the initialization bit in the CAN control register to "1" and stop the operation of all buses. • Set the frequency of the CAN clock which is provided to the CAN interface by setting this register to 20 MHz or less. 500 CHAPTER 16 CAN CONTROLLER 16.5 CAN Controller Functions This section describes the operations and functions of the CAN controller. The following functions are explained: • Message Object • Message Transmission Operation • Message Reception Operation • FIFO Buffer Function • Interrupt Function • Bit Timing • Test Mode • Software Initialization • CAN Clock Prescaler 501 CHAPTER 16 CAN CONTROLLER 16.5.1 Message Object This section describes the message objects in the message RAM and the interfaces being used. ■ Message Object The message object settings in the message RAM (except for the MsgVal, NewDat, IntPnd, and TxRqst bits) are not initialized by hardware reset. Therefore, you need to initialize the message objects from the CPU, or to disable the MsgVal bit (MsgVal=0). The CAN bit timing register must be set while the Init bit in the CAN control register is "0". To set a message object, configure appropriate message interface registers (IFx mask register, IFx arbitration register, the IFx message control register, and IFx data register), and write a message No. to the IFx command request register. The data of the interface register is transferred to the specified message object. When the Init bit in the CAN control register is cleared to "0", the CAN controller starts operation. The reception message which passed the acceptance filter is stored in the message RAM. The message for which a transmission request is pending is transferred from the message RAM to the shift register of the CAN controller, and then sent to the CAN bus. The CPU reads reception messages and updates transmission messages via the message interface registers. The interrupt to the CPU occurs based on the settings of the CAN control register and IFx message control register (message objects). ■ Data Transmission/Reception to/from the Message RAM When the data transfer between the message interface register and message RAM starts, the BUSY bit in the IFx command request register is set to "1". When the data transfer is complete, the BUSY bit is cleared to "0". (Refer to Figure 16.5-1.) The IFx command mask register sets either of all-data transfer or partial-data transfer of a message object. Due to the structure of the message RAM, it is impossible to write a single bit/byte of a message object. All data of a message object is always written to the message RAM. Consequently, the data transfer from the message interface register to the message RAM requires a execution cycle of read-modify-write (RMW) instruction. 502 CHAPTER 16 CAN CONTROLLER Figure 16.5-1 Data Transfer Between Message Interface Register and Message RAM Start Write to IFx command request register. NO YES BUSY = 1 Interrupt = 0 NO YES WR/RD = 1 Read from message RAM to message interface register. Read from message RAM to message interface register. Write from message interface register to message RAM. BUSY = 0 Interrupt = 1 503 CHAPTER 16 CAN CONTROLLER 16.5.2 Message Transmission Operation This section describes the settings and transmission operations for the transmission message objects. ■ Message Transmission When no data transfer is detected between the message interface register and message RAM, the MsgVal bit in the CAN message validation register and the TxRqst bit in the CAN transmission request register are evaluated. Then, a valid message object which has a pending transmission request and the highest priority is transmitted to the transmission shift register. At this point, the NewDat bit in the message object is reset to "0". When the transmission is complete successfully and the message object has no new data (NewDat=0), the TxRqst bit is reset to "0". If TxIE is set to "1", the IntPnd bit is set to "1" after successful transmission. If the CAN controller loses arbitration on the CAN bus, or if an error occurs during transmission, the message is re-transmitted immediately after the CAN bus becomes idle. ■ Transmission Priority The transmission priority of the message objects are determined by the message numbers. Message object 1 has the highest priority, and message object 32 (or the maximum message object No. implemented) has the lowest priority. Consequently, when two or more transmission requests are pending, the message object with smaller message No. is transmitted. ■ Transmission Message Object Setting Figure 16.5-2 shows the initialization of transmission message object. Figure 16.5-2 Initialization of Transmission Message Object MsgVal Arb Data Mask EoB Dir 1 appl. appl. appl. 1 1 NewDat MsgLst 0 0 RxIE TxIE IntPnd 0 appl. 0 RmtEn TxRqst appl. 0 The IFx arbitration register (ID28 to ID0 and Xtd bits) is provided by the application and defines the ID and message type of the transmission message. When a standard frame (11-bit ID) is set, ID28 through ID18 are used, and ID17 through ID0 are invalid. When an expansion frame (29-bit ID) is set, ID28 through ID0 are used. When the TxIE bit is set to "1", the IntPnd bit is set to "1" after the message object is transmitted successfully. When the RmtEn bit is set to "1", the TxRqst bit is set to "1" after the corresponding remote frame is received, and the data frame is transmitted automatically. The settings of the data registers (DLC3 to DLC0, Data0 to Data7) are provided by the application. When UMask= 1, the IFx mask registers (Msk28 to Msk0, UMask, MXtd, and MDir bits) receive remote frames having IDs grouped by the mask setting. Then, the registers are used to enable transmission (Set the TxRqst bit to "1".). For details, refer to "Remote frame" in "16.5.3 Message Reception Operation". 504 CHAPTER 16 CAN CONTROLLER Note: It is prohibited to set the Dir bit in the IFx mask register to enable mask. ■ Updating a Transmission Message Object The CPU can update the data of transmission message objects via the message interface register. The data of the transmission message object is written in the unit of 4 bytes of the corresponding IFx data register (IFx data register A or IFx data register B). Therefore, you cannot change only one byte of the transmission message object. To update only 8 bytes of data, first write "0087H" to the IFx command mask register. By writing a message No. to the IFx command request register, the data of the transmission message object (8-byte data) is updated and "1" is written to the TxRqst bit at the same time. To transmit the data immediately following the message No. currently transmitted, set the TxRqst and NewDat bits to "1". By this, the TxRqst bit is not reset to "0" and data can be transmitted continuously. When both NewDat bit and TxRqst bit are set to "1", the NewDat bit is reset to "0" after transmission starts. • To update data, write the data in the unit of 4 bytes of IFx data register A or IFx data register B. • To update data only, set the NewDat and TxRqst bits to "1". 505 CHAPTER 16 CAN CONTROLLER 16.5.3 Message Reception Operation This section describes the settings and reception operations for the reception message objects. ■ Acceptance Filter for Reception Messages When the arbitration/control fields of the message (ID + IDE + RTR + DLC) are completely shifted to the CAN controller reception shift register, the scan of the message RAM starts for the comparison with valid message objects to find a match. During the scan, the arbitration field and mask data (including MsgVal, UMask, NewDat, and EoB) are loaded from the message object in the message RAM, and the arbitration fields of the message object and shift register are compared including the mask data. This operation is repeated until the match of the arbitration fields of the message object and shift register is detected, or until the operation reaches the last word of the message RAM. When the match is detected, the scan of the message RAM stops, and the CAN controller starts processing according to the type of the reception frame (data frame or remote frame). ■ Reception Priority The reception priority of the message objects are determined by the message numbers. Message object 1 has the highest priority, and message object 32 (or the maximum message object No. implemented) has the lowest priority. Consequently, when two or more message objects are found to be a match by the acceptance filter, the message object with a smaller message No. is received. ■ Data Frame Reception The CAN controller transfers and stores the reception message from the shift register to the message RAM of the message object which was found to be a match by the acceptance filter. The data to be stored is not only data bytes, but also all the arbitration fields and data length codes. The same is true even when the IFx mask register is set for masking (in order to retain the ID and data bytes). When new data is received, the NewDat bit is set to "1". When the CPU reads a message object, reset the NewDat bit to "0". If the NewDat bit is already set to "1" when a message is received, the preceding data is assumed to be lost, and the MsgLst bit is set to "1". When the RxIE bit is set to "1" and a message buffer is received, the IntPnd bit in the CAN interrupt pending register is set to "1". At this point, the TxRqst bit in the corresponding message object is reset to "0", in order to disable transmission when a request data frame is received during the transmission of a remote frame. 506 CHAPTER 16 CAN CONTROLLER ■ Remote Frame The following three types of processing are available when a remote frame is received: The processing during the remote frame reception is selected based on the settings of the matching message object. • Dir=1 (transmission direction), RmtEn=1, UMask=1 or 0 The matching remote frame is received, only the TxRqst bit in this message object is set to "1", and the data frame for the remote frame is automatically returned (transmitted). (The bits other than the TxRqst bit in the message object are not changed.) • Dir=1 (transmission direction), RmtEn=0, UMask=0 The reception is disabled even if the received remote frame matches with the message object. The remote frame becomes invalid. (The TxRqst bit in this message object is not changed.) • Dir=1 (transmission direction), RmtEn=0, UMask=1 When the received remote frame matches with the message object, the TxRqst bit in the message object is reset to "0", and the remote frame is processed as a received data frame. The received arbitration field and control field (ID + IDE + RTR + DLC) are stored in the message object in the message RAM. The NewDat bit in the message object is set to "1". The data field of the message object is not changed. 507 CHAPTER 16 CAN CONTROLLER ■ Reception Message Object Setting Figure 16.5-3 shows the initialization of reception message object. Figure 16.5-3 Initialization of Reception Message Object MsgVal Arb Data Mask EoB Dir 1 appl. appl. appl. 1 0 NewDat MsgLst 0 0 RxIE TxIE IntPnd appl. 0 0 RmtEn TxRqst 0 0 The IFx arbitration register (ID28 to ID0, Xtd bit) is provided by the application. It defines the ID and message type of the reception message used for the acceptance filter. When a standard frame (11-bit ID) is set, ID28 through ID18 are used, and ID17 through ID0 are invalid. When a standard frame is received, ID17 through ID0 are reset to "0". When an expansion frame (29-bit ID) is set, ID28 through ID0 are used. When the RxIE bit is set to "1" and a reception data frame is stored in the message object, the IntPnd bit is set to "1". The data length code (DLC3 to DLC0) is provided by the application. When the CAN controller stores a reception data frame into the message object, it stores the reception data length code and the 8-byte data. If the data length code is less than 8, indeterminate data is written as the rest of the message object data. When UMask=1, the IFx mask register (Msk28 to Msk0, UMask, MXtd, and MDir bits) is used to enable the reception of data frames having IDs grouped by the mask setting. For details, refer to "Data frame reception" in "16.5.3 Message Reception Operation". Note: It is prohibited to set the Dir bit in the IFx mask register for masking. 508 CHAPTER 16 CAN CONTROLLER ■ Reception Message Processing The CPU can read reception messages any time via the message interface register. In normal times, "007FH" is written to the IFx command mask register. Then the message No. of the message object is written to the IFx command request register. By this, the reception message of the specified message No. is transferred from the message RAM to the message interface register. During this process, the NewDat and IntPnd bits in the message object can be cleared to "0" by setting the IFx command mask register. As for the processing of the reception message, the message is received when it is found to be a match by the acceptance filter. If the message object uses the masking by the acceptance filter, the data to be masked is removed from the acceptance filter, and whether or not to receive the message is judged. The NewDat bit indicates whether a new message was received after the last message object was read. The MsgLst bit indicates that the preceding data was lost because the next reception data is received before the preceding reception data was read from the message object. The MsgLst bit is not reset automatically. When a matching data frame is received by the acceptance filter while the remote frame is being transmitted, the TxRqst bit is automatically reset to "0". 509 CHAPTER 16 CAN CONTROLLER 16.5.4 FIFO Buffer Function This section describes the configuration of the message objects in the FIFO buffer and the FIFO buffer operations used for the reception message processing. ■ Configuration of the FIFO Buffer The configuration of the reception message object in the FIFO buffer is the same as the configuration of the normal reception message object except for the EoB bit (For details, refer to "Setting a reception message object" in "16.5.3 Message Reception Operation"). The FIFO buffer uses two or more reception message objects by concatenating them. To store a reception message into such FIFO buffer using the ID and masking of the reception message object, the ID and mask settings of the message objects must be the same. The first reception message object in the FIFO buffer is the object with the smaller message No. which has the highest priority. It is necessary to set the EoB bit in the last reception message object in the FIFO buffer to "1" to indicate the end of the FIFO buffer block (As for the message objects other than the last message object using the FIFO buffer configuration, set their EoB bits to "0"). • Be sure to use the same ID and mask settings for the message objects used in the FIFO buffer. • When the FIFO buffer is not used, be sure to set the EoB bit of the message object to "1". ■ Message Reception by the FIFO Buffer When the reception message matches with the ID of the FIFO buffer, it is stored in the reception message object having the smallest message No. in the FIFO buffer. When a message is stored in the reception message object in the FIFO buffer, the NewDat bit in the reception message object is set to "1". When the EoB bit of the reception message object is "0" and its NewDat bit is set to "1", the reception message object is protected and the CAN controller cannot write to the FIFO buffer until the operation reaches the last reception message object (EoB bit=1). Unless "0" is written to the NewDat bit in the reception message object (canceling write protection) with valid data being stored until the last FIFO buffer, the message received next is written to the last message object, and the previous message is overwritten. 510 CHAPTER 16 CAN CONTROLLER ■ Reading from the FIFO Buffer To use the CPU to read the content of the reception message object, write the reception message No. to the IFx command request register. Then, the data is transferred to the message interface register, and can be read by the CPU. To do this, set the IFx command mask register’s WR/RD to "0" (read), TxRqst/ NewDat=1, IntPnd=1, and reset the NewDat and IntPnd bits to "0". To ensure the function of the FIFO buffer, the reception message object having the smallest message No. in the FIFO buffer must be read first. Figure 16.5-4 shows how the CPU processes the message objects concatenated by the FIFO buffer. Figure 16.5-4 Processing of FIFO Buffer by CPU Start Message interrupt Read CAN interrupt register. 8000H 0000H Value of CAN interrupt register Other than 8000H and 0000H Execute status interrupt. Message No. = Value of CAN interrupt register End (Normal processing) Write (Message No.) to IFx command request register. Read message interface register (Reset: NewDat=0, IntPnd=0) Read IFx message control register. No NewDat = 1 Yes Read IFx message data register A, B. Yes EoB = 1 No Message No. = Message No. 1 511 CHAPTER 16 CAN CONTROLLER 16.5.5 Interrupt Function This section describes interrupt processing using the status interrupt (IntId=8000H) and message interrupt (IntId message No.). When two or more interrupts are pending, the CAN interrupt register shows the interrupt code of the highest priority among the pending codes. The time order specified to the interrupt codes is ignored, and the interrupt code of the highest priority is always shown. The interrupt code is retained until it is cleared by the CPU. The status interrupt (IntId bit=8000H) has the highest priority. The priority of the message interrupt is set higher for the message with a smaller message No., and is set lower for the message with a larger message No. The message interrupt is cleared by clearing the IntPnd bit in the message object. The status interrupt is cleared by reading the CAN status register. The IntPnd bit in the CAN interrupt pending register indicates whether an interrupt is pending or not. If there is no pending interrupt, the IntPnd is "0". When the IntPnd bit is set to "1" while the IE bit in the CAN control register and the TxIE and RxIE bits in the IFx message control register are "1", an interrupt signal to the CPU becomes active. The interrupt signal is retained to be active until the CAN interrupt pending register is cleared to "0" (interrupt factor reset), or until the IE bit in the CAN control register is reset to "0". When the CAN interrupt register is "8000H", it indicates that the CAN status register is updated by the CAN controller. This interrupt has the highest priority. The interrupt by updating the CAN status register can be used to enable or disable the setting of the CAN interrupt register with the EIE and SIE bits in the CAN control register. The interrupt signal to the CPU can be controlled with the IE bit in the CAN control register. The RxOk, TxOk, and LEC bits in the CAN status register can be updated (reset) by writing data from the CPU. This writing, however, cannot set or reset interrupt. When the CAN interrupt register is set to the value other than "8000H" and "0000H", it indicates that the message interrupt is pending, and the pending message interrupt of the highest priority is shown. The CAN interrupt register is updated even when the IE bit is reset. The factor of the message interrupt to the CPU can be checked with the CAN interrupt register or CAN interrupt pending register. (Refer to "16.4.4 Message Handler Register".) It is possible to clear a message interrupt and read the message data simultaneously. When the message interrupt indicated by the CAN interrupt register is cleared, the interrupt of the second highest priority is set to the CAN interrupt register and waits for the next interrupt processing. When no interrupt exists, the CAN interrupt register indicates" 0000H". 512 CHAPTER 16 CAN CONTROLLER • The status interrupt (IntId=8000H) is cleared by the read access of the CAN status register. • The status interrupt (IntId=8000H) is not triggered by the write access to the CAN status register. 513 CHAPTER 16 CAN CONTROLLER 16.5.6 Bit Timing This section describes the overview of bit timing and the bit timing operations in the CAN controller. Each CAN node in the CAN network has its own clock oscillator (generally, a quartz oscillator). The time parameters of the bit time can be configured individually for the CAN nodes. Even when the oscillation cycles (fosc) of the CAN nodes vary, a common bit rate can be created. The frequencies of these oscillators vary a little depending on the change in temperature or voltage, or the deterioration of components. As long as the variations remain within the allowable range of the oscillator (df), the CAN node can compensate different bit rate by re-synchronizing it with the bit stream. The bit time is divided into four segments in accordance with the CAN specification (Refer to Figure 16.55.). It consists of a synchronization segment (Sync_Seg), a propagation time segment (Prop_Seg), phase buffer segment 1 (Phase_Seg1), and phase buffer segment 2 (Phase_Seg2). Each segment consists of programmable time quantities (Refer to Table 16.5-1.). The basic unit time quantity (tq) of the bit time is defined with the CAN clock (fsys) and baud rate prescaler (BRP) as follows: tq = BRP / fsys The CAN clock (fsys) is a clock generated by the CAN prescaler. The synchronization segment (Sync_Seg) expresses the timing within the bit time where the edge of the CAN bus is expected. The propagation time segment (Prop_Seg) compensates the physical delay time in the CAN network. The phase buffer segments (Phase_Seg1, Phase_Seg2) designate sampling points. The re-synchronization jump width (SJW) defines the width of the sampling point movement during re-synchronization in order to compensate an edge phase error. Figure 16.5-5 Bit Timing 1 bit time (BT) Sync _Seg Prop_Seg 1 unit time (tq) 514 Phase_Seg1 Phase_Seg2 Sampling point CHAPTER 16 CAN CONTROLLER Table 16.5-1 CAN Bit Time Parameters Parameter Range Function BRP [1-32] Sync_Seg 1 tq Prop_Seg [1-8] tq Compensation for the physical delay time Phase_Seg1 [1-8] tq Compensation for the edge phase error before the sample point. It may be temporarily extended due to synchronization. Phase_Seg2 [1-8] tq Compensation for the edge phase error after the sample point. It may be temporarily shortened due to synchronization. SJW [1-4] tq Re-synchronization jump width It is not longer than either of the phase buffer segments. Definition of the length of time quantity (tq) The length is fixed. Synchronization with the system clock Figure 16.5-6 shows the bit timing in the CAN controller. Figure 16.5-6 Bit Timing in CAN Controller 1 bit time (BT) Sync _Seg TEG1 1 unit time (tq) TEG2 Sampling point 515 CHAPTER 16 CAN CONTROLLER Table 16.5-2 CAN Controller Parameters Parameter Range Function BRPE,BRP [0-1023] Definition of the length of time quantity (tq). The prescaler can be expanded up to 1024 by using the bit timing register and prescaler expansion register. Sync_Seg 1 tq TSEG1 [1-15] tq Time segment before the sampling point. It corresponds to Prop_Seg and Phase_Seg1. It can be controlled by the bit timing register. TSEG2 [0-7] tq Time segment after the sampling point. It corresponds to Phase_Seg2. It can be controlled by the bit timing register. SJW [0-3] tq Re-synchronization jump width. It can be controlled by the bit timing register. Synchronization with the CAN clock. The length is fixed. The relationships between the parameters are as follows: tq = ([BRPE,BRP] + 1) / fsys BT = SYNC_SEG + TEG1 + TEG2 = (1 + (TSEG1 + 1) + (TSEG2 + 1)) × tq = (3 + TSEG1 + TSEG2) × tq 516 CHAPTER 16 CAN CONTROLLER 16.5.7 Test Mode This section describes the setting procedure and operations of the test mode. ■ Setting the Test Mode Setting the Test bit in the CAN control register to "1" activates the test mode. In the test mode, the Tx1, Tx0, LBack, Silent, and Basic bits in the CAN test register are enabled. When the Test bit in the CAN control register is reset to "0", all test register functions are disabled. ■ Silent Mode Setting the Silent bit in the CAN test register to "1" sets the CAN controller to the silent mode. In the silent mode, data frames and remote frames can be received, but only recessives are output to the CAN bus, and messages and ACK are not transmitted. When the CAN controller is requested to send dominant bits (ACK bit, overload flag, active error flag), they are sent to the RX side by the fold-back circuit inside of the CAN controller. This operation means that the RX side receives dominant bits which are sent back from the inside of the CAN controller although the status is recessive on the CAN bus. In the silent mode, the traffic on the CAN bus can be analyzed without being affected by the transmission of dominant bits (ACK bit, error flag). Figure 16.5-7 shows the CAN controller in the silent mode. Figure 16.5-7 CAN Controller in Silent Mode CAN_TX CAN_RX CAN controller Silent bit = 1 Tx Rx CAN Core 517 CHAPTER 16 CAN CONTROLLER ■ Loop-back Mode Setting the LBack bit in the CAN test register to "1" sets the CAN controller to the loop-back mode. The loop-back mode can be used for the self-diagnosis function. In the loop-back mode, the TX and RX sides are connected inside the CAN controller. The message sent by the CAN controller is treated as a message received by the RX side, and the message which passed the acceptance filter is stored in the reception buffer. Figure 16.5-8 shows the CAN controller in the loop-back mode. Figure 16.5-8 CAN Controller in Loop-back Mode CAN_TX CAN_RX Tx Rx CAN controller CAN Core To maintain the independence from external signals, the dominant bits in the acknowledge slot of a data/ remote frame are not sampled. Consequently, the CAN controller does not generate acknowledge errors, which it normally generates, in this test mode. 518 CHAPTER 16 CAN CONTROLLER ■ Combination of the Silent Mode and Loop-back Mode. Setting both LBack and Silent bits in the CAN test register to "1" enables the combined operation of the loop-back mode and silent mode. This mode can be used for a hot self-test. In a hot self-test, the test of the CAN controller in the loop-back mode provides fixed output of recessives to the CAN_TX pin and ignores the input from the CAN_RX pin. Consequently, the test does not affect the operation of the CAN system. Figure 16.5-9 shows the CAN controller when the silent mode and the loop-back mode are combined. Figure 16.5-9 CAN Controller When Silent Mode and Loop-back Mode Are Combined CAN_TX CAN_RX CAN controller LBack bit,Silent bit = 1 Tx Rx CAN Core 519 CHAPTER 16 CAN CONTROLLER ■ Basic Mode Setting the Basic bit in the CAN test register to "1" sets the CAN controller in the basic mode. In the Basic mode, the CAN controller operates without using the message RAM. The IF1 message interface register is used to control transmission. Before starting message transmission, set the content to be transmitted in the IF1 message interface register. Then, request transmission by setting the BUSY bit in the IF1 command request register to "1". Setting the BUSY bit to "1" indicates that the IF1 message interface register is locked, or transmission is pending. When the BUSY bit is set to "1", the CAN controller operates as follows: As soon as the CAN bus becomes idle, the content of the IF1 message interface register is loaded to the transmission shift register and transmission starts. When the transmission is complete successfully, the BUSY bit is reset to "0", and the locked IF1 message interface register is unlocked. When transmission is pending, you can discontinue the transmission by resetting the BUSY bit in the IF1 command request register to "0". If the BUSY bit is reset to "0" during transmission, the re-transmission which is performed in the cases of arbitration loss or error is disabled. The IF2 message interface register is used to control reception. All messages are received without using the acceptance filter. Setting the BUSY bit in the IF2 command request register to "1" enables reading the content of the received message. When the BUSY bit is set to "1", the CAN controller operates as follows: The received message (content of the reception shift register) is stored in the IF2 message interface register without using the acceptance filter. When a new message is stored in the IF2 message interface register, the CAN controller sets the NewDat bit to "1". If another new message is received while the NewDat bit is "1", the CAN controller sets the MsgLst bit to "1". • In the basic mode, the control mode settings of all message objects and IFx command mask registers concerning the control/status bit are invalid. • The message No. of the command request register is invalid. • The NewDat and MsgLst bits in the IF2 message control register operate as normal, DLC3 to DLC0 show the received DLC, and other control bits are read as "0". 520 CHAPTER 16 CAN CONTROLLER ■ Software Control by the CAN_TX Pin CAN_TX, the CAN transmission pin, has the following four output functions: • Serial data output (normal output) • CAN sampling point signal output to monitor the bit timing of the CAN controller • Fixed output of dominants • Fixed output of recessives The fixed outputs of dominants and recessives can be used to check the physical layer of the CAN bus as well as to monitor CAN_RX of the CAN reception pin. The output mode of the CAN_TX pin can be controlled by the Tx1 and Tx0 bits in the CAN test register. To use the CAN message transmission, or the loop-back, silent, or basic mode, you need to set CAN_TX to the serial data output. 521 CHAPTER 16 CAN CONTROLLER 16.5.8 Software Initialization This section describes the details of the software initialization. The factors that cause software initialization are as follows: • Hardware reset • Setting the Init bit in the CAN control register • Transition to the bus-off status The reset by hardware initializes everything other than the message RAM (except for MsgVal, NewDat, IntPnd, and TxRqst bits). After the hardware reset, the message RAM should be initialized by the CPU, or the message RAM’s MsgVal must be set to "0". To set a bit timing register, set it before clearing the Init bit in the CAN control register to "0". The Init bit in the CAN control register is set to "1" when the following occurs: • The CPU writes "1". • Hardware reset • Bus-off When the Init bit is set to "1", all message transmission/reception on the CAN bus is stopped, and the CAN_TX pin for the CAN bus output is set to recessive output. (Except for the CAN_TX test mode). When the Init bit is set to "1", no error counters and registers change. When the Init and CCE bits in the CAN control register are set to "1", the bit timing register and prescaler expansion register for baud rate control can be set. Resetting the Init bit to "0" terminates the software initialization. The Init bit can be reset to "0" only by the access from the CPU. When 11-bit recessives continuously occur (= bus idle) after the Init bit was reset to "0", messages are transferred after being synchronized with the data transfer on the CAN bus. Before changing the message object masks, ID, XTD, EoB, and RmtEn, set MsgVal to invalid. 522 CHAPTER 16 CAN CONTROLLER 16.5.9 CAN Clock Prescaler This section describes the switching of the CAN clock while PLL is running. ■ Block Diagram Figure 16.5-10 shows the CAN Clock Prescaler block diagram. The clock provided to the CAN is decided according to the setting of the CAN clock prescaler register (CANPRE). Figure 16.5-10 CAN Clock Prescaler Block Diagram CPU clock CAN Interface Clock unit Clock Divider CAN Controller X0 PLL CPCK[1:0] DVC[3:0] CANPRE 523 CHAPTER 16 CAN CONTROLLER ■ Clock Switching Procedure The following procedure is recommended to switch the clock by using the CAN clock prescaler. Figure 16.5-11 Clock Switching Procedure Switching CAN clock : OSCILLATOR -> PLL Switching CAN clock : PLL -> OSCILLATOR Set bit Init in the CAN Control Register Set bit Init in the CAN Control Register Enable PLL Set prescaler value Wait for PLL Lock Time Disable PLL Set prescaler value Reset bit Init in the CAN Control Register Reset bit Init in the CAN Control Register 524 CHAPTER 16 CAN CONTROLLER ■ CAN Clock Frequency The following table shows the CAN clock frequency generated by setting CPCKS[1:0] and DVC[3:0] of CANPRE (When a 18 MHz quartz oscillator is connected). Table 16.5-3 CAN Clock Frequency DVC[3:0] CPCKS[1:0]=00B (when 72 MHz CPU clock is selected) CPCKS[1:0]=01B (when 144 MHz PLL output is selected) CPCKS[1:0]=11B (when 18 MHz source oscillation clock is selected) 0000B 72.00 MHz (Setting disabled) 144.00 MHz (Setting disabled) 18.00 MHz 0001B 36.00 MHz (Setting disabled) 72.00 MHz (Setting disabled) 9.00 MHz 0010B 24.00 MHz (Setting disabled) 48.00 MHz (Setting disabled) 6.00 MHz 0011B 18.00 MHz 36.00 MHz (Setting disabled) 4.50 MHz 0100B 14.40 MHz 28.80 MHz (Setting disabled) 3.60 MHz 0101B 12.00 MHz 24.00 MHz (Setting disabled) 3.00 MHz 0110B 10.29 MHz 20.57 MHz (Setting disabled) 2.57 MHz 0111B 9.00 MHz 18.00 MHz 2.25 MHz 1000B 8.00 MHz 16.00 MHz 2.00 MHz 1001B 7.20 MHz 14.40 MHz 1.80 MHz 1010B 6.55 MHz 13.09 MHz 1.64 MHz 1011B 6.00 MHz 12.00 MHz 1.50 MHz 1100B 5.54 MHz 11.08 MHz 1.38 MHz 1101B 5.14 MHz 10.29 MHz 1.29 MHz 1110B 4.80 MHz 9.60 MHz 1.33 MHz 1111B 4.50 MHz 9.00 MHz 1.25 MHz • Before changing the value of the CAN prescaler setting bit, set the initialization bit in the CAN control register to "1" and stop the operation of all buses. • Set the CAN clock to 20 MHz or lower. 525 CHAPTER 16 CAN CONTROLLER 526 CHAPTER 17 LIN-UART This chapter describes functions and operations of the LIN-compatible LIN-UART. 17.1 Overview of LIN-UART 17.2 Configuration of LIN-UART 17.3 LIN-UART Registers 17.4 LIN-UART Interrupts 17.5 LIN-UART Baud Rate Setting 17.6 LIN-UART Operations 17.7 Notes on Using LIN-UART 527 CHAPTER 17 LIN-UART 17.1 Overview of LIN-UART LIN (Local Interconnect Network)-compatible LIN-UART (Universal Asynchronous Receiver and Transmitter) is a general-purpose serial data communication interface which achieves asynchronous/synchronous communication with external devices. The LIN-UART supports bidirectional communication functions (normal mode), master/slave communication functions (multiprocessor mode in a master system), and LIN-bus system (both master and slave operations). ■ Overview The LIN-UART is a general-purpose serial data communication interface used for data transmission/ reception with other CPUs or peripheral circuits, especially with LIN devices. Table 17.1-1 lists the LINUART Functions. Table 17.1-1 LIN-UART Functions (1 / 2) Item Function Data buffer Full-duplex buffer Serial input In asynchronous mode, a received value is determined by 5 oversampling operations. Transfer mode • Clock synchronous (start/stop synchronization or start/stop bit selectable) • Clock asynchronous (start/stop bit) Transfer rate • Dedicated 15-bit baud rate generator is provided. • External clock input can be used, which is adjustable by a reload counter. Data length • 7 bits (Cannot be used in synchronous and LIN modes) • 8 bits Signal mode NRZ (Non Return Zero) format Start bit timing In asynchronous mode, clock synchronization with the falling edge of the start bit. Reception error detection • Framing error • Overrun error • Parity error Interrupt request • Reception interrupt (reception completion/reception error detection) • Transmission interrupt (transmission completion) • Bus Idle interrupt (belongs to reception interrupt) • LIN-Synch-Break interrupt (belongs to reception interrupt) Master/slave communication function (multiprocessor mode) One-to-many (One master and multiple slaves) communication available (supported by either of a master or slave system) Synchronization mode Function as master or slave LIN-UART Transmission cable Direct access available 528 CHAPTER 17 LIN-UART Table 17.1-1 LIN-UART Functions (2 / 2) Item Function LIN bus options • Operation as a master device • Operation as a slave device • Generation of LIN-Synch-Break • Detection of LIN-Synch-Break • Detection of the start/stop edges in the LIN-Synch-Field with ICU Synchronous serial clock The synchronous serial clock can be continuously output from the SCK pin for synchronous communication using start/stop bits. Clock delay option Special synchronous clock mode for clock delay (for SPI) ■ Operation Modes of LIN-UART The LIN-UART offers four operation modes which are specified with the MD0 and MD1 bits in the serial mode register (SMR). Mode 0 and mode 2 are used for bidirectional serial communication, and mode 1 is for master/slave communication. Mode 3 is for LIN master/slave communication. Table 17.1-2 Operation Modes of LIN-UART Data length Operation mode Parity disabled 0 Normal mode bit7 or bit8 1 Multiprocessor mode bit7 or bit8 + 1 (*2) 2 Normal mode bit8 3 LIN mode bit8 Parity enabled − − Synchronization mode Data bit detection*1 Stop bit length Asynchronous bit1 or bit2 L/M Asynchronous bit1 or bit2 L/M Synchronous bit0, bit1 or bit2 L/M Asynchronous bit1 L *1: Indicates that the transfer starts from LSB first or MSB first. *2: "+1" is used to show the address/data selection in the multiprocessor mode when a parity bit is not used. Note: Mode 1 (multiprocessor mode) supports the operations of both the LIN-UART master and slave in a master/slave system. In mode 3, the functions of the LIN-UART are fixed to 8N1 format and LSB first. 529 CHAPTER 17 LIN-UART When the mode is changed, the LIN-UART stops transmission and reception, and waits for and changes to the new action. Table 17.1-3 lists the mode bit settings. Table 17.1-3 Mode Bit Settings 530 MD1 MD0 Mode Function 0 0 0 Asynchronous (Normal mode) 0 1 1 Asynchronous (Multiprocessor mode) 1 0 2 Synchronous (Normal mode) 1 1 3 Asynchronous (LIN mode) CHAPTER 17 LIN-UART 17.2 Configuration of LIN-UART This section describes the configuration of the LIN-UART. ■ LIN-UART Block Diagram The LIN-UART consists of the following blocks: • Reload counter • Reception control circuit • Reception shift register • Reception data register (RDR) • Transmission control circuit • Transmission shift register • Transmission data register (TDR) • Error detection circuit • Oversampling unit • Interrupt generation circuit • LIN-Synch-Break and Synch-Field detection circuit • Bus Idle detection circuit • Serial mode register (SMR) • Serial control register (SCR) • Serial status register (SSR) • Extended communication control register (ECCR) • Extended communication status/control register (ESCR) 531 CHAPTER 17 LIN-UART ■ LIN-UART Block Diagram Figure 17.2-1 LIN-UART Block Diagram PE ORE FRE Transmission clock CLK TIE Reception clock Reload Counter SCK RIE RECEPTION CONTROL CIRCUIT Pin LBD Interrupt Generation circuit BIE Transmission Start circuit Start bit Detection circuit SIN LBIE TRANSIMISSION CONTROL CIRCUIT RBI TBI Pin Restart Reception Reload Counter Oversampling Unit Received Bit counter Transmission Bit counter Received Parity counter Transmission Parity counter Transmission IRQ SOT Pin RDRF Reception complete SIN Signal to ICU Reception shift register LIN sync break and Synch Field Detection circuit Reception IRQ TDRE SOT SIN Transmission shift register LIN break generation circuit Transmission start Error Detection RDR Bus Idle Detection circuit TDR STR PE ORE FRE RBI TBI LBD Internal data bus PE ORE FRE RDRF TDRE BDS RIE TIE 532 SSR register MD1 MD0 (OTO) (EXT) (REST) UPCL SCKE SOE SMR register PEN P SBL CL AD CRE RXE TXE SCR register LBIE LBD LBL1 LBL0 SOPE SIOP CCO SCES ESCR Rregister LBR MS SPI SSM BIE RBI TBI ECCR register LBR LBL1 LBL0 CHAPTER 17 LIN-UART ■ Description of the Blocks ● Reload counter The reload counter operates as a dedicated baud rate generator. The transmission/reception clocks are generated from an external clock or an internal clock. The reload counter has a 15-bit register to store a reload value. The actual count value of the transmission reload counter can be read from the value of BGR0/BGR1. ● Reception control circuit The reception control circuit consists of a received bit counter, a start bit detection circuit, and a received parity counter. The received bit counter counts received data bits. When the reception of one data item of the specified data length is complete, the received bit counter sets a reception data register full flag. The start bit detection circuit detects a start bit from serial input signals, and sends out a signal to the reload counter in synchronization with the falling edge of the start bit. The received parity counter calculates the parity of the received data. ● Reception shift register The reception shift register captures the received data input from the SIN pin by shifting the data bit by bit. When the reception is complete, the reception shift register transfers the received data to the reception data register (RDR). ● Reception data register (RDR) The reception data register retains the received data. Serial input data is converted and stored into this register. ● Transmission control circuit The transmission control circuit consists of a transmission bit counter, a transmission start circuit, and a transmission parity counter. The transmission bit counter counts transmission data bits. When the transmission of one data item of the specified data length is complete, the transmission bit counter sets a transmission data register empty flag. The transmission start circuit starts transmission when data is written to the TDR. If parity is enabled, the transmission parity counter generates a parity bit of the transmission data. ● Transmission shift register The transmission shift register shifts the transmission data written to the transmission data register (TDR) and outputs the data bit by bit to the SOT pin. ● Transmission data register (TDR) Transmission data is set to the transmission data register. The data written to this register is converted into serial data and is output. ● Error detection circuit The error detection circuit checks whether an error occurred during the last reception. When it detects an error occurrence, it sets the corresponding error flag. 533 CHAPTER 17 LIN-UART ● Oversampling unit The oversampling unit repeats oversampling of the data input from the SIN pin for five times. This unit is disabled in the synchronous operation mode. ● Interrupt generation circuit The interrupt generation circuit controls every interrupt. When an interrupt is enabled and an interrupt factor for the interrupt arises, the interrupt is generated immediately. ● LIN-Break and Synch-Field detection circuit The LIN-Break and LIN-Synch-Break detection circuit detects a LIN-Break when the LIN master node is sending out a message handler. When a LIN-Break is detected, the LBD flag bit is generated. The first and fifth falling edges in the Synch-Field are detected by this circuit. Then an internal signal is sent to the input capture in order to measure an accurate serial clock cycle of the transmission master node. ● LIN-Break generation circuit The LIN-Break generation circuit generates a LIN-Synch-Break of a specified length. ● Bus Idle detection circuit The Bus Idle detection circuit detects the status where neither reception nor transmission is performed (bus idle). When such a status is detected, the circuit generates flag bits TBI and RBI. ● Serial mode register (SMR) The serial mode register is used for the following operations: • Select the operation mode of the LIN-UART. • Select clock input. • Select whether the external clock is connected 1-to-1 or connected to the reload-counter. • Restart the dedicated reload timer. • Reset the LIN-UART (The register settings are saved.). • Enable the output at the serial output pin (SOT). • Switch the input/output at the serial clock pin (SCK). ● Serial control register (SCR) The serial control register is used for the following operations: • Select whether to enable or disable parity bits. • Select the type of parity bits. • Specify the stop bit length. • Specify the data length. • Specify the frame data format in mode 1. • Clear an error flag. • Enable transmission. • Enable reception. 534 CHAPTER 17 LIN-UART ● Serial status register (SSR) The serial status register checks the transmission/reception and error statuses. It is also used to enable transmission/reception interrupts and set the transfer direction (LSB first/MSB first). ● Extended status/control register (ESCR) The extended status/control register sets the LIN functions. It specifies the direct access to the SIN and SOT pins and the settings for the LIN-UART synchronous clock mode. ● Extended communication control register (ECCR) The extended communication control register specifies the Bus Idle detection interrupt, sets the synchronous clock, and generates a LIN-Break. 535 CHAPTER 17 LIN-UART 17.3 LIN-UART Registers Figure 17.3-1 shows the LIN-UART registers. ■ LIN-UART Registers Figure 17.3-1 LIN-UART Registers SCR Address: 000040H, 000048H, bit15 000050H, 000058H, 000060H, 000068H, PEN 000070H Read/Write (R/W) Initial value (0) 14 13 12 11 10 9 8 P SBL CL AD CRE RXE TXE (R/W) (R/W) (R/W) (R/W) (W) (R/W) (R/W) (0) (0) (0) (0) (0) (0) (0) SMR Address: 000041H, 000049H, bit7 000051H, 000059H, 000061H, 000069H, MD1 000071H 6 5 4 3 2 1 0 MD0 OTO EXT REST UPCL SCKE SOE Read/Write (R/W) (R/W) (R/W) (R/W) (W) (W) (R/W) (R/W) (0) (0) (0) (0) (0) (0) (0) 14 13 12 11 10 9 8 ORE FRE RDRF TDRE BDS RIE TIE Initial value (0) SSR Address: 000042H, 00004AH, bit15 000052H, 00005AH, 000062H, 00006AH, PE 000072H Read/Write (R) (R) (R) (R) (R) (R/W) (R/W) (R/W) Initial value (0) (0) (0) (0) (1) (0) (0) (0) Address: 000043H, 00004BH, 000053H, 00005BH, 000063H, 00006BH, 000073H bit7 6 5 4 3 2 1 0 D7 D6 D5 D4 D3 D2 D1 D0 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (0) (0) (0) (0) (0) (0) (0) 14 13 12 11 10 9 8 LBD LBL1 LBL0 SOPE SIOP CCO SCES (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (0) (0) (0) (0) (x) (0) (0) RDR/TDR Read/Write (R/W) Initial value (0) ESCR Address: 000044H, 00004CH, bit15 000054H, 00005CH, 000064H, 00006CH, LBIE 000074H Read/Write (R/W) Initial value (0) (Continued) 536 CHAPTER 17 LIN-UART (Continued) ECCR Address: 000045H, 00004DH, 000055H, 00005DH, 000065H, 00006DH, 000075H bit7 6 5 4 3 2 1 0 Reserved LBR MS SCDE SSM BIE RBI TBI Read/Write (− ) (W) (R/W) (R/W) (R/W) (R/W) (R) (R) Initial value (0) (0) (0) (0) (0) (0) (X) (X) 14 13 12 11 10 9 8 B14 B13 B12 B11 B10 B09 B08 BGR1 Address: 000080H, 000082H, bit15 000084H, 000086H, Reserved 000088H, 00008AH, 00008CH Read/Write (− ) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Initial value (0) (0) (0) (0) (0) (0) (0) (0) Address: 000081H, 000083H, 000085H, 000087H, 000089H, 00008BH, 00008DH bit7 6 5 4 3 2 1 0 B07 B06 B05 B04 B03 B02 B01 B00 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (0) (0) (0) (0) (0) (0) (0) BGR0 Read/Write (R/W) Initial value (0) 537 CHAPTER 17 LIN-UART 17.3.1 Serial Control Register (SCR) The serial control register (SCR) specifies parity bits, selects the stop bit length and data length, selects the frame data format in mode 1, clears a reception error flag, and enable transmission/reception. ■ Serial Control Register (SCR) Figure 17.3-2 Bit Configuration of Serial Control Register (SCR) SCR Address: 000040H, 000048H, bit15 000050H, 000058H, 000060H, 000068H, PEN 000070H Read/Write (R/W) Initial value (0) 14 13 12 11 10 9 8 P SBL CL AD CRE RXE TXE (R/W) (R/W) (R/W) (R/W) (W) (R/W) (R/W) (0) (0) (0) (0) (0) (0) (0) [bit15] PEN: Parity enable bit Table 17.3-1 Parity Enable Bit PEN Parity enable 0 Parity disabled [Initial value] 1 Parity enabled This bit selects whether or not to add parity to the transmission data in the serial asynchronous mode. Parity is detected during reception. Parity is added in mode 0, and in mode 2 when the SSM bit in the ECCR is set. In mode 3 (LIN mode), this bit is fixed to "0" (Parity disabled). [bit14] P: Parity selection bit Table 17.3-2 Parity Selection Bit P Parity selection 0 Even parity [Initial value] 1 Odd parity When parity is enabled, this bit selects whether to use even parity (0) or odd parity (1). 538 CHAPTER 17 LIN-UART [bit13] SBL: Stop bit length selection bit Table 17.3-3 Stop Bit Length Selection Bit SBL Stop bit length 0 1 bit [Initial value] 1 2 bits This bit selects the stop bit length of an asynchronous data frame. When the SSM bit in the ECCR is set, the stop bit length is selected also for a synchronous data frame. In mode 3 (LIN mode), this bit is fixed to "0" (1 bit). [bit12] CL: Data length selection bit Table 17.3-4 Data Length Selection Bit CL Data length 0 7 bits [Initial value] 1 8 bits This bit specifies the length of transmission/reception data. In modes 2 and 3, this bit is fixed to "1" (8 bits). [bit11] AD: Address/data selection bit Table 17.3-5 Address/Data Selection Bit AD Address/data bit 0 Data bit [Initial value] 1 Address bit This bit specifies the data format used in the multiprocessor mode (mode 1). Writing to this bit is used for the master CPU, and reading this bit is used for the slave CPU. Value "1" indicates an address frame, and "0" indicates a data frame. Note: For the usage of the AD bit, refer to "17.7 Notes on Using LIN-UART". 539 CHAPTER 17 LIN-UART [bit10] CRE: Reception error flag clear bit Table 17.3-6 Reception Error Flag Clear Bit Reception error clear CRE Write 0 Invalid [Initial value] 1 Clear all reception errors (PE, FRE, ORE). Read Read value is always "0". This bit clears the PE, FRE, and ORE flags of the serial status register (SSR). It also clears a reception error interrupt factor. Writing "1" to this bit clears the error flags. Writing "0" is invalid. Reading this bit always returns "0". [bit9] RXE: Reception enable bit Table 17.3-7 Reception Enable Bit RXE Reception enable 0 Disable reception. [Initial value] 1 Enable reception. This bit enables the LIN-UART’s reception operation. When this bit is set to "0", the LIN-UART stops receiving data frames. This bit remains invalid for the LIN-Break detection in modes 0 and 3. [bit8] TXE: Transmission enable bit Table 17.3-8 Transmission Enable Bit TXE Transmission enable 0 Disable transmission. [Initial value] 1 Enable transmission. This bit enables the LIN-UART’s transmission operation. When this bit is set to "0", the LIN-UART stops transmitting data frames. 540 CHAPTER 17 LIN-UART 17.3.2 Serial Mode Register (SMR) The serial mode register (SMR) selects the operation mode and baud rate clock. It also specifies the I/O direction of the serial clock (SCK) and enables serial outputs. ■ Serial Mode Register (SMR) Figure 17.3-3 Bit Configuration of Serial Mode Register (SMR) SMR Address: 000041H, 000049H, bit7 000051H, 000059H, 000061H, 000069H, MD1 000071H 6 5 4 3 2 1 0 MD0 OTO EXT REST UPCL SCKE SOE Read/Write (R/W) (R/W) (R/W) (R/W) (W) (W) (R/W) (R/W) Initial value (0) (0) (0) (0) (0) (0) (0) (0) [bit7, bit6] MD1, MD0: Operation mode selection bit Table 17.3-9 Operation Mode Selection Bit MD0 MD1 Operation mode setting 0 0 Mode 0: Asynchronous normal mode [Initial value] 1 0 Mode 1: Asynchronous multiprocessor mode 0 1 Mode 2: Synchronous mode 1 1 Mode 3: Asynchronous LIN mode These bits are used to set the operation mode of the LIN-UART. [bit5] OTO: 1-to-1 external clock selection bit Table 17.3-10 1-to-1 External Clock Selection Bit OTO External clock selection 0 Use an external clock for the baud rate generator (reload counter). [Initial value] 1 Use an external clock as a serial clock. When this bit is set, an external clock is directly used as a serial clock for the LIN-UART. This function is used when the LIN-UART operates as a slave in the synchronous mode. 541 CHAPTER 17 LIN-UART [bit4] EXT: External clock selection bit Table 17.3-11 External Clock Selection Bit EXT External serial clock enable 0 Use the built-in baud rate generator (reload counter). [Initial value] 1 Use an external clock as a serial clock. This bit selects the clock used for the reload counter. [bit3] REST: Transmission reload counter restart bit Table 17.3-12 Transmission Reload Counter Restart Bit Transmission reload counter restart REST Write 0 Invalid [Initial value] 1 Restart the counter. Read Read value is always "0". Writing "1" to this bit restarts the reload counter. Writing "0" is invalid. Reading this bit always returns "0". [bit2] UPCL: LIN-UART clear bit (software reset) Table 17.3-13 LIN-UART Clear Bit (Software Reset) LIN-UART clear (software reset) UPCL Write 0 Invalid [Initial value] 1 Reset the LIN-UART. Read Read value is always "0". When "1" is written to this bit, the LIN-UART is reset immediately, but the register setting values are saved. Reception/transmission is discontinued. All error flags are cleared and the reception data register (RDR) is set to "00H". Writing "0" is invalid. Reading this bit always returns "0". 542 CHAPTER 17 LIN-UART [bit1] SCKE: Serial clock output enable Table 17.3-14 Serial Clock Output Enable SCKE Serial clock output enable 0 External clock input [Initial value] 1 Serial clock output This bit controls the input/output at the serial clock pin (SCK). When this bit is set to "0", the SCK pin operates as a general-purpose port/serial clock input pin. When this bit is set to "1", the pin operates as a serial clock output pin. Note: To use the SCK pin for a serial clock input (SCKE=0), set the port as an input port. To use it for a serial clock output, you need to set the SCKE bit as well as the port function register (PFR) corresponding to the SCK pin. For details of the port function register setting, refer to "CHAPTER 10 I/O PORT". Also, select an external clock by setting the external clock selection bit (EXT=1). [bit0] SOE: Serial data output enable bit Table 17.3-15 Serial Data Output Enable Bit SOE Serial data output enable 0 Disable SOT output. [Initial value] 1 Enable SOT output. This bit enables serial output. When this bit is set to "1", serial data output is enabled. Note: To use the SOT pin for serial output, you need to set the SOE bit as well as the corresponding port function register (PFR). For details of the port function register setting, refer to "CHAPTER 10 I/O PORT". 543 CHAPTER 17 LIN-UART 17.3.3 Serial Status Register (SSR) The serial status register (SSR) shows the transmission/reception status and the occurrence of errors. It also controls transmission/reception interrupts. ■ Serial Status Register (SSR) Figure 17.3-4 Bit Configuration of Serial Status Register (SSR) SSR Address: 000042H, 00004AH, bit15 000052H, 00005AH, PE 000062H, 00006AH, 000072H 14 13 12 11 10 9 8 ORE FRE RDRF TDRE BDS RIE TIE Read/Write (R) (R) (R) (R) (R) (R/W) (R/W) (R/W) Initial value (0) (0) (0) (0) (1) (0) (0) (0) [bit15] PE: Parity error flag bit Table 17.3-16 Parity Error Flag Bit PE Parity error 0 No parity error occurred. [Initial value] 1 Parity error occurred during reception. If a parity error occurs during reception, this bit is set to "1". This bit is cleared when "1" is written to the CRE bit in the serial control register (SCR). When this bit and the RIE bit are "1", a reception interrupt request is output. When this flag is set, the data in the reception data register (RDR) is invalid. [bit14] ORE: Overrun error flag bit Table 17.3-17 Overrun Error Flag Bit ORE Overrun error 0 No overrun error occurred. [Initial value] 1 Overrun error occurred during reception. If an overrun error occurs during reception, this bit is set to "1". This bit is cleared when "1" is written to the CRE bit in the serial control register (SCR). When this bit and the RIE bit are "1", a reception interrupt request is output. When this flag is set, the data in the reception data register (RDR) is invalid. 544 CHAPTER 17 LIN-UART [bit13] FRE: Framing error flag bit Table 17.3-18 Framing Error Flag Bit FRE Framing error 0 No framing error occurred. [Initial value] 1 Framing error occurred during reception. If a framing error occurs during reception, this bit is set to "1". This bit is cleared when "1" is written to the CRE bit in the serial control register (SCR). When this bit and the RIE bit are "1", a reception interrupt request is output. When this flag is set, the data in the reception data register (RDR) is invalid. [bit12] RDRF: Reception data full flag bit Table 17.3-19 Reception Data Full Flag Bit RDRF Reception data register full 0 Reception data register contains no data. [Initial value] 1 Reception data register contains data. This flag shows the status of the reception data register (RDR). When received data is stored in the RDR, this bit is set to "1". This bit is cleared to "0" only when the RDR is read. When this bit and the RIE bit are "1", a reception interrupt request is output. [bit11] TDRE: Transmission data empty flag bit Table 17.3-20 Transmission Data Empty Flag Bit TDRE Transmission data register empty 0 Transmission data register contains data. 1 Transmission data register contains no data. [Initial value] This flag shows the status of the transmission data register (TDR). This bit is cleared to "0" when transmission data is written to the TDR. This bit is set to "1" when data is stored into the transmission shift register and transmission starts. When this bit and the TIE bit are "1", a transmission interrupt request is output. 545 CHAPTER 17 LIN-UART [bit10] BDS: Transfer direction selection bit Table 17.3-21 Transfer Direction Selection Bit BDS Transfer direction setting 0 Transmission/reception uses "LSB first" method. [Initial value] 1 Transmission/reception uses "MSB first" method. Setting this bit selects the transfer direction of the serial transfer data to either of LSB first (BDS=0) or MSB first (BDS=1). In mode 3 (LIN mode), this bit is fixed to "0". Note: During reading/writing of the serial data register, the high-order side and low-order side of the serial data is switched. When the value of this bit is changed after data is written to the RDR, the data is invalid. [bit9] RIE: Reception interrupt request enable bit Table 17.3-22 Reception Interrupt Request Enable Bit RIE Reception interrupt request enable 0 Disable reception interrupts. [Initial value] 1 Enable reception interrupts. This bit controls the reception interrupt request to the CPU. When this bit is set and the reception data flag bit (RDRF) is set to "1" or an error flag (PE, ORE, FRE) is set, a reception interrupt request is issued. [bit8] TIE: Transmission interrupt request enable bit Table 17.3-23 Transmission Interrupt Request Enable Bit TIE Transmission interrupt request enable 0 Disable transmission interrupts. [Initial value] 1 Enable transmission interrupts. This bit controls the transmission interrupt request to the CPU. When this bit is set and the TDRE bit is set to "1", a transmission interrupt request is issued. 546 CHAPTER 17 LIN-UART 17.3.4 Transmission/Reception Data Registers (RDR/TDR) The reception data register (RDR) retains received data, and the transmission data register retains transmission data. The RDR and TDR are located at the same address. ■ Transmission/Reception Data Registers (RDR/TDR) Figure 17.3-5 Reception/Transmission Data Registers RDR/TDR bit7 6 5 4 3 2 1 0 D7 D6 D5 D4 D3 D2 D1 D0 Read/Write (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Initial value (0) (0) (0) (0) (0) (0) (0) (0) Address: 000043H, 00004BH, 000053H, 00005BH, 000063H, 00006BH, 000073H [bit7 to bit0] D7 to D0: Data registers Table 17.3-24 Data Registers Access Data register Read Read from the reception data register Write Write to the transmission data register ● Reception RDR is a register to store received data. The transferred serial data signal received at the SIN pin is converted in the shift register and stored into this register. If the data length is 7 bits, the most significant bit (D7) is "0". When reception is complete, the data is stored into this register, and the reception data full flag bit (SSR: RDRF bit) is set to "1". If a reception interrupt request is enabled in this situation, a reception interrupt occurs. Read the RDR when the RDRF bit in the SSR is set to "1". When the RDR is read, the RDRF bit is automatically cleared to "0". If a reception interrupt is enabled and no reception error occurs, the reception interrupt is also cleared. 547 CHAPTER 17 LIN-UART ● Transmission When transmission is enabled and transmission data is written to the transmission data register, the data is transferred to the transmission shift register, converted into serial data, and transmitted from the serial data output (SOT) pin. When the data length is 7 bits, the most significant bit (D7) is not transmitted. When transmission data is written to this register, the transmission data empty flag bit (SSR: TDRE bit) is cleared to "0". When the transfer to the transmission shift register is complete, the TDRE bit is set to "1". When the TDRE bit is "1", the next transmission data can be written to this register. If a transmission interrupt request is enabled, a transmission interrupt occurs. When a transmission interrupt occurs, or when the TDRE bit is "1", write the next data. Note: The TDR is a write-only register, and the RDR is a read only register. Since these registers are located at the same address, the read value and write value are different. Therefore, do not access to these registers with a read-modify-write (RMW) instruction. 548 CHAPTER 17 LIN-UART 17.3.5 Extended Status/Control Register (ESCR) The extended status/control register sets the LIN functions. It also enables the direct access to the SIN and SOT pins and specifies the LIN-UART synchronous clock mode. ■ Extended Status/Control Register (ESCR) Figure 17.3-6 Bit Configuration of Extended Control Register (ESCR) ESCR Address: 000044H, 00004CH, bit15 000054H, 00005CH, LBIE 000064H, 00006CH, 000074H 14 13 12 11 10 9 8 LBD LBL1 LBL0 SOPE SIOP CCO SCES Read/Write (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Initial value (0) (0) (0) (0) (0) (x) (0) (0) [bit15] LBIE: LIN-Break detection interrupt enable bit Table 17.3-25 LIN-Break Detection Interrupt Enable Bit LBIE LIN-Break detection interrupt enable 0 Disable LIN-Break interrupts. [Initial value] 1 Enable LIN-Break interrupts. This bit enables an interrupt which is generated when a LIN-Break is detected. [bit14] LBD: LIN-Break detection flag bit Table 17.3-26 LIN-Break Detection Flag Bit LIN-Break detection LBD Write Read 0 Clear the LIN-Break detection flag. LIN-Break was not detected. [Initial value] 1 Invalid LIN-Break was detected. When a LIN-Break is detected, this bit is set to "1". This flag bit is cleared when "0" is written to it. If a LIN-Break detection interrupt has been enabled, the interrupt is also cleared. For a read-modify-write (RMW) instruction, the return value is always "1". This, however, does not mean that a LIN-Break was detected. 549 CHAPTER 17 LIN-UART [bit13, bit12] LBL1, LBL0: LIN-Break length selection bit Table 17.3-27 LIN-Break Length Selection Bit LBL0 LBL1 LIN-Break length 0 0 LIN-Break length is 13 bits. [Initial value] 1 0 LIN-Break length is 14 bits. 0 1 LIN-Break length is 15 bits. 1 1 LIN-Break length is 16 bits. These bits define the serial bit length of the LIN-Break generated in the LIN-UART. For the LIN-Break reception, the length is always fixed to 11 bits. [bit11] SOPE: Serial output pin direct access enable bit Table 17.3-28 Serial Output Pin Direct Access Enable Bit SOPE Serial output pin direct access 0 Disable the direct access to the serial output pin. [Initial value] 1 Enable the direct access to the serial output pin. Setting this bit to "1" enables the direct writing to the SOT pin. For details, refer to Table 17.3-30 . [bit10] SIOP: Serial I/O pin direct access enable bit Table 17.3-29 Serial I/O Pin Direct Access Enable Bit Serial I/O pin direct access enable SIOP Write (SOPE=1) 0 SOT outputs "0" 1 SOT outputs "1" [Initial value] Read The value of SIN is read. For a normal read instruction, the value at the SIN pin is returned. Writing to this bit sets the value at the SOT pin. For a read-modify-write (RMW) instruction, the value at SOT is returned. For details, refer to Table 17.3-30 . Table 17.3-30 SOPE and SIOP Operations 550 SOPE SIOP Write to SIOP Read from SIOP 0 R/W The SOT pin is not affected. The written value is retained. The value of SIN is read. 1 R/W Value is written to the SOT pin and is output. The value of SIN is read. 1 RMW The value of the SOT pin is read and written. CHAPTER 17 LIN-UART Note: A setting value of this bit is effective only for the TXE bit of serial control register (SCR) is "0". [bit9] CCO: Continuous clock output enable bit Table 17.3-31 Continuous Clock Output Enable Bit CCO Continuous clock output (mode 2) 0 Disable continuous clock output. [Initial value] 1 Enable continuous clock output. When the LIN-UART operates as a master in mode 2 (synchronous mode) and the SCK pin is set for output, setting this bit enables the continuous serial clock output from SCK. [bit8] SCES: Serial clock edge selection bit Table 17.3-32 Serial Clock Edge Selection Bit SCES Serial clock edge selection 0 Perform sampling at the rising edge of the clock (normal). [Initial value] 1 Perform sampling at the falling edge of the clock (Inverted clock). This bit inverts the internal serial clock in mode 2 (synchronous mode). When the LIN-UART operates as a master in mode 2 (synchronous mode) and the SCK pin is set for output, the output clock is also inverted. When the LIN-UART operates as a slave in mode 2, the sampling edge changes from a rising edge to a falling edge. 551 CHAPTER 17 LIN-UART 17.3.6 Extended Communication Control Register (ECCR) The extended communication control register (ECCR) specifies the Bus Idle detection interrupt, sets the synchronous clock, and generates a LIN-Break. ■ Extended Communication Control Register (ECCR) Figure 17.3-7 Bit Configuration of Extended Communication Control Register ECCR bit7 6 5 4 3 2 1 0 Reserved LBR MS SCDE SSM BIE RBI TBI Read/Write (−) (W) (R/W) (R/W) (R/W) (R/W) (R) (R) Initial value (0) (0) (0) (0) (0) (0) (x) (x) Address: 000045H, 00004DH, 000055H, 00005DH, 000065H, 00006DH, 000075H [bit7] Reserved: Reserved bit This bit is reserved. Be sure to write "0" to this bit. [bit6] LBR: LIN-Break setting bit Table 17.3-33 LIN-Break Setting Bit LIN-Break setting LBR Write 0 Invalid [Initial value] 1 Generate LIN-Break. Read Read value is always "0". When the operation mode is mode 0 or 3, writing "1" to this bit generates a LIN-Break of the length specified with LBL1 and LBL0 in the ESCR. [bit5] MS: Master/slave mode selection bit Table 17.3-34 Master/Slave Mode Selection Bit MS Master/slave function in mode 2 0 Master mode (Generates a serial clock.) [Initial value] 1 Slave mode (Receives an external serial clock.) This bit sets the LIN-UART in mode 2 (synchronous mode) to a master or a slave. When set as a master, the LIN-UART generates a synchronous clock. When set as a slave, it receives an external serial clock. 552 CHAPTER 17 LIN-UART Note: When setting the LIN-UART as a slave, set the clock source to an external clock for the 1-to-1 external clock input (SMR: SCKE=0, EXT=1, OTO=1). [bit4] SCDE: Serial clock delay enable bit Table 17.3-35 Serial Clock Delay Enable Bit SCDE Serial clock delay enable in mode 2 0 Disable clock delay. [Initial value] 1 Enable clock delay. When the LIN-UART operates in mode 2 and this bit is set, the serial output clock delays one machine cycle. [bit3] SSM: Start/stop bit mode enable Table 17.3-36 Start/Stop Bit Mode Enable SSM Start/stop synchronization in mode 2 0 Disable start/stop bits in mode 2. [Initial value] 1 Enable start/stop bits in mode 2. When the LIN-UART operates in mode 2, setting this bit adds start and stop bits for synchronization. In the other modes (modes 0, 1, and 3), this bit is fixed to "0". [bit2] BIE: Bus idle interrupt enable Table 17.3-37 Bus Idle Interrupt Enable BIE Bus idle interrupt enable 0 Disable Bus Idle interrupts. [Initial value] 1 Enable Bus Idle interrupts. When neither reception nor transmission is performed (RBI=1, TBI=1), this bit enables a reception interrupt. Do not use this bit when the SSM bit is "0" in mode 2. 553 CHAPTER 17 LIN-UART [bit1] RBI: Reception bus idle flag bit Table 17.3-38 Reception Bus Idle Flag Bit RBI Reception bus idle 0 During reception 1 Reception idle When nothing is received at the SIN pin, this bit is set to "1". Do not use this bit when the SSM bit is "0" in mode 2. [bit0] TBI: Transmission bus idle flag bit Table 17.3-39 Transmission Bus Idle Flag Bit TBI Transmission bus idle 0 During transmission 1 Transmission idle When nothing is transmitted at the SOT pin, this bit is set to "1". Do not use this bit when the SSM bit is "0" in mode 2. Note: When setting the operation mode of the LIN-UART to mode 2, do not use the BIE, RBI, and TBI bits if the SSM bit is "0". 554 CHAPTER 17 LIN-UART 17.3.7 Baud Rate/Reload Counter Register (BGR) The baud rate/reload counter register (BGR) sets the division ratio of the serial clock. It can also be used to read the accurate value of the transmission reload counter. ■ Baud Rate/Reload Counter Register (BGR) Figure 17.3-8 Baud Rate/Reload Counter Register BGR1 Address: 000080H, 000082H, bit15 000084H, 000086H, Reserved 000088H, 00008AH, 00008CH 14 13 12 11 10 9 8 B14 B13 B12 B11 B10 B09 B08 Read/Write (−) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Initial value (0) (0) (0) (0) (0) (0) (0) (0) bit7 6 5 4 3 2 1 0 B07 B06 B05 B04 B03 B02 B01 B00 Read/Write (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Initial value (0) (0) (0) (0) (0) (0) (0) (0) BGR0 Address: 000081H, 000083H, 000085H, 000087H, 000089H, 00008BH, 00008DH [bit15] Reserved: Reserved bit This bit is reserved. Read value is always "0". [bit14 to bit8] B14 to B08: Baud rate generator register 1 Table 17.3-40 Baud Rate Generator Register 1 B14 to B08 Baud rate generator register 1 Write Write bit14 to bit8 of the reload value to the counter. Read Read count bit14 to bit8. [bit7 to bit0] B07 to B00: Baud rate generator register 0 Table 17.3-41 Baud Rate Generator Register 0 B07 to B00 Baud rate generator register 0 Write Write bit7 to bit0 of the reload value to the counter. Read Read count bit7 to bit0. 555 CHAPTER 17 LIN-UART ■ Baud Rate/Reload Counter Register (BGR) The baud rate/reload counter register (BGR) sets the division ratio of the serial clock. This register can be read/written with byte access or half-word access. 556 CHAPTER 17 LIN-UART 17.4 LIN-UART Interrupts The LIN-UART provides reception interrupts and transmission interrupts. An interrupt request is generated when any of the following occurs: • Received data is stored to the reception data register (RDR), or a reception error occurs. • Transmission data is transferred from the transmission data register (TDR) to the transmission shift register. • LIN-Break is detected. • Bus Idle (No transmission/reception operation) ■ LIN-UART Interrupts Table 17.4-1 shows the interrupt control bits and interrupt factors of LIN-UART. Table 17.4-1 Interrupt Control Bits and Interrupt Factors of LIN-UART Reception/ Interrupt transmission/ request flag bit ICU Reception Transmission Flag register Operation mode Interrupt factor 0 1 2 3 Interrupt factor enable bit How to clear the interrupt request RDRF SSR O O O O Received data written to RDR ORE SSR O O O O Overrun error FRE SSR O O ▲ O Framing error PE SSR O X ▲ X Parity error LBD ESCR O X X O Detection of LINSync-Break ESCR: LBIE Write "1" to the LBD bit in ESCR. TBI & RBI ECCR O O ▲ O Bus Idle ECCR: BIE Receive or transmit data. TDRE SSR O O O O Transmission register empty SSR: TIE Write transmission data. ICP ICS O X X O First falling edge in ICS: ICP LIN-Sync-Field Dsiabe ICP temporarily. ICP ICS O X X O Fifth falling edge in ICS: ICP LIN-Sync-Field Disable ICP. ICU Read the received data. SSR: RIE Write "1" to the reception error clear bit (SSR: CRE). O : Available ▲ : Available when ECCR’s SSM bit is "1". X : Unavailable 557 CHAPTER 17 LIN-UART ■ Reception Interrupt When one of the following events occurs during reception, the corresponding flag bit in the serial status register (SSR) is set to "1". • Completion of data reception: RDRF The received data is transferred from the serial input shift register to the reception data register (RDR) and becomes readable. • Overrun error: ORE RDRF=1 and the RDR was not read from the CPU. • Framing error: FRE During the stop bit reception, "0" was received. • Parity error: PE An incorrect parity bit was detected. When a reception interrupt is enabled (SSR: RIE=1) and any of these flags is set to "1", a reception interrupt is generated. When the reception data register (RDR) is read, the RDRF flag is automatically cleared to "0". This is the only method to clear the RDRF flag. All error flags are cleared to "0" when "1" is written to the reception error flag clear bit (CRE) in the serial control register (SCR). Note: The CRE bit is write-only. When "1" is written, it retains the value for one machine cycle. ■ Transmission Interrupt When transmission data is transferred from the transmission data register (TDR) to the transmission shift register (this occurs when the shift register is empty and transmission data exists), the transmission data register empty flag bit (TDRE) in the serial status register (SSR) is set to "1". If the transmission interrupt enable bit (TIE) in the SSR has been set in this situation, an interrupt request is generated. Note: The initial value of TDRE is "1". Consequently, a transmission interrupt is generated as soon as the TIE flag is set to "1". The TDRE flag is reset only when data is written to the transmission data register (TDR). 558 CHAPTER 17 LIN-UART ■ LIN-Synch-Break Interrupt This interrupt is available when the LIN-UART is in mode 0 or operates as a LIN slave in mode 3. When the serial input bus continues to be "0" for 11 bit times or longer (dominant), the LIN-Break detection flag bit (LBD) in the extended status/control register (ESCR) is set to "1". When this occurs, the reception error flag is set to "1" after 9 bit times. Therefore, set the RIE or RXE flag to "0" if you want to perform the LIN-Synch-Break detection only. Otherwise, you must have a reception error interrupt be generated first, and then use an interrupt processing routine to wait for LBD=1. When "1" is written to the LBD flag, the interrupt and the LBD flag are cleared. This ensures that the CPU reliably detects a LIN-Synch-Break during the procedure of the serial clock adjustment for the LIN master described below. ■ LIN-Synch-Field Edge Detection Interrupt This interrupt is available when the LIN-UART is in mode 0 or operates as a LIN slave in mode 3. After a LIN-Break is detected, the LIN-UART shows the falling edge of the reception bus. At the same time, an interrupt signal connected to the ICU is set to "1". This signal is reset at the 5th falling edge in the LIN-Synch-Field. In either case, the ICU generates an interrupt as long as both edges are detected and an ICU interrupt has been enabled. The difference in the counter values detected by the ICU is eight times greater than that of the serial clock. Using this result enables calculation of baud rate for the dedicated reload counter. Since the reload counter is automatically reset when the falling edge of the start bit is detected, restart operation is unnecessary. ■ Bus Idle Interrupt When no reception activity is detected at the SIN pin, the RBI flag bit in the ECCR is set to "1". Similarly, when no transmission activity is detected at the SOT pin, the TBI flag bit is set to "1". When the Bus Idle enable bit (BIE) in the ECCR is set and both Bus Idle flags (TBI and RBI) are set to "1", an interrupt is generated. Note: When "0" is written to the SIOP bit while the SOPE bit is "1", the TBI flag is set to "0" even when no bus activity is detected. The TBI and RBI bits cannot be used when the SSM bit in the ECCR register is "0" in mode 2 (synchronous mode). 559 CHAPTER 17 LIN-UART Figure 17.4-1 shows the generation of the Bus Idle interrupt. Figure 17.4-1 Generation of Bus Idle Interrupt Transmission data Reception data TBI RBI Reception IRQ : Start bit 560 : Stop bit : Data bit CHAPTER 17 LIN-UART 17.4.1 Reception Interrupt Generation and Flag Set Timing This section describes a reception interrupt factor, reception completion (SSR: RDRF bit), and the occurrence of reception errors (SSR: PE, ORE, and FRE bits). ■ Reception Interrupt Generation and Flag Set Timing When the reception interrupt enable flag bit (RIE) in the serial status register (SSR) is set to "1" and the data reception is complete (RDRF=1), an interrupt is generated. This interrupt is generated when a stop bit is detected in mode 0, 1, 2 (SSM=1), or 3, or when the last data bit is read in mode 2 (SSM=0). Note: If a reception error occurs, the content of the reception data register is invalid regardless of the operation mode. Figure 17.4-2 Reception Activity and Flag Set Timing Receive data (mode 0/mode 3) ST D0 D1 D2 D5 D6 D7/ P SP ST Receive data (mode 1) ST D0 D1 D2 D6 D7 AD SP ST D0 D1 D2 D4 D5 D6 D7 D0 Receive data (mode 2) PE*1, FRE RDRF ORE*2 (if RDRF=1) *1: The PE flag will always remain "0" in mode 1 or mode 3. *2: ORE only occurs, if the reception data is not read by the CPU (RDRF=1) and another fram is read. ST: Start Bit SP: Stop Bit Reception interrupt occurs AD: Mode 1 (multi processor) address/data selection bit Note: Figure 17.4-2 does not show all reception options available in modes 0 and 3. Only "7p1" and "8N1" are shown here (p="E"[even] or "O"[odd]). 561 CHAPTER 17 LIN-UART Figure 17.4-3 ORE Set Timing Receive data RDRF ORE 562 CHAPTER 17 LIN-UART 17.4.2 Transmission Interrupt Generation and Flag Timing A transmission interrupt is generated when the transmission data register (TDR) is ready to accept writing of the next transmission data. ■ Transmission Interrupt Generation and Flag Timing A transmission interrupt is generated when the transmission data register (TDR) is ready to accept writing of the next transmission data. When the transmission interrupt enable bit (TIE) in the serial status register (SSR) is set to "1" to enable a transmission interrupt, and the TDR becomes empty, a transmission interrupt is generated. The transmission register empty (TDRE) flag bit in the SSR indicates whether the TDR is empty. The TDRE bit is read only. This flag is cleared only when data is written to the TDR. Figure 17.4-4 shows the transmission activity and flag set timing. Figure 17.4-4 Transmission Activity and Flag Set Timing Transmission interrupt occurs Transmission interrupt occurs Mode 0,1 or 3: Write to TDR TDRE Serial output P P ST D0 D1 D2 D3 D4 D5 D6 D7 AD SP ST D0 D1 D2 D3 D4 D5 D6 D7 AD SP Transmission interrupt occurs Transmission interrupt occurs Mode 2 (SSM = 0): Write to TDR TDRE Serial output D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 ST: Start bit D0 to D7: data bits P: Parity AD: Address/data selection bit (mode1) SP: Stop bit Note: The example in Figure 17.4-4 does not show all transmission options available in mode 0. Only "8p1" (p="E"[even] or "O"[odd]) is shown here. When the SSM bit is "0" in modes 3 and 2, parity is not added. 563 CHAPTER 17 LIN-UART ■ Transmission Interrupt Request Generation Timing When a transmission interrupt is enabled (SSR: TIE bit=1) and the TDRE flag is set to "1", a transmission interrupt request is generated. Note: The initial value of the TDRE is "1". Therefore, a transmission completion interrupt is set as soon as a transmission interrupt is enabled (TIE=1). The TDRE is read only. The TDRE flag is cleared only when data is written to the transmission data register (TDR). Be sure to determine proper timing to enable a transmission interrupt. 564 CHAPTER 17 LIN-UART 17.5 LIN-UART Baud Rate Setting Any of the following can be selected as a serial clock for the LIN-UART. • Dedicated baud rate generator (reload counter) • External clock (Clock input from the SCK pin) • External clock used for the baud rate generator (reload counter) ■ Selecting the Baud Rate for the LIN-UART Figure 17.5-1 shows the baud rate selection circuit (reload counter). Baud rate can be selected from the following three options: ● Dedicated baud rate generator (reload counter) The LIN-UART has independent reload counters for the transmission and reception serial clocks respectively. Baud rate is set based on the 15-bit reload value stored in the baud rate generator register (BGR). The reload counter divides the frequency of the machine clock using the setting value in the baud rate generator register. ● External clock (1-to-1 mode) The clock input received at the LIN-UART’s clock input pin (SCK) is directly used as baud rate. ● External clock used for the dedicated baud rate generator It is also possible to connect an external clock to the reload counter inside the device. In this option, the external clock is used as a replacement of the internal machine clock. 565 CHAPTER 17 LIN-UART Figure 17.5-1 Baud Rate Selection Circuit (Reload Counter) REST Start bit falling edge detected Reload Value: v Rxc = 0? Set Reception 15-bit Reload Counter Reload Rxc = v/2? FF Reset 0 1 EXT Reload Value: v Txc = 0? CLK SCK (External clock input) 0 Set Transmission 15-bit Reload Counter Reload 1 Count Value: Txc Txc = v/2? FF Reset 0 566 OTO 1 Transmission Clock Internal data bus EXT REST OTO Reception Clock SMR register B14 B13 B12 B11 B10 B09 B08 BGR1 register B07 B06 B05 B04 B03 B02 B01 B00 BGR0 register CHAPTER 17 LIN-UART 17.5.1 Baud Rate Setting This section describes the baud rate setting procedure and the calculation result of the serial clock frequency. ■ Baud Rate Calculation The baud rate generator register (BGR) sets the 15-bit reload counter. Use the following formula to calculate the baud rate. v = [φ / b] − 1 Where, "φ" is the machine clock frequency, and "b" is the baud rate. ● Calculation example When the machine clock is 16 MHz and the target baud rate is 19200 bps, the reload value "v" can be calculated as follows: v = [16 × 106 / 19200] − 1 = 832 The precise value of the baud rate can be obtained by the following re-calculation: bexact = φ / (v + 1) = 16 × 106 / 833 = 19207.6831 bps Note: When the reload value is set to "0", the reload counter stops. Consequently, the minimum division ratio is 2. 567 CHAPTER 17 LIN-UART ■ Examples of Baud Rate Settings by Machine Clock Frequencies Table 17.5-1 lists the examples of baud rate settings by machine clock frequency. Table 17.5-1 Examples of Baud Rate Settings By Machine Clock Frequency Baud rate (bps) 9 MHz 10 MHz 18 MHz 20 MHz value dev. value dev. value dev. value dev. 4M − − − − − − 4 0 2M 4 10.00 4 0.00 8 0.00 9 0 1M 8 0.00 9 0.00 17 0.00 19 0 500000 17 0.00 19 0.00 35 0.00 39 0 460800 − − − − 38 -0.16 − − 250000 35 0.00 39 0.00 71 0.00 79 0 230400 38 -0.16 − − 77 -0.16 − − 153600 58 0.69 64 -0.16 116 -0.16 129 -0.16 125000 71 0.00 79 0.00 143 0.00 159 0 115200 77 -0.16 86 0.22 155 -0.16 173 0.22 76800 116 -0.16 129 -0.16 233 -0.16 259 -0.16 57600 155 -0.16 173 0.22 312 0.16 346 -0.06 38400 233 -0.16 259 -0.16 468 0.05 520 0.03 28800 312 0.16 346 -0.06 624 0.00 693 -0.06 19200 468 0.05 520 0.03 937 0.05 1041 0.03 10417 863 0.00 959 0.00 1727 0.00 1919 0 9600 937 0.05 1041 0.03 1874 0.00 2083 0.03 7200 1249 0.00 1388 0.01 2499 0.00 2777 0.01 4800 1874 0.00 2082 -0.02 3749 0.00 4166 0.01 2400 3749 0.00 4166 0.01 7499 0.00 8332 0 1200 7499 0.00 8332 0.00 14999 0.00 16666 0 600 14999 0.00 16666 0.00 29999 0.00 − − 300 29999 0.00 − − − − − − Note: The unit of the deviation (dev.) is %. The maximum synchronization baud rate is 5 divisions of the machine clock. 568 CHAPTER 17 LIN-UART ■ Using an External Clock When the EXT bit in the SMR is set, an external pin SCK is selected for clock input. The external clock is treated in the same manner as the internal MCU clock. It is designed, by connecting the SCK pin to a 1.8432-MHz quartz oscillator, for example, to use the reload counter to select every baud rate of PC-16550LIN-UART. When the "1-to-1" external clock input mode (SMR: OTO bit) is selected, the SCK signal is directly connected to the LIN-UART serial clock input. This is necessary to use the LIN-UART as a slave device in mode 2 (synchronous mode). Note: In either case, the clock signal is synchronized with the MCU clock inside the LIN-UART. This means that the clock ratio which cannot be divided may result in unstable signals. ■ Example of Counting Figure 17.5-2 shows the example of counting by reload counters. In this example, the reload value is assumed to be 832. Figure 17.5-2 Example of Counting by Reload Counters Transmission/ Reception Clock Reload Count 001 000 832 831 830 829 828 827 412 411 410 Reload Count value Transmission/ Reception Clock Reload Count 417 416 415 414 413 Note: The falling edge of the serial clock signal is always after |(v + 1) / 2|. 569 CHAPTER 17 LIN-UART 17.5.2 Restarting Reload Counter The reload counter can be restarted with the following factors: (Common to the transmission and reception reload counters) • MCU reset • LIN-UART software clear (SMR: UPCL bit) • LIN-UART software restart (SMR: REST bit) (Reception reload counter only) • Falling edge of the start bit in asynchronous mode ■ Software Restart When the REST bit in the serial mode register (SMR) is set, both transmission/reception reload counters are restarted at the next clock cycle. This function is provided to use the transmission reload counter as a timer. Figure 17.5-3 shows the example of reload counter restart operation. The reload value is assumed as 100. Figure 17.5-3 Example of Reload Counter Restart Operation MCU Clock Reload Counter Clock Outputs REST Reload Value 37 36 35 100 99 98 97 96 95 94 93 92 91 90 89 88 87 Read BGR0/BGR1 Data Bus 90 : Don’t care In this example, the MCU clock cycle count (cyc) after the REST is set is obtained as follows: cyc = v − c + 1 = 100 − 90 + 1 = 11 Where, "v" is the reload value, and "c" is the readout counter value. 570 CHAPTER 17 LIN-UART Note: When the LIN-UART is reset by the UPCL bit in the SMR, the reload counter is also restarted. ■ Automatic Restart In the asynchronous mode of the LIN-UART, the reception reload counter is restarted when the falling edge of the start bit is detected. This is intended to synchronize the serial input shift register with the input serial data. 571 CHAPTER 17 LIN-UART 17.6 LIN-UART Operations In operation mode 0, the LIN-UART normally operates for bidirectional serial communication. In mode 2 or mode 3, it offers bidirectional communication as a master or a slave. In mode 1, it offers multiprocessor communication as a master or a slave. ■ LIN-UART Operations ● Operation mode The LIN-UART can be used in four operation modes: Modes 0 to 3. Table 17.6-1 shows available operation modes according to the connection settings between the CPUs and the data transfer type. Table 17.6-1 Operation Modes of LIN-UART Data length Operation mode 0 Normal mode 1 Multiprocessor mode Parity disabled 7-bit or 8-bit 7-bit or 8bit + 1 (*2) 2 Normal mode 3 LIN mode Parity enabled − 8-bit 8-bit − Synchronization Stop bit length Data direction *1 Asynchronous 1-bit or 2-bit L/M Asynchronous 1-bit or 2-bit L/M Synchronous 0-bit, 1-bit or L/M 2-bit Asynchronous 1-bit L *1: Indicates the type of the transfer data (LSB first or MSB first). *2: "+1" expresses the bit displayed in the address/data section which is added instead of the parity bit in the multiprocessor mode. Note: Mode 1 supports both master and slave operations of the LIN-UART in the master/slave connection system. In mode 3, the functions of the LIN-UART are fixed as 8N1 format, LSB first. When the mode is changed, the LIN-UART stops all the current transmission/reception operations and starts the next action. ■ Connection between CPUs Either the external clock "1-to-1" connection (normal mode) or the master/slave connection (multiprocessor mode) can be selected. In either connection, the settings of the data length, parity, and synchronization method must be the same in all CPUs. Select the operation mode according to the following instructions: • In the "1-to-1" connection, set the two CPUs in operation mode 0 (asynchronous transfer mode) or operation mode 2 (synchronous transfer mode). To use mode 2, be sure to set one CPU as a master, and the other as a slave. • In the master/slave connection, select operation mode 1 and use the CPUs as either a master or a slave. 572 CHAPTER 17 LIN-UART ■ Synchronization Method In the asynchronous operation mode, the LIN-UART reception clock is automatically synchronized with the falling edge of the reception start bit. In the synchronous operation mode, the synchronization is performed either by the clock signal of the master device, or by the LIN-UART itself if it operates as a master. ■ Single Mode The LIN-UART treats data as NRZ (Non Return to Zero) format data. ■ Operation Enable Bit The LIN-UART controls transmission and reception using the transmission enable bit (SCR: TXE bit) and the reception enable bit (SCR: RXE bit). When the operation is disabled, the transmission and reception will stop in the following steps respectively: • When the reception operation is disabled during reception (inputting data to the reception shift register), the frame reception finishes. After the received data in the reception data register (RDR) is read, the reception stops. • When transmission operation is disabled during transmission (outputting data from the transmission shift register), the transmission continues until no data remains in the transmission data register (TDR), and then stops. 573 CHAPTER 17 LIN-UART 17.6.1 Operation in Asynchronous Mode (Operation Modes 0 and 1) When the LIN-UART is used in operation mode 0 (normal mode) or operation mode 1 (multiprocessor mode), the asynchronous transfer mode is selected. ■ Transfer Data Format The data transfer in the asynchronous mode starts with the start bit ("L" level), and ends with the stop bit (the least 1 bit, "H" level). The direction of the bit stream (LSB first or MSB first) is determined by the BDS bit in the serial status register (SSR). When a parity bit is enabled, it is placed between the last data bit and the stop bit. In operation mode 0, the length of the data frame is 7 or 8 bits, including the address/data separation bit which is used instead of a parity bit. The stop bit length is selectable from 1 bit or 2 bits. The bit length of the transfer frame can be calculated as follows: Bit length = 1 + d + p + s (d = Data bit [7-bit or 8-bit], p = Parity [0-bit or 1-bit], s = Stop bit [1-bit or 2-bit]) Figure 17.6-1 Transfer Data Format (Operation Modes 0 and 1) *1 Operation mode 0 ST D0 D1 D2 D3 D4 D5 D6 D7/P Operation mode 1 ST D0 D1 D2 D3 D4 D5 D6 D7 *2 SP AD SP SP *1: D7 (bit 7) if parity is not provided and data length is 8 bits P (parity) if parity is provided and data length is 7 bits *2: Only if SBL-Bit of SCR is set to "1" ST: Start Bit SP: Stop Bit AD: Address/data selectio n bit in mode 1 (multiprocessor mode) Note: When the BDS bit in the serial status register (SSR) is set to "1" (MSB first), the bit stream is processed in the order of D7, D6, ..., D1, D0, (P). When two bits are selected as stop bits, both of them are detected during reception. The reception data full flag (RDRF), however, is set to "1" at the reception of the first stop bit. If the second stop bit is detected and the next start bit is not detected, the Bus Idle flag (ECCR: RBI bit) is set to "1". 574 CHAPTER 17 LIN-UART ■ Transmission Operation When the transmission data register empty flag (TDRE) bit in the serial status register (SSR) is set to "1", data is allowed to be written to the transmission data register (TDR). When data is written to the TDR, the TDRE flag is set to "0". When the transmission operation is enabled by the TXE bit in the serial control register (SCR), the data is written to the transmission shift register, and the transmission starts at the next serial clock cycle, beginning with the start bit. This sets the TDRE flag to "1", and then it is possible to write the next data to the TDR. When a transmission interrupt is enabled (TIE=1), the interrupt is generated by the TDRE flag. Since the initial value of the TDRE flag is "1", the interrupt occurs as soon as the TIE bit is set to "1". If the bit length is set to 7 bits (CL=0), the most significant bit (MSB) of the TDR becomes an unused bit regardless of the bit direction setting of the BDS bit (LSB first or MSB first). ■ Reception Operation Reception operation is performed when it is enabled by the RXE flag bit in the SCR. When the start bit is detected, a data frame is received according to the format specified in the SCR. When an error occurs, the corresponding error flag (PE, ORE, or FRE) is set. After the data frame is received, the data is transferred from the serial shift register to the reception data register (RDR), and the reception data register full flag (RDRF) bit in the SSR is set. To clear the RDRF flag, the RDR must be read from the CPU. When a reception interrupt is enabled (RIE=1), the interrupt is generated by the RDRF. If the data length is set to 7 bits (CL=0), the most significant bit (MSB) of the RDR becomes an unused bit regardless of the bit direction setting of the BDS bit (LSB first or MSB first). Note: When the RDRF flag is set and no error occurs, the reception data register (RDR) contains valid data. Set the reception enable flag (RXE) to "1" while the reception bus level is "H". ■ Stop Bit For transmission, one bit or two bits can be selected as stop bits. When two stop bits are set for reception, both are detected. This is intended to properly set the reception Bus Idle (RBI) flag in the ECCR after the detection of the second stop bit. ■ Error Detection In mode 0, parity, overrun, and framing errors can be detected. In mode 1, overrun and framing errors can be detected. Parity is not used in this mode. ■ Parity In mode 0 (and in mode 2 where the SSM bit in the ECCR is set), when the parity enable (PEN) bit in the serial control register (SCR) is set, the LIN-UART performs parity calculation (during transmission) or parity detection and check (during reception). The P bit in the SCR specifies whether to use odd parity or even parity. 575 CHAPTER 17 LIN-UART 17.6.2 Operation in Synchronous Mode (Operation Mode 2) The clock synchronous transfer is used in the LIN-UART operation mode 2 (normal mode). ■ Transfer Data Format In the synchronous mode, when the SSM bit in the extended communication control register (ECCR) is "0", 8-bit data is transferred without waiting for start/stop bits. The data format in mode 2 depends on the clock signal. Figure 17.6-2 shows the transfer data format (operation mode 2). Figure 17.6-2 Transfer Data Format (Operation Mode 2) Reception or transfer data (ECCR:SSM=0, SCR:PEN=0) D0 D1 D2 D3 D4 D5 D6 D7 Reception or transfer data (ECCR:SSM=1, SCR:PEN=0) ST D0 D1 D2 D3 D4 D5 D6 D7 SP * SP Reception or transfer data (ECCR:SSM=1, SCR:PEN=1) ST D0 D1 D2 D3 D4 D5 D6 D7 P SP * SP *: Only if SBL-Bit of SCR is set to ST: Start Bit SP: Stop Bit P: Parity Bit ■ Clock Inversion and Start/Stop Bits in Mode 2 If the SCES bit in the extended status/control register (ESCR) is set, the serial clock is inverted. As a result, if the LIN-UART is a slave, it captures data at the falling edge of the reception serial clock. When the LINUART is a master and the SCES bit is set, the clock signal’s mark level becomes "0". When the SSM bit in the extended communication control register (ECCR) is set, start and stop bits are added to the data format as in the case of the asynchronous mode. Figure 17.6-3 Transfer Data Format with Inverted Clock Mark level Reception or transmission clock (SCES=0, CCO=0): Reception or transmission clock (SCES=1, CCO=0): Data stream (SSM=1) (here: no parity, 1 stop bit) Mark level ST SP Data frame 576 CHAPTER 17 LIN-UART ■ Clock Supply In the clock synchronous mode (normal mode), the number of transmitted/received bits is equal to the number of clock cycles. If the start/stop synchronization communication is enabled, the number of clock cycles matches with the value including the start/stop bits. If the internal clock (dedicated reload timer) is selected, the data received with clock synchronization is automatically generated when it is transmitted. If the external clock is selected, data is stored in the transmission data register, and the clock cycle for each bit to be sent is supplied or generated externally. When the SCES is "0", the mark level ("H") is retained before transmission starts and after transmission finishes. Setting the SCDE bit in the ECCR delays the transmission clock signal by 1 machine cycle so that the transmission data is valid and stable at any falling edge of the clock. (This is necessary for the receiving device to capture data at the rising or falling edge of the clock.) This function is disabled when the CCO is set. Figure 17.6-4 Delayed Transmission Clock Signal (SCDE=1) Transmission data writing Reception data sample edg (SCES = 0) Mark level Transmitting or receiving clock (normal) Mark level Transmitting clock (SCDE=1) Mark level Transmission and reception data 0 1 1 0 LSB 1 0 Data 0 1 MSB When the serial clock edge selection (SCES) bit in the ESCR is set, the LIN-UART clock is inverted, and the received data is captured at the falling edge of the clock. In this case, make sure that the serial data is valid at the falling edge of the clock. When the LIN-UART is a master and the CCO bit in the extended status/control register (ESCR) is set, the serial clock is continuously output from the SCK pin. In this case, be sure to use both start and stop bits to clearly notify the receiver of the beginning and end of a data frame. Figure 17.6-5 lists the continuous clock output in mode 2. Figure 17.6-5 Continuous Clock Output in Mode 2 Reception or transmission clock (SCES=0, CCO=1): Reception or transmission clock (SCES=1, CCO=1): Data stream (SSM=1) (here: no parity, 1 stop bit) ST SP Data frame 577 CHAPTER 17 LIN-UART ■ Error Detection When start/stop bits are not used (ECCR: SSM=0), only overrun errors are detected. ■ Communication The initialization of the synchronous communication mode requires the following settings: • Baud rate generator register (BGR) Set a reload value to the dedicated baud rate reload counter. • Serial mode register (SMR) MD1, MD0: "10B" (Mode 2) SCKE: "1" (for using the dedicated baud rate reload counter) "0" (external clock input) • Serial control register (SCR) RXE, TXE: Set these flag bits to "1". SBL, AD: No stop bit; No address/data separation; The value is invalid. CL: Automatically fixed to 8-bit data; The value is invalid. CRE: "1" (The error flag is cleared for initialization; Transmission/reception stops.) When SSM=0: No parity; The setting values of PEN and P are invalid. When SSM=1: The setting values of PEN and P are valid. • Serial status register (SSR) BDS: "0" (LSB first), "1" (MSB first) RIE: "1" (Interrupt enabled), "0" (Interrupt disabled) TIE: "1" (Interrupt enabled), "0" (Interrupt disabled) • Extended communication control register (ECCR) SSM: "0" (No start/stop bits, normal) "1" (with start/stop bits, special) MS: "0" (Master mode; The LIN-UART generates a serial clock.) "1" (Slave mode; The LIN-UART receives a serial clock from an external device.) To start communication, write data into the transmission data register (TDR). To only receive data, stop the output with the serial output enable (SOE) bit in the SMR, and write dummy data to the TDR. Note: As in the asynchronous mode, you can use a continuous clock, start/stop bits, and bidirectional communication. 578 CHAPTER 17 LIN-UART 17.6.3 Operation with LIN Function (Operation Mode 3) The LIN-UART can be used as either a LIN master device or a LIN slave device. Mode 3 has been assigned to the LIN function. Setting the LIN-UART to mode 3 specifies the data format to 8N1, LSB first. ■ LIN-UART as LIN Master In the LIN master mode, the master determines the baud rate of the entire bus. Consequently, slave devices are synchronized with the master device. The baud rate specified in the master operation after initialization is retained. When "1" is written to the LBR bit in the extended communication control register (ECCR), "L" level of 13 to 16 bit times is output to the SOT pin. This signifies a LIN-Sync-Break and the start of LIN message. As a result, the TDRE flag in the serial status register (SSR) is set to "0". This flag is reset to "1" after the break, and generates a transmission interrupt to the CPU when the TIE bit in the SSR is "1". The length of the Sync-Break to be transmitted can be set with the LBL1 and LBL0 bits in the ESCR as shown in Table 17.6-2 . Table 17.6-2 LIN-Break Length LBL1 LBL0 Break length 0 0 13 bit times 0 1 14 bit times 1 0 15 bit times 1 1 16 bit times The Synch-Field can be transmitted as one byte "55H" after the LIN-Break. To prevent a transmission interrupt, you can write "55H" to the TDR by writing "1" to the LBR even if the TDRE flag is "0". The transmission shift register waits until the LIN-Break finishes, and then shifts the TDR value. In this case, no interrupt is generated after the LIN-Break and before the start bit. 579 CHAPTER 17 LIN-UART ■ LIN-UART as LIN Slave In the LIN slave mode, the LIN-UART synchronizes with the baud rate of the master. If reception is disabled (RXE=0) but the LIN-Break interrupt is enabled (LBIE=1), and the Synch-Break to the LIN master is detected and indicated by the LBD flag in the ESCR, the LIN-UART generates a reception interrupt. Writing "0" to this bit clears the interrupt. Then, the baud rate of the LIN master is analyzed. The LIN-UART detects the first falling edge in the Synch-Field. The LIN-UART signals it to the input capture (ICU) via the internal signal, and resets the signal to the ICU at the fifth falling edge. Therefore, it is necessary to specify the ICU as the LIN input capture and enable its interrupts. The period when the signal to the ICU is "1" is the accurate baud rate of the LIN master divided by 8. The baud rate setting value can be calculated as follows: Without timer overflow: BGR value = (b − a) / 8 With timer overflow: BGR value = (Max + b − a) / 8 Where, "Max" is the maximum value of the timer, "a" is the value of the ICU counter register after the first interrupt, and "b" is the value of the ICU counter register after the second interrupt. 580 CHAPTER 17 LIN-UART ■ LIN-Synch-Break Interrupt Detection and Flag When a LIN-Synch-Break is detected in the slave mode, the LIN-Break detection (LBD) flag in the ESCR is set to "1". If the LIN-Break interrupt enable (LBIE) bit has been set, it is considered to be an interrupt factor. Figure 17.6-6 shows the timing of the LIN-Synch-Break detection and flag setting. Figure 17.6-6 Timing of LIN-Synch-Break Detection and Flag Setting Serial clock cycle# 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Serial clock Serial input (LIN bus) FRE (RXE=1) LBD (RXE=0) Reception interrupt occurs, if RXE=1 Reception interrupt occurs, if RXE=0 When reception is enabled (RXE=1) and an reception interrupt is enabled (RIE=1), the reception data framing error (FRE) flag bit becomes a reception interrupt factor 2 bit times ("8N1") faster than the LINBreak interrupt. If you want to use the LIN-Break, set the RXE to "0". The LBD can be used in operation modes 0 and 3. Figure 17.6-7 Operation of LIN-UART as LIN Slave Serial clock Serial Input (LIN bus) LBR cleared by CPU LBD Internal ICU Signal Synch break (e.g. 14 Tbit) Synch field 581 CHAPTER 17 LIN-UART ■ LIN Bus Timing Figure 17.6-8 LIN Bus Timing and LIN-UART Signals Old serial clock No clock used (calibration frame) New (calibrated) serial clock ICU count LIN bus (SIN) RXE LBD (IRQ0) LBIE Internal Signal to ICU IRQ from ICU RDRF (IRQ0) RIE Read RDR by CPU Reception Interrupt enable LIN break begins LIN break detected and Interrupt IRQ cleared by CPU (LBD -> 0) IRQ from ICU IRQ cleared: Begin of Input Capture IRQ from ICU IRQ cleared: Calculate & set new baud rate LBIE disable Reception enable Edge of Start bit of Identifier byte Byte read in RDR RDR read by CPU 582 CHAPTER 17 LIN-UART 17.6.4 Direct Access to Serial Pins The LIN-UART allows the direct access to the values of transmission pins (SOT) and reception pins (SIN). ■ Direct Access to LIN-UART Pins The LIN-UART provides a function to directly access to the value of the serial input/output pins by using software. Reading the SIOP bit in the ESCR enables monitoring of the serial input data. When the serial output pin direct access enable (SOPE) bit in the ESCR is set, the software can fix the output value from the SOT pin. This is possible only when the transmission shift register is empty, such as when there is no transmission activity. In the LIN mode, this function can be used to read back the data which you have transmitted. It can also be used for error handling when some physical failure exists on the single-wire LIN bus. Note: The SIOP retains the value which was written most recently. To prevent unnecessary edge output, write a value to the SIOP before configuring the access to the output pin. During the read-modify-write (RMW) instruction to the SIOP bit, the value of the SOT pin is returned. For the normal read instruction, the value of the SIN pin is returned. 583 CHAPTER 17 LIN-UART 17.6.5 Bidirectional Communication Function (Normal Mode) Operation modes 0 and 2 offer normal serial bidirectional communication. Select operation mode 0 for asynchronous communication, and operation mode 2 for synchronous communication. ■ Bidirectional Communication Function Figure 17.6-9 shows the LIN-UART settings in operation modes 0 and 2. Figure 17.6-9 LIN-UART Settings in Operation Modes 0 and 2 bit 15 14 13 12 11 P SBL CL AD CRE RXE TXE MD1 MD0 OTO EXT REST UPCL SCKE SOE Mode 0 → ❍ ❍ ❍ ❍ X 0 ❍ ❍ 0 0 X 0 0 0 1 ❍ Mode 2 → ❑ ❑ X X 0 ❍ ❍ 1 0 ❍ ❍ 0 0 ❍ ❍ SCR, SMR PEN ❑ SSR, TDR/RDR 10 9 PE ORE FRE RDRF TDRE BDS RIE 8 TIE Mode 0 → ❍ ❍ ❍ ❍ ❍ ❍ ❍ ❍ Mode 2 → ❍ ❑ ❍ ❍ ❍ ❍ ❍ ❑ ESCR, ECCR LBIE LBD LBL1 LBL0 SOPE SIOP CCO SECS 7 6 5 4 3 2 1 0 Set conversion data (during writing) Retain reception data (during reading) Reserved LBR MS SCDE SSM BIE RBI TBI Mode 0 → ❍ ❍ ❍ ❍ ❍ ❍ X X ❍ X X X ❍ ❍ ❍ Mode 2 → X X X ❍ ❍ ❍ ❍ X ❍ ❍ ❍ ❑ ❑ ❑ X ❍ : Bit used X : Bit not used 1 : Set 1 0 : Set 0 ❑ : Bit used if SSM=1 (Synchronous start-/stop-bit mode) + : Bit automatically set to correct value ■ Connection between CPUs Figure 17.6-10 shows the connection example for bidirectional communication in LIN-UART operation mode 2. Figure 17.6-10 Connection Example for Bidirectional Communication in LIN-UART Operation Mode 2 SOT SOT SIN SIN SCK CPU-1 (Master) 584 Output Input SCK CPU-2 (Slave) CHAPTER 17 LIN-UART 17.6.6 Master/Slave Communication Function (Multiprocessor Mode) In the master/slave mode, the LIN-UART communication with multiple CPUs is possible from either a master or slave system. ■ Master/Slave Communication Function Figure 17.6-11 shows the LIN-UART settings in operation mode 1. Figure 17.6-11 LIN-UART Settings in Operation Mode 1 bit 15 SCR, SMR Mode 1 → SSR, TDR/RDR 14 13 12 11 10 9 PEN P SBL CL AD CRE RXE TXE MD1 MD0 OTO EXT REST UPCL SCKE SOE + X ❍ ❍ ❍ ❍ 0 PE ORE FRE RDRF TDRE BDS RIE Mode 1 → X ❍ ❍ ❍ ❍ ❍ ❍ 8 ❍ TIE X X X X ❍ ❍ X 6 0 1 5 0 4 0 3 0 2 0 1 1 0 ❍ Set conversion data (during writing) Retain reception data (during reading) ❍ ESCR, ECCR LBIE LBD LBL1 LBL0 SOPE SIOP CCO SECS Mode 1 → 7 Reserved LBR MS SCDE SSM BIE X X X X X ❍ RBI TBI ❍ ❍ ❍ : Bit used X 1 0 + : Bit not used : Set 1 : Set 0 : Bit automatically set to correct value ■ Connection between CPUs Figure 17.6-12 shows the connection example of LIN-UART master/slave communication. The LINUART can be used for the master or slave CPU. Figure 17.6-12 Connection Example of LIN-UART Master/Slave Communication SOT SIN Master CPU SOT SIN Slave CPU #0 SOT SIN Slave CPU #1 585 CHAPTER 17 LIN-UART ■ Function Settings For the master/slave communication, set the operation mode and data transfer mode as shown in the table below: Table 17.6-3 Settings of Master/Slave Communication Functions Operation mode Data Master CPU Address transmission/ Mode 1 reception (AD bit transmission/ Data transmission/ reception) Parity Synchronization method Stop bit None Asynchronous 1 bit or 2 bits Slave CPU Mode 2 (AD bit transmission/ reception) reception AD=1 + 7-bit or 8-bit address AD=0 + 7-bit or 8-bit data Bit direction LSB first or MSB first ■ Communication Procedure When the master CPU transmits address data, communication starts. The AD bit in the address data is set to "1", and the communication target CPU is selected. Each slave CPU checks the address data. When the address data indicates the address assigned to one of the slave CPUs, the slave CPU communicates with the master CPU (normal mode). The following is a flowchart of the master/slave communication (multiprocessor mode). 586 CHAPTER 17 LIN-UART Figure 17.6-13 Flowchart of Master/Slave Communication (Master CPU) (Slave CPU) Start Start Set operation mode 1 Set operation mode 1 Set SIN pin as the serial data input pin. Set SOT pin as the serial data output pin. Set SIN pin as the serial data input pin. Set SOT pin as the serial data output pin. Set 7 or 8 data bits. Set 1 or 2 stop bits. Set 7 or 8 data bits. Set 1 or 2 stop bits. Set "1" in AD bit Set TXE = RXE = 1 Set TXE = RXE = 1 Receive Byte Send Slave Address Is AD bit = 1 ? Waiting NO YES Bus-idle Interrupt Does Slave Address match ? Set "0" in AD bit NO YES Communication with slave CPU Is communication complete? Communication with master CPU NO YES Communicate with another slave CPU? Is communication complete? NO YES NO YES Set TXE = RXE = 0 End 587 CHAPTER 17 LIN-UART 17.6.7 LIN Communication Function The LIN-UART communication with LIN devices is possible with either LIN master or LIN slave system. ■ LIN Master/Slave Communication Function Figure 17.6-14 shows the LIN-UART settings in operation mode 3 (LIN). Figure 17.6-14 LIN-UART Settings in Operation Mode 3 (LIN) bit 15 SCR, SMR 14 13 12 11 PEN P SBL CL AD CRE RXE TXE MD1 MD0 OTO EXT REST UPCL SCKE SOE + X + + Mode 3 → SSR, TDR/RDR X 10 0 9 ❍ PE ORE FRE RDRF TDRE BDS RIE Mode 3 → X ❍ ❍ ❍ ❍ + ❍ 8 ❍ TIE ❍ ❍ ❍ ❍ ❍ X 6 1 1 5 0 4 0 3 0 2 1 0 1 0 ❍ Set conversion data (during writing) Retain reception data (during reading) ❍ ESCR, ECCR LBIE LBD LBL1 LBL0 SOPE SIOP CCO SECS Mode 3 → ❍ 7 0 Reserved LBR MS SCDE SSM BIE ❍ X X X RBI TBI ❍ ❍ ❍ ❍ : Bit used X 1 0 + : Bit not used : Set 1 : Set 0 : Bit automatically set to correct value ■ LIN Device Connection Figure 17.6-15 shows the connection example of LIN bus system. The LIN-UART can be configured as either of a LIN master or a LIN slave. Figure 17.6-15 Connection Example of LIN Bus System SOT SOT LIN bus SIN LIN-Master 588 SIN Single-WireTransceiver Single-WireTransceiver LIN-Slave CHAPTER 17 LIN-UART 17.6.8 Sample Flowchart for LIN-UART in LIN Communication Mode (Operation Mode 3) This section provides the sample flowcharts for the LIN-UART in the LIN communication mode. ■ LIN-UART as a Master Device Figure 17.6-16 Flowchart for LIN-UART in LIN Master Mode START Initialization: Set Operat. mode 3 (8N1 data format) TIE = 0, RIE = 0 Send Message? NO YES Send Synch Break: write "1" to ECCR: LBR, TIE = 1; Send Sleep Mode TDR = 80H TIE = 0 Send Synch Field: TDR = 55H Wake up from CPU? YES NO Send Sleep Mode? Send Wake up signal RIE = 0 TIE = 1 TDR = 80H RIE = 1 YES NO Send Identify Field: TDR = Id Write to slave? NO TIE = 0 RIE = 1 Read data from slave RIE = 0 NO YES 00H, 80H or C0H received? TIE = 1 Write data to slave TIE = 0 YES RIE = 0 Errors occurred? NO YES Error Handler 589 CHAPTER 17 LIN-UART ■ LIN-UART as a Slave Device Figure 17.6-17 Flowchart for LIN-UART in LIN Slave Mode START A B Initialization: Set Operat. mode 3 (8N1 data format) C RIE = 0; LBIE = 1; RXE = 0 Error occurred? Slave address match? NO E NO C YES YES Master wants to send data? Waiting (slave action) LBD = 1 LIN break interrupt NO YES Awaiting message from LIN master. Write "0" to LBD to clear interrupt Enable ICU interrupt . (both edge) Receive data + check sum 80H received? (sleep mode) S (On next page) Waiting (slave action) ICU Interrupt NO RIE = 0 TIE = 1 Calculate checksum Send data TIE = 0 YES B Read ICU value and store it. Clear Interrupt. Waiting (slave action) ICU Interrupt Read ICU value. Calculate new baud rate. Set it to Reload Counter. Clear Interrupt. Waiting (slave action) Bus -idle Interrupt C Master wants to send data? NO YES C E Error handler C Receive identifier RIE = 1; RXE = 1 A (Continued) 590 CHAPTER 17 LIN-UART (Continued) S Wake up from CPU? NO Send Wake up signal RIE = 0 TIE = 1 TDR = 80H YES RIE = 1 NO 00H, 80H or C0H received? TIE = 0 YES RIE = 0 C 591 CHAPTER 17 LIN-UART 17.7 Notes on Using LIN-UART This section provides the notes on using the LIN-UART. ■ Operation Setting The LIN-UART’s serial control register (SCR) has the TXE (transmission) and RXE (reception) operation enable bits. These bits are disabled by default. Before starting transfer for either of transmission or reception operation, these bits must be enabled. The transfer can be discontinued by disabling these bits. Since a single-wire bus system such as ISO9141 (LIN bus system) offers mono-directional communication, do not enable these two bits simultaneously. The LIN-UART receives also the data sent by itself because reception is automatically performed. ■ Communication Mode Setting Set the communication mode while the system is not operating. If the operation mode is changed during transmission or reception, the transmission or reception is stopped and the data being transferred will be lost. ■ Transmission Interrupt Enable Timing The initial value of the transmission data empty flag bit (SSR: TDRE bit) is "1" (There is no transmission data, and writing of transmission data is enabled.). A transmission interrupt request is generated as soon as the transmission interrupt request is enabled (SSR: TIE bit set to "1"). To prevent this interrupt from generating, set the TIE flag to "1" after the transmission data is written to the TDR register. ■ Using LIN in Operation Mode 3 The LIN functions can also be used in mode 0 (transmission/reception break); however, using operation mode 3 sets the LIN-UART data format automatically to the LIN format (8N1, LSB first). To apply the LIN-UART to the LIN bus protocol, use operation mode 3. The transmission time of the break is changeable; however, it must be at least 11 serial bit times. ■ Changing Operation Settings Be sure to reset the LIN-UART after changing its operation settings. Carefully check the presence of the start/stop bits in mode 2 (synchronous mode), in particular. When the settings of the serial mode register (SMR) are changed, the setting of UPCL bit cannot be set at the same time to reset the LIN-UART. Otherwise, the LIN-UART may not operate properly. Set the other bits in the SMR first, and then to set the UPCL bit. ■ Setting LIN Slave To initialize the LIN-UART to use it as a LIN slave, make sure to set the baud rate before receiving the first LIN synchronization break. This is necessary for the reliable detection of the LIN synchronization break of 13 bit times at minimum. 592 CHAPTER 17 LIN-UART ■ Software Compatibility Although this LIN-UART is similar to the one included in the conventional MCU, its software is not compatible. The programming models are almost the same, but the register configuration is different. Furthermore the baud rate is now set with a reload value, not by selecting a preset value. ■ Bus Idle Function The Bus Idle function cannot be used in synchronous mode 2. ■ AD Bit in the Serial Control Register (SCR) Note the following when using the AD bit (address/data bit used in the multiprocessor mode) in the serial control register (SCR): When this bit is read, the AD bit which is received most recently is returned. When this bit is written, the AD bit during transmission is set. Consequently, the AD bit operates as both control bit and flag bit. Internally, the received data and transmission data are stored into different registers. For a read-modifywrite (RMW) instruction, the received data is read, processed, and then written as transmission data. If the bit in the same register is accessed by the same type of instruction, incorrect value may be set in the AD bit. To prevent the problem, perform the write-access to this bit before transmission. Or, set all bits correctly at the same time using byte access. Unlike transmission data register, the AD bit does not retain data. If this bit is updated during transmission operation, the AD bit of the data being transmitted is modified. 593 CHAPTER 17 LIN-UART 594 CHAPTER 18 I2C INTERFACE This chapter describes overview, register configuration/ function, and operation of the I2C interface. 18.1 I2C Interface Overview 18.2 I2C Interface Register 18.3 Explanation of I2C Interface Operation 18.4 Operation Flowchart 595 CHAPTER 18 I2C INTERFACE 18.1 I2C Interface Overview The I2C interface uses the serial I/O port for supporting the inter-IC bus to serve as the master/slave device on the I2C bus. ■ Feature of I2C Interface The feature of the I2C interface is as the following. • Transmitting and receiving of master/slave device • Arbitration • Clock synchronization • Detection of slave address/general call address • Detection of transfer direction • Function to generate/detect the iterative START condition • Detection of bus error • Supports 10-/7-bit slave address • Performs slave address receive acknowledge control in master mode • Supports composite slave address • Interrupt at transmission/bus error • Supports standard mode (max. 100 kbps) and high-speed mode (max. 400 kbps) 596 CHAPTER 18 I2C INTERFACE ■ I2C Interface Registers The registers of the I2C interface are as the following. • Bus status register (IBSR) Figure 18.1-1 Bit Configuration of Bus Status Register (IBSR) IBSR Address: 0000D1H, 0000DDH bit7 6 5 4 3 2 1 0 000369H BB RSC AL LRB TRX AAS GCA ADT Read/Write (R) (R) (R) (R) (R) (R) (R) (R) Initial value (0) (0) (0) (0) (0) (0) (0) (0) • Bus control register (IBCR) Figure 18.1-2 Bit Configuration of Bus Control Register (IBCR) IBCR Address: 0000D0H, 0000DCH bit15 000368H BER 14 13 12 11 10 9 8 BEIE SCC MSS ACK GCAA INTE INT Read/Write (R/W) (R/W) (W) (R/W) (R/W) (R/W) (R/W) (R/W) Initial value (0) (0) (0) (0) (0) (0) (0) (0) • Clock control register (ICCR) Figure 18.1-3 Bit Configuration of Clock Control Register (ICCR) ICCR Address: 0000DAH, 0000E6H bit15 14 000372H Reserved NSF 13 12 11 10 9 8 EN CS4 CS3 CS2 CS1 CS0 Read/Write (−) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Initial value (−) (0) (0) (1) (1) (1) (1) (1) 597 CHAPTER 18 I2C INTERFACE • 10-bit slave address register (ITBA) Figure 18.1-4 Bit Configuration of 10-bit Slave Address Register (ITBA) ITBAH Address: 0000D2H, 0000DEH bit15 14 13 12 11 10 00036AH Reserved Reserved Reserved Reserved Reserved Reserved 9 8 TA9 TA8 Read/Write (−) (−) (−) (−) (−) (−) (R/W) (R/W) Initial value (−) (−) (−) (−) (−) (−) (0) (0) Address: 0000D3H, 0000DFH bit7 6 5 4 3 2 1 0 00036BH TA7 TA6 TA5 TA4 TA3 TA2 TA1 TA0 Read/Write (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Initial value (0) (0) (0) (0) (0) (0) (0) (0) ITBAL • 10-bit slave address mask register (ITMK) Figure 18.1-5 Bit Configuration of 10-bit Slave Address Mask Register (ITMK) ITMKH Address: 0000D4H, 0000E0H bit15 00036CH ENTB 14 RAL 13 12 11 10 Reserved Reserved Reserved Reserved 9 8 TM9 TM8 Read/Write (R/W) (R) (−) (−) (−) (−) (R/W) (R/W) Initial value (0) (0) (−) (−) (−) (−) (1) (1) Address: 0000D5H, 0000E1H bit7 6 5 4 3 2 1 0 00036DH TM7 TM6 TM5 TM4 TM3 TM2 TM1 TM0 Read/Write (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Initial value (1) (1) (1) (1) (1) (1) (1) (1) ITMKL • 7-bit slave address register (ISBA) Figure 18.1-6 Bit Configuration of 7-bit Slave Address Register (ISBA) ISBA Address: 0000D7H, 0000E3H bit7 00036FH Reserved 598 6 5 4 3 2 1 0 SA6 SA5 SA4 SA3 SA2 SA1 SA0 Read/Write (−) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Initial value (−) (0) (0) (0) (0) (0) (0) (0) CHAPTER 18 I2C INTERFACE • 7-bit slave address mask register (ISMK) Figure 18.1-7 Bit Configuration of 7-bit Slave Address Mask Register (ISMK) ISMK Address: 0000D6H, 0000E2H bit15 00036EH ENSB 14 13 12 11 10 9 8 SM6 SM5 SM4 SM3 SM2 SM1 SM0 Read/Write (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Initial value (0) (1) (1) (1) (1) (1) (1) (1) • Data register (IDAR) Figure 18.1-8 Bit Configuration of Data Register (IDAR) IDAR Address: 0000D9H, 0000E5H bit7 6 5 4 3 2 1 0 000371H D7 D6 D5 D4 D3 D2 D1 D0 Read/Write (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Initial value (0) (0) (0) (0) (0) (0) (0) (0) 599 CHAPTER 18 I2C INTERFACE ■ Block Diagram of I2C Interface The block diagram of the I2C interface is shown in the Figure 18.1-9 . Figure 18.1-9 Block Diagram of I2C Interface ICCR EN I2C operation enable ICCR Clock division 2 2345 32 CS4 CS3 CS2 CS1 CS0 Sync Clock selection 2 (1/12) Shift clock edge change timing IB SR BB RSC Bus busy Repeat start Last bit LRB TRX Start/stop condition detection Transmitting/ receiving Error First byte ADT Arbitration lost detection AL IB CR SCLI SCLO R-bus BER BEIE Interrupt request IRQ INTE INT IB CR SCC MSS ACK GCAA End Start Mater ACK enable Start/stop condition occurrence GC-ACK enable IDAR IB SR Slave AAS Global call GCA Slave address comparison ISMK FNSB ITMK ENTB RAL ITBA 600 Shift clock generation ITMK ISBA ISMK SDA SDAO CHAPTER 18 I2C INTERFACE 18.2 I2C Interface Register This section describes the configuration and function of the register used in the I2C interface. ■ I2C Interface Register Overview I2C interface register includes the following eight types. • Bus Status Register (IBSR) • Bus Control Register (IBCR) • Clock Control Register (ICCR) • 10-bit Slave Address Register (ITBA) • 10-bit Slave Address Mask Register (ITMK) • 7-bit Slave Address Register (ISBA) • 7-bit Slave Address Mask Register (ISMK) • Data Register (IDAR) 601 CHAPTER 18 I2C INTERFACE 18.2.1 Bus Status Register (IBSR) Bus status register (IBSR) has the following functions. • Bus busy detection • Repeated START condition detection • Arbitration lost detection • Acknowledge detection • Data transfer direction display • Slave addressing detection • General call address detection • Address data transfer detection ■ Bus Status Register (IBSR) The register configuration of the bus status register (IBSR) is as the following. Figure 18.2-1 Bit Configuration of Bus Status Register (IBSR) IBSR Address: 0000D1H, 0000DDH bit7 6 5 4 3 2 1 0 000369H BB RSC AL LRB TRX AAS GCA ADT Read/Write (R) (R) (R) (R) (R) (R) (R) (R) Initial value (0) (0) (0) (0) (0) (0) (0) (0) This register is read only. All bits of the register are automatically controlled by the hardware. When I2C interface is not enabled (EN of ICCR=0), all bits of this register are cleared. [bit7] BB: Bus busy bit This bit indicates the status of the I2C bus. Table 18.2-1 BB (Bus Busy Bit) Value 602 Description 0 The STOP condition detected [Initial value] 1 The START condition detected (The bus is in use) CHAPTER 18 I2C INTERFACE [bit6] RSC: Repeated start condition bit This bit detects the iterative START condition. Table 18.2-2 RSC (Repeated Start Condition Bit) RSC Description 0 The iterative START condition not detected [Initial value] 1 The iterative START condition detected This bit is cleared when the slave address transfer ends (ADT=0) or when the STOP condition is detected. [bit5] AL: Arbitration lost detect bit This bit is used to detect arbitration lost. Table 18.2-3 AL (Arbitration Lost Detect Bit) AL Description 0 Arbitration lost not detected [Initial value] 1 Arbitration lost occurred during transmitting to master This bit is cleared when "0" is written to the INT bit or when "1" is written to the MSS bit of the IBCR register. Examples of arbitration lost: • Transmit data does not match SDA line data on SCL rising edge • Iterative START condition caused at first bit of data by another master • SCL line of I2C interface driven to "L" by another slave, so unable to generate START or STOP condition [bit4] LRB: Acknowledge store bit This bit stores an acknowledge signal from the receive side. Table 18.2-4 LRB (Acknowledge Store Bit) LRB Description 0 Slave acknowledge detected [Initial value] 1 Slave acknowledge not detected This bit is rewritten when acknowledge is detected (receive 9 bits). This bit is cleared when the START or STOP condition is detected. 603 CHAPTER 18 I2C INTERFACE [bit3] TRX: Transferring data bit This bit indicates the transmission state during data transfer. Table 18.2-5 TRX (Transferring Data Bit) TRX Description 0 Data transmission not in progress [Initial value] 1 Data transmission in progress • This bit is set to "1" in the following cases: START condition generated in master mode - Transfer of first byte ends at read access (transmission) in slave mode - Transmission in progress in master mode • This bit is set to "0" in the following cases: Bus in idle state (BB=0:IBCR) - At arbitration lost - "1" written to SCC at master interrupt (MSS=1, INT=1) - MSS bit cleared at master interrupt (MSS=1, INT=1) - No acknowledge at end of transfer in slave mode - Reception in progress in slave mode - Data receiving from slave in master mode [bit2] AAS: Slave address detect bit This bit detects the slave address. Table 18.2-6 AAS (Slave Address Detect Bit) AAS Description 0 Slave address not specified [Initial value] 1 Slave address specified This bit is cleared when the (iterative) START or STOP condition is detected. This bit is set when the 7-/10-bit slave address is detected. [bit1] GCA: General call address detect bit This bit is used to detect a general call address (00H). Table 18.2-7 GCA (General Call Address Detect Bit) GCA Description 0 Detect no general call address [Initial value] 1 Detect general call address This bit is cleared when the (iterative) START or STOP condition is detected. 604 CHAPTER 18 I2C INTERFACE [bit0] ADT: Address data transfer bit This bit is the slave address receive detect bit. Table 18.2-8 ADT (Address Data Transfer Bit) ADT Description 0 Receive data not at slave address (or bus free) [Initial value] 1 Receive data at slave address This bit is set to "1" when START is detected. When the header at the slave address is detected at 10-bit write access, this bit is cleared after the second byte; in other cases, it is cleared after the first byte. "After the first/second byte" means: • "0" is written to MSS bit during master interrupt (MSS=1, INT=1:IBCR) • "1" is written to SCC bit during master interrupt (MSS=1, INT=1:IBCR) • INT bit is cleared • Start of all transfer bytes when data not to be transferred as master/slave address 605 CHAPTER 18 I2C INTERFACE 18.2.2 Bus Control Register (IBCR) The bus control register (IBCR) has the following functions. • Interrupt enable flag • Interrupt generation flag • Bus error detection flag • Repeated START condition generation • Master/slave mode selection • General call acknowledge generation enable • Data byte acknowledge generation enable ■ Bus Control Register (IBCR) Figure 18.2-2 shows the bit configuration of bus control register (IBCR). Figure 18.2-2 Bit Configuration of Bus Control Register (IBCR) IBCR Address: 0000D0H, 0000DCH bit15 000368H BER 14 13 12 11 10 9 8 BEIE SCC MSS ACK GCAA INTE INT Read/Write (R/W) (R/W) (W) (R/W) (R/W) (R/W) (R/W) (R/W) Initial value (0) (0) (0) (0) (0) (0) (0) (0) Perform writing to the bus control register (IBCR) when INT bit is "1" or transfer is started. Do not perform writing during transferring because change of ACK bit or GCAA bit may cause detection of a bus error. When the I2C interface is not enabled (EN=0:ICCR), all bits except the BER and BEIE bits are cleared. 606 CHAPTER 18 I2C INTERFACE [bit15] BER: Bus error flag This is the bus error interrupt request flag bit. "1" is always read when this bit is read using the readmodify-write (RMW) instruction. (Writing) Table 18.2-9 BER (Bus Error Flag) BER Description 0 Bus error interrupt request flag cleared 1 No meaning (Reading) Table 18.2-10 BER (Bus Error Flag) BER Description 0 Bus error not detected [Initial value] 1 The error condition detected When this bit is set, the EN bit of the CCR register is cleared, the I2C interface is stopped, and data transfer is suspended. Also, all bits of the IBSR and IBCR registers are cleared except the BER and BEIE bits. Clear this bit before enabling (EN=1) the I2C interface again. This bit is set to "1" in the following cases: 1) START or STOP condition is detected at illegal location (during slave address transfer or data transfer). 2) In 10-bit read access, the read-access slave address header is received before making 10-bit write access to the first byte. 3) START condition is detected during transfer in master mode. In 1) and 2), when operation of the I2C interface is enabled during transfer, an illegal bus error report is prohibited, so the flag is set after reception of the first STOP condition. [bit14] BEIE: Bus error interrupt enable bit This bit enables a bus error interrupt. Table 18.2-11 BEIE (Bus Error Interrupt Enable Bit) BEIE Description 0 Bus error interrupt disabled [Initial value] 1 Bus error interrupt enabled When this bit is "1" and the BER bit is set to "1", an interrupt occurs. 607 CHAPTER 18 I2C INTERFACE [bit13] SCC: Start condition continue bit This bit continues the iterative START condition. (Writing) Table 18.2-12 SCC (Start Condition Continue Bit) SCC Description 0 No meaning 1 The iterative START condition occurs during transfer in the master mode. The read value of this bit is always "0". When "1" is written to this bit during master mode (MSS=1, INT=1), the iterative START condition occurs, clearing the INT bit automatically. [bit12] MSS: Master/slave select bit This bit selects between master and slave. Table 18.2-13 MSS (Master/Slave Select Bit) MSS Description 0 Slave mode [Initial value] 1 The master mode established, the START condition occurs, and the value of the IDAR register is transmitted as the slave address. • When arbitration lost occurs during transmission in the master mode, this bit is cleared, causing the slave mode. • When "0" is written to this bit with the master interrupt flag set (MSS=1, INT=1), the INT bit is cleared automatically, causing the STOP condition and then ending transfer. Note: The MSS bit functions as the direct reset. Occurrence of the STOP condition can be checked by referring to the BB bit of the IBSR register. • When "1" is written to this bit while the bus is idle (MSS=0, BB=0), the START condition occurs, transmitting the IDAR value. • When "1" is written to this bit while the bus is in use (BB=1, TRX=0, MSS=0), the I2C interface waits until the bus is freed, and then starts transmission. When the I2C interface is addressed during this wait as the slave involving write access, the bus is freed after transfer has ended. During this wait, when transmission is in progress as the slave (IBCR:AAS=1, TRX=1), data transmission is not performed even when the bus is freed. It is important to check whether or not the I2C interface is specified as the slave (IBSR:AAS=1), whether or not data transmission ends normally at the next interrupt (IBCR:MSS=1), and whether or not an illegal end occurs (IBSR:AL=1). Note: Under the following condition, transmission of general-call address is prohibited because it cannot be received as a slave. LSI other than MB91461/F467R exists on the bus and MB91461/F467R transmits general-call address as a master and arbitration lost occurs at second byte or later. 608 CHAPTER 18 I2C INTERFACE [bit11] ACK: Acknowledge bit This bit generates acknowledge in accordance with the data receive enable bit. Table 18.2-14 ACK (Acknowledge Bit) ACK Description 0 Acknowledge not generated in response to data reception [Initial value] 1 Acknowledge generated in response to data reception • This bit is disabled at slave address reception in the slave mode. When the I2C interface detects the 7- or 10-bit slave address designation with the corresponding enable bit (ITMK:ENTB, ISMK:ENSB) set, acknowledge is returned. • Write to this bit while the interrupt flag is set (INT=1) or while the bus is free (IBSR:BB=0), or while the I2C interface is stopped (ICCR:EN=0). [bit10] GCAA: General call address acknowledge bit This bit enables generation of an acknowledge signal when a general call address is received. Table 18.2-15 GCAA (General Call Address Acknowledge Bit) GCAA Description 0 Acknowledge not generated in response to reception of general call address [Initial value] 1 Acknowledge generated in response to reception of general call address Write to this bit while the interrupt flag is set (INT=1), or while the bus is freed (IBSR:BB=0), or while the I2C interface is stopped (ICCR:EN=0). • When the general call address is received, setting both this bit and ACK bit to "1" enable the acknowledge response generation. • When the general call address is transmitted, setting this bit to "1" enable the acknowledge response generation. • With data received by slave receiving (including the case in which the arbitration lost occurs after transmission of general call address as master), acknowledge bit output is enabled when both ACK bit and this bit are "1". • Do not change the setting of this bit when GCA bit of the bus status register (IBSR) is "1". [bit9] INTE: Interrupt enable bit This bit enables an interrupt. Table 18.2-16 INTE (Interrupt Enable Bit) INTE Description 0 Interrupt disabled [Initial value] 1 Interrupt enabled When the INT bit is "1" and this bit is "1", an interrupt is generated. 609 CHAPTER 18 I2C INTERFACE [bit8] INT: Interrupt request flag This is a transfer end interrupt request flag bit. "1" is always read when this bit is read using the readmodify-write (RMW) instruction. (Writing) Table 18.2-17 INT (Interrupt Request Flag) INT Description 0 The transfer end interrupt request flag is cleared. [Initial value] 1 No meaning (Reading) Table 18.2-18 INT (Interrupt Request Flag) INT Description 0 Transfer has not ended or data is not to be transferred, or the bus is freed. [Initial value] 1 This bit is set when the following conditions are met at completion of 1 byte transfer including the acknowledge bit: • Bus master • The address is specified as a slave address • General call address received • Arbitration lost When the address is specified as a slave address, this bit is set at the end of slave address reception containing acknowledge. When this bit is "1", the SCL line is kept "L" level. When "0" is written to this bit, it is cleared, the SCL line is freed, the next byte is transferred, and the iterative START or STOP condition is generated. This bit is cleared when "1" is written to the SCC bit or to the MSS bit. Notes: At conflict between SCC, MSS, and INT bits: When write to the SCC, MSS, and INT bits occurs simultaneously, a conflict occurs between: transfer of the next byte, occurrence of the iterative START condition, and occurrence of the STOP condition. The priority at this time is shown below. • Transfer of next byte and occurrence of STOP condition When "0" is written to the INT bit and to the MSS bit, write to the MSS bit is prior to write to the INT bit, generating the STOP condition. • Transfer of next byte and occurrence of START condition When "0" is written to the INT bit and "1" is written to the SCC bit, writing to the SCC bit is prior to writing to the INT bit, generating the iterative START condition and transmitting the IDAR value. • Occurrence of iterative START condition and occurrence of STOP condition When "1" is written to the SCC bit and "0" is written to the MSS bit, clearing of the MSS bit is prior to writing to the SCC bit, generating the STOP condition and enabling the I2C interface in the slave mode. 610 CHAPTER 18 I2C INTERFACE Regarding the timing shown in Figure 18.2-3 and Figure 18.2-4 , when the command causing generation of the START condition is executed (MSS=1:IBCR), interrupt (INT=1:IBCR) caused by the arbitration lost detect (AL=1:IBSR) does not occur. • Conditions for no occurrence of interrupt caused by arbitration lost detect (1) With the START condition not detected (BB=0:IBSR), the command causing generation of the START condition is executed (MSS=1:IBCR) when the level of SDA pin or SCL pin is "L". Figure 18.2-3 Timing Diagram for No Occurrence of Interrupt Caused by Arbitration Lost Detect SCL pin or SDA pin is "L" level. SCL pin SDA pin "L" "L" 2 I C operation enable state(EN bit=1) 1 Master mode setting (MSS=1) Arbitration lost detect (AL bit=1) Bus busy (BB bit) 0 Interrupt (INT bit) 0 611 CHAPTER 18 I2C INTERFACE • Conditions for no occurrence of interrupt caused by arbitration lost detect (2) With the I2C bus occupied by the other master, I2C operation is enabled (EN=1:ICCR) and the command causing generation of the START condition is executed (MSS=1:IBCR). As shown in Figure 18.2-4 , if the other master of I2C bus begins transmission when I2C operation is disabled (EN=0:ICCR), the START condition is not detected (BB=0:IBSR) with I2C bus occupied. Figure 18.2-4 Timing Diagram for No Occurrence of Interrupt Caused by Arbitration Lost Detect Start Condition INT bit interrupt does not occur at 9th clock. Stop Condition SCL pin SDA pin SLAVE ADDRESS ACK DATA ACK EN bit MSS bit AL bit BB bit 0 INT bit 0 If these may occur, the following procedure needs to be executed on a software. 1) Execute a command causing generation of the START condition (MSS=1:IBCR). 2) Wait for 3-bit data transmission at the I2C transfer frequency set in ICCR by using timer function or other. (*) Example: I2C transfer frequency = 100 kHz 3-bit data transmission time = {1 / (100 ¥ 103)} ¥ 3 = 30 ms (*): If the arbitration lost is detected, AL will be "1" after the 3-bit data transmission at the I2C transfer frequency subsequent to MSS bit setting. 3) Check AL bit and BB bit of IBSR. If AL is "1" and BB is "0", initialize I2C by setting EN bit of ICCR to "0". If state of AL bit and BB bit is other than above, execute the normal process. 612 CHAPTER 18 I2C INTERFACE A flow example is shown below. Master mode setting Set MSS bit of the bus control register (IBCR) to "1" Wait for 3-bit data transmission at the I2C transfer frequency set in the clock control register (ICCR). NO BB=0 and AL=1 YES Set EN bit and initialize I2C Normal process • Occurrence of interrupt caused by arbitration lost detect With the bus busy detected (BB=1:IBSR), if a command causing generation of the START condition is executed (MSS=1:IBCR) and the arbitration lost is performed, INT will be "1" when AL=1 is detected and interrupt will occur. Figure 18.2-5 Occurrence of Interrupt Caused by Arbitration Lost Detect Interrupt occurs at 9th clock. Start Condition SCL pin SDA pin SLAVE ADDRESS ACK DATA EN bit MSS bit AL bit AL bit cleared by software BB bit INT bit cleared by software and SCL freed INT bit 613 CHAPTER 18 I2C INTERFACE 18.2.3 Clock Control Register (ICCR) The clock control register (ICCR) has the following functions. • Noise filter enable • I2C interface operation enable • Serial clock frequency set ■ Clock Control Register (ICCR) Figure 18.2-6 shows the bit configuration of the clock control register (ICCR). Figure 18.2-6 Bit Configuration of Clock Control Register (ICCR) ICCR Address: 0000DAH, 0000E6H bit15 000372H Reserved 14 13 12 11 10 9 8 NSF EN CS4 CS3 CS2 CS1 CS0 Read/Write (−) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Initial value (−) (0) (0) (1) (1) (1) (1) (1) [bit15] Reserved: Reserved bit Always read value of this bit is "0". [bit14] NSF: Noise filter enable bit This bit enables the noise filter placed on SDA pin and SCL pin. This noise filter suppresses input spikes (CLKP 1 to CLKP 1.5 cycle). When the transmit/receive rate is 100 kbps or faster, set this bit to "1". [bit13] EN: Operation enable bit This bit enables the operation of the I2C interface. Table 18.2-19 EN (Operation Enable Bit) Value Description 0 Operation disabled [Initial value] 1 Operation enabled Notes: • When the operation of the I2C interface is prohibited, transmission/reception is stopped at once. • Please prohibit operating after confirming the generation of the stop condition (IBSR:BB=0) when you prohibit the operation of the I2C interface after "0" is written in the MSS bit and the stop condition is generated (ICCR:EN=0). 614 CHAPTER 18 I2C INTERFACE [bit12 to bit8] CS4 to CS0: Clock period select bit These bits set the serial clock frequency. These bits can be written to only when operation of the I2C interface is disabled (EN=0) or when the EN bit is cleared. The shift clock frequency (fsck) is set by the following expression: [Noise filter disabled] φ fsck = n × 12+18 N>0 φ : Peripheral clock (=CLKP) N>0 φ : Peripheral clock (=CLKP) (+1) means uncertainty of noise filter [Noise filter enabled] φ fsck = n × 12+19(+1) Table 18.2-20 Register Setting N CS4 CS3 CS2 CS1 CS0 1 0 0 0 0 1 2 0 0 0 1 0 3 0 0 0 1 1 ··· ··· ··· ··· ··· ··· 31 1 1 1 1 1 Setting of CS4 to CS0=00000B is disabled. 615 CHAPTER 18 I2C INTERFACE 18.2.4 10-bit Slave Address Register (ITBA) This section describes configuration and function of the 10-bit slave address register (ITBA). ■ 10-bit Slave Address Register (ITBA) Figure 18.2-7 shows the bit configuration of the 10-bit slave address register (ITBA) is as the following. Figure 18.2-7 Bit Configuration of 10-bit Slave Address Register (ITBA) ITBAH Address: 0000D2H, 0000DEH bit15 14 13 12 11 10 00036AH Reserved Reserved Reserved Reserved Reserved Reserved 9 8 TA9 TA8 Read/Write (−) (−) (−) (−) (−) (−) (R/W) (R/W) Initial value (−) (−) (−) (−) (−) (−) (0) (0) Address: 0000D3H, 0000DFH bit7 6 5 4 3 2 1 0 00036BH TA7 TA6 TA5 TA4 TA3 TA2 TA1 TA0 Read/Write (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Initial value (0) (0) (0) (0) (0) (0) (0) (0) ITBAL Perform writing to the 10-bit slave address register (ITBA) when the I2C interface is disabled (EN=0:ICCR). [bit15 to bit10] Reserved: Reserved bits "0" is always read from these bits. [bit9 to bit0] TA9 to TA0: 10-bit slave address bit When a slave address is received in the slave mode with the 10-bit address enabled (ITMK:ENTB=1), the received address and ITBA are compared. Acknowledge is transmitted to the master after the address header at the 10-bit write access is received. The first/second byte (receive data) compares with the ITBAL register. When a match is detected, the acknowledge signal is transmitted to the master device, setting the AAS bit. The I2C interface responds to reception of the address header at the 10-bit read access after occurrence of the iterative START condition. All the bits of the slave address are masked by the ITMK setting. The receive slave address is overwritten by the ITBA register. This register (ITBA register) is enabled only when AAS (IBSR register) is "1". 616 CHAPTER 18 I2C INTERFACE 18.2.5 10-bit Slave Address Mask Register (ITMK) This section describes configuration and function of the 10-bit slave address mask register (ITMK) . ■ 10-bit Slave Address Mask Register (ITMK) Figure 18.2-8 shows the bit configuration of the 10-bit slave address mask register (ITMK). Figure 18.2-8 Bit Configuration of 10-bit Slave Address Mask Register (ITMK) ITMKH Address: 0000D4H, 0000E0H bit15 00036CH ENTB 14 RAL 13 12 11 10 Reserved Reserved Reserved Reserved 9 8 TM9 TM8 Read/Write (R/W) (R) (−) (−) (−) (−) (R/W) (R/W) Initial value (0) (0) (−) (−) (−) (−) (1) (1) Address: 0000D5H, 0000E1H bit7 6 5 4 3 2 1 0 00036DH TM7 TM6 TM5 TM4 TM3 TM2 TM1 TM0 Read/Write (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Initial value (1) (1) (1) (1) (1) (1) (1) (1) ITMKL [bit15] ENTB: 10-bit slave address enable bit This bit enables the 10-bit slave address operation. Write to this bit when the I2C interface is stopped (ICCR:EN=0). [bit14] RAL: Slave address length bit This bit indicates the slave address length. This bit can be used to determine which transfer length (10 bits or 7 bits) will be enabled when both the 10-bit slave address operation enable bit and the 7-bit slave address operation enable bit are enabled (ENTB=1 and ENSB=1). This bit is enabled when the AAS bit (IBSR) is "1". This bit is cleared when operation of the interface is disabled (ICCR:EN=0). This bit is read only. [bit13 to bit10] Reserved: Reserved bit "1" is always read from these bits. 617 CHAPTER 18 I2C INTERFACE [bit9 to bit0] TM9 to TM0: 10-bit slave address mask bit These bits mask bits of the 10-bit slave address register (ITBA). Write to this register when operation of the I2C interface is disabled (ICCR:EN=0). Setting these bits makes it possible to transmit acknowledge to the composite 10-bit slave address. Set these bits to "1" when using this register at comparison of the 10-bit slave address. The received slave address is overwritten by ITBA. When ASS=1 (IBSR), the specified slave address can be identified by reading the ITBA register. Each bit (TM9 to TM0) of ITMK corresponds to each bit of the ITBA address. When the value of TM9 to TM0 is "1", the ITBA address is enabled; when the value of TM9 to TM0 is "0", the ITBA address is disabled. Example: When ITBA address = 0010010111B and ITMK address = 1111111100B, the slave address area is "0010010100B" to "0010010111B". 618 CHAPTER 18 I2C INTERFACE 18.2.6 7-bit Slave Address Register (ISBA) This section describes configuration and function of the 7-bit slave address register (ISBA). ■ 7-bit Slave Address Register (ISBA) Figure 18.2-9 shows the bit configuration of the 7-bit slave address register (ISBA). Figure 18.2-9 Bit Configuration of 7-bit Slave Address Register (ISBA) ISBA Address: 0000D7H, 0000E3H bit7 00036FH Reserved 6 5 4 3 2 1 0 SA6 SA5 SA4 SA3 SA2 SA1 SA0 Read/Write (−) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Initial value (−) (0) (0) (0) (0) (0) (0) (0) Perform writing to the 7-bit slave address register (ISBA) when the I2C interface is disabled (EN=0:ICCR). [bit7] Reserved: Reserved bit "0" is always read from this bit. [bit6 to bit0] SA6 to SA0: Slave address bit When 7-bit slave address is already enabled (ISMK:ENSB=1) when a slave address is received in the slave mode, the received slave address and ISBA are compared. When a slave address match is detected, acknowledge is transmitted to the master, setting the AAS bit. The I2C interface returns acknowledge in response to reception of the address header at the 7-bit read access after the occurrence of the iterative START condition. All the bits of the slave address are masked by the ISMK setting. The receive slave address is overwritten by the ISBA register. This register is enabled only when the AAS register (IBSR register) is "1". The I2C interface does not compare ISBA with the receive slave address when the 10-bit slave address is specified or the general call is received. 619 CHAPTER 18 I2C INTERFACE 18.2.7 7-bit Slave Address Mask Register (ISMK) The 7-bit slave address mask register (ISMK) includes the 7-bit slave address mask and the 7-bit slave address enable bit. ■ 7-bit Slave Address Mask Register (ISMK) Figure 18.2-10 shows the bit configuration of the 7-bit slave address mask register (ISMK). Figure 18.2-10 Bit Configuration of 7-bit Slave Address Mask Register (ISMK) ISMK Address: 0000D6H, 0000E2H bit15 00036EH ENSB 14 13 12 11 10 9 8 SM6 SM5 SM4 SM3 SM2 SM1 SM0 Read/Write (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Initial value (0) (1) (1) (1) (1) (1) (1) (1) Perform writing to the 7-bit slave address mask register (ISMK) when the I2C interface is disabled (EN=0:ICCR). [bit15] ENSB: 7-bit slave address enable bit This is the 7-bit slave address operation enable bit. [bit14 to bit8] SM6 to SM0: 7-bit slave address mask bit These bits mask the bits of the 7-bit slave address register (ISBA). Setting these bits makes it possible to transmit acknowledge to the composite 7-bit slave address. When using this register at comparison of the 7-bit slave address, set these bits to "1". The received slave address is overwritten by ISBA. When ASS=1 (IBSR), the specified slave address can be identified by reading the ISBA register. After the I2C interface is enabled, the slave address (ISBA) is rewritten by the reception operation; when the slave address is rewritten by ISMK, operation may not be as expected unless ISMK is re-set. Each bit (SM6 to SM0) of ISMK corresponds to each bit of the ISBA address. When the value of SM6 to SM0 is "1", the ISBA address is enabled; when the value of SM6 to SM0 is "0", the ISBA address is disabled. Example: When ISBA address = 0010111B and ISMK address =1111100B, the slave address area is "0010100B" to "0010111B". 620 CHAPTER 18 I2C INTERFACE 18.2.8 Data Register (IDAR) This section describes the data register (IDAR). ■ Data Register (IDAR) Figure 18.2-11 shows the bit configuration of the data register (IDAR). Figure 18.2-11 Bit Configuration of Data Register (IDAR) IDAR Address: 0000D9H, 0000E5H bit7 6 5 4 3 2 1 0 000371H D7 D6 D5 D4 D3 D2 D1 D0 Read/Write (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Initial value (0) (0) (0) (0) (0) (0) (0) (0) [bit7 to bit0] D7 to D0: Data bit The data register (IDAR) is used for serial transfer. This register is transferred from MSB. The write side of the IDAR register has a double buffer. When the bus is busy (BB=1), write data is loaded into the register for serial transfer. When the INT bit (IBCR) is cleared or when the bus is idle (IBSR:BB=0), transfer data is loaded into the internal transfer register. At reading, the register for serial transfer is read directly, so receive data is valid only when the INT bit (IBCR) is set. 621 CHAPTER 18 I2C INTERFACE 18.3 Explanation of I2C Interface Operation The I2C bus is a bidirectional bus with one serial data line (SDA) and one serial clock line (SCL). The I2C interface has two open-drain I/O pins (SDA and SCL) to provide wired logic. ■ START Condition When "1" is written to the MSS bit with the bus free (BB=0, MSS=0), the I2C interface enters into the master mode, generating the START condition. At this time, it transmits the value of the IDAR register as the slave address. When "1" is written to the SCC bit, with the bus master mode enabled and with the interrupt flag set (IBCR:MSS=1, INT=1), the iterative START condition is generated. When "1" is written to the MSS bit with the bus in use (IBSR:BB=1, TRX=0, MSS=0 or IBCR:INT=0), the bus is freed and transmission is started. When write (reception) access is made in the slave mode, transfer ends, the bus is freed and transmission starts. When the interface is transmitting data at this time, transmission does not occur even when the bus is freed. The interface must be checked for the following: • Whether or not the interface is specified as the slave (IBCR:MSS=0, IBSR:AAS=1) • Whether or not the data byte can be transmitted normally at the next interrupt (IBSR:AL=1) ■ STOP Condition When "0" is written to the MSS bit, with the master mode in effect (IBCR:MSS=1, INT=1), the STOP condition is generated, making a transition to the slave mode. When "0" is written to the MSS bit under other conditions, the write is ignored. An attempt is made to generate the STOP condition after the MSS bit is cleared. When the SCL line is driven to "L" before generating the STOP condition, the STOP condition is not generated. An interrupt is generated after the next byte is transferred. Note: It takes some time from when "0" is written to the MSS bit until the STOP condition is generated. When operation of the I2C interface is disabled (ICCR:EN=0) before generating the START condition, the I2C interface stops immediately, generating illegal clocks in the SCL line. When disabling operation of the I2C interface (ICCR:EN=0), do so after ensuring that the START condition is generated (IBSR:BB=0). 622 CHAPTER 18 I2C INTERFACE ■ Slave Address Detection In the slave mode, the START condition is generated and then BB is set to "1", transmitting the data from the master to the IDAR register. [When 7-bit slave address operation enabled] (ENSB=1 in ISMK) After reception of 8-bit data, the IDAR register and the ISBA register are compared. At comparison, each bit of the ISBA register is masked by the ISMK register. When a match occurs, AAS is set to "1", transmitting an acknowledge to the master. After this, bit0 of the receive data (bit0 of IDAR register after reception) is reversed and then stored in the TRX bit. [When 10-bit slave address operation enabled] (ENTB=1 in ITMK) When the 10-bit address header section (11110B, TA1, TA0, write) is detected, an acknowledge is transmitting to the master, and bit0 of the receive data is reversed and then stored in the TRX bit. No interrupt occurs at this time. Then, the next transfer data and ITBA register low-order data are compared. At this comparison, each bit of the ITBA register is masked by the ISMK register. When a match occurs, AAS is set to "1", sending an acknowledge to the master. An interrupt occurs at this time. When the value is specified as a slave address and the iterative START condition is detected, the 10-bit address header section (11110B, TA1, TA0, read) is received and then "1" is set at AAS, generating an interrupt. There are 10-bit slave address register (ITBA) and 7-bit slave address register (ISBA). An acknowledge can be transmitted to the 10-bit and 7-bit addresses by enabling both the 10-bit slave address operation and the 7-bit slave address operation (ENSB=1 in ISMK, ENTB=1 in ITMK). In the slave mode (AAS=1), the receive slave address length is determined by the RAL bit of the ITMK register. In the master mode, it is possible not to generate slave addresses in the I2C interface by disabling operation of both (ISMK:ENSB=0, ITMK:ENTB=0). All slave addresses can be masked by setting the ITMK and ISMK registers. 623 CHAPTER 18 I2C INTERFACE ■ Slave Address Mask The slave address mask register (ITMK, ISMK) can mask each bit of the slave address register. Bits that are set to "1" by the mask register are subject to address comparison, but bits that are set to "0" are ignored. In the slave mode (IBSR:AAS=1), receive slave addresses can be read from ITBA (10-bit address) and ISBA (7-bit address). When the bit mask is cleared, the slave address register can always be accessed as a slave, so it can be used as a bus monitor. Note: Even if there are no other slave devices, the slave address register returns an acknowledge when a slave address is received, so the slave address register cannot be used as a real bus monitor. ■ Slave Addressing In the master mode, after a START condition is generated, the BB bit and TRX bit are set to "1" and the value in the IDAR register is output from MSB first. When an acknowledge signal is received from the slave after address data is transmitted, bit0 (of the IDAR register after transmitting data) of transmit data is inverted and stored in the TRX bit. This operation is also performed under the iterative START condition. Since the address is a 10-bit slave address write, 2 bytes are transmitted. The first byte is the header "1 1 1 1 0 A9 A8 0" indicating a 10-bit sequence; the second byte is the slave address low-order 8 bits (A7 to A0). The 10-bit slave address read transmits the above bytes, generating the iterative START condition and the header "1 1 1 1 0 A9 A8 1" indicating read access simultaneously. ■ Arbitration Arbitration occurs when one master and another master are transmitting data at the same time. When the transmit data is "1" and data on the SDA line is Low, arbitration is regarded as having been lost and the AL bit is set to "1". At the first bit of data, when an unnecessary START condition is detected or generation of the START condition or STOP condition fails, AL is set to "1". When arbitration lost occurs, MSS=0 and TRX=0 will occur, enabling the slave receive mode in which an acknowledge is returned when the own slave address of the interface is received. 624 CHAPTER 18 I2C INTERFACE ■ Acknowledge An acknowledge is transmitted to the transmitting side by the receiving side. At data reception, the ACK bit (IBCR) can be used to select whether or not to transmit an acknowledge at reception. Even when an acknowledge is not returned from the master at slave-mode data transmission (read access from another master), the TRX bit is set to "0", enabling the receive mode. Then, when the slave frees the SCL line, the master can generate the STOP condition. In the master mode, whether or not acknowledge is returned can be checked by reading the LRB bit (IBSR). If an arbitration lost occurs after transmission of the general call address, set both ACK bit and GCAA bit to "1" when performing the acknowledge response at receiving data (including generated data). With other setting, the acknowledge response is not performed. ■ Bus Error A bus error is regarded as having occurred when the following conditions are met, and the I2C interface is set in the stopped state. • A violation of the basic regulations is detected on the I2C bus during data transfer (including ACK bit). • A STOP condition in the master mode is detected. • A violation of the basic regulations is detected on the I2C bus when the bus is idle. ■ Communication Error Not Causing Error When, an illegal clock is generated in the SCL line due to noise, etc., during master mode transmission, the transmit bit counter of the I2C interface advances fast and may cause a hang-up with "L" set at the SDA line at the ACK cycle. No error (AL=1,BER=1) occurs for this illegal clock. In this case, perform error handling as follows: • When LRB is "1", with MSS set to "1", TRX set to "1", and INT set to "1", determine that a communication error has occurred. • Set EN to "0" and then to "1"; SCL will generate one pseudo-clock. This causes the slave to free the bus. The period from when EN is set to "0" until it is set to "1" should be the period during which the slave can recognize the clock (approximately same as the "H" period of the transmit clock). • When EN is "0", IBSR and IBCR are cleared, so perform retransmission processing under the START condition. At this time, no STOP condition is generated by BSS=0. Then, secure a period of "n × 7 × tCPP" or more from when EN is set to "1" until MSS is set to "1" (START condition). Example: For high-speed mode: 6 × 7 × 40 ≅ 2.333 µs For standard mode: 27 × 7 × 40 ≅ 10.50 µs (CLKP=18 MHz) Note: When BER is set, clear does not occur due to EN=0, so perform clear and then retransmission. 625 CHAPTER 18 I2C INTERFACE ■ Others • After arbitration lost has occurred, whether or not the interface is addressed must be determined via software. When arbitration lost has occurred, the interface is set as a slave via hardware, but after completion of 1byte transfer, both the CLK line and the DATA line are driven to "L". Consequently, if the interface is not addressed, the CLK line and the DATA line must be freed immediately; if the interface is addressed, preparations for slave transmission or for slave reception must be made and then the CLK line and the DATA line must be freed. (These processes must be performed via software.) • The I2C bus has only one interrupt; so when an interrupt condition is satisfied at completion of 1-byte transfer, an interrupt factor occurs. Since two or more interrupt conditions must be determined using one interrupt, each flag must be checked within the interrupt routine. The interrupt conditions at completion of 1-byte transfer are given below. - When bus master - When slave addressed - When general call address received - When arbitration lost occurred • When arbitration lost is detected, an interrupt factor does not occur immediately; it occurs at completion of 1-byte transfer. When arbitration lost is detected, the interface is set as a slave by hardware but an interrupt factor still occurs, outputting a total of 9 clocks. Since an interrupt factor does not occur immediately arbitration lost, processing cannot be performed immediately after arbitration lost. 626 CHAPTER 18 I2C INTERFACE 18.4 Operation Flowchart This section shows the operation flowchart. The shown examples include slave address and data transfer, and receive data. ■ Example of Slave Address and Data Transfer Figure 18.4-1 shows the example of slave address and data transfer. Figure 18.4-1 Example of Slave Address and Data Transfer 7-bit slave addressing Transfer data Start Start Clear (or set) BER bit. Enable interface operation (EN=1). Slave address for write access IDAR=S; address << 1+RW IDAR=byte data MSS=1 INT=0 INT=0 NO NO INT=1? INT=1? YES YES YES YES BER=1? NO AL=1? Bus error BER=1? NO YES Perform reactivation/transfer via AAS checking. AL=1? NO NO ACK? (LRB=0?) YES Perform reactivation/transfer via AAS checking. NO ACK? (LRB=0?) YES NO YES Prepare for data transfer. Transfer of last byte YES NO Completion of trans t ansfer: · Slave does not generate ACK or master cannot receive ACK. · Set EN to "0" and then perform retransmission. Completion of trans t ansfer: · Generate iterative START and STOP conditions. · Check occurrence of STOP condition (BB=0) and then set EN to "0". Completion of trans t ansfer: At transmission: · Slave does not generate ACK or master cannot receive ACK. · Set EN to "0" and then perform retransmission. At reception: ACK not generated; generate the iterative START and STOP conditions. 627 CHAPTER 18 I2C INTERFACE ■ Example of Receive Data Figure 18.4-2 shows the example of receive data. Figure 18.4-2 Example of Receive Data Start Slave address of read access When the data is the last read data from the slave, clear the ACK bit. INT=0 NO INT=1? YES YES BER=1? Bus error; perform reactivation. NO NO Transfer of the last byte YES Completion of transfer: Generate the iterative START and STOP conditions. 628 CHAPTER 18 I2C INTERFACE ■ Interrupt Handling Figure 18.4-3 shows the interrupt handling. Figure 18.4-3 Interrupt Handling Start NO Receive interrupt from other modules INT=1? YES BER=1? YES Bus error; perform reactivation. NO YES GCA=1? NO NO Transfer failed; retry. Detect general call during slave mode. YES AAS=1? YES AL=1? AL=1? YES Arbitration lost; perform transfer again. NO NO YES LRB=1? YES ADT=1? Start new data transfer at next interrupt; if necessary, change ACK bit. No slave ACK; generate STOP and iterative START conditions. NO YES NO TRX=1? YES NO TRX=1? NO Read receive data from IDAR. if necessary, Change ACK bit. Write next transmit data to IDAR. Read receive data from IDAR. If necessary, change ACK bit. Write next transmit data to IDAR or clear MSS bit. Clear INT bit. Completion of ISR 629 CHAPTER 18 I2C INTERFACE 630 CHAPTER 19 16-BIT RELOAD TIMER This chapter describes the 16-bit reload timer, the configuration and functions of registers, and 16-bit reload timer operation. 19.1 Overview of the 16-bit Reload Timer 19.2 16-bit Reload Timer Registers 19.3 16-bit Reload Timer Operation 631 CHAPTER 19 16-BIT RELOAD TIMER 19.1 Overview of the 16-bit Reload Timer The 16-bit reload timer consists of a 16-bit down counter, a 16-bit reload register, a prescaler for creating an internal count clock, and a control register. ■ Overview of the 16-bit Reload Timer (RLT) The 16-bit reload timer consists of a 16-bit down counter, a 16-bit reload register, a prescaler for creating an internal count clock, and a control register. This device has 5 channels of 16-bit reload timers (RLT0 to RLT3, RLT7). One of them (RLT7) can be used for A/D convert trigger. The clock source can be selected from three internal clocks (resource clock divided by 2, 8, and 32) and an external event (An external event cannot be selected for only RLT7). ■ Block Diagram of 16-bit Reload Timer Figure 19.1-1 shows the block diagram of the 16-bit reload timer. Figure 19.1-1 Block Diagram of the 16-bit Reload Timer 16-bit reload register (TMRLR) Reload R-bus 16-bit down counter (THR) RELD UF OUTL OUT CTL Count enable INTE UF CNTE IRQ TRG Clock selector CSL1 CSL0 EXCK Prescaler φ 632 Prescaler clear External timer output IN CTL CSL1 CSL0 TOE0 to TOE3 External trigger selection Bits in PFRK External trigger input CHAPTER 19 16-BIT RELOAD TIMER 19.2 16-bit Reload Timer Registers This section describes the configuration and functions of registers used by the 16-bit reload timer. ■ 16-bit Reload Timer Registers Figure 19.2-1 16-bit Reload Timer Registers TMCSR (Upper) 14 13 12 Address: 0001B6H, 0001BEH bit15 0001C6H, 0001CEH Reserved Reserved Reserved Reserved 0001EEH 11 10 9 8 CL1 CSL0 MOD2 MOD1 Read/Write (−) (−) (−) (−) (R/W) (R/W) (R/W) (R/W) Initial value (−) (−) (−) (−) (0) (0) (0) (0) 4 3 2 1 0 RELD INTE UF CNTE TRG TMCSR (Lower) 6 5 Address: 0001B7H, 0001BFH bit7 0001C7H, 0001CFH MOD0 Reserved OUTL 0001EFH Read/Write (R/W) (R) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Initial value (0) (0) (0) (0) (0) (0) (0) (0) TMR Address: 0001B2H, 0001BAH bit15 0001C2H, 0001CAH 0001EAH 0 Read/Write (R) Initial value (xxxxH) TMRLR Address: 0001B0H, 0001B8H bit15 0001C0H, 0001C8H 0001E8H 0 Read/Write (W) Initial value (xxxxH) 633 CHAPTER 19 16-BIT RELOAD TIMER 19.2.1 Control Status Register (TMCSR) The control status register (TMCSR) controls the 16-bit timer operating modes and interrupts. ■ Bit Configuration of the Control Status Register (TMCSR) Figure 19.2-2 Bit Configuration of the Control Status Register (TMCSR) TMCSR (Upper) 14 13 12 11 Address: 0001B6H, 0001BEH bit15 0001C6H, 0001CEH Reserved Reserved Reserved Reserved CSL1 0001EEH 10 9 8 CSL0 MOD2 MOD1 Read/Write (−) (−) (−) (−) (R/W) (R/W) (R/W) (R/W) Initial value (−) (−) (−) (−) (0) (0) (0) (0) 4 3 2 1 0 RELD INTE UF CNTE TRG TMCSR (Lower) 6 5 Address: 0001B7H, 0001BFH bit7 0001C7H, 0001CFH MOD0 Reserved OUTL 0001EFH Read/Write (R/W) (R) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Initial value (0) (0) (0) (0) (0) (0) (0) (0) [bit15 to bit12] Reserved: Reserved bit These bits are reserved. In a read operation, "0000B" is always read. 634 CHAPTER 19 16-BIT RELOAD TIMER [bit11, bit10] CSL1, CSL0: Count source select bit These bits are the count source select bits. Either an internal clock or an external event can be selected as the count source. The following table lists the count sources that can be selected using these bits. An external event cannot be selected for only RLT7. Set other than CSL1=CSL0=1. Table 19.2-1 CSL1, CSL0 (Count Source Select Bit) Count source (φ: Resource clock) φ=18 MHz φ=9 MHz φ/21 [Initial value] 0.11 µs 0.22 µs Internal clock φ/23 0.44 µs 0.89 µs 0 Internal clock φ/25 1.78 µs 3.56 µs 1 External event − − CSL1 CSL0 0 0 Internal clock 0 1 1 1 Countable edges used when an external event is the count source are set using the MOD1 and MOD0 bits. The minimum pulse width required for an external clock is 2 × T (T: peripheral clock machine cycle). [bit9, bit8, bit7] MOD2, MOD1, MOD0: Mode bit These bits set the operating modes. These bits have different functions if the count source is an internal clock or an external clock. • Internal clock: Reload trigger setting • External clock: Count valid edge setting Be sure to set "0" for MOD2. [Reload trigger setting used when an internal clock is selected] If the selected count source is an internal clock and a valid edge is input according to the setting of the MOD2, MOD1, and MOD0 bits, the contents of the reload register are loaded, and the count operation is continued. There is no external trigger pin for RLT7, so always set MOD[2:0] = 000B (software trigger). Table 19.2-2 MOD2, MOD1, MOD0 (Mode Bit) MOD2 MOD1 MOD0 Valid edge 0 0 0 Software trigger [initial value] 0 0 1 External trigger (rising edge) 0 1 0 External trigger (falling edge) 0 1 1 External trigger (both edges) 1 X X Setting disabled 635 CHAPTER 19 16-BIT RELOAD TIMER [Valid edge setting used when an external clock is selected] If the selected count source is an external event and a valid edge is input according to the setting of the MOD2, MOD1, and MOD0 bits, events are counted. Table 19.2-3 MOD2, MOD1, MOD0 (Mode Bit) MOD2 MOD1 MOD0 Valid edge X 0 0 − [Initial value] X 0 1 External trigger (rising edge) X 1 0 External trigger (falling edge) X 1 1 External trigger (both edges) Reloading during an external event occurs for an underflow and a software trigger. [bit6] Reserved: Reserved bit This bit is reserved. In a read operation, "0" is always read. [bit5] OUTL: Output level This bit sets the external timer output level. The output level is reversed depending on whether this bit is "0" or "1". The timer output of RLT7, which has no external output pin, is connected to A/D converter. When RLT7 is selected as A/D convert trigger, the A/D converter starts to convert using the rising edge of the timer output as the trigger. See the after-mentioned notice. 636 CHAPTER 19 16-BIT RELOAD TIMER [bit4] RELD: Reload enable bit This bit is the reload enable bit. When it is set to "1", reload mode is started. As soon as the counter value underflows from "0000H" to "FFFFH", the contents of the reload register are loaded into the counter, and the count operation is continued. When this bit is set to "0", one-shot mode is started. As soon as the counter value underflows from "0000H" to "FFFFH", counter operation stops. Table 19.2-4 RELD (Reload Enable Bit) PFRxy OUTL RELD 0 X X Output disabled [initial state] 0 "H" level square wave during counting • Count stop: "L" • Count in process: "H" • Underflow: "L" 1 "L" level toggle output when the counter starts • Count stop: "L" • Count in process: "L" → Toggle output every underflow 0 "L" level square wave during counting • Count stop: "H" • Count in process: "L" • Underflow: "H" 1 "H" level toggle output when the counter starts • Count stop: "H" • Count in process: "H" → Toggle output every underflow 1 1 1 1 0 0 1 1 Output waveform PFRxy represents PFR register value of the corresponding pin. [bit3] INTE: Interrupt request enable bit This bit is the interrupt request enable bit. When the INTE bit is set to "1" and the UF bit is set to "1", an interrupt request is generated. When the INTE bit is set to "0", no interrupt request is generated. [bit2] UF: Underflow interrupt flag This bit is the timer interrupt request flag. As soon as the counter value underflows from "0000H" to "FFFFH", this bit is set to "1". Write "0" to this bit to clear it. Writing "1" to this bit is meaningless. A read-modify-write (RMW) instruction always reads "1" from this bit. [bit1] CNTE: Count enable bit This bit is the timer count enable bit. Write "1" to this bit to enter the start trigger wait state. Write "0" to this bit to stop the count operation. 637 CHAPTER 19 16-BIT RELOAD TIMER [bit0] TRG: Trigger bit This bit is the software trigger bit. Write "1" to this bit to generate a software trigger, load the contents of the reload register into the counter, and start the count operation. Writing "0" to this bit is meaningless. The read value is always "0". The trigger input to this register is valid only if CNTE=1. No effect occurs if CNTE=0. Notes: • Rewrite bits other than UF, CNTE, and TRG only when CNTE=0. • Do not set OUTL bit and CNTE/TRG simultaneously. When RLT7 is selected as A/D convert trigger, the register setting order of OUTL bit and A/D converter may cause the A/D converter to start at unintended timing because the A/D converter starts to convert using the rising edge of the timer output as the trigger. For example, to start A/D convert when the counter underflows in one-shot mode of RLT7, set as the following procedure. Set OUTL bit. (OUTL setting of TMCSR) → Set A/D convert trigger selection. (STS1 and STS0 setting of ADCS1) → RLT7 count start (CNTE and TRG setting of TMCSR) 638 CHAPTER 19 16-BIT RELOAD TIMER 19.2.2 16-bit Timer Register (TMR) The 16-bit timer register (TMR) is used to read the count value of the 16-bit timer. ■ Bit Configuration of the 16-bit Timer Register (TMR) Figure 19.2-3 Bit Configuration of the 16-bit Timer Register (TMR) TMR Address: 0001B2H, 0001BAH bit15 0001C2H, 0001CAH 0001EAH 0 Read/Write (R) Initial value (xxxxH) The 16-bit timer register (TMR) is used to read the count value of the 16-bit timer. The initial value is undefined. Be sure to read this register using a 16-bit data transfer instruction. 639 CHAPTER 19 16-BIT RELOAD TIMER 19.2.3 16-bit Reload Register (TMRLR) The 16-bit reload register (TMRLR) holds the initial value of a counter. ■ Bit Configuration of the 16-bit Reload Register (TMRLR) Figure 19.2-4 Bit Configuration of the 16-bit Reload Register (TMRLR) TMRLR Address: 0001B0H, 0001B8H bit15 0001C0H, 0001C8H 0001E8H 0 Read/Write (W) Initial value (xxxxH) The 16-bit reload register (TMRLR) holds the initial value of a counter. The initial value is undefined. Be sure to read this register using a 16-bit data transfer instruction. 640 CHAPTER 19 16-BIT RELOAD TIMER 19.3 16-bit Reload Timer Operation This section describes the following operations of the 16-bit reload timer: • Internal clock operation • Underflow operation • Operation of the output pin function ■ Internal Clock Operation If the timer operates with a divide-by clock of the internal clock, one of the clocks created by dividing the machine clock by 2, 8, or 32 can be selected as the clock source. To start a count operation as soon as counting is enabled, write 1 to the CNTE and TRG bits of the control status register. While the timer is running (CNTE=1), trigger input occurring due to the TRG bit is always valid, regardless of the operating mode. Time T (T: resource clock machine cycle) is required between input of the counter start trigger and the actual loading the reload register data into the counter. Figure 19.3-1 Startup and Operations of the Counter Count clock Reload data Counter -1 -1 -1 Data load CNTE register TRG register T 641 CHAPTER 19 16-BIT RELOAD TIMER ■ Underflow Operation An underflow is an event occurring when the counter value changes from "0000H" to "FFFFH". Thus, an underflow occurs when the count is [reload register setting value + 1]. If the RELD bit of the control status register is set to 1 when an underflow occurs, the contents of the reload register are loaded, and the count operation is continued. If the RELD bit is set to "0", the counter stops at "FFFFH". Figure 19.3-2 Underflow Operation RELD=1 Count clock Counter 0000H Reload data 0000H FFFFH Data load Underflow set RELD=0 Count clock Counter Underflow set 642 -1 -1 -1 CHAPTER 19 16-BIT RELOAD TIMER ■ Operation of the Output Pin Function The TOT pins provide toggle output that is reversed for an underflow in reload mode or pulse output that indicates that counting is in progress in one-shot mode. The output polarity can be set in the OUTL bit of the register. If OUTL=0, toggle output is "0" for the initial value and the one-shot pulse output is "1" while a count operation is in progress. If OUTL=1, the output waveform is reversed. Figure 19.3-3 Output Pin Function Operation [RELD=1, OUTL=0] Count started Underflow Reversed if OUTL=1 TOT0 to TOT3 CNTE Generalpurpose port Startup trigger Figure 19.3-4 Output Pin Function Operation [RELD=0, OUTL=0] Count started Underflow TOT0 to TOT3 CNTE Reversed if OUTL=1 Generalpurpose port Startup trigger Startup trigger wait status 643 CHAPTER 19 16-BIT RELOAD TIMER ■ Operating States of the Counter The counter state is determined by the CNTE bit of the control register and the WAIT signal, which is an internal signal. The states that can be set include the stop state, when CNTE=0 and WAIT=1 (STOP state); the startup trigger wait state, when CNTE=1 and WAIT=1 (WAIT status); and the operation state, when CNTE=1 and WAIT=0 (RUN state) Figure 19.3-5 Status Transitions of the Counter. Reset State transition caused by hardware State transition caused by register access STOP CNTE=0, WAIT=1 Counter: Retains the value when it stops; undefined just after reset CNTE=1 TRG=0 WAIT CNTE=1 TRG=1 CNTE=1, WAIT=1 Counter: Retains the value when it stops; undefined from just after reset until data is loaded TRG=1 LOAD RUN RELD · UF CNTE=1, WAIT=0 Counter: Running TRG=1 CNTE=1,WAIT=0 Loads contents of reload register into counter RELD · UF Loading completed ■ Notice • The internal prescaler is enabled if a trigger (software or external trigger) is applied while bit1 (timer enable: CNTE) of the control status register is set to "1". • If the device attempts to set and clear the interrupt request flag at the same time, the flag is set and the clear operation does not occur. • If the device attempts to write to and reload the data into the 16-bit reload register at the same time, old data is loaded into the counter. New data is loaded into the counter only at the next reload timing. • If the device attempts to load and count the 16-bit timer register at the same time, the load (reload) operation takes precedence. 644 CHAPTER 20 16-BIT FREE-RUN TIMER This chapter describes the functions and operation of the 16-bit free-run timer. 20.1 Overview of 16-bit Free-run Timer 20.2 16-bit Free-run Timer Registers 20.3 16-bit Free-run Timer Operation 20.4 Notes on Using the 16-bit Free-run Timer 645 CHAPTER 20 16-BIT FREE-RUN TIMER 20.1 Overview of 16-bit Free-run Timer The 16-bit free-run timer consists of a 16-bit timer (up counter) and control circuit. The 16-bit free-run timer can be used with input capture and/or output compare. ■ Overview of 16-bit Free-run Timer The 16-bit free-run timer consists of a 16-bit up counter and control status register. The count value from the 16-bit free-run timer is used as the base time (base timer) for the output compare and the input capture. • The count clock can be selected from four different clocks. • An interrupt can be generated when a counter overflow occurs. • A mode setting is available that initializes the counter when a match with the value in compare register in the output compare occurs. • The free-run timer, the input capture, and the output compare unit operate cooperatively by the following combinations. - Free-run timer 0, input capture 0, 1 - Free-run timer 1, input capture 2, 3 - Free-run timer 2, output compare 0, 1 - Free-run timer 3, output compare 2, 3 ■ Block Diagram of the 16-bit Free-run Timer Interrupt ECLK IVF IVFE STOP MODE CLR CLK1 CLK0 Frequency divider φ R-bus FRCK Clock selection 16-bit free-run timer (TCDT) Clock To internal circuit (T15 to T00) Comparator 646 CHAPTER 20 16-BIT FREE-RUN TIMER 20.2 16-bit Free-run Timer Registers This section describes the 16-bit free-run timer registers. ■ 16-bit Free-run Timer Registers Figure 20.2-1 Bit Configuration of 16-bit Free-run Timer Registers TCDT (Upper) bit15 14 13 12 11 10 9 8 T15 T14 T13 T12 T11 T10 T09 T08 Read/Write (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Initial value (0) (0) (0) (0) (0) (0) (0) (0) bit7 6 5 4 3 2 1 0 T07 T06 T05 T04 T03 T02 T01 T00 Read/Write (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Initial value (0) (0) (0) (0) (0) (0) (0) (0) bit7 6 5 4 3 2 1 0 IVF IVFE STOP MODE CLR CLK1 CLK0 Address: 0001F0H, 0001F4H 0001F8H, 0001FCH TCDT (Lower) Address: 0001F1H, 0001F5H 0001F9H, 0001FDH TCCS Address: 0001F3H, 0001F7H ECLK 0001FBH, 0001FFH Read/Write (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Initial value (0) (x) (0) (0) (0) (0) (0) (0) 647 CHAPTER 20 16-BIT FREE-RUN TIMER 20.2.1 Timer Data Register (TCDT) The timer data register is used to read the count value of the 16-bit free-run timer. ■ Timer Data Register (TCDT) Figure 20.2-2 Bit Configuration of Timer Data Register (TCDT) TCDT (Upper) bit15 14 13 12 11 10 9 8 T15 T14 T13 T12 T11 T10 T09 T08 Read/Write (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Initial value (0) (0) (0) (0) (0) (0) (0) (0) bit7 6 5 4 3 2 1 0 T07 T06 T05 T04 T03 T02 T01 T00 Read/Write (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Initial value (0) (0) (0) (0) (0) (0) (0) (0) Address: 0001F0H, 0001F4H 0001F8H, 0001FCH TCDT (Lower) Address: 0001F1H, 0001F5H 0001F9H, 0001FDH The counter value of the timer data register is initialized to "0000H" by a reset. Write to this register to set the timer value. Note that this register must be written to in the stop state (STOP=1 in TCCS register). The 16-bit free-run timer is initialized as a result of the following: • Reset • Setting the clear bit (CLR) of the timer control status register to "1" • Match of the value of the compare clear register in the output compare and the counter value (Mode setting is required). Note: Access to the TCDT register must be half word (16 bits) access. 648 CHAPTER 20 16-BIT FREE-RUN TIMER 20.2.2 Timer Control Status Register (TCCS) The timer control status register (TCCS) is used to control the count value of the 16-bit free-run timer. ■ Timer Control Status Register (TCCS) TCCS bit7 Address: 0001F3H, 0001F7H ECLK 0001FBH, 0001FFH 6 5 4 IVF IVFE 3 2 1 0 STOP MODE CLR CLK1 CLK0 Read/Write (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Initial value (0) (x) (0) (0) (0) (0) (0) (0) [bit7] ECLK: Clock selection bit This bit selects either the internal count clock source or external count clock source for the 16-bit freerun timer. Change the clock source while the output compare and input capture are stopped. Table 20.2-1 Clock Selection Bit ECLK Clock selection 0 Selects the internal clock source (CLKP) [Initial value] 1 Selects the external pin (FRCK) Note: If the internal clock is selected, set the count clock in bit1 and bit0 (CLK1 and CLK0 of the TCDT register). This count clock is handled as the base clock. The minimum pulse width required for the external clock is 2 x T (T: peripheral clock machine cycle). If the external clock is specified and the output compare is used, a compare match or interrupt occurs at the next clock cycle. For a compare match to be output and an interrupt to occur, at least one clock cycle must be input after the compare match. 649 CHAPTER 20 16-BIT FREE-RUN TIMER [bit6] IVF: Interrupt request flag IVF is the interrupt request flag of the 16-bit free-run timer. When the 16-bit free-run timer overflows or when, as a result of the mode setting, a match with compare register is detected, this bit is set to "1". An interrupt occurs when the interrupt request enable bit (IVFE) is set. Write "0" to this bit to clear it. A read-modify-write (RMW) instruction always reads "1" from this bit. Table 20.2-2 Interrupt Request Flag IVF Interrupt request flag 0 No interrupt request 1 Interrupt request Note: The initial value of the IVF bit immediately after a reset clear is "0". But, after an overflow occurs, the initial value of the IVF bit read is "1" because the timer counter automatically performs the count operation following a reset clear. [bit5] IVFE: Interrupt enable bit IVFE is the interrupt enable bit of the 16-bit free-run timer. When this bit is set to "1" and the interrupt flag (IVF) is set to "1", an interrupt occurs. Table 20.2-3 Interrupt Enable Bit IVFE Interrupt enabled 0 Interrupt disabled [Initial value] 1 Interrupt enabled [bit4] STOP: Stop bit The STOP bit is used to stop counting by the 16-bit free-run timer. Table 20.2-4 Stop Bit STOP Count operation 0 Counting enabled (operation) [Initial value] 1 Counting disabled (stop) Note: When the 16-bit free-run timer stops, the output compare operation also stops. 650 CHAPTER 20 16-BIT FREE-RUN TIMER [bit3] MODE: Mode setting bit The MODE bit is used to set the initialization conditions of the 16-bit free-run timer. When this bit is set to "0", the counter value can be initialized by a reset and the clear bit (bit2: CLR). When this bit is set to "1", the counter value can be initialized as the result of a match with the value of compare register of the output compare as well as by a reset and the clear bit (bit2: CLR). Table 20.2-5 Mode Setting Bit MODE Timer initialization condition 0 Initialization caused by a reset or the clear bit [Initial value] 1 Initialization caused by a reset, the clear bit, or compare register [bit2] CLR: Timer clear bit The CLR bit is used to initialize the value of the operating 16-bit free-run timer to "0000H". When "1" is written to this bit, the timer value is initialized to "0000H". "0" is always read from this bit. Note: The counter value is initialized at the change point of the count value. After "1" is written to CLR bit, the counter clear request is canceled if "0" is written to the CLR bit before the counter is cleared. To initialize the counter value while the timer is stopped, write "0000H" to the data register. [bit1, bit0] CLK1, CLK0: Count clock selection bits The CLK1 and CLK0 bits are used to select the count clock of the 16-bit free-run timer. Immediately after a value is written to these bits, the clock is updated. Therefore, be sure to stop the output compare and input capture operation before writing a value to these bits. Table 20.2-6 Count Clock Selection Bits CLK1 CLK0 Count clock (φ) φ=18 MHz φ=9 MHz 0 0 φ/22 0.22 µs 0.44 µs 0 1 φ/24 0.89 µs 1.78 µs 1 0 φ/25 1.78 µs 3.56 µs 1 1 φ/26 3.56 µs 7.11 µs φ: Resource clock (CLKP) 651 CHAPTER 20 16-BIT FREE-RUN TIMER 20.3 16-bit Free-run Timer Operation The 16-bit free-run timer starts counting from counter value "0000H" after a reset is cleared. This counter value is used as the base time for 16-bit output compare and 16bit input capture. ■ 16-bit Free-run Timer Operation The counter value is cleared in the following cases: • An overflow occurs. • A compare match with the compare clear register (compare register in the output compare) value (A mode setting is required). • "1" is written to the CLR bit of the TCCS register during operation. • "0000H" is written to the TCDT register while the timer is stopped. • A reset occurs. An interrupt can occur when an overflow occurs or when the counter is cleared because a compare match with the compare clear register value occurs (A mode setting is required for a compare match interrupt). Figure 20.3-1 Clearing of Counter Because of an Overflow Counter value FFFFH BFFFH 7FFFH 3FFFH 0000H Reset Interrupt 652 Time CHAPTER 20 16-BIT FREE-RUN TIMER Figure 20.3-2 Clearing of Counter Because of a Compare Match with the Compare Clear Register Value Counter value FFFFH Match BFFFH Match 7FFFH 3FFFH 0000H Time Reset Compare register BFFFH Interrupt ■ Clear Timing of the 16-bit Free-run Timer The counter can be cleared by a reset, software, or a match with the compare clear register. A reset and software clear the counter as soon as the clear occurs. A match with the compare clear register, however, clears the counter in synchronization with the count timing. Figure 20.3-3 Clear Timing of the 16-bit Free-run Timer Compare clear register value N Counter clear Counter value N 0000H ■ Count Timing of the 16-bit Free-run Timer The 16-bit free-run timer counts up according to an input clock (internal or external clock). When an external clock is selected, the clock’s falling edge ↓ is synchronized with the system clock, then the falling edge of the internal count clock is counted. Figure 20.3-4 Count Timing of the 16-bit Free-run Timer External clock input Internal count clock Counter value N N+1 653 CHAPTER 20 16-BIT FREE-RUN TIMER 20.4 Notes on Using the 16-bit Free-run Timer This section contains notes on using the 16-bit free-run timer. ■ Notes on Using the 16-bit Free-run Timer • If the interrupt request flag is set and cleared at the same time, setting of the flag takes precedence and the clear operation is ineffective. • If "1" is written to bit2 (counter initialization bit: CLR) of the control status register, the bit retains the value until the internal counter is cleared, then clears itself when the internal counter is cleared. If "1" is written to counter initialization bit at the same time that the bit is cleared, the write takes precedence, and the counter initialization bit retains "1" until the next clear timing. • The counter is cleared only during operation of the internal counter (The internal prescaler is also in operation). To clear the counter while it is stopped, write" 0000H" to the timer count data register. 654 CHAPTER 21 INPUT CAPTURE This chapter describes the functions and operation of the input capture. 21.1 Overview of the Input Capture 21.2 Input Capture Registers 21.3 Input Capture Operation 655 CHAPTER 21 INPUT CAPTURE 21.1 Overview of the Input Capture The input capture detects rising edges, falling edges, or both edges on the signal input from an external pin and saves the value of the 16-bit free-run timer at that time to a register. The unit can also generate an interrupt when an edge is detected. The input capture consists of an input capture data register and control register. ■ Overview of the Input Capture Each input capture has its own external input pin. • The active edge on the external input can be selected from the following three options : - Rising edge - Falling edge - Both edges • The input capture can generate an interrupt when an active edge on the external input is detected. • The free-run timer and the input capture operate cooperatively by the following combinations. - Free-run timer 0, input capture 0, 1 - Free-run timer 1, input capture 2, 3 ■ Block Diagram of the Input Capture Figure 21.1-1 Block Diagram Count value from 16-bit free-run timer (T15 to T00) R-bus Capture data register ch.0 IN0 Input pin Edge detection EG11 Count value from 16-bit free-run timer (T15 to T00) EG10 EG01 IN1 Input pin Edge detection Capture data register ch.1 ICP1 ICP0 ICE1 EG00 ICE0 Interrupt Interrupt 656 CHAPTER 21 INPUT CAPTURE 21.2 Input Capture Registers The input capture has the following two registers: • Input capture register (IPCP0 to IPCP3) • Input capture control register (ICS01,ICS23) This section describes these registers in detail. ■ Input Capture Registers Figure 21.2-1 Bit Configuration of Input Capture Registers IPCP (Upper) bit15 14 13 12 11 10 9 8 CP15 CP14 CP13 CP12 CP11 CP10 CP09 CP08 Read/Write (R) (R) (R) (R) (R) (R) (R) (R) Initial value (X) (X) (X) (X) (X) (X) (X) (X) bit7 6 5 4 3 2 1 0 CP07 CP06 CP05 CP04 CP03 CP02 CP01 CP00 Read/Write (R) (R) (R) (R) (R) (R) (R) (R) Initial value (X) (X) (X) (X) (X) (X) (X) (X) bit7 6 5 4 3 2 1 0 ICP1 ICP0 ICE1 ICE0 EG11 EG10 EG01 EG00 Read/Write (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Initial value (0) (0) (0) (0) (0) (0) (0) (0) Address: IPCP0: 000184H IPCP1: 000186H IPCP2: 000188H IPCP3: 00018AH IPCP (Lower) Address: IPCP0: 000185H IPCP1: 000187H IPCP2: 000189H IPCP3: 00018BH ICS Address: ICS01: 000181H ICS23: 000183H 657 CHAPTER 21 INPUT CAPTURE 21.2.1 Input Capture Register (IPCP0 to IPCP3) The input capture register (IPCP0 to IPCP3) retains the 16-bit free-run timer value when the device detects the valid edge of a waveform input from the corresponding external pin. ■ Bit Configuration of the Input Capture Register (IPCP0 to IPCP3) Figure 21.2-2 Bit Configuration of the Input Capture Register (IPCP0 to IPCP3) IPCP (Upper) Address: IPCP0: 000184H IPCP1: 000186H IPCP2: 000188H IPCP3: 00018AH bit15 14 13 12 11 10 9 8 CP15 CP14 CP13 CP12 CP11 CP10 CP09 CP08 Read/Write (R) (R) (R) (R) (R) (R) (R) (R) Initial value (X) (X) (X) (X) (X) (X) (X) (X) bit7 6 5 4 3 2 1 0 CP07 CP06 CP05 CP04 CP03 CP02 CP01 CP00 Read/Write (R) (R) (R) (R) (R) (R) (R) (R) Initial value (X) (X) (X) (X) (X) (X) (X) (X) IPCP (Lower) Address: IPCP0: 000185H IPCP1: 000187H IPCP2: 000189H IPCP3: 00018BH The input capture register retains the 16-bit free-run timer value when the device detects the valid edge of a waveform input from the corresponding external pin. The value of this register is undefined after a reset. Access this register using 16-bit or 32-bit data. Writing to this register is not permitted. 658 CHAPTER 21 INPUT CAPTURE 21.2.2 Input Capture Control Register (ICS01,ICS23) The input capture control register (ICS01,ICS23) is used to control an input capture interrupt or an edge detection. ■ Bit Configuration of the Input Capture Control Register (ICS01,ICS23) Figure 21.2-3 Bit Configuration of the Input Capture Control Register (ICS01,ICS23) ICS bit7 6 5 4 3 2 1 0 ICP1 ICP0 ICE1 ICE0 EG11 EG10 EG01 EG00 Read/Write (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Initial value (0) (0) (0) (0) (0) (0) (0) (0) Address: ICS01: 000181H ICS23: 000183H [bit7, bit6] ICP1, ICP0: Input capture interrupt flags These bits are input capture interrupt flags. When a valid edge from the external input pin is detected, these bits are set to "1". If the interrupt enable bits (ICE3 to ICE0) are also set, the detection of a valid edge causes an interrupt to be generated. Write "0" to these bits to clear them. Writing "1" is meaningless. A read-modify-write (RMW) instruction always reads "1" from these bits. Table 21.2-1 Input Capture Interrupt Flags ICP0/ICP1 Interrupt flag 0 Valid edge not detected [Initial value] 1 Valid edge detected [bit5, bit4] ICE1, ICE0: Input capture interrupt enable bits These bits are the input capture interrupt enable bits. If they are set to "1" and the input capture interrupt flags (ICP1, ICP0) are also set to "1", an input capture interrupt occurs. Table 21.2-2 Input Capture Interrupt Enable Bits ICE0/ICE1 Input capture interrupt enable 0 Interrupt disabled [Initial value] 1 Interrupt enabled 659 CHAPTER 21 INPUT CAPTURE [bit3 to bit0] EG11, EG10, EG01, EG00 (EG31, EG30, EG21, EG20): Edge selection bits These bits are used to select a valid edge polarity for external input. They also enable an input capture operation. Table 21.2-3 Edge Selection Bits EGn1 EGn0 Edge polarity detection 0 0 Edge not detected (stopped) [Initial value] 0 1 Rising edge detected ↑ 1 0 Falling edge detected ↓ 1 1 Both edges (rising and falling edges) detected ↑ & ↓ The number n in EGn1/EGn0 corresponds to the input capture channel number. n = 0 to 3 660 CHAPTER 21 INPUT CAPTURE 21.3 Input Capture Operation When the 16-bit input capture detects the specified valid edge, it can read the value of the 16-bit free-run timer into the capture register and generate an interrupt. ■ 16-bit Input Capture Operation Figure 21.3-1 Example of Timing for Input Capture Reading Counter value FFFFH BFFFH 7FFFH 3FFFH Time 0000H Reset IN0 IN1 IN2 Data register 0 Undefined 3FFFH Data register 2 BFFFH Undefined Data register 1 Undefined BFFFH 7FFFH Capture 0 interrupt Capture 1 interrupt Capture 2 interrupt Capture 0 = Rising edge Capture 1 = Falling edge Capture 2 = Both edges Interrupt generated again due to a valid edge Interrupt cleared by software 661 CHAPTER 21 INPUT CAPTURE ■ 16-bit Input Capture Input Timing Figure 21.3-2 Example of 16-bit Input Capture Input Timing φ Counter value N N+1 Input capture input Valid edge Capture signal Capture register value Interrupt 662 N+1 CHAPTER 22 OUTPUT COMPARE UNIT This chapter describes the functions and operation of the output compare unit. 22.1 Overview of the Output Compare Unit 22.2 Output Compare Unit Registers 22.3 Output Compare Unit Operation 663 CHAPTER 22 OUTPUT COMPARE UNIT 22.1 Overview of the Output Compare Unit The output compare module consists of a compare register, compare output latch, and control register. ■ Features of the Output Compare Unit • The compare registers operate independently. Each compare register has a corresponding output pin and interrupt flag. • The output pin can be controlled using two compare registers as a pair. The output pin is reversed using two compare registers. • The initial value of each output pin default can be set. • Interrupts can be generated at a compare match. • The free-run timer and the output compare unit operate cooperatively by the following combinations. - Free-run timer 2, output compare 0, 1 - Free-run timer 3, output compare 2, 3 ■ Block Diagram of the Output Compare Unit Figure 22.1-1 Block Diagram of Output Compare Unit OTD1 OTD0 Compare register Compare circuit R-bus Compare register OTE0 Output Compare output latch OTE1 Output CMOD Compare circuit CST1 Compare output latch CST0 ICP1 ICP0 ICE1 ICE0 16-bit free-run timer Interrupt output Interrupt output 664 CHAPTER 22 OUTPUT COMPARE UNIT 22.2 Output Compare Unit Registers The output compare unit has the compare register and control register. ■ Output Compare Unit Registers Figure 22.2-1 Bit Configuration of Output Compare Unit Registers OCCP (Upper) bit15 14 13 12 11 10 9 8 C15 C14 C13 C12 C11 C10 C09 C08 Read/Write (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Initial value (X) (X) (X) (X) (X) (X) (X) (X) bit7 6 5 4 3 2 1 0 C07 C06 C05 C04 C03 C02 C01 C00 Read/Write (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Initial value (X) (X) (X) (X) (X) (X) (X) (X) bit15 14 13 12 11 10 9 8 CMOD Reserved Reserved OTD1 OTD0 Address: OCCP0: 000190H OCCP1: 000192H OCCP2: 000194H OCCP3: 000196H OCCP (Lower) Address: OCCP0: 000191H OCCP1: 000193H OCCP2: 000195H OCCP3: 000197H OCS (Upper) Address: OCS01: 00018CH OCS23: 00018EH Reserved Reserved Reserved Read/Write (−) (−) (−) (R/W) (−) (−) (R/W) (R/W) Initial value (1) (1) (1) (0) (1) (1) (0) (0) bit7 6 5 4 3 2 1 0 ICP1 ICP0 ICE1 ICE0 CST1 CST0 Read/Write (R/W) (R/W) (R/W) (R/W) (−) (−) (R/W) (R/W) Initial value (0) (0) (0) (0) (1) (1) (0) (0) OCS (Lower) Address: OCS01: 00018DH OCS23: 00018FH Reserved Reserved 665 CHAPTER 22 OUTPUT COMPARE UNIT 22.2.1 Compare Register (OCCP0 to OCCP3) This section describes the compare register (OCCP0 to OCCP3) in detail. ■ Bit Configuration of the Compare Register (OCCP0 to OCCP3) Figure 22.2-2 Bit Configuration of the Compare Register (OCCP0 to OCCP3) OCCP (Upper) bit15 14 13 12 11 10 9 8 C15 C14 C13 C12 C11 C10 C09 C08 Read/Write (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Initial value (X) (X) (X) (X) (X) (X) (X) (X) bit7 6 5 4 3 2 1 0 C07 C06 C05 C04 C03 C02 C01 C00 Read/Write (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Initial value (X) (X) (X) (X) (X) (X) (X) (X) Address: OCCP0: 000190H OCCP1: 000192H OCCP2: 000194H OCCP3: 000196H OCCP (Lower) Address: OCCP0: 000191H OCCP1: 000193H OCCP2: 000195H OCCP3: 000197H ■ Functions of the Compare Register (OCCP0 to OCCP3) The compare register is the 16-bit compare register that is compared with the 16-bit free-run timer. Since the initial value of the register is undefined, set the compare value before enabling startup. Access the compare register using 16-bit or 32-bit data. When the register value and the 16-bit free-run timer value match, a compare signal is generated and the output compare interrupt flag is set. When the corresponding bit of the port function register (PFR) is set and output is enabled, the output level corresponding to the compare register is reversed. 666 CHAPTER 22 OUTPUT COMPARE UNIT 22.2.2 Control Register (OCS01,OCS23) This section describes the control register (OCS01,OCS23) in detail. ■ Bit Configuration of the Control Register (OCS01,OCS23) Figure 22.2-3 Bit Configuration of the Control Register (OCS01,OCS23) OCS (Upper) Address: OCS01: 00018CH OCS23: 00018EH bit15 14 13 Reserved Reserved Reserved 12 11 10 9 8 CMOD Reserved Reserved OTD1 OTD0 Read/Write (−) (−) (−) (R/W) (−) (−) (R/W) (R/W) Initial value (1) (1) (1) (0) (1) (1) (0) (0) bit7 6 5 4 3 2 1 0 ICP1 ICP0 ICE1 ICE0 CST1 CST0 Read/Write (R/W) (R/W) (R/W) (R/W) (−) (−) (R/W) (R/W) Initial value (0) (0) (0) (0) (1) (1) (0) (0) OCS (Lower) Address: OCS01: 00018DH OCS23: 00018FH Reserved Reserved [bit15 to bit13] Reserved: Reserved bits These bits are reserved bits. In a read operation, "111B" is always read from these bits. [bit12] CMOD: Mode bit Switches the mode for reversing the pin output level for a compare match if pin output is enabled. • When CMOD=0 (initial value), the output level of the pin corresponding to the compare register is reversed. - The level is reversed when compare register 0 (2) provides a match. - The level is reversed when compare register 1 (3) provides a match. • When CMOD=1, - The level is reversed when compare register 0 (2) provides a match. - The level is reversed when compare registers 0 (2) or 1 (3) provides a match. [bit11, bit10] Reserved: Reserved bits These bits are reserved bits. In a read operation, "11B" is always read from these bits. 667 CHAPTER 22 OUTPUT COMPARE UNIT [bit9, bit8] OTD1, OTD0: Compare pin output level change bits Use these bits to change the pin output level when the output compare register pin output is enabled. Write to these bits after stopping the compare operation. In a read operation, the output compare pin output value is read from these bits. Table 22.2-1 Compare Pin Output Level Change Bits OTD1, OTD0 Compare pin output level 0 The compare pin output changes to "0". [Initial value] 1 The compare pin output changes to "1". [bit7, bit6] ICP1, ICP0: Interrupt flags These bits are interrupt flags for an output compare. They are set to "1" if the compare registers and the 16-bit free-run timer value match. When the interrupt request bits (ICE1, ICE0) are enabled and these bits are set to "1", an output compare interrupt occurs. Write "0" to these bits to clear them. Writing "1" is meaningless. A read-modify-write (RMW) instruction always reads "1" from these bits. Table 22.2-2 Interrupt Flags ICP1, ICP0 Interrupt flag 0 No output compare match [Initial value] 1 Output compare match If an external clock is specified for the free-run timer, a compare match or interrupt occurs at the next clock. For a compare match to be output and an interrupt to occur, at least one clock must be input to the external clock of the free-run timer after the compare match. [bit5, bit4] ICE1, ICE0: Interrupt enable bits These bits enable an output compare interrupt. When they are set to "1" and the interrupt flags (ICP0 and ICP1) are set to "1", an output compare interrupt occurs. Table 22.2-3 Interrupt Enable Bits ICE1, ICE0 Interrupt enable 0 Output compare interrupt disabled [Initial value] 1 Output compare interrupt enabled [bit3, bit2] Reserved: Reserved bits These are the reserved bits. In a read operation, "11"B is always read from these bits. 668 CHAPTER 22 OUTPUT COMPARE UNIT [bit1, bit0] CST1, CST0: Match operation enable bits These bits enable a match operation with the 16-bit free-run timer. Before enabling the compare operation, be sure to set the compare register value and the output control register value. Table 22.2-4 Match Operation Enable Bits CST1, CST0 Match operation enable 0 Compare operation disabled [Initial value] 1 Compare operation enabled Since output compare is synchronized with the 16-bit free-run timer, stopping the 16-bit free-run timer also stops the compare operation. 669 CHAPTER 22 OUTPUT COMPARE UNIT 22.3 Output Compare Unit Operation The 16-bit output compare operation compares the specified compare register value and the 16-bit free-run timer value. If a match occurs, the interrupt flag is set and the output level is reversed. ■ 16-bit Output Compare Operation The compare operation can be executed for each channel independently (when CMOD=0). Figure 22.3-1 Example of Output Waveform When Compare Registers 0 and 1 are Used (The Initial Value of the Output is "0") Counter value FFFFH BFFFH 7FFFH 3FFFH Time 0000H Reset Compare register 0 value BFFFH Compare register 1 value 7FFFH OP0 Output OP1 Output Compare 0 interrupt Compare 1 interrupt 670 CHAPTER 22 OUTPUT COMPARE UNIT The output level can be changed if two compare registers are used (when CMOD=1). Figure 22.3-2 Example of Output Waveform When the Compare Registers 0 and 1 are Used (The Initial Value of the Output is "0") Counter value FFFFH BFFFH 7FFFH 3FFFH Time 0000H Reset Compare register 0 value BFFFH Compare register 1 value 7FFFH OP0 Output OP1 Output Compare 0 interrupt Compare 1 interrupt 671 CHAPTER 22 OUTPUT COMPARE UNIT ■ 16-bit Output Compare Operation Timing The output level can be changed if two compare registers are used (when CMOD=1). When the values of the free-run timer and the specified compare register match, the output compare unit generates a compare match signal to reverse the output and generate an interrupt. Reversal of output due to a compare match occurs in synchronization with the count timing of the counter. ● Compare register rewrite timing When rewritten, the compare register is not compared with the counter value. Figure 22.3-3 Compare Register Rewrite Timing Counter value N N+1 N+2 N+3 Match signal not generated Compare clear register 0 value M N+1 Compare register 0 write Compare clear register 1 value L N+3 Compare register 1 write Compare 0 stopped Compare 1 stopped ● Compare match, interrupt timing Figure 22.3-4 Compare Match, Interrupt Timing Count clock Counter value Compare register value Compare match Pin output Interrupt 672 N N N+1 N+2 N+3 CHAPTER 22 OUTPUT COMPARE UNIT ● Pin output timing Figure 22.3-5 Pin Output Timing Counter value Compare register value N N+1 N+1 N+1 N Compare match Pin output 673 CHAPTER 22 OUTPUT COMPARE UNIT 674 CHAPTER 23 PPG (PROGRAMMABLE PULSE GENERATOR) This chapter describes the registers, function, and operation of the PPG. 23.1 Overview of PPG 23.2 PPG Registers 23.3 PPG Operation 675 CHAPTER 23 PPG (PROGRAMMABLE PULSE GENERATOR) 23.1 Overview of PPG The PPG can output high-precision PWM waves at an arbitrary cycle and duty ratio. Each of the channels consists of a 16-bit down-counter, cycle setting 16-bit register with buffer, duty setting 16-bit register with buffer, and pin controller. The control status register for each channel is used to indicate the operation control mode. General control registers 10 and 20 are common registers shared by each channel for its control. ■ Features The count clock for the 16-bit down-counter can be selected from among the following four types: • Clocks: FCLKP, FCLKP/4, FCLKP/16, FCLKP/64 (FCLKP: Clock for peripherals) • The counter can be set to "FFFFH" by a reset or underflow. The 16-bit down-counter causes an underflow when it changes from "0000H" to "FFFFH". • Each channel has output pin. • Registers Cycle setting register: Data reload register with buffer Duty setting register: Compare register with buffer • Output pin control A duty match causes an output 1. An underflow causes an output 0. The output value fix mode enables output of all "L" or all "H". The polarity reverse can also be specified. • An interrupt factor can be generated using any combination of the following: Activation trigger of PPG (software trigger) Occurrence of counter borrow (cycle match) Occurrence of duty match Occurrence of counter borrow (cycle match) or occurrence of duty match • You can set simultaneous activation of two or more channels using software or reload timer. You can also set restarting the PPG during operation. 676 CHAPTER 23 PPG (PROGRAMMABLE PULSE GENERATOR) ■ Block Diagram of PPG ● Configuration diagram of the entire PPG0 to PPG7 and the reload timer connection Figure 23.1-1 Configuration Diagram of the Entire PPG PPG0 to PPG3 External trigger 0 External trigger 1 Output pins TRG input PPG ch.0 PPG0 TRG input PPG ch.1 PPG1 TRG input PPG ch.2 PPG2 TRG input PPG ch.3 PPG3 External trigger 2 External trigger 3 Selector Reload timer 0 Reload timer 1 General control register 20 Select signal General control register 10 (Indicates trigger input) PPG4 to PPG7 Selector Reload timer 2 Reload timer 3 General control register 21 Select signal Output pins TRG input PPG ch.4 PPG4 TRG input PPG ch.5 PPG5 TRG input PPG ch.6 PPG6 TRG input PPG ch.7 PPG7 General control register 11 (Indicates trigger input) 677 CHAPTER 23 PPG (PROGRAMMABLE PULSE GENERATOR) ● Configuration diagram of PPG (1 channel) Figure 23.1-2 Configuration Diagram of PPG (1 Channel) Cycle setting register Duty setting register PCSR PDUT Prescaler CMP FCLKP/1 Clock Load FCLKP/4 16-bit down-counter FCLKP/16 FCLKP/64 Start Underflow PPG mask Peripheral clock (FCLKP) PPG output Reversal bit Enable Internal trigger (EN0 to EN3) GCN20 Reload Timer ch.0, ch.1 input Edge detection Software trigger 678 Interrupt selection IRQ (Interrupt request signal) CHAPTER 23 PPG (PROGRAMMABLE PULSE GENERATOR) 23.2 PPG Registers This section lists the PPG registers and details their functions. ■ PPG Registers Figure 23.2-1 PPG Registers GCN10 (Upper) bit15 Address: 000100H 14 13 12 11 TSEL33 to TSEL30 10 9 8 TSEL23 to TSEL20 Read/Write (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Initial value (0) (0) (1) (1) (0) (0) (1) (0) bit7 6 5 4 3 2 1 0 GCN10 (Lower) Address: 000101H TSEL13 to TSEL10 TSEL03 to TSEL00 Read/Write (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Initial value (0) (0) (0) (1) (0) (0) (0) (0) bit15 14 13 12 11 10 9 8 GCN11 (Upper) Address: 000104H TSEL73 to TSEL70 TSEL63 to TSEL60 Read/Write (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Initial value (0) (0) (1) (1) (0) (0) (1) (0) bit7 6 5 4 3 2 1 0 GCN11 (Lower) Address: 000105H TSEL53 to TSEL50 TSEL43 to TSEL40 Read/Write (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Initial value (0) (0) (0) (1) (0) (0) (0) (0) bit7 6 5 4 3 2 1 0 EN3 EN2 EN1 EN0 GCN2 Address: Reserved Reserved Reserved Reserved GCN20: 000103H GCN21: 000107H Read/Write (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Initial value (−) (−) (−) (−) (0) (0) (0) (0) (Continued) 679 CHAPTER 23 PPG (PROGRAMMABLE PULSE GENERATOR) (Continued) PTMR (Upper) Address: 000110H, 000118H bit15 000120H, 000128H 000130H, 000138H D15 000140H, 000148H 14 13 12 11 10 9 8 D14 D13 D12 D11 D10 D09 D08 Read/Write (R) (R) (R) (R) (R) (R) (R) (R) Initial value (1) (1) (1) (1) (1) (1) (1) (1) bit7 6 5 4 3 2 1 0 D07 D06 D05 D04 D03 D02 D01 D00 Read/Write (R) (R) (R) (R) (R) (R) (R) (R) Initial value (1) (1) (1) (1) (1) (1) (1) (1) 14 13 12 11 10 9 8 D14 D13 D12 D11 D10 D09 D08 PTMR (Lower) Address: 000111H, 000119H 000121H, 000129H 000131H, 000139H 000141H, 000149H PCSR (Upper) Address: 000112H, 00011AH bit15 000122H, 00012AH D15 000132H, 00013AH 000142H, 00014AH Read/Write (W) (W) (W) (W) (W) (W) (W) (W) Initial value (X) (X) (X) (X) (X) (X) (X) (X) bit7 6 5 4 3 2 1 0 D07 D06 D05 D04 D03 D02 D01 D00 Read/Write (W) (W) (W) (W) (W) (W) (W) (W) Initial value (X) (X) (X) (X) (X) (X) (X) (X) 14 13 12 11 10 9 8 D14 D13 D12 D11 D10 D09 D08 PCSR (Lower) Address: 000113H, 00011BH 000123H, 00012BH 000133H, 00013BH 000143H, 00014BH PDUT (Upper) Address: 000114H, 00011CH bit15 000124H, 00012CH D15 000134H, 00013CH 000144H, 00014CH Read/Write (W) (W) (W) (W) (W) (W) (W) (W) Initial value (X) (X) (X) (X) (X) (X) (X) (X) (Continued) 680 CHAPTER 23 PPG (PROGRAMMABLE PULSE GENERATOR) (Continued) PDUT (Lower) Address: 000115H, 00011DH 000125H, 00012DH 000135H, 00013DH 000145H, 00014DH bit7 6 5 4 3 2 1 0 D07 D06 D05 D04 D03 D02 D01 D00 Read/Write (W) (W) (W) (W) (W) (W) (W) (W) Initial value (X) (X) (X) (X) (X) (X) (X) (X) 14 13 12 11 10 9 8 STGR MDSE RTRG CKS1 CKS0 PGMS Reserved PCNH Address: 000116H, 00011EH bit15 000126H, 00012EH CNTE 000136H, 00013EH 000146H, 00014EH Read/Write (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (−) Initial value (0) (0) (0) (0) (0) (0) (0) (−) 6 5 4 3 2 1 0 EGS0 IREN IRQF IRS1 IRS0 Reserved OSEL PCNL Address: 000117H, 00011FH bit7 000127H, 00012FH EGS1 000137H, 00013FH 000147H, 00014FH Read/Write (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (−) (R/W) Initial value (0) (0) (0) (0) (0) (0) (−) (0) 681 CHAPTER 23 PPG (PROGRAMMABLE PULSE GENERATOR) 23.2.1 Control Status Registers (PCNH, PCNL) The control status registers (PCNH and PCNL) are a register per each channel for controlling the operation mode setting, the start enable, the clock selection, the output mask, the trigger input edge selection, and the interrupt enable. Also the registers indicate the interrupt status flag. ■ Structure of the Control Status Registers (PCNH, PCNL) Figure 23.2-2 Configuration of the Control Status Registers PCNH Address: 000116H, 00011EH bit15 000126H, 00012EH CNTE 000136H, 00013EH 000146H, 00014EH 14 13 12 11 10 9 8 STGR MDSE RTRG CKS1 CKS0 PGMS Reserved Read/Write (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (−) Initial value (0) (0) (0) (0) (0) (0) (0) (−) 6 5 4 3 2 1 0 EGS0 IREN IRQF IRS1 IRS0 Reserved OSEL PCNL Address: 000117H, 00011FH bit7 000127H, 00012FH EGS1 000137H, 00013FH 000147H, 00014FH Read/Write (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (−) (R/W) Initial value (0) (0) (0) (0) (0) (0) (−) (0) ■ Functions of the PCNH/PCNL Bits [bit15] CNTE: Counter operation enable This bit enables or disables operation of the 16-bit down-counter. Table 23.2-1 Counter Operation Enable CNTE Function 0 Disable the operation [Initial value] 1 Enable the operation [bit14] STGR: Software trigger Setting this bit to "1" causes a software trigger to activate PPG. The bit returns a value of "0" whenever read. 682 CHAPTER 23 PPG (PROGRAMMABLE PULSE GENERATOR) [bit13] MDSE: Operation mode This bit selects PWM operation for generating a continuous stream of pulses or one-shot operation for generating a single pulse. Table 23.2-2 Operation Mode MDSE Function 0 PWM operation [Initial value] 1 One-shot operation [bit12] RTRG: Restart enable bit This bit enables or disables restart using a trigger input. Table 23.2-3 Restart Enable Bit RTRG Function 0 Disables restarting. [Initial value] 1 Enables restarting. [bit11, bit10] CKS1, CKS0: Clock select These bits select the count clock for the 16-bit down-counter. Table 23.2-4 Selecting the Count Clock CKS1 CKS0 Count clock 0 0 FCLKP/1 [Initial value] 0 1 FCLKP/4 1 0 FCLKP/16 1 1 FCLKP/64 FCLKP: Peripheral macro operation clock [bit9] PGMS: PPG output mask When set to "1", this bit sets the PPG output to "L" or "H" regardless of the mode, cycle, and duty settings. Table 23.2-5 PPG Output Mask Polarity PPG output Normal polarity "L" level output [Initial value] Inverted polarity "H" level output Use OSEL bit (bit0 of the control status register) to specify the output polarity. 683 CHAPTER 23 PPG (PROGRAMMABLE PULSE GENERATOR) [bit8] Unused bit [bit7, bit6] EGS1, EGS0: Trigger input select These bits select the effective edge for the trigger input selected by general control register 10 (GCN10). Table 23.2-6 Trigger Input Select EGS1 EGS0 Trigger input edge 0 0 Invalid [Initial value] 0 1 Rising edge 1 0 Falling edge 1 1 Both edges [bit5] IREN: Interrupt request enable This bit enables or disables interrupt requests. Table 23.2-7 Interrupt Request Enable IREN Function 0 Disable interrupt requests [Initial value] 1 Enable interrupt requests [bit4] IRQF: Interrupt request flag When the interrupt source selected by bit3 and bit2 (IRS1 and IRS0) is generated with bit5 (IREN) enabling interrupt requests, this bit is set, generating an interrupt request to the CPU. This bit is cleared by writing "0" to it. Writing "1" to this bit does not change the bit value. When read by a read-modify-write (RMW) instruction, the bit returns "1" regardless of the bit value. If this bit is selected as a DMAC trigger, DMA transfer request occurs. In this case, this bit is cleared by DMAC at the transfer. [bit3, bit2] IRS1, IRS0: Interrupt source select These bits select the interrupt source. Table 23.2-8 Selecting the Interrupt Source IRS1 IRS0 0 0 Generation of a software trigger or trigger input [Initial value] 0 1 Occurrence of counter borrow (cycle match) 1 0 Occurrence of duty match 1 1 Occurrence of counter borrow (cycle match) or occurrence of duty match [bit1] Unused bit 684 Interrupt source CHAPTER 23 PPG (PROGRAMMABLE PULSE GENERATOR) [bit0] OSEL: PPG output polarity select This bit sets the PPG output polarity. The bit is used in combination with bit9 (PGMS) to specify the following: Table 23.2-9 PPG Output Polarity and Edge PGMS OSEL PPG output Polarity After reset 0 0 Normal polarity [Initial value] 0 1 Inverted polarity Normal polarity "L" output 1 0 Fixed at "L" output 1 1 Fixed at "H" output Inverted polarity "H" output Duty match Underflow 685 CHAPTER 23 PPG (PROGRAMMABLE PULSE GENERATOR) 23.2.2 PPG Cycle Setting Register (PCSR) The PPG cycle setting register (PCSR) is a 16-bit reload register for setting the PPG cycle. ■ Configuration of the PPG Cycle Setting Register (PCSR) Figure 23.2-3 Configuration of the PPG Cycle Setting Register PCSR (Upper) Address: 000112H, 00011AH bit15 000122H, 00012AH D15 000132H, 00013AH 000142H, 00014AH 14 13 12 11 10 9 8 D14 D13 D12 D11 D10 D09 D08 Read/Write (W) (W) (W) (W) (W) (W) (W) (W) Initial value (X) (X) (X) (X) (X) (X) (X) (X) bit7 6 5 4 3 2 1 0 D07 D06 D05 D04 D03 D02 D01 D00 Read/Write (W) (W) (W) (W) (W) (W) (W) (W) Initial value (X) (X) (X) (X) (X) (X) (X) (X) PCSR (Lower) Address: 000113H, 00011BH 000123H, 00012BH 000133H, 00013BH 000143H, 00014BH ■ Functions of the PCSR This register has a buffer. PCSR setting value is loaded from the buffer to counter when a counter borrow occurs or a trigger input is detected. An counter borrow is caused when the counter reaches "the PCSR set value + 1" count after starting counting. The cycle is the value obtained by multiplying "the count clock cycle" by "PCSR set value + 1" count. Be sure to write to the PPG duty setting register (PDUT) after writing to the PPG cycle setting register. To write to this register, access it using half word (16-bit) or word (32-bit) data. 686 CHAPTER 23 PPG (PROGRAMMABLE PULSE GENERATOR) 23.2.3 PPG Duty Setting Register (PDUT) The PPG duty setting register (PDUT) is a 16-bit register for setting the duty of the output wave. ■ Configuration of the PPG Duty Setting Register (PDUT) Figure 23.2-4 Configuration of the PPG Duty Setting Register PDUT (Upper) Address: 000114H, 00011CH bit15 000124H, 00012CH D15 000134H, 00013CH 000144H, 00014CH 14 13 12 11 10 9 8 D14 D13 D12 D11 D10 D09 D08 Read/Write (W) (W) (W) (W) (W) (W) (W) (W) Initial value (X) (X) (X) (X) (X) (X) (X) (X) bit7 6 5 4 3 2 1 0 D07 D06 D05 D04 D03 D02 D01 D00 Read/Write (W) (W) (W) (W) (W) (W) (W) (W) Initial value (X) (X) (X) (X) (X) (X) (X) (X) PDUT (Lower) Address: 000115H, 00011DH 000125H, 00012DH 000135H, 00013DH 000145H, 00014DH ■ Functions of the PDUT The PPG duty setting register sets the duty of the PPG output waveform. When the value matches with the 16-bit counter of the PPG, the PPG output polarity is inverted. The PPG output pulse width is the value obtained by multiplying "the count clock cycle" by "the PDUT set value + 1" count. The PDUT values should be set as "PCSR > PDUT". Setting the register values as "PCSR < PDUT" results in undefined PPG output. Setting the PPG cycle setting and PPG duty setting registers to the same value produces all "H" output with normal polarity (OSEL=0) or all "L" output with inverted polarity (OSEL=1). To write to this register, access it using half word (16-bit) or word (32-bit) data. 687 CHAPTER 23 PPG (PROGRAMMABLE PULSE GENERATOR) 23.2.4 PPG Timer Register (PTMR) The PPG timer register (PTMR) is used to read the count value. ■ Configuration of the PPG Timer Register (PTMR) Figure 23.2-5 Configuration of the PPG Timer Register PTMR (Upper) Address: 000110H, 000118H bit15 000120H, 000128H D15 000130H, 000138H 000140H, 000148H 14 13 12 11 10 9 8 D14 D13 D12 D11 D10 D09 D08 Read/Write (R) (R) (R) (R) (R) (R) (R) (R) Initial value (1) (1) (1) (1) (1) (1) (1) (1) bit7 6 5 4 3 2 1 0 D07 D06 D05 D04 D03 D02 D01 D00 Read/Write (R) (R) (R) (R) (R) (R) (R) (R) Initial value (1) (1) (1) (1) (1) (1) (1) (1) PTMR (Lower) Address: 000111H, 000119H 000121H, 000129H 000131H, 000139H 000141H, 000149H ■ Functions of the PTMR The PPG timer register (PTMR) is a register from which the count value is read. To read a value from this register, access it using half word (16-bit) data. Using a byte data cannot read correctly. 688 CHAPTER 23 PPG (PROGRAMMABLE PULSE GENERATOR) 23.2.5 General Control Register 10 (GCN10) General control register 10 (GCN10) selects the PPG0 to PPG3 trigger input source. ■ Configuration of General Control Register 10 (GCN10) Figure 23.2-6 Configuration of General Control Register 10 (GCN10) GCN10 (Upper) bit15 Address: 000100H 14 13 12 11 TSEL33 to TSEL30 10 9 8 TSEL23 to TSEL20 Read/Write (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Initial value (0) (0) (1) (1) (0) (0) (1) (0) bit7 6 5 4 3 2 1 0 GCN10 (Lower) Address: 000101H TSEL13 to TSEL10 TSEL03 to TSEL00 Read/Write (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Initial value (0) (0) (0) (1) (0) (0) (0) (0) ■ Functions of the GCN10 [bit15 to bit12] TSEL33 to TSEL30: PPG ch.3 input select Table 23.2-10 Selecting the PPG ch.3 Trigger Input TSEL33 to TSEL30 PPG ch.3 trigger input bit15 bit14 bit13 bit12 0 0 0 0 GCN20 EN0 bit 0 0 0 1 GCN20 EN1 bit 0 0 1 0 GCN20 EN2 bit 0 0 1 1 GCN20 EN3 bit [Initial value] 0 1 0 0 16-bit reload timer ch.0 0 1 0 1 16-bit reload timer ch.1 0 1 1 x Setting prohibited 1 0 0 0 External trigger 0 1 0 0 1 External trigger 1 1 0 1 0 External trigger 2 1 0 1 1 External trigger 3 1 1 x x Setting prohibited 689 CHAPTER 23 PPG (PROGRAMMABLE PULSE GENERATOR) [bit11 to bit8] TSEL23 to TSEL20: PPG ch.2 trigger input select Table 23.2-11 Selecting the PPG ch.2 Trigger Input TSEL23 to TSEL20 PPG ch.2 trigger input bit11 bit10 bit9 bit8 0 0 0 0 GCN20 EN0 bit 0 0 0 1 GCN20 EN1 bit 0 0 1 0 GCN20 EN2 bit [Initial value] 0 0 1 1 GCN20 EN3 bit 0 1 0 0 16-bit reload timer ch.0 0 1 0 1 16-bit reload timer ch.1 0 1 1 x Setting prohibited 1 0 0 0 External trigger 0 1 0 0 1 External trigger 1 1 0 1 0 External trigger 2 1 0 1 1 External trigger 3 1 1 x x Setting prohibited [bit7 to bit4] TSEL13 to TSEL10: PPG ch.1 trigger input select Table 23.2-12 Selecting the PPG ch.1 Trigger Input TSEL13 to TSEL10 PPG ch.1 trigger input 690 bit7 bit6 bit5 bit4 0 0 0 0 GCN20 EN0 bit 0 0 0 1 GCN20 EN1 bit [Initial value] 0 0 1 0 GCN20 EN2 bit 0 0 1 1 GCN20 EN3 bit 0 1 0 0 16-bit reload timer ch.0 0 1 0 1 16-bit reload timer ch.1 0 1 1 x Setting prohibited 1 0 0 0 External trigger 0 1 0 0 1 External trigger 1 1 0 1 0 External trigger 2 1 0 1 1 External trigger 3 1 1 x x Setting prohibited CHAPTER 23 PPG (PROGRAMMABLE PULSE GENERATOR) [bit3 to bit0] TSEL03 to TSEL00: PPG ch.0 trigger input select Table 23.2-13 Selecting the PPG ch.0 Trigger Input TSEL03 to TSEL00 PPG ch.0 trigger input bit3 bit2 bit1 bit0 0 0 0 0 GCN20 EN0 bit [Initial value] 0 0 0 1 GCN20 EN1 bit 0 0 1 0 GCN20 EN2 bit 0 0 1 1 GCN20 EN3 bit 0 1 0 0 16-bit reload timer ch.0 0 1 0 1 16-bit reload timer ch.1 0 1 1 x Setting prohibited 1 0 0 0 External trigger 0 1 0 0 1 External trigger 1 1 0 1 0 External trigger 2 1 0 1 1 External trigger 3 1 1 x x Setting prohibited 691 CHAPTER 23 PPG (PROGRAMMABLE PULSE GENERATOR) 23.2.6 General Control Register 11 (GCN11) General control register 11 (GCN11) selects the PPG4 to PPG7 trigger input source. ■ Configuration of the General Control Register 11 (GCN11) Figure 23.2-7 Configuration of the General Control Register 11 (GCN11) GCN11 (Upper) bit15 Address: 000104H 14 13 12 11 TSEL73 to TSEL70 10 9 8 TSEL63 to TSEL60 Read/Write (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Initial value (0) (0) (1) (1) (0) (0) (1) (0) bit7 6 5 4 3 2 1 0 GCN11 (Lower) Address: 000105H TSEL53 to TSEL50 TSEL43 to TSEL40 Read/Write (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Initial value (0) (0) (0) (1) (0) (0) (0) (0) ■ Functions of the GCN11 [bit15 to bit12] TSEL73 to TSEL70: PPG ch.7 trigger input select Table 23.2-14 Selecting the PPG ch.7 Trigger Input TSEL73 to TSEL70 PPG ch.7 trigger input 692 bit15 bit14 bit13 bit12 0 0 0 0 GCN21 EN0 bit 0 0 0 1 GCN21 EN1 bit 0 0 1 0 GCN21 EN2 bit 0 0 1 1 GCN21 EN3 bit [Initial value] 0 1 0 0 16-bit reload timer ch.2 0 1 0 1 16-bit reload timer ch.3 0 1 1 x Setting prohibited 1 x x x Setting prohibited CHAPTER 23 PPG (PROGRAMMABLE PULSE GENERATOR) [bit11 to bit8] TSEL63 to TSEL60: PPG ch.6 trigger input select Table 23.2-15 Selecting the PPG ch.6 Trigger Input TSEL63 to TSEL60 PPG ch.6 trigger input bit11 bit10 bit9 bit8 0 0 0 0 GCN21 EN0 bit 0 0 0 1 GCN21 EN1 bit 0 0 1 0 GCN21 EN2 bit [Initial value] 0 0 1 1 GCN21 EN3 bit 0 1 0 0 16-bit reload timer ch.2 0 1 0 1 16-bit reload timer ch.3 0 1 1 x Setting prohibited 1 x x x Setting prohibited [bit7 to bit4] TSEL53 to TSEL50: PPG ch.5 trigger input select Table 23.2-16 Selecting the PPG ch.5 Trigger Input TSEL53 to TSEL50 PPG ch.5 trigger input bit7 bit6 bit5 bit4 0 0 0 0 GCN21 EN0 bit 0 0 0 1 GCN21 EN1 bit [Initial value] 0 0 1 0 GCN21 EN2 bit 0 0 1 1 GCN21 EN3 bit 0 1 0 0 16-bit reload timer ch.2 0 1 0 1 16-bit reload timer ch.3 0 1 1 x Setting prohibited 1 x x x Setting prohibited 693 CHAPTER 23 PPG (PROGRAMMABLE PULSE GENERATOR) [bit3 to bit0] TSEL43 to TSEL40: PPG ch.4 trigger input select Table 23.2-17 Selecting the PPG ch.4 Trigger Input TSEL43 to TSEL40 PPG ch.4 trigger input 694 bit3 bit2 bit1 bit0 0 0 0 0 GCN21 EN0 bit [Initial value] 0 0 0 1 GCN21 EN1 bit 0 0 1 0 GCN21 EN2 bit 0 0 1 1 GCN21 EN3 bit 0 1 0 0 16-bit reload timer ch.2 0 1 0 1 16-bit reload timer ch.3 0 1 1 x Setting prohibited 1 x x x Setting prohibited CHAPTER 23 PPG (PROGRAMMABLE PULSE GENERATOR) 23.2.7 General Control Register 2 (GCN20,GCN21) General control register 2 (GCN20,GCN21) is used to generate an activation trigger by software. This register can activate 4 channels at a same time. ■ Configuration of the General Control Register 2 (GCN20,GCN21) Figure 23.2-8 Configuration of the General Control Register 2 (GCN20,GCN21) GCN20,GCN21 bit7 6 5 4 Address: Reserved Reserved Reserved Reserved GCN20: 000103H GCN21: 000107H 3 2 1 0 EN3 EN2 EN1 EN0 Read/Write (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Initial value (−) (−) (−) (−) (0) (0) (0) (0) ■ Functions of the GCN20,GCN21 If the EN0 to EN3 bits in GCN20, GCN21 register are selected as the activation trigger source by general control register 1 (GCN1), the written value of EN0 to EN3 is passed to the PPG trigger input as it is. The trigger input edge is selected by bit7 and bit6 (EGS1 and EGS0) in the control status register (PCNL). Multiple PPG timer channels can be activated at the same time by using this register. Be sure to write "0" to bit7 to bit4 in this register. 695 CHAPTER 23 PPG (PROGRAMMABLE PULSE GENERATOR) 23.3 PPG Operation This section describes the operation of the PPG. There are two PPG output operation modes: PWM operation and one-shot operation modes. ■ PPG Operation The PWM operation mode outputs a continuous stream of pulses; the one-shot operation mode outputs a single pulse. The items covered in this section are shown below: • PWM operation • One-shot operation • Interrupts • All "L" and all "H" PPG outputs 696 CHAPTER 23 PPG (PROGRAMMABLE PULSE GENERATOR) 23.3.1 PWM Operation The PWM operation mode outputs a continuous stream of pulses. ■ PWM Operation The PWM operation mode outputs a continuous stream of pulses from the time at which an activation trigger is detected. The output pulse cycle can be controlled by changing the value in the cycle setting register (PCSR). The duty can also be controlled by changing the value in the duty setting register (PDUT). When setting the output pulse cycle and duty ratio, be sure to write data to the PDUT register after writing data to the PCSR register. ■ PPG Output Timing When the activation trigger is detected, the cycle setting value is loaded into the counter and the downcounter starts counting. When the counter value and the duty setting value (PDUT) match, the PPG output polarity is inverted. If the counter causes an underflow, the value set in the PCSR register (cycle) is loaded into the counter and the PPG output polarity is inverted. When the trigger restarting has been disabled, a trigger input causes no effect on PPG output (Refer to Figure 23.3-1). When the trigger restarting has been enabled, a trigger input causes PCSR value to be loaded into the counter even during counting. Then the counting is continued (Refer to Figure 23.3-2). [Equations for calculating the PPG output pulse cycle and duty ratio] Pm = T(m+1) µs Pn = T(n+1) µs Pm: Output pulse cycle Pn: Output pulse width T: Count clock cycle m: Value set in the cycle setting register (PCSR) n: Value set in the duty setting register (PDUT) 697 CHAPTER 23 PPG (PROGRAMMABLE PULSE GENERATOR) ● PWM operation timing example 1 (Trigger restarting disabled, PPG output: Normal polarity) Figure 23.3-1 PWM Operation Timing Example 1 (Trigger Restarting Disabled, PPG Output: Normal Polarity) Rising edge detected Restarted by the trigger Activation trigger Count value m n Time 0 PPG output Pn Pm Pm: Output pulse cycle m: PCSR value Pn: Output pulse "H" width n: PDUT value ● PWM operation timing example 2 (Trigger restarting enabled, PPG output: Normal polarity) Figure 23.3-2 PWM Operation Timing Example 2 (Trigger Restarting Enabled, PPG Output: Normal Polarity) Rising edge detected Restarted by the trigger Activation trigger Count value m n Time 0 PPG output Pn Pm Pm: Output pulse cycle m: PCSR value 698 Pn: Output pulse "H" width n: PDUT value CHAPTER 23 PPG (PROGRAMMABLE PULSE GENERATOR) 23.3.2 One-Shot Operation The one-shot operation mode outputs a single pulse. ■ One-Shot Operation The one-shot operation mode outputs a single pulse upon detection of an activation trigger. The output pulse cycle can be controlled by changing the value in the cycle setting register (PCSR). The output pulse width can also be controlled by changing the value in the duty setting register (PDUT). When setting the output pulse cycle and width (duty ratio), be sure to write data to the PDUT register after writing data to the PCSR register. One-shot operation mode also depends on whether restarting has been disabled or enabled. When restarting is enabled, PCSR value is reloaded to the counter at the time of receiving a restarting trigger. Then the counting is continued ● One-shot operation timing example when Trigger restarting is disabled, PPG output: Normal polarity) Figure 23.3-3 One-Shot Operation Timing Example When Trigger Restarting is Disabled Activation trigger Rising edge detected Trigger ignored Counter value m n Time 0 PPG output Pn Pm Pm = T(m+1) Pn = T(n+1) Pm: Output pulse cycle Pn: Output pulse "H" width T: Count clock cycle m: PCSR value n: PDUT value 699 CHAPTER 23 PPG (PROGRAMMABLE PULSE GENERATOR) ● One-shot operation timing example when trigger restarting is enabled (Normal polarity) Figure 23.3-4 One-Shot Operation Timing Example When Trigger Restarting is Enabled Activation trigger Rising edge detected Restarted by trigger Counter value m n Time 0 PPG output Pn Pm Pm = T(m+1) Pn = T(n+1) 700 Pm: Output pulse cycle Pn: Output pulse "H" width T: Count clock cycle m: PCSR value n: PDUT value CHAPTER 23 PPG (PROGRAMMABLE PULSE GENERATOR) 23.3.3 Interrupts Interrupt resources generated in PPG are followings: • Activation of the PPG timer (software trigger or external trigger) • Occurrence of an underflow • Occurrence of a duty match • Occurrence of an underflow or duty match ■ Interrupt Operation The interrupt request signal to the CPU is generated by setting bits in the control status register (PCNL) as follows: • Use bit5 as the interrupt enable bit (IREN) to enable interrupts. • Use bit3 and bit2 as the interrupt source select bits (IRS1 and IRS0) to select the desired interrupt source. • Bit (IRQF) is the interrupt request flag and indicates the interrupt occurrence status. Figure 23.3-5 shows an interrupt timing diagram. Figure 23.3-5 Interrupt Source and Timing Activation trigger 2.5T max* Load Clock Count value X 0003 H 0002 H 0001 H 0000 H 0003 H PPG output Interrupt Effective edge Duty match Counter borrow *: It takes up to 2.5T (T: count clock cycle) from applying the activation trigger to loading the count value. 701 CHAPTER 23 PPG (PROGRAMMABLE PULSE GENERATOR) 23.3.4 All "L" and All "H" PPG Outputs This section provides examples of producing all "L" and all "H" PPG outputs. ■ All "L" or All "H" Output Writing "1" to bit9, or the PPG output mask select bit (PGMS), in the control status register (PCNH) masks the PPG output to the "L" level (normal polarity) or "H" level (inverted polarity) regardless of the mode, cycle, and duty settings. Figure 23.3-6 Example of Producing All "L" PPG Output PPG output Decrease the duty value. Use an interrupt upon an borrow to write "1" to the PGMS (mask bit). Using the borrow interrupt to write "0" to the PGMS can output the PPG waveform without hazard output. Figure 23.3-7 Example of Producing All "H" PPG Output PPG output Increase the duty value 702 Use an interrupt upon a compare match to set the duty setting register to the same value as the cycle setting register value. CHAPTER 23 PPG (PROGRAMMABLE PULSE GENERATOR) 23.3.5 Activation of Multiple Channels Multiple channels can be activated concurrently by selecting the start trigger by using the general control register 10 (GCN10). An example of activation using GCN20 is given below. ■ Activating Multiple PPG Channels Using Software [Setting procedure] (1) Set the cycle setting register (PCSR) to the cycle setting value. (2) Set the duty setting register (PDUT) to the duty ratio value. Note: Be sure to write data to the PDUT register after writing data to the PCSR register. (3) Set the GCN10 register to determine the trigger input source for each channel you want to activate. ch.0: EN0 ch.1: EN1 ch.2: EN2 ch.3: EN3 (4) Set the control status registers (PCNL, PCNH) corresponding to the channels to be activated. Table 23.3-1 Setting Example of Activate Channel Bit Function No. Abbreviation Value 15 CNTE 1 Timer operation enabled 14 STGR 0 STGR is not activated because GCN20 is used. 13 MDSE 0 PWM operation 12 RTRG 0 Reactivation disabled 11 CKS1 0 10 CKS0 0 9 PGMS 0 Output not masked 8 − 0 Unused bit 7 EGS1 0 6 EGS0 1 5 IREN 1 Interrupt enabled 4 IRQF 0 Interrupt factor cleared 3 IRS1 0 2 IRS0 1 0 OSEL 0 Count clock: FCLKP/1 (No division) Activation on rising edge Interrupt request occurs due to counter borrow Normal polarity (5) Write data to general control register (GCN20) to generate the activation trigger. To activate ch.0 and ch.1 at the same time, write "1" to the EN0 and EN1 bits in the GCN20 register. 703 CHAPTER 23 PPG (PROGRAMMABLE PULSE GENERATOR) ■ Multiple Activation Using a Trigger from the Reload Timer In step (3) in the above setting procedure, select the 16-bit reload timer as the trigger input source. In step (5), activate the 16-bit reload timer in place of general control register 2 (GCN20). 704 CHAPTER 24 REAL TIME CLOCK This chapter describes the register structure and functions, and the operation of RTC module for the real time clock. 24.1 Register Configuration of Real Time Clock 24.2 Block Diagram of Real Time Clock 24.3 Register Details of Real Time Clock 705 CHAPTER 24 REAL TIME CLOCK 24.1 Register Configuration of Real Time Clock This section shows the register configuration of the real time clock. ■ Real Time Clock Registers Figure 24.1-1 Bit Configuration of Real Time Clock Registers WTCRH bit15 Address: 0004A2H INTE3 14 13 12 11 10 9 8 INT3 INTE2 INT2 INTE1 INT1 INTE0 INT0 Read/Write (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Initial value (0) (0) (0) (0) (0) (0) (0) (0) bit7 6 5 4 3 2 1 0 TST1 TST0 − − ST WTCRL Address: 0004A3H TST2 RUN Reserved Read/Write (R/W) (R/W) (R/W) (−) (R) (−) (−) (R/W) Initial value (0) (0) (0) (−) (0) (0) (−) (0) bit23 22 21 20 19 18 17 16 Address: 0004A5H − − − D20 D19 D18 D17 D16 Read/Write (−) (−) (−) (R/W) (R/W) (R/W) (R/W) (R/W) Initial value (−) (−) (−) (X) (X) (X) (X) (X) bit15 14 13 12 11 10 9 8 Address: 0004A6H D15 D14 D13 D12 D11 D10 D9 D8 Read/Write (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Initial value (X) (X) (X) (X) (X) (X) (X) (X) bit7 6 5 4 3 2 1 0 Address: 0004A7H D7 D6 D5 D4 D3 D2 D1 D0 Read/Write (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Initial value (X) (X) (X) (X) (X) (X) (X) (X) bit31 30 29 28 27 26 25 24 − − − H4 H3 H2 H1 H0 Read/Write (−) (−) (−) (R/W) (R/W) (R/W) (R/W) (R/W) Initial value (−) (−) (−) (X) (X) (X) (X) (X) WTBR (Upper) WTBR (Middle) WTBR (Lower) WTHR Address: 0004A8H (Continued) 706 CHAPTER 24 REAL TIME CLOCK (Continued) WTMR bit23 22 21 20 19 18 17 16 Address: 0004A9H − − M5 M4 M3 M2 M1 M0 Read/Write (−) (−) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Initial value (−) (−) (X) (X) (X) (X) (X) (X) bit15 14 13 12 11 10 9 8 − − S5 S4 S3 S2 S1 S0 Read/Write (−) (−) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Initial value (−) (−) (X) (X) (X) (X) (X) (X) WTSR Address: 0004AAH 707 CHAPTER 24 REAL TIME CLOCK 24.2 Block Diagram of Real Time Clock This section shows the block diagram of the real time clock. ■ Block Diagram of Real Time Clock Figure 24.2-1 Block Diagram of Real Time Clock Inside RTC Outside RTC 8 clock divider Oscillation clock UPDT 2 clock divider 21-bit prescaler Sub-second register ST Second counter Minute counter Hour counter 2 clock divider 6 bits Sub-second counter overflow INTE0 INT0 6 bits 5 bits Second/minute/hour register INTE1 INT1 INTE2 INT2 INTE3 INT3 IRQ 708 CHAPTER 24 REAL TIME CLOCK 24.3 Register Details of Real Time Clock This section describes the detailed register configuration of the real time clock. ■ Timer Control Register (WTCRH, WTCRL) Figure 24.3-1 Bit Configuration of the Timer Control Register (WTCRH, WTCRL) WTCRH bit15 Address: 0004A2H INTE3 14 13 12 11 10 9 8 INT3 INTE2 INT2 INTE1 INT1 INTE0 INT0 Read/Write (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Initial value (0) (0) (0) (0) (0) (0) (0) (0) bit7 6 5 4 3 2 1 0 TST1 TST0 − − ST WTCRL Address: 0004A3H TST2 RUN Reserved Read/Write (R/W) (R/W) (R/W) (−) (R) (−) (−) (R/W) Initial value (0) (0) (0) (−) (0) (0) (−) (0) −: Unused bit [WTCRH: bit15 to bit8] INT3 to INT0, INTE3 to INTE0: Interrupt flags and Interrupt enable bits INT0 to INT3 are the interrupt flags. They are set when the sub-second counter, second counter, minute counter, and hour counter overflow respectively. If the INT bit is set while the corresponding INTE bit is "1", the interrupt signal is generated. These flags are intended to generate the interrupt signal every sub-second/second/minute/hour/day. Writing "0" to the INT bits clears the flags and writing "1" does not have any effect. Any read-modify-write (RMW) instruction performed on the INT bit results reading "1". Table 24.3-1 Interrupt Flags and Interrupt Enable Bits Interrupt Factor Interrupt enable bit Interrupt flag Second interrupt Sub-second counter overflow INTE0 INT0 Minute interrupt Second counter overflow INTE1 INT1 Hour interrupt Minute counter overflow INTE2 INT2 Day interrupt Hour counter overflow INTE3 INT3 [WTCRL: bit7 to bit5] TST2 to TST0: Test bits These bits are prepared for the device test. In any user applications, they should be set to "000B". [WTCRL: bit4] Unused bit 709 CHAPTER 24 REAL TIME CLOCK [WTCRL: bit3] RUN: Flag This bit can be read only and if "1" is read it indicates that the RTC module is actively operating. [WTCRL: bit2] Reserved bit This bit is a reserved bit. Write always "0". [WTCRL: bit1] Unused bit [WTCRL: bit0] ST: Start bit When the ST bit is set to "1", the watch timer loads second/minute/hour values from the registers and starts its operation. When it is reset to "0", all the counters and the prescalers are reset to "0" and halts. This bit can also be used for updating the counter values. Set ST bit to "0", wait for RUN to go to "0", update the counter values and set ST bit to "1". 710 CHAPTER 24 REAL TIME CLOCK ■ Sub-second Registers Figure 24.3-2 Bit Configuration of Sub-second Registers WTBR (Upper) bit23 22 21 20 19 18 17 16 Address: 0004A5H − − − D20 D19 D18 D17 D16 Read/Write (−) (−) (−) (R/W) (R/W) (R/W) (R/W) (R/W) Initial value (−) (−) (−) (X) (X) (X) (X) (X) bit7 6 5 4 3 2 1 0 Address: 0004A6H D15 D14 D13 D12 D11 D10 D9 D8 Read/Write (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Initial value (X) (X) (X) (X) (X) (X) (X) (X) bit15 14 13 12 11 10 9 8 Address: 0004A7H D7 D6 D5 D4 D3 D2 D1 D0 Read/Write (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Initial value (X) (X) (X) (X) (X) (X) (X) (X) WTBR (Middle) WTBR (Lower) −: Unused bit [bit23 to bit21] Unused bits [bit20 to bit0] D20 to D0 The sub-second register stores the reload value for the 21-bit prescaler. This value is reloaded after the reload counter reaches "0". Note that when modifying all three bytes, make sure the reload operation will not be performed in between the write instructions. Otherwise the 21-bit prescaler loads the incorrect value of the combination of new data and old data bytes. It is generally recommended that the sub-second registers are updated while the ST bit is "0". If the sub-second registers are set to "0", the 21-bit prescaler does not operate at all. The clock supplied to RTC has the frequency which equals the 8 clock divider (MB91461) or the 2 clock divider (MB91F467R) of the oscillation. And the 2 divider of the RTC clock (= 16 divider) is the counter clock of the 21-bit prescaler. 711 CHAPTER 24 REAL TIME CLOCK WTBR resister set value for generating 1 second is as follows. Table 24.3-2 WTBR Resister Setting Value (MB91461) Oscillation clock (MHz) Oscillation clock cycle (ns) 21-bit prescaler clock cycle (µs) WTBR set value WTBR set value (dec) (hex) 9.00 111.11 1.78 281249 044AA1 10.00 100.00 1.60 312499 04C4B3 12.00 83.33 1.33 374999 05B8D7 14.00 71.43 1.14 437499 06ACFB 16.00 62.50 1.00 499999 07A11F 18.00 55.56 0.89 562499 089543 20.00 50.00 0.80 624999 098967 Table 24.3-3 WTBR Resister Setting Value (MB91F467R) 712 Oscillation clock (MHz) Oscillation clock cycle (ns) 21-bit prescaler clock cycle (µs) 4 250 0.5 WTBR set value WTBR set value (dec) (hex) 999999 0F423F CHAPTER 24 REAL TIME CLOCK ■ Hour/Minute/Second Register Figure 24.3-3 Bit Configuration of Hour/Minute/Second Register WTHR bit31 30 29 28 27 26 25 24 Address: 0004A8H − − − H4 H3 H2 H1 H0 Read/Write (−) (−) (−) (R/W) (R/W) (R/W) (R/W) (R/W) Initial value (−) (−) (−) (X) (X) (X) (X) (X) bit23 22 21 20 19 18 17 16 Address: 0004A9H − − M5 M4 M3 M2 M1 M0 Read/Write (−) (−) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Initial value (−) (−) (X) (X) (X) (X) (X) (X) bit15 14 13 12 11 10 9 8 − − S5 S4 S3 S2 S1 S0 Read/Write (−) (−) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Initial value (−) (−) (X) (X) (X) (X) (X) (X) WTMR WTSR Address: 0004AAH −: Unused bit The hour/minute/second registers store the time information. It is a binary representation of the hour, minute and second. Reading these registers simply returns the counter values. Since there are three byte-registers, make sure the obtained values from the registers are consistent. i.e. Obtained value of "1 hour, 59 minute, 59 second" could be "0 hour, 59 minute, 59 second" or "1 hour, 0 minute, 0 second" or "2 hour, 0 minute, 0 second". If reading is done at the moment of the counter overflow, it is possible to read wrong values. So reading should be either triggered by an interrupt of the RTC or the following procedure should be followed: 1. Clear interrupt flags (INT) of the RTC module 2. Read registers 3. If flags are set after reading (time overflow occurred during reading), read again. 713 CHAPTER 24 REAL TIME CLOCK 714 CHAPTER 25 A/D CONVERTER This chapter describes the overview, register configuration and function, and operation of the A/D converter. 25.1 Overview of A/D Converter 25.2 Block Diagram of A/D Converter 25.3 Registers of A/D Converter 25.4 Operation of A/D Converter 715 CHAPTER 25 A/D CONVERTER 25.1 Overview of A/D Converter This A/D converter converts analog input voltage to digital values. This section describes the overview of the A/D converter. ● Feature of A/D converter The A/D converter has the following features: • Conversion time: 1.0 µs at minimum per channel • The serial-parallel conversion method with a sample & hold circuit is used. • 10-bit resolution (switching between 8 and 10 bits.) • Analog input can be selected from 13 (MB91461) / 16 (MB91F467R) channels by software. • Conversion mode • Single conversion mode: Scan conversion mode: conversion of one selected channel. continuous conversion of multiple channels, programmable for up to 13/ 16 channels Continuous conversion mode: Repeatedly convert the specified channels. Stop conversion mode: Convert one channel then temporarily halt until the next activation. (Enables synchronization of the conversion start timing.) • Interrupt request At completion of A/D conversion, an interrupt request can be generated to the CPU. • Selectable start factor The start factor can be selected from software, external trigger (falling edge), and 16-bit reload timer ch.7 (rising edge). ● Input impedance The sampling circuit of the A/D converter is shown in the following equivalent circuit. Figure 25.1-1 Input Impedance Analog Signal source Rext ANx Analog SW Rext = Tsamp / (7 + Cin ) − Rin 716 Rin: max 1.9kΩ (AVCC ≥ 2.7V) Cin: max 14.7pF A/D Converter CHAPTER 25 A/D CONVERTER 25.2 Block Diagram of A/D Converter Figure 25.2-1 shows the block diagram of A/D converter. ■ Block Diagram of A/D Converter Figure 25.2-1 Block Diagram of A/D Converter AVRH/ AVCC AVRL AVSS D/A converter MPX Sequential comparison register Internal data bus ····· AN12 AN13* AN14* AN15* Input circuit AN0 Comparator Decoder Sample & hold circuit Data register A/D control register 0 A/D control register 1 ATGX pin Operation clock 16-bit reload timer 7 CLKP Prescaler *: MB91F467R only 717 CHAPTER 25 A/D CONVERTER 25.3 Registers of A/D Converter This section describes the register configuration and function of the A/D converter. ■ Overview of A/D Converter Registers The A/D converter has the following six types of registers. • Analog input enable register (ADER) • Control status register (ADCS1, ADCS0) • Data register (ADCR) • Conversion time set register (ADCT) • Start channel set register (ADSCH) • End channel set register (ADECH) ■ Registers Figure 25.3-1 Bit Configuration of A/D Converter ADERH (Lower) bit7 6 5 4 3 2 1 0 Address: 0001A1H − − − − − − − − Read/Write (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Initial value (0) (0) (0) (0) (0) (0) (0) (0) bit15 14 13 12 11 10 9 8 ADERL (Upper) Address: 0001A2H ADE15* ADE14* ADE13* ADE12 ADE11 ADE10 ADE9 ADE8 Read/Write (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Initial value (0) (0) (0) (0) (0) (0) (0) (0) bit7 6 5 4 3 2 1 0 ADE6 ADE5 ADE4 ADE3 ADE2 ADE1 ADE0 ADERL (Lower) Address: 0001A3H ADE7 Read/Write (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Initial value (0) (0) (0) (0) (0) (0) (0) (0) bit15 14 13 12 11 10 9 8 Address: 0001A4H BUSY INT INTE PAUS STS1 STS0 STRT reserved ADCS1 Read/Write (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Initial value (0) (0) (0) (0) (0) (0) (0) (0) *: MB91F467R only (Continued) 718 CHAPTER 25 A/D CONVERTER (Continued) ADCS0 bit7 Address: 0001A5H MD1 6 5 4 3 2 1 0 MD0 S10 ACH4 ACH3 ACH2 ACH1 ACH0 Read/Write (R/W) (R/W) (R/W) (R) (R) (R) (R) (R) Initial value (0) (0) (0) (0) (0) (0) (0) (0) bit15 14 13 12 11 10 9 8 Address: 0001A6H − − − − − − D9 D8 Read/Write (−) (−) (−) (−) (−) (−) (R) (R) Initial value (−) (−) (−) (−) (−) (−) (X) (X) bit7 6 5 4 3 2 1 0 Address: 0001A7H D7 D6 D5 D4 D3 D2 D1 D0 Read/Write (R) (R) (R) (R) (R) (R) (R) (R) Initial value (X) (X) (X) (X) (X) (X) (X) (X) bit15 14 13 12 11 10 9 8 Address: 0001A8H CT5 CT4 CT3 CT2 CT1 CT0 ST9 ST8 Read/Write (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Initial value (0) (0) (0) (1) (0) (0) (0) (0) bit7 6 5 4 3 2 1 0 Address: 0001A9H ST7 ST6 ST5 ST4 ST3 ST2 ST1 ST0 Read/Write (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Initial value (0) (0) (1) (0) (1) (1) (0) (0) bit15 14 13 12 11 10 9 8 − − − − ANS3 ANS2 ANS1 ANS0 Read/Write (−) (−) (−) (−) (R/W) (R/W) (R/W) (R/W) Initial value (−) (−) (−) (−) (0) (0) (0) (0) bit7 6 5 4 3 2 1 0 − − − − ANE3 ANE2 ANE1 ANE0 Read/Write (−) (−) (−) (−) (R/W) (R/W) (R/W) (R/W) Initial value (−) (−) (−) (−) (0) (0) (0) (0) ADCR1 ADCR0 ADCT1 ADCT0 ADSCH Address: 0001AAH ADECH Address: 0001ABH 719 CHAPTER 25 A/D CONVERTER 25.3.1 Analog Input Enable Register (ADER) The ADER bits correspond to the pins used for analog input. Always set these bits to "1". ■ A/D Enable Register (ADER) Figure 25.3-2 Bit Configuration of A/D Enable Register (ADER) ADERH (Lower) bit7 6 5 4 3 2 1 0 Address: 0001A1H − − − − − − − − Read/Write (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Initial value (0) (0) (0) (0) (0) (0) (0) (0) bit15 14 13 12 11 10 9 8 ADERL (Upper) Address: 0001A2H ADE15* ADE14* ADE13* ADE12 ADE11 ADE10 ADE9 ADE8 Read/Write (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Initial value (0) (0) (0) (0) (0) (0) (0) (0) bit7 6 5 4 3 2 1 0 ADE6 ADE5 ADE4 ADE3 ADE2 ADE1 ADE0 ADERL (Lower) Address: 0001A3H ADE7 Read/Write (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Initial value (0) (0) (0) (0) (0) (0) (0) (0) *: MB91F467R only [bit7 to bit0] Reserved bits Reserved bits. Always set them to "0". [bit15 to bit0] ADE15 to ADE0: A/D input enable (ADE15 to ADE13 are supported in MB91F467R only) Table 25.3-1 A/D Input Enable ADE Function 0 General-purpose port [Initial value] 1 Analog input These bits are initialized to "00000000H" when reset. Always set these bits to "1" for the start channel and end channel of this register. 720 CHAPTER 25 A/D CONVERTER 25.3.2 A/D Control Status Register (ADCS) The A/D control status register (ADCS) is used to control the A/D converter and to indicate the status. Do not update the ADCS register during A/D converting. ■ A/D Control Status Register 1 (ADCS1) Figure 25.3-3 Bit Configuration of A/D Control Status Register 1 (ADCS1) ADCS1 bit15 14 13 12 11 10 9 8 Address: 0001A4H BUSY INT INTE PAUS STS1 STS0 STRT reserved Read/Write (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Initial value (0) (0) (0) (0) (0) (0) (0) (0) [bit7] BUSY: Busy flag and stop Table 25.3-2 BUSY (Busy Flag and Stop) BUSY Function Reading A/D converter operation indication bit. Set on activation of A/D conversion and cleared on completion of conversion for last channel. Writing Writing 0 to this bit during A/D conversion forcibly terminates conversion. Use to forcibly terminate in continuous and stop modes. Bits for operation indication cannot be set to "1". Read-modify-write (RMW) instructions read the bit as "1". Cleared on the completion of A/D conversion for the last channel in single conversion mode. In continuous and stop mode, the flag is not cleared until conversion is terminated by writing "0". This bit is initialized to "0" by a reset. Note: Do not specify forcible termination and software activation (BUSY = 0 and STRT = 1) at the same time. 721 CHAPTER 25 A/D CONVERTER [bit6] INT: Interrupt This bit is set when conversion data is written in ADCR. If bit5 (INTE) is "1" when this bit is set, an interrupt request is generated. This bit is cleared by writing "0". This bit is initialized to "0" by a reset. If DMA is used, this bit is cleared when DMA transfer completes. Note: Only clear this bit by writing "0" when A/D conversion is halted. [bit5] INTE: Interrupt enable This bit enables or disables the conversion completion interrupt. Table 25.3-3 INTE (Interrupt Enable) INTE Function 0 Disable interrupt [Initial value] 1 Enable interrupt This bit is initialized to "0" by a reset. [bit4] PAUS: A/D converter pause This bit is set when A/D conversion temporarily halts. The A/D converter has only one register to store the conversion result. Therefore the previous conversion result is lost if it is not transferred by DMA when performing continuous conversion. To avoid this problem, the next conversion data is not stored in the data register until the previous value has been transferred by DMA. A/D conversion halts during this time. A/D conversion restarts when DMA transfer completes. This bit is only meaningful when using DMA. - Cleared only by writing "0". (not cleared by DMA transfer completion.) Unable to be cleared during waiting for DMA transferred. - See the description of the conversion data protection function in the section "25.4 Operation of A/D Converter". - This bit is initialized to "0" when a reset. 722 CHAPTER 25 A/D CONVERTER [bit3, bit2] STS1 and STS0: A/D Start source select These bits are initialized to "00B" when a reset. Setting these bits selects the A/D start factor. Table 25.3-4 STS1 and STS0 (A/D Start Source Select) STS1 STS0 Function 0 0 Start by software [Initial value] 0 1 Start by external pin trigger or by software 1 0 Start by 16-bit reload timer or by software 1 1 Start by external pin trigger, by 16-bit reload timer or by software In the mode in which two or more A/D conversion start factors are used, A/D conversion is started using the A/D conversion start factor that occurs first. The setting of the start source changes immediately after these bits are rewritten. Therefore it is important to pay attention to rewriting during A/D converting. - The external pin trigger detects a falling edge. If the external trigger is selected by writing these bits when the external trigger input level is "L", the A/D may start. - When 16-bit reload timer is selected, 16-bit reload timer 7 output is selected and a rising edge of the 16-bit reload timer output is detected. Refer to "CHAPTER 19 16-BIT RELOAD TIMER" for the order of A/D setting and timer setting. [bit1] STRT: Start A/D converter is started by writing "1" to this bit (start by software). Write "1" again to restart. This bit is initialized to "0" by a reset. Restart by setting this bit is ignored in the continuous mode or the stop mode. Check BUSY bit before writing "1" (Clear BUSY bit before a restart). Do not perform start by software and forced stop concurrently (STRT = 1, BUSY = 0). [bit0] Reserved bit Always set this bit to "0". 723 CHAPTER 25 A/D CONVERTER ■ A/D Control Status Register 0 (ADCS0) Figure 25.3-4 Bit Configuration of A/D Control Status Register 0 (ADCS0) ADCS0 bit7 Address: 0001A5H MD1 6 5 4 3 2 1 0 MD0 S10 ACH4 ACH3 ACH2 ACH1 ACH0 Read/Write (R/W) (R/W) (R/W) (R) (R) (R) (R) (R) Initial value (0) (0) (0) (0) (0) (0) (0) (0) [bit7, bit6] MD1, MD0: A/D converter mode set MD1 and MD0 bits set the operation mode. These bits are initialized to "00B" by a reset. Table 25.3-5 MD1, MD0 (A/D Converter Mode Set) MD1 MD0 Operation mode 0 0 Single mode: Disabled restart during operation [Initial value] 0 1 Single mode: Disabled restart during operation 1 0 Continuous mode: Disabled restart during operation 1 1 Stop mode: Disabled restart during operation • Single mode Continuous A/D conversion from selected channel(s) ANS4 to ANS0 to selected channel(s) ANE4 to ANE0 with a pause after every conversion cycle. • Continuous mode Repeated A/D conversion cycles from selected channels ANS4 to ANS0 to selected channels ANE4 to ANE0. • Stop mode A/D conversion for each channel from selected channels ANS4 to ANS0 to selected channels ANE4 to ANE0, followed by a pause. Restart is determined by the occurrence of a start source. • When A/D conversion is started in continuous mode or stop mode, conversion operation continued until forcibly stopped by the BUSY bit. • Conversion is forcibly stopped by writing "0" to the BUSY bit. • Conversion after forcible stop starts from selected channel(s) ANS4 to ANS0. • All restarts are disabled for any of the timer, external trigger and software start sources in single, continuous and stop modes. [bit5] S10 This bit selects the conversion resolution. When this bit is set to "0", 10-bit A/D conversion is selected, otherwise, 8-bit A/D conversion is selected and ADCR0 stores the result. This bit is initialized to "0" by a reset. 724 CHAPTER 25 A/D CONVERTER [bit4 to bit0] ACH4 to ACH0: Analog convert select channel These bits represent the channel currently being A/D converted. These bits are initialized to "00000B" by a reset. Table 25.3-6 Conversion Channel ACH4 ACH3 ACH2 ACH1 ACH0 Conversion channel 0 0 0 0 0 AN0 0 0 0 0 1 AN1 0 0 0 1 0 AN2 0 0 0 1 1 AN3 0 0 1 0 0 AN4 0 0 1 0 1 AN5 0 0 1 1 0 AN6 0 0 1 1 1 AN7 0 1 0 0 0 AN8 0 1 0 0 1 AN9 0 1 0 1 0 AN10 0 1 0 1 1 AN11 0 1 1 0 0 AN12 0 1 1 0 1 AN13* 0 1 1 1 0 AN14* 0 1 1 1 1 AN15* *: MB91F467R only Table 25.3-7 Function ACH Function Reading These bits represent the channel currently being converted during A/D conversion (BUSY bit = 1) and represent the forcibly stopped channel when a forcibly stop occurs with BUSY bit = 0. Writing Writing to these bits are ignored. 725 CHAPTER 25 A/D CONVERTER 25.3.3 Data Register (ADCR1, ADCR0) Data register (ADCR1, ADCR0) stores the digital value of the conversion result from the A/D converter. ADCR0 stores the lower-order 8 bits and ADCR1 stores the higher-order 2 bits of the conversion result. The register value is updated at the completion of each conversion. The register normally stores the result of the previous conversion. ■ Data Register (ADCR1, ADCR0) Figure 25.3-5 Bit Configuration of Data Register (ADCR1, ADCR0) ADCR1 bit15 14 13 12 11 10 9 8 Address: 0001A6H − − − − − − D9 D8 Read/Write (−) (−) (−) (−) (−) (−) (R) (R) Initial value (−) (−) (−) (−) (−) (−) (X) (X) bit7 6 5 4 3 2 1 0 Address: 0001A7H D7 D6 D5 D4 D3 D2 D1 D0 Read/Write (R) (R) (R) (R) (R) (R) (R) (R) Initial value (X) (X) (X) (X) (X) (X) (X) (X) ADCR0 Bit15 to bit10 of ADCR1 are read as "000000B". The A/D converter has a conversion data protection function. See the section "25.4 Operation of A/D Converter". 726 CHAPTER 25 A/D CONVERTER 25.3.4 Conversion Time Setting Register (ADCT) A/D conversion time setting register (ADCT) controls the sampling period and the comparison period of the analog input. The A/D conversion time is set by this ADCT register. Do not write to ADCT register during a A/D conversion operation. ■ Conversion Time Setting Register Figure 25.3-6 Bit Configuration of Conversion Time Setting Register ADCT1 bit15 14 13 12 11 10 9 8 CT5 CT4 CT3 CT2 CT1 CT0 ST9 ST8 Read/Write (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Initial value (0) (0) (0) (1) (0) (0) (0) (0) bit7 6 5 4 3 2 1 0 ST7 ST6 ST5 ST4 ST3 ST2 ST1 ST0 Read/Write (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Initial value (0) (0) (1) (0) (1) (1) (0) (0) Address: 0001A8H ADCT0 Address: 0001A9H [bit15 to bit10] CT5 to CT0: A/D comparison time set These bits specify the clock divider value of the comparison operation period. Set CT5 to CT0 to "000001B" for no divider (=CLKP). Do not set CT5 to CT0 to "000000B". These bits are initialized to "000100B" by a reset. Compare time = CT setting value × CLKP cycle × 10 + (4 × CLKP cycle) Note: Set CT5 to CT0 so that 660 ns or more of the compare time is obtained. 727 CHAPTER 25 A/D CONVERTER [bit9 to bit0] ST9 to ST0: A/D input sampling time set These bits specify the sampling time of the analog input. These bits are initialized to "0000101100B" by a reset. Sampling time required for A/D conversion (required sampling time) is determined depending on Rext value. Therefore set ST9 to ST0 so that the obtained time is same or longer than the required sampling time. • Calculating formula for required sampling time Required sampling time (Tsamp) = (Rext + Rin) × Cin × 7 • Calculating formula for ST9 to ST0 setting value ST9 to ST0 setting value ≥ Required sampling time (Tsamp) ÷ CLKP cycle Example: CLKP = 18 MHz, AVCC ≥ 3.0 V, Rext = 15 kΩ Tsamp = (15 × 103 + 1.9 × 103) × 14.7 × 10-12 × 7 = 1.74s → ST = 1.74 × 10-6 ÷ (1/18.0 × 106 ) = 31.3 → Set 32 ("0000100000B") or more. Note: 0000000000B, 0000000001B and 0000000010B must not be set to ST9 to ST0. Set Rext so that 400 ns or more of the sampling time is obtained. ■ Recommended Setting Value To obtain the best conversion time, the following setting value is recommended. Table 25.3-8 Recommended Setting Value CLKP (MHz) Comparison time (CT5 to CT0) Sampling time (ST9 to ST0) ADCT setting value Conversion time (µs) 9 000001B 0000001001B 0409H 1.56 + 1.00 = 2.56 18 000010B 0000010010B 0812H 1.33 + 1.00 = 2.33 (AVCC ≥ 3.0V, Rext ≤ 5.1 kΩ) 728 CHAPTER 25 A/D CONVERTER 25.3.5 Start Channel Setting Register (ADSCH) End Channel Setting Register (ADECH) Registers for setting the start channel and the end channel of the A/D conversion. Do not write to ADSCH or ADECH during A/D conversion. ■ Start Channel Setting Register (ADSCH) and End Channel Setting Register (ADECH) Figure 25.3-7 Bit Configuration of Start Channel Setting Register (ADSCH) and End Channel Setting Register (ADECH) ADSCH bit15 14 13 12 11 10 9 8 − − − − ANS3 ANS2 ANS1 ANS0 Read/Write (−) (−) (−) (−) (R/W) (R/W) (R/W) (R/W) Initial value (−) (−) (−) (−) (0) (0) (0) (0) bit7 6 5 4 3 2 1 0 − − − − ANE3 ANE2 ANE1 ANE0 Read/Write (−) (−) (−) (−) (R/W) (R/W) (R/W) (R/W) Initial value (−) (−) (−) (−) (0) (0) (0) (0) Address: 0001AAH ADECH Address: 0001ABH These bits specify the start channel and the end channel of the A/D conversion. When the same channel is written to ANS4 to ANS0 and ANE4 to ANE0, the conversion is performed for only one channel (single channel conversion). In a continuous mode or a stop mode, after the conversion of the channel set by these bits are completed, return to the start channel set by ANS4 to ANS0 is performed. Note: Set the start channel and the end channel so that always ANS is same or smaller than ANE. If ANS is larger than ANE, correct operation is not assured. 729 CHAPTER 25 A/D CONVERTER [bit12 to bit8] ANS4 to ANS0 (A/D start channel set) [bit4 to bit0] ANE4 to ANE0 (A/D end channel set) Table 25.3-9 Start/end Channel ANS4 ANE4 ANS3 ANE3 ANS2 ANE2 ANS1 ANE1 ANS0 ANE0 Start/end channel 0 0 0 0 0 AN0 0 0 0 0 1 AN1 0 0 0 1 0 AN2 0 0 0 1 1 AN3 0 0 1 0 0 AN4 0 0 1 0 1 AN5 0 0 1 1 0 AN6 0 0 1 1 1 AN7 0 1 0 0 0 AN8 0 1 0 0 1 AN9 0 1 0 1 0 AN10 0 1 0 1 1 AN11 0 1 1 0 0 AN12 0 1 1 0 1 AN13* 0 1 1 1 0 AN14* 0 1 1 1 1 AN15* 1 x x x x Setting disabled *: MB91F467R only Note: Please do not set the A/D start channel setting by the read-modify-write (RMW) instruction after setting the start channel to the A/D start channel setting (ANS4, ANS3, ANS2, ANS1, ANS0). The last conversion channel is read from the ANS4, ANS3, ANS2, ANS1, and ANS0 bits until the A/ D conversion operating starts. Therefore, when ANE4, ANE3, ANE2, ANE1, and ANE0 bits are set by the read-modify-write (RMW) instruction after setting the start channel to ANS4, ANS3, ANS2, ANS1, and ANS0 bits, the value of the ANE4, ANE3, ANE2, ANE1, and ANE0 bits may be overwritten. 730 CHAPTER 25 A/D CONVERTER 25.4 Operation of A/D Converter The A/D converter operates using the successive approximation method with 10-bit or 8-bit selectable resolution. This section describes the operation mode of the A/D converter. ■ A/D Conversion Data The conversion data register (ADCR0 and ADCR1) is rewritten at each completion of the conversion because this A/D converter has only one register (16-bit) for storing the conversion result. Therefore the alone A/D converter is not suitable for a continuous conversion. It is recommended to transfer the conversion data to the memory using DMA during conversion. ■ Single Mode In single mode, the analog input signals selected by the ANS bits and ANE bits are converted in order until the completion of conversion on the end channel determined by the ANE bits. A/D conversion then ends. If the start channel and end channel are the same (ANS = ANE), only a single channel conversion is performed. Examples: • ANS = 00000B, ANE = 00011B Start ⇒ AN0 ⇒ AN1 ⇒ AN2 ⇒ AN3 ⇒ (End) • ANS = 00010B, ANE = 00010B Start ⇒ AN2 ⇒ (End) ■ Continuous Mode In continuous mode, the analog input signals selected by the ANS bits and ANE bits are converted in order until the completion of conversion on the end channel determined by the ANE bits, then the converter returns to the ANS channel for analog input and repeats the process continuously. When the start and end channels are the same (ANS = ANE), conversion is performed continuously for a single channel. Examples: • ANS = 00000B, ANE = 00011B Start ⇒ AN0 ⇒ AN1 ⇒ AN2 ⇒ AN3 ⇒ AN0 ⇒ AN1 (repeat) • ANS = 00010B, ANE = 00010B Start ⇒ AN2 ⇒ AN2 ⇒ AN2 (repeat) In continuous mode, conversion is repeated until "0" is written to the BUSY bit. (Writing "0" to the BUSY bit forcibly stops the conversion operation.) Note that forcibly terminating operation halts the current conversion during mid-conversion. (If operation is forcibly terminated, the value in the conversion register is the result of the most recently completed conversion.) 731 CHAPTER 25 A/D CONVERTER ■ Stop Mode In stop mode, the analog input signals selected by the ANS bits and ANE bits are converted in order, but conversion operation pauses for each channel. The pause is released by applying another start signal. At the completion of conversion on the end channel determined by the ANE bits, the converter returns to the ANS channel for analog input signal and repeats the conversion process continuously. When the start and end channels are the same (ANS = ANE), only a single channel conversion is performed. Examples: • ANS = 00000B, ANE = 00011B Start ⇒ AN0⇒ stop ⇒ start ⇒ AN1 ⇒ stop ⇒ start ⇒ AN2 ⇒ stop ⇒ start ⇒ AN3 ⇒ stop ⇒ start ⇒ AN0 ⇒ stop ⇒ start ⇒ AN1 (repeat) • ANS = 00010B, ANE = 00010B Start ⇒ AN2 ⇒ stop ⇒ start ⇒ AN2 ⇒ stop ⇒ start ⇒ AN2 (repeat) In stop mode, the startup source is only the source determined by the STS1, STS0 bits. This mode enables synchronization of the conversion start signal. 732 CHAPTER 26 SUB CLOCK CALIBRATION UNIT This section explains the sub clock calibration unit installed in MB91F467RA and MB91F467RB. 26.1 Overview 26.2 Clock 26.3 Explanation of the Registers 26.4 Notes on Using Sub Clock Calibration Unit 733 CHAPTER 26 SUB CLOCK CALIBRATION UNIT 26.1 Overview The clock calibration module can calibrate a 32 kHz oscillation clock or 100 kHz CR oscillation clock using a 4 MHz oscillation clock. This chapter describes the overview and registers of the calibration unit, and notes on using the unit. This function is not installed on MB91461. ■ Description Using MB91467R, the time generated by a 32 kHz clock (or 100 kHz CR clock) can be measured with a 4 MHz clock. Using this hardware with software processing, the accuracy of a 32 kHz clock (or 100 kHz CR clock) can be brought close to the accuracy of a 4 MHz clock. The results of the clock calibration module measurement can be processed by software to obtain the settings required for the real time clock module. In this module, 2 types of timers are provided for operating with a 32 kHz clock (or a 100 kHz CR clock) and a 4 MHz clock. The 4 MHz timer is activated by the 32 kHz (100 kHz) timer and the result value of the 4 MHz timer is stored in the register. The value stored in the register is used in software processing that follows to calculate the necessary settings for the real time clock module. 734 CHAPTER 26 SUB CLOCK CALIBRATION UNIT ■ Block Diagram Figure 26.1-1 Block Diagram of Calibration Unit UC18CLK OSC4 CLK4G CLK4G = OSC4 | ~STRT | (READY & ~RUNS); Gate STRT READY RUNS OSC32 Gate STRT CLKPG CLKP Gate 32kHz Timer CLK32G RSLEEPB CLKPG2 CUTD Gate UC18TRD CUTR Counter (24 bits) sync STRTS RSLEEPB STRT 4MHz Timer RUN RUN async RST 32 RUNS CUTR (24 bits) 4 UC18TRR & CLKPG2 = CLKP | (~STRT & RSLEEPB); READY READY STRT sync CLKP 32 async RST STRT reset STRT STRT RB READY set/reset & INTEN RBB RB RUNSS1 RUNSS set/reset 4 sync CLKP RSLEEPB RSLEEP INT RMWB RMW set READYPULSE reset UC18BUS CUCR (3 bits) INT_I INT & INT_INT CUTR (24 bits) *_RDB *_RD *_WRB *_WR CUTD RSTB RST UC18IO CUTD (16 bits) UC18RBI FC18 735 CHAPTER 26 SUB CLOCK CALIBRATION UNIT ■ Timing Figure 26.1-2 Timing of Measurement Processing 32 kHz STRT (CLKP) STRTS (32 kHz) RUN (32 kHz) RUNS (4 MHz) 32kHz counter (16 bits) 4MHz counter (24 bits) Old CUTR READY (32 kHz) (16 bits) READYPULSE (CLKP) INT (CLKP) 736 CUTD-1 CUTD 0 2 1 0 CUTD New CUTR CHAPTER 26 SUB CLOCK CALIBRATION UNIT 26.2 Clock The modules operate with 3 types of clocks - 4 MHz clock OSC4, 32 kHz clock OSC32 (100 kHz clock OSC100), and peripheral clock CLKP. These are synchronized to operate for different domains. Clock frequency must meet the following requirements. ■ Clock Ratio TOSC32/OSC100 > 2 × TOSC4 + 3 × TCLKP TOSC4 < 1/2 × TOSC32/OSC100 - 3/2 × TCLKP TCLKP < 1/3 × TOSC32/OSC100 - 2/3 × TOSC4 ■ Input Frequency Input Frequency must not Exceed the Value Given in Table 26.4-1 . Table 26.2-1 Maximum Operating Frequency Maximum OSC32/OSC100 OSC4 CLKP 2MHz 10MHz 50MHz Table 26.2-2 Example of Valid Clock Ratio Meeting Requirements 1 and 2 OSC32 OSC100 OSC4 Maximum operating speed 2MHz 2MHz 10MHz Normal operation 32kHz 100kHz 4MHz 737 CHAPTER 26 SUB CLOCK CALIBRATION UNIT 26.3 Explanation of the Registers This section shows the calibration unit registers and describes the details of the functions of each register. ■ Calibration Unit Control Register (CUCR) bit Control register (lower bytes) Address: 0004BDH Read/Write → Initial value → 7 6 5 4 3 2 - - - STRT - - (R) (0) (R) (0) (R) (0) (R/W) (0) 1 0 INT INTEN CUCRL (R) (R/W) (R/W) (R/W) (0) (0) (0) (0) ■ 32 kHz/100 kHz Timer Data Register (CUTD) 32/100 kHz timer register (upper bytes) bit 15 14 13 12 11 10 9 8 TDD15TDD14 TDD13 TDD12 TDD11TDD10 TDD9 TDD8 Address: 0004B2H Read/Write→ Initial value → (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (1) (0) (0) (0) (0) (0) (0) (0) 6 5 4 3 2 1 0 32/100 kHz timer register (lower bytes) bit 7 Address: 0004B3H TDD7 TDD6 TDD5 TDD4 TDD3 TDD2 TDD1 TDD0 Read/Write → Initial value → 738 CUTDH (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (0) (0) (0) (0) (0) (0) (0) (0) CUTDL CHAPTER 26 SUB CLOCK CALIBRATION UNIT ■ 4MHz Timer Data Register (CUTR1/CUTR2) 4 MHz timer register 1 (upper bytes) bit 15 Address: 0004B4H Read/Write → Initial value → 14 13 12 11 10 9 8 - - - - - - - - (R) (0) (R) (0) (R) (0) (R) (0) (R) (0) (R) (0) (R) (0) (R) (0) 6 5 4 3 2 1 0 4 MHz timer register 1 (lower bytes) bit 7 Address: 0004B5H TDR23 TDR22 TDR21TDR20 TDR19 TDR18 TDR17 TDR16 Read/Write → Initial value → (R) (0) (R) (0) (R) (0) (R) (0) (R) (0) (R) (0) (R) (0) (R) (0) 4 MHz timer register 2 (upper bytes) bit 15 14 13 12 11 10 9 8 TDR15 TDR14 TDR13 TDR12 TDR11TDR10 TDR9 TDR8 Address: 0004B6H Read/Write → Initial value → 4 MHz timer register 2 (lower bytes) Address: 0004B7H Read/Write → Initial value → (R) (0) bit 7 (R) (0) (R) (0) (R) (0) (R) (0) (R) (0) (R) (0) (R) (0) 6 5 4 3 2 1 0 TDR7 TDR6 TDR5 TDR4 TDR3 TDR2 TDR1 TDR0 (R) (0) (R) (0) (R) (0) (R) (0) (R) (0) (R) (0) (R) (0) CUTR1H CUTR1L CUTR2H CUTR2L (R) (0) 739 CHAPTER 26 SUB CLOCK CALIBRATION UNIT 26.3.1 Calibration Unit Control Register (CUCR) The control register (CUCR) has the following functions. • Starting and stopping of calibration measurement • Enabling and disabling of interrupts • Displaying the end of calibration measurement bit Control register (lower bytes) Address: 0004B1H Read/Write → Initial value → 7 6 5 4 3 2 - - - STRT - - (R) (0) (R) (0) (R) (0) (R/W) (0) 1 0 INT INTEN CUCRL (R) (R/W) (R/W) (R/W) (0) (0) (0) (0) [bit4] STRT: Calibration start 0 Stop of calibration, switching to module off (Initial value) 1 Start of calibration When the START bit is set to "1" by software, a calibration starts. The 32 kHz/100 kHz timer starts a count down from the value stored in the 32 kHz/100 kHz timer data register and the 4 MHz timer starts a count up from zero. When the 32 kHz/100 kHz timer reaches to zero, the STRT bit is reset to "0" by hardware. If "0" is written to this bit by software during a calibration processing, the calibration stops immediately. If "0" is written by software and reset for the "0" is done by hardware simultaneously, the software operation has priority over the hardware operation. This means that the INT bit is set to "1" after a calibration ends normally. Writing "1" to this bit during a calibration has no effect. [bit1] INT: Interrupt 0 During calibration execution/module inactivate (Initial value) 1 Calibration completed This bit shows the end of a calibration. When the 32 kHz/100 kHz timer reaches to zero after a calibration start, the 4 MHz timer data register stores the last 4 MHz timer value and sets the INT bit to "1". A reading-modifying-writing operation for this bit reads "1" and the flag is cleared (INT=0) by writing "0" to this bit. Writing "1" to this bit does not affect the operation. The interrupt flag INT cannot be reset by hardware. Therefore, reset it by software before starting a new calibration. Without this reset, the end of a calibration processing can be converted to signals only by the STRT bit (the INT flag remains 1 during calibration). 740 CHAPTER 26 SUB CLOCK CALIBRATION UNIT [bit0] INTEN: Interrupt enable 0 Disables interrupts (Initial value) 1 Enables interrupts This bit is the interrupt enable bit corresponding to the INT bit. When this bit is set to 1 and the INIT bit is set by hardware, the calibration module sends the interrupt to CPU. Even if the interrupt is being disabled (INTEN=0), the INT bit itself is set by hardware without the effect from the INTEN bit. 741 CHAPTER 26 SUB CLOCK CALIBRATION UNIT 26.3.2 32 kHz/100 kHz Timer Data Register (16-bit) (CUTD) This section describes the 32 kHz/100 kHz timer data register. The 32 kHz/100 kHz timer data register (CUTD) retains the value (32 kHz/100 kHz reload value) that sets the time required for a calibration. Figure 26.3-1 32/100 kHz timer register (upper bytes) bit 15 14 13 12 11 10 9 8 TDD15TDD14 TDD13 TDD12 TDD11TDD10 TDD9 TDD8 Address: 0004B2H CUTDH Read/Write → (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (1) (0) (0) (0) (0) (0) (0) (0) Initial value → 32/100 kHz timer register (lower bytes) bit Address: 0004B3H Read/Write → Initial value → 7 6 5 4 3 2 1 0 TDD7 TDD6 TDD5 TDD4 TDD3 TDD2 TDD1 TDD0 CUTDL (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (0) (0) (0) (0) (0) (0) (0) (0) If a 32.768 kHz crystal is used, the default value corresponding to the measurement time for 1 second is 8000H. This register is written only if a calibration is inactive (STRT=0). The value specifying the time required for a calibration is stored in the 32 kHz/100 kHz timer register. When a calibration starts, this stored value is loaded into the 32 kHz/100 kHz timer and a count down is performed until the timer reaches to zero. Initializing CUTD by 0000 causes an underflow and the measurement becomes (FFFF hex + 1) × Tosc32 × Tosc100. The 32 kHz/100 kHz timer operates with a 32 kHz or 100 kHz oscillation clock. To obtain the measurement time for 1 second using a 32 kHz oscillator, the CUTD register must be loaded with 8000H = 32768 dec. This number is derived from a precise crystal oscillation frequency Fosc32768 Hz. Theoretical values for the measurement results (when 4.00 MHz crystal is used) are shown in the table below. To obtain the measurement time for 1 second using a 100 kHz oscillator, the CUTD register must be loaded with C350H = 50000 dec. This number is derived from a precise crystal oscillation frequency Fosc = 100000 Hz. Theoretical values for the measurement results (when 4.00 MHz crystal is used) are shown in the table below. 742 CHAPTER 26 SUB CLOCK CALIBRATION UNIT Table 26.3-1 32 kHz: Theoretical Value of Measurement Result for Each Measurement Time Time required for calibration CUTD value CUTR value 2s 0000H 7A1200H 1.75 s E000H 6ACFC0H 1.5 s C000H 5B8D80H 1.25 s A000H 4C4B40H 1s 8000H 3D0900H 0.75 s 6000H 2DC6C0H 0.5 s 4000H 1E8480H 0.25 s 2000H 0F4240H The time required for the overall processes from when "1" is written to the STRT bit and until when the STRT is reset by hardware takes longer than the actual calibration measurement time due to synchronizations between various clock domains. Processing time < (CUTD + 3) x Tosc32 Calibration measurement time is CUTD x Tosc32 Table 26.3-2 100 kHz: Theoretical Value of Measurement Result for Each Measurement Time Time required for calibration CUTD value CUTR value 0.5 s C350H 1E8480H 0.25 s 61A8H 0F4240H 0.125 s 30D4H 07A120H 0.1 s 2710H 061A80H The time required for the overall processes from when "1" is written to the STRT bit and until when the STRT is reset by hardware takes longer than the actual calibration measurement time due to synchronizations between various clock domains. Processing time < (CUTD + 3) x Tosc100 Calibration measurement time is CUTD x Tosc100 743 CHAPTER 26 SUB CLOCK CALIBRATION UNIT 26.3.3 4MHz Timer Data Register (24bit) (CUTR) The timer data register (CUTR) retains the value of a calibration result. (4 MHz counter). Note: The value read from this register is a random value during a calibration. The end of a calibration is shown by the INT bit and the STRT bit in the CUCR register. The CUTR value is enabled if INT is changed from "0" to "1" and STRT is changed from "1" to "0". Figure 26.3-2 4 MHz timer register 1 (upper bytes) bit 15 Address: 0004B4H Read/Write → Initial value → 14 13 12 11 10 9 8 - - - - - - - - (R) (0) (R) (0) (R) (0) (R) (0) (R) (0) (R) (0) (R) (0) (R) (0) 6 5 4 3 2 1 0 4 MHz timer register 1 (lower bytes) bit 7 Address: 0004B5H TDR23 TDR22 TDR21 TDR20 TDR19 TDR18 TDR17 TDR16 Read/Write → Initial value → (R) (0) (R) (0) (R) (0) (R) (0) (R) (0) (R) (0) (R) (0) (R) (0) 4 MHz timer register 2 (upper bytes) bit 15 14 13 12 11 10 9 8 Address: 0004B6H Read/Write → Initial value → TDR15 TDR14 TDR13 TDR12 TDR11 TDR10 TDR9 TDR8 (R) (0) (R) (0) (R) (0) (R) (0) (R) (0) (R) (0) (R) (0) (R) (0) (R) (0) (R) (0) (R) (0) (R) (0) (R) (0) (R) (0) CUTR1L CUTR2H (R) (0) 6 5 4 3 2 1 0 4 MHz timer register 2 (lower bytes) bit 7 Address: 0004B7H TDR7 TDR6 TDR5 TDR4 TDR3 TDR2 TDR1 TDR0 Read/Write → Initial value → CUTR1H CUTR2L (R) (0) The result of a calibration is stored in the 4 MHz timer data register. When a calibration starts, the 4 MHz timer starts a count up from zero. When the 32 kHz/100 kHz timer reaches to zero, the 4 MHz timer stops counting until the next calibration is started by software and the register retains the calibration result. The value read from this register is a random value during a calibration. The end of a calibration is shown by the INT bit and the START bit in the CUCR register. The CUTR value is enabled if these bits are changed from "0" to "1" and from "1" to "0" respectively. Writing to this register by software has no effect. The 4 MHz timer operates with a 4 MHz oscillation clock. 744 CHAPTER 26 SUB CLOCK CALIBRATION UNIT 26.4 Notes on Using Sub Clock Calibration Unit This section describes the cautions regarding the calibration accuracy, power loss, and measurement time. ■ 32 kHz The 32 kHz timer register setting can be calculated as follows. If the time required for a calibration is 1 second, the 32 kHz timer data register must be set to 8000H = 32768, indicating 32,768 pulses of a 32.768 kHz oscillation clock. This setting becomes the stored value of 3D0900H for the 4 MHz timer data register. This value indicates 4,000,000 pulses of a 4 MHz oscillator. ■ 100 kHz The 100 kHz timer register setting can be calculated as follows. If the time required for a calibration is 0.5 second, the 100 kHz timer data register must be set to C350H = 50000, indicating 50,000 pulses of a 100 kHz oscillation clock. This setting becomes the stored value of 1E8480H for the 4 MHz timer data register. This value indicates 2,000,000 pulses of a 4MHz oscillator. Table 26.4-1 Theoretical Measurement Results of 32.768 kHz and 4.0 MHz Oscillators (CUTR) Time required for calibration CUTD value CUTR value 2s 0000H 7A1200H 1.75 s E000H 6ACFC0H 1.5 s C000H 5B8D80H 1.25 s A000H 4C4B40H 1s 8000H 3D0900H 0.75 s 6000H 2DC6C0H 0.5 s 4000H 1E8480H 0.25 s 2000H 0F4240H The important factors for using the calibration module are power loss and calibration accuracy. 745 CHAPTER 26 SUB CLOCK CALIBRATION UNIT Table 26.4-2 Theoretical Measurement Results of 100 kHz and 4.0 MHz Oscillators (CUTR) Time required for calibration CUTD value CUTR value 0.5 s C350H 1E8480H 0.25 s 61A8H 0F4240H 0.125 s 30D4H 07A120H 0.1 s 2710H 061A80H The important factors for using the calibration module are power loss and calibration accuracy. ■ Accuracy: The accuracy of a calibration differs depending on the clock frequency used by the 4 MHz timer and the time required for the calibration. The maximum error of the 4 MHz timer is +/-1 digit. When the clock frequency is 4 MHz and the time required for a calibration is 1 second, the attained accuracy can be calculated as follows. 0.25 us (clock cycle time)/1 second (time require) = 0.25 ppm Normally, the calculation is performed as follows. Accuracy = (Clock cycle time of 4 MHz timer)/(Time required for calibration) ■ Power Loss: Assume that the dissipation IRUN in the execution mode at this moment is 20 times of the dissipation IRTC in the RTC mode (IRUN=20 × IRTC). If MCU is generated by software from the RTC mode to perform a calibration measurement per minute and the time required for a calibration is set to 1 second, the increase of the power loss is 20 × IRTC/60= 1/3 × IRTC. For this reason, it is necessary to prevent the effect of an increase of a power loss on the hardware limitation by the system requirement using software. For example, design the software to perform calibrations at the minimum occurrence frequency. Generally, it is recommended to keep a logical increase of a power loss below 5% in the RTC mode of MCU. ■ Measurement Limit: If the 32 kHz/100 kHz timer operates with a 32 kHz clock, the limitation of the time required for a calibration is about 2 seconds (or 0.5 seconds with a 100 kHz clock). Meanwhile, if the 4 MHz timer operates with a 4 MHz clock, it can measure for up to 4 seconds. 746 CHAPTER 27 FLASH MEMOEY This chapter describes the use of the built-in flash memory. 27.1 Overview 27.2 Access Modes 27.3 Auto Program Algorithm 27.4 Notes on Using Flash Memory 747 CHAPTER 27 FLASH MEMOEY 27.1 Overview This section describes the overview of the flash memory. The MB91F467R has built-in Flash memory with a capacity of 1024 Kbytes + 64 Kbytes, capability of batch-erasing all sectors or erasing on the sector level via single +3.3V power supply, and writing by the FR-CPU at the half-word (16-bit) and word (32-bit) level. ■ Features of Flash Memory • Capacity: 1024 Kbytes + 64 Kbytes • Power: 1.8V / +3.3 supply • Basic specification: Same as MBM29LV400TC (except size and part of sector configuration) • Additional specifications: Faster device operation by enabling commands/data reads at D-word (64-bit) level. • External writers: Interface for Parallel Flash Programmer available. • Operation modes: (1) 64-bit CPU mode: CPU reads and executes programs in word (32-bit) length units. Flash writing is not possible. Actual Flash Memory access is performed in d-word (64-bit) length units. (2) 32-bit CPU mode: CPU reads, writes and executes programs in word (32-bit) length units. Actual Flash Memory access is performed in word (32-bit) length units. (3) 16-bit CPU mode: CPU reads and writes in half-word (16-bit) length units. Program execution from the Flash is not possible. Actual Flash Memory access is performed in word (16-bit) length units. (4) Flash memory mode (external access to Flash memory enabled) • Features (Through combination of Flash memory macro and FR-CPU interface circuit): - Functions as CPU program/data storage memory. - Enables access to 32-bit bus width. - Enables read/write/erase by CPU (auto program algorithm*). - Functions equivalent to MBM29LV400TC stand-alone Flash-memory product. - Enables read/write/erase by parallel Flash programmer (auto program algorithm*). *: Auto program algorithm = Embedded AlgorithmTM 748 CHAPTER 27 FLASH MEMOEY ■ Configuration of Flash Memory Figure 27.1-1 Block Diagram CPU CPU core FLASH interface FLASH memory Control signal Control signal Control signal Address A0 to A20 A0 to A20 Data DQ0 to DQ63 DQ0 to DQ63 Control signal Address Data Interface with FLASH writer (when in FLASH mode) 749 CHAPTER 27 FLASH MEMOEY ■ Configuration in CPU Mode Table 27.1-1 Address Map (Sector Addresses, When Accessing from FR-CPU) Sector address Address range (in increments of 8) Corresponding bit position Sector capacity SA7 0014C004H to 0014FFFCH bit31 to bit0 8 Kbytes SA6 0014C000H to 0014FFF8H bit31 to bit0 8 Kbytes SA5 00148004H to 0014BFFCH bit31 to bit0 8 Kbytes SA4 00148000H to 0014BFF8H bit31 to bit0 8 Kbytes SA3 00144004H to 00147FFCH bit31 to bit0 8 Kbytes SA2 00144000H to 00147FF8H bit31 to bit0 8 Kbytes SA1 00140004H to 00143FFCH bit31 to bit0 8 Kbytes SA0 00140000H to 00143FF8H bit31 to bit0 8 Kbytes SA23 00120004H to 0013FFFCH bit31 to bit0 64 Kbytes SA22 00120000H to 0013FFF8H bit31 to bit0 64 Kbytes SA21 00100004H to 0011FFFCH bit31 to bit0 64 Kbytes SA20 00100000H to 0011FFF8H bit31 to bit0 64 Kbytes SA19 000E0004H to 000FFFFCH bit31 to bit0 64 Kbytes SA18 000E0000H to 000FFFF8H bit31 to bit0 64 Kbytes SA17 000C0004H to 000DFFFCH bit31 to bit0 64 Kbytes SA16 000C0000H to 000DFFF8H bit31 to bit0 64 Kbytes SA15 000A0004H to 000BFFFCH bit31 to bit0 64 Kbytes SA14 000A0000H to 000BFFF8H bit31 to bit0 64 Kbytes SA13 00080004H to 0009FFFCH bit31 to bit0 64 Kbytes SA12 00080000H to 0009FFF8H bit31 to bit0 64 Kbytes SA11 00060004H to 0007FFFCH bit31 to bit0 64 Kbytes SA10 00060000H to 0007FFF8H bit31 to bit0 64 Kbytes SA9 00040004H to 0005FFFCH bit31 to bit0 64 Kbytes SA8 00040000H to 0005FFF8H bit31 to bit0 64 Kbytes Flash memory's address mapping is different depending on whether it is being accessed from the FR-CPU or parallel Flash programmer. Refer to "■ Address Conversion from CPU Mode to Flash Programming Mode". 750 CHAPTER 27 FLASH MEMOEY Figure 27.1-2 Address Map (When Accessing from FR-CPU) CPU mode address 0014FFFFH 0014C000H 0014BFFFH 00148000H 00147FFFH 00144000H 00143FFFH 00140000H 0013FFFFH 00120000H 0011FFFFH 00100000H 000FFFFFH 000E0000H 000DFFFFH 000C0000H 000BFFFFH 000A0000H 0009FFFFH 00080000H 0007FFFFH 00060000H 0005FFFFH 00040000H addr+0 16-bit write mode 32-bit write mode SA6 (8 Kbytes) SA7 (8 Kbytes) SA4 (8 Kbytes) SA5 (8 Kbytes) SA2 (8 Kbytes) SA3 (8 Kbytes) SA0 (8 Kbytes) SA1 (8 Kbytes) SA22 (64 Kbytes) SA23 (64 Kbytes) SA20 (64 Kbytes) SA21 (64 Kbytes) SA18 (64 Kbytes) SA19 (64 Kbytes) SA16 (64 Kbytes) SA17 (64 Kbytes) SA14 (64 Kbytes) SA15 (64 Kbytes) SA12 (64 Kbytes) SA13 (64 Kbytes) SA10 (64 Kbytes) SA11 (64 Kbytes) SA8 (64 Kbytes) SA9 (64 Kbytes) addr+1 addr+2 dat[31:16] addr+3 dat[15:0] dat[31:0] addr+4 addr+5 addr+6 dat[31:16] addr+7 dat[15:0] dat[31:0] 751 CHAPTER 27 FLASH MEMOEY ■ Configuration in Flash Memory Mode Table 27.1-2 Sector Addresses (When Accessing from Parallel Flash Programmer) Sector address Address range FA[20:0] Corresponding bit position Sector capacity SA23 1F0000H to 1FFFFFH bit31 to bit0 64 Kbytes SA22 1E0000H to 1EFFFFH bit31 to bit0 64 Kbytes SA21 1D0000H to 1DFFFFH bit31 to bit0 64 Kbytes SA20 1C0000H to 1CFFFFH bit31 to bit0 64 Kbytes SA19 1B0000H to 1BFFFFH bit31 to bit0 64 Kbytes SA18 1A0000H to 1AFFFFH bit31 to bit0 64 Kbytes SA17 190000H to 19FFFFH bit31 to bit0 64 Kbytes SA16 180000H to 18FFFFH bit31 to bit0 64 Kbytes SA15 170000H to 17FFFFH bit31 to bit0 64 Kbytes SA14 160000H to 16FFFFH bit31 to bit0 64 Kbytes SA13 150000H to 15FFFFH bit31 to bit0 64 Kbytes SA12 140000H to 14FFFFH bit31 to bit0 64 Kbytes SA11 130000H to 13FFFFH bit31 to bit0 64 Kbytes SA10 120000H to 12FFFFH bit31 to bit0 64 Kbytes SA9 110000H to 11FFFFH bit31 to bit0 64 Kbytes SA8 100000H to 10FFFFH bit31 to bit0 64 Kbytes SA7 0FE000H to 0FFFFFH bit31 to bit0 8 Kbytes SA6 0FC000H to 0FDFFFH bit31 to bit0 8 Kbytes SA5 0FA000H to 0FBFFFH bit31 to bit0 8 Kbytes SA4 0F8000H to 0F9FFFH bit31 to bit0 8 Kbytes SA3 0F6000H to 0F7FFFH bit31 to bit0 8 Kbytes SA2 0F4000H to 0F5FFFH bit31 to bit0 8 Kbytes SA1 0F2000H to 0F3FFFH bit31 to bit0 8 Kbytes SA0 0F0000H to 0F1FFFH bit31 to bit0 8 Kbytes Flash memory's address mapping is different depending on whether it is being accessed from the FR-CPU or parallel Flash programmer. Refer to "■ Address Conversion from CPU Mode to Flash Programming Mode". 752 CHAPTER 27 FLASH MEMOEY Figure 27.1-3 Address Map (When Accessing from Parallel Flash Programmer) Flash program mode Address (FA)[20:0] 1FFFFFH SA23 (64 Kbytes) 1FC000H 1EBFFFH SA22 (64 Kbytes) 1E8000H 1D7FFFH SA21 (64 Kbytes) 1D4000H 1C3FFFH SA20 (64 Kbytes) 1C0000H 1BFFFFH SA19 (64 Kbytes) 1B0000H 1AFFFFH SA18 (64 Kbytes) 1A0000H 19FFFFH SA17 (64 Kbytes) 190000H 18FFFFH SA16 (64 Kbytes) 180000H 17FFFFH SA15 (64 Kbytes) 170000H 16FFFFH SA14 (64 Kbytes) 160000H 15FFFFH SA13 (64 Kbytes) 150000H 14FFFFH SA12 (64 Kbytes) 140000H 13FFFFH SA11 (64 Kbytes) 13C000H 12FFFFH SA10 (64 Kbytes) 128000H 11FFFFH SA9 (64 Kbytes) 114000H 10FFFFH SA8 (64 Kbytes) 100000H 0FFFFFH SA7 (64 Kbytes) 0FE000H 0FDFFFH SA6 (64 Kbytes) 0FC000H 0FBFFFH SA5 (64 Kbytes) 0FA000H 0F9FFFH SA4 (64 Kbytes) 0F8000H 0F7FFFH SA3 (64 Kbytes) 0F6000H 0F5FFFH SA2 (64 Kbytes) 0F4000H 0F3FFFH SA1 (64 Kbytes) 0F2000H 0F1FFFH SA0 (64 Kbytes) 0F0000H 16-bit write mode 8-bit write mode FA[1:0]=0x FA[1:0]=1x DQ[15:0] DQ[15:0] FA[1:0]=00 FA[1:0]=01 FA[1:0]=10 FA[1:0]=11 DQ[7:0] DQ[7:0] DQ[7:0] DQ[7:0] 753 CHAPTER 27 FLASH MEMOEY ■ Address Conversion from CPU Mode to Flash Programming Mode Use the following equations to calculate a Flash programming mode address (FA) from a CPU mode address (addr). SA0, SA2, SA4, SA6 (140000H ≤ addr ≤ 14FFFFH; addr[2]=0): FA = addr - addr%004000H + (addr%004000H)/2 - (addr/2)%4 + addr%4 - 050000H SA1, SA3, SA5, SA7 (140000H ≤ addr ≤ 14FFFFH; addr[2]=1): FA = addr - addr%004000H + (addr%004000H)/2 - (addr/2)%4 + addr%4 - 04E000H SA8, SA10, SA12, SA14, SA16, SA18, SA20, SA22 (040000H ≤ addr ≤ 13FFFFH; addr[2]=0): FA = addr - addr%020000H + (addr%020000H)/2 - (addr/2)%4 + addr%4 + 0C0000H SA9, SA11, SA13, SA15, SA17, SA19, SA21, SA23 (040000H ≤ addr ≤ 13FFFFH; addr[2]=1): FA = addr - addr%020000H + (addr%020000H)/2 - (addr/2)%4 + addr%4 + 0D0000H 754 CHAPTER 27 FLASH MEMOEY 27.2 Access Modes This section describes the Flash memory access modes. 755 CHAPTER 27 FLASH MEMOEY 27.2.1 Access from the FR-CPU This section describes three types of access mode from FR-CPU. The following three types of access mode are available: ■ 64-bit CPU Mode (Read/Execute) This mode does not allow data erase/write. Data can only be accessed by the CPU in lengths of words (32 bits) but is actually read from the Flash Memory in lengths of d-words (64 bits). Programs can be executed in Flash memory while this mode is enabled. • Specification of mode Do not set this mode from a program on the FLASH. Set this mode from a program placed on the RAM. • Description of operation When reading or executing code from the Flash memory area, data is read by the CPU in word (32-bit) length units but is actually read from memory in D-word (64-bit) length units. Running Auto Algorithms is not possible. ■ 32-bit CPU Mode (Read/Write/Execute) This mode allows data erase/write. Data can only be accessed in lengths of words (32 bits). Programs cannot be executed in Flash memory while the Flash is being written/erased. • Specification of mode Use a program on the RAM to switch to this mode. (The mode is set to this mode after reset.) • Description of operation When reading or executing code from the Flash memory area, data is read from memory in word (32bit) length units. Auto Algorithms can be run by writing commands to Flash memory. It is possible to erase/write to Flash memory by running an Auto Algorithm. See "27.3 Auto Program Algorithm" for details about Auto Algorithms. 756 CHAPTER 27 FLASH MEMOEY ■ 16-bit CPU Mode (Read/Write) This mode allows data erase/write. Data can only be accessed in lengths of half-words (16 bits). Programs cannot be executed in Flash memory while this mode is enabled. • Specification of mode Use a program on the RAM to switch to this mode. • Description of operation When reading from the Flash memory area, data is read from memory in half-word (16-bit) length units. Auto Algorithms can be run by writing commands to Flash memory. It is possible to erase/write the Flash memory by running an Auto Algorithm. See "27.3 Auto Program Algorithm" for details about Auto Algorithms. 757 CHAPTER 27 FLASH MEMOEY 27.2.2 Flash Memory Mode This section describes the use of the flash memory mode. Resetting after setting the MD3, MD2, MD1, and MD0 pins to "0", "1", "1", and "1" will halt CPU functioning. At this time, the Flash memory's interface circuit functions to enable direct control of the Flash memory unit from external pins, by directly linking some of the signals of ports 2 through 27 to the Flash memory unit's control signal. In this mode, the Flash memory appears to the external pins as a stand-alone unit. This mode is generally set when writing/erasing using the parallel Flash programmer. In this mode, all operations of the Flash memory's Auto Algorithms are available. Table 27.2-1 Correspondence between MBM29LV400TC and Flash Memory Control Signal MB91F467R external pins MBM29LV400TC External pins FR-CPU mode - Flash memory mode Normal function Pin number INIT - INITX 131 RESET - FRSTX P13_2 10 - - MD3 MD3 127 - - MD2 MD2 128 - - MD1 MD1 129 - - MD0 MD0 130 RY/BY FMCS:RDY bit RY/BY P09_4 15 BYTE Internally fixed to "H" BYTEX P13_1 9 WEX P09_3 16 OEX P09_2 17 CEX P09_1 18 A-1, A0 to A2 FA0 to FA3 P17_4 to P17_7 93 to 96 A3 to A13 FA4 to FA14 P29_0 to P29_7 P28_0 to P28_2 98 to 108 A14 to A18 FA15 to FA19 P28_3 to P28_7 109 to 113 A19, A20 FA20, FA21 P22_4, P22_5 117, 118 D0 to D15 P10_0 to P10_6 P08_0 to P08_1 P08_4 to P08_7 P11_1 to P11_0 P09_0 35 to 29 27 to 19 WE OE CE DQ0 to DQ15 758 Internal control signal + control via interface circuit Internal address bus Internal data bus CHAPTER 27 FLASH MEMOEY 27.3 Auto Program Algorithm Writing into and erasing from the flash memory are performed by activating auto algorithms of the flash memory itself. ■ Command Operation To activate auto algorithms, write a half-word (16 bits) of 1 to 6 into the flash memory consecutively. This is called a "command". If an improper address and the data are written, or if an address and the data are written in the wrong order, the flash memory will be reset to the read mode. Table 27.3-1 Command List of CPU Mode Command sequence Bus write cycle 1st bus write cycle 2nd bus write cycle 3rd bus write cycle 4th read/write cycle 5th bus write cycle 6th bus write cycle Address Data Address Data Address Data Address Data Address Data Address Data Read/Reset 1 *XXXXH F0H --- --- --- --- --- --- --- --- --- --- Read/Reset 4 *x557H AAH *yAAFH 55H *x557H F0H RA RD --- --- --- --- Write 4 *x557H AAH *yAAFH 55H *x557H A0H PA PD --- --- --- --- Chip erase 6 *x557H AAH *yAAFH 55H *x557H 80H *x557H AAH *yAAFH 55H *x557H 10H Sector erase 6 *x557H AAH *yAAFH 55H *x557H 80H *x557H AAH *yAAFH 55H SA 30H Enter address = "*XXXXH" and data = "B0H" to stop the erase temporarily in a sector erase operation. Sector temporary stop Enter address = "*XXXXH" and data = "30H" to restart the erase after sector erase temporary stop. Sector erase restart Continuous mode 3 *x557H AAH *yAAFH 55H *x557H 20H --- --- --- --- --- --- Continuous write 2 *XXXXH A0H PA PD --- --- --- --- --- --- --- --- Continuous mode reset 2 *XXXXH 90H *XXXXH F0H or 00H --- --- --- --- --- --- --- --- The commands for the word mode and the half-word mode are the same. Data can be set using bits except specified bits. RA: Read address PA: Write address SA: Sector address (specifying an address in a sector) RD: Read data PD: Write data *: "0004H", "0005H", "0006H", "0007H", "0008H", "0009H", "000AH", "000BH", "000CH", "000DH", "000EH", "000FH", "0010H", "0011H", "0012H", "0013H", or "0014H" x: hexadecimal odd digit: "1H", "3H", "5H", "7H", "9H", "BH", "DH", or "FH" y: hexadecimal even digit: "0H", "2H", "4H", "6H", "8H", "AH", "CH", or "EH" • Auto algorithm execution state If an auto algorithm starts in the CPU mode, the operation state of the auto algorithm can be checked using the internal ready signal (RDY). The level of this ready signal can be read from the "RDY" bit in the flash memory control status register. If the "RDY" bit is "0", the read data becomes a hardware sequence flag indicating the flash memory status (see Hardware sequence (3) and (4)). 759 CHAPTER 27 FLASH MEMOEY 27.3.1 Commands of Auto Program Algorithm This section describes the commands of auto program algorithm. ■ Read/Reset Command When a read/reset command sequence is issued, the mode can be returned to the read mode after exceeding the timing limit. Data is read from the flash memory at read cycle. The flash memory remains in reading status until another command is entered. When the power is turned on, the flash memory is automatically set to the read/reset mode. In this case, a command for reading data is not needed. ■ Program (Write) In CPU programming mode, data is basically written in half-word units. The write operation is performed in four cycles of bus operation. The command sequence has two unlock cycles, which are followed by a write setup command and a write data cycle. And the last write cycle starts the writing to the memory. Once an automatic write algorithm command sequence was executed, the flash memory needs no more external controls. The flash memory internally generates appropriate write pulses to check the margin of the cells to which data is written. The data polling function compares the data of bit7 with the written data for this bit, and if these data are the same, the automatic write operation ends (see "(3) Hardware sequence flags"). The automatic write operation then returns to the read mode and accepts no more write addresses. Consequently, the flash memory requests the next valid address at this moment. In this manner, the data polling function indicates that the memory is being in a write operation. During a write operation, all commands written to the flash memory are ignored. If a hardware reset is activated during a write operation, the data at the writing address may become invalid. Writing into data addresses can be performed in any order and even in the outside of sector boundaries. Writing cannot return data "0" back to data "1". If data "0" is overwritten with data "1", the data polling algorithm determines either that the device is defective, or that data "1" has been written in the reset/read mode, resulting that the data is read as "0" when reading. Only an erase operation can change data "0" to data "1". 760 CHAPTER 27 FLASH MEMOEY Figure 27.3-1 Write Sequence Using Write Command Starts writing Command sequence writing Devise data polling Next address NO Last address? YES Ends writing ■ Chip Erase A chip erase command sequence ("erase all sectors simultaneously") is executed in six accesses. After two unlock cycles, a setup command is written. Then after two more unlock cycles, the chip erase command is entered. Writing to the flash memory before erasing chip is not needed. When the automatic erase algorithm is executed, the flash memory checks each cell by writing 0 to cells before automatically erasing the contents of the cells. In this operation, the flash memory does not need to be controlled externally. The automatic erase operation starts with the write operation of the command sequence and ends when bit7 is set to "1", and at this time, the flash memory returns to the read mode. The chip erase time can be expressed as "time for sector erase × number of sectors + time for chip writing (preprogram) ". The figure below shows the chip erase sequence using the chip erase command. ■ Sector Erase A sector erase command sequence is executed in six accesses. After two unlock cycles, a setup command is written, and then two more unlock cycles follow. The sector erase command is entered in the sixth cycle for starting the sector erase operation. The next sector erase command can be accepted within a time-out period of 50 s after the last sector erase command is written. To execute multiple sector erases simultaneously, write the above-mentioned six bus cycles. This sequence is executed by writing the addresses of the sectors to be erased consecutively after the sector erase command (30H). The sector erase operation starts after the end of the time-out period of 50 µs after the last sector erase command is written. Therefore, to erase multiple sectors simultaneously, each sector must be entered within the 50 µs time-out period, otherwise it may not be accepted. Bit3 can be used to monitor whether each sector erase command is valid or not. (See "(3) Hardware sequence flag"). The flash memory returns to the read mode when the erase ends. Other commands are ignored. Data polling can operate on any addresses in the erased sector. The erase time for multiple sectors can be expressed as "(time for sector erase + time for chip writing (preprogram)) × number of erased sectors)". 761 CHAPTER 27 FLASH MEMOEY Figure 27.3-2 Chip Erase Sequence Using Chip Erase Command Starts erase / erase Chip/Sector command sequence End of device data polling or toggle bit Ends writing ■ Erase Temporary Stop The erase temporary stop command temporarily stops the automatic algorithm in flash memory during a sector erase operation, thereby making it possible to write data to and read data from the other sectors that is not subject to the erase operation. This command is valid only during a sector erase operation and ignored during a chip erase operation and a write operation. The erase temporary stop command (B0H) is valid only during a sector erase operation that includes the time-out period after a sector erase command (30H) is issued. When this command is entered within the time-out period, the time-out is ended immediately and the erase operation is suspended. The erase operation is restarted when an erase restart command is entered. Any addresses can be used for the entry of erase temporary stop and erase restart commands. When an erase temporary stop command is entered during a sector erase operation, the flash memory needs a maximum of 20 µs to stop the erase operation. When the flash memory enters the erase temporary stop mode, it outputs a ready/busy signal, bit7 outputs "1" and bit6 stops a toggle action. For checking whether the erase operation has stopped, enter the address of the sector being erased and monitor the read values of bit6 and bit7. In this period, another erase temporary stop command entry will be ignored. When the erase operation stops, the flash memory enters the erase temporary stop read mode. Data reading is enabled in this mode for sectors that are not subject to the erase temporary stop, and other than that, there is no difference from the standard read operation. In the erase temporary stop read mode, bit2 is toggled when the data is read sequentially from the sectors that are in the erase temporary stop (for details, see "(3) Hardware sequence flag"). After the erase temporary stop read mode is entered, the user can write to the flash memory by writing a write command sequence. This mode is called the "erase temporary stop write mode". In this mode, data writing is enabled for sectors that are not subject to the erase temporary stop, and other than that, there is no difference from the standard byte writing operation. In the erase temporary stop write mode, bit2 is toggled when the data is read sequentially from the sectors that are in the erase temporary stop. This mode is detected by the erase temporary stop bit (bit6). Notes on using this mode: Bit6 can be read from any addresses, but bit7 must be read from write addresses. To restart the sector erase operation, a restart command (30H) must be entered. Another restart command entry is ignored in this point. On the other hand, an erase temporary stop command can be entered after the flash memory restarts the erase operation. 762 CHAPTER 27 FLASH MEMOEY 27.3.2 Hardware Sequence Flag This section describes the hardware sequence flag. In this flash memory, write/erase sequences are executed by automatic algorithms. For this reason, this flash memory has hardware that notifies the end of internal operations to externals. ● Hardware sequence flag A hardware sequence flag is obtained as data by reading an arbitrary address (odd address if byte access) from the flash memory while the automatic algorithm is being executed. The data contains five valid bits, and each of them indicates the status of the automatic algorithm. Figure 27.3-3 Hardware Sequence Flag Format bit When reading from hardware 15 8 7 bit 7 6 5 DPOLL TOGGLE TLOVER 7 0 Hardware sequence flag When reading from byte (odd address only) bit When accessing with half-word and byte 0 Hardware sequence flag (Indeterminate) 4 (Indeterminate) 3 2 SETIMR TOGGL2 1 0 (Indeterminate) (Indeterminate) These flags have no meaning in the FR-CPU ROM mode. Read this data only in the FR-CPU programming mode using half-word or byte. 763 CHAPTER 27 FLASH MEMOEY Table 27.3-2 List of Hardware Sequence Flag Status Status DPOLL (bit7) TOGGLE (bit6) TLOVER (bit5) SETIMR (bit3) TOGGL2 (bit2) Automatic write Inverted data Toggle 0 0 1 0 Toggle 0 1 Toggle 1 1 0 0 Toggle Data Data Data Data Toggle 0 0 1 *1 Inverted data Toggle 1 0 1 0 Toggle 1 1 *2 Write/Erase in automatic write Executing Timing limit exceeded Read (from sectors to be erased) Erase Read (from sectors temporary Data not to be erased) stop Write (to sectors not Inverted data to be erased) Automatic write Write/Erase in automatic write *1: Bit2 outputs "1" when the written address is read in the erase temporary stop write mode. However, bit2 is toggled when the data is read sequentially from the sectors where erasing is temporarily stopped. *2: When bit5 is set to "1" (time limit exceeded), bit2 is toggled when the data is read sequentially to the sectors in a writing/ erasing operation, but it is not toggled when the data is read to other sectors. • Ready/Busy signal (RDY/BUSYX) The flash memory uses the ready/busy signal in addition to the hardware sequence flags to indicate whether an internal automatic algorithm is running or not. This ready/busy signal is connected to the flash memory interface circuit, and it can be read as the "RDY" bit of the flash memory control status register. When the ready/busy signal is activated, an interrupt request can be issued to CPU. When the read value of the "RDY" bit is "0": The flash memory is executing a write operation or an erase operation. At this moment, no new write or erase commands are accepted. When the read value of the "RDY" bit is "1": The flash memory is in a read/write or erase standby state. 764 CHAPTER 27 FLASH MEMOEY 27.3.3 Flash Control Register (FLCR) This section describes the bit configuration and functions of flash control register (FLCR). Figure 27.3-4 FLCR: Address is Any Address in Flash Memory (Access: Byte or Half-word) FLCR Address: bit7 DPOLL R R - bit6 bit5 TOGGLE TLOVER R R bit4 R bit3 bit2 SETIMR TOGGL2 R R bit1 bit0 Initial value - - --------B R R : Read only : Undefined [bit7] Data polling (DPOLL) • In automatic write operation When a read access is performed while the automatic write algorithm is being executed, the flash memory outputs the inverted data of the last written value in bit7. When a read access is performed at the end of the automatic write algorithm, the flash memory outputs bit7 of the read data of the address indicated by the address signal. • In automatic erase operation When a read access is performed while the automatic erase algorithm is being executed, the flash memory outputs "0" regardless of the address indicated by the address signal. Similarly, the flash memory outputs "1" at the end of the algorithm. • In sector erase temporary stop mode When a read access is performed in sector erase temporary stop mode, the flash memory outputs "1" when the address indicated by the address signal belongs to the sector being in erase status. If the address does not belong to the sector being in erase status, the flash memory outputs bit7 of the read value for the address. By referring to this bit while bit6 is toggling, it allows to determine whether the current sector is in the sector erase temporary stop status or not, and which sector is to be erased. • As an automatic algorithm operation comes near to the end, the value of bit7 (data polling) is changed to asynchronous. This means that the flash memory will send this data after it sends the operation status to bit7. When the flash memory ends the automatic algorithm and outputs data set in bit7, other bits remain undefined. • The defined data of other bits is read by executing a normal read. [bit6] Toggle bit (TOGGLE) • In automatic write/erase operation When continuous read accesses are performed while the automatic write algorithm or erase algorithm is being executed, the flash memory outputs a toggle result "1" or "0" to bit6. When the automatic write or erase algorithm ends, the toggling of bit6 for the continuous read accesses is stopped and valid data is output. The toggle bit becomes valid after the last write cycle of the corresponding command. If a writing processing the data to the sector protected from being written to during a writing operation is made, a toggling for approximately 2 ms will be performed and no data is rewritten. While erasing, if all the selected sectors are protected from being written to, the toggle bit will perform a toggling 765 CHAPTER 27 FLASH MEMOEY operation for approximately 100 µs and then the mode will return to the read mode without rewriting data. • Sector erase temporary stop mode When a read access is performed in the sector erase temporary stop mode, the flash memory outputs "1" if the address indicated by the address signal belongs to the sector being erased. If the address does not belong to the sector being erased, the flash memory outputs bit6 of the read value of the address indicated by the address signal. [bit5] Timing limit over (TLOVER) • In automatic write/erase operation Bit5 indicates that an automatic algorithm execution exceeds the time (number of internal pulses) specified in the flash memory. In this state, bit5 outputs "1". That is, if this flag outputs "1" during an automatic algorithm operation, the writing or erasing is failed. If an attempt to write to bit5 or a non-blank portion that is not being erased is made, the attempt will fail. In this case, the set data cannot be read from bit7 (data polling), keeping bit6 (toggle bit) toggling. If timing limit over occurs in this state, bit5 will output "1". This status indicates that flash memory was not used correctly, not that it was defective. If this status occurs in the flash memory, execute a reset command. [bit4] Undefined The read value is indeterminate. [bit3] Sector erase timer (SETIMR) • In sector erase operation The flash memory becomes the standby state for sector erase after the first sector erase command sequence is executed. At this time, bit3 becomes "0". It outputs "0" when a sector erase wait period ends. Data polling and toggle bit will be enabled after the first sector erase command sequence is executed. When this flag is set to "1" by the data polling or toggle bit function while the erase algorithm is being executed, an internally controlled erase operation has been started. Subsequent writing of commands is ignored until the termination of the erase operation is shown by the data polling or toggle bit function (only erase temporary stop commands are accepted). When this flag is "0", the flash memory accepts additional sector erase commands. To confirm this, it is recommended to check the status of this flag before writing the succeeding sector erase commands. If this flag is "1" at the second time of status check, it means that the additional sector erase command may have not been accepted. When a read access is performed in the sector erase temporary stop mode, the flash memory outputs 1 if the address indicated by the address signal belongs to the sector to be erased. If the address does not belong to that sector, the flash memory outputs bit3 of the read value of the address indicated by the address signal. [bit2] Toggle bit2 (TOGGLE2) • In sector erase operation Together with toggle bit of bit6, this toggle bit is used to detect whether the flash memory is under automatic erase operation or in the erase temporary stop status. If data is read repeatedly from the data to be erased in an automatic erase operation, bit2 toggles. If the flash memory is in the erase temporary stop mode, bit2 toggles when data is read repeatedly from the sector where the erase is temporarily stopped. If the flash memory is in the erase temporary stop write mode, "1" is read from bit2 when address is read repeatedly from the sector where the erase is not temporarily stopped. Unlike bit2, bit6 only toggles in a normal write, erase, or erase temporary stop write operation. For example, bit2 and bit6 are used together to detect the erase temporary stop read mode (bit2 toggles but bit6 does not toggle). In addition, bit2 is used to detect sectors to be erased. If data is read from the 766 CHAPTER 27 FLASH MEMOEY sector to be erased when the flash memory is executing an erase operation, this bit will perform toggling operation. [bit1, bit0] Undefined The read value is indeterminate. 767 CHAPTER 27 FLASH MEMOEY 27.3.4 Examples of Using Hardware Sequence Flag This section describes the examples of using hardware sequence flag. By using hardware sequence flags mentioned above, the status of the internal automatic algorithms in the flash memory can be determined. As the examples, write/erase determination sequences, one each for when data polling function is used and for when toggle bit function is used are shown. Figure 27.3-5 Write/Erase Determination Sequence Using Data Polling Function Starts write/erase Read (D0 to D7) address = VA D7 = Data? YES VA = Write address = Erased sector address under sector erase operation = Non-protected sector address under chip erase operation *: Because D7 is changed at the same time as D5, D7 must be rechecked even if D5 = 1. NO NO D5 = 1? YES Read (D0 to D7) address = VA D7 = Data? * YES NO Write/Erase failed 768 Write/Erase succeeded CHAPTER 27 FLASH MEMOEY Figure 27.3-6 Write/Erase Determination Sequence Using Toggle Bit Function Starts write/erase Read (D0 to D7) address = "H" to "L" D6 = Toggle? NO YES NO D5=1? YES Read (D0 to D7) address = "H" to "L" D6 = Toggle? * NO YES Write/erase failed Write/erase succeeded * Because D6 stops toggling when D5 is changed to "1", D6 must be rechecked even if D5 = 1. 769 CHAPTER 27 FLASH MEMOEY 27.4 Notes on Using Flash Memory This section describes notes on using flash memory and the serial programming. • Refer to MBM29LV400TC datasheet together with this document. • CPU mode In CPU mode, how to assign addresses differs from the one using parallel flash programmer in a write operation. See "■ Address Conversion from CPU Mode to Flash Programming Mode". • Flash memory card (writing by parallel flash programmer) By using this flash memory, the data can be written from external devices using parallel flash programmer. In this state, the pin functions equivalent to the ones in the stand-alone product MBM29LV400TC are assigned to external pins of the devices and CPU operation stops. In the flash memory card, the address line connection to mapping in the memory area is changed from the CPU mode. ■ FLASH Serial Programming MB91F467R has a support function for on-board FLASH serial programming. This is called serial download function. With this function, data can be