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FUJITSU SEMICONDUCTOR
CONTROLLER MANUAL
CM71-10107-2E
FR30
32-BIT MICROCONTROLLER
MB91121 Series
HARDWARE MANUAL
FR30
32-BIT MICROCONTROLLER
MB91121 Series
HARDWARE MANUAL
Be sure to refer to the “Check Sheet” for the latest cautions on development.
“Check Sheet” is seen at the following support page
URL : http://www.fujitsu.com/global/services/microelectronics/product/micom/support/index.html
“Check Sheet” lists the minimal requirement items to be checked to prevent problems beforehand in system development.
FUJITSU LIMITED
PREFACE
■ Objectives and Intended Reader
The MB91121 was developed as a product belonging to the FR30 that offers 32-bit single-chip
microcontrollers with CPUs of a new RISC architecture. MB91121 is based on optimum specifications for
internal uses requiring high CPU processing power.
This manual describes the functions and operations of MB91121 for engineers who design products using
the microcontrollers of the series. Read through this manual before use. For details on the software
instructions, refer to "Software Instruction Manual".
■ Trademark
FR representing FUJITSU RISC Controller is a trademark of Fujitsu Limited.
i
■ Structure of This Manual
This manual consists of 16 chapters and appendixes:
CHAPTER 1 OUTLINE OF MB91121
This chapter explains the features and functions of MB91121 with a block diagram and other figures,
including an outline of the pin function.
CHAPTER 2 DEVICE HANDLING NOTES
This chapter gives MB91121 handling notes.
CHAPTER 3 CPU
This chapter gives basic information on the architecture, specifications, and instructions to assist in
obtaining an understanding of the functions of the FR family CPU core.
CHAPTER 4 BUS INTERFACE
This chapter provides a sample program for bus operations and an outline of the bus interface
explaining the register configuration and functions, bus operations, and bus timings.
CHAPTER 5 I/O PORT
This chapter explains an outline of an I/O port, the register configuration and its functions, and the
relationship between the external pins and the switching registers.
CHAPTER 6 16-BIT RELOAD TIMER
This chapter gives an outline of the 16-bit reload timer and explains the register configuration and
functions and the timer operations.
CHAPTER 7 PWM TIMER
This chapter gives an outline of the PWM timer and explains the register configuration and functions
and the timer operations.
CHAPTER 8 U-TIMER
This chapter explains an outline of the U-TIMER, the register configuration and its functions, and UTIMER operations.
CHAPTER 9 EXTERNAL INTERRUPT/NMI CONTROL SECTION
This chapter gives an outline of the external interrupt/NMI control section and explains the register
configuration and functions and the section operations.
CHAPTER 10 DELAYED INTERRUPT MODULE
This chapter gives an outline of the delayed interrupt module and explains the register configuration and
functions and the module operations.
CHAPTER 11 INTERRUPT CONTROLLER
This chapter provides an outline of the interrupt controller and explains the register configuration and
functions and provides an example of using the hold request cancel function.
CHAPTER 12 A/D CONVERTER
This chapter gives an outline of the A/D converter and explains the register configuration and functions
and the converter operations.
CHAPTER 13 UART
This chapter gives an outline of the UART and explains the register configuration and functions and the
UART operations.
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CHAPTER 14 DMA CONTROLLER (DMAC)
This chapter gives an outline of the DMA controller (DMAC) and explains the register configuration
and functions and the controller operations.
CHAPTER 15 BIT SEARCH MODULE
This chapter gives an outline of the bit search module and explains the register configuration and
functions, the module operations, and the save/return processing.
CHAPTER 16 SUM-OF-PRODUCTS MACRO (SIMPLE DSP)
This chapter outlines the sum-of-products macro (DSP hereafter) and explains the register configuration
and functions and DSP operations.
APPENDIX
These appendixes describe the I/O mapping, the interrupt vectors, the pin status in the CPU state, the
notes on using little endian areas, and the instruction list.
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The contents of this document are subject to change without notice.
Customers are advised to consult with FUJITSU sales representatives before ordering.
The information, such as descriptions of function and application circuit examples, in this document are presented solely for the
purpose of reference to show examples of operations and uses of FUJITSU semiconductor device; FUJITSU does not warrant
proper operation of the device with respect to use based on such information. When you develop equipment incorporating the
device based on such information, you must assume any responsibility arising out of such use of the information. FUJITSU
assumes no liability for any damages whatsoever arising out of the use of the information.
Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of
the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of FUJITSU or any third
party or does FUJITSU warrant non-infringement of any third-party's intellectual property right or other right by using such
information. FUJITSU assumes no liability for any infringement of the intellectual property rights or other rights of third parties
which would result from the use of information contained herein.
The products described in this document are designed, developed and manufactured as contemplated for general use, including
without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed
and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured,
could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss
(i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life
support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible
repeater and artificial satellite).
Please note that FUJITSU will not be liable against you and/or any third party for any claims or damages arising in connection
with above-mentioned uses of the products.
Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such
failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and
prevention of over-current levels and other abnormal operating conditions.
If any products described in this document represent goods or technologies subject to certain restrictions on export under the
Foreign Exchange and Foreign Trade Law of Japan, the prior authorization by Japanese government will be required for export of
those products from Japan.
Copyright ©2000-2006 FUJITSU LIMITED All right reserved
iii
READING THIS MANUAL
■ Terms
The following terms are used in this manual:
Term
Explanation
I-bus
16-bit internal instruction bus: The instruction bus is independent of the data bus in the
FR family because the internal Harvard architecture is adopted. An instruction cache and
a bus converter are connected to I-bus.
D-bus
32-bit internal data bus: Internal resources are connected to D-bus.
C-bus
Internal multiplexer bus: This bus is connected to I-bus and D-bus through a switch. An
external interface module is connected to this bus. Data and instructions are multiplexed
on the external data bus.
R-bus
16-bit internal data bus: This bus is connected to D-bus through an adapter. An I/O
resource, clock generator, or interrupt controller is connected to this bus. Since R-bus is
16 bits wide and data and addresses are multiplexed, it takes several cycles for the CPU
to access the resources.
E-unit
Arithmetic operation unit.
φ
System clock signal output from the clock generator to an internal resource connected to
the R-bus. The fastest cycle of this signal is equal to the oscillation cycle. However, the
cycle is divided as 1/1, 1/2, 1/4, and 1/8 (or 1/2, 1/4, 1/8, and 1/16) depending on the
setting of the PCK1 and PCK0 bits in the GCR register of the clock generator.
θ
System clock signal serving as an operation clock for a resource connected to a bus other
than R-bus and also for the CPU. The fastest cycle of this signal is equal to the
oscillation cycle. However the cycle is divided as 1/1, 1/2, 1/4, and 1/8 (or 1/2, 1/4, 1/8,
and 1/16) depending on the setting of the CCK1 and CCK0 bits in the GCR register of
the clock generator.
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CONTENTS
CHAPTER 1
1.1
1.2
1.3
1.4
1.5
1.6
CHAPTER 2
2.1
2.2
2.3
OUTLINE OF MB91121 ................................................................................ 1
Features of MB91121 ......................................................................................................................... 2
Block Diagram of MB91121 ................................................................................................................ 6
Outside Dimension Drawing ............................................................................................................... 7
Pin Arrangement Diagram .................................................................................................................. 8
Explanations of the Pin Functions ...................................................................................................... 9
I/O Circuit Types ............................................................................................................................... 15
DEVICE HANDLING NOTES ..................................................................... 17
Notes on Handling Pins and Circuits ................................................................................................ 18
Notes on Using Devices ................................................................................................................... 20
Notes on Turning on the Power ........................................................................................................ 21
CHAPTER 3
CPU ............................................................................................................ 23
3.1
Memory Space ..................................................................................................................................
3.2
CPU Architecture ..............................................................................................................................
3.3
Instruction Cache ..............................................................................................................................
3.3.1
Instruction Cache Control Register (ICHCR) ...............................................................................
3.3.2
Status in Each Operation Mode ...................................................................................................
3.3.3
Instruction Cache Setting Method ...............................................................................................
3.4
Dedicated Registers .........................................................................................................................
3.4.1
Program Status Register (PS) .....................................................................................................
3.5
General-purpose Registers ...............................................................................................................
3.6
Data Structure ...................................................................................................................................
3.7
Word Alignment ................................................................................................................................
3.8
Memory Mapping ..............................................................................................................................
3.9
Outline of Instructions .......................................................................................................................
3.9.1
Branch Instruction with Delay Slot ...............................................................................................
3.9.2
Branch Instruction with No Delay Slot .........................................................................................
3.10 Exception, Interrupt, and Trap (EIT) .................................................................................................
3.10.1 EIT Interrupt Level .......................................................................................................................
3.10.2 Interrupt Control Register (ICR) ...................................................................................................
3.10.3 System Stack Pointer (SSP) ........................................................................................................
3.10.4 Interrupt Stack .............................................................................................................................
3.10.5 Table Base Register (TBR) .........................................................................................................
3.10.6 EIT vector table ...........................................................................................................................
3.10.7 Multi-EIT Processing ...................................................................................................................
3.10.8 EIT Processing ............................................................................................................................
3.11 Reset Sequence ...............................................................................................................................
3.12 Clock .................................................................................................................................................
3.12.1 Reset Source Register (RSRR) and Watchdog Cycle Control Register (WTCR) ........................
3.12.2 DMA Request Suppression Register (PDRR) .............................................................................
3.12.3 Timebase Timer Clear Register (CTBR) .....................................................................................
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24
26
29
33
35
37
40
43
46
47
48
49
51
53
56
57
58
60
61
62
63
64
66
68
71
72
74
76
77
3.12.4 Gear Control Register (GCR) ...................................................................................................... 78
3.12.5 Watchdog Reset Defer Register (WPR) ...................................................................................... 81
3.12.6 PLL Control Register (PCTR) ...................................................................................................... 82
3.12.7 Watchdog Function ...................................................................................................................... 83
3.12.8 Gear Function .............................................................................................................................. 85
3.12.9 Reset Source Hold Function ........................................................................................................ 88
3.12.10 DMA Suppression Function ......................................................................................................... 90
3.12.11 Clock Doubler Function ............................................................................................................... 92
3.12.12 Example of PLL Clock Setting ..................................................................................................... 94
3.13 Low-power Consumption .................................................................................................................. 97
3.13.1 Standby Control Register (STCR) ............................................................................................... 99
3.13.2 Stop Status ................................................................................................................................ 100
3.13.3 Sleep Status .............................................................................................................................. 102
3.13.4 Status Transition in Low-power Consumption Mode ................................................................. 104
3.14 Memory Access Modes .................................................................................................................. 105
CHAPTER 4
BUS INTERFACE ..................................................................................... 109
4.1
Outline of the Bus Interface ............................................................................................................
4.2
Block Diagram of the Bus Interface ................................................................................................
4.3
Bus Interface Registers ..................................................................................................................
4.3.1
Area Selection Register (ASR) and Area Mask Register (AMR) ...............................................
4.3.2
Area Mode Register 0 (AMD0) ..................................................................................................
4.3.3
Area Mode Register 1 (AMD1) ..................................................................................................
4.3.4
Area Mode Register 32 (AMD32) ..............................................................................................
4.3.5
Area Mode Register 4 (AMD4) ..................................................................................................
4.3.6
Area Mode Register 5 (AMD5) ..................................................................................................
4.3.7
DRAM Control Registers 4 and 5 (DMCR4 and DMCR5) .........................................................
4.3.8
Refresh Control Register (RFCR) ..............................................................................................
4.3.9
External Pin Control Register 0 (EPCR0) ..................................................................................
4.3.10 External Pin Control Register 1 (EPCR1) ..................................................................................
4.3.11 DRAM Signal Control Register (DSCR) ....................................................................................
4.3.12 Little Endian Register (LER) ......................................................................................................
4.4
Bus Operations ...............................................................................................................................
4.4.1
Relationships between Data Bus Widths and Control Signals ..................................................
4.4.2
Big-endian Bus Access ..............................................................................................................
4.4.3
Little-endian Bus Access ...........................................................................................................
4.4.4
Comparison of External Accesses in Big and Little Endian Modes ...........................................
4.4.5
DRAM Connection .....................................................................................................................
4.5
Bus Timing ......................................................................................................................................
4.5.1
Basic Read Cycle ......................................................................................................................
4.5.2
Basic Write Cycle ......................................................................................................................
4.5.3
Read Cycle in Each Mode .........................................................................................................
4.5.4
Write Cycle In Each Mode .........................................................................................................
4.5.5
Read-write Cycle .......................................................................................................................
4.5.6
Automatic Wait Cycle ................................................................................................................
4.5.7
External Wait Cycle ...................................................................................................................
4.5.8
Ordinary DRAM Interface Read Cycle .......................................................................................
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110
113
114
115
118
120
121
122
123
124
127
129
131
132
133
134
135
137
142
146
150
154
157
158
160
162
164
165
166
167
4.5.9
Ordinary DRAM Interface Write Cycle .......................................................................................
4.5.10 Ordinary DRAM Read Cycle ......................................................................................................
4.5.11 Ordinary DRAM Write Cycle ......................................................................................................
4.5.12 Automatic Wait Cycle in the Ordinary DRAM Interface .............................................................
4.5.13 DRAM Interface in high-speed Page Mode ...............................................................................
4.5.14 Single DRAM Interface Read Cycle ..........................................................................................
4.5.15 Single DRAM Interface Write Cycle ...........................................................................................
4.5.16 Single DRAM Interface ..............................................................................................................
4.5.17 Hyper DRAM Interface Read Cycle ...........................................................................................
4.5.18 Hyper DRAM Interface Write Cycle ...........................................................................................
4.5.19 Hyper DRAM Interface ..............................................................................................................
4.5.20 DRAM Refresh ..........................................................................................................................
4.5.21 External Bus Request ................................................................................................................
4.6
Internal Clock Multiplication (Clock Doubler) ..................................................................................
4.7
Sample Program for External Bus Operations ................................................................................
CHAPTER 5
5.1
5.2
5.3
5.4
6.1
6.2
6.2.1
6.2.2
6.3
6.4
192
193
194
195
16-BIT RELOAD TIMER ........................................................................... 199
Outline of the 16-bit Reload Timer ..................................................................................................
Registers of the 16-bit Reload Timer ..............................................................................................
Control Status Register (TMCSR) .............................................................................................
16-bit Timer Register (TMR) and 16-bit Reload Register (TMRLR) ..........................................
16-bit Reload Timer Operations ......................................................................................................
Counter Operation Statuses ...........................................................................................................
CHAPTER 7
7.1
7.2
7.3
7.3.1
7.3.2
7.3.3
7.3.4
7.3.5
7.3.6
7.4
7.5
7.6
7.7
I/O PORT .................................................................................................. 191
Outline of I/O Port ...........................................................................................................................
Port Data Register (PDR2 to PDRI) ................................................................................................
Port Direction Register (DDR2 to DDRI) .........................................................................................
Relationship between External Pins and Switching Registers ........................................................
CHAPTER 6
169
171
173
175
176
178
179
180
181
182
183
184
186
187
188
200
201
202
204
205
207
PWM TIMER ............................................................................................. 209
Outline of the PWM Timer ..............................................................................................................
Block Diagram of the PWM Timer ..................................................................................................
Registers of the PWM Timer ...........................................................................................................
Control/Status Register (PCNH0 to PCNH3, PCNL0 to PCNL3) ...............................................
PWM Cycle Setting Register (PCSR0 to PCSR3) .....................................................................
PWM Duty Setting Register (PDUT0 to PDUT3) .......................................................................
PWM Timer Register (PTMR0 to PTMR3) ................................................................................
General Control Register 1 (GCN1) ..........................................................................................
General Control Register 2 (GCN2) ..........................................................................................
PWM Mode .....................................................................................................................................
One-shot Mode ...............................................................................................................................
PWM Timer Interrupt Resources and Timing Charts ......................................................................
Activating Multiple PWM Timer Channels .......................................................................................
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210
211
213
214
218
219
220
221
224
225
227
228
230
CHAPTER 8
8.1
8.2
8.3
Outline of the U-TIMER .................................................................................................................. 232
Registers of the U-TIMER ............................................................................................................... 233
U-TIMER Operations ...................................................................................................................... 235
CHAPTER 9
9.1
9.2
9.2.1
9.2.2
9.2.3
9.3
9.4
9.5
U-TIMER ................................................................................................... 231
EXTERNAL INTERRUPT/NMI CONTROL SECTION .............................. 237
Outline of the External Interrupt/NMI Control Section .....................................................................
Registers of the External Interrupt/NMI Control Section .................................................................
Enable Interrupt Request Register (ENIR) ................................................................................
External Interrupt Request Register (EIRR) ..............................................................................
External Level Register (ELVR) .................................................................................................
External Interrupt Processing .........................................................................................................
External Interrupt Request Level ....................................................................................................
Non-maskable Interrupt (NMI) Processing .....................................................................................
238
239
240
241
242
243
244
247
CHAPTER 10 DELAYED INTERRUPT MODULE ........................................................... 249
10.1
10.2
10.3
Outline of the Delayed Interrupt Module ......................................................................................... 250
Delayed Interrupt Control Register (DICR) ..................................................................................... 251
Operations of the Delayed Interrupt Module ................................................................................... 252
CHAPTER 11 INTERRUPT CONTROLLER ................................................................... 253
11.1 Outline of the Interrupt Controller ...................................................................................................
11.2 Block Diagram of the Interrupt Controller .......................................................................................
11.3 Registers of the Interrupt Controller ................................................................................................
11.3.1 Interrupt Control Register (ICR00 to ICR47) .............................................................................
11.3.2 Hold Request Cancel Request Level Setting Register (HRCL) .................................................
11.4 Priority Judgment ............................................................................................................................
11.5 Return from Standby Mode (Stop or Sleep) ...................................................................................
11.6 Hold Request Cancel Request .......................................................................................................
11.7 Using the Hold Request Cancel Register (HRCR) .........................................................................
254
255
256
258
259
260
263
264
265
CHAPTER 12 A/D CONVERTER .................................................................................... 269
12.1 Outline of the A/D Converter ...........................................................................................................
12.2 Block Diagram of the A/D Converter ...............................................................................................
12.3 Registers of the A/D Converter .......................................................................................................
12.3.1 Control Status Register (ADCS) ................................................................................................
12.3.2 Data Register (ADCR) ...............................................................................................................
12.4 Operations of the A/D Converter ....................................................................................................
12.5 Converted Data Protection Function ...............................................................................................
12.6 Notes on Using the A/D Converter .................................................................................................
270
271
272
273
278
279
281
283
CHAPTER 13 UART ........................................................................................................ 285
13.1 Outline of UART ..............................................................................................................................
13.2 UART Block Diagram ......................................................................................................................
13.3 UART Registers ..............................................................................................................................
13.3.1 Serial Mode Register (SMR0 to SMR2) .....................................................................................
13.3.2 Serial Control Register (SCR0 to SCR2) ...................................................................................
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286
287
288
289
291
13.3.3
Serial Input Data Register (SIDR0 to SIDR2)/
Serial Output Data Register (SODR0 to SODR2) .....................................................................
13.3.4 Serial Status Register (SSR) .....................................................................................................
13.4 UART Operation Modes and Clock Selection .................................................................................
13.4.1 Asynchronous (Step-synchronous) Modes ................................................................................
13.4.2 CLK Synchronous Mode ............................................................................................................
13.5 UART Interrupts and Flag Setting Timings .....................................................................................
13.6 Notes on Use with Example of UART Application ..........................................................................
13.7 Examples of Setting Baud Rates and U-TIMER Reload Values .....................................................
294
295
297
298
300
302
305
307
CHAPTER 14 DMA CONTROLLER (DMAC) .................................................................. 309
14.1 Outline of the DMA Controller .........................................................................................................
14.2 Block Diagram of the DMA Controller .............................................................................................
14.3 Registers of the DMA Controller .....................................................................................................
14.3.1 DMAC Parameter Descriptor Point (DPDP) ..............................................................................
14.3.2 DMAC Control/Status Register (DACSR) ..................................................................................
14.3.3 DMAC Pin Control Register (DATCR) .......................................................................................
14.3.4 Descriptor Register in RAM .......................................................................................................
14.4 Transfer Modes of DMA Controller .................................................................................................
14.4.1 Step Transfer (Single or Block Transfer) ...................................................................................
14.4.2 Continuous Transfer ..................................................................................................................
14.4.3 Burst Transfer ............................................................................................................................
14.4.4 Differences in DREQ Sensing Modes (Note on Edge Sensing) ................................................
14.4.5 Differences in DREQ Sensing Modes (Note on Level Sensing) ................................................
14.5 Transfer Acknowledge Signal Output and Transfer End Signal Output ..........................................
14.6 Notes on DMA Controller ................................................................................................................
14.7 DMA Controller Timing Chart ..........................................................................................................
14.7.1 Timing Chart for Descriptor Access Section ..............................................................................
14.7.2 Timing Chart for Data Transfer Section .....................................................................................
14.7.3 Timing Chart for Stopping a Transfer in Continuous Transfer Mode .........................................
14.7.4 Timing Chart for Transfer End Operation ..................................................................................
14.8 DMA Controller Software Trigger Circuit (STRG) ...........................................................................
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311
312
313
314
316
318
321
324
325
326
327
328
329
330
332
333
335
336
338
340
CHAPTER 15 BIT SEARCH MODULE ........................................................................... 341
15.1
15.2
15.3
Outline of the Bit Search Module .................................................................................................... 342
Registers of the Bit Search Module ................................................................................................ 343
Bit Search Module Operations and Save/Restore Processing ....................................................... 345
CHAPTER 16 SUM-OF-PRODUCTS MACRO (SIMPLE DSP) ....................................... 347
16.1 Outline of DSP ................................................................................................................................
16.2 Block Diagram of the DSP ..............................................................................................................
16.3 Registers of the DSP ......................................................................................................................
16.3.1 Offset Address Initial Value Setting Register (OFAS) ...............................................................
16.3.2 Store Address Initial Value Setting Register (STRS) .................................................................
16.3.3 Offset Control Setting Register (OFSC) ....................................................................................
16.3.4 Offset Register (OFFSS) ...........................................................................................................
16.3.5 Y-RAM Bank Control Register (Y-BANKC) ...............................................................................
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348
349
352
353
354
355
357
358
16.3.6 Offset Data Register (OFSD) .....................................................................................................
16.3.7 Control/Status Register (DSP-CSR) ..........................................................................................
16.3.8 Program Counter (DSP-PC) ......................................................................................................
16.3.9 Delay Register (DSP-LY) ...........................................................................................................
16.3.10 Variable Monitor Register (DSP-OT0 to DSP-OT3) ..................................................................
16.4 DSP Instructions .............................................................................................................................
16.4.1 MAC Instruction .........................................................................................................................
16.4.2 STR Instruction (Transfer Instruction) .......................................................................................
16.4.3 JMP Instruction (Branch Instruction) .........................................................................................
16.5 DSP Operation Mode ......................................................................................................................
16.6 DSP Functions ................................................................................................................................
16.7 DMA Transfer When Y-RAM Bank Is Disabled ..............................................................................
16.8 DMA Transfer When Y-RAM Bank Is Enabled ...............................................................................
16.9 Y-RAM Expansion Configuration ....................................................................................................
16.10 Y-RAM Expansion Mode ................................................................................................................
16.11 Example of Using Y-RAM Expansion Mode ...................................................................................
360
361
364
365
366
367
368
370
372
373
376
379
381
383
384
385
APPENDIX ......................................................................................................................... 391
APPENDIX A I/O Mapping .........................................................................................................................
APPENDIX B Interrupt Vectors ..................................................................................................................
APPENDIX C Pin Status in Each CPU State ..............................................................................................
APPENDIX D Notes on Using Little Endian Area .......................................................................................
D.1 Compiler (fcc911) ...........................................................................................................................
D.2 Assembler (fasm911) .....................................................................................................................
D.3 Linker (flnk911) ..............................................................................................................................
D.4 Debugger (sim911, eml911, mon911) ............................................................................................
APPENDIX E Instruction List ......................................................................................................................
E.1 Instruction List ................................................................................................................................
E.2 FR family Instruction List ................................................................................................................
392
399
402
409
410
412
413
414
415
416
421
INDEX................................................................................................................................... 435
x
Main changes in this edition
Page
Changes (For details, refer to main body.)
-
Register names are changed.
(DMAC Software Trigger Circuit(STRG) → DMA Controller Software Trigger Circuit (STRG))
(Bus release (BGRNT) → Bus release (BGRNTX))
-
Pin name is changed.
(RDXD → RDX)
9, 12
Function of Table 1.5-1 Explanations of the Pin Functions is changed.
No.1 to 7(P20 to P27 → P61 to P67)
No.12 to 19(This function is valid when analog input is specified in the AIC register. is deleted.)
No.56 to 63(For details on the above pins, see "DRAM interface." → For details on the above pins, see
"CHAPTER 4 BUS INTERFACE".)
19
● Crystal oscillation circuit is changed.
(Please ask the crystal maker to evaluate the oscillational characteristics of the crystal and this device. is
added.)
20
■ Notes on During Operation of PLL Clock Mode is changed. (Description is changed.)
■ Watchdog Timer Function is added.
21
■ Handling when the Power-supply Voltage is Unstable or the Power Supply is Intercepted is added.
24
Figure 3.1-1 Memory Mapping of MB91121 is changed.
(This area serves as RAM in the mode in which YBANK of DSP macro is not used. → This area serves as
RAM when the DSP macro is not used and YBEN bit of Y-BANKC = "0".)
31
Bits 7 to 4: Sub-block Valid (SBV3 to SBV0) is changed.
(When an SBV* bit is 1, these bits have the current instruction data of the address indicated by a tag in the
corresponding sub-block.A sub-block usually stores two instructions (excluding an immediate value transfer
instruction). → If sub-block valid (SBV3 to SBV1) is set to "1", the current instruction data of the address
indicated by the tag in the corresponding sub-block is entered. In the sub-block, two instructions are normally
stored (excluding immediate transfer instructions).)
50
Figure 3.8-2 Common Memory Mapping of the FR Family is changed.
(The description of (PDR) is deleted.)
65
Table 3.10-3 Vector Table (2 / 2) is changed.
(The description of INT instruction is added to Vector No. FF)
73
Figure 3.12-2 Block Diagram of the Clock Generator is changed.
(Line is deleted.)
(The description of HSTX pin is deleted.)
81
Bits 07 to 00: D7 to D0 is changed.
(Since these bits are automatically cleared for stop, sleep, or hold, watchdog reset is automatically deferred
under these conditions. is deleted.)
83
3.12.7 Watchdog Function is changed.
(Watchdog Function → Watchdog Timer Function)
Overview of 3.12.7 Watchdog Timer Function is changed.
■ Setting of the Watchdog Timer Function is changed.
84
■ Causes of Reset Delays Other than Programs is added.
xi
Page
Changes (For details, refer to main body.)
87
■ Blocks Using the Peripheral Clock is changed.
• PWM timer (ch.0, ch.1, ch.2) → • U-TIMER (ch.0, ch.1, ch.2)
94
Figure 3.12-10 Example of PLL Clock Setting is changed.
(DBLACK=1 → DBLAK=1)
145
Figure 4.4-16 Example of Connection between MB91121 and External Device (16-bit Bus) and Figure 4.417 Example of Connection between MB91121 and External Device (8-bit Bus) are changed.
(CSnX CSmX → CS0X to CS5X)
166
[Operations] is changed.
(An RDY signal is detected not during but after the automatic wait cycle. → The RDY is detected in the last
cycle of an automatic wait.)
195
Table 5.4-1 External Pin Function Selection (1 / 4) is changed. (Switching register of Pin No.8 is changed.)
(EPCR1 (AE24 bit) → EPCR1 (AE23 bit))
200
Figure 6.1-1 Block Diagram of the 16-bit Reload Timer is changed.
(The description of EXCK is deleted.)
(The description of TIM0 to TIM2 is added.)
202
■ Control Status Register (TMCSR) is changed. (Initial value in the figure is changed.)
(-000H → 0000 00000000H)
213
Figure 7.3-1 Registers of the PWM Timer is changed. (Register Abbreviation and Register are changed.)
233
Overview of 8.2 Registers of the U-TIMER is changed.
((UTIM0 to UTIM3) → (UTIM0 to UTIM2))
((UTIMR0 to UTIMR3) → (UTIMR0 to UTIMR2))
((UTIMC0 to UTIMC3) → (UTIMC0 to UTIMC2))
■ U-TIMER Value Register: UTIM (U-TIMER) is changed.
(UTIM0 to UTIM3 → UTIM0Å` UTIM2)
■ Reload Register: UTIMR (Reload Register) is changed.
(UTIMR0 to UTIMR3 → UTIMR0 to UTIMR2)
(Note: When U-TIMER is used as a baud rate in the UART mode 2 (CLK synchronous mode), the setting of
UTIMR=0 is prohibited. is added.)
■ U-TIMER Control Register: UTIMC (U-TIMER Control Register) is changed.
(UTIMC0 to UTIMC3 → UTIMC0 to UTIMC2)
235
■ Calculating the Baud Rate is changed.
(Note: When U-TIMER is used as a baud rate in the UART mode 2 (CLK synchronous mode), the setting of
UTIMR=0 is prohibited. is added.)
240
9.2.1 Enable Interrupt Request Register (ENIR) is changed.
(In this device, writing data to EN4 to EN7 bits has no significance. Write 0 into EN4 to EN7 bits. is deleted.)
243
■ External Interrupt Procedure is changed.
(1. The general-purpose I/O port that is shared with the pin as using the external interrupt input is set to the
input port. is added.)
245
■ Notes If Restoring from Clock Generation STOP Status Performed Using an External Interrupt is added.
246
■ Recovery Operations from STOP Status is added.
254
■ Hardware Configuration of the Interrupt Controller is changed.
(This module consists of the following sections: → This module consists of the following registers and circuits: )
xii
Page
256, 257
Changes (For details, refer to main body.)
Figure 11.3-1 Registers of the Interrupt Controller is changed. (Read/Write of ICR4 is changed.)
(R → R/W)
259
■ Hold Request Cancel Request Level Setting Register (HRCL) is changed. (Read/Write of LVL4 in the figure is changed.)
(R → R/W)
271
Figure 12.2-1 Block Diagram of the A/D Converter is changed.
(AVR → AVRH AVRL)
(TIM0 (internal connection) → TIM2(internal connection))
273
■ Control Status Register (ADCS) is changed. (Read/Write of STRT in the figure is changed.)
(W → R/W)
277
Note is added.
(Note:
Please do not set the A/D conversion mode setting bit (MD1,MD0) and the A/D conversion end channel
selection bit (ANE2, ANE1, ANE0) by the read-modify-write type instruction after setting the start channel
to the A/D conversion start channel selection bit (ANS2, ANS1, ANS0). From ANS2, ANS1, and the ANS0
bit, the last conversion channel is read until starting the A/D conversion. Therefore, when MD1, the MD0 bit,
ANE2, ANE1, and the ANE0 bit are set by the read-modify-write type instruction after setting the start channel to ANS2, ANS1, and the ANS0 bit, the value of ANE2, ANE1, and the ANE0 bit may be written.)
278
■ Data Register (ADCR) is changed. (Initial value in the figure is changed.)
(0 0 0 0 0 0 X X → - - - - - - X X)
289
■ Serial Mode Register (SMR0 to SMR2) is changed. (Read/Write of CS0 in the figure is changed.)
(W → R/W)
298, 299
● Detecting the start bit is added.
300
● Initialization is changed.
(Specify: Clock input → -CS0: Clock input)
314
Bits 31, 27, 23, 19, 15, 11, 7, and 3: DER7 to DER0 (DMA ERror) is changed.
(There are also DMA request sources that do not cause an error. → For details, see "■ DMA Transfer
Request Resources" in "14.6 Notes on DMA Controller".)
327
14.4.4 Differences in DREQ Sensing Modes (Note on Edge Sensing) is changed.
(Note on Edge Mode → Note on Edge Sensing)
328
14.4.5 Differences in DREQ Sensing Modes (Note on Level Sensing) is changed.
(Note on Level Mode → Note on Level Sensing)
Figure 14.4-6 Differences in DREQ Sensing Modes (Note on Level Mode) is changed.
(Up to 1 cycle → Up to 1 tcyc)
329
Overview of 14.5 Transfer Acknowledge Signal Output and Transfer End Signal Output is changed.
(DMACT counter → DMACT bit)
■ Transfer Acknowledge Signal Output is changed.
(AKSn, AKDn bits in DATCR → AKSE, AKDE bits in DATCR)
■ Transfer End Signal Output is changed.
(EPSn and EPDn bits in DATCR → EPSE and EPDE bits in DATCR)
331
❍ DREQ2 is deleted.
340
Bit 9: CLRX and ■ Operation of DMA Controller Software Trigger Circuit are changed.
(ACK from DMAC → DACK from DMA controller)
xiii
Page
Changes (For details, refer to main body.)
350
Table 16.2-1 Outline of DSP Blocks (1 / 2) is changed. (Explanation of DSP-CSR is changed.)
((used for conditional branch instructions in DSP1.) → (used for conditional branch instructions in DSP.))
355
■ Offset Control Setting Register (OFSC) is changed. (Read/Write of OFCC is changed.)
((W) → (R/W))
357
Overview of 16.3.4 Offset Register (OFFSS) and Bits 7 to 0: OFIA7 to OFIA0: Address setting by performing the offset operation are changed.
(IRAM → I-RAM)
362
Bit 3: IrqDSP (software interrupt request flag) is changed (Table is changed.)
(DSP1 → DSP)
(YBANK → Y-RAM1)
366
■ Variable Monitor Register (DSP-OT0 to DSP-OT3) is changed. (Figure is changed.)
(The description of Read Only is deleted.)
372
Bit 13: HLT (HLT instruction specification flag) is changed.
(uDSP → DSP)
(RunDSP flag → RunDSP bit)
Bit 12: SIRQ (INT instruction specification flag) is changed.
(IrqDSP flag → IrqDSP bit)
383
Figure 16.9-1 Y-RAM Expansion Configuration is changed.
(CLR → CLRX)
384
● Both MAC and STR instructions is changed.
(OFA00 to OFA05 → OFA00 to OFA11)
● A MAC instruction has the same mode as the above, but an STR instruction has a different mode is
changed.
(For details, see "Bit 4: STRM (STR mode setting)" in "16.3.3 Offset Control Setting Register (OFSC)". is
added.)
387
● Setting the offset specification is changed.
(Ch → 0CH)
393 to 395
393, 395
415 to 434
The register abbreviations of the following registers in Table A-1 I/O Mapping are changed.
(SSR0, SIDR0/SODR0, SCR0, SMR0, SSR1, SIDR1/SODR1, SCR1, SMR1, SSR2, SIDR2/SODR2, SCR2,
SMR2, TMRLR0, TMR0, TMCSR0, TMRLR1, TMR1, TMCSR1, TMRLR2, TMR2, TMCSR2, STRG,
UTIM0/UTIMR0, UTIMC0, UTIM1/UTIMR1, UTIMC1, UTIM2/UTIMR2, UTIMC2, PTMR0, PCSR0,
PDUT0, PCNH0, PCNL0, PTMR1, PCSR1, PDUT1, PCNH1, PCNL1, PTMR 2, PCSR2, PDUT2, PCNH2,
PCNL2, PTMR3, PCSR3, PDUT3, PCNH3, PCNL3)
Read/Write of the following registers in Table A-1 I/O Mapping are changed.
(SSR0, SCR0, SSR1, SCR1, SSR2, SCR2, Y-BANKC)
APPENDIX E Instruction List is changed.
xiv
CHAPTER 1
OUTLINE OF MB91121
This chapter explains the features and functions of
MB91121 with a block diagram and other figures,
including an outline of the pin function.
1.1 Features of MB91121
1.2 Block Diagram of MB91121
1.3 Outside Dimension Drawing
1.4 Pin Arrangement Diagram
1.5 Explanations of the Pin Functions
1.6 I/O Circuit Types
1
CHAPTER 1 OUTLINE OF MB91121
1.1
Features of MB91121
MB91121 is a microcontroller with a 32-bit RISC CPU (FR family) as its core. This
microcontroller contains I/O resources and bus control features for internal control that
requires high-performance, high-speed CPU processing. It also contains the sum-ofproducts unit (simple DSP) having a built-in program RAM.
External bus access is basically used to support a wide address space accessed by the
32-bit CPU. For high-speed CPU instruction processing, however, a 1K-byte instruction
cache memory and 4K-byte (8K-byte when DSP is not used) RAM are included.
This microcontroller is based on the optimum specifications for internal use in a digital
camera, navigation system, high-performance facsimile, or printer control system
requiring high CPU performance.
■ Features of MB91121
● FR-CPU
• 32-bit RISC, load/store architecture, and five-stage pipeline
• Operating frequency: 50 MHz inside [25 MHz outside] (when PLL is used and the source oscillation is
12.5 MHz)
• General-purpose register: 32 bits ×16
• 16-bit fixed-length instructions (basic instructions), one instruction/cycle
• Instructions suitable for built-in control: Inter-memory transfer, bit processing, and barrel shift
• "H" level language instructions: Function entry/exit and register contents multi-load/store
• Register interlock function: Making assembler descriptions easy
• Branch instruction with delayed slot: Reducing the overhead at branching
• Built-in multiplier: Support on the instruction level
- Signed 32-bit multiplication: 5 cycles
- Signed 16-bit multiplication: 3 cycles
• Interrupt (PC and PS save): 6 cycles, 16 priority levels
● Bus interface
• Clock doubler: Operating at 50 MHz inside and 25 MHz outside
• 25-bit address bus (32M-byte space)
• 16/8-bit data bus
• Basic external bus cycle: 2 clock cycles
• Chip select outputs that can be set in the minimum units of 64 Kbytes: 6
• Memory interface support
- DRAM interface (Areas 4 and 5)
• Automatic wait cycle: Arbitrary setting from 0 to 7 cycles for each area
• Unused data/address pin available as an I/O port
• Little endian mode supported (One selected area from 1 to 5)
2
CHAPTER 1 OUTLINE OF MB91121
● DRAM interface
• Two-bank independent control (Areas 4 and 5)
• Double CAS DRAM (standard DRAM interface)/Single CAS DRAM/Hyper DRAM
• Basic bus cycle: 5 in ordinary mode and 2 in high-speed page mode
• Programmable waveform: Automatic one-cycle wait insertion into RAS and CAS
• DRAM refresh
- CBR refresh (Arbitrary interval setting using the 6-bit timer)
- Self-refresh mode
• 8, 9, 10, or 12 column addresses
• 2CAS/1WE or 2WE/1CAS selectable
■ Sum-of-products Macro (Simple DSP)
• High-speed sum-of-products (1 machine cycle)
• Data format: 16-bit fixed point (16 × 16 + 40 bits)
• Instruction area: 256 words × 16 bits
• Data area: 64 words × 16 bits × 1 and 1024 words × 16 bits × 2 (bank)
• Rounding and saturation
• Number of items to be added: Up to 32 items
• Instruction: MAC instruction/STR instruction/JMP instruction
• Delayed processing: Freely transferable within 32 words
• Fixed point method: Selectable from Q12 to Q15
• Program execution control: Eight calculation programs selectable externally
• Variable monitor: Monitoring of the calculation result up to 4 words without stopping the program
• Efficient data variable area: Data variable area available for two banks; another bank can be used to
execute the DSP calculation program during data variable access from the
CPU.
● Cache memory
• 1K-byte instruction cache
• Two-way set associative
• 32 blocks/way or 4 entries (4 words)/block
• Lock function (Keeping specific program codes resident in a cache)
● DMAC (DMA controller)
• 8 channels
• Transfer sources: External pin, UART interrupt request, DSP macro, and software activation
• Transfer sequences
- Step or block transfer
- Burst or continuous transfer
• Transfer data length: 8, 16, or 32 bits selectable
• Pause by interrupt request
3
CHAPTER 1 OUTLINE OF MB91121
● UART
• Three independent channels
• Full-duplex double buffer
• Data length: 7 to 9 bits (with no parity) or 6 to 8 bits (with parity)
• Asynchronous (step-synchronous) or CLK synchronous selectable
• Multiprocessor mode
• Built-in 16-bit timer (U-TIMER) as baud rate generator: Any baud rate generated
• External clock available as transfer clock
• Error detection: Parity, frame, and overrun errors
● A/D converter (Successive conversion)
• 10-bit resolution, 8 channels
• Successive approximation: 5.6 µs at 25 MHz
• Built-in sample & hold circuit
• Conversion mode: Single, scan, or repetitive conversion selectable
• Activation: Software, external trigger, or internal timer selectable
● Reload timer
• 16-bit timer: 3 channels
• Internal clock: Two-clock-cycle resolution, number of divisions selectable from 2, 8, and 32
● Other interval timer
• 16-bit timer: 3 channels (U-TIMER)
• PWM timer: 4 channels
• Watchdog timer: 1 channel
● Bit search module
• Searching the position of the first bit changing to "1" or "0" from MSB in a word
● Interrupt controller
• External interrupt input: Non-maskable interrupt (NMIX), ordinary interrupt x 8 (INT0 to INT7)
• Internal interrupt sources: UART, DMAC, A/D, U-TIMER, delayed interrupt, and DSP macro
• The priorities of interrupts other than a non-maskable interrupt can be set to 16 levels by programming.
● Reset sources
• Power-on reset, watchdog timer, software reset, and external reset
● Low-power consumption mode
• Sleep and stop
4
CHAPTER 1 OUTLINE OF MB91121
● Clock control
• Gear function: The CPU and peripheral operation clock frequencies can be set independently.
The gear clock can be selected from 1/1, 1/2, 1/4, and 1/8 (or 1/2, 1/4, 1/8, and 1/16).
The peripheral operation clock frequency is set to up to 25 MHz.
● Other
• Package: LQFP-120
• CMOS technology: 0.35 µm
• Power supply: 3.3 V plus or minus 0.3 V
5
CHAPTER 1 OUTLINE OF MB91121
1.2
Block Diagram of MB91121
Figure 1.2-1 shows a general block diagram of MB91121.
■ General Block Diagram of MB91121
Figure 1.2-1 General Block Diagram of MB91121
FR CPU
RAM 4KB
I-bus
Bit Search Module
DMAC (8ch)
(16 bit)
DREQ0 DREQ1 DREQ2
DACK0 DACK1 DACK2
EOP0 EOP1 EOP2
D-bus (32bit)
DSP macro
(Built-in RAM 4KB)
Instruction Cache
1KB
Harvard
Princeton
Bus Converter
C-bus
Bus Controller
DRAM Controller
32bit
16bit
Bus Converter
(32 bit)
X0, X1
RSTX
INT0 to INT7
NMIX
AN0 to AN7
AVCC, AVSS
AVRH, AVRL
D31 to D16
A24 to A00
RDX
WR0X, WR1X
RDY
CLK
CS0X to CS5X
BRQ, BGRNTX
RAS0, RAS1
CS0L, CS1L
CS0H, CS1H
DW0X, DW1X
Port 0 - B
Clock Control Unit
(Watch Dog Timer)
STRG
Soft DMA starter
Interrupt Control
Unit
10bit A/D
Converter (8ch)
Reload Timer (3ch)
R-bus (16bit)
UART (3ch)
with
Baud Rate Timer
SI0, SI1, SI2
SO0, SO1, SO2
SC0, SC1, SC2
PWM Timer (4ch)
OCPA0 to OCPA3
TRG0 to TRG3
Port
Notes:
• The above figure shows the pins by functions. The actual pins are partially multiplexed.
• When using REALOS, manage the time using the external interrupt function or the internal timer.
6
CHAPTER 1 OUTLINE OF MB91121
1.3
Outside Dimension Drawing
Figure 1.3-1 shows the outside dimensions of MB91121.
■ Outside Dimension Drawing of LQFP-120
Figure 1.3-1 Outside Dimension Drawing of LQFP-120
120-pin plastic LQFP
Lead pitch
0.50 mm
Package width ×
package length
16.0 × 16.0 mm
Lead shape
Gullwing
Sealing method
Plastic mold
M ounting height
1.70 mm MAX
Weight
0.88 g
Code
(Reference)
P-LFQFP120-16×16-0.50
(FPT-120P-M21)
120-pin plastic LQFP
(FPT-120P-M21)
Note 1) * : These dimensions do not include resin protrusion.
Resin protrusion is +0.25(.010) MAX(each side).
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
18.00±0.20(.709±.008)SQ
+0.40
* 16.00 –0.10 .630 +.016
–.004 SQ
90
61
91
60
0.08(.003)
Details of "A" part
+0.20
1.50 –0.10
+.008
(Mounting height)
.059 –.004
INDEX
0~8˚
120
LEAD No.
1
30
0.50(.020)
C
"A"
31
2002 FUJITSU LIMITED F120033S-c-4-4
0.22±0.05
(.009±.002)
0.08(.003)
M
0.145
.006
+0.05
–0.03
+.002
–.001
0.60±0.15
(.024±.006)
0.10±0.05
(.004±.002)
(Stand off)
0.25(.010)
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
7
CHAPTER 1 OUTLINE OF MB91121
1.4
Pin Arrangement Diagram
Figure 1.4-1 shows the pin arrangement of MB91121.
■ Pin Arrangement Diagram of LQFP-120
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
RAS1/PB4
DW0X/PB3
CS0H/PB2
CS0L/PB1
RAS0/PB0
VCC
X0
X1
VSS
PI1/EOP2/ATGX
PI0/DACK2
PE7/DREQ2
PE6/EOP1
PE5/DACK1
PE4/DREQ1
PE3/EOP0
PE2/DACK0
PE1/DREQ0
PE0/SC2
PF7/SO2
PF6/SI2
PF5/SC1
PF4/SO1
PF3/SI1
PF2/SC0
PF1/SO0
VSS
PF0/SI0
PG7/INT7/TRG3
PG6/INT6/TRG2
Figure 1.4-1 Pin Arrangement Diagram of LQFP-120
MB91121
(TOP VIEW)
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
P26/D22
P27/D23
D24
D25
D26
D27
D28
D29
D30
D31
VSS
A00
A01
A02
A03
A04
A05
A06
A07
VCC
A08
A09
A10
A11
A12
A13
A14
A15
VSS
P60/A16
PB5/CS1L
PB6/CS1H
PB7/DW1X
VCC
CS0X
PA1/CS1X
PA2/CS2X
PA3/CS3X
PA4/CS4X
PA5/CS5X
PA6/CLK
NMIX
MD3
RSTX
VSS
MD0
MD1
MD2
P80/RDY
P81/BGRNTX
P82/BRQ
RDX
WR0X
P85/WR1X
P20/D16
P21/D17
P22/D18
P23/D19
P24/D20
P25/D21
8
PG5/INT5/TRG1
PG4/INT4/TRG0
PG3/INT3
PG2/INT2
PG1/INT1
PG0/INT0
VCC
PH7/OCPA3
PH6/OCPA2
PH5/OCPA1
PH4/OCPA0
AN7
AN6
AN5
AN4
AN3
AN2
AN1
AN0
AVSS/AVRL
AVRH
AVCC
A24
A23/P67
A22/P66
A21/P65
A20/P64
A19/P63
A18/P62
A17/P61
CHAPTER 1 OUTLINE OF MB91121
1.5
Explanations of the Pin Functions
Table 1.5-1 explains the functions of the MB91120 pins.
■ Explanations of the Pin Functions
Table 1.5-1 Explanations of the Pin Functions (1 / 6)
No.
Pin name
I/O circuit
type
1
2
3
4
5
6
7
A17/P61
A18/P62
A19/P63
A20/P64
A21/P65
A22/P66
A23/P67
F
Bits 16 to 23 of the external data bus
When the external bus width is set to 8 bits, these pins can be used as ports
P61 to P67.
8
A24
M
Bit 24 of the external address bus
9
AVCC
-
A/D converter VCC power supply
10
AVRH
-
A/D converter reference voltage (high potential side). Always turn this pin
on and off when AVRH or a greater potential is applied to VCC.
11
AVSS/AVRL
-
A/D converter VSS power supply and reference voltage (low potential side)
12 to
19
AN0 to AN7
[AN0 to AN7] A/D converter analog inputs.
20
21
22
23
OCPA0/PH4
OCPA1/PH5
OCPA2/PH6
OCPA3/PH7
[OCPA0 to OCPA3] PWM timer output. This function is valid when PWM
timer output is enabled.
25
26
27
29
30
3
32
INT0/PG0
INT1/PG1
INT2/PG2
INT3/PG3
INT4/PG4/TRG0
INT5/PG5/TRG1
INT6/PG6/TRG2
INT7/PG7/TRG3
33
SI0/PF0
F
Function
[PH4 to PH7] General-purpose I/O port
[INT0 to INT7] External interrupt
request inputs
F
[TRG0 to TRG3] PWM timer
external trigger inputs
These inputs are used as required
while corresponding input
operations are performed. Therefore,
output by another function should be
disabled unless required.
[PG0 to PG7] General-purpose I/O port
F
[SI0] UART0 data input. This input is used as required if UART0 is
performing an input operation. Therefore, output by another function should
be disabled unless required.
[PF0] General-purpose I/O port
9
CHAPTER 1 OUTLINE OF MB91121
Table 1.5-1 Explanations of the Pin Functions (2 / 6)
No.
Pin name
I/O circuit
type
Function
[SO0] UART0 data output. This function is valid when UART0 data output
is enabled.
35
SO0/PF1
F
[PF1] General-purpose I/O port. This function is valid when UART0 data
output is disabled.
[SC0] UART0 clock I/O. The clock output is valid when UART0 clock
output is enabled.
36
SC0/PF2
F
[PF2] General-purpose I/O port. This function is valid when UART0 data
output is disabled.
37
SI1/PF3
F
[SI1] UART1 data input. This input is used as required if UART1 is
performing an input operation. Therefore, output by another function should
be disabled unless required.
[PF3] General-purpose I/O port
[SO1] UART1 data output. This function is valid when UART1 data output
is enabled.
38
SO1/PF4
F
[PF4] General-purpose I/O port. This function is valid when UART1 data
output is disabled.
[SC1] UART1 clock I/O. The clock output is valid when UART1 clock
output is enabled.
39
SC1/PF5
F
[PF5] General-purpose I/O port. This function is valid when UART1 clock
output is disabled.
40
SI2/PF6
F
[SI2] UART2 data input. This input is used as required if UART2 is
performing an input operation. Therefore, output by any other function
should be disabled unless required.
[PF6] General-purpose I/O port
[SO2] UART2 data output. This function is valid when UART2 data output
is enabled.
41
SO2/PF7
F
[PF7] General-purpose I/O port. This function is valid when UART2 data
output is disabled.
[SC2] UART2 clock I/O. The clock output is valid when UART2 data
output is enabled.
42
SC2/PE0
F
[PE0] General-purpose I/O port. This function is valid when UART2 clock
output is disabled.
43
DREQ0/PE1
F
[DREQ0] DMA external transfer request input (channel 0). This input is
used as required if selected as a DMAC transfer source. Therefore, output by
another function should be disabled unless required.
[PE1] General-purpose I/O port
10
CHAPTER 1 OUTLINE OF MB91121
Table 1.5-1 Explanations of the Pin Functions (3 / 6)
No.
44
Pin name
DACK0/PE2
I/O circuit
type
F
Function
[DACK0] DMAC external transfer acknowledge output (channel 0). This
function is valid when DMAC external transfer acknowledge output is
enabled.
[PE2] General-purpose I/O port. This function is valid when DMAC
external transfer acknowledge output or DACK0 output is disabled.
45
EOP0/PE3
F
[EOP0] DMA EOP output (channel 0). This function is valid when DMAC
EOP output is enabled.
[PE3] General-purpose I/O port
46
DREQ1/PE4
F
[DREQ1] DMA external transfer request input (channel 1). This input is
used as required if selected as a DMAC transfer source. Therefore, output by
another function should be disabled unless required.
[PE4] General-purpose I/O port
47
DACK1/PE5
F
[DACK1] DMAC external transfer acknowledge output (channel 1). This
function is valid when DMAC external transfer acknowledge output is
enabled.
[PE5] General-purpose I/O port. This function is valid when DMAC
external transfer acknowledge output or DACK1 output is disabled.
48
EOP1/PE6
F
[EOP1] DMA EOP output (channel 1). This function is valid when DMAC
EOP output is enabled.
[PE6] General-purpose I/O port
49
DREQ2/PE7
F
[DREQ2] DMA external transfer request input (channel 2). This input is
used as required if selected as a DMAC transfer source. Therefore, output by
another function should be disabled unless required.
[PE7] General-purpose I/O port
50
DACK2/PI0
F
[DACK2] DMAC external transfer acknowledge output (channel 2). This
function is valid when DMAC external transfer acknowledge output is
enabled.
[PI0] General-purpose I/O port. This function is valid when DMAC external
transfer acknowledge output or DACK2 output is disabled.
[EOP2] DMA EOP output (channel 2). This function is valid when DMAC
EOP output is enabled.
51
EOP2/PI1/ATGX
F
[ATGX] A/D converter external trigger input. This input is used as required
if selected as an A/D activation source. Therefore, output by another
function should be disabled unless required.
[PI1] General-purpose I/O port. This function is valid when DMAC transfer
end signal output is disabled.
53
54
X1
X0
A
Clock (oscillator) output
Clock (oscillator) input
11
CHAPTER 1 OUTLINE OF MB91121
Table 1.5-1 Explanations of the Pin Functions (4 / 6)
No.
56
57
58
59
60
61
62
63
Pin name
RAS0/PB0
CS0L/PB1
CS0H/PB2
DW0X/PB3
RAS1/PB4
CS1L/PB5
CS1H/ PB6
DW1X/PB7
I/O circuit
type
F
Function
RAS output of DRAM bank 0
CASL output of DRAM bank 0
CASH output of DRAM bank 0
[WE] output of DRAM bank 0 (low active)
RAS output of DRAM bank 1
CASL output of DRAM bank 1
CASH output of DRAM bank 1
[WE] output of DRAM bank 1 (low active)
For details on the above pins, see "CHAPTER 4 BUS INTERFACE".
[PB0 to PB7] These pins can be used as ports when not occupied.
65
CS0X
66
67
68
69
70
CS1X/PA1
CS2X/PA2
CS3X/PA3
CS4X/PA4
CS5X/PA5
M
F
Chip select 0 output (low active)
Chip select 1 output (low active)
Chip select 2 output (low active)
Chip select 3 output (low active)
Chip select 4 output (low active)
Chip select 5 output (low active)
[PA1 to PA5] These pins can be used as ports when not occupied.
71
CLK/PA6
F
System clock output. This pin outputs the same clock signal as the external
bus operation frequency.
[PA6] This pin can be used as a port when not occupied.
12
72
NMIX
H
Non-Maskable Interrupt (NMI) input (low active)
73
MD3
G
Mode pin 3
Connect the pin directly to VCC or VSS.
74
RSTX
B
External reset signal input
76
77
78
MD0
MD1
MD2
G
Mode pins 0 to 2
Set the MCU basic operation mode using these pins. Connect the pins
directly to VCC or VSS.
79
RDY/P80
C
External ready signal input. When the current bus cycle is not completed, 0
is entered. This pin can be used as a port when not occupied.
80
BGRNTX/P81
F
External bus release status output. When the external bus is released, this pin
outputs a "L" level signal. This pin can be used as a port when not occupied.
81
BRQ/P82
C
External bus release request input. When the external bus is to be released,
"1" is entered. This pin can be used as a port when not occupied.
81
BRQ/P82
C
External bus release request input. When the external bus is to be released,
"1" is entered. This pin can be used as a port when not occupied.
82
RDX
M
External bus read strobe
CHAPTER 1 OUTLINE OF MB91121
Table 1.5-1 Explanations of the Pin Functions (5 / 6)
No.
Pin name
I/O circuit
type
Function
External bus write strobe. The byte positions for control signals and data
buses are as follows.
83
WR0X
M
16-bit bus width
8-bit bus width
D23-16
WR0X
WR0X
D31-24
WR1X
(Available as port)
84
WR1X/P85
F
85
86
87
88
89
90
91
92
D16/P20
D17/P21
D18/P22
D19/P23
D20/P24
D21/P25
D22/P26
D23/P27
C
Bits 16 to 23 of the external data bus
When the external bus width is set to 8 bits, these pins can be used as ports
P20 to P27.
93
94
95
96
97
98
99
100
D24
D25
D26
D27
D28
D29
D30
D31
C
Bits 24 to 31 of the external data bus
102
103
104
105
106
107
108
109
111
112
113
114
115
116
117
118
A00
A01
A02
A03
A04
A05
A06
A07
A08
A09
A10
A11
A12
A13
A14
A15
F
Bits 00 to 15 of the external address bus
120
A16/P60
-
Bit 16 of the external address bus. This pin can be used as port P60 if not
used as the address bus.
Note:
WR1X is in Hi-Z state during reset. To use this pin as a 16-bit bus, connect
the pull-up resistor externally.
13
CHAPTER 1 OUTLINE OF MB91121
Table 1.5-1 Explanations of the Pin Functions (6 / 6)
No.
Pin name
I/O circuit
type
24
55
64
110
VCC
-
Power supply to digital circuit
34
52
75
101
119
VSS
-
Ground level of digital circuit
Function
Note:
At most of the above pins, I/O port and resource input and output are multiplexed in a manner like
xxxx/Pxx. If port and resource outputs conflict at a pin, priority is given to resource output.
14
CHAPTER 1 OUTLINE OF MB91121
1.6
I/O Circuit Types
Table 1.6-1 shows the I/O circuit types.
■ I/O Circuit Types
Table 1.6-1 I/O Circuit Types (1 / 2)
Category
Circuit type
Remarks
A
• Oscillation feedback resistor:
About 1MΩ
X1
Clock input
X0
Standby control
B
VCC
P-ch transistor
Diffused resistor
• CMOS-level hysteresis input
No standby control
With pull-up resistor
N-ch transistor
VSS
Digital input
C
Digital output
• CMOS-level output
CMOS-level input
Standby control
Digital output
Digital input
Standby control
15
CHAPTER 1 OUTLINE OF MB91121
Table 1.6-1 I/O Circuit Types (2 / 2)
Category
Circuit type
Remarks
F
Digital output
• CMOS-level output
• CMOS-level hysteresis input
Standby control
Digital output
Digital input
Standby control
G
• CMOS-level input
No standby control
Digital input
H
• CMOS-level hysteresis input
No standby control
Digital input
M
• CMOS-level output
Digital output
Digital output
N
• Analog input
Analog input
16
CHAPTER 2
DEVICE HANDLING NOTES
This chapter gives MB91121 handling notes.
2.1 Notes on Handling Pins and Circuits
2.2 Notes on Using Devices
2.3 Notes on Turning on the Power
17
CHAPTER 2 DEVICE HANDLING NOTES
2.1
Notes on Handling Pins and Circuits
This section explains latch-up prevention, pin treatment, and circuit handling.
■ Latch-up Prevention
A CMOS IC may experience a latch-up if a voltage higher than Vcc or lower than Vss is applied to an input
or output pin or if a voltage beyond the rating is applied between Vcc and Vss. If this occurs, the powersupply current may generate heat and damage the device. Be sure to keep the supply voltage within the
acceptable range.
Note that when turning the power to the analog circuits on or off, analog supply voltages (AVcc, AVRH)
and the analog input voltage must not exceed the digital supply voltage (Vcc).
■ Pin Treatment
● Treatment of unused pin
If an unused pin is left open, the device may malfunction. To avoid this problem, pull the pin up or down.
● Treatment of NC pin
Open the NC pin to use.
● Power-supply pin
If there are several Vcc and Vss pins, the device is designed to have pins of the same potential connected in
the device to prevent latch-up and other phenomena. However, connect all pins to the power supply or
ground outside the device to reduce unnecessary radiation, to prevent a rise of the ground level from
causing strobe signals to malfunction, and to satisfy the total output current standard.
Connect a current supply to the Vcc and Vss pins of the device with minimum impedance.
It is also recommended to connect a ceramic capacitor of about 0.1µF close to the device between Vcc and
Vss as a bypass capacitor.
● Treatment of mode pins (MD0 to MD3)
Connect these pins directly to Vcc or Vss. To prevent the test mode from being entered mistakenly (as a
result of noise), minimize the pattern length between the mode pins and Vcc or Vss and connect with
minimal impedance.
● Power-on
At power-on, always start the RSTX pin from the low level. Change the signal level to high at least five
cycles of the internal operation clock after the power supply reaches the Vcc level.
● Oscillation input at power-on
At power-on, keep clock signal input until the oscillation stabilization wait status is released.
18
CHAPTER 2 DEVICE HANDLING NOTES
● Hardware standby at power-on
If the power is turned on when the HSTX pin level is low, the device does not enter the standby status.
Although this pin becomes valid after reset, the level should be returned once to high.
● Power-on reset
Be sure to apply power-on reset if power-on fails or the power-supply voltage becomes lower than the
operation guarantee voltage.
● Restrictions on standby status
For the stop or sleep the status, a program should be placed in ROM on the C-bus or in the address area of
external memory. If the program is placed in the ROM address area on the I-bus, the operation after reset
cannot be guaranteed.
● Program execution in I-ROM/RAM area
When executing a program in the I-ROM/RAM area, be sure to enter the area using a JMP-type instruction.
Use a JMP-type instruction also for access from a program in the I-ROM/RAM area to a different program
area.
■ Handling of Circuit
● Crystal oscillation circuit
Noise near the X0 and X1 pins may cause the device to malfunction. A PC board should be designed so
that the X0 and X1 pins, crystal oscillator (or ceramic oscillator), and bypass capacitor are as close to the
ground as possible.
Please ask the crystal maker to evaluate the oscillational characteristics of the crystal and this device.
● Setting of PC Board
It is strongly recommended to surround the X0 and X1 pins with a ground because this PC-board artwork is
expected to stabilize operations.
19
CHAPTER 2 DEVICE HANDLING NOTES
2.2
Notes on Using Devices
This section provides notes on using external reset input and the external clock.
■ Note on Using External Reset Input
A "L" level signal must be input to the RSTX pin for at least five machine cycles to reset the device.
■ Note on Using the External Clock
When using the external clock, simultaneously provide the X0 and X1 pins with clock signals that are
opposite in phase. However, do not use the STOP (oscillation stop) mode (the device stops when the X1
pin level is high in STOP mode). At 12.5 MHz, an external clock can be used by providing the X0 pin only
with a clock signal.
Figure 2.2-1 is an example of using an external clock in the standard case and Figure 2.2-2 is an example of
using an external clock at 12.5 MHz or less.
Figure 2.2-1 Example of Using External Clock (in the Standard Case)
X0
X1
MB91121
Note:
The STOP (oscillation stop) mode cannot be used.
Figure 2.2-2 Example of Using External Clock (at 12.5 MHz or Less)
X0
OPEN
X1
MB91121
■ Notes on During Operation of PLL Clock Mode
On this microcontroller, if in case the crystal oscillator breaks off or an external reference clock input stops
while the PLL clock mode is selected, a self-oscillator circuit contained in the PLL may continue its
operation at its self-running frequency. However, Fujitsu will not guarantee results of operations if such
failure occurs.
■ Watchdog Timer Function
The watchdog timer supported by the FR family monitors the program that performs the reset delay
operation for a specified time. If the program hangs and the reset delay operation is not performed, the
watchdog timer resets the CPU. Therefore, once the watchdog timer is enabled, operation continues until
the CPU is reset.
As an exception, a reset delay automatically occurs if the CPU stops program execution. For the conditions
that apply to this exception, refer to "3.12.7 Watchdog Timer Function".
20
CHAPTER 2 DEVICE HANDLING NOTES
2.3
Notes on Turning on the Power
This section provides notes on pins and inputs at power-on.
■ Treatment of RSTX Pin
At power-on, always start the RSTX pin from the low level. Change the signal level to high at least five
internal operation clock cycles after the power supply reaches the Vcc level.
■ Pin Status
The pin status at power-on is undefined. The circuit is initialized in several clocks after power is turned on
and oscillation starts.
■ Note on Source Oscillation Input
At power-on, maintain clock signal input until the oscillation stabilization wait status is released.
■ Power-on Reset
The device contains built-in registers that are initialized by power-on reset only. To initialize these
registers, apply power-on reset by turning on the power again.
■ A/D Converter
When the A/D converter is not used, connect the pins as follows: AVcc = Vcc, AVss = Vss.
■ Handling when the Power-supply Voltage is Unstable or the Power Supply is
Intercepted
When the power-supply voltage falls below the operating guarantee voltage, the device state becomes
unstable. Therefore, please initialize the device by either of the following methods.
• The external reset is input for 221 of source oscillation or more.
• The power is supplied from the voltage value for the power-on reset (VCC ≤ 0.2 V).
21
CHAPTER 2 DEVICE HANDLING NOTES
22
CHAPTER 3
CPU
This chapter gives basic information on the architecture,
specifications, and instructions to assist in obtaining an
understanding of the functions of the FR family CPU
core.
3.1 Memory Space
3.2 CPU Architecture
3.3 Instruction Cache
3.4 Dedicated Registers
3.5 General-purpose Registers
3.6 Data Structure
3.7 Word Alignment
3.8 Memory Mapping
3.9 Outline of Instructions
3.10 Exception, Interrupt, and Trap (EIT)
3.11 Reset Sequence
3.12 Clock
3.13 Low-power Consumption
3.14 Memory Access Modes
23
CHAPTER 3 CPU
3.1
Memory Space
The FR30 Series has a 4G-byte logical address space (232 addresses) and the CPU
permits linear access.
■ Memory Mapping
Figure 3.1-1 shows the memory mapping of MB91121.
Figure 3.1-1 Memory Mapping of MB91121
External-ROM/external-bus mode
0000 0000H
I/O
Direct addressing area
0000 0400H
I/O
I/O mapping (See Appendix A.)
0000 0800H
Access prohibited
0000 1000H
Internal RAM (4KB)
0000 2000H
Y-RAM1
This area serves as RAM when the DSP macro is not used
and YBEN bit of Y-BANKC = "0" .
Y-RAM0
This area serves as RAM when the DSP macro is not used.
0000 2800H
0000 3000H
Access inhibited
0000 F000H
DSP macro
0000 F300H
Access inhibited
0001 0000H
External area
FFFF FFFFH
24
CHAPTER 3 CPU
● Direct addressing area
The following area in the address space is used for input and output. This area is called the direct
addressing area. An operand address can be specified directly in an instruction.
Depending on the access data size, the direct addressing area differs as follows:
• Byte data access: 000H to 0FFH
• Half-word data access: 000H to 1FFH
• Word data access: 000H to 3FFH
25
CHAPTER 3 CPU
3.2
CPU Architecture
The FR CPU is a high-performance core based on the RISC architecture with highfunction instructions for built-in uses.
■ Features of the CPU Architecture
● RISC architecture
Basic instructions: One instruction/cycle
● 32-bit architecture
General-purpose register: 32 bits × 16
● 4G-byte linear space
● Mounted multiplier
• Signed 32-bit multiplication: 5 cycles
• Signed 16-bit multiplication: 3 cycles
● Strengthened interrupt processing function
• High response speed (6 cycles)
• Multiple interrupt support
• Level masking function (16 levels)
● Strengthened I/O operation instructions
• Inter-memory transfer function
• Bit processing instruction
● High coding efficiency
Basic instruction word length: 16 bits
● Low-power consumption mode
Sleep or stop
26
CHAPTER 3 CPU
■ Structure of the Internal Architecture
The FR CPU has the Harvard architecture where the instruction and data buses are independent of each
other.
An on-chip instruction cache is connected to the instruction bus (I-bus).
A 32-bit ↔ 16-bit bus converter is connected to the data bus (D-bus) to realize an interface between the
CPU and peripheral resources. A Harvard ↔ Princeton bus converter is connected both to I-bus and D-bus
to realize an interface between the CPU and bus controller.
Figure 3.2-1 shows the structure of the internal architecture.
Figure 3.2-1 Structure of the Internal Architecture
FR CPU
D-bus
I-bus
32
I-ADDR
Instruction
cache
16
Harvard
I-DATA
Princeton
bus converter
32
32bit
D-ADDR
16bit
32
bus converter
16
D-DATA
R-bus
C-bus
Resource
32
Bus controller
● CPU
The CPU is the FR architecture of a 32-bit RISC implemented in compact form.
To execute an instruction per cycle, the CPU has a five-stage instruction pipeline system. This pipeline
consists of the following stages:
• Instruction fetch (IF): Output an instruction address and fetch an instruction.
• Instruction decode (ID): Decode the fetched instruction and read the register.
• Execution (EX): Execute the operation.
• Memory access (MA): Ensure load or store memory access.
• Write back (WB): Write the operation results (or loaded memory data) into the register.
Figure 3.2-1 shows the instruction pipeline.
27
CHAPTER 3 CPU
Figure 3.2-2 Instruction Pipeline
CLK
Instruction 1
WB
Instruction 2
MA
WB
Instruction 3
EX
MA
WB
Instruction 4
ID
EX
MA
WB
Instruction 5
IF
ID
EX
MA
WB
IF
ID
EX
MA
Instruction 6
WB
Instructions are not executed in a particular order. If instruction A enters the pipeline before instruction B,
instruction A attains the write-back stage before instruction B.
As a rule, instructions are executed at the speed of one instruction per cycle. However, several cycles are
necessary for a load/store instruction with a memory wait, a branch instruction with no delayed slot, or a
multi-cycle instruction. The instruction execution speed also decreases if instructions are supplied slowly.
For details on the instructions, see "3.9 Outline of Instructions".
● Instruction cache
The on-chip instruction cache enables a high-performance system to be constructed without extra costs on
the external high-speed memory and its control logic. Even if the external bus speed is slow, instructions
can be supplied to the CPU at high speed.
For details on the instructions, see "3.3 Instruction Cache".
● 32-bit ↔ 16-bit bus converter
This converter interfaces 32-bit D-bus and 16-bit R-bus to realize access from the CPU to the internal
peripheral circuits.
If the CPU makes 32-bit access, this bus converter converts the access into two 16-bit accesses to the Rbus. The access width is limited on some internal peripheral circuits.
● Harvard ↔ Princeton bus converter
This converter coordinates CPU instruction access and data access to realize a smooth interface with an
external bus.
The CPU has the Harvard architecture of an instruction bus and a data bus, while the bus controller for
external bus control has the Princeton architecture of a single bus. This bus converter gives priorities to
CPU instruction access and data access to control access to the bus controller. This function always
optimizes the external bus access order.
This converter has a two-word write buffer to eliminate the CPU bus wait time and a one-word prefetch
buffer to fetch an instruction.
28
CHAPTER 3 CPU
3.3
Instruction Cache
The instruction cache is a temporary storage memory device. For access from external
low-speed memory to an instruction code, the instruction cache holds codes once
accessed to increase the speed of the second or later access.
The instruction cache and instruction cache tag do not allow direct read or write access
by software.
Whenever enabling (ON) and then disabling (OFF) the instruction cache, use the
subroutine described in Section "3.3.3 Instruction Cache Setting Method".
■ Cacheable Areas of the Instruction Cache
All the space in the instruction cache is available for caching.
• If internal ROM is mounted, its space is also used for caching.
• Since no instruction access is assumed to an external area or a space other than the internal ROM, codes
are cached even after instruction access to a control register in the I/O area.
• Even when the external memory contents are updated by DMA transfer, the cache contents are not made
coherent. In this case, flash the cache to maintain coherency.
■ Configuration of the Instruction Cache
• Basic instruction length of the FR family: 2 bytes
• Block placement: Two-way set associative
• Block
- 1 way = 32 blocks
- 1 block = 16 bytes (4 sub-blocks)
- 1 sub-block = 4 bytes (one bus access)
Figure 3.3-1 shows the configuration of the instruction cache.
29
CHAPTER 3 CPU
Figure 3.3-1 Configuration of the Instruction Cache
4 bytes
4 bytes
4 bytes
4 bytes
4 bytes
I 3
I 2
I 1
I 0
Cache tag
Sub-block 3
Sub-block 2
Sub-block 1
Sub-block 0
Block 0
Cache tag
Sub-block 3
Sub-block 2
Sub-block 1
Sub-block 0
Block 31
Cache tag
Sub-block 3
Sub-block 2
Sub-block 1
Sub-block 0
Block 0
Cache tag
Sub-block 3
Sub-block 2
Sub-block 1 Sub-block 0
Way 1
32 block
Way 2
32 block
30
Block 31
CHAPTER 3 CPU
■ Configuration of the Instruction Cache Tag
Figure 3.3-2 shows the configuration of the instruction cache tag.
Figure 3.3-2 Configuration of the Instruction Cache Tag
Way 1
31
09
Address tag
07
08
Blank
06
05
04
03
02
SBV3 SBV2 SBV1 SBV0 TAGV Blank
Sub-block valid
LRU
Entry lock
01
00
LRU
ETLK
Tag valid
Way 2
31
09
Address tag
07
08
Blank
06
05
04
03
SBV3 SBV2 SBV1 SBV0 TAGV
Sub-block valid
02
01
Blank
00
ETLK
Tag valid
Entry lock
Bits 31 to 9: Address Tag
These bits have the upper 23 bits of the memory address of the instruction cached in the corresponding
block.
Memory address IA of the instruction data stored at sub-block k in block i is:
IA = Address tag × 211 + i × 24 + k × 22
This tag is used to check that the instruction address requested by the CPU for access matches.
The next processing depends on the result of tag check.
• Requested instruction data existing in cache (Hit): Data is transferred from the cache into the CPU
within the cycle.
• Requested instruction data not existing in cache (Miss): The CPU and cache simultaneously acquire
data obtained by external access.
Bits 7 to 4: Sub-block Valid (SBV3 to SBV0)
If sub-block valid (SBV3 to SBV1) is set to "1", the current instruction data of the address indicated by
the tag in the corresponding sub-block is entered. In the sub-block, two instructions are normally stored
(excluding immediate transfer instructions).
31
CHAPTER 3 CPU
Bit 3: Tag Valid (TAGV)
This bit indicates whether the address tag value is valid. When the bit is 0, this block is invalid (at
flashing), irrespective of the Sub-block Valid bit.
Bit 1: LRU (Way 1 only)
This bit exists in the instruction cache tag of way 1 only.
As to a selected set, this bit indicates whether the last cache-miss entry is on way 1 or 2.
The last cache-miss entry of the set is on way 1 when the bit value is 1 or on way 2 when the bit value is
0.
Bit 0: Entry Lock (ETLK)
All entries in the block corresponding to the tag are locked in cache.
When the bit value is 1, the entries are locked and updated at a cache miss.
However, an invalid sub-block is updated.
If a cache miss occurs when all entries are locked both on ways 1 and 2, external memory is accessed
after one cycle is spent on cache miss judgment.
32
CHAPTER 3 CPU
3.3.1
Instruction Cache Control Register (ICHCR)
The instruction cache control register (ICHCR) controls the instruction cache operation,
Writing this register does not affect the caching of an instruction fetched within three
cycles.
■ Instruction Cache Control Register (ICHCR)
The instruction cache control register (ICHCR) is shared between ways 1 and 2.
Figure 3.3-3 Instruction Cache Control Register (ICHCR)
Address: 0000 03E7H
07
06
-
-
05
04
03
02
01
00
Initial value
GBLK ALFL EOLK ELKR FLSH ENAB --000000B
Access
R/W
Global lock
Auto lock fail
Entry auto lock
Entry unlock
Flash
Enable
Bit 5: Global Lock (GBLK)
All the current entries are locked in cache.
When the bit value is 1, valid entries in cache are not updated at a cache miss.
However, an invalid sub-block is updated. The instruction data fetch operation is the same as when the
current entries are not locked.
Even when the global lock is on, one cycle is spent for a penalty at a cache miss.
Bit 4: Auto Lock Fail (ALFL)
A lock attempt on entries already locked sets this bit to 1.
If entry update is attempted on entries already locked in the entry auto lock status, new entries are not
locked in cache as intended by the user. This bit is referenced for debugging this kind of program.
Writing 0 clears this bit.
Bit 3: Entry Auto Lock (EOLK)
This bit enables or disables auto locking for each entry in the instruction cache.
If entry access ends in a miss when this bit is 1, the entry lock bit in the cache tag is set to 1 by hardware
to lock the entry. The entry once locked will not be updated even in the case of a cache miss.
However, an invalid sub-block is updated. For secure locking, set this bit after flashing.
Bit 2: Entry Unlock (ELKR)
This bit clears the Entry Lock bit in all cache tags. When this bit is set to 1, the Entry Lock bit is cleared
to 0 in all cache tags at the next cycle. However, the contents of this bit are held for one clock cycle only.
For the second or later clock cycle, this bit is cleared.
33
CHAPTER 3 CPU
Note:
Do not release the entry lock (ELKR = 1) when the instruction cache is enabled (ENAB = 1).
Bit 1: Flash (FLSH)
This bit specifies flashing of the instruction cache.
When the bit value is 1, the cache contents are flashed. However, the contents of this bit are held for one
clock cycle only. For the second or subsequent clock cycle, this bit is cleared.
Note:
Do not flash the instruction cache (FLSH = 1) when the instruction cache is enabled (ENAB = 1).
Bit 0: Enable (ENAB)
This bit enables or disables the instruction cache.
When the bit value is 0, the instruction cache is disabled. In this status, instruction access from the CPU
does not go through the cache but goes out directly and the cache contents are held.
34
CHAPTER 3 CPU
3.3.2
Status in Each Operation Mode
This section explains the cache status and entry update in each operation mode.
■ Cache Status in Each Operation Mode
"Disabled" and "Flash" indicate the status only when the bit status is changed by a bit operation instruction.
Table 3.3-1 Cache Status in Each Operation Mode
Immediately
after reset
Tag
Control
register
Disabled
Flash
Cache memory
Contents not
defined
Previous status held
Rewriting not permitted
Previous status held
Address tag
Contents not
defined
Previous status held
Rewriting not permitted
Previous status held
Sub-block Valid bit
Contents not
defined
Previous status held
Rewriting not permitted
Previous status held
LRU
Contents not
defined
Previous status held
Rewriting not permitted
Previous status held
Entry Lock bit
Contents not
defined
Previous status held
Rewriting not permitted
Previous status held
(Entry unlock necessary)
Tag Valid bit
Contents not
defined
Previous status held
Flashing permitted
All entries invalid
Global Lock
Unlocked
Previous status held
Rewriting not permitted
Previous status held
Auto Lock Fail
No failure
Previous status held
Rewriting not permitted
Previous status held
Entry Auto Lock
Unlocked
Previous status held
Rewriting not permitted
Previous status held
Entry Unlock
Not unlocked
Previous status held
Rewriting not permitted
Previous status held
Enable
Disabled
Disabled
Previous status held
No flashing
Previous status held
Rewriting not permitted
Flashing at cycle
immediately after
memory access
(Returning to 0)
Flash
35
CHAPTER 3 CPU
■ Cache Entry Update
Cache entries are updated as explained in Table 3.3-2.
Table 3.3-2 Cache Entry Update
Unlock
36
Lock
Hit
No update
No update
Miss
The memory contents are loaded and the
cache entries are updated.
The entries are not updated in the case of a
tag error.
The entries are updated when the subblock is invalid.
CHAPTER 3 CPU
3.3.3
Instruction Cache Setting Method
This section explains how to set the MB91121 instruction cache for use.
■ Instruction Cache Setting Method
● Initializing
When starting to use the instruction cache, clear the cache contents first.
Set the FLSH and ELKR bits of the register to 1 to erase the past data.
ldi #0x000003e7,r0
// Address of the instruction
// cache control register
ldi #0B00000110,r1
// FLSH bit (Bit 1)
// ELKR bit (Bit 2)/
stb r1,@r0
// Register write
This initializes the cache.
Be sure to disable the cache when clearing its contents after use starts.
ldi #0x000003e7,r0
// Address of instruction
ldi #0B00000000,r1
// Disable cache
stb r1,@r0
// Write to register
ldi #0B00000010,r1
// FLSH bit (1 bit)
stb r1,@r0
// Write to register
// cache control register
● Enabling the cache (ON)
Set the ENAB bit to 1 to enable the instruction cache.
ldi #0x000003e7,r0
// Address of the instruction
// cache control register
ldi #0B00000001,r1
// ENAB bit (Bit 0)
stb r1,@r0
// Register write
The subsequent accesses will be taken into cache.
The cache can be enabled simultaneously when initialized.
ldi #0x000003e7,r0
// Address of the instruction
ldi #0B00000111,r1
// ENAB bit (Bit 0)
// cache control register
// FLSH bit (Bit 1)
// ELKR bit (Bit 2)
stb r1,@r0
// Register write
37
CHAPTER 3 CPU
● Disabling the cache (OFF)
Set the ENAB bit to 0 to disable the instruction cache.
To maintain address consistency between the instruction cache and CPU when the cache is disabled (OFF),
execute NOP, RET, and JMP to synchronize timing after a reset as shown in the sample program below.
• Disabling in a subroutine
ldi #0x000003e7,r0
// Address of instruction
// cache control register
ldi #0B00000000,r1
// Set ENAB bit to 0
stb r1,@r0
// Write to register
nop
// Execute nop three times for
// timing synchronization
nop
//
nop
//
ret
// Execute ret three times for
// timing synchronization
ret
//
ret
//
• Disabling in the middle of a program
ldi #chche_off,r2
// Specification of jump-to destination
// after cache-off
ldi #0x000003e7,r0
// Address of instruction
// cache control register
ldi #0B00000000,r1
// Set ENAB bit to 0
stb r1,@r0
// Write to register
nop
// Execute nop three times for
// timing synchronization
nop
//
nop
//
jmp @r2
// Execute jmp three times for
// timing synchronization
jmp @r2
//
jmp @r2
//
chche_off:
// Label
In this status (same as after a reset), the cache does nothing as though it did not exist. If a cache overhead is
anticipated, it is recommended that you disable the cache.
38
CHAPTER 3 CPU
● Locking all the cache contents
Lock the cache contents so that the instructions in the instruction cache will not be removed.
Set the GBLK bit in the register to 1. If the ENAB bit is not set to 1 together, the cache will be turned off
and the instructions locked in cache will not be available.
ldi #0x000003e7,r0
// Address of the instruction
// cache control register
ldi #0B00100001,r1
// ENAB bit (Bit 0)
stb r1,@r0
// Register write
// GBLK bit (Bit 5)
● Locking specific instructions in cache
To lock a specific group of instructions (such as a subroutine) in cache, set the EOLK bit to 1 before
executing the instructions.
The locked instructions are accessed as if existing in high-speed internal ROM.
ldi #0x000003e7,r0
// Address of the instruction
ldi #0B00001001,r1
// ENAB bit (Bit 0)
// cache control register
// EOLK bit (Bit 3)
stb r1,@r
// Register write
Although dependent on the number of memory waits, this setting becomes valid from the next instruction
after the stb instruction.
At the end of the instruction group to be locked, set the EOLK bit to 0.
ldi #0x000003e7,r0
// Address of the instruction
// cache control register
ldi #0B00000001,r1
// ENAB bit (Bit 0)
// EOLK bit (Bit 3)
stb r1,@r0
// Register write
● Unlocking the cache
Release the lock information of the instructions locked above.
ldi #0x000003e7,r0
// Address of the instruction
// cache control register
ldi #0B00000101,r1
// ENAB bit (Bit 0)
stb r1,@r0
// Register write
// ELKR bit (Bit 2)
Since only the lock information is released, the locked instructions are sequentially replaced with new
instructions depending on the LRU bit status.
39
CHAPTER 3 CPU
3.4
Dedicated Registers
The dedicated registers in the CPU are a program counter (PC), a program status
register (PS), a table base register (TBR), a return pointer (RP), a system stack pointer
(SSP), a user stack pointer (USP), and a multiplication/division result register (MDH/
MDL).
■ Dedicated Registers
Figure 3.4-1 shows the dedicated registers.
Figure 3.4-1 Dedicated Registers
32 bits
Program counter
PC
Program status
PS
Table base register
TBR
[Initial value]
XXXX XXXXH (Not defined)
000F FC00H
Return pointer
RP
XXXX XXXXH (Not defined)
System stack pointer
SSP
User stack pointer
USP
XXXX XXXXH (Not defined)
Multiplication/division
result register
MDH
XXXX XXXXH (Not defined)
MDL
XXXX XXXXH (Not defined)
0000 0000H
● Program counter (PC)
This counter indicates the address of the current instruction.
Bit 0 is set to 0 when the PC value is updated after the execution of an instruction. Bit 0 may become 1
only when an odd address is specified as the branch-to address. Even in this case, however, bit 0 is invalid
and the instruction should be placed at an address that is a multiple of 2.
The initial value after reset is not defined.
40
CHAPTER 3 CPU
● Program status (PS)
This register for holding a program status consists of CCR, SCR, and ILM. For details, see Section "3.4.1
Program Status Register (PS)".
All the undefined bits are reserved and their read values are always 0.
This register cannot be written.
● Table base register (TBR)
This register holds the first address of a vector table used for EIT processing.
The initial value after reset is 000FFC00H.
● Return pointer (RP)
This register holds an address returned from a subroutine.
When a CALL instruction is executed, the PC value is transferred to this register.
When a RET instruction is executed, the RP contents are transferred to PC.
The initial value after reset is not defined.
● System stack pointer (SSP)
SSP functions as R15 when the S flag is 0.
This pointer can be specified explicitly.
This pointer is also used as a stack pointer to specify a stack which saves PS and PC in the case of EIT.
The initial value after reset is 00000000H.
● User stack pointer (USP)
USP functions as R15 when the S flag is 1.
This pointer can be specified explicitly.
The initial value after reset is not defined.
This pointer cannot be used in an RETI instruction.
● Multiplication/division result storage register (MDH/MDL)
This register for storing the results of a multiplication or division is 32 bits long.
The initial value after reset is not defined.
[Multiplication]
The 64-bit result of "32 bits × 32 bits" is stored in the multiplication/division result storage register as
follows:
• MDH: Upper 32 bits
• MDL: Lower 32 bits
The 32-bit result of "16 bits × 16 bits" is stored as follows:
• MDH: Not defined
• MDL: 32 bits (result)
41
CHAPTER 3 CPU
[Division]
At the start of calculation, the dividend is stored in MDL.
If a DIV0S/DIV0U, DIV1, DIV2, DIV3, or DIV4S instruction is executed for a division, the calculation
results are stored in MDL and MDH as follows:
• MDH: Remainder
• MDL: Quotient
42
CHAPTER 3 CPU
3.4.1
Program Status Register (PS)
This register for holding a program status consists of ILM, SCR, and CCR.
All the undefined bits are reserved and their read values are always 0.
This register cannot be written.
■ Program Status Register (PS)
The program status register (PS) has the following configuration:
31
20
16
10
ILM
8 7
0
SCR
CCR
● Condition code register (CCR)
7
6
5
4
3
2
1
0
[Initial value]
-
-
S
I
N
Z
V
C
--00XXXXB
Bit 5: Stack flag
This flag specifies a stack pointer used as R15.
Value
Contents
0
Specify SSP as R15.
If EIT occurs, this value is automatically cleared to 0.
(The value before clearance is saved to the stack.)
1
Specify USP as R15.
Reset clears this bit to 0.
When executing an RETI instruction, set this bit to 0.
Bit 4: Interrupt enable flag
This flag enables or disables a user interrupt request.
Value
Contents
0
Disable a user interrupt.
When an INT instruction is executed, this value is cleared to 0.
(The value before clearance is saved to the stack.)
1
Enable a user interrupt.
Masking of a user interrupt request is controlled depending on the value held in ILM.
Reset clears this bit to 0.
43
CHAPTER 3 CPU
Bit 3: Negative flag
This flag indicates a sign when an operation result is regarded as an integer represented by a 2’s
complement.
Value
Contents
0
Operation result: Positive
1
Operation result: Negative
The initial value after reset is not defined.
Bit 2: Zero flag
This flag indicates whether an operation result is "0".
Value
Contents
0
Operation result: Other than "0"
1
Operation result: "0"
The initial value after reset is not defined.
Bit 1: Overflow flag
This flag indicates whether an operation ended in an overflow when the operand used for the operation is
regarded as an integer represented by a 2’s complement.
Value
Contents
0
Operation result: No overflow
1
Operation result: Overflow
The initial value after reset is not defined.
Bit 0: Carry flag
This flag indicates whether an operation ended in carry or borrow from the top bit.
Value
Contents
0
No carry or borrow
1
Carry or borrow
The initial value after reset is not defined.
● System condition code register (SCR)
The system condition code register (SCR) configuration is as follows:
44
10
9
8
[Initial value]
D1
D0
T
XX0B
CHAPTER 3 CPU
Bits 10 and 9: D1, D0: Step division flag
This flag holds intermediate data during step division processing.
Do not change the data during step division processing.
When executing another processing during step division processing, first save or restore the PS register
value to ensure the restart of step division processing.
The initial value after reset is not defined.
When a DIV0S instruction is executed, this flag is set by referencing the dividend and divider.
When a DIV0U instruction is executed, this flag is cleared forcibly.
Bit 8: T: Step trace trap flag
This flag enables or disables the step trace trap function.
Value
Contents
0
Disable the step trace trap function.
1
Enable the step trace trap function.
All the user NMIs and user interrupts are prohibited.
Reset clears this bit to 0.
The emulator uses the step trace trap function. When the emulator is used, the step trace trap function is
not available in a use program.
● Interrupt level mask register (ILM)
The interrupt level mask register (ILM) configuration is as follows:
20
19
18
17
16
[Initial value]
ILM4
ILM3
ILM2
ILM1
ILM0
01111B
This register holds an interrupt level mask value. The register value is used for level masking.
An interrupt request to the CPU is accepted only when its interrupt level is higher than the level indicated
in the register.
The highest level is 0 (00000B) and the lowest level is 31 (11111B)
The program setting range is limited. When the original value is from 16 to 31, a new value from 16 to 31
can be set. If an instruction setting 0 to 15 is executed, (specified value + 16) is transferred. When the
original value is from 0 to 15, a new value from 0 to 31 can be set.
Reset initialized this bit to 15 (01111B).
45
CHAPTER 3 CPU
3.5
General-purpose Registers
R0 to R15 are general-purpose registers. These registers are used as operation
accumulators and memory access pointers.
■ General-purpose Registers
Figure 3.5-1 shows the general-purpose registers.
Figure 3.5-1 General-purpose Registers
32 bits
R0
[Initial value]
XXXXXXXXH
R1
R12
R13
AC
R14
FP
XXXXXXXXH
R15
SP
0000 0000H
Of the 16 registers, the following registers are intended for special use and have partially strengthened
instructions for specific purposes:
• R13: Virtual accumulator
• R14: Frame pointer
• R15: Stack pointer
The initial values after reset are not defined for R0 to R14 but 00000000H (SSP value) for R15.
46
CHAPTER 3 CPU
3.6
Data Structure
The data placement of the FR family is as follows:
• Bit ordering: Little endian
• Byte ordering: Big endian
■ Bit Ordering
The FR family uses the little endian format for bit ordering.
Figure 3.6-1 shows the data placement for bit ordering.
Figure 3.6-1 Data Placement for Bit Ordering
bit
31
29
30
27
28
25
26
23
24
21
22
19
20
17
18
15
16
13
14
11
12
9
10
7
8
5
6
3
1
4
2
MSB
0
LSB
■ Byte Ordering
The FR family uses the big endian format for byte ordering.
Figure 3.6-2 shows the data placement for byte ordering.
Figure 3.6-2 Data Placement for Byte Ordering
MSB
Memory
LSB
bit31
23
10101010
bit
7
11001100
15
11111111
7
0
00010001
0
Address n
10101010
Address n + 1
11001100
Address n + 2
11111111
Address n + 3
00010001
47
CHAPTER 3 CPU
3.7
Word Alignment
Since an instruction or data is accessed in bytes, the placement address is dependent
on the instruction length or data width.
■ Program Access
An FR family program should be placed at an address of 2’s multiple.
Bit 0 of the program counter (PC) is set to 0 when the PC bit is updated after the execution of an
instruction.
The bit value may be 1 only if an odd address is specified as the branch destination.
Even in this case, however, bit 0 is invalid and the instruction should be placed at an address of 2’s
multiple.
There is no odd address exception.
■ Data Access
When making data access, the FR family applies forced alignment to the address depending on the access
width.
• Word access: 4’s multiple for address (The lowest two bits are forcibly cleared to 00.)
• Half-word access: 2’s multiple for address (The lowest bit is forcibly cleared to 0.)
• Byte access:
For word or half-word data access, some bits are forcibly cleared to 0 on the calculation result of an
effective address. In @ (R13, Ri) addressing mode, for example, the register before addition is used for
calculation as is (even when the lowest bit is 1) and the lower bits of the addition result are masked. The
pre-calculation register is not masked directly.
[Example] LD @(R13,R2),R0
R13
00002222H
R2
00000003H
+)
Addition result
00002225H
Lower two bits
forcibly masked
Address pin
48
00002224H
CHAPTER 3 CPU
3.8
Memory Mapping
This section explains the memory mapping of MB91121 and the common memory
mapping of the FR family.
■ Memory Mapping of MB91121
The address space is a 32-bit linear.
Figure 3.8-1 shows the memory mapping of MB91121.
Figure 3.8-1 Memory Mapping of MB91121
0000
0000H
0000
0100H
Byte data
Direct addressing area
Half-word data
0000
0200H
0000
0400H
000F
FC00H
Word data
Vector table
initial area
000F
FFFFH
FFFF FFFFH
● Direct addressing area
The following area in the address space is used for input and output. An operand address can be specified
directly in an instruction by direct addressing. Depending on the data length, the direct addressing area
differs as follows:
• Byte data (8 bits): 000H to 0FFH
• Half-word data (16 bits): 000H to 1FFH
• Word data (32 bits): 000H to 3FFH
● Vector table initial area
The initial area of the EIT vector table is from 000FFC00H to 000FFFFFH.
The vector table used for EIT addressing can be shifted to an arbitrary address by changing the TBR.
However, reset places the table in this area.
49
CHAPTER 3 CPU
■ Common Memory Mapping of the FR Family
For the FR family, the memory mapping is prescribed as follows. This mapping is common regardless of
the model (excepting the single-chip mode). Figure 3.8-2 shows the common memory mapping of the FR
family.
Figure 3.8-2 Common Memory Mapping of the FR Family
00000000H
00000010H
Direct addressing area
Byte I/O
00000100H
HalfWord I/O
00000200H
Word I/O
00000400H
Other I/O
00000800H
Non-access area
00001000H
(60)KB
Internal RAM or
non-access area
00010000H
External area
000C0000H
(256)KB
Internal ROM or
external area
1KB
Initial vector area
00100000H
External area
FFFFFFFFH
Note:
In the single-chip mode, the external area cannot be accessed.
50
CHAPTER 3 CPU
3.9
Outline of Instructions
The FR family supports the general RISC instruction set and also a set of logical
operation instructions, bit operation instructions, and direct addressing instructions
optimized for built-in uses. Since each instruction is 16 bits long (some are 32 or 48 bits
long), excellent memory efficiency is maintained. For details on the instructions, see
"APPENDIX E Instruction List".
The instruction set can be divided into the following function groups:
• Arithmetic operation
• Load and store
• Branch
• Logical operation and bit operation
• Direct addressing
• Other
■ Outline of Instructions
● Arithmetic operation
The standard arithmetic operation instructions (addition, deduction, and comparison) and shift instructions
(logical shift and arithmetic operation shift) belong to this group. For addition and deduction, an operation
function with carry is available for a multi-word operation instruction and an operation function not
changing the flag value is useful for an address calculation.
This group also includes multiplication instructions (32 bits × 32 bits, 16 bits × 16 bits) and a step division
instruction (32 bits / 32 bits).
A immediate value transfer function for setting an immediate value in a register and an inter-register
transfer function are also provided.
All the arithmetic operation instructions are executed using the general-purpose and multiplication/division
registers in the CPU.
● Load and store
The load and store instructions are to read and write external memory. These instructions are also used to
read or write a peripheral circuit (I/O) in the chip. These instructions make byte access, half-word access, or
word access. In addition to general indirect register memory addressing, indirect register addressing with
displacement or with register increment/decrement are also available for some instructions.
● Branch
The branch, call, interrupt, and return instructions belong to this group. The branch instruction may or may
not have a delay slot for optimum application according to the use.
For details on the branch instruction, see Section "3.9.1 Branch Instruction with Delay Slot" and "3.9.2
Branch Instruction with No Delay Slot".
51
CHAPTER 3 CPU
● Logical operation and bit operation
The logical operation instructions are used to calculate AND, OR, and EOR between general-purpose
registers and memory (and I/O). The bit operation instructions are used to edit the memory (and I/O)
contents directly. The memory addressing type is general indirect register addressing.
● Direct addressing
The direct address instructions are used for access between an I/O resource and a general-purpose register
and between an I/O resource and memory. Not indirect register setting but direct specification in an
instruction ensures high-speed efficiency access. Some instructions allow memory addressing by indirect
register setting with increment/decrement.
● Other
The other instructions are used for flag setting in the PS register, stack operation, and sign/zero expansion.
Function entry/exit and register multi-load/store instructions for a high-grade language are also provided.
52
CHAPTER 3 CPU
3.9.1
Branch Instruction with Delay Slot
A branch instruction with a delay slot branches control after executing the subsequent
instruction (delay slot).
■ Branch Instruction with Delay Slot
The following instructions branch control with delay slots:
JMP:D
@Ri
CALL:D
label12
CALL:D
@Ri
RET:D
BRA:D
label9
BNO:D
label9
BEQ:D
label9
BNE:D
label9
BC:D
label9
BNC:D
label9
BN:D
label9
BP:D
label9
BV:D
label9
BNV:D
label9
BLT:D
label9
BGE:D
label9
BLE:D
label9
BGT:D
label9
BLS:D
label9
BHI:D
label9
■ Operation of Branch Instruction with Delay Slot
A branch instruction with a delay slot branches control after executing the subsequent instruction (delay
slot). Since the delay-slot instruction is executed before branching, the apparent execution speed becomes
one cycle. If an effective instruction cannot be entered into the delay slot, an NOP instruction must be
placed.
[Example]
;
Instruction listing
ADD
R1, R2
;
BRA:D
LABEL
; Branch instruction
MOV
R2, R3
; Delay slot ......
Executed before branching
.
LABEL : ST
R3, @R4
; Branch destination
A conditional branch instruction executes the instruction at the delay slot whether or not the branch
conditions are satisfied.
In a delayed branch instruction, the execution order of some instructions seems to be reversed.
However, the instructions are executed in reverse order only when the PC is updated but in the described
order in other operations (register update and referencing).
Examples are shown below.
● Ri referenced by the JMP:D @Ri or CALL:D @Ri instruction is not affected even when updated by the
instruction in the delay slot.
[Example]
LDI:32
#Label,R0
JMP:D
@R0
; Branching to Label
LDI:8
#0,R0
; Not affecting the branch-to address
.
53
CHAPTER 3 CPU
● RP referenced by the RET:D instruction is not affected even when updated by an instruction in the
delay slot.
[Example]
RET:D
; Branching to the address indicated by
; the preset RP
MOV
R8,RP
; Not affecting the return operation
.
● The flag referenced by the Bcc:D rel instruction is not affected by the instruction in the delay slot.
[Example]
ADD
#1,R0
; Changing the flag
BC:D
Overflow
; Branching control according to the results
ANDCCR
#0
; of the above instruction
; Flag update not referenced by the above
; branch instruction
.
● If RP is referenced by the instruction in the delay slot of the CALL:D instruction, the contents updated
by the CALL:D instruction are read.
[Example]
CALL:D
Label
; Branching by updating RP
MOV
RP,R0
; Transferring RP produced by the execution
; of the above CALL:D
.
■ Limitations on the Operation of Branch Instruction with Delay Slot
● Instruction acceptable in delay slot
Only an instruction satisfying the following conditions can be placed in a delay slot:
• One-cycle instruction
• No branch instruction
• Instruction not affecting operation even when the order is changed
"One-cycle instruction" is marked "1", "a", "b", "c", or "d", in the number of cycles column of the
instruction list.
● Step trace trap
No step trace trap occurs between the execution of the branch instruction with a delay slot and that of the
instruction in the delay slot.
● Interrupt/NMI
No interrupt/NMI is received between the execution of the branch instruction with a delay slot and that of
the instruction in the delay slot.
54
CHAPTER 3 CPU
● Undefined instruction exception
If there is an undefined instruction in a delay slot, no undefined instruction exception occurs.
The undefined instruction then operates as an NOP instruction.
55
CHAPTER 3 CPU
3.9.2
Branch Instruction with No Delay Slot
A branch instruction with no delay slot executes instructions in the order of instruction
listing.
■ Branch Instruction with No Delay Slot
The following instructions branch control with no delay slots:
JMP
@Ri
CALL
label12
CALL
@Ri
RET
BRA
label9
BNO
label9
BEQ
label9
BNE
label9
BC
label9
BNC
label9
BN
label9
BP
label9
BV
label9
BNV
label9
BLT
label9
BGE
label9
BLE
label9
BGT
label9
BLS
label9
BHI
label9
■ Operation of Branch Instruction with No Delay Slot
A branch instruction with no delay slot executes instructions in the order of listing branches. The
instruction at the next position will not be executed before branching.
[Example]
;
Instruction listing
ADD
R1,R2
;
BRA
LABEL
; Branch instruction (with no delay slot)
MOV
R2,R3
; Not executed
R3,@R4
; Branch destination
.
LABEL
ST
The number of execution cycles for a branch instruction with no delay slot is 2 for branching and 1 for no
branching.
Since an appropriate instruction cannot be entered into the delay slot, the instruction code efficiency can be
raised higher than a conditional branch instruction with a delay slot stating
NOP.
To realize both high execution speed and high code efficiency, select an instruction with a delay slot when
an effective slot can be entered into the slot or an instruction with no delay slot when it cannot be entered
into the slot.
56
CHAPTER 3 CPU
3.10
Exception, Interrupt, and Trap (EIT)
EIT representing Exception, Interrupt, and Trap means to suspend the current program
and execute another program in the case of an event.
Exception is an event related to a context now being executed. Processing is executed
again from the instruction where the exception occurred.
Interrupt is an event not related to a context now being executed. This event is caused
by hardware.
Trap is an event related to a context now being executed. This event may be specified in
a program like a system call. Processing is executed again from the next instruction.
■ Features of EIT
• Multi-interrupt
• Level masking function (15 level available to the user)
• Trap instruction (INT)
• Emulator activation EIT (hardware or software)
■ EIT Sources
The EIT sources are as follows:
• Reset
• User interrupt (internal resource or external interrupt)
• NMI
• Delayed interrupt
• Undefined instruction exception
• Trap instruction (INT)
• Trap instruction (INTE)
• Step trace trap
• Coprocessor absence trap
• Coprocessor error trap
■ Return from EIT
The following instruction is used for return from EIT:
RETI instruction
■ Notes on EIT
● Delay slot
The delay slot of a branch instruction has some instructions on EIT. For details, see Section "3.9 Outline of
Instructions".
57
CHAPTER 3 CPU
3.10.1
EIT Interrupt Level
The EIT interrupt level is from 0 to 31 and managed by five bits.
■ Interrupt Level
Table 3.10-1 lists the interrupt levels.
Table 3.10-1 Interrupt Levels
Level Source
Source
Binary
Decimal
00000
.
.
00011
0
.
.
3
00100
4
00101
.
.
01110
5
.
.
14
(Reserved for system)
.
.
(Reserved for system)
01111
15
NMI (for user)
10000
10001
.
.
11110
11111
16
17
.
.
30
31
Interrupt
Interrupt
.
.
Interrupt
Remarks
}
(Reserved for system)
.
.
(Reserved for system)
INTE instruction
Step trace trap
When the original ILM value is
from 16 to 31, a value in this range
cannot be set in a program using
the ILM.
No user interrupt when ILM is set
No interrupt when ICR is set
}
Levels 16 to 31 can be operated.
The interrupt level does not affect the undefined instruction exception, coprocessor absence trap,
coprocessor error trap, or INT instruction or change the ILM value.
■ I Flag
This flag enables or disables an interrupt. CCR bit 4 of the PS register is used for this flag.
Value
58
Contents
0
Disable an interrupt.
When an INT instruction is executed, this value is cleared to 0.
(The value before clearance is saved to the stack.)
1
Enable an interrupt.
Masking of an interrupt request is controlled depending on the value held in ILM.
CHAPTER 3 CPU
■ Interrupt Level Mask Register (ILM)
This PS register (bits 20 to 16) holds an interrupt level mask value.
An interrupt request to the CPU is accepted only when its interrupt level is higher than the level indicated
in this ILM register.
The highest level is 0 (00000B) and the lowest level is 31 (11111B).
The program setting range is limited. When the original value is from 16 to 31, a new value from 16 to 31
can be set. If an instruction setting 0 to 15 is executed, (specified value + 16) is transferred. When the
original value is from 0 to 15, a new value from 0 to 31 can be set.
Note:
The STLIM instruction is used for this setting.
■ Interrupt/NMI Level Masking
If a NMI or interrupt request occurs, the interrupt level of the interrupt source (see Table 3.10-1) is
compared with the level mask value in the ILM. The request is masked and not received when the
following condition is satisfied:
Interrupt level of the source greater than or equal to Level mask value
59
CHAPTER 3 CPU
3.10.2
Interrupt Control Register (ICR)
The interrupt control register in the interrupt controller is set a level for each interrupt
request. This register is prepared for each interrupt request input. This register is
mapped in the I/O space and accessed from the CPU through a bus.
■ Interrupt Control Register (ICR)
The interrupt control register (ICR) has the following configuration:
ICR00 to ICR47
7
6
5
4
3
2
1
0
-
-
-
ICR4
ICR3
ICR2
ICR1
ICR0
R
R/W
R/W
R/W
R/W
Initial value ---11111B
Bit 4: ICR4
This bit value is always 1.
Bits 3 to 0: ICR3 to ICR0
These are the lower four bits indicating the interrupt level of the corresponding interrupt source.
These bits can be read and written.
With bit 4, a value from 16 to 31 can be set in this register.
■ Mapping of the Interrupt Control Register (ICR)
Table 3.10-2 lists the interrupt sources and vectors.
Table 3.10-2 Interrupt Sources and Vectors
Interrupt control register
Interrupt
source
Corresponding interrupt vector
Number
Number
Address
Address
Hex
Dec
IRQ00
ICR00
000400H
10H
16
TBR + 3BCH
IRQ01
ICR01
000401H
11H
17
TBR + 3B8H
IRQ02
ICR02
000402H
12H
18
TBR + 3B4H
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
IRQ45
ICR45
00042DH
3DH
61
TBR + 308H
IRQ46
ICR46
00042EH
3EH
62
TBR + 304H
IRQ47
ICR47
00042FH
3FH
63
TBR + 300H
For details, see "CHAPTER 11 INTERRUPT CONTROLLER".
60
CHAPTER 3 CPU
3.10.3
System Stack Pointer (SSP)
The system stack pointer (SSP) indicates a stack to save data into and restore from for
receipt of and recovery from EIT.
■ System Stack Pointer (SSP)
The system stack pointer (SSP) has the following register configuration:
bit
31...
SSP
...0
[Initial value]
00000000B
The pointer value is decremented by 8 at EIT processing and incremented by 8 at return from EIT by a
RETI instruction.
The initial value after reset is 00000000H.
61
CHAPTER 3 CPU
3.10.4
Interrupt Stack
The interrupt stack is an area indicated by the system stack pointer (SSP) to save and
restore PC and PS values. After an interrupt, the PC value is stored at the SSP address
and the PS value at the SSP+4 address.
■ Interrupt Stack
Figure 3.10-1 shows an example of interrupt stack.
Figure 3.10-1 Example of Interrupt Stack
[Before interrupt]
SSP
80000000H
[After interrupt]
SSP
Memory
62
7FFFFFF8H
Memory
80000000 H
80000000 H
7FFFFFFC H
7FFFFFFC H
PS
7FFFFFF8 H
7FFFFFF8 H
PC
CHAPTER 3 CPU
3.10.5
Table Base Register (TBR)
The table base register (TBR) indicates the first address of the vector table for EIT.
■ Table Base Register (TBR)
The table base register (TBR) has the following configuration:
bit
31...
TBR
...0
[Initial value]
000FFC00B
The offset value determined for each EIT source is added to the TBR value to determine the vector address.
The initial value after reset is 000FFC00H.
63
CHAPTER 3 CPU
3.10.6
EIT vector table
The EIT vector area is 1K-byte from the area indicated by the table base register (TBR).
■ EIT Vector Table
The area size per vector is 4 bytes and the relationship between vector number and vector address can be
expressed as follows:
vctadr = TBR + vctofs
= TBR + (3FCH - 4 × vct)
vctadr: Vector address
vctofs: Vector offset
vct: Vector number
The lower two bits of the addition result are always 00.
000FFC00H to 000FFFFFH is the initial area of the vector table after reset.
Special functions are assigned to some of the vectors.
Table 3.10-3 shows the vector table on the architecture.
Table 3.10-3 Vector Table (1 / 2)
Vector No.
Vector offset (Hex)
64
Explanation
Hex
Dec
3FC
00
0
Reset *1
3F8
01
1
Reserved for system
3F4
02
2
Reserved for system
3F0
03
3
Reserved for system
.
.
.
.
.
.
.
.
.
3E0
07
7
Reserved for system
3DC
08
8
Reserved for system
3D8
09
9
INTE instruction
3D4
0A
10
Reserved for system
3D0
0B
11
Reserved for system
3CC
0C
12
Step trace trap
3C8
0D
13
Reserved for system
3C4
0E
14
Undefined instruction exception
3C0
0F
15
NMI (for user)
.
.
.
CHAPTER 3 CPU
Table 3.10-3 Vector Table (2 / 2)
Vector No.
Vector offset (Hex)
Explanation
Hex
Dec
3BC
10
16
Maskable interrupt source #0
3B8
11
17
Maskable interrupt source #1 *2
.
.
.
.
.
.
.
.
.
300
3F
63
Maskable interrupt source/INT instruction
2FC
40
64
Reserved for system (used by REALOS)
2F8
41
65
Reserved for system (used by REALOS)
2F4
42
66
Maskable interrupt source/INT instruction
.
.
.
.
.
.
.
.
.
000
FF
255
.
.
.
.
.
.
INT instruction
*1: Even when the TBR value is changed, the reset vector is always fixed at address "000FFFFCH".
*2: For the vector table of this model, see "APPENDIX B Interrupt Vectors".
65
CHAPTER 3 CPU
3.10.7
Multi-EIT Processing
If several EIT sources occur simultaneously, the CPU selects and receives one EIT
source. After executing the EIT sequence, the CPU detects another EIT source. If there
is no more EIT source left, the CPU executes the handler instruction of the EIT source
received last.
Therefore, if several EIT sources occur simultaneously, the handler execution order of
the sources is determined by the following two sources:
• Priority of EIT source received
• Masking of other sources
■ Priority of EIT Source Received and Masking of Other Sources
The priority of an EIT source determines the execution order of the EIT sequence where the PS and PC
values are saved, the PC bit is updated (as required), and other sources are masked.
The handlers of sources are not always executed on a first-in first-out basis.
Table 3.10-4 lists the priorities of EIT sources and the masking levels of other sources.
Table 3.10-4 Priorities of EIT Sources and the Masking Levels of Other Sources
Priority
Source
Masking level
1
Reset
Discard other sources
2
Undefined instruction exception
Cancel
3
INT instruction
I flag = 0
4
User interrupt
ILM = Level of received source
5
User NMI
ILM = 15
6
INTE instruction
ILM = 4 *
7
Emulator NMI
ILM = 4
8
Step trace trap
ILM = 4
9
INTE instruction
ILM = 4
*: The priority level is 6 only when an INTE instruction and an emulator NMI are generated simultaneously.
(MB91121 uses an emulator NMI for a break by data access.)
Considering the mask processing on other sources after an EIT source is received, the handler execution
order of the EIT sources that occurred simultaneously will be as prescribed in Table 3.10-5.
66
CHAPTER 3 CPU
Table 3.10-5 EIT Handler Execution Order
Handler execution order
Source
1
Reset *1
2
Undefined instruction exception
3
Step trace trap
4
INT instruction *2
5
User NMI
6
INT instruction
7
User interrupt
*1: Other sources are discarded.
*2: If an INTE instruction is step-executed, only a step trace trap is generated as an EIT.
The source by INTE is ignored.
Figure 3.10-2 shows an example of multi-EIT processing.
Figure 3.10-2 Example of Multi-EIT Processing
Main routine
NMI handler
Priority
(High) Occurrence of NMI
(Low) Occurrence of
INT instruction
INT instruction
handler
Executed first
Executed next
67
CHAPTER 3 CPU
3.10.8
EIT Processing
This section explains the EIT processing.
In the explanation, "transfer-from PC" indicates the address of an instruction where
each EIT source was detected.
"Next instruction address" means that the EIT-detected instruction is as follows:
• LDI = 32: PC+6
• LDI = 20, COPOP, COPLD, COPST, or COPSV: PC+4
• Other instruction: PC+2
■ Processing of User Interrupt/NMI
If a user interrupt or user NMI interrupt request is issued, the acceptance of the request is determined in the
following order:
● Determining the acceptance of interrupt request
1. The interrupt levels of requests issued simultaneously are compared and the request of the highest level
(smallest value) is selected. The level of a maskable interrupt is compared with the value of the
corresponding ICR and that of a NMI is compared with a predetermined constant.
2. If several interrupt requests of the same level are issued, the interrupt request of the smallest interrupt
number is selected.
3. The interrupt level of the selected interrupt request is compared with the level mask value determined by
ILM.
• When the interrupt level is equal to or greater than the level mask value, the interrupt request is
masked and not accepted.
• When the interrupt level is smaller than the level mask value, go to 4.
4. If the selected interrupt request is maskable, the interrupt request is masked and not accepted when the I
flag is "0". When the I flag is "1", go to 5.
• If the selected interrupt request is NMI, go to 5 whether or not the I flag is "0".
5. When the above conditions are satisfied, the interrupt request is accepted at a break of interrupt
processing.
If a user interrupt/NMI request is received at the detection of an EIT request, the CPU effects the following
processing using the interrupt number corresponding to the accepted interrupt request.
( ) in [Processing] represents an address specified in the register.
[Processing]
SSP-4 → SSP
PS → (SSP)
SSP-4 → SSP
Instruction of next address → (SSP)
Interrupt level of accepted request → ILM
"O" → S flag
(TBR + Vector offset of received interrupt request) → PC
A new EIT is detected after the interrupt sequence and before the first instruction of the handler is
executed. If an acceptable EIT occurs in this period, the CPU changes to the EIT processing sequence.
68
CHAPTER 3 CPU
■ Processing of INT Instruction
The INT #u8 instruction processing is as shown below.
Control branches to the interrupt handler of the vector indicated by u8.
[Processing]
SSP-4 → SSP
PS → (SSP)
SSP-4 → SSP
PC+2 → (SSP)
"O" → I flag
"O" → S flag
(TBR + 3FCH-. 4 × u8) → PC
■ Processing of INTE Instruction
The INTE instruction processing is as shown below.
Control branches to the interrupt handler of the vector with vector No. #9.
[Processing]
SSP-4 → SSP
PS → (SSP)
SSP-4 → SSP
PC+2 → (SSP)
"00100" → ILM
"O" → S flag
(TBR + 3D8H) → PC
Do not use an INTE instruction in the processing routine of INTE instruction or step trace trap.
The INTE instruction does not generate an EIT during step execution.
■ Processing of Step Trace Trap
If the T flag is set at SCR in the PS register and the step trace function is enabled, a trap occurs at the
execution of every instruction to cause a break.
The step trace trap detection conditions are as follows:
• T flag = 1
• Not delayed branch condition
• During processing other than an INTE instruction or step trace trap
If the above conditions are satisfied, a break is inserted between the processing of instructions.
[Processing]
SSP-4 → SSP
PS → (SSP)
SSP-4 → SSP
Address of next instruction → (SSP)
"00100" → ILM
"O" → S flag
(TBR + 3CCH) → PC
If the T flag is set and the step trace trap function is enabled, the user NMI and user interrupt are disabled.
An INTE instruction no longer generates an EIT.
69
CHAPTER 3 CPU
■ Processing of Undefined Instruction Exception
If an instruction is found undefined at decoding, an undefined instruction exception occurs.
The undefined instruction exception detection conditions are as follows:
• Instruction found undefined at decoding
• Placed outside the delay slot (not immediately after the delayed branch instruction)
If the above conditions are satisfied, an undefined instruction exception occurs and breaks the processing.
[Processing]
SSP-4 → SSP
PS → (SSP)
SSP-4 → SSP
PC → (SSP)
"O" → S flag
(TBR + 3C4H) → PC
The address of the instruction where the undefined instruction exception was detected is saved in the PS
register.
■ Processing of RETI Instruction
The RETI instruction returns control from an EIT processing.
[Processing]
(R15) → PC
R15 + 4 → R15
(R15) → PS
R15 + 4 → R15
Note that the stack pointer to be referenced for returning the PS or PC register is selected according to the S
flag. When executing a instruction that operates R15 (stack pointer) in the interrupt handler, set the S flag
to 1 to use USP as R15 and the S flag to 0 before the RETI instruction.
70
CHAPTER 3 CPU
3.11
Reset Sequence
This section explains reset to set the CPU to the operation status.
■ Reset Sources
The reset sources are as follows:
• Input from an external reset pin
• Software reset using the SRST bit in the standby control register (STCR)
• Watchdog timer increment
• Power-on reset
■ Initialization by Reset
A reset source initializes the CPU.
● Release by external reset pin or software reset or from hardware standby
• Set a pin to a specified status.
• Reset each resource in the device. The control register is initialized to the predetermined value.
• The slowest gear is selected for the clock.
■ Reset Sequence
Once the reset source has been released, the CPU executes the following reset sequence:
• (000FFFFCH) → PC
Note:
After reset, set the operation mode in detail by setting the mode register.
For details, see the mode register in Section "3.14 Memory Access Modes".
71
CHAPTER 3 CPU
3.12
Clock
The clock generator is a module responsible for the following functions:
• CPU clock generator (including the gear function)
• Peripheral clock generator (including the gear function)
• Reset occurrence and source hold function
• Standby function (including hardware standby)
• DMA request suppression
• Built-in PLL (multiplier circuit)
■ Registers of the Clock Generator
Figure 3.12-1 shows the registers of the clock generator.
Figure 3.12-1 Registers of the Clock Generator
15
14
13
12
11
10
09
RSRR/WTCR
07
06
05
04
03
02
01
00
STCR
PDRR
GCR
08
CTBR
WPR
PCTR
Note:
For details of the standby control register (STCR), see Section "3.13 Low-power Consumption".
72
CHAPTER 3 CPU
■ Block Diagram of the Clock Generator
Figure 3.12-2 shows a block diagram of the clock generator.
Figure 3.12-2 Block Diagram of the Clock Generator
[Gear control section]
-
R
b
u
s
GCR register
CPU gear
CPU clock
Peripheral
gear
Oscillation
circuit
PLL
1/2
External bus clock
Peripheral DMA clock
DSP macro clock
Selection
circuit
X0
X1
Internal bus clock
Internal
clock
generator
PCTR register
Internal peripheral clock
[Stop/sleep control circuit]
Internal interrupt
Internal reset
STCR register
Stop status
Status
transition
control
circuit
CPU hold enable
Sleep status
CPU hold request
Reset
F/F
Internal reset
[DMA suppression circuit]
DMA request
PDRR register
[Reset source circuit]
Power-on cell
RSTX pin
RSRR register
[Watchdog control circuit]
WPR register
Watchdog F/F
CTBR register
Timebase timer
Count clock
73
CHAPTER 3 CPU
3.12.1
Reset Source Register (RSRR) and Watchdog Cycle
Control Register (WTCR)
The reset source register (RSRR) holds the type of reset that occurred and the
watchdog cycle control register (WTCR) specifies the watchdog timer cycle.
■ Reset Source Register (RSRR) and Watchdog Cycle Control Register (WTCR)
The reset source register (RSRR) and watchdog cycle control register (WTCR) have the following
configuration:
RSRR/WTCR
After power-on
15
000480H PONR
14
-
13
12
11
WDOG ERST SRST
10
9
8
Initial value
Access
-
WT1
WT0
1-XXX-00B
R/W
RSRR(R)
WTCR(W)
Bit 15: PONR
When the value is 1, this bit indicates that the reset type immediately before was power-on reset. If this
bit is 1, the contents of this register except this bit are invalid.
Bit 14: (Reserved)
This value is reserved. The read value is not defined.
Bit 13: WDOG
When the value is 1, this bit indicates that the reset type immediately before was watchdog reset.
Bit 12: ERST
When the value is 1, this bit indicates that the preceding reset type occurred because of the external reset
pin.
Bit 11: SRST
When the value is 1, this bit indicates that the preceding reset type occurred because of the software reset
request.
Bit 10: (Reserved)
This value is reserved. The read value is not defined.
Bits 9 and 8: WT1 and WT0
These bits are used to specify the watchdog cycle. Table 3.12-1 shows the correspondence between the
bit values and the specified cycles. Reset initializes these bits.
74
CHAPTER 3 CPU
Table 3.12-1 Watchdog Cycles Specified by WT1 and WT0
Minimum WPR write interval necessary
for suppressing watchdog reset
Time from final WPR write
(5AH) until watchdog reset
WT1
WT0
0
0
φ × 215 [Initial value]
φ × 215 to φ × 216
0
1
φ × 217
φ × 217 to φ × 218
1
0
φ × 219
φ × 219 to φ × 220
1
1
φ × 221
φ × 221 to φ × 222
WPR: Watchdog reset defer register
φ is twice the X0 value when the CHC bit in the GCR register is 1 and equal to the PLL oscillation
frequency when the CHC bit is 0.
75
CHAPTER 3 CPU
3.12.2
DMA Request Suppression Register (PDRR)
The DMA request suppression register (PDRR) suppresses the DMA request
temporarily and activates the CPU.
■ DMA Request Suppression Register (PDRR)
The DMA request suppression register (PDRR) has the following configuration:
PDRR
000482H
15
14
13
12
11
10
09
08
Initial value
Access
-
-
-
-
D3
D2
D1
D0
----0000B
R/W
Bits 11 to 08: D3 to D0
When a value other than "0" is written into this register, the DMA transfer request from DMA to the CPU
is suppressed thereafter. DMA transfer is suppressed unless the register is cleared to "0".
Note:
Be sure to use this register with HRCL of the interrupt controller.
76
CHAPTER 3 CPU
3.12.3
Timebase Timer Clear Register (CTBR)
The timebase timer clear register (CTBR) initializes the timebase timer to 0.
■ Timebase Timer Clear Register (CTBR)
The timebase timer clear register (CTBR) has the following configuration:
CTBR
000483H
07
06
05
04
03
02
01
00
Initial value
Access
D7
D6
D5
D4
D3
D2
D1
D0
XXXXXXXXB
W
Bits 07 to 00: D7 to D0
When A5H and 5AH are written into this register sequentially, the timebase timer is cleared to "0"
immediately after 5AH write. The read value of this register is not defined. There is no time limit between
A5H write and 5AH write.
Note:
When the timebase timer is cleared using this register, the oscillation stabilization wait time interval,
watchdog cycle, and peripheral cycles based on the timebase timer change temporarily.
77
CHAPTER 3 CPU
3.12.4
Gear Control Register (GCR)
The gear control register (GCR) controls the gear functions of the CPU/DSP and
peripheral clocks.
■ Gear Control Register (GCR)
The gear control register (GCR) has the following register configuration:
GCR
15
000484H
14
13
12
11
10
09
08
Initial value
Access
-
CHC
110011-1B
R/W
CCK1 CCK0 DBLAK DBLON PCK1 PCK0
Bits 15 and 14: CCK1 and CCK0
These bits are used to specify the gear cycles of CPU/DSP.
These bits are used to specify the CPU machine clock cycle. Table 3.12-2 shows the correspondence
between the bit values and the specified cycles.
Reset initializes these bits.
Table 3.12-2 CPU Machine Clock Cycles
CCK1
CCK0
CHC
CPU/DSP machine clock cycles
0
0
0
PLL × 1
0
1
0
PLL × 1/2
1
0
0
PLL × 1/4
1
1
0
PLL × 1/8
0
0
1
Oscillation × 1/2
0
1
1
Oscillation × 1/2 × 1/2
1
0
1
Oscillation × 1/2 × 1/4
1
1
1
Oscillation × 1/2 × 1/8 [Initial value]
PLL: PLL oscillation frequency
Oscillation: Input frequency from X0
Bit 13: DBLAK
This bit indicates the clock doubler operation status. This is a read-only bit and ignores write access. This
bit is initialized by reset.
Since the bus frequency is switched with a time lag, this bit is used to confirm that the bus frequency has
actually been switched.
DBLAK
78
Internal: External operating frequency
0
Operating at 1:1 [Initial value]
1
Operating at 2:1
CHAPTER 3 CPU
Bit 12: DBLON
This bit specifies the clock doubler operation status. This bit is initialized by reset.
DBLON
Internal: External operating frequency
0
Operation at 1:1 [Initial value]
1
Operation at 2:1
Bits 11 and 10: PCK1 and PCK0
These bits are used to specify the peripheral machine clock cycle. Table 3.12-3 shows the correspondence
between the bit values and the specified cycles. Reset initializes these bits.
Table 3.12-3 Peripheral Machine Clock Cycles
Peripheral machine clock
(Oscillation: Input frequency from X0)
PCK1
PCK0
CHC
0
0
0
PLL × 1
0
1
0
PLL × 1/2
1
0
0
PLL × 1/4
1
1
0
PLL × 1/8
0
0
1
Oscillation × 1/2
0
1
1
Oscillation × 1/2 × 1/2
1
0
1
Oscillation × 1/2 × 1/4
1
1
1
Oscillation × 1/2 × 1/8 [Initial value]
PLL: PLL oscillation frequency
Oscillation: Input frequency from X0
When the CPU/DSP clock frequencies are higher than 25 MHz, set the peripheral clock frequency to half
(or less) of the CPU/DSP clock frequencies.
The maximum peripheral clock frequency is 25 MHZ.
Note:
To change the CPU/DSP gear and peripheral gear simultaneously, set both bears to the same one,
and then set each gear to desired one.
The gears may be set to the same target gear in the following cases; if the CPU/DSP gear and
peripheral gear are the same, if only one of the gears is changed, or if both gears are set to the
same type of gear.
When the clock doubler is ON, direct setting to the target gear is permissible because the CPU and
DSP clocks are fixed regardless of the GCR value.
79
CHAPTER 3 CPU
[Example of program description]
ldi
#0x484,
r1
ldi
#0x0d,
r0
stb
r0,
@r1
ldi
#0x484,
r1
ldi
0xcd,
r0
stb
r0,
@r1
; CPU:1/1, pheripheral:1/8
:
; CPU:1/1, pheripheral:1/8 temporally set
; to the same ratio.
ldi
#0xc5,
r0
stb
r0,
@r1
; CPU:1/1, pheripheral:1/2 set to
; the desired ratio.
Bit 09: (Reserved)
Always write "1".
Bit 08: CHC
This bit is used to select the reference clock. Reset initializes this bit. When the VSTP bit in the PCTR
register is 1, this bit ignores 0 write.
CHC
Clock selection
1
Using the oscillation circuit output divided by two as the reference clock [Initial value]
0
Using the PLL oscillation output as the reference clock
Note:
If the system changes to Stop mode when the VSTP bit in the PCTR register is "0", the PLL stops
oscillation but the VSTP bit remains "0". When the system is returned from Stop mode by an external
interrupt, about 100 ms is necessary until the PLL oscillation becomes stable, on top of the
stabilization oscillation time set by the OSC1 and OSC0 bits in the STCR register. Therefore, do not
set "0" to this bit before this processing.
80
CHAPTER 3 CPU
3.12.5
Watchdog Reset Defer Register (WPR)
The watchdog reset defer register (WPR) clears the watchdog timer flip-flop. The
occurrence of watchdog reset can be deferred using this register.
■ Watchdog Reset Defer Register (WPR)
The watchdog reset defer register (WPR) has the following configuration:
WPR
000485H
07
06
05
04
03
02
01
00
Initial value
Access
D7
D6
D5
D4
D3
D2
D1
D0
XXXXXXXXB
W
Bits 07 to 00: D7 to D0
When A5H and 5AH are written into this register sequentially, the watchdog timer flip-flop is cleared to
"0" immediately after 5AH write to defer the occurrence of watchdog reset. The read value of this register
is not defined. There is no time limit between A5H write and 5AH write. Watchdog reset occurs if both
data is not written in the period specified in Table 3.12-4.
Table 3.12-4 Watchdog Cycles Specified by WT1 and WT0
Minimum WPR write interval
necessary for suppressing
watchdog reset
Time from final WPR write
(5AH) until watchdog reset
WT1
WT0
0
0
φ × 215
φ × 215 to φ × 216
0
1
φ × 217
φ × 217 to φ × 218
1
0
φ × 219
φ × 219 to φ × 220
1
1
φ × 221
φ × 221 to φ × 222
φ is twice the X0 value when the CHC bit in the GCR register is 1 and equal to the PLL oscillation
frequency when the CHC bit is 0.
81
CHAPTER 3 CPU
3.12.6
PLL Control Register (PCTR)
The PLL control register (PCTR) controls PLL oscillation.
The setting of this register can be changed when the CHC bit in the GCR register is "1".
■ PLL Control Register (PCTR)
The PLL control register (PCTR) has the following configuration:
PCTR
15
14
000488H SLCT1 SLCT0
13
12
11
10
09
08
Initial value
Access
-
-
VSTP
-
-
-
00--0---B
R/W
Bits 15 and 14: SLCT1 and SLCT0
These bits are used to control the PLL multiplication source. Only power-on initializes these bits.
These bits are set to the internal operating frequency when the CHC bit in the GCR register is set to "0".
SLCT1
SLCT0
Internal operating frequency (oscillation: 12.5 MHz)
0
0
12.5 MHz [Initial value]
0
1
25.0 MHz
1
X
50.0 MHz
Bits 13 and 12: (Reserved)
Always write "0".
Bit 11: VSTP
This bit is used to control PLL oscillation. Power-on reset or external reset initializes this bit.
To keep the PLL out of operation, stop the PLL after every reset.
VSTP
PLL operation
0
Oscillation [Initial value]
1
No oscillation
Note:
If the system changes to Stop, the PLL oscillation stops, irrespective of the bit setting.
82
CHAPTER 3 CPU
3.12.7
Watchdog Timer Function
The watchdog timer function is to detect overdrive programming by the time-base timer
output.
If A5H and 5AH are not written to the watchdog reset postpone register within the
prescribed time due to an overdrive programming and the like, the watchdog reset will
be requested through the watchdog timer function.
■ Block Diagram of the Watchdog Control Section
Figure 3.12-3 shows the block diagram of the watchdog control section.
Figure 3.12-3 Block Diagram of the Watchdog Control Section
Internal bus
WPR
A5&5A
RSRR
WDOG
clr
and
Select
Edge
sense
circuit
Watchdog
F/F
Status decoder
Timebase timer
divided output
Timebase timer
divided output
Reset status transition
request signal
Latch
Status transition control circuit
CTBR
WTx
Timebase timer
Reset
F/F
Internal reset
Reset status
■ Setting of the Watchdog Timer Function
The watchdog timer is operated by using time-base timer output. It starts operating by writing to the
watchdog timer control register (WTCR). Then, the interval time of watchdog timer will be set by WT1 and
WT0 bits. For the interval time setting, the value is valid only if set at the time of initial writing after the
complete reset, and the value set later than that is invalid.
Furthermore, be sure to initialize the watchdog timer by writing A5H and 5AH into watchdog reset
postpone register (WPR) before startup. Unless it's initialized, the watchdog reset may be requested after
startup due to the fluctuation of time-base timer cycle.
[Example]
LDI:20
LDI:8
LDI:32
LDI:8
STB
LDI:8
STB
STB
#WRP,R0
#10000000b,R1
#WTCR,R2
#0xA5,R3
R3,@R0
#0xA5,R3
R3,@R0
R1,@R2
; WT1, WT0=10
; Watchdog Timer start
83
CHAPTER 3 CPU
■ Reset Defer Method
Once the watchdog timer has been activated, it is necessary to write A5H and 5AH periodically into the
watchdog reset defer register (WPR) by a program. The watchdog records the occurrence of the falling
edge of the selected tap of the timebase timer. If the flip-flop is not cleared at the second fall, a reset signal
is generated.
Figure 3.12-4 shows the watchdog timer operation timings.
Figure 3.12-4 Watchdog Timer Operation Timings
Timebase timer overflow
Watchdog flip-flop
Write
Watchdog start
Watchdog clear
Watchdog reset
■ Causes of Reset Delays Other than Programs
The following cause the watchdog timer to automatically delay generation of a reset:
1. Stop or sleep state
2. DMA transfer
3. A break occurs when the emulator debugger or the monitor debugger is being used.
4. The INTE instruction is executed.
5. Step trace trap (a break occurs at each instruction by specifying 1 for T in the PS register)
Notes:
• The write interval between the first A5H and the next 5AH is not prescribed. A watchdog reset can
be deferred only when the interval of writing 5AH twice is within the time specified on the WT bit
and A5H is written at least once within the period.
• If the write value after the first A5H is something other than 5AH, the first A5H write becomes
invalid. Therefore, A5H should be written again.
■ Timebase Timer
The timebase timer is used to supply clock signals to the watchdog timer, and count the amount of time the
system waits for oscillation stabilization. φ is twice the X0 value when the CHC bit in the GCR register is 1
and equal to the PLL oscillation frequency when the CHC bit is 0.
The 1/25 value of this timebase timer is used as the DRAM refresh count clock in the RFCR register.
Figure 3.12-5 Timebase Timer Counter
φ→
84
1/21
1/22
1/23
........
1/218
1/219
1/220
1/221
CHAPTER 3 CPU
3.12.8
Gear Function
The gear function thins out and provides clock signals. The gear control section
consists of two independent circuits for the CPU and peripheral so as to enable data
transfer between the CPU and a peripheral at different gear ratios. As the original clock,
a clock synchronous with the PLL clock or a clock from the divide-by-2 circuit can be
specified.
■ Block Diagram of the Gear Control Section
Figure 3.12-6 shows a block diagram of the gear control section.
Figure 3.12-6 Block Diagram of the Gear Control Section
CPU gear interval
designation signal
GCR
CCK0,
CCK1
PCK0,
PCK1
CPU clock
Gear interval
generator for
CPU clock
DBLON
CHC
X0
X1
Oscillation
circuit
PLL
1/2
Selection
circuit
Gear interval
generator for
peripheral clock
Original clock
Internal clock generator
Internal bus
Internal bus clock
Internal DMA clock
DSP macro clock
External bus clock
Internal peripheral clock
Peripheral gear interval
designation signal
85
CHAPTER 3 CPU
■ Setting the Gear Ratio
When setting the gear ratio, set a desired value to the CCK1 and CCK0 bits of the gear control register
(GCR) for CPU clock control and to the PCK1 and PCK0 bits for peripheral clock control.
[Example]
LDI:20
#GCR,R2
LDI:8
#11111110b,R1
; CCK=11,PCK=11,CHC=0
STB
R1,@R2
; CPU clock=1/8f, Peripheral clock=1/8f,
; f=direct
LDI:8
#01111010b,R1
; CCK=01,PCK=10,CHC=0
STB
R1,@R2
; CPU clock=1/2f, Peripheral clock=1/4f,
LDI:8
#00111010b,R1
; CCK=00,PCK=10,CHC=0
STB
R1,@R2
; CPU clock=f, Peripheral clock=1/4f,
; f=direct
; f=direct
LDI:8
#00110010b,R1
; CCK=00,PCK=00,CHC=0
STB
R1,@R2
; CPU clock=f, Peripheral clock=f,
; f=direct
LDI:8
#10110010b,R1
; CCK=10,PCK=00,CHC=0
STB
R1,@R2
; CPU clock=1/4f, Peripheral clock=f,
; f=direct
When the CHC bit in the gear control register is set to 1, the output from the divide-by-2 circuit is selected
as the original clock. When the bit is set to 0, a clock synchronous with the clock from the oscillation
circuit is used as is.
Since the original clock is switched, both the CPU and peripheral systems change together.
[Example]
LDI:8
#01110001b,R1
LDI:20
#GCR,R2
STB
R1,@R2
; CCK=01,PCK=00,CHC=1
; CPU clock=1/2f, Peripheral clock=f,
; f=1/2xtal
LDI:8
#00110011b,R1
; CCK=00,PCK=00,CHC=1
STB
R1,@R2
; CPU clock=f, Peripheral clock=f,
; f=1/2xtal
LDI:8
#00110010b,R1
; CCK=00,PCK=00,CHC=0
STB
R1,@R2
; CPU clock=f, Peripheral clock=f,
; f=direct
86
CHAPTER 3 CPU
Figure 3.12-7 shows a clock selection timing chart.
Figure 3.12-7 Clock Selection Timing Chart
Original clock
CPU clock (a)
CPU clock (b)
Peripheral clock (a)
Peripheral clock (b)
CHC
CCK value
01
PCK value
00
00
■ Blocks Using the Peripheral Clock
The following blocks use the peripheral clock that can be set using the gear function.
• Clock generator
• Interrupt controller
• Ports D to I
• U-TIMER (channels 0 to 2)
• UART (channels 0 to 2)
• A/D converter
• 16-bit reload timer (channels 0 to 2)
• External interrupt
• NMI controller
• Delayed interrupt module
The above blocks use the peripheral clock for operation.
Calculate the operation time from the dividing ratio set on the PCK0 and PCK1 bits of the GCR register in
the clock generator.
87
CHAPTER 3 CPU
3.12.9
Reset Source Hold Function
The reset source hold circuit holds the source of reset immediately before in the reset
source register. Reading this register clears all the bits to 0. A source flag once set is
not cleared until the register is read.
■ Block Diagram of the Reset Source Hold Circuit
Figure 3.12-8 shows a block diagram of the reset source hold circuit.
Figure 3.12-8 Block Diagram of the Reset Source Hold Circuit
Internal bus
RSTX input
circuit
Watchdog
reset detection
circuit
RSTX pin
88
PONR
PONR
WDOG
WDOG
ERST
ERST
SRST
SRST
clr
SRST
Status=RST
STCR
Initialized by
reading
Decoder
or
Status
transition
From power-on cell
CHAPTER 3 CPU
■ Setting the Reset Source Hold Function
No special setting is necessary when using this function. Place a reset source register read instruction and a
branch instruction at the beginning of the program at the reset entry address to branch control to an
appropriate program.
[Example]
RESET-ENTRY
LDI:20
#RSRR,R10
LDI:8
#10000000B,R2
LDUB
@R10,R1
; GET RSRR VALUE INTO R1
MOV
R1,R10
; R10 USED AS A TEMPORARY REGISTER
AND
R2,R10
; WAS PONR RESET?
BNE
PONR-RESET
LSR
#1,R2
; POINT NEXT BIT
MOV
R1,R10
; R10 USED AS A TEMPORARY REGISTER
AND
R2,R10
; WAS HARDWARE STANDBY RESET?
BNE
HSTB-RESET
LSR
#1,R2
; POINT NEXT BIT
MOV
R1,R10
; R10 USED AS A TEMPORARY REGISTER
AND
R2,R10
; WAS WATCH DOG RESET?
BNE
WDOG-RESET
.
.
Notes:
• When the PONR bit is 1, the other bits should be handled as undefined. If the reset source should
be checked, be sure to place a power-on check instruction at the beginning.
• A reset source check instruction can be placed at an arbitrary position for a check other than a
power-on reset check. The priority is determined in the order of write.
89
CHAPTER 3 CPU
3.12.10
DMA Suppression Function
If an interrupt request of a higher priority during DMA transfer, the FR family interrupts
the DMA transfer and branches control to the interrupt routine. The DMA suppression
circuit is effective as long as an interrupt request exists. When the interrupt source is
cleared, the circuit is deactivated and the DMA transfer starts again in the interrupt
processing routine.
Therefore, use the DMA suppression function to suppress DMA transfer restart after
clearing the interrupt source in the routine that processes the interrupt source at the
level at which DMA transfer is stopped.
Write a value other than "0" in the DMA suppression register (PDRR) to start the DMA
transfer function and "0" to stop.
■ Block Diagram of the DMA Suppression Circuit
Figure 3.12-9 shows a block diagram of the DMA suppression circuit.
Figure 3.12-9 Block Diagram of the DMA Suppression Circuit
PDRR
Internal bus
D3
D2
nor
D1
D0
DMA request
and
Status transition control circuit
■ Setting the DMA Suppression Function
This function is mainly used in the interrupt processing routine. The DMA suppression register value is
incremented by one before the interrupt processing routine clears the interrupt source.
Then no more DMA transfer is made. The DMA suppression register value is decremented by one before
return from the interrupt processing. If the interrupt is multiple, DMA transfer remains suppressed because
the register value does not become 0. If the interrupt is not multiple, the DMA transfer request is enabled
because the register value becomes "0".
90
CHAPTER 3 CPU
[Example]
INT-ENTRY
LDI:20
#PDRR,R10
LD
@R10,R1
ADD
#1,R1
ST
R1,@R10
; PDRR:=PDRR+1, DMA disabled
LDI:20
#int-REG,R10
; int occurred with int-REG
LDI:8
#10H,R1
; example, int-flag=#10h
ST
R1,@R10
; CLEAR int-REQ,(but still DMA disabled)
; GET PDRR VALUE INTO R1
.
.
; interrupt execute routine
.
.
LDI:20
#PDRR,R10
LD
@R10,R1
SUB
#1,R1
ST
R1,@R10
; GET PDRR VALUE INTO R1
; PDRR:=PDRR-1, DMA may be enabled
RETI
Notes:
• Since this register consists of four bits, this function cannot be used for a multiple interrupt of over
15 levels. A DMA task should have priority of 15 levels higher than other interrupt levels.
• When an NMI interrupt is accepted, the source is cleared automatically and DMA cannot be
suppressed. When the interrupt is accepted, DMA transfer restarts. When DMA terminates, NMI
processing is executed.
• The PDRR register may not be used alone. Always combine the PDRR register with the HRCL
register of the interrupt controller (see Section "14.6 Notes on DMA Controller").
91
CHAPTER 3 CPU
3.12.11
Clock Doubler Function
The clock doubler function enables the external bus to internal operating frequency
ratio of 1:2 to prevent a rise of the internal operating frequency from making the
external bus timing severe.
■ Activating the Clock Doubler Function
Set the DBLON bit in the GCR register to "1" to activate the clock doubler function. When the bit is set to
"1", the external bus clock is switched at the end of all C-bus accesses. Although there is a slight time lag in
switching, the switching timing can be known from the DBLAK bit in the GCR register.
When the clock doubler function is activated, the CPU clock gear ratio is set to 1/1, regardless of the GCR
setting.
This device allows the external bus operating frequency to be set up to 25 MHz. To turn the clock doubler
function on, set as follows:
[Example]
DOUBLER-ON
LDI:20
#GCR,R0
BORL
#0001B,@R0
BORH
#0001B,@R0
; Clock doubler on (DBLON=1)
BTSTH
#0010B,@R0
; DBLAK check
BEQ
LOOP
; Loop until DBLAK becomes 1
BANDL
#1110B,@R0
; Switching to PLL system (CHC=0)
; Switching to divide-by-two system
; (CHC=1)
LOOP
■ Deactivating the Clock Doubler Function
Set the DBLON bit in the GCR register to "0" to deactivate the clock doubler function. The CPU clock gear
ratio returns from 1/1 according to the setting of the CCK bit in the GCR register.
[Example]
DOUBLER-OFF
LDI:20
#GCR,R0
BORL
#0001B,@R0
BANDH
#1110B,@R0
; Switching to divide-by-two system
; (CHC=1)
; Clock doubler off (DBLON=0)
When using the PLL clock after turning the clock doubler function off, set as follows:
92
CHAPTER 3 CPU
[Example]
DOUBLER-OFF
LDI:20
#GCR,R0
BORL
#0001B,@R0
; Switching to divide-by-two system
; (CHC=1)
BANDH
#1110B,@R0
; Clock doubler off (DBLON=0)
LDI:20
#PCTR,R1
LDI:8
#01000000B,R2
STB
R2,@R1
; PLL=25MHz
BANDL
#1110,@R0
; Switching to PLL system (CHC=0)
■ Precaution on Clock Doubler Function ON/OFF
When the clock doubler function is turned ON and OFF, the internal clock may generate a dead cycle. If a
dead cycle is generated, an error occurs in time measurement using a timer and a UART transfer.
■ Combination of Operating Frequencies by Clock Doubler Function ON/OFF
Table 3.12-5 lists the combinations of operating frequencies of this device depending on the SLCT1 and
SLCT0 bits in the PCTR register and the GCR register setting (oscillation: 12.5 MHz).
Table 3.12-5 Combinations of Operating Frequencies by Clock Doubler Function ON/OFF
GCR
CHC
Divideby-two
PLL *3
Gear
PLL oscillation
frequency (MHz)
Clock
doubler
Internal operating
frequency (MHz)
External bus
frequency (MHz)
1/1
-
OFF
6.25
6.25
1/2
-
OFF
3.12
3.12
1/4
-
OFF
1.56
1.56
1/8
-
OFF
0.78
0.78
*1
-
ON
6.25
3.12
-
50.0
OFF
50.0
50.0
1/1
25.0
OFF
25.0
25.0
1/2
25.0
OFF
12.5
12.5
1/4
25.0
OFF
6.25
6.25
1/8
25.0
OFF
3.12
3.12
1/1
12.5
OFF
12.5
12.5
1/2
12.5
OFF
6.25
6.25
1/4
12.5
OFF
3.12
3.12
1/8
12.5
OFF
1.56
1.56
*1
50.0
ON
50.0
25.0
*1
25.0
ON
25.0
12.5
*1
12.5
ON
12.5
6.25
Remarks
Initial value
Do not set
*2
*1: The rate is fixed at 1:1, irrespective of setting.
*2: When turning the clock doubler function off, first change to the divide-by-two clock.
*3: When changing the PLL oscillation frequency, change to the divide-by-two clock.
93
CHAPTER 3 CPU
3.12.12
Example of PLL Clock Setting
This section provides an example of a PLL clock setting with a sample assembler
source.
■ Example of PLL Clock Setting
Figure 3.12-10 shows an example of switching to the 50-MHz PLL clock.
Figure 3.12-10 Example of PLL Clock Setting
No
CHC = 1
CHC
For PLL-related setting, switch to the divide-by-two clock first.
-1
Yes
No
DBLON = 1
DBLON
-1
When the doubler function is turned on, the CPU clock
gear rate is fixed at CPU=1/1. The peripheral system allows
an arbitrary setting.
Yes
DBLAK = 1
No
Yes
No
VSTP = 0
VSTP
-0
Yes
Reactivate the PLL if stopped. When reactivating the PLL,
however, 300 s or longer stabilization wait time should be
reserved by software.
WAIT 100 µs
SLCT1
CHC
-1
-0
Switch the PLL output tap to 50 MHz.
Switch from the divide-by-two clock to the PLL clock.
Notes:
• The DBLON, VSTP, and SLCTI bits may be set in an arbitrary order.
• Make sure that the peripheral operating frequency does not exceed 25 MHz.
• When reactivating the PLL, however, be sure to wait 300 µs or longer stabilization wait time by
software. Be careful not to make the wait time short by cache on/off.
94
CHAPTER 3 CPU
■ Reference Drawing of the Clock System
Figure 3.12-11 Reference Drawing of the Clock System
12.5MHz
1/2
PLL input
CHC
1
0
DBLON
DBLACK
CPU, DSP macro
Peripheral
1/2
P L L
Oscillation input
Divide-by-two
clock input
50MHz
VSTP
STAND-BY
1/2
SLCT1,0
1X
01
00
GCR register
25MHz
PCTR register
1/2
12.5MHz
■ Sample Assembler Source
; *******************************************
;
PLL Sample Program
; *******************************************
; Load Setting Data
ldi:20
#GCR, R0
ldi:20
#PCTR,R1
ldi:8
#GCR_MASK,R2
; GCR_MASK = 0000 0001 b
ldi:8
#PCTR_MASK,R3
; PCTR_MASK = 0000 1000 b
ldub
@R0,R4
; read GCR register
ldub
@R1,R5
; read PCTR register
st PS,
@-R15
; push processor status
stilm
#0x0
; disable interrupt
borl
#0001B,@r0
; to 1/2 clock @r0=GCR register
call
VCO_RUN
call
DOUBLER_ON
;
and R4,R2
beq CHC_0
bra CHC_1
CHC_0:
CHC_1:
PLL_SET_END:
ld @R15+, PS
; pop processor status
95
CHAPTER 3 CPU
; *******************************************
;
VCO Setting
; *******************************************
VCO_RUN:
st
R3,@-R15
; push R3
ldi:8
#PCTR _MASK,R3
; PCTR_MASK = 0000 1000 b
and
R5, R3
; PTCR->VSTP=1 ?
beq
LOOP_100US_END
; if VSTP = 0 return
st
R2, @-R15
; push R2 for Loop counter
bandl
#0111B,@r1
; set VSTP = 0
ldi:20
#0x41A,R2
; set VSTP = 1 and wait 100 µs
WAIT_300US:
; 300us = 160ns(6.25MHz)
; * 7 * 300 (834)cycle
add2
#(-1), R2
bne
WAIT_300US;
; 384h/2 = 41Ah (if cache on)
LOOP_100US_END:
ld
@R15+, R2
; Pop R2
ld
@R15+, R3
; Pop R3
ret
; *******************************************
;
doubler ON
; *******************************************
DOUBLER_ON:
borh
#0001B,@r0
; doubler ON
btsth
#0010B,@r0
; check DBLACK
beq
LOOP_DBLON1
; loop while DBLACK = 0
bandl
#1110B,@r0
; to 1/1(PLL) clock
LOOP_DBLON1:
nop
nop
nop
nop
nop
nop
ret
96
CHAPTER 3 CPU
3.13
Low-power Consumption
The low-power consumption mode can be divided into the stop status and the sleep
status.
■ Outline of the Stop Status
In the stop status, all internal clocks and the oscillation circuit are disabled. The power consumption is
minimal in this status.
Change to the stop status using the following method:
• Writing the standby control register (STCR) using an instruction
Return to the operation status using one of the following methods:
• Issuing an interrupt request (only from a peripheral that can issue an interrupt request even in the stop
status)
• Applying a "L" level signal to the RSTX pin
In the stop status, all internal peripheral circuits except one capable of generating a return interrupt are
disabled because all internal clocks are stopped.
■ Outline of the Sleep Status
In the sleep status, the CPU clock and internal bus clock are disabled. Since the CPU need not operate, the
power consumption is suppressed to some extent.
Change to the sleep status using the following method:
• Writing the standby control register (STCR) using an instruction
Return to the operation status using one of the following methods:
• Issuing an interrupt request
• Generating a reset source
The internal DMA clock and the peripheral clock operate in sleep status. An interrupt from any internal
peripheral using these two clocks can clear the sleep status.
97
CHAPTER 3 CPU
■ List of Operations in Low-power Consumption Mode
Table 3.13-1 lists operations in low-power consumption mode.
Table 3.13-1 Operations in Low-power Consumption Mode
Internal clock
Operation
status
Transition
condition
Oscillator
CPU/
internal
bus
DMA/
peripheral/
DSP
macro
Run
-
Y
Y
Y
Y
Operation
-
Sleep
SLEP = 1 in
STCR
Y
N
Y
Y
Operation
-
Stop
STOP = 1 in
STCR
N
N
N
N
Peripheral
Pin
Clearing
method
*
-
Y: Operation
N: Stop
*: The status remains unchanged when the HIZX bit in the STCR register is set to 0 and changes to Hi-Z when the bit is set to 1.
Note:
Reset: RSTX = 0
SRST = 0 in STCR
Watchdog reset
Power-on reset
■ Restrictions on Standby Status
● Address of program to be set to stop or sleep status
To set to the stop or sleep status, place a program in C-bus ROM or in the address area of external memory.
If the program is placed in the address area of I-bus ROM, the post-return operation cannot be guaranteed.
98
CHAPTER 3 CPU
3.13.1
Standby Control Register (STCR)
The standby control register (STCR) controls the standby operation and specifies the
oscillation stabilization wait time.
■ Standby Control Register (STCR)
The standby control register (STCR) has the following register configuration.
STCR
07
000481H
06
05
04
03
02
01
00
Initial value
Access
-
-
000111--B
R/W
STOP SLEP HIZX SRST OSC1 OSC0
Bit 07: STOP
Writing 1 into this bit sets the stop status where the internal peripheral and internal CPU clocks and the
oscillation are stopped.
Bit 06: SLEP
Writing 1 into this bit sets the sleep status where the internal CPU clock is stopped.
If 1 is written into both bits 07 and 06, the stop status is set.
Bit 05: HIZX
If the stop status is set when "1" is written into this bit, the device pin is set to high impedance.
Bit 04: SRST
Writing 0 into this bit generates a software reset request.
Bits 03 and 02: OSC1 and OSC0
These bits are used to specify the oscillation stabilization wait time. Table 3.13-2 shows the
correspondence between the bit values and the specified cycles. Power-on or hardware standby reset
initializes these bits, which are not affected by other reset sources.
Table 3.13-2 Oscillation Stabilization Wait Times Specified by OSC1 and OSC0
OSC1
OSC0
Oscillation stabilization wait time
0
0
φ x 215
0
1
φ x 217
1
0
φ x 219
1
1
φ x 221 [Initial value]
φ is twice the X0 value.
Bits 01 and 00: (Reserved)
These bits are reserved. The read values are not defined.
99
CHAPTER 3 CPU
3.13.2
Stop Status
In the stop status, all the internal clocks and the oscillation circuit are disabled. The
power consumption is minimal in this status.
■ Block Diagram of the Stop Control Section
Figure 3.13-1 shows a block diagram of the stop control section.
Figure 3.13-1 Block Diagram of the Stop Control Section
clear
Internal interrupt
Internal reset
or
CPU hold enable
CPU hold request
Stop status display signal
CPU clock
CPU clock
generator
Internal
bus clock
generator
Internal
DMA clock
generator
Internal clock generator
STOP
Status decoder
STCR
Internal bus
Status transition control circuit
Stop status transition request signal
Stop signal
Internal
peripheral
clock
generator
Clock stop
request signal
Internal bus clock
Internal DMA clock
External bus clock
Internal peripheral clock
Clock release
request signal
■ Changing to the Stop Status
● Setting the stop status using an instruction
To set the stop status, write 1 into STCR bit 7.
The stop request makes the CPU not use the internal bus and stops the clocks in the following order:
CPU clock ==> Internal bus clock ==> Internal DMA clock ==> Internal peripheral clock
The oscillation circuit is stopped simultaneously with the internal peripheral clock.
Notes:
• To set the stop status using an instruction, be sure to use the routine shown below.
• When writing the STCR register, set the same value to the pairs of CCK1, CCK0 and PCK1,
PCK0 in the GCR register to make the gear ratios of the CPU and peripheral clocks equal.
• Do not set the stop status when the CHC bit in the GCR register is 0 (operation on PLL). When
setting the stop status, write 1 into the CHC bit in the GCR register to select the divide-by-two
clock first.
• When setting the stop status, turn off the clock doubler.
• At least six continuous NOP instructions are necessary immediately after STCR write.
100
CHAPTER 3 CPU
[Setting method: Top gear level]
LDI:20
#GCR,R0
LDI:8
#00000011b,R1
STB
R1,@R0
loop
BTSTH
#0010b,@R0
BNE
loop
LDI:20
#STCR,R0
LDI:8
#10010000b,R1
STB
R1,@R0
NOP
NOP
NOP
NOP
NOP
NOP
; CHC=1,CPU=Peripheral gear ratio
; DBLON=0
;
; Wait until DBLAK becomes 0
; STOP=1
;
;
;
;
;
;
■ Returning from the Stop Status
An interrupt or reset can return the CPU from stop status.
● Return by interrupt
If the interrupt enable bit accompanying the peripheral function is valid, a peripheral interrupt returns the
CPU from stop status.
The return procedure from the stop status to the ordinary operation status is as follows:
Interrupt ==> Restart of oscillation circuit ==> Wait for stabilization ==> Restart of internal peripheral
clock supply ==> Restart of internal DMA clock supply ==> Restart of internal bus clock supply ==>
Restart of internal CPU clock supply
After the oscillation stabilization wait time, the program processing becomes as follows:
• If the interrupt level is permitted by the I flag in the ILM register of the CPU
- After the register is saved, an interrupt vector is imported and executed by the interrupt processing
routine.
• If the interrupt level is prohibited by the I flag in the ILM register of the CPU
- Execution starts from the instruction following the stop status setting instruction.
● Return using the RSTX pin
The return procedure from the stop status to the ordinary operation status is as follows:
"L" level signal application to RSTX pin ==> Internal reset ==> Restart of oscillation circuit ==> Wait for
stabilization ==> Restart of internal peripheral clock supply ==> Restart of internal DMA clock supply ==>
Restart of internal bus clock supply ==> Restart of internal CPU clock supply ==> Import of reset vector
==> Restart of execution from reset entry address
Notes:
• If an interrupt request has already been issued from a peripheral, the CPU does not change to the
stop status but ignores write access.
• No internal clocks are supplied during the oscillation stabilization wait time except after power-on
reset. After power-on reset, however, all internal clocks are supplied to initialize the internal
status.
101
CHAPTER 3 CPU
3.13.3
Sleep Status
In the sleep status, the CPU clock and internal bus clock are disabled. Since the CPU
need not operate, the power consumption is suppressed to some extent.
■ Block Diagram of the Sleep Control Section
Figure 3.13-2 shows a block diagram of the sleep control section.
Figure 3.13-2 Block Diagram of the Sleep Control Section
Sleep status transition request signal
Stop signal
Internal interrupt
Internal reset
or
CPU hold enable
CPU hold request
Stop status display signal
CPU clock
CPU clock
generator
Internal
bus clock
generator
Internal clock generator
clear
Status decoder
STCR
SLEP
Status transition control circuit
Internal bus
Internal
DMA clock
generator
bus clock
generator
Internal
peripheral
clock
generator
Clock stop
request signal
Internal bus clock
Internal DMA clock
External bus clock
Internal peripheral clock
Clock release
request signal
■ Changing to the Sleep Status
To set the sleep status, write 0 into STCR bit 7 and 1 into STCR bit 6.
The sleep request makes the CPU not use the internal bus and stops the clocks in the following order:
CPU clock ==> Internal bus clock
Note:
To set the sleep status using an instruction, be sure to use the routine shown below.
When writing the STCR register, set the same value to the pairs of CCK1, CCK0 and PCK1, PCK0 in
the GCR register to make the gear ratios of the CPU and peripheral clocks equal.
The CHC bit in the GCR register may be set arbitrarily.
At least six continuous NOP instructions are necessary immediately after STCR write.
102
CHAPTER 3 CPU
[Setting method: Top gear level]
LDI:20
#GCR,R0
LDI:8
#00000011b,R1
; CHC=1,CPU=Peripheral gear ratio
STB
R1,@R0
; DBLON=0
LDI:20
#STCR,R0
LDI:8
#01010000b,R1
STB
R1,@R0
; SLEP=1
NOP
;
NOP
;
NOP
;
NOP
;
NOP
;
NOP
;
■ Returning from the Sleep Status
An interrupt or reset can return the CPU from sleep status.
● Return by interrupt
If the interrupt enable bit accompanying the peripheral function is valid, a peripheral interrupt returns the
CPU from sleep status.
The return procedure from the sleep status to the ordinary operation status is as follows:
Interrupt ==> Restart of internal bus clock supply ==> Restart of internal CPU clock supply
After the restart of clock supplies, the program processing becomes as follows:
• If the interrupt level is permitted by the I flag in the ILM register of the CPU
- After the register is saved, an interrupt vector is imported and executed by the interrupt processing
routine.
• If the interrupt level is prohibited by the I flag in the ILM register of the CPU
- Execution starts from the instruction following the sleep status setting instruction.
● Return by reset request
The return procedure from the sleep status to the ordinary operation status is as follows:
Internal reset ==> Restart of internal bus clock supply ==> Restart of internal CPU clock supply ==>
Import of reset vector ==> Restart of execution from reset entry address
Note:
If there is already a peripheral interrupt, the CPU does not change to the sleep status.
DMA transfer is prohibited in sleep mode. To change to sleep mode, disable DMA.
103
CHAPTER 3 CPU
3.13.4
Status Transition in Low-power Consumption Mode
Figure 3.13-3 shows status transition in low-power consumption mode.
■ Status Transition in Low-power Consumption Mode
Figure 3.13-3 Status Transition in Low-power Consumption Mode
Power-on
Oscillation
stabilization
wait reset status
(3)
(1)
Oscillation
stabilization
wait status
(3)
Reset status
(1)
(2)
(3)
(5)
(3)
Stop status
Run status
(6)
(4)
(5)
Sleep status
(3)
104
(1) End of oscillation stabilization wait time
(4) SLEP = 1 in STCR register
(2) Reset release
(5) Interrupt or NMI input
(3) Reset input
(6) STOP = 1 in STCR register
CHAPTER 3 CPU
3.14
Memory Access Modes
The MB91121 operation modes related to memory access are bus mode and access
mode.
The operation modes are controlled using the mode pins (MD3 to MD0) and the mode
register (MODR).
■ Operation Modes
The operation modes are bus mode and access mode.
Bus mode
Access mode
Single chip
Internal ROM/external bus
External ROM/external bus
16-bit bus
8-bit bus
● Bus mode
In bus mode, the internal ROM and external access function are controlled according to the mode pins
(MD3 to MD0) and the M1 and M0 bits in the mode register (MODR).
● Access mode
In access mode, the external data bus width is controlled according to the mode pins (MD3 to MD0) and
the BW1 and BW0 bits in the area mode register (AMD0/AMD1/AMD2/AMD32/AMD4/AMD5).
105
CHAPTER 3 CPU
■ Mode Pins
By using the four mode pins from MD3 to MD0, specify a mode as shown in Table 3.14-1.
Table 3.14-1 Mode Pins and Set Modes
Mode pin
Reset vector
access area
Mode name
External data
bus width
Remarks
MD3
MD2
MD1
MD0
1
0
0
0
External vector
mode 0
External
8 bit
External ROM external
bus mode
1
0
0
1
External vector
mode 1
External
16 bit
External ROM external
bus mode
1
0
1
0
1
0
1
1
1
1
-
-
-
-
-
Do not use
0
-
-
-
-
-
-
Do not use and set
-
-
Internal vector
mode
-
Internal
Do not set
Single chip mode*
(Mode register)
*: MB91121 does not support single chip mode.
■ Mode Data
The data that the CPU writes into 000007FFH is called mode data.
The mode register (MODR) exists at 000007FFH. Once this register has been set, the CPU operates in the
mode set in this register.
After reset, the mode register can be written once only.
The set value in this register becomes valid immediately after write.
■ Mode Register (MODR)
The mode register (MODR) has the following configuration:
Figure 3.14-1 Mode Register (MODR)
MODR
Address: 0000 07FFH
M1
M0
*
*
*
*
*
*
Initial value
Access
XXXXXXXXB
W
Bus mode setting bits
106
CHAPTER 3 CPU
● Bus mode setting bits (M1, M0)
These bits are used to specify the bus mode after the mode register is written.Table 3.14-2 lists the bus
mode setting bits and explains their functions.
Table 3.14-2 Bus Mode Setting Bits and Functions
M1
M0
0
0
1
1
0
1
0
1
Function
Remarks
Single chip mode
Internal ROM/external bus mode
External ROM/external bus mode
-
See Precaution.
Do not set
Note:
In the model without internal ROM, set "10B". In this model, the setting value is "10B".
● Other bits (*)
Always write 0.
■ Notes on Mode Register (MODR) Write
Before writing the MODR register, set AMD0 to AMD5 and determine the bus width of each chip selector
(CS) area.
The MODR register does not have bus width setting bits.
As to the bus width, the values of mode pins MD3 to MD0 are valid before MODR write and those of BW1
and BW0 in AMD0 to AMD5 are valid after MODR write.
For example, an external reset vector is valid in ordinary area 0 (CS0X active area) but mode pins MD3 to
MD0 determine the bus width. The initial value of bus width setting bit AMD0 is 8 bits. Therefore, if the
MODR register is written after the bus width is set to 16 bits on the mode pins but AQMD0 is not set, area
0 changes to 8-bit bus mode after written into the MODR register and causes a malfunction.
To prevent this problem, be sure to set AMD0 to AMD5 before MODR write.
MODR writing part
RSTX (reset)
Bus width specification: MD3,MD2,MD1,MD0
BW1 and BW0 in AMD0 to AMD5
107
CHAPTER 3 CPU
108
CHAPTER 4
BUS INTERFACE
This chapter provides a sample program for bus
operations and an outline of the bus interface explaining
the register configuration and functions, bus operations,
and bus timings.
4.1 Outline of the Bus Interface
4.2 Block Diagram of the Bus Interface
4.3 Bus Interface Registers
4.4 Bus Operations
4.5 Bus Timing
4.6 Internal Clock Multiplication (Clock Doubler)
4.7 Sample Program for External Bus Operations
109
CHAPTER 4 BUS INTERFACE
4.1
Outline of the Bus Interface
The bus interface controls the interface with external memory and external I/O devices.
■ Features of the Bus Interface
• 25-bit (32M-byte) address output
• Six independent banks by chip selection function
- Setting at an arbitrary space in the logical address space in the minimum units of 64K-byte
- Address and chip select pins for setting a total area of 32M-byte × 6
• Bus width setting (16 or 8 bits) for each chip select area
• Programmable insertion of automatic memory wait (for 7 cycles max.)
• DRAM interface support
- Three DRAM interfaces: Double CAS DRAM (ordinary DRAM interface), Single CAS DRAM,
Hyper DRAM
- Two-band independent control (RAS, CAS, and other control signals)
- 2CAS/1WE or 1CAS/2WE DRAM selectable
- High-speed page mode
- CBR refresh and self refresh
- Programmable waveform output
• Unused address and data terminals available as I/O ports
• Little endian mode
• Clock doubler: Internal (50 MHz) and external bus (25 MHz)
■ Chip Select Area
The bus area has a total of six chip select areas.
Each area can be placed at an arbitrary position in a 4G-byte space in the minimum unit of 64K-byte using
the area selection registers (ASR1 to ASR5) and area mask registers (AMR1 to AMR5).
If external bus access is attempted in an area specified by these registers, the corresponding chip select
signal (CS0X to CS5X) becomes actively low.
Reset makes these pins actively high, excluding CS0X.
Note:
Area 0 is allocated to a space outside the area specified by ASR1 to ASR5.
In the reset status, the external area other than 00010000H to 0005FFFFH is area 0.
Figure 4.1-1 (a) shows an example where areas 1 to 5 are placed at 00100000H to 0014FFFFH in units of
64K-byte. Figure 4.1-1 (b) shows an example where area 1 is placed at the 512K-byte space of 00000000H
to 0007FFFFH and areas 2 to 5 are placed at 00100000H to 004FFFFFH in units of 1M-byte.
110
CHAPTER 4 BUS INTERFACE
Figure 4.1-1 Example of Chip Select Area Arrangement
00000000H
00080000H
CS0X(1M byte)
00000000H
CS1X(512K byte)
00080000H
CS0X(512K byte)
000FFFFFH
CS2X(1M byte)
000FFFFFH
001FFFFFH
0010FFFFH
CS1X(64K byte)
0011FFFFH
CS2X(64K byte)
0012FFFFH
CS3X(64K byte)
0013FFFFH
CS4X(64K byte)
0014FFFFH
CS5X(64K byte)
CS3X(1M byte)
002FFFFFH
CS4X(1M byte)
003FFFFFH
CS5X(1M byte)
004FFFFFH
CS0X
CS0X
(a)
(b)
■ Interface
The bus interface can be classified as follows:
• Ordinary bus interface
• DRAM interface
These interfaces can be used in predetermined areas only.
Table 4.1-1 shows the correspondence between the chip select areas and the selectable interface functions.
Select an interface using the area mode registers (AMD).
The default is the ordinary bus interface.
Table 4.1-1 Chip Select Areas and Selectable Interface Functions
Selectable bus interface
Area
Remarks
Ordinary bus
Time division
DRAM
0
Y
-
-
1
Y
-
-
2
Y
-
-
3
Y
-
-
4
Y
-
Y
5
Y
-
Y
At reset
111
CHAPTER 4 BUS INTERFACE
■ DRAM Interface
Two channels are prepared and areas 4 and 5 are used for DRAM interface
• Three DRAM interface types
- Double CAS DRAM (ordinary DRAM interface)
- Single CAS DRAM
- Hyper DRAM
• High-speed page mode
• 2CAS/1WE or 1CAS/2WE selectable
• CBR refresh
• Self refresh
• RAS/CAS programmable waveform output
● Specifying the bus size
An arbitrary bus width can be specified to each area by register setting.
Reset changes area 0 to the bus width specified by pins MD2 to MD0. Once the mode register (MODR) has
been written, a bus size is specified according to the setting of the AMD0 register.
112
CHAPTER 4 BUS INTERFACE
4.2
Block Diagram of the Bus Interface
Figure 4.2-1 shows a block diagram of the bus interface.
■ Block Diagram of the Bus Interface
Figure 4.2-1 Block Diagram of the Bus Interface
ADDRESS BUS
32
DATA BUS
32
A-OUT
EXTERNAL
DATA BUS
MUX
write
buffer
switch
read buffer
switch
DATA BLOCK
ADDRESS BLOCK
+1or+2
EXTERNAL
ADDRESS BUS
inpage
address
buffer
shifter
ASR1 to
ASR5
AMR1 to
AMR5
CS0X-CS5X
comparator
DRAM control
underflow
DMCR4,
DMCR5
RAS0, RAS1
CS0L, CS1L
CS0H, CS1H
DW0X,DW1X
refresh counter
from Time
Base Timer
External pin control section
RDX
WR0X,WR1X
All block control
registers
&
control
BRQ
BGRNTX
CLK
RDY
113
CHAPTER 4 BUS INTERFACE
4.3
Bus Interface Registers
Figure 4.3-1 shows the bus interface registers.
■ Bus Interface Registers
Figure 4.3-1 Bus Interface Registers
31
--------
24 23
--------
16 15
--------
8 7
--------
ASR1 (Area Select Reg. 1)
AMR1 (Area Mask Reg. 1)
ASR2 (Area Select Reg. 2)
AMR2 (Area Mask Reg. 2)
ASR3 (Area Select Reg.3)
AMR3 (Area Mask Reg.3)
ASR4 (Area Select Reg. 4)
AMR4 (Area Mask Reg. 4)
ASR5 (Area Select Reg.5)
AMR5 (Area Mask Reg. 5)
AMD0*1
AMD1*1
AMD5*1
DSCR*2
AMD32*1
AMD4*1
RFCR (ReFresh Control Register)
EPCR0 (External Pin Control 0)
EPCR1 (External Pin Control 1)
DMCR4 (DRAM Control Reg. 4)
DMCR5 (DRAM Control Reg. 5)
LER*3
MODR*4
*1: AMD (Area MoDe register)
*2: DSCR (DRAM Signal Control Register)
*3: LER (Little Endian Register)
*4: MODR (MODe Register)
For details of the mode register (MODR), see Section "3.14 Memory Access Modes".
114
0
CHAPTER 4 BUS INTERFACE
4.3.1
Area Selection Register (ASR) and Area Mask Register
(AMR)
The area selection registers (ASR1 to ASR5) and area mask registers (AMR1 to AMR5)
specify addresses for chip select areas 1 to 5.
■ Area Selection Register (ASR) and Area Mask Register (AMR)
The area selection register (ASR) and area mask register (AMR) have the following configurations:
● Area selection registers (ASR1 to ASR5)
ASR1
Address: 0000 060CH
15
A31
14
A30
13
A29
12
15
A31
14
A30
13
A29
12
15
A31
14
A30
13
A29
12
15
A31
14
A30
13
A29
12
15
A31
14
A30
13
A29
12
...
2
A18
1
A17
0
A16
Initial value
0001H
Access
W
...
2
A18
1
A17
0
A16
Initial value
0002H
Access
W
...
2
A18
1
A17
0
A16
Initial value
0003H
Access
W
...
2
A18
1
A17
0
A16
Initial value
0004H
Access
W
...
2
A18
1
A17
0
A16
Initial value
0005H
Access
W
ASR2
Address: 0000 0610H
ASR3
Address: 0000 0614H
ASR4
Address: 0000 0618H
ASR5
Address: 0000 061CH
115
CHAPTER 4 BUS INTERFACE
● Area mask registers (AMR1 to AMR5)
AMR1
Address: 0000 060EH
15
A31
14
A30
13
A29
12
15
A31
14
A30
13
A29
12
15
A31
14
A30
13
A29
12
15
A31
14
A30
13
A29
12
15
A31
14
A30
13
A29
12
...
2
A18
1
A17
0
A16
Initial value
0000H
Access
W
...
2
A18
1
A17
0
A16
Initial value
0000H
Access
W
...
2
A18
1
A17
0
A16
Initial value
0000H
Access
W
...
2
A18
1
A17
0
A16
Initial value
0000H
Access
W
...
2
A18
1
A17
0
A16
Initial value
0000H
Access
W
AMR2
Address: 0000 0612H
AMR3
Address: 0000 0616H
AMR4
Address: 0000 061AH
AMR5
Address: 0000 061EH
The area selection registers (ASR1 to ASR5) and area mask registers (AMR1 to AMR5) specify addresses
for chip select areas 1 to 5.
ASR1 to ASR5 specify the upper 16 bits (A31 to A16) and AMR1 to AMR5 mask the corresponding
address bits. Each bit AMR1 to AMR5 is set to 0 for "Care" and 1 for "Don’t care".
A bit in the Care status is set to 0 when the ASR value is 0 or to 1 when the ASR value is 1 to indicate the
address space. A bit in the Don’t care status indicates the address space for both cases, irrespective of the
ASR setting.
The following are two examples of specifying chip select areas by combining ASR and AMR.
[Example 1]
ASR1 = 00000000 00000011 B
AMR1 = 00000000 00000000 B
If the registers are set as above, the AMR1 bit corresponding to the ASR1 bit set to 1 is 0. Therefore, the
address space of area 1 will be 64K-byte as follows:
00000000 00000011 00000000 00000000 B (00030000 H)
to
00000000 00000011 11111111 11111111 B (0003FFFF H)
[Example 2]
ASR2 = 00001111 11111111 B
AMR2 = 00000000 00000011 B
If the registers are set as above, the ASR2 bit corresponding to the AMR2 bit set to 0 is 1, 0 (Care). The
ASR2 bit corresponding to the AMR2 bit set to 1 is 0 or 1 (Don’t care). Therefore, the address space of
area 2 will be 256K-byte as follows:
00001111 11111100 00000000 00000000 B (0FFC0000 H)
to
00001111 11111111 11111111 11111111 B (0FFFFFFF H)
116
CHAPTER 4 BUS INTERFACE
The bus area has a total of six chip select areas.
Each area from areas 1 to 5 can be placed at an arbitrary position in a 4G-byte space in the minimum unit
of 64K-byte using ASR1 to ASR5 and AMR1 to AMR5. If external bus access is attempted in an area
specified by these registers, the corresponding chip select signal (CS0X to CS5X) becomes low.
Area 0 is allocated to a space outside the area specified by ASR1 to ASR5 and AMR1 to AMR5.
In the reset status, an area other than 00010000H to 0005FFFFH is allocated according to the initial values
of ASR1 to ASR5 and AMR1 to AMR5.
Note:
Make sure that the chip select areas do not overlap.
Figure 4.3-2 compares a map set in units of 64K-byte according to the default setting at reset and the area
map based on Examples 1 and 2.
Figure 4.3-2 Maps where Chip Select Areas are Set
Initial value
Map based on Examples 1 and 2
00000000H
00000000H
Area 0
00010000H
Area 0
Area 1
64KB
00020000H
00030000H
Area 2
64KB
00030000H
Area 1
00040000H
Area 3
64KB
Area 0
0FFC0000H
00040000H
Area 4
64KB
Area 2
00050000H
Area 5
00060000H
256KB
64KB
10000000H
Area 0
FFFFFFFFH
64KB
Area 0
FFFFFFFFH
117
CHAPTER 4 BUS INTERFACE
4.3.2
Area Mode Register 0 (AMD0)
Area mode register 0 (AMD0) specifies the operation mode of chip select area 0 (area
other than those specified by ASR1 to ASR5 and AMR1 to AMR5). At reset, area 0 is
selected.
■ Area Mode Register 0 (AMD0)
Area mode register 0 (AMD0) has the following configuration:
AMD0
Address: 0000 0620H
7
6
5
4
3
-
-
-
BW1
2
1
0
Initial value
BW0 WTC2 WTC1 WTC0 ---00111B
Access
R/W
Bits 4 and 3: BW1, BW0 (Bus Width)
These bits specify the bus width of area 0.
BW1
BW0
0
0
1
1
0
1
0
1
Bus width
8 bits
16 bits
Do not set
Do not set
Bits 2 to 0: WTC2 to WCT0 (Wait Cycle)
These bits specify the number of wait cycles to be inserted automatically for the ordinary bus interface.
WTC2
WTC1
WTC0
Number of wait cycles to be inserted
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
2
3
4
5
6
7
WTC2 to WTC0 in AMD0 are set to 111 and seven wait cycles are automatically inserted into bus access
immediately after reset clearance.
Note:
The initial values of BW1 and BW0 are both "0". However, the terminal levels of MD1 and MD0, not
the register value, are read until MODR is written.
When writing the MODR register, set the same bus width as the one set on the BW1 and BW0 bits in
AMD0 and mode pins MD3 to MD0.
At reset, mode pins MD3 to MD0 specify the bus width of area 0. When the mode register (MODR) is
set, the bus width set in AMD0 becomes valid.
118
CHAPTER 4 BUS INTERFACE
MODR write
RSTX(reset)
CS0 bus width:
Pins DM3 to DM0
AMD0 register
When the bus width of area 0 is set to 16 bits on the MD3, MD2, MD1, and MD0 pins, the MODR register
may be written without setting AMD0. In this case, the bit width changes to 8 bits and a malfunction occurs
because the initial values of BW1 and BW0 in AMD0 are "00".
119
CHAPTER 4 BUS INTERFACE
4.3.3
Area Mode Register 1 (AMD1)
Area mode register 1 (AMD1) specifies the operation mode of chip select area 1 (area
specified by ASR1 and AMR1).
■ Area Mode Register 1 (AMD1)
Area mode register 1 (AMD1) has the following configuration:
AMD1
7
Address: 0000 0621H MPX
6
5
4
-
-
BW1
3
2
1
0
Initial value Access
BW0 WTC2 WTC1 WTC0 0--00000B
R/W
Bit 7: MPX (MultiPleX bit)
This bit controls a time-division I/O interface for address/data input and output.
This mode does not support a time-division I/O interface.
Always write 0.
Bits 4 and 3: BW1, BW0 (Bus Width bit)
These bits specify the bus width of area 1.
BW1
BW0
0
0
1
1
0
1
0
1
Bus width
8 bits
16 bits
Do not set
reserved
Bits 2 to 0: WTC2 to WTC0 (Wait Cycle)
These bits specify the number of wait cycles to be inserted automatically for the ordinary bus interface.
These bits are used in the same way as WTC2 to WTC0 in the AMD0 register.
Reset initializes these bits to 000B and the number of wait cycles to be inserted becomes 0.
120
CHAPTER 4 BUS INTERFACE
4.3.4
Area Mode Register 32 (AMD32)
Area mode register 32 (AMD32) specifies the operation modes of chip select areas 2
(area specified by ASR2 and AMR2) and 3 (area specified by ASR3 and AMR3).
These areas usually accept ordinary bus access and a special DRAM interface cannot
be used.
The bus widths of areas 2 and 3 are controlled together using the BW1 and BW0 bits
and the number of wait cycles can be set independently for automatic insertion.
■ Area Mode Register 32 (AMD32)
Area mode register 32 (AMD32) has the following configuration:
AMD32
7
Address: 0000 0622H
BW1
6
5
4
3
2
1
0
Initial value
BW0 WT32 WT31 WT30 WT22 WT21 WT20 00000000B
Access
R/W
Bits 7 and 6: BW1, BW0 (Bus Width)
These bits specify the bus width of areas 2 and 3.
BW1
BW0
0
0
1
1
0
1
0
1
Bus width
8 bits
16 bits
Do not set
reserved
Bits 5 to 3: WT32 to WT30 (Wait Cycle bit)
These bits specify the number of wait cycles to be inserted automatically at memory access to area 3.
These bits are used in the same way as WTC2 to WTC0 in the AMD0 register.
Reset initializes these bits to 000B and the number of wait cycles to be inserted becomes 0.
Bits 2 to 0: WT22 to WT20 (Wait Cycle bit)
These bits specify the number of wait cycles to be inserted automatically at memory access to area 2.
These bits are used in the same way as WTC2 to WTC0 in the AMD0 register.
Reset initializes these bits to 000B and the number of wait cycles to be inserted becomes 0.
121
CHAPTER 4 BUS INTERFACE
4.3.5
Area Mode Register 4 (AMD4)
Area mode register 4 (AMD4) specifies the operation mode of chip select area 4 (area
specified by ASR4 and AMR4).
The DRAM interface can be used in area 4.
■ Area Mode Register 4 (AMD4)
Area mode register 4 (AMD4) has the following configuration:
AMD4
7
Address: 0000 0623H DRME
6
5
4
-
-
BW1
3
2
1
0
Initial value
BW0 WTC2 WTC1 WTC0 0--00000B
Access
R/W
Bit 7: DRME (DRAM Enable bit)
This bit selects the ordinary bus interface or DRAM interface for area 4.
0: Ordinary bus interface [Initial value]
1: DRAM interface
When using the DRAM interface, provide delicate control using the DRAM control register (DMCR)
explained later.
Bits 4 and 3: BW1, BW0 (Bus Width bit)
These bits specify the bus width of area 4. These bits have the same functions as the BW bits of other
AMD registers. Even when the DRAM interface is used, the bus width specified by these bits is valid.
BW1
BW0
0
0
1
1
0
1
0
1
Bus width
8 bits
16 bits
Do not set
reserved
Bits 2 to 0: WTC2 to WTC0 (Wait Cycle bit)
These bits specify the number of wait cycles to be inserted automatically at memory access to area 4.
These bits have the same functions as the WTC bits of other AMD registers. Reset initializes these bits to
000B and the number of wait cycles to be inserted becomes 0.
When the DRAM interface is used, however, WTC2 to WTC 0 become invalid because the number of
control cycles is controlled with the DMCR.
122
CHAPTER 4 BUS INTERFACE
4.3.6
Area Mode Register 5 (AMD5)
Area mode register 5 (AMD5) specifies the operation mode of chip select area 5 (area
specified by ASR5 and AMR5).
The DRAM interface can be used in area 5.
■ Area Mode Register 5 (AMD5)
Area mode register 5 (AMD5) has the following configuration:
AMD5
7
Address: 0000 0624H DRME
6
5
4
-
-
BW1
3
2
1
0
Initial value
BW0 WTC2 WTC1 WTC0 0--00000B
Access
R/W
Bit 7: DRME (DRAM Enable bit)
This bit selects the ordinary bus interface or DRAM interface for area 5.
0: Ordinary bus interface [Initial value]
1: DRAM interface
When using the DRAM interface, provide delicate control using the DRAM control register (DMCR)
explained later.
Bits 4 and 3: BW1, BW0 (Bus Width bit)
These bits specify the bus width of area 5. These bits have the same functions as the BW bits of other
AMD registers. Even when the DRAM interface is used, the bus width specified by these bits is valid.
BW1
BW0
0
0
1
1
0
1
0
1
Bus width
8 bits [Initial value]
16 bits
Do not set
reserved
Bits 2 to 0: WTC2 to WTC0 (Wait Cycle bit)
These bits specify the number of wait cycles to be inserted automatically at memory access to area 5.
These bits have the same functions as the WTC bits of other AMD registers. Reset initializes these bits to
000B and the number of wait cycles to be inserted becomes 0.
When the DRAM interface is used, however, WTC2 to WTC 0 become invalid because the number of
control cycles is controlled with the DMCR.
123
CHAPTER 4 BUS INTERFACE
4.3.7
DRAM Control Registers 4/5 (DMCR4/DMCR5)
DRAM control registers 4 and 5 (DMCR4/DMCR5) control the DRAM interfaces of areas 4
and 5. These registers are valid only when the DRME bit is 1 in AMD4/AMD5.
■ DRAM Control Registers 4 and 5 (DMCR4 and DMCR5)
DRAM control registers 4 and 5 (DMCR4 and DMCR5) have the following configuration:
DMCR4
15
Address: 0000 062CH
14
13
12
11
10
9
8
Initial value
Access
00000000B
R/W
0
Initial value
Access
-
0000000-B
R/W
8
Initial value
Access
00000000B
R/W
0
Initial value
Access
-
0000000-B
R/W
PGS3 PGS2 PGS1 PGS0 Q1W Q4W DSAS HYPR
7
6
5
4
3
2
1
PAGE C/W SLFR REFE PAR PERR PEIE
DMCR5
15
Address: 0000 062EH
14
13
12
11
10
9
PGS3 PGS2 PGS1 PGS0 Q1W Q4W DSAS HYPR
7
6
5
4
3
2
1
PAGE C/W SLFR REFE PAR PERR PEIE
Bits 15 to 12: PGS3 to PGS0 (Page Size Select bit)
These bits specify the DRAM page size to be connected.
Table 4.3-1 DRAM Page Sizes to be Connected
ROW Address
PGS3 to
PGS0
Page size
A31 to A16
A15 to A00
Column
address
Access judgment
8-bit bus
16-bit bus
0000
256
A31 to A16
A23 to A08
A31 to A00
A31 to A08
A31 to A09
0001
512
A31 to A16
A24 to A09
A31 to A00
A31 to A09
A31 to A10
0010
1024
A31 to A16
A25 to A10
A31 to A00
A31 to A10
A31 to A11
0011
4096
A31 to A16
A27 to A12
A31 to A00
A31 to A12
A31 to A13
0100
to
1111
reserved
-
-
-
-
-
The bus interface unit judges the row size (page size) from the values of PGS3 to PGS0 and the set bus
width. When page access mode is permitted in the register, high-speed access is executed for access in a
page.
Bit 11: Q1W (Q1 Wait bit)
This bit specifies whether to add another Q1 cycle (RAS level high) for DRAM access automatically.
0: Do not add Q1 cycle (Initial value)
1: Add Q1 cycle
Bit 10: Q4W (Q4 Wait bit)
124
CHAPTER 4 BUS INTERFACE
This bit specifies whether to add another Q4 cycle (RAS level high) for DRAM access automatically.
This bit is valid only when the DSAS bit (bit 9) is 0.
0: Do not add Q4 cycle (Initial value)
1: Add Q4 cycle
Bit 9: DSAS (Double/Single CAS Access Cycle Select bit)
When using high-speed page mode for DRAM access, this bit specifies two CAS access cycles (double
CAS access) or one CAS access cycle (single CAS access).
0: Double CAS access (Initial value)
1: Single CAS access
Bit 8: HYPR (HYPeR Page Mode Enable bit)
This bit is used to connect an external DRAM device supporting hyper page mode.
This bit is valid only when the DSAS bit (bit 9) is 1.
0: Double/single CAS DRAM (Initial value)
1: DRAM supporting hyper page mode
Bit 7: PAGE (PAGe Enable bit)
This bit is used to enable high-speed page mode.
0: Disable high-speed page mode (for random access) (Initial value)
1: Enable high-speed page mode (high-speed page mode for access in the page specified by PGS3 to
PGS0)
Bit 6: C/W (1CAS-2WE/2CAS-1WE Select bit)
This bit specifies the 1CAS-2WE or 2CAS-1WE memory interface for using a 16-bit or wider interface.
0: 1CAS-2WE interface (Initial value)
1: 2CAS-1WE interface
Bit 5: SLFR (SeLF Refresh bit)
Writing 1 into this bit changes DRAM to self-refresh mode.
Regardless of areas 4 and 5, self-refresh mode is activated when 1 is written into this bit in DMCR4 or
DMCR5.
This bit can be read or written at an arbitrary timing. When DRAM self-refresh mode is released,
however, reserve an adequate RAS recovery time.
0: Release self-refresh mode (Initial value)
1: Activate self-refresh mode
Bit 4: REFE (REFresh Enable bit)
This bit controls cyclic refresh of the CAS before RAS (CBR) system.
Regardless of areas 4 and 5, cyclic refresh is enabled when 1 is written into this bit in DMCR4 or
DMCR5 and also to the STR bit in the refresh control register (RFCR).
0: Disable refresh (Initial value)
1: Enable refresh (at the intervals specified by the refresh control register (RFCR))
Bit 3: PAR (PARity Select bit)
This device does not support the parity function.
Writing 1 into this bit has no meaning.
Bit 2: PERR (Parity ERRor bit)
This device does not support the parity function.
Writing 1 into this bit has no meaning.
Bit 1: PEIE (Parity Error Interrupt Enable bit)
125
CHAPTER 4 BUS INTERFACE
This bit is used to specify whether to output an interrupt request in case of a parity error.
This device does not support the parity function.
Always write 0.
■ Combinations of Bus Widths
Table 4.3-2 lists the combinations of bus widths available in areas 4 and 5.
Table 4.3-2 Combinations of Bus Widths Available in Areas 4 and 5
Case
126
Area 4
Area 5
1
Ordinary: 16/8 bits
Ordinary: 16/8 bits
2
Ordinary: 16/8 bits
DRAM: 16 bits (C/W = 0,1)
3
Ordinary: 16/8 bits
DRAM: 8 bits (C/W = 0,1)
4
DRAM: 16 bits (C/W = 0,1)
Ordinary: 16/8 bits
5
DRAM: 16 bits (C/W = 0,1)
DRAM: 16 bits (C/W = 0,1)
6
DRAM: 16 bits (C/W = 0,1)
DRAM: 8 bits (C/W = 0,1)
7
DRAM: 8 bits (C/W = 0,1)
Ordinary: 16/8 bits
8
DRAM: 8 bits (C/W = 0,1)
DRAM: 16 bits (C/W = 0,1)
9
DRAM: 8 bits (C/W = 0,1)
DRAM: 8 bits (C/W = 0,1)
CHAPTER 4 BUS INTERFACE
4.3.8
Refresh Control Register (RFCR)
The refresh control register (RFCR) controls CAS before RAS (CBR) refresh when the
DRAM interface is used.
This register has a 6-bit down counter that operates on 1/32 of the timebase timer
output as the clock source. The reload value is controlled in the register to specify the
refresh interval.
■ Refresh Control Register (RFCR)
The refresh control register (RFCR) has the following register configuration:
RFCR
Address: 0000 0626H
15
14
-
-
7
6
13
12
11
10
9
8
REL5 REL4 REL3 REL2 REL1 REL0
R1W R3W
5
4
3
-
-
-
2
1
0
STR CKS1 CKS0
Initial value
Access
--XXXXXXB
R/W
Initial value
Access
00---000B
R/W
The timebase timer is used to control the oscillation stabilization wait time intervals. This counter operates
on 1/2 of the X0 output when the CHC bit is 1 in the gear control register (GCR) and at the internal PLL
oscillation frequency when the bit is 0. For example, one cycle becomes 20 ns when the CHC bit is 0 and
the PLL oscillation frequency is 50 MHz. Then one cycle of the refresh interval is 20 × 32 = 640 ns.
The timebase timer outputs the refresh count, whether or not the clock doubler is on or off.
Bits 13 to 8: REL5 to REL0 (REfresh Value bits)
These bits are a refresh interval setting register.
The read value from this register indicates the count of the down counter counting refresh cycles.
The DRAM in areas 4 and 5 is refreshed simultaneously at the interval read from this bit.
Bit 7: R1W (Refresh 1 Wait)
This bit extends the first refresh cycle (R1) by one cycle.
0: Not wait (Initial value)
1: Wait
Bit 6: R3W (Refresh 3 Wait)
This bit extends the third refresh cycle (R3) by one cycle.
0: Not wait (Initial value)
1: Wait
Bit 2: STR (STaRT bit)
This bit starts or stops the down counter.
0: Stop (Initial value)
1: Start
When this bit is set, the REL value is loaded to the down counter at the same time.
CBR refresh starts when the REFE and STR bits in DMCR are set to 1.
127
CHAPTER 4 BUS INTERFACE
Bits 1 and 0: CKS1, CKS0 (Clock Select)
These bits are used to select a clock source for the down counter. The down counter uses 1/32 of the
timer base output φ as the clock.
128
CKS1
CKS0
0
0
1
1
0
1
0
1
Source clock
φ (Initial value)
φ/8
reserved
reserved
Maximum number of clock signals
26 (REL5-0:6bit) × 32 (1/32 division) = 2048
26(REL5-0:6bit) × 32 (1/32 division) × 8 = 16384
CHAPTER 4 BUS INTERFACE
4.3.9
External Pin Control Register 0 (EPCR0)
External pin control register 0 (EPCR0) controls signal output.
When output is enabled, this register outputs a desired timing signal in each bus mode.
When input is enabled, this register accepts an external input signal.
If both output and input are disabled, the corresponding pin can be used as an I/O port.
■ External Pin Control Register 0 (EPCR0)
External pin control register 0 (EPCR0) has the following register configuration:
EPCR0
Address: 0000 0628H
15
14
13
12
-
-
-
-
7
6
5
4
-
11
10
9
8
WRE RDXE RDYE BRE
3
2
1
0
CKE COE5 COE4 COE3 COE2 COE1 COE0
Initial value Access
----1100B
W
Initial value Access
-1111111B
W
Bit 11: WRE (WRite pulse output bit)
This bit controls the output of write pulses WR0X and WR1X.
Reset enables the output.
0: Disable output
1: Enable output (Initial value)
Since this product does not provide I/O port control over the WR0X and WR1X pins using the WRE bit,
always write 1 into this bit.
Even when 1 is written into this bit, the corresponding pin can be used as an I/O port of the width set by
AMD.
(For example, WR1X is not output in 8-bit mode and the corresponding pin can be used as an I/O port.)
Bit 10: RDXE (ReaDX pulse output Enable bit)
This bit controls the output of read pulse RDX.
Reset enables the output.
0: Disable output (Do not set)
1: Enable output (Initial value)
Since this product does not provide I/O port control over the RDX pin using the RDX bit, always write 1
into this bit.
Bit 9: RDYE (ReaDY Input Enable bit)
This bit controls RDY input as follows.
Reset disables the input.
0: Disable RDY input (Initial value)
1: Enable RDY input
129
CHAPTER 4 BUS INTERFACE
Bit 8: BRE (Bus Request Enable bit)
This bit controls BRQ input and BGRNTX output as follows.
Reset disables BRQ input and BGRNTX output.
0: Disable BRQ input and BGRNTX output (corresponding pin serving as an I/O port) (Initial value)
1: Enable BRQ input and BGRNTX output
Bit 6: CKE (ClocK Output Enable bit)
This bit controls external bus operating clock (CLK) output.
0: Disable output
1: Enable output (Initial value)
Reset initializes this bit to 1 to enable the CLK output.
Bit 5: COE5 (Chip select Output Enable 5)
This bit controls CS5X output. Reset enables the output.
0: Disable output
1: Enable output (Initial value)
Bit 4: COE4 (Chip select Output Enable 4)
This bit controls CS4X output. Reset enables the output.
0: Disable output
1: Enable output (Initial value)
Bit 3: COE3 (Chip select Output Enable 3)
This bit controls CS3X output. Reset enables the output.
0: Disable output
1: Enable output (Initial value)
Bit 2: COE2 (Chip select Output Enable 2)
This bit controls CS2X output. Reset enables the output.
0: Disable output
1: Enable output (Initial value)
Bit 1: COE1 (Chip select Output Enable 1)
This bit controls CS1X output. Reset enables the output.
0: Disable output
1: Enable output (Initial value)
Bit 0: COE0 (Chip select Output Enable 0)
This bit controls CS0X output. Reset enables the output.
0: Disable output (Do not set)
1: Enable output (Initial value)
Since this product does not provide I/O port control over the CS0X pin using the COE0 bit, always write
1 into this bit.
130
CHAPTER 4 BUS INTERFACE
4.3.10
External Pin Control Register 1 (EPCR1)
External pin control register 1 (EPCR1) controls address signal output.
■ External Pin Control Register 1 (EPCR1)
External pin control register 1 (EPCR1) has the following register configuration:
EPCR1
7
6
5
4
3
2
1
0
Initial value Access
Address: 0000 062BH AE23 AE22 AE21 AE20 AE19 AE18 AE17 AE16 11111111B
W
Bits 7: AE23 (Address output Enable 23)
AE23 controls the output of address 23.
When output is disabled, this pin can be used as an I/O port.
0: Disable output
1: Enable output (initial value)
AE23 also controls the output of address 24 to the A24 pin.
Bits 6 to 0: AE22 to AE16 (Address output Enable)
These bits control the output of corresponding addresses.
When output is disabled, the corresponding pin can be used as an I/O port.
0: Disable output
1: Enable output (Initial value)
Reset initializes these bits to FFH.
131
CHAPTER 4 BUS INTERFACE
4.3.11
DRAM Signal Control Register (DSCR)
DRAM signal control register (DSCR) controls DRAM control signal output.
When output is disabled, the corresponding pin can be used as an I/O port.
■ DRAM Signal Control Register (DSCR)
DRAM signal control register (DSCR) has the following register configuration:
DSCR
7
Address: 0000 0625H
6
5
4
3
2
0
Initial value Access
DW1E DW0E C1HE C1LE C0HE C0LE RS1E RS0E 00000000B
Bit 7: DW1E
This bit controls DW1X output. Reset disables the output.
0: Disable output (Initial value)
1: Enable output
Bit 6: DW0E
This bit controls DW0X output. Reset disables the output.
0: Disable output (Initial value)
1: Enable output
Bit 5: C1HE
This bit controls CS1H output. Reset disables the output.
0: Disable output (Initial value)
1: Enable output
Bit 4: C1LE
This bit controls CS1L output. Reset disables the output.
0: Disable output (Initial value)
1: Enable output
Bit 3: C0HE
This bit controls CS0H output. Reset disables the output.
0: Disable output (Initial value)
1: Enable output
Bit 2: C0LE
This bit controls CS0L output. Reset disables the output.
0: Disable output (Initial value)
1: Enable output
Bit 1: RS1E
This bit controls RAS1 output. Reset disables the output.
0: Disable output (Initial value)
1: Enable output
Bit 0: RS0E
This bit controls RAS0 output. Reset disables the output.
0: Disable output (Initial value)
1: Enable output
132
1
W
CHAPTER 4 BUS INTERFACE
4.3.12
Little Endian Register (LER)
MB91121 always make bus access with all areas as big endians. However, one of areas
1 to 5 can be set as a little endian area in the little endian register (LER).
This setting is supported in all bus modes for ordinary, time-division, and DRAM
interfaces modes. However, area 0 cannot be set as a little endian area.
The LER register can only be written once after the reset.
■ Little Endian Register (LER)
Little endian register (LER) has the following register configuration:
LER
Address: 0000 07FEH
7
6
5
4
3
2
1
0
Initial value
Access
-
-
-
-
-
LE2
LE1
LE0
-----000B
W
Bits 2 to 0: LE2 to LE0
Table 4.3-3 shows the settings of little endian modes by the combinations of bits LE2 to LE0.
Table 4.3-3 Mode Settings by the Combinations of Bits LE2 to LE0
LE2
LE1
LE0
Mode
0
0
0
Initial value after reset
No little endian area
0
0
1
Area 1: Little endian
Areas 0 and 2 to 5: Big endian
0
1
0
Area 2: Little endian
Areas 0, 1, and 3 to 5: Big endian
0
1
1
Area 3: Little endian
Areas 0 to 2, 4 and 5: Big endian
1
0
0
Area 4: Little endian
Areas 0 to 3 and 5: Big endian
1
0
1
Area 5: Little endian
Areas 0 to 4: Big endian
133
CHAPTER 4 BUS INTERFACE
4.4
Bus Operations
This section explains the following basics about bus operations:
• Relationship between data bus width and control signal
• Big-endian bus access
• Little-endian bus access
• Comparison of external access
• DRAM connection
■ Relationships between Data Bus Widths and Control Signals
The relationships between data bus widths and control signals are explained in terms of the following
interfaces:
• Ordinary bus interface
• DRAM interface
■ Big-endian Bus Access
The following items are explained with regard to external access.
• Data format
• Data bus width
• External bus access
• Example of external device connection
■ Little-endian Bus Access
The following items are explained with regard to external access.
• Differences between little endian and big endian
• Data format
• Data bus width
• Example of external device connection
■ Comparison of External Access
By comparing external big-endian and little-endian accesses, word access, half-word access, and byte
access are explained from the viewpoint of bus width.
■ DRAM Connection
The basics of DRAM connection are explained:
• DRAM control pin
• Row address and column address
• Example of DRAM device connection
134
CHAPTER 4 BUS INTERFACE
4.4.1
Relationships between Data Bus Widths and Control
Signals
The WR0X, WR1X, CS0H, CS1L, DW0X, and DW1X control signals always have one-toone correspondence with the data bus byte positions, regardless of the endian (big or
little) and data bus width.
■ Relationships between Data Bus Widths and Control Signals
The data bus byte positions depending on the data bus widths set in each bus mode and their corresponding
control signals are shown here.
● Ordinary interface
Figure 4.4-1 Data Bus Widths and Control Signals in Ordinary Bus Interface Mode
8-bit bus
16-bit bus
Data bus
D31
Control signal
Data bus
D31
Control signal
WR0X
WR0X
D24
WR1X
D16
(D23 to D16: Not used)
● DRAM interface
Figure 4.4-2 Data Bus Widths and Control Signals in DRAM Interface Mode
8-bit bus
16-bit bus
Data bus
D31
Control signal
Data bus
D31
CASL WEL
Control signal
CAS WE
D24
CASH WEH
D16
(D23 to D16: Not used)
135
CHAPTER 4 BUS INTERFACE
Table 4.4-1 summarizes the above relationships.
Table 4.4-1 Relationships between Data Bus Widths and Control Signals
Bus width
Data bus
136
16-bit bus
8-bit bus
WR
2CAS/1WE
1CAS/2WE
WR
2CAS/1WE
1CAS/2WE
D31-D24
WR0X
CASL
WEH
WR0X
CAS
WE
D23-D16
WR1X
CASH
WEH
-
-
-
CHAPTER 4 BUS INTERFACE
4.4.2
Big-endian Bus Access
A big endian is used for external bus access to an area where the little endian register
(LER) is not set.
The FR family usually uses a big endian.
■ Data Format
The following figures show the relationships between the internal register and external data bus by access
types.
● Word access (LD and ST instructions)
Figure 4.4-3 Relationship between the Internal Register and External Data Bus in Word Access
Internal
register
External
bus
D31
D31
AA
AA
CC
BB
BB
DD
D23
D23
D15
CC
D07
DD
● Half-word access (LDUH and STH instructions)
Figure 4.4-4 Relationship between the Internal Register and External Data Bus in Half-word Access
Internal
register
D31
D23
D15
D07
External
bus
D31
AA
BB
D23
AA
BB
137
CHAPTER 4 BUS INTERFACE
● Byte access (LDUB and STB instructions)
Figure 4.4-5 Relationship between the Internal Register and External Data Bus in Byte Access
(a) Lower output address: 0
(b) Lower output address: 1
Internal
External
Internal
External
register
bus
register
bus
D31 D31
D31
D31
AA
D23
D23
D23
D23
AA
D15
D15
D07
D07
AA
AA
■ Data Bus Width
The following figures show the relationships between the internal register and external data bus by bus
widths.
● 16-bit bus
Figure 4.4-6 Relationship between the Internal Register and External Data Bus for 16-bit Bus
Internal
register
External
bus
Lower output address
"00" "10"
D31
D31
AA
Read/Write
AA
CC
BB
DD
D23
D23
BB
D15
CC
D07
DD
● 8-bit bus
Figure 4.4-7 Relationship between the Internal Register and External Data Bus for 8-bit Bus
Internal
External
register
bus
Lower output address
"00" "01" "10" "11"
Read/Write
D31
D31
AA
AA BB CC DD
D23
BB
D15
CC
D07
DD
138
CHAPTER 4 BUS INTERFACE
■ External Bus Access
Figure 4.4-8 and Figure 4.4-9 show the external bus access formats by bus widths (16 and 8 bits) and
access types (word, half-word, and byte).
The following items are also explained:
• Access byte position
• Program address and output address
• Bus access count
MB91121 does not detect misalignment. Therefore, even when the low-order two bits of an output address
are set to 00, 01, 10, or 11 by program, they always become 00 for word access.
For half-word access, the bits become 00 when set to 00 or 01 and become 10 when set to 10 or 11.
● 16-bit bus
Figure 4.4-8 External Bus Access by 16-bit Bus
(A)Word access
(a) PA1/PA0= 00
(b) PA1/PA0= 01
1) Output A1/A0= 00
2) Output A1/A0= 10
MSB
(c) PA1/PA0= 10
1) Output A1/A0= 00
2) Output A1/A0= 10
(d) PA1/PA0= 11
1) Output A1/A0= 00
2) Output A1/A0= 10
1) Output A1/A0= 00
2) Output A1/A0= 10
LSB
1)
00
01
1)
00
01
1)
00
01
1)
00
01
2)
10
11
2)
10
11
2)
10
11
2)
10
11
16bit
(B)Half-word access
(a) PA1/PA0= 00
(b) PA1/PA0= 01
1) Output A1/A0= 00
1)
00
01
10
11
(c) PA1/PA0= 10
1) Output A1/A0= 00
1)
00
01
10
11
(d) PA1/PA0= 11
1) Output A1/A0= 10
1)
00
01
10
11
1) Output A1/A0= 10
1)
00
01
10
11
(C)Byte access
(a) PA1/PA0= 00
(b) PA1/PA0= 01
1) Output A1/A0= 00
1)
00
01
10
11
(c) PA1/PA0= 10
1) Output A1/A0= 01
1)
00
01
10
11
(d) PA1/PA0= 11
1) Output A1/A0= 10
1)
00
01
10
11
1) Output A1/A0= 11
1)
00
01
10
11
PA1/PA0
:Lower 2 bits of program-specified address
Output A1/A0 :Lower 2 bits of output address
:First byte position of output address
:Data byte position to be accessed
:Bus access count
1), 2)
139
CHAPTER 4 BUS INTERFACE
● 8-bit bus
Figure 4.4-9 External Bus Access by 8-bit Bus
(A)Word access
(a) PA1/PA0= 00
1) Output A1/A0= 00
2) Output A1/A0= 01
3) Output A1/A0= 10
4) Output A1/A0= 11
MSB LSB
(b) PA1/PA0= 01
1) Output A1/A0= 00
2) Output A1/A0= 01
3) Output A1/A0= 10
4) Output A1/A0= 11
(c) PA1/PA0= 10
1) Output A1/A0= 00
2) Output A1/A0= 01
3) Output A1/A0= 10
4) Output A1/A0= 11
(d) PA1/PA0= 11
1) Output A1/A0= 00
2) Output A1/A0= 01
3) Output A1/A0= 10
4) Output A1/A0= 11
1)
00
1)
00
1)
00
1)
00
2)
01
2)
01
2)
01
2)
01
3)
10
3)
10
3)
10
3)
10
4)
11
4)
11
4)
11
4)
11
8bit
(B)Half-word access
(a) PA1/PA0= 00
1) Output A1/A0= 00
2) Output A1/A0= 01
(c) PA1/PA0= 10
1) Output A1/A0= 10
2) Output A1/A0= 11
(d) PA1/PA0= 11
1) Output A1/A0= 10
2) Output A1/A0= 11
1)
00
1)
00
00
00
2)
01
2)
01
01
01
10
10
1)
10
1)
10
11
11
2)
11
2)
11
(C)Byte access
(a) PA1/PA0= 00
1) Output A1/A0= 00
1)
PA1/PA0
:
Output A1/A0 :
:
:
1) - 4)
(b) PA1/PA0= 01
1) Output A1/A0= 01
00
01
140
(b) PA1/PA0= 01
1) Output A1/A0= 00
2) Output A1/A0= 01
1)
(c) PA1/PA0= 10
1) Output A1/A0= 10
(d) PA1/PA0= 11
1) Output A1/A0= 11
00
00
00
01
01
01
10
10
10
10
11
11
Lower 2 bits of program-specified address
Lower 2 bits of output address
First byte position of output address
Data byte position to be accessed
1)
11
1)
11
CHAPTER 4 BUS INTERFACE
■ Example of External Device Connection
Figure 4.4-10 shows an example of connection between MB91121 and an external device.
Figure 4.4-10 Example of Connection between MB91121 and External Device
MB91121
WW
D31 R
D23 R
to 1
to 0
D24 X
D16 X
0
1
D15 D08 D07 D00
16-bit device*
X
D07 D00
8-bit device*
(0 and 1 indicate the lower address bit of MSB and LSB respectively. X means that the lower address bit may be 0 or 1.)
* : For a 16/8-bit device, use the MSB-side data bus of the MB91121.
141
CHAPTER 4 BUS INTERFACE
4.4.3
Little-endian Bus Access
A little endian is used for external bus access to an area where the little endian register
(LER) is not set.
Since little endian access by MB91121 uses bus access for a big endian, the output
address order and control signal output are the same as for access using a big endian.
For data output, the data bus byte positions for a big endian are swapped according to
the bus width.
Note that the big endian and little endian areas need to be distinguished physically for
connection.
■ Differences between Little and Big Endians
The differences between little and big endians are listed below.
The output address order is not different between little and big endians.
The data bus control signals for 16/8-bit bus are not different between little and big endians.
● Word Access
The MSB data at address 00B of a big endian corresponds to the LSB data in a little endian.
For word access, the positions of four bytes in a word are all reversed.
00B → 11B, 01B → 10B, 10B → 01B, 11B → 00B
● Half-word access
The MSB data at address 00B of a big endian corresponds to the LSB data in a little endian.
For half-word access, the positions of two bytes in a half word are reversed.
0 → 1, 1 → 0
● Byte access
There is no difference in the way of byte access between little and big endians.
142
CHAPTER 4 BUS INTERFACE
■ Data Format
The following figures show the relationships between the internal register and external data bus by access
types.
● Word access (LD and ST instructions)
Figure 4.4-11 Relationship between the Internal Register and External Data Bus in Word Access
Internal
register
External
bus
D31
D31
AA
DD BB
BB
CC AA
D23
D23
D15
CC
D07
DD
● Half-word access (LDUH and STH instructions)
Figure 4.4-12 Relationship between the Internal Register and External Data Bus in Half-Word Access
Internal
register
External
bus
D31
D31
BB
D23
D23
AA
D15
AA
D07
BB
● Byte access (LDUB and STB instructions)
Figure 4.4-13 Relationship between the Internal Register and External Data Bus in Byte Access
(a) Lower output address: 0
Internal
External
register
bus
D31
(b) Lower output address: 1
Internal
External
register
bus
D31
D31
D23
D23
D31
AA
D23
D23
AA
D15
D15
D07
D07
AA
AA
143
CHAPTER 4 BUS INTERFACE
■ Data Bus Width
The following figures show the relationships between the internal register and external data bus by bus
widths.
● 16-bit bus
Figure 4.4-14 Relationship between the Internal Register and External Data Bus for 16-Bit Bus
Internal
External
register
bus
Lower output address
“00“ “10“
D31
D31
AA
read/Write
DD BB
D23
D23
BB
CC AA
D15
CC
D07
DD
● 8-bit bus
Figure 4.4-15 Relationship between the Internal Register and External Data Bus for 8-Bit Bus
Internal
register
Lower output address
External
bus
“00“ “01“ “10“ “11“
read/Write
D31
AA
D23
BB
D15
CC
D07
DD
144
D31
DD CC BB
AA
CHAPTER 4 BUS INTERFACE
■ Examples of External Device Connection
Figure 4.4-16 and Figure 4.4-17 show examples of connection between MB91121 and an external device.
● 16-bit bus
Figure 4.4-16 Example of Connection between MB91121 and External Device (16-bit Bus)
CS0 to
CS5
MB91121
W
D31 R
to 0
D24 X
W
D23 R
to 1
D16 X
Big endian area
WR0X
Little endian area
WR1X
WR1X
D31 to D24 D23 to D16
LSB
MSB
D15 D08 D07
WR0X
D23 to D16 D31 to D24
D00
MSB
LSB
D15
D08 D07
D00
● 8-bit bus
Figure 4.4-17 Example of Connection between MB91121 and External Device (8-bit Bus)
MB91121
W
D31 R
to 0
D24 X
W
D23 R
to 1
D16 X
Big endian area
D07
D00
CS0 to
CS5
Little endian area
D07
D00
145
CHAPTER 4 BUS INTERFACE
4.4.4
Comparison of External Accesses in Big and Little
Endian Modes
External access in big and little endian modes are compared in word access, half-word
access, and byte access for the bus width.
■ Word Access
Bus width
16-bit bus
Big endian mode
Internal
External pin
register
address: '0' '2'
D31
D31
AA
BB
Little endian mode
Control pin
Internal
register
address: '0'
D31
AA CC
WR0X CASL WEL
AA
BB DD
WR1X CASH WEH
BB
DD BB
WR0X CASL WEL
CC AA
WR1X CASH WEH
CC
DD
DD
D00
1)
Internal
register
D00
2)
External pin
address: '0' '1' '2' '3'
D31
AA
AA BB CC DD
1)
Internal
register
Control pin
2)
External pin
BB
address: '0' '1' '2' '3'
D31
AA
DD CC BB AA
D24
BB
CC
CC
D31
WR0X CAS WE
D24
DD
DD
D00
D00
1) 2) 3) 4)
146
'2'
D16
CC
D31
Control pin
D31
D16
8-bit bus
External pin
1) 2) 3) 4)
Control pin
WR0X CAS WE
CHAPTER 4 BUS INTERFACE
■ Half-word Access
Bus width
Big endian mode
Little endian mode
16-bit bus
Internal
External pin
register
address: '0'
D31
D31
AA
BB
Control pin
WR0X CASL WEL
Internal
register
D31
External pin
Control pin
address: '0'
D31
BB
WR0X CAS0 WEL
AA
WR1X CAS1 WEH
WR1X CASH WEH
D16
D16
AA
AA
BB
BB
D00
D00
1)
1)
Internal
register
D31
External pin
Control pin
address: '2'
D31
CC
WR0X CASL WEL
DD
WR1X CASH WEH
Internal
register
D31
External pin
Control pin
address: '2'
D31
DD
WR0X CASL WEL
CC
WR1X CASH WEH
D16
D16
CC
CC
DD
DD
D00
D00
1)
1)
8-bit bus
Internal
register
External pin
address: '0' '1'
D31
AA BB
D24
D31
Control pin
Internal
register
D31
WR0X CAS WE
AA
address: '0' '1'
D31
BB AA
D24
D00
D00
1) 2)
1) 2)
Internal
register
External pin
address: '2' '3'
D31
CC DD
D24
Internal
register
Control pin
D31
WR0X CAS WE
External pin
address: '2' '3'
D31
DD CC
D24
Control pin
WR0X CAS WE
CC
CC
DD
DD
D00
WR0X CAS WE
BB
D00
D31
Control pin
AA
BB
D00
External pin
D00
D00
1) 2)
D00
1) 2)
147
CHAPTER 4 BUS INTERFACE
■ Byte Access
Bus width
Big endian mode
Little endian mode
16-bit bus
Internal
External pin
register
address: '0'
D31
D31
AA
Internal
register
Control pin
D31
WR0XCASL WEL
address: '0'
D31
AA
D16
AA
AA
Internal
register
External pin
1)
Control pin
address: '1'
D31
BB
Internal
register
D31
External pin
Control pin
address: '1'
D31
BB
WR1XCASH WEH
WR1XCASH WEH
D16
D16
BB
BB
D00
D00
1)
1)
Internal
register
External pin
address: '2'
D31
CC
Control pin
WR0XCASL WEL
Internal
External pin
register
address: '2'
D31
D31
CC
Control pin
WR0XCASL WEL
D16
D16
CC
CC
D00
D00
1)
1)
Internal
External pin
register
address: '3'
D31
D31
DD
Control pin
Internal
register
D31
External pin
WR1XCASH WEH
DD
D16
DD
DD
D00
D00
1)
Control pin
address: '3'
D31
D16
148
WR0XCASL WEL
D00
1)
D31
Control pin
D16
D00
D31
External pin
1)
WR1X CASH WEH
CHAPTER 4 BUS INTERFACE
Bus width
Big endian mode
Little endian mode
8-bit bus
Internal
register
D31
External pin
address: '0'
D31
AA
D24
Control pin
Internal
register
D31
WR0X CAS WE
AA
address: '0'
D31
AA
D24
WR0X CAS WE
D00
1)
Internal
register
External pin
address: '1'
D31
BB
D24
1)
Control pin
Internal
register
D31
WR0X CAS WE
BB
External pin
address: '1'
D31
BB
D24
Control pin
WR0X CAS WE
BB
D00
D00
1)
Internal
External pin
register
address: '2'
D31
D31
CC
D24
1)
Control pin
Internal
register
D31
WR0X CAS WE
CC
address: '2'
D31
CC
D24
Control pin
WR0X CAS WE
D00
1)
Internal
register
External pin
CC
D00
D31
Control pin
AA
D00
D31
External pin
External pin
address: '3'
D31
DD
D24
1)
Control pin
Internal
register
D31
WR0X CAS WE
DD
External pin
address: '3'
D31
DD
D24
Control pin
WR0X CAS WE
DD
D00
D00
1)
1)
149
CHAPTER 4 BUS INTERFACE
4.4.5
DRAM Connection
This section explains the basics about DRAM connection to MB91121 with some
examples of connection.
■ DRAM Control Pins
Table 4.4-2 lists DRAM control pin functions and data bus areas used.
Table 4.4-2 DRAM Control Pin Functions and Data Bus Areas
Data bus in 16-bit mode
Pin name
150
Data bus in 8bit mode
2CAS/1WR
mode
1CAS/2WR
mode
RAS0
Area 4 RAS
Area 4 RAS
Area 4 RAS
RAS1
Area 5 RAS
Area 5 RAS
Area 5 RAS
CS0L
Area 4 CASL
Area 4 CAS
Area 4 CAS
CS0H
Area 4 CASH
Area 4 WEL
Area 4 CAS
CS1L
Area 5 CASL
Area 5 CAS
Area 5 CAS
CS1H
Area 5 CASH
Area 5 WEL
Area 5 CAS
DW0X
Area 4 WE
Area 4 WEH
Area 4 WE
DW1X
Area 5 WE
Area 5 WEH
Area 5 WE
Remarks
• Signal level and lower one address bit (A0)
when the data bus is in 16-bit mode
• L: 0
• H: 1
CASL: CAS corresponding to area of A0 = 0
CASH: CAS corresponding to area of A0 = 1
WEL: WE corresponding to area of A0 = 0
WEH: WE corresponding to area of A0 = 1
CHAPTER 4 BUS INTERFACE
■ Row Address and Column Address
The page size selection bits (PG3 to PG0) in DRAM control registers 4 and 5 (DMCR4 and DMCR5)
determine address generation for the DRAM interface. When high-speed page mode is used, PG3 to PG0
and the data bus width determine whether access is in a page.
Table 4.4-3 Page Size Selection Bits
Row address
PGS3 to
PGS0
Page size
0000B
A31-A16
A15-A00
256
A31 to A16
A23 to A08
0001B
512
A31 to A16
0010B
1024
0011B
0100B
to
1111B
Column
address
Access judgment
8-bit bus
16-bit bus
A31 to A00
A31 to A08
A31 to A09
A24 to A09
A31 to A00
A31 to A09
A31 to A10
A31 to A16
A25 to A10
A31 to A00
A31 to A10
A31 to A11
4096
A31 to A16
A27 to A12
A31 to A00
A31 to A12
A31 to A13
reserved
-
-
-
-
-
For DRAM connection, the output addresses of this LSI should be shifted according to the bus width.
DRAM connection (8 bits, 256 pages) is explained here using 8-bit and 16-bit buses. When a 16-bit bus is
used, the lower one bit of each address output is not connected.
151
CHAPTER 4 BUS INTERFACE
● 8-bit data bus (one DRAM device)
Figure 4.4-18 Connection of MB91121 and One 8-bit Output DRAM Device
This LSI
COLUMN Address A07 A06 A05 A04 A03 A02 A01 A00
ROW Address
A15 A14 A13 A12 A11 A10 A09 A08
External pin
A07 A06 A05 A04 A03 A02 A01 A00
DRAM (1)
A07 A06 A05 A04 A03 A02 A01 A00
D07 to D00
8
RAS,CAS,WE
D31 to D24
● 16-bit data bus (two DRAM devices)
Figure 4.4-19 Connection of MB91121 and Two 8-bit Output DRAM Devices
This LSI
Not connected
COLUMN Address A08 A07 A06 A05 A04 A03 A02 A01 A00
ROW Address
A16 A15 A14 A13 A12 A11 A10 A09 A08
External pin
A08 A07 A06 A05 A04 A03 A02 A01 A00
A07 A06 A05 A04 A03 A02 A01 A00
DRAM (2)
8
D07 to D00
A07 A06 A05 A04 A03 A02 A01 A00
8
152
D07 to D00
RAS,CASL,WE (RAS,CAS,WEL)
D31 to D24
RAS,CASH,WE (RAS,CAS,WEH)
D23 to D16
( ): 1CAS/2WE
CHAPTER 4 BUS INTERFACE
■ Example of DRAM Device Connection
Figure 4.4-20 shows an example of DRAM device connection under the following conditions:
• DRAM: 2CAS/1WE, 512 page size, 16 bits
• Bus width: 16 bits
• Number of banks: 2 (areas 4 and 5)
Figure 4.4-20 DRAM Device Connection to MB91121
This LSI
Area 4
DRAM
(Area 4 RAS) RAS0
RAS
(Area 4 CASL) CSOL
UCAS
(Area 4 CASH) CS0H
LCAS
(Area 4 WE) DW0X
WE
(Area 5 RAS) RAS1
OE
(Area 5 CASL) CS1L
A8 to A0
(Area 5 CASH) CS1H
D16 to D1
(Area 5 WE) DW1X
Area 5
DRAM
RAS
UCAS
LCAS
WE
RDX
(A00 not connected)
A09 to D01
D31 to D16
OE
A8 to A0
D16 to D1
153
CHAPTER 4 BUS INTERFACE
4.5
Bus Timing
This section explains the bus access timings and operations in each mode in terms of
the following items:
• Ordinary bus access
• Wait cycle
• DRAM interface
• DRAM refresh
• External bus request
■ Ordinary Bus Access
In the ordinary bus interface, two clock cycles are the basic bus cycle both for read and write.
This guide refers to the two cycles as BA1 and BA2.
• Basic read cycle
• Basic write cycle
• Read cycle in each mode
• Write cycle in each mode
• Read-write cycle
■ Wait Cycle
The wait cycle can be classified into an automatic wait cycle by the WTC bit in the AMD register and an
external wait cycle using the RDY pin.
Wait cycle mode is to continue the previous cycle. The BA1 cycle is repeated until the wait status is
released.
• Automatic wait cycle
• External wait cycle
■ DRAM Interface
Areas 4 and 5 can be used as DRAM spaces. The DRME bit in AMD4 or AMD5 is set to 1 for operation
control with DMCR4 or DMCR5.
Depending on CAS output, the DRAM interface operates in the following three modes:
• Double CAS access (DSAS: 0, HYPR: 0): Ordinary DRAM interface in this guide
• Single CAS access (DSAS: 0, HYPR: 0): Single DRAM interface in this guide
• DRAM with hyper page mode (DSAS: 1, HYPR: 1): Hyper DRAM interface in this guide
DRAM of 1CAS/2WE or 2CAS/1WE can be selected by setting the C/W bit in DMCR4 and DMCR5.
The page size specified by bits PG3 to PG0 in DMCR and the bus width specified by bits BW1 and BW0 in
AMD4 or AMD5 determine the row and column addresses.
154
CHAPTER 4 BUS INTERFACE
● Ordinary DRAM interface
The ordinary DRAM interface is a bus interface mode where CAS access is made in two clock cycles. For
this mode, set both the DSAS and HYPR bits to 0 in DMCR4 or DMCR5. In this mode, five clock cycles
are the basic cycle both for read and write. The cycles are expressed as Q1 to Q5 in this guide.
High-speed mode can be set using the PAGE bit in DMCR4 or DMCR5.
In this mode, the column address and CAS control ensure high-speed memory access in the same page
space where row addresses match. To use this mode, the PAGE bit in DMCR4 or DMCR5 should be set to
1.
Bits PGS3 to PGS1 in DMCR4 or DMCR5 are checked to see whether access is within the same page.
Access in high-speed page mode starts when ordinary access by Q1 to Q5 is finished. When high-speed
page mode starts, the cycles of Q4 and Q5 are repeated. Once this mode has been set, RAS remains low
until access outside a page or a refresh cycle is generated.
The Q1 and Q4 wait cycles can be set even in high-speed page mode. When high-speed page mode starts,
the cycles of Q4, Q4W, and Q5 are repeated.
• Read cycle of ordinary DRAM interface
• Write cycle of ordinary DRAM interface
• Ordinary DRAM read cycle
• Ordinary DRAM write cycle
• Automatic wait cycle in ordinary DRAM interface
• DRAM interface in high-speed page mode
● Single DRAM interface
The single DRAM interface is a bus interface mode where CAS access is made in one clock cycle. For this
mode, set the DSAS bit to 1 and the HYPR bit to 0 in DMCR4 or DMCR5. When using this mode, set the
PAGE bit to 1 in DMCR4 or DMCR5 to activate high-speed page mode.
The single DRAM interface starts up at the rise of Q1 to Q3 cycles like the ordinary DRAM interface.
Once the Q4 cycle has started, one-cycle CAS control is executed in one cycle for read or write. In this
guide, the Q4 cycle is expressed as Q4SR for read and Q4SW for write.
The page size, 1CAS/2WE or 2CAS/1WE setting, and Q1-cycle wait are the same those for the ordinary
DRAM interface.
• Read cycle of single DRAM interface
• Write cycle of single DRAM interface
• Single DRAM interface
155
CHAPTER 4 BUS INTERFACE
● Hyper DRAM interface
The hyper DRAM interface is a bus interface mode where CAS access is made in one clock cycle. In this
mode, data is fetched at a read cycle to set the next address one step earlier for high-speed DRAM access.
For this mode, set both the DSAS and HYPR bits to 1 in DMCR4 or DMCR5. When using this mode, set
the PAGE bit to 1 in DMCR4 or DMCR5 to activate high-speed page mode.
The hyper DRAM interface starts up at the rise of Q1 to Q3 cycles like the ordinary DRAM interface. Once
the Q4 cycle has started, one-cycle CAS control is executed in one cycle for read or write. In this guide, the
Q4 cycle is expressed as Q4HR for read and Q4HW for write.
The page size, 1CAS/2WE or 2CAS/1WE setting, and Q1-cycle wait are the same those for the ordinary
DRAM interface.
• Read cycle of hyper DRAM interface
• Write cycle of hyper DRAM interface
• Hyper DRAM interface
■ DRAM Refresh
• CAS before RAS (CBR) refresh
• Automatic wait cycle for CBR refresh
• Self-refresh
■ External Bus Request
• Release of bus privilege
• Acquisition of bus privilege
156
CHAPTER 4 BUS INTERFACE
4.5.1
Basic Read Cycle
This section explains the basic read cycle timings.
■ Basic Read Cycle Timings
● Bus width: 16 bits, access: word access to CS0 area
Figure 4.5-1 Basic Read Cycle Timings
BA1
BA2
BA1
BA2
CLK
# in A23 to A00 represents the lower two address bits.
A24 to D00
D31 to D24
D23 to D16
#0
#2
#0
#1
#2
#3
# in D31 to D16 represents the byte address of read data.31-1
indicates a read data fetch timing.
RDX
WR0X
WR1X
CS0X
CS1X
CS2X
CS3X
CS4X
CS5X
(DACK0)
(EOP0)
(DACK0) and (EOP0) represent DMAC bus cycles.
Half-word access
with upper data
address
Half-word access
with lower data
address
[Operations]
• The CLK outputs external bus operation clock signals.
When the clock doubler is off, the operation clock ratio of CPU to external bus is 1:1. The CLK outputs
a clock signal of the same frequency as the CPU. When the clock doubler is on, the operation clock ratio
of CPU to external bus becomes 1:1/2 and the CLK outputs a signal of half the CPU frequency.
When a gear is applied, the CLK frequency goes down according to the CLK frequency.
• A24 to A00 (addresses 24 to 00) output the address at the first byte position of word, half-word, or byte
access in a read cycle from the start of a bus cycle (BA1). The 16-bit word access in the above example
outputs the data storage address (lower two bits: 0) of the upper 16 bits at the first bus cycle and that of
the lower 16 bits (lower two bits: 2) at the second bus cycle.
• D31 to D16 (data 31 to 16) represent read data from an external memory or I/O device.
Regardless of the data bus width or access type (word, half-word, or byte), the read data is all fetched at
the rise of RDX and its validity is confirmed inside the chip.
• RDX is a read strobe signal for an external data bus. This signal is asserted at the fall of BA1 and
negated at the fall of BA2.
• In a read cycle, WR0X and WR1X are negated.
• The CS0X to CS5X (Area Chip Select) signal output is asserted at the start of a bus cycle (BAI) at the
same timing as A24 to A00. CS0X to CS5X are decoded from address output and change only when the
chip select area set by ASR and AMR changes. One of CS0X to CS5X is always asserted.
• DACK0 to DACK2 and EOP0 to EOP2 are output at DMA external bus cycles. The signal output is
determined by DMAC register setting and the output timing is the same as for RDX.
157
CHAPTER 4 BUS INTERFACE
4.5.2
Basic Write Cycle
This section explains the basic write cycle timings.
■ Basic Write Cycle Timings
● Bus width: 8 bits, access: word access to CS0 area
Figure 4.5-2 Basic Write Cycle Timings
BA1
BA2
BA1
BA2
BA1
BA2
BA1
BA2
CLK
A24 to D00
D31 to D24
D23 to D16
RDX
WR0X
WR1X
CS0X
CS1X
CS2X
CS3X
CS4X
CS5X
(DACK0)
(EOP0)
#0
#0
Byte access with
lower two address
bits = 0
#1
#1
#2
#2
Byte access with Byte access with
lower two address lower two address
bits = 1
bits = 2
#3
#3
Byte access with
lower two address
bits = 3
[Operations]
• A24 to A00 (addresses 24 to 00) output the address at the first byte position of word, half-word, or byte
access in a write cycle from the start of a bus cycle (BA1). The 8-bit word access in the above example
outputs the address (lower address bit: 0) of the first byte, then the addresses of the first byte + 1 (1), the
first byte + 2 (2), and the first byte + 3 (3) sequentially.
• D31 to D16 (data 31 to 16) represent write data to an external memory or I/O device. The write data is
output at the start of a bus cycle (BA1). The signal is set to Hi-Z at the end of a bus cycle (BA2). The 8bit data access in the above example outputs write data to D31 to D24.
• In a write cycle, RDX is negated.
• WR0X and WR1X are write strobe signals for an external data bus. These signals are asserted at the fall
of BA1 and negated at the fall of BA2. D31 to D24 are asserted according to WR0X and the
corresponding bus and D23 to D16 are asserted according to WR1X and the corresponding bus. The 8bit data access in the above example asserts WR0X only.
• If the maximum bus width of areas 0 to 5 is 8 bits (all the set areas are 8 bits wide), D23 to D16 and
WR1X automatically become I/O ports and their signals are set to Hi-Z. In the above example, D23 to
D16 and WR1X are used as I/O ports. Note that D23 to D16 and WR1X cannot be used as I/O ports if
the bus width is set to 16 bits even in one of chip select areas 0 to 5.
158
CHAPTER 4 BUS INTERFACE
Pin
Maximum bus width
D31 to D4
WR0X
D23 to D16
WR1X
16 bits
D31 to D24
WR0X
D23 to D16
WR1X
8 bits
D31 to D24
WR0X
I/O port
• DACK0 to DACK2 and EOP0 to EOP2 are output at DMA external bus cycles. The signal output is
determined by the DMAC register setting and the output timing is the same as for WR0X and WR1X.
159
CHAPTER 4 BUS INTERFACE
4.5.3
Read Cycle in Each Mode
This section shows the read cycle timings in each mode.
■ Read Cycle Timings in Each Mode
● 16-bit bus, half-word access
Figure 4.5-3 Read Cycle Timings 1
BA1
BA2
BA1
BA2
CLK
A24 to A00
D31 to D24
D23 to D16
RDX
#0
#2
#0
#1
#2
#3
● 16-bit bus, byte access
Figure 4.5-4 Read Cycle Timings 2
BA1
BA2
BA1
BA2
BA1
BA2
BA1
BA
CLK
A24 to A00
D31 to D24
D23 to D16
RDX
#0
#1
#0
X
#2
X
#1
#3
#2
X
X
#3
X: Invalid data
● 8-bit bus, word access
Figure 4.5-5 Read Cycle Timings 3
BA1
BA2
BA1
BA2
BA1
BA2
BA1
BA2
CLK
A24 to A00
D31 to D24
D23 to D16
RDX
160
#0
#1
#0
#2
#1
#3
#2
#3
CHAPTER 4 BUS INTERFACE
● 8-bit bus, half-word access
Figure 4.5-6 Read Cycle Timings 4
BA1
BA2
BA1
BA2
BA1
BA2
BA1
BA2
CLK
A24 to A00
D31 to D24
D23 to D16
RDX
#0
#1
#0
#2
#1
#3
#2
#3
● 8-bit bus, byte access
Figure 4.5-7 Read Cycle Timings 5
BA1
BA2
BA1
BA2
BA1
BA2
BA1
BA
CLK
A24 to A00
D31 to D24
D23 to D16
RDX
#0
#1
#0
#2
#1
#3
#2
#3
161
CHAPTER 4 BUS INTERFACE
4.5.4
Write Cycle In Each Mode
This section shows the write cycle timings in each mode.
■ Write Cycle Timings in Each Mode
● 16-bit bus, word access
Figure 4.5-8 Write Cycle Timings 1
BA1
BA2
BA1
BA2
CLK
A24 to A00
D31 to D24
D23 to D16
WR0X
WR1X
#0
#0
#1
#2
#2
#3
● 16-bit bus, half-word access
Figure 4.5-9 Write Cycle Timings 2
BA1
BA2
BA1
BA2
CLK
A24 to A00
D31 to D24
D23 to D16
WR0X
WR1X
#0
#0
#1
#2
#2
#3
● 16-bit bus, byte access
Figure 4.5-10 Write Cycle Timings 3
BA1
BA2
BA1
BA2
BA1
BA2
BA1
CLK
A24 to A00
D31 to D24
D23 to D16
WR0X
WR1X
#0
#0
X
#1
X
#1
#2
#2
X
X: Invalid data
162
#3
X
#3
BA
CHAPTER 4 BUS INTERFACE
● 8-bit bus, half-word access
Figure 4.5-11 Write Cycle Timings 4
BA1
BA2
BA1
BA2
BA1
BA2
BA1
BA2
CLK
A24 to A00
D31 to D24
D23 to D16
WR0X
WR1X
#0
#0
#1
#1
#2
#2
#3
#3
● 8-bit bus, byte access
Figure 4.5-12 Write Cycle Timings 5
BA1
BA2
BA1
BA2
BA1
BA2
BA1
BA
CLK
A24 to A00
D31 to D24
D23 to D16
WR0X
WR1X
#0
#0
#1
#1
#2
#2
#3
#3
163
CHAPTER 4 BUS INTERFACE
4.5.5
Read-write Cycle
This section explains the read-write cycle timings.
■ Read-write Cycle Timings
● CS0 area: 16-bit bus, word read
CS1 area: 8-bit bus, half-word write
Figure 4.5-13 Read-write Cycle Timings
BA1
BA2
BA1
BA2
Idle
BA1
BA2
BA1
BA
Idle
CLK
A24 to A00
D31 to D24
D23 to D16
#0
#2
#0
#1
#2
#3
#0
#0
X
#1
#1
X
RDX
WR0X
WR1X
CS0X
CS1X
Word read cycle
CS0 area
Half-word write cycle
CS1 area
[Operations]
• In the above example, an idle cycle (no bus cycle) is inserted at the switching of a chip select area. If an
idle cycle is inserted during a bus cycle, the address of the previous bus cycle remains output until the next
bus cycle begins. The CS0X to CS5X corresponding to the output address also remains asserted accordingly.
• In the above example, 16-bit and 8-bit buses are mixed.
Since the maximum bus width is 16 bits, D23 to D16 and WR1X do not become I/O ports even in an 8bit access area (CS1 area). D23 to D16 output undefined data and WR1X is negated.
164
CHAPTER 4 BUS INTERFACE
4.5.6
Automatic Wait Cycle
This section explains the automatic wait cycle timings.
■ Automatic Wait Cycle Timings
● 16-bit bus, half-word read/write access
Figure 4.5-14 Automatic Wait Cycle Timings
BA1
BA1
BA2
BA1
BA1
BA2
CLK
A24 to A00
D31 to D16
RDX
WR0X,WR1X
(DACK0)
(EOP0)
#0
#0:1
wait
Read
#2
#2,3
wait
Write
[Operations]
• An automatic wait cycle can be realized by setting the WTC bit in the AMD register of the
corresponding chip select area.
• In the above example, 001B is set to the WTC bit to insert a wait cycle into ordinary bus cycles. The
total number of clock bus cycles becomes three: two ordinary bus clock cycles + one wait clock cycle.
Up to seven clock cycles can be set for automatic wait (the total number of ordinary bus clock cycles
then becomes 9).
165
CHAPTER 4 BUS INTERFACE
4.5.7
External Wait Cycle
This section explains the external wait cycle timings.
■ External Wait Cycle Timings
● 16-bit bus, half-word access
Figure 4.5-15 External Wait Cycle Timings
BA1
BA1
BA1
BA1
BA1
BA2
CLK
A24 to A00
Read
D31 to D16
RDX
Write
D31 to D16
WR0X,WR1X
#0
#0:1
#0,1
wait
wait
RDY
RDY
Automatic wait
Wait by RDY
Bus cycle
[Operations]
• An external wait cycle can be realized by setting 1 to the RDYE bit in EPCR0 to enable input of the
external RDY pin.
• When using external RDY, set 001B or a greater value to the WTC bit in AMD to insert one or more
automatic wait clock cycles. The RDY is detected in the last cycle of an automatic wait.
• Enter a signal into the external RDY pin synchronously with the fall of CLK pin input. If the external
RDY is low at the fall of CLK, the wait cycle is inserted and the same BA1 cycle is repeated. If the
signal is high, the wait cycle is assumed to have finished and the BA2 cycle starts.
166
CHAPTER 4 BUS INTERFACE
4.5.8
Ordinary DRAM Interface Read Cycle
This section explains the read cycle timings of the ordinary DRAM interface.
■ Read Cycle Timings of the Ordinary DRAM Interface
● 16-bit bus, word access to CS4 area
Figure 4.5-16 Read Cycle Timings of the Ordinary DRAM Interface
Q1
Q2
Q3
Q4
Q5
Q1
Q2
Q3
Q4
Q5
CLK
1)1CAS/2WE
A24 to A00
D31 to D24
D23 to D16
RAS
CAS
WEL
WEH
RDX
CS4X
(DACK0)
(EOP0)
2)2CAS/1WE
A24 to A00
D31 to D24
D23 to D16
RAS
CASL
CASH
WE
RDX
CS4X
(DACK0)
(EOP0)
X
#0 row.adr.
#0 col.adr
#0
#1
X
#2 row.adr.
#2 col.adr
#2
#3
X
#0 row.adr.
#0 col.adr
#0
#1
X
#2 row.adr.
#2 col.adr
#2
#3
Half-word access with upper address bit
Half-word access with lower address bit
[Operations]
• A24 to A00 (addresses 24 to 00) output a row address from a Q2 rise cycle and a column address from a
Q4 rise cycle for the read address determined by PG3 to PG0 in the DMCR register and the bus width.
The address output at the Q1 cycle is not defined.
• D31 to D16 (data 31 to 16) represent read data from an external memory or I/O device. 1CAS/2WE
fetches the read data at the rise of CAS and 2CAS/1WE at the rise of CASL or CASH. In 1CAS/2WE,
CAS corresponds to D31 to D16. In 2CAS/1WE, CAS corresponds to D31 to D24 and CASH
corresponds to D23 to D16.
Regardless of the data bus width or the access type (word, half-word, or byte), the data of D31 to D16 is
all fetched in a read cycle and its validity is confirmed inside the chip.
167
CHAPTER 4 BUS INTERFACE
• RAS is the row address strobe signal and goes high at the fall of Q1 and low at the rise of Q3. When the
PAGE bit is 0 (not in high-speed page mode), the RAS becomes normally high.
• CAS is the column address strobe signal. In 2CAS/1WE, CASL represents CAS on the upper address bit
side (lower bit: 0) and CASH represents CAS on the lower address bit side (lower bit: 1).
CAS is asserted at the rise of Q4, and negated at the fall of Q5.
• In a read cycle, WE (including WEL and WEH) are negated.
• In a read cycle, RDX outputs a "L" level signal from the Q1 cycle.
• CS4X and CS5X are output at the rise of the Q1 cycle.
• DACK0 to DACK2 and EOP0 to EOP2 are output at DMA external bus cycles.
The signal output is determined by DMAC register setting and the output timing is the same as for CAS.
168
CHAPTER 4 BUS INTERFACE
4.5.9
Ordinary DRAM Interface Write Cycle
This section explains the write cycle timings of the ordinary DRAM interface.
■ Write Cycle Timings of the Ordinary DRAM Interface
● 16-bit bus, word access to CS4 area
Figure 4.5-17 Write Cycle Timings of the Ordinary DRAM Interface
Q1
Q2
Q3
Q4
Q5
Q1
Q2
Q3
Q4
Q5
CLK
1)1CAS/2WE
A24 to A00
D31 to D24
D23 to D16
RAS
CAS
WEL
WEH
RDX
CS4X
(DACK0)
(EOP0)
2)2CAS/1WE
A24 to A00
D31 to D24
D23 to D16
RAS
CASL
CASH
WE
RDX
CS4X
(DACK0)
(EOP0)
X
#0 row.adr.
#0
#1
#0 col.adr
X
#2 row.adr.
#2
#3
#2 col.adr
X
#0 row.adr.
#0
#1
#0 col.adr
X
#2 row.adr.
#2
#3
#2 col.adr
Half-word access with upper address bit
Half-word access with lower address bit
[Operations]
• Output from A24 to A00 (addresses 24 to 00) is the same as for a read cycle.
• D31 to D16 (data 31 to 16) represent write data to an external memory or I/O device. In a write cycle,
write data is output from the Q1 cycle and the signal becomes Hi-Z after Q5. In 1CAS/2WE, WEL
corresponds to D31 to D24 and WEH corresponds to D23 to D16. In 2CAS/1WE, WE corresponds to
D31 to D16 and effective data is output.
If the data bus width is 8 bits, write data is output to D31 to D24.
• RAS is the same as for a read cycle.
• CAS is the same as for a read cycle.
169
CHAPTER 4 BUS INTERFACE
• WE is the DRAM write strobe signal. In 1CAS/2WE, WEL represents WE on the upper address bit side
(lower bit: 0) and WEH represents WE on the lower address bit side (lower bit: 1).
This signal is output at a write cycle, asserted at the rise of Q4, and negated at the next cycle of Q5.
• In a write cycle, RDX outputs a "H" level signal.
• CS4X and CS5X are output at the rise of the Q1 cycle.
• DACK0 to DACK2 and EOP0 to EOP2 are output at DMA external bus cycles.
The signal output is determined by DMAC register setting and the output timing is the same as for CAS.
170
CHAPTER 4 BUS INTERFACE
4.5.10
Ordinary DRAM Read Cycle
This section shows the ordinary DRAM read cycle timings.
■ Ordinary DRAM Read Cycle Timings
● 16-bit bus, half-word access
Figure 4.5-18 Ordinary DRAM Read Cycle Timings 1
Q1
Q2
Q3
Q4
Q5
CLK
1)1CAS/2WE
A24 to A00
D31 to D24
D23 to D16
RAS
CAS
WEL
WEH
2)2CAS/1WE
A24 to A00
D31 to D24
D23 to D16
RAS
CASL
CASH
WE
X
#0 row.adr.
#0 col.adr
#0
#1
X
#0 row.adr.
#0 col.adr
#0
#1
171
CHAPTER 4 BUS INTERFACE
● 16-bit bus, byte access
Figure 4.5-19 Ordinary DRAM Read Cycle Timings 2
Q1
Q2
Q3
Q4
Q5
Q1
Q2
Q3
Q4
Q5
CLK
1)1CAS/2WE
A24 to A00
D31 to D24
D23 to D16
RAS
CAS
WEL
WEH
2)2CAS/1WE
A24 to A00
D31 to D24
D23 to D16
RAS
CASL
CASH
WE
X
#0 row.adr.
#0 col.adr
#0
X
X
#1 row.adr.
#1 col.adr
X
#1
X
#0 row.adr.
#0 col.adr
#0
X
X
#1 row.adr.
#1 col.adr
X
#1
Upper address bit
Lower address bit
● 8-bit bus, half-word access
Figure 4.5-20 Ordinary DRAM Read Cycle Timings 3
Q1
Q2
Q3
Q4
Q5
Q1
Q2
Q3
Q4
Q5
CLK
A24 to A00
D31 to D24
D23 to D16
RAS
CAS
WE
172
X
#0 row.adr.
#0 col.adr
#0
X
#1 row.adr.
#1 col.adr
#1
CHAPTER 4 BUS INTERFACE
4.5.11
Ordinary DRAM Write Cycle
This section shows the ordinary DRAM write cycle timings.
■ Ordinary DRAM Write Cycle Timings
● 16-bit bus, half-word access
Figure 4.5-21 Ordinary DRAM Write Cycle Timings 1
Q1
Q2
Q3
Q4
Q5
CLK
1) 1CAS/2WE
A24 to A00
D31 to D24
D23 to D16
RAS
CAS
WEL
WEH
2) 2CAS/1WE
A24 to A00
D31 to D24
D23 to D16
RAS
CASL
CASH
WE
X
#0 row.adr.
#0
#1
#0 col.adr
X
#0 row.adr.
#0
#1
#0 col.adr
173
CHAPTER 4 BUS INTERFACE
● 16-bit bus, byte access
Figure 4.5-22 Ordinary DRAM Write Cycle Timings 2
Q1
Q2
Q3
Q4
Q5
Q1
Q2
Q3
Q4
Q5
CLK
1)1CAS/2WE
A24 to A00
D31 to D24
D23 to D16
RAS
CAS
WEL
WEH
2)2CAS/1WE
A24 to A00
D31 to D24
D23 to D16
RAS
CASL
CASH
WE
X
#0 row.adr.
#0
X
#0 col.adr
X
#1 row.adr.
X
#1
#1 col.adr
Upper address bit
Lower address bit
X
#0 row.adr.
#0
X
#0 col.adr
X
#1 row.adr.
#1
#1
#1 col.adr
Upper address bit
Lower address bit
● 8-bit bus, half-word access
Figure 4.5-23 Ordinary DRAM Write Cycle Timings 3
Q1
Q2
Q3
Q4
Q5
Q1
Q2
Q3
Q4
Q5
CLK
A24 to A00
D31 to D24
D23 to D16
RAS
CAS
WE
174
X
#0 row.adr.
#0
#0 col.adr
X
#1 row.adr.
X
#1 col.adr
CHAPTER 4 BUS INTERFACE
4.5.12
Automatic Wait Cycle in the Ordinary DRAM Interface
This section explains the automatic wait cycle timings of the ordinary DRAM interface.
■ Automatic Wait Cycle Timings of the Ordinary DRAM Interface
● 8-bit bus, byte access
Figure 4.5-24 Automatic Wait Cycle Timings of the Ordinary DRAM Interface
Q1
Q1W
Q2Q
X
#0 row.adr.
3Q
4Q
4W
Q5
CLK
1)Read
A24 to A00
D31 to D24
D23 to D16
RAS
CAS
WE
RDX
2)Write
A24 to A00
D31 to D24
D23 to D16
RAS
CAS
WE
RDX
#0 col.adr.
#0
X
#0 row.adr.
#0 col.adr.
#0
Q1 wait
Q4 wait
Ordinary DRAM interface
[Operations]
One clock cycle can be inserted into both the Q1 and Q4 cycles by setting the Q1W and Q4W bits in
DMCR4 or DMCR5. These cycles are called Q1W and Q4W.
Q1W and Q4W execute the same cycles as the Q1 and Q4 cycles. Thus the "H" level duration of RAS and
the "L" level duration of CAS can be extended by one cycle each.
Set the cycles according to the DRAM access type.
175
CHAPTER 4 BUS INTERFACE
4.5.13
DRAM Interface in high-speed Page Mode
This section explains the DRAM interface timings in high-speed page mode.
■ DRAM Interface Timings in High-speed Page Mode
● Read cycle: 16-bit bus, word access
Figure 4.5-25 DRAM Interface Timings 1 in High-speed Page Mode
Q1
Q2
Q3
Q4
Q5
Q4
Q5
Q4
Q5
Q4
Q5
CLK
1) 1CAS/2WE
A24 to A00
D31 to D24
D23 to D16
RAS
CAS
WEL
WEH
RDX
X
#0 row.adr.
#0 col.adr
#0
#1
Ordinary DRAM bus cycle
#2 col.adr
#2
#3
High-speed page
#4 col.adr
#4
#5
High-speed page
#6 col.adr
#6
#7
High-speed page
[Operations]
• While RAL is held low, WE (including WEL and WEH) is held high for read control only by CAS
(including CASL and CASH).
• Column addresses are output at the Q4 and Q5 cycles.
• Write cycle: 16-bit bus, word access
Figure 4.5-26 DRAM Interface Timings 2 in High-speed Page Mode
Q1
Q2
Q3
Q4
Q5
Q4
Q5
Q4
Q5
Q4
Q5
CLK
2) 2CAS/1WE
A24 to A00
D31 to D24
D23 to D16
RAS
CASL
CASH
WE
RDX
X
#0 row.adr.
#0 col.adr
#0
#1
Ordinary DRAM bus cycle
#2 col.adr
#2
#3
High-speed page
#4 col.adr
#4
#5
High-speed page
#6 col.adr
#6
#7
High-speed page
[Operations]
• While RAL is held low, WE (including WEL and WEH) is turned low for write control only by CAS
(including CASL and CASH).
• Column addresses and data are output at the Q4 and Q5 cycles.
176
CHAPTER 4 BUS INTERFACE
● CS area (CS4/5) switching in high-speed page mode, read-write cycle, 2CAS1WE
Figure 4.5-27 DRAM Interface Timings 3 in High-speed Page Mode
Q4
Q5
Idle
Q4
Q5
Q4
Q5
Q4
Q5
Q4
Q5
CLK
A24 to A00
D31 to D24
D23 to D16
CS4X
CS5X
RDX
CS5X col.adr
Read
Read
CS5X col.adr
CS5X col.adr
Write
Write
Write
Write
CS4X col.adr
CS4X col.adr
Read
Read
Read
Read
CS4:RAS
CS4:CASL
CS4:CASH
CS4:WE
CS5:RAS
CS5:CASL
CS5:CASH
CS5:WE
CS4 area
CS5 area
[Operations]
• In high-speed page mode, even when the CS area is switched, RAL is held low.
• When the bus cycle starts from a high-speed page, RDX is turned low at the rise of Q4 and negated after
Q5 in a read cycle. In a write cycle, WE (including WEL and WEH) is turned low at the rise of Q4 and
negated after Q5.
• CS4X and CS5X change at the same timing as the output address. If the bus cycle starts from a highspeed page, CS4X and CS5X change from the same Q4 cycle as the column address.
● Basic bus cycle in high-speed page mode
Figure 4.5-28 DRAM Interface Timings 4 in High-speed Page Mode
Q4
Q5
Idle
BA1
BA2
BA1
BA2
Idle
Q4
Q5
Q4
CLK
A24 to A00
D31 to D24
D23 to D16
CS2X
CS4X
CS4X col.adr
Read
Read
CS2X basic bus
Write
Write
CS2X basic bus
Read
Read
CS4X col.adr
Read
Read
CS4X c
RDX
WROX
CS4:RAS
CS4:CASL
CS4:CASH
CS4:WE
CS4 high-speed page
CS2 basic bus
CS4 high-speed page
[Operations]
In high-speed page mode, even when the CS area is switched and another CS area is accessed, RAS
remains low.
177
CHAPTER 4 BUS INTERFACE
4.5.14
Single DRAM Interface Read Cycle
This section explains the read cycle timings of the single DRAM interface.
■ Read Cycle Timings of the Single DRAM Interface
● 16-bit bus, word access
Figure 4.5-29 Read Cycle Timings of the Single DRAM Interface
Q1
Q2
Q3
Q4SR
Q4SR
Q4SR
Q4SR
Idle
Q1
Q2
Q3
CLK
1)1CAS/2WE
A24 to A00
D31 to D24
D23 to D16
RAS
CAS
WEL
WEH
RDX
(DACK0)
(EOP0)
X
row.adr.
col.
col.
Read
Read
col.
Read
Read
col.
Read
Read
X
row.adr.
Read
Read
Outside the page
High-speed High-speed High-speed
page
page
page
[Operations]
• Column addresses are output at Q4SR cycles.
• CAS is asserted at the fall of Q4SR and negated at the rise representing the end of Q4SR.
• The interface fetches data from D31 to D16 at the rise of CAS (including CASL and CASH) like the
ordinary DRAM interface.
• To avoid a bus conflict on an external data bus, insert at least one idle clock cycle at the end of a read
cycle.
• The DACK0 to DACK2 and EOP0 to EOP2 output timings are the same as CAS.
178
CHAPTER 4 BUS INTERFACE
4.5.15
Single DRAM Interface Write Cycle
This section explains the write cycle timings of the single DRAM interface.
■ Write Cycle Timings of the Single DRAM Interface
● 16-bit bus, word access
Figure 4.5-30 Write Cycle Timings of the Single DRAM Interface
Q1
Q2
Q3
Q4SW
Q4SW
Q4SW
Q4SW
Q1
Q2
Q3
Q4SW
CLK
2)2CAS/1WE
A24 to A00
D31 to D24
D23 to D16
RAS
CASL
CASH
WE
RDX
(DACK0)
(EOP0)
X
W
W
row.adr.
col.
col.
W
W
col.
W
W
col.
W
W
X
W
W
row.adr.
col.
High-speed High-speed High-speed
page
page
page
[Operations]
• Column addresses and write data are output at Q4SW cycles.
• CAS is asserted at the fall of Q4SW and negated at the rise representing the end of Q4SW.
• WE (including WEL and WEH) is asserted at the rise of Q4SW and negated after Q4SW.
179
CHAPTER 4 BUS INTERFACE
4.5.16
Single DRAM Interface
This section explains the single DRAM interface timings.
■ Single DRAM Interface Timings
● Single DRAM interface, basic bus cycle, CS switching
Figure 4.5-31 Single DRAM Interface Timings
Q4SR Idle
BA1
BA2
Q1
Q2
Q3
Q4SW
Q4SR
Idle
Q4SR
CLK
A24 to A00 col.
D31 to D24
Read
D23 to D16
Read
CS2X
CS4X
CS5X
CS2X basic bus
Write
Write
X
row.adr.
col.
Write
Write
col.
col.
Read
Read
Read
Read
RDX
WR0X
CS4:RAS
CS4:CASL
CS4:CASH
CS4:WE
CS5:RAS
CS5:CASL
CS5:CASH
CS5:WE
CS5 Single
CS2
ordinary
CS4 Single
CS5
[Operations]
• When the bus cycle starts from a high-speed page, RDX is turned low at the rise of Q4SR and negated
after Q4SR in a read cycle. In a write cycle, WE (including WEL and WEH) is turned low at the rise of
Q4SW and negated after Q4SW
• CS4X and CS5X change at the same timing as the output address. If the bus cycle starts from a highspeed page, CS4X and CS5X change from the same Q4SR and Q4SW cycles as the column address.
180
CHAPTER 4 BUS INTERFACE
4.5.17
Hyper DRAM Interface Read Cycle
This section explains the read cycle timings of the hyper DRAM interface.
■ Read Cycle Timings of the Hyper DRAM Interface
● 16-bit bus, word access
Figure 4.5-32 Read Cycle Timings of the Hyper DRAM Interface
Q1
Q2
Q3
Q4HR Q4HR Q4HR Q4HR Q4HR
Idle
Q1
Q3
CLK
1) 1CAS/2WE
A24 to A00
D31 to D24
D23 to D16
RAS
CAS
WEL
WEH
RDX
(DACK0)
(EOP0)
X
row.adr.
col.0
col.2
col.4
col.6
X
Read0
Read2
Read4
Read6
Read1
Read3
Read5
Read7
row.a
Outside the page
High-speed High-speed High-speed High-speed
page
page
page
page
[Operations]
• Column addresses are output at Q4HR cycles.
• CAS is asserted at the fall of Q4HR and negated at the rise representing the end of Q4HR.
• The interface fetches data from D31 to D16 at the fall of CAS that is output at the next Q4HR cycle
after the one where the corresponding column address was output.
• To avoid a bus conflict on an external data bus, insert at least one idle clock cycle at the end of a read
cycle.
• The DACK0 to DACK2 and EOP0 to EOP2 output timings are the same as CAS.
181
CHAPTER 4 BUS INTERFACE
4.5.18
Hyper DRAM Interface Write Cycle
This section explains the write cycle timings of the hyper DRAM interface.
■ Write Cycle Timings of the Hyper DRAM Interface
● 16-bit bus, word access
Figure 4.5-33 Write Cycle Timings of the Hyper DRAM Interface
Q1
Q2
Q3
Q4HW
Q4HW
Q4HW
Q4HW
Q1
Q2
Q3
Q4HW
CLK
2)2CAS/1WE
A24 to A00
D31 to D24
D23 to D16
RAS
CASL
CASH
WE
RDX
(DACK0)
(EOP0)
X
W
W
row.adr.
col.
col.
W
W
col.
W
W
col.
W
W
X
W
W
row.adr.
col.
[Operations]
• Column addresses and write data are output at Q4HW cycles.
• CAS is asserted at the fall of Q4HW and negated at the rise representing the end of Q4HW.
• WE (including WEL and WEH) is asserted at the rise of Q4HW and negated after Q4HW.
182
CHAPTER 4 BUS INTERFACE
4.5.19
Hyper DRAM Interface
This section explains the hyper DRAM interface timings.
■ Hyper DRAM Interface Timings
● Hyper DRAM interface, basic bus cycle, CS switching
Figure 4.5-34 Hyper DRAM Interface Timings
BA1
BA2
Q1
Q2
Q3
Q4HR Idle
Q4HR
Q4HW Q4HR
Q4HR
CLK
A24 to A00 CS2X basic bus
D31 to D24
Write
D23 to D16
Write
CS2X
CS4X
CS5X
X
row.adr.
col.adr.
Read
Read
col.
Write
Write
col.
col.
Read
Read
RDX
WR0X
CS4:RAS
CS4:CASL
CS4:CASH
CS4:WE
CS5:RAS
CS5:CASL
CS5:CASH
CS5:WE
CS2 ordinary
CS4 Hyper DRAM read
CS5 Hyper DRAM
Write/Read
[Operations]
• When the bus cycle starts from a high-speed page, RDX is turned low at the fall of Q4HR and negated
after Q4HR in a read cycle. In a write cycle, WE (including WEL and WEH) is turned low at the rise of
Q4HW and negated after Q4HW.
• CS4X and CS5X change at the same timing as the output address. If the bus cycle starts from a highspeed page, CS4X and CS5X change from the same Q4HR and Q4HW cycles as the column address.
183
CHAPTER 4 BUS INTERFACE
4.5.20
DRAM Refresh
This section explains the DRAM refresh timings.
■ CAS before RAS (CBR) Refresh
Figure 4.5-35 CAS before RAS (CBR) Refresh Timings
Q4
Q5
R1
R2
R3
R4
idle
Q1
Q2
xx
row.adr.
Q3
CLK
CBR
RAS
CAS
WE
A24 to A00
D31 to D16
col.adr.
[Operations]
• CBR refresh can be executed by setting both the REFE bit in DMCR4 or DMCR5 and the STR bit in
RFCR.
• In this guide, the CBR cycles are expressed as R1 to R4.
CAS is asserted at the fall of the R2 cycle and negated at the fall of the R4 cycle.
RAS is asserted at the rise of the R3 cycle and negated at the fall of the next idle cycle of R4 cycle. WE
indicates the negated status during CBR.
• CAS in 1CAS/2WE and CASL and CASH in 2CAS/1WE are output at the above timings.
• CBR refresh has priority over DRAM bus access.
If DRAM word access is attempted through an 8-bit bus, the bus access should usually be repeated four
times. Even if a refresh request is detected in the first to the third accesses, refresh is not executed until
the end of the fourth bus access.
Refresh is always executed after a single unit of access is completed.
• Even when the next bus access is within the page, DRAM access after CBR refresh starts from the Q1
cycle indicating the start of DRAM access and data is output from the row address.
• CBR refresh is executed periodically even in the following statuses:
- Ordinary bus access other than DRAM access
- External bus release status (BGRNTX = L)
- CPU in sleep status
184
CHAPTER 4 BUS INTERFACE
■ Automatic Wait Cycle for CBR Refresh
Figure 4.5-36 Automatic Wait Cycle Timings for CBR Refresh
R1
R1W
R2
R3
R3W
R4
idle
CLK
RAS
CAS
wait
wait
[Operations]
• An automatic wait cycle for CBR refresh can be inserted by setting the R1W and R3W bits in RFCR.
■ Self-Refresh
Figure 4.5-37 Self-refresh Timings
SR1
SR2
SR3
SR3
SR3
idle
CLK
SLFRbit
RAS
CAS
[Operations]
• Self-refresh starts when the SLFR bit is set to 1 in DMCR4 or DMCR5 and stops when the SLFR bit is
set to 0.
• After self-refresh, at least seven idle cycles are inserted.
• In this guide, the self-fresh cycles are expressed as SR1 to SR3.
185
CHAPTER 4 BUS INTERFACE
4.5.21
External Bus Request
This section explains the external bus request timings.
■ Release of Bus Privilege
Figure 4.5-38 Bus Privilege Release Timing
CLK
A24 to A00
D31 to D16
RDX
#0:1
#0:1
Hi-Z
Hi-Z
Hi-Z
BRQ
BGRNTX
One cycle
[Operations]
• Bus arbitration by BRQ and BGRNTX can be executed by setting the BRE bit to 1 in EPCR0.
• To release the bus privilege, set the pin to Hi-Z and then assert BGRNTX one clock cycle later.
■ Acquisition of Bus Privilege
Figure 4.5-39 Bus Privilege Acquisition Timing
CLK
A24 to A00
D31 to D16
RDX
BRQ
BGRNTX
Hi-Z
Hi-Z
Hi-Z
One cycle
[Operations]
• Bus arbitration by BRQ and BGRNTX can be executed by setting the BRE bit to 1 in EPCR0.
• To acquire the bus privilege, negate BGRNTX and then make each pin active one clock cycle later.
186
CHAPTER 4 BUS INTERFACE
4.6
Internal Clock Multiplication (Clock Doubler)
MB91121 has a clock multiplication circuit and the CPU operates at single or double the
frequency of the bus interface. Even when either clock is selected, the bus interface
operates synchronously with the CLK output pin. If the CPU issues an external access
request, external access starts at the rise of CLK output.
■ Internal Clock Multiplication
For the single-frequency or double-frequency clock selection method, see Section "3.12.11 Clock Doubler
Function".
The clock can be changed even when the chip is in operation. For clock switching, the bus operation is
temporarily suspended. Reset automatically selects the single-frequency clock.
Figure 4.6-1 shows the timings of the double-frequency clock and Figure 4.6-2 shows those of the singlefrequency clock.
Figure 4.6-1 Timings of the Double-frequency Clock (16-bit Bus, Word Read Access)
Internal clock
Internal instruction address
2
N
N
2
D
D
Internal instruction data
CLK output
N
External address bus
N
D
External data bus
N
2
D
4
2
External RDX
External access (instruction fetch)
Prefetch
Figure 4.6-2 Timings of the Single-frequency Clock (16-bit Bus, Word Read Access)
Internal clock
Internal instruction address
N
N
Internal instruction data
D
2
D
2
CLK output
External address bus
External data bus
N
N
D
2
D
N
4
2
External RDX
External access (instruction fetch)
Prefetch
187
CHAPTER 4 BUS INTERFACE
4.7
Sample Program for External Bus Operations
This section gives a simple program for operating an external bus.
■ Program Specifications for External Bus Operations
The register settings are as follows:
● Areas
• Area 0 (AMD0): 16-bit ordinary bus, automatic wait 0
• Area 1 (AMD1): 16-bit ordinary bus, automatic wait 2
• Area 2 (AMD32): 16-bit ordinary bus, automatic wait 1
• Area 3 (AMD32): 16-bit ordinary bus, automatic wait 1
• Area 4 (AMD4): 16-bit DRAM bus, page size: 256, 1CAS/2WE, wait, CBR refresh
• Area 5 (AMD5): 16-bit DRAM bus, page size: 512, 2CAS/1WE, no wait, CBR refresh
● Other buses
• Refresh (RFCR): No wait, 1/8 setting
• External pin (EPCR0): External RDY acceptance, BRQ/BGRNTX arbitration
• External pin (DSCR): DRAM pin setting
• Little endian (LER): Area 2
● Note also the following:
• Set MD2 to MD0 to 001B. The external vector is in 16-bit mode.
• Set the mode register (MODR) after setting area 0 to the same bus width.
• Set areas 1 to 5 so as not to overlap.
188
CHAPTER 4 BUS INTERFACE
■ Sample Program for External Bus Operations
For ease of understanding, this program writes a byte register by byte access and a half-word register by
half-word access.
***** Sample program *****
//Register settings
init_epcr
ldi:20
#0xffff,r0
// External pin setting
// External RDY wait, and
// BRQ/BGRNTX arbitration
init_dscr
ldi:20
#0x628,r1
// epcr0 register address setting
sth
r0,@r1
// epcr0 register write
ldi:8
#0xff,r0
// DRAM pin setting
// RAS,CAS,WE
init_amd0
init_amd1
ldi:20
#0x625,r1
// dscr register address setting
stb
r0,@r1
// dscr register write
ldi:8
#0x08,r0
// 16-bit bus, 0-wait
ldi:20
#0x620,r1
// amd0 register address setting
stb
r0,@r1
// amd0 register write
ldi:8
#0x0a,r0
// 16-bit bus, 2-wait
ldi:20
#0x621,r1
// amd1 register address setting
stb
r0,@r1
// amd1 register write
init_amd32 ldi:8
init_amd4
init_amd5
#0x49,r0
// Ordinary 16-bit bus, 1-wait
ldi:20
#0x622,r1
// amd32 register address setting
stb
r0,@r1
// amd32 register write
ldi:8
#0x88,r0
// DRAM 16-bit bus
ldi:20
#0x623,r1
// amd4 register address setting
stb
r0,@r1
// amd4 register write
ldi:8
#0x88,r0
// DDRAM 16-bit bus
ldi:20
#0x624,r1
// amd5 register address setting
stb
r0,@r1
// amd5 register write
#0x0c90,r0
// page size=256,Q1/Q4-wait, Page
init_dmcr4 ldi:20
// 1CAS-2WE, CBR, no parity
ldi:20
#0x62c,r1
// dmcr4 register address setting
sth
r0,@r1
// dmcr4 register write
#0x10c0,r0
// Page size = 512,
init_dmcr5 ldi:20
// no Q1/Q4-wait, page
// 2CAS-1WE, CBR, no parity
init_rfcr
ldi:20
#0x62e,r1
// dmcr5 register address setting
sth
r0,@r1
// dmcr5 register write
ldi:20
#0x0205,r0
// REL = 2, no R1W/R3W-wait,
// refresh, 1/8
ldi:20
#0x626,r1
// rfcr register address setting
x sth
r0,@r1
// rfcr register write
189
CHAPTER 4 BUS INTERFACE
init_asr
ldi:32
#0x0013001,r0
// asr1/amr1 register set value
ldi:32
#0x0015001,r1
// asr2/amr2 register set value
ldi:32
#0x0017001,r2
// asr3/amr3 register set value
ldi:32
#0x0019001,r3
// asr4/amr4 register set value
ldi:32
#0x001b001,r4
// asr5/amr5 register set value
ldi:20
#0x60c,r5
// asr1/amr1 register
// address setting
ldi:20
#0x610,r6
// asr2/amr2 register
// address setting
ldi:20
#0x614,r7
// asr3/amr3 register
// address setting
ldi:20
#0x618,r8
// asr4/amr4 register
// address setting
ldi:20
#0x61C,r9
// asr5/amr5 register
// address setting
init_ler
st
r0,@r5
// asr1/amr1 register write
st
r1,@r6
// asr2/amr2 register write
st
r2,@r7
// asr3/amr3 register write
st
r3,@r8
// asr4/amr4 register write
st
r4,@r9
// asr5/amr5 register write
ldi:8
#0x02,r0
// CH2 little endian
ldi:20
#0x7fe,r1
// ler register address setting
stb
r0,@r1
// ler register write
#0x80,r0
// External ROM/external bus
ldi:20
#0x7ff,r1
// modr register address setting
stb
r0,@r1
// modr register write
init_modr ldi:8
//External bus access
adr_set
bus_acc
190
ldi:32
#0x00136da0,r0 // ch.1 address
ldi:32
#0x00151300,r1 // ch.2 address
ldi:32
#0x00196434,r2 // ch.4 address (inside page)
ldi:32
#0x0019657c,r3 // ch.4 address (inside page)
ldi:32
#0x00196600,r4 // ch.4 address (outside page)
ldi:32
#0x001a6818,r5 // ch.5 address (inside page)
ldi:32
#0x001a6b8c,r6 // ch.5 address (inside page)
ldi:32
#0x001a6c00,r7 // ch.5 address (outside page)
ld
@r0,r8
// ch.1 data word load
lduh
@r1,r9
// ch.2 data half word load
ld
@r2,r10
// ch.4 data word load
ldub
@r3,r11
// ch.4 data byte load
st
r8,@r4
// ch.4 data word store
sth
r9,@r5
// ch.5 data half word store
st
r10,@r6
// ch.5 data word store
stb
r11,@r7
// ch.5 data byte store
CHAPTER 5
I/O PORT
This chapter explains an outline of an I/O port, the
register configuration and its functions, and the
relationship between the external pins and the switching
registers.
5.1 Outline of I/O Port
5.2 Port Data Register (PDR2 to PDRI)
5.3 Port Direction Register (DDR2 to DDRI)
5.4 Relationship between External Pins and Switching Registers
191
CHAPTER 5 I/O PORT
5.1
Outline of I/O Port
MB91121 allows a pin to be used as an I/O port when the corresponding resource is not
set to use the pin for input or output.
■ Basic Block Diagram of I/O Port
Figure 5.1-1 shows the basic I/O port configuration.
Figure 5.1-1 Basic I/O Port Configuration
Resource input
Data bus
0
1
PDR read
0
pin
P D R
Resource output 1
Resource output
enable
D D R
PDR: Port Data Register
DDR: Data Direction Register
■ I/O Port Registers
An I/O port consists of port data registers (PDR) and port direction registers (DDR).
● Input mode (DDR = 0)
• PDR read: The corresponding external pin level is read.
• PDR write: A set value is written into PDR.
● Output mode (DDR = 1)
• PDR read: The PDR value is read.
• PDR write: When a set value is written into PDR, the PDR value is output to the corresponding external
pin.
192
CHAPTER 5 I/O PORT
5.2
Port Data Register (PDR2 to PDRI)
The port data registers (PDR2 to PDRI) are input-output data registers for an I/O port
and the corresponding port direction registers (DDR2 to DDRI) control input and output.
■ Port Data Register (PDR2 to PDRI)
A port data register (PDR2 to PDRI) has the following register configuration:
PDR2
Address: 000001H
7
P27
6
P26
5
P25
4
P24
3
P23
2
P22
1
P21
0
P20
Initial value
XXXXXXXXB
Access
R/W
PDR6
Address: 000005H
7
P67
6
P66
5
P65
4
P64
3
P63
2
P62
1
P61
0
P60
Initial value
XXXXXXXXB
Access
R/W
PDR8
Address: 00000BH
7
-
6
-
5
P85
4
-
3
-
2
P82
1
P81
0
P80
Initial value
--X--XXXB
Access
R/W
PDRA
Address: 000009H
7
-
6
PA6
5
PA5
4
PA4
3
PA3
2
PA2
1
PA1
0
-
Initial value
-XXXXXX-B
Access
R/W
PDRB
Address: 000008H
7
PB7
6
PB6
5
PB5
4
PB4
3
PB3
2
PB2
1
PB1
0
PB0
Initial value
XXXXXXXXB
Access
R/W
PDRE
Address: 000012H
7
PE7
6
PE6
5
PE5
4
PE4
3
PE3
2
PE2
1
PE1
0
PE0
Initial value
XXXXXXXXB
Access
R/W
PDRF
Address: 000013H
7
PF7
6
PF6
5
PF5
4
PF4
3
PF3
2
PF2
1
PF1
0
PF0
Initial value
XXXXXXXXB
Access
R/W
PDRG
Address: 000014H
7
PG7
6
PG6
5
PG5
4
PG4
3
PG3
2
PG2
1
PG1
0
PG0
Initial value
XXXXXXXXB
Access
R/W
PDRH
Address: 000015H
7
PH7
6
PH6
5
PH5
4
PH4
3
-
2
-
1
-
0
-
Initial value
XXXX----B
Access
R/W
PDRI
Address: 000016H
7
-
6
-
5
-
4
-
3
-
2
-
1
PI1
0
PI0
Initial value
------XXB
Access
R/W
193
CHAPTER 5 I/O PORT
5.3
Port Direction Register (DDR2 to DDRI)
The port direction registers (DDR2 to DDRI) control the input-output direction of the
corresponding I/O port in bits.
The register value is set to 0 for input control and 1 for output control.
■ Port Direction Register (DDR2 to DDRI)
A port direction register (DDR2 to DDRI) has the following register configuration:
DDR2
Address: 000601H
7
P27
6
P26
5
P25
4
P24
3
P23
2
P22
1
P21
0
P20
Initial value
00000000B
Access
W
DDR6
Address: 000605H
7
P67
6
P66
5
P65
4
P64
3
P63
2
P62
1
P61
0
P60
Initial value
00000000B
Access
W
DDR8
Address: 00060BH
7
-
6
-
5
P85
4
-
3
-
2
P82
1
P81
0
P80
Initial value
--0--000B
Access
W
DDRA
Address: 000609H
7
-
6
PA6
5
PA5
4
PA4
3
PA3
2
PA2
1
PA1
0
-
Initial value
-000000-B
Access
W
DDRB
Address: 000608H
7
PB7
6
PB6
5
PB5
4
PB4
3
PB3
2
PB2
1
PB1
0
PB0
Initial value
00000000B
Access
W
DDRE
Address: 0000D2H
7
PE7
6
PE6
5
PE5
4
PE4
3
PE3
2
PE2
1
PE1
0
PE0
Initial value
00000000B
Access
W
DDRF
Address: 0000D3H
7
PF7
6
PF6
5
PF5
4
PF4
3
PF3
2
PF2
1
PF1
0
PF0
Initial value
00000000B
Access
W
DDRG
Address: 0000D4H
7
PG7
6
PG6
5
PG5
4
PG4
3
PG3
2
PG2
1
PG1
0
PG0
Initial value
00000000B
Access
W
DDRH
Address: 0000D5H
7
PH7
6
PH6
5
PH5
4
PH4
3
-
2
-
1
-
0
-
Initial value
0000----B
Access
W
DDRI
Address: 0000D6H
7
-
6
-
5
-
4
-
3
-
2
-
1
PI1
0
PI0
Initial value
------00B
Access
W
194
CHAPTER 5 I/O PORT
5.4
Relationship between External Pins and Switching
Registers
Table 5.4-1 shows the relationship between the initial values of the external pins and the
register values that set external pins as I/O ports or control pins.
"8-bit: to" and "16-bit: to" mean that the function changes depending on the external
bus width.
■ Selection of External Pin Function (I/O Port or Control Pin)
Table 5.4-1 External Pin Function Selection (1 / 4)
Pin No.
Pin symbol
P20 to P27
85 to 92
D16 to D23
Initial value
8-bit: P20 to P27
16-bit: D16 to D23
Switching register
Automatic switching according to the bus width
selected by MD0 to MD3 and AMD0 to AMD5
8-bit: P20 to P27
16-bit: D16 to D23
93 to 100
D24 to D31
D24 to D31
-
102 to 109
111 to 118
A00 to A15
A00 to A15
-
P60 to P67
120, 1 to 7
A16 to A23
A16 to A23
8
A24
A24
EPCR1 (AE23 bit)
P80
EPCR0 (RDYE bit)
0: P80
1: RDY
P81
EPCR0 (BRE bit)
0: P81
1: BGRNTX
P82
EPCR0 (BRE bit)
0: P82
1: BRQ
P80
79
RDY
P81
80
BGRNTX
P82
81
EPCR1 (AE16 to AE23 bits)
0: P60 to P67
1: A16 to A23
BRQ
82
RDX
RDX
Always set 1 to the RDXE bit in EPCR0
83
WR0X
WR0X
Always set 1 to the WRE bit in EPCR0
P85
84
WR1X
8-bit: P85
16-bit: WR1X
Automatic switching according to the bus width
selected by MD0 to MD3 and AMD0 to AMD5
8-bit: P85
16-bit: WR1X
CS1 to CS5X
EPCR0 (COE1 to COE5 bits)
0: PA1 to PA5
1: CS1X to CS5X
PA1 to PA5
66 to 70
CS1X to CS5X
195
CHAPTER 5 I/O PORT
Table 5.4-1 External Pin Function Selection (2 / 4)
Pin No.
Pin symbol
Initial value
PA6
71
CLK
CLK
Switching register
EPCR0 (CKE bit)
0: PA6
1: CLK
PB0 to PB7
56 to 63
RAS0
CS0L
CS0H
DW0X
RAS1
CS1L
CS1H
DW1X
PB0 to PB7
DSCR (RS0E to DW1E bits)
0: PB0 to PB7
1: RAS0 to DW1X
76 to 78
MD0 to MD2
MD0 to MD2
-
73
MD3
MD3
-
72
NMIX
NMIX
-
12 to 19
AN0 to AN7
AN0 to AN7
-
PE0/SC2 (input)
SMR (SCKE bit)
0: Pin value is input to SC2 (except in stop status).
1: SC2 (output)
PE0
42
SC2
PE1
43
PE1/DREQ0
Pin value is always input to DREQ0.
PE2
DATCR (AKSE0 and AKDE0 bits)
00: PE2
Other: DACK0
PE3
DATCR (EPSE0 and EPDE0 bits)
00: PE3
Other: EOP0
DREQ0
PE2
44
DACK0
PE3
45
EOP0
PE4
46
PE4/DREQ1
Pin value is always input to DREQ1.
PE5
DATCR (AKSE1 and AKDE1 bits)
00: PE5
Other: DACK1
PE6
DATCR (EPSE1 and EPDE1 bits)
00: PE6
Other: EOP1
DREQ1
PE5
47
DACK1
PE6
48
EOP1
PE7
49
PE7/DREQ2
DREQ2
196
Pin value is always input to DREQ2.
CHAPTER 5 I/O PORT
Table 5.4-1 External Pin Function Selection (3 / 4)
Pin No.
Pin symbol
Initial value
PF0
33
PF0/SI0
SI0
PF1
35
PF1
SO0
PF2
36
PF2/SC0 (input)
SC0
PF3
37
PF3/SI1
SI1
PF4
38
PF4
SO1
PF5
39
PF5/SC1 (input)
SC1
PF6
40
PF6/SI2
SI2
PF7
41
PF7
SO2
PG0 to PG3
25 to 28
PG0/INT0 to PG3/INT3
INT0 to INT3
PG4 to PG7
29 to 32
INT4 to INT7
PG4/INT4/TRG0 to
PG7/INT7/TRG3
PH4 to PH7
20 to 23
PH4 to PH7
OCPA0 to OCPA3
PI0
50
AVCC
SMR (SCKE bit)
0: Pin value is input to SC0 (except in stop status).
1: SC0 (output)
Pin value is always input to SI1
(except in stop status).
SMR (SOE bit)
0: PF4
1: SO1 (output)
SMR (SCKE bit)
0: Pin value is input to SC1 (except in stop status).
1: SC1 (output)
Pin value is always input to SI2
(except in stop status).
SMR (SOE bit)
0: PF7
1: SO2 (output)
Pin value is always input to INT0 to
INT3.
Pin value is always input to INT4 to INT7 (except
in stop status).
Pin value is always input to INT0 to INT3 (except
in stop status).
PCNL (POEN bit)
0: PH4 to PH7
1: OCPA0 to OCPA3
PI1/ATGX
DATCR (EPSE2 and EPDE2 bits)
0: PI1
1: EOP2
Pin value is always input to ATGX
(except in stop status).
ATGX
9
SMR (SOE bit)
0: PF1
1: SO0 (output)
DATCR (AKSE2 and AKDE2 bits)
0: PI0
1: DACK2
PI1
EOP2
Pin value is always input to SI0
(except in stop status).
PI0
DACK2
51
Switching register
AVCC
-
197
CHAPTER 5 I/O PORT
Table 5.4-1 External Pin Function Selection (4 / 4)
Pin No.
Pin symbol
Initial value
Switching register
10
AVRH
AVRH
-
11
AVSS
(AVRL)
AVSS
(AVRL)
-
74
RSTX
RSTX
-
54
X0
X0
-
53
X1
X1
-
24, 55, 64, 110
VCC
VCC
-
34, 52, 75, 101,119
VSS
VSS
-
198
CHAPTER 6
16-BIT RELOAD TIMER
This chapter gives an outline of the 16-bit reload timer
and explains the register configuration and functions
and the timer operations.
6.1 Outline of the 16-bit Reload Timer
6.2 Registers of the 16-bit Reload Timer
6.3 16-bit Reload Timer Operations
6.4 Counter Operation Statuses
199
CHAPTER 6 16-BIT RELOAD TIMER
6.1
Outline of the 16-bit Reload Timer
The 16-bit reload timer consists of a 16-bit down counter, a 16-bit reload register, a
prescaler for internal count clock generation, and control registers.
An input clock can be selected from three internal clocks (1/2, 1/8, and 1/32 of the
machine clock frequency).
MB91121 includes this timer for three channels.
The channel-2 T0 output from the reload timer is connected to the A/D converter inside
the LSI. Therefore, A/D conversion can be activated at the cycle set on the reload
register.
■ Block Diagram of the 16-bit Reload Timer
Figure 6.1-1 is a block diagram of the 16-bit reload timer.
Figure 6.1-1 Block Diagram of the 16-bit Reload Timer
R-BUS
16
/
16-bit reload timer
/
8
Reload
RELD
16-bit down counter
/
16
UF
OUTE
OUTL
2
/
OUT
CTL.
GATE
Clock selector
INTE
/
2U
CSL1
UF
CNTE
CSL0
TRG
/
2
Retrigger
IN CTL.
TIM0 to TIM2
φ
φ
φ
1
3
5
2
2
2
3
A/D (ch.2)
Prescaler clear
MOD2
MOD1
MOD0
/
3
200
PWM(ch.0,ch.1)
IRQ
CHAPTER 6 16-BIT RELOAD TIMER
6.2
Registers of the 16-bit Reload Timer
Figure 6.2-1 shows the registers of the 16-bit reload timer.
■ Registers of the 16-bit Reload Timer
Figure 6.2-1 Registers of the 16-bit Reload Timer
15
14
13
12
-
-
-
-
7
6
5
4
11
9
8
CSL1 CSL0 MOD2 MOD1 Control status register (TMCSR)
3
MOD0 OUTE OUTL RELD INTE
15
10
2
UF
1
0
CNTE TRG
0
16-bit reload timer (TMR)
15
0
16-bit reload register (TMRLR)
201
CHAPTER 6 16-BIT RELOAD TIMER
6.2.1
Control Status Register (TMCSR)
The control status register (TMCSR) controls the 16-bit timer operation modes and
interrupts.
Rewrite bits other than UF, CNTE, and TRG when CNTE=0.
The bits can be written simultaneously.
■ Control Status Register (TMCSR)
The control status register (TMCSR) has the following register configuration:
TMCSR
Address:
11
10
9
8
7
6
5
4
3
2
1
0
Initial value
00002EH CSL1 CSL0 MOD2MOD1MOD0 OUTE OUTL RELD INTE UF CNTE TRG 0000 00000000H
000036H R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
000042H
Bits 11 and 10: CSL1, CSL0 (Count Clock Select)
These bits are used to select a count clock. Table 6.2-1 lists the clock sources to be selected.
Table 6.2-1 Clock Source Setting Using the CSL Bits
CSL1
CSL0
Clock source (φ machine clock)
0
0
φ /21
0
1
φ /23
1
0
φ /25
1
1
Setting prohibited
The minimum pulse width necessary for an external clock is 2-T (T: peripheral clock machine cycle).
Bits 9, 8, and 7: MOD2, MOD1, MOD0 (MODe)
These bits set the operation mode.
Always set 0 to these bits.
Bit 6: OUTE (OUTput Enable)
Always set 0 to this bit.
Bit 5: OUTL
Always set 0 to this bit.
Bit 4: RELD
This bit enables reload. When this bit is set to 1, the reload mode is activated. A counter underflow from
0000H to FFFFH causes the reload register contents to be loaded to the counter for continuous counting.
When this bit is set to 0, a counter overflow from 0000H to FFFFH stops counting.
Bit 3: INTE
This bit enables an interrupt request. When this bit is 1, an interrupt request is generated as soon as the
UF bit becomes 1. When this bit is 0, no interrupt request is generated.
202
CHAPTER 6 16-BIT RELOAD TIMER
Bit 2: UF
This is a timer interrupt request flag. A counter underflow from 0000H to FFFFH sets this bit to 1 and
writing 0 clears it.
Writing 1 into this bit produces no effect.
The read value is 1 when a read-modify-write instruction is used.
Bit 1: CNTE
This bit enables timer counting. When this bit is set to 1, the timer changes to the trigger wait status.
When this bit is set to 0, the counter stops counting.
Bit 0: TRG
This is a software trigger register. When this bit is set to 1, software trigger causes the reload register
contents to be loaded to the counter for continuous counting.
Writing 0 into this bit produces no effect. The read value is always 0. Trigger input by this register is
valid only when the CNTE bit is 1. Nothing occurs when the CNTE bit is 0.
203
CHAPTER 6 16-BIT RELOAD TIMER
6.2.2
16-bit Timer Register (TMR) and 16-bit Reload Register
(TMRLR)
The 16-bit timer register (TMR) can read a count value from the 16-bit reload register.
The 16-bit reload register (TMRLR) can hold the initial count value.
■ 16-bit Timer Register (TMR)
TMR
Initial value
15
0
~ ~
~ ~
Address:
00002AH
000032H
00003EH
R
R
R
R
...
R
R
R
R
R
X
X
X
X
...
X
X
X
X
X
This register can read a count value from the 16-bit reload register.
The initial value is not defined.
Always use a 16-bit data transfer instruction to read this register.
■ 16-bit Timer Register (TMRLR)
TMRLR
Initial value
15
0
~ ~
~ ~
Address:
000028H
000030H
00003CH
W
W
W
W
...
W
W
W
W
W
X
X
X
X
...
X
X
X
X
X
The 16-bit reload register (TMRLR) can hold the initial count value.
The initial value is not defined.
Always use a 16-bit data transfer instruction to write this register.
204
CHAPTER 6 16-BIT RELOAD TIMER
6.3
16-bit Reload Timer Operations
The 16-bit reload timer operates in the following two ways:
• Internal clock operation
• Underflow operation
■ Internal Clock Operation
When operating the timer on a divided internal clock, 1/2, 1/8, or 1/32 of the machine clock can be selected
as a clock source.
The external input pin can be used for trigger input or gate input by register setting.
To enable and start counting, write 1 into both the CNTE and TRG bits in the control status register.
Trigger input by the TRG bit is always effective in any mode when the timer is active (CNTE=1).
Figure 6.3-1 shows the counter activation and operation timings.
It takes time T (peripheral clock machine cycle) from when a counter start trigger signal is entered until
data is loaded from the reload register to the counter.
Figure 6.3-1 Counter Activation and Operation Timings
Count clock
Counter
Reload data
1
1
1
Data load
CNTE (Register)
TRG(Register)
T
■ Underflow Operation
An underflow means a change of the counter value from 0000H to FFFFH. Therefore, an underflow occurs
at the count of "reload register set value + 1".
When the RELD bit is 1, the reload register contents are loaded to the counter in the case of an underflow
to keep counting. When the RELD bit is 0, the counter stops at FFFFH.
An underflow sets the UF bit in the control register and an interrupt request is generated when the INTE bit
is 1.
Figure 6.3-2 shows the underflow operation.
205
CHAPTER 6 16-BIT RELOAD TIMER
Figure 6.3-2 Underflow Operation Timings
Count clock
Counter
0000H
Reload data
Data load
Underflow setting
RELD
1
Count clock
Counter
0000H
FFFFH
Underflow setting
RELD
206
0
1
1
1
CHAPTER 6 16-BIT RELOAD TIMER
6.4
Counter Operation Statuses
The CNTE bit in the control register and the internal signal WAIT determine the counter
status. The counter can be set to CNTE=0, WAIT=1 (the stop status), CNTE=1, WAIT=1
(activation trigger wait status [wait status]), CNTE=1, WAIT=0 (run status). Figure 6.4-1
shows status transition.
■ Counter Operation Statuses
Figure 6.4-1 Counter Status Transition
Reset
Status transition by hardware
Status transition by register access
STOP
CNTE=0,WAIT=1
Counter: Stop value held
(Not defined immediately after reset)
CNTE= '0'
WAIT
CNTE= '0'
CNTE= '1'
CNTE= '1'
TRG= '0'
TRG= '1'
CNTE=1,WAIT=1
RUN
Counter: Stop value held
(Not defined from immediately after
reset to loading)
CNTE=1,WAIT=0
Counter: Operating
RELD UF
TRG= '1'
TRG= '1'
RELD UF
LOAD
CNTE=1,WAIT=0
Load reload register contents
to counter
End of load
207
CHAPTER 6 16-BIT RELOAD TIMER
208
CHAPTER 7
PWM TIMER
This chapter gives an outline of the PWM timer and
explains the register configuration and functions and
the timer operations.
7.1 Outline of the PWM Timer
7.2 Block Diagram of the PWM Timer
7.3 Registers of the PWM Timer
7.4 PWM Mode
7.5 One-shot Mode
7.6 PWM Timer Interrupt Resources and Timing Charts
7.7 Activating Multiple PWM Timer Channels
209
CHAPTER 7 PWM TIMER
7.1
Outline of the PWM Timer
The PWM timer can efficiently output a highly accurate PWM waveform.
MB91121 contains the PWM timer for four channels.
Each channel consists of a 16-bit down counter, a 16-bit data register with cycle setting
buffer, a 16-bit compare register with duty setting buffer, and a pin control unit.
■ Features of the PWM Timer
• A count clock of the 16-bit down counter can be selected from four internal clocks.
- Internal clocks: φ, φ /4, φ /16, and φ /64
• The count value can be initialized to FFFFH by performing at reset and counter-borrow timings.
• PWM output is available for each channel.
• Registers
- Cycle setting register: Reload data register with buffer
- Duty setting register: Compare register with buffer
- Data is transferred from the buffer at a counter-borrow timing.
• Pin control
- Duty match sets a pin to 1 (priority).
- Counter-borrow resets a pin to 0.
- The fixed output value mode is available to enable easy output of all-L (or H).
- The polarity can also be specified.
• An interrupt request can be selected from the following combinations and then issued:
- PWM timer activation
- Counter-borrow (cycle match)
- Duty match
- Counter-borrow (cycle match) or duty match
• Concurrent activation of multiple channels can be set using software or other interval timer.
Reactivation during operation can also be set.
210
CHAPTER 7 PWM TIMER
7.2
Block Diagram of the PWM Timer
Figure 7.2-1 is a block diagram of the entire PWM timer. Figure 7.2-2 is a block diagram
of the PWM timer for one channel.
■ Block Diagram of the Entire PWM Timer
Figure 7.2-1 Block Diagram of the Entire PWM Timer
TRG input
16-bit reload timer
channel 0
PWM0
PWM timer channel 0
16-bit reload timer
channel 1
General control
register 2
General control
register 1
(resource selection)
4
TRG input
PWM1
PWM timer channel 1
TRG input
PWM2
PWM timer channel 2
External TRG0 to TRG3
4
TRG input
PWM3
PWM timer channel 3
211
CHAPTER 7 PWM TIMER
■ Block Diagram of the PWM Timer for One Channel
Figure 7.2-2 Block Diagram of the PWM Timer for One Channel Timer
PCSR
PDUT
Prescaler
1/1
1/4
1/16
1/64
cmp
ck
Load
16-bit
down counter
Start
Borrow
PPG masking
SQ
PWM output
R
Bit inversion
Enable
TRG
input
Edge
detection
Software trigger
212
Interrupt
selection
IRQ
CHAPTER 7 PWM TIMER
7.3
Registers of the PWM Timer
Figure 7.3-1 shows the registers of the PWM timer.
■ Registers of the PPG Timer
Figure 7.3-1 Registers of the PWM Timer
Address
15
0000DCH
0
GCN1
0000DFH
GCN2
R/W
General control register 1
R/W
General control register 2
0000E0H
PTMR0
R
Channel 0 timer register
0000E2H
PCSR0
W
Channel 0 cycle setting register
0000E4H
PDUT0
W
Channel 0 duty setting register
0000E6H
PCNH0
PCNL0
R/W
Channel 0 control status register
0000E8H
PTMR1
R
Channel 1 timer register
0000EAH
PCSR1
W
Channel 1 cycle setting register
0000ECH
PDUT1
W
Channel 1 duty setting register
0000EEH
PCNH1
PCNL1
R/W
Channel 1 control status register
0000F0H
PTMR2
R
Channel 2 timer register
0000F2H
PCSR2
W
Channel 2 cycle setting register
0000F4H
PDUT2
W
Channel 2 duty setting register
0000F6H
PCNH2
PCNL2
R/W
Channel 2 control status register
0000F8H
PTMR3
R
Channel 3 timer register
0000FAH
PCSR3
W
Channel 3 cycle setting register
0000FCH
PDUT3
W
Channel 3 duty setting register
0000FEH
PCNH3
PCNL3
R/W
Channel 3 control status register
213
CHAPTER 7 PWM TIMER
7.3.1
Control/Status Register (PCNH0 to PCNH3, PCNL0 to
PCNL3)
The control status registers (PCNH0 to PCNH3, PCNL0 to PCNL3) are used to control
the PWM timer and to indicate status. Note that these registers have bits that cannot be
rewritten during PWM timer operation.
■ Control/Status Register (PCNH0 to PCNH3, PCNL0 to PCNL3)
The control/status register (PCNH0 to PCNH3, PCNL0 to PCNL3) has the following configuration:
PCNH
bit
15
14
13
12
11
10
9
Address: ch0 0000E6H CNTE STGR MDSE RTRG CKS1 CKS0 PGMS
ch1 0000EEH R/W
8
-
R/W
R/W
R/W
R/W
R/W
R/W
-
←Attribute
ch2 0000F6H
0
0
0
0
0
0
0
-
←Initial value
ch3 0000FEH
❍
❍
×
×
×
×
❍
-
←Rewrite during operation
bit
7
6
5
4
3
2
1
0
PCNL
Address: ch0 0000E7H EGS1 EGS0 IREN IRQF
ch1 0000EFH R/W
IRS1
IRS0 POEN OSEL
R/W
R/W
R/W
R/W
R/W
R/W
R/W ←Attribute
ch2 0000F7H
0
0
0
0
0
0
0
0
←Initial value
ch3 0000FFH
×
×
❍
❍
×
×
×
×
←Rewrite during operation
Bit 15: CNTE (timer enable bit)
This bit is used to enable the operation of a 16-bit down counter.
0
Disable (initial value)
1
Enable
Bit 14: STGR (software trigger bit)
Writing 1 to this bit applies a software trigger.
The value read from the STGR bit is always 0.
Bit 13: MDSE (mode select bit)
This bit is used to select the PWM mode in which pulses are output continuously or the one-shot mode in
which a single pulse is output.
214
0
PWM mode (initial value)
1
One-shot mode
CHAPTER 7 PWM TIMER
Bit 12: RTRG (retrigger enable bit)
This bit is used to enable a retrigger by software trigger or trigger input.
0
Disable retrigger (initial value)
1
Enable retrigger
Bits 11 and 10: CKS1 and CKS0 (counter clock select bits)
These bits are used to select the count clock of the 16-bit down counter.
Table 7.3-1 Counter Clock Selection
CKS1
CKS0
Cycle
0
0
φ (initial value)
0
1
φ/ 4
1
0
φ/ 16
1
1
φ/ 64
φ: Peripheral machine clock
Bit 9: PGMS (PWM output mask select bit)
Writing 1 to this bit allows PWM output to be masked to 0 or 1 regardless of the mode, cycle, or duty
settings.
Table 7.3-2 PWM Output when 1 is Written to PGMS
Polarity
PWM output
Ordinary polarity
"L"
Inverted polarity
"H"
To output all-H in ordinary polarity mode and all-L in inverted polarity mode, write the same value to the
cycle setting register and duty setting register to output the above mask value in inverted form.
Bit 8: Unused bit
Bits 7 and 6: EGS1 and EGS0 (trigger input edge select bit)
These bits are used to select the effective edge of the activation resource selected in general control
register 1.
Writing 1 to the software trigger bit enables software trigger regardless of the selected mode.
Table 7.3-3 Trigger Input Edge Selection
EGS1
EGS0
Edge selection
0
0
Not effective (initial value)
0
1
Rising edge
1
0
Falling edge
1
1
Both edges
215
CHAPTER 7 PWM TIMER
Bit 5: IREN (interrupt request enable bit)
This bit is used to enable an interrupt request.
0
Disable (initial value)
1
Enable
Bit 4: IRQF (interrupt request flag)
When bit 5 (IREN) is enabled and an interrupt source selected by bits 3 and 2 (IRS1 and IRS0) is
generated, this bit is set to generate an interrupt to the CPU.
Writing 0 and a clear signal from DMAC clears this bit.
Even if 1 is written to this bit, the bit value remains unchanged.
The value read by a read-modify-write instruction is always 1 regardless of the bit value.
Bits 3 and 2: IRS1 and IRS0 (interrupt resource select bit)
These bits are used to select the resource that sets bit 4 (IRQF).
Table 7.3-4 Interrupt Resource Selection
IRS1
IRS0
Interrupt resource
0
0
Software trigger or trigger input (initial value)
0
1
Counter-borrow (cycle match)
1
0
Duty match
1
1
Counter-borrow (cycle match) or duty match
Bit 1: POEN (PWM output enable bit)
Setting 1 to this bit selects the PWM output pin.
216
0
General-purpose port (initial value)
1
PWM output pin
CHAPTER 7 PWM TIMER
Bit 0: OSEL (PWM output polarity specification bit)
This bit is used to set the PWM output polarity.
This bit is combined with bit 9 (PGMS) as follows:
Table 7.3-5 PWM Output Polarity and Edge Specification
PGMS
OSEL
0
0
Ordinary polarity (initial value)
0
1
Inverted polarity
1
0
Fixed "L" output
1
1
Fixed "H" output
Polarity
PWM output
After reset
Ordinary
polarity
"L" output
Inverted
polarity
"H" output
Duty match
Counter-borrow
217
CHAPTER 7 PWM TIMER
7.3.2
PWM Cycle Setting Register (PCSR0 to PCSR3)
The PWM cycle setting register (PCSR0 to PCSR3) has a buffer for cycle setting. Data is
transferred from the buffer at a counter-borrow timing.
■ PWM Cycle Setting Register (PCSR0 to PCSR3)
The PWM cycle setting register (PCSR0 to PCSR3) has the following configuration:
PCSR
bit
Address: ch0 0000E2H
ch1 0000EAH
ch2 0000F2H
ch3 0000FAH
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Attribute
→ Write only
Initial value → XXXXXXXX XXXXXXXXB
When the cycle setting register is initialized and rewritten, write data to the cycle setting register, then to
the duty setting register.
Access this register with 16-bit data.
218
CHAPTER 7 PWM TIMER
7.3.3
PWM Duty Setting Register (PDUT0 to PDUT3)
The PWM duty setting register (PDUT0 to PDUT3) has a buffer for duty setting. Data is
transferred from the buffer at a counter-borrow timing.
■ PWM Duty Setting Register (PDUT0 to PDUT3)
The PWM duty setting register (PDUT0 to PDUT3) has the following configuration:
PDUT
bit
Address: ch0 0000E4H
ch1 0000ECH
ch2 0000F4H
ch3 0000FCH
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Attribute
→ Write only
Initial value → XXXXXXXX XXXXXXXXB
If the same value is set in the cycle setting register and the duty setting register, all-H is output in standard
polarity mode and all-L in inverted polarity mode.
If the value set in PDUT is greater than the value set in PCSR, PWM output is undefined.
Access this register with 16-bit data.
219
CHAPTER 7 PWM TIMER
7.3.4
PWM Timer Register (PTMR0 to PTMR3)
The PWM timer register (PTMR0 to PTMR3) can be used to read the value of the 16-bit
down counter.
■ PWM Timer Register (PTMR0 to PTMR3)
The PWM timer register (PTMR0 to PTMR3) has the following configuration:
PTMR
bit
Address: ch0 0000E0H
ch1 0000E8H
ch2 0000F0H
ch3 0000F8H
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Attribute
→ Write only
Initial value → 11111111 11111111B
Access this register with 16-bit data.
220
CHAPTER 7 PWM TIMER
7.3.5
General Control Register 1 (GCN1)
General control register 1 (GCN1) is used to select the PWM timer trigger input
resource.
■ General Control Register 1 (GCN1)
General control register 1 (GCN1) has the following configuration:
GCN1
bit
15
Address: 0000DCH
bit
14
13
12
11
TSEL 33 to TSEL 30
10
9
8
TSEL 23 to TSEL 20
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
1
1
0
0
1
0
7
6
5
4
3
2
1
0
TSEL 13 to TSEL 10
←Attribute
←Initial value
TSEL 03 to TSEL 00
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
1
0
0
0
0
←Attribute
←Initial value
Bits 15 to 12: TSEL33 to TSEL30 (channel 3 trigger input select bits)
Table 7.3-6 Channel 3 Trigger Input Selection
TSEL33 to TSEL30
Channel 3 trigger input
15
14
13
12
0
0
0
0
GCN2 EN0 bit
0
0
0
1
GCN2 EN1 bit
0
0
1
0
GCN2 EN2 bit
0
0
1
1
GCN2 EN3 bit (initial value)
0
1
0
0
16-bit reload timer channel 0
0
1
0
1
16-bit reload timer channel 1
0
1
1
X
Setting prohibited
1
0
0
0
External TRG0
1
0
0
1
External TRG1
1
0
1
0
External TRG2
1
0
1
1
External TRG3
1
1
X
X
Setting prohibited
221
CHAPTER 7 PWM TIMER
Bits 11 to 8: TSEL23 to TSEL20 (channel 2 trigger input select bits)
Table 7.3-7 Channel 2 Trigger Input Selection
TSEL23 to TSEL20
Channel 2 trigger input
11
10
9
8
0
0
0
0
GCN2 EN0 bit
0
0
0
1
GCN2 EN1 bit
0
0
1
0
GCN2 EN2 bit (initial value)
0
0
1
1
GCN2 EN3 bit
0
1
0
0
16-bit reload timer channel 0
0
1
0
1
16-bit reload timer channel 1
0
1
1
X
Setting prohibited
1
0
0
0
External TRG0
1
0
0
1
External TRG1
1
0
1
0
External TRG2
1
0
1
1
External TRG3
1
1
X
X
Setting prohibited
Bits 7 to 4: TSEL13 to TSEL10 (channel 1 trigger input select bits)
Table 7.3-8 Channel 1 Trigger Input Selection
TSEL13 to TSEL10
Channel 1 trigger input
222
7
6
5
4
0
0
0
0
GCN2 EN0 bit
0
0
0
1
GCN2 EN1 bit (initial value)
0
0
1
0
GCN2 EN2 bit
0
0
1
1
GCN2 EN3 bit
0
1
0
0
16-bit reload timer channel 0
0
1
0
1
16-bit reload timer channel 1
0
1
1
X
Setting prohibited
1
0
0
0
External TRG0
1
0
0
1
External TRG1
1
0
1
0
External TRG2
1
0
1
1
External TRG3
1
1
X
X
Setting prohibited
CHAPTER 7 PWM TIMER
Bits 3 to 0: TSEL03 to TSEL00 (channel 0 trigger input select bits)
Table 7.3-9 Channel 0 Trigger Input Selection
TSEL03 to TSEL00
Channel 0 trigger input
3
2
1
0
0
0
0
0
GCN2 EN0 bit (initial value)
0
0
0
1
GCN2 EN1 bit
0
0
1
0
GCN2 EN2 bit
0
0
1
1
GCN2 EN3 bit
0
1
0
0
16-bit reload timer channel 0
0
1
0
1
16-bit reload timer channel 1
0
1
1
X
Setting prohibited
1
0
0
0
External TRG0
1
0
0
1
External TRG1
1
0
1
0
External TRG2
1
0
1
1
External TRG3
1
1
X
X
Setting prohibited
223
CHAPTER 7 PWM TIMER
7.3.6
General Control Register 2 (GCN2)
General control register 2 (GCN2) is used to enable software to generate an activation
trigger.
■ General Control Register 2 (GCR2)
General control register 2 (GCR2) has the following configuration:
GCN2
bit
7
6
5
4
3
2
1
0
Address: 0000DFH
-
-
-
-
EN3
EN2
EN1
EN0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W ←Attribute
0
0
0
0
0
0
0
0
←Initial value
If the EN bit in this register is selected by general control register 1 (GCR1), the register value is set in
PWM timer trigger input as is.
Software can be used to generate the edge selected by EGS1 and EGS0 bits in the control status register to
activate multiple PWM timer channels concurrently.
Always write 0 into bits 7 to 4 in this register.
224
CHAPTER 7 PWM TIMER
7.4
PWM Mode
In PWM mode, pulses can be continued to output after the activation trigger is detected.
The output pulse cycle can be controlled by changing the PCSR value, and the duty
ratio can be controlled by changing the PDUT value.
Always write data into PCSR, then into PDUT.
■ PWM Mode Timing Charts
● When retrigger is disabled
Figure 7.4-1 shows the PWM mode timing chart when retrigger is disabled.
Figure 7.4-1 PWM Mode Timing Chart (Retrigger Disabled)
Rising edge detection
Trigger ignored
Trigger
m
n
0
PWM
(1)
(2)
(1)
T
n
1
µs
T: Count clock cycle
(2)
T
m
1
µs
m: PCSR value
n: PDUT value
225
CHAPTER 7 PWM TIMER
● When retrigger is enabled
Figure 7.4-2 shows the PWM mode timing chart when retrigger is enabled.
Figure 7.4-2 PWM Mode Timing Chart (Retrigger Enabled)
Reactivated by trigger
Rising edge detection
Trigger
m
n
0
PWM
(1)
(2)
(1)
T
n
1
µs
T: Count clock cycle
(2)
T
m
1
µs
m: PCSR value
n: PDUT value
226
CHAPTER 7 PWM TIMER
7.5
One-shot Mode
In one-shot mode, the PWM timer can output a single pulse of an arbitrary width when
triggered.
When retrigger is enabled, the PWM timer reloads the counter value after edge
detection during operation.
■ One-shot Mode Timing Charts
● When retrigger is disabled
Figure 7.5-1 shows the one-shot mode timing chart when retrigger is disabled.
Figure 7.5-1 One-shot Mode Timing Chart (Retrigger Disabled)
Rising edge detection
Trigger ignored
Trigger
m
n
0
PWM
(1)
(2)
(1)
=
T (n + 1 ) µs
(2)
=
T (m + 1 ) µs
T: Count clock cycle
m: PCSR value
n: PDUT value
● When retrigger is enabled
Figure 7.5-2 shows the one-shot mode timing chart when retrigger is enabled.
Figure 7.5-2 One-shot Mode Timing Chart (Retrigger Enabled)
Rising edge detection
Reactivated by trigger
Trigger
m
n
0
PWM
(1)
(2)
(1)
=
T (n + 1 ) µs
(2)
=
T (m + 1 ) µs
T: Count clock cycle
m: PCSR value
n: PDUT value
227
CHAPTER 7 PWM TIMER
7.6
PWM Timer Interrupt Resources and Timing Charts
This section explains the interrupt resources and timing charts.
■ PWM Timer Interrupt Resources and Timing Chart (PWM Output is Ordinary Polarity)
Figure 7.6-1 shows the PWM timer interrupt resources and timing chart.
Figure 7.6-1 PWM Timer Interrupt Resources and Timing Chart (PWM Output: Standard Polarity)
Activation trigger
Up to 2.5T*
Load
Clock
Count value
X
0003
0002
0001
0000
0003
PWM
Interrupt
Effective edge
Duty match
Counter-borrow
*: Up to 2.5 T (T: Count clock cycle) is required until the counter value is loaded after applying the activation trigger.
■ All-L or All-H PWM Output Method
Figure 7.6-2 shows the all-L PWM output method, and Figure 7.6-3 shows the all-H PWM output method.
● Example of setting PWM output to all-"L" level
Figure 7.6-2 Example of Setting PWM Output to All-"L" Level
PWM
Reducing
the duty
228
An interrupt by borrow sets the mask bit
(PGMS) to 1. If an interrupt by borrow
clears the mask bit (PGMS) to 0, a PWM
waveform can be output without whisker.
CHAPTER 7 PWM TIMER
■ Example of Setting PWM Output to All-"H" Level
Figure 7.6-3 Example of Setting PWM Output to All-"H" Level
PWM
Increasing
An interrupt by compare match writes
the same value as the frequency setting
register into the duty setting register.
the duty
229
CHAPTER 7 PWM TIMER
7.7
Activating Multiple PWM Timer Channels
General control registers 1 and 2 (GCN1 and GCN2) can be used to activate multiple
PWM timer channels.
The activation trigger can be selected in the GCN1 register to activate multiple channels
concurrently.
This section provides an example of activation by software using the GCN2 register and
an example of activation using the 16-bit reload timer.
■ Activating Multiple PWM Timer Channels by Software
To effect a setting, proceed as follows:
1. Set the cycle in PCSR.
2. Set the duty in PDUT.
• Always write data into PCSR, then into PDUT.
3. Use GCN1 to determine the trigger input resource of the channel to be activated.
• Because GCN2 is used, maintain the initial setting in this step:
(channel 0 → EN0, channel 1 → EN1, channel 2 → EN2, channel 3 → EN3)
4. Set the control status register for the channel to be activated.
• CNTE: 1 → Enable timer operation.
• STGR: 0 → Because GCN2 is used for activation, the channels are not activated here.
• MDSE: 0 → PWM mode
• RTRG: 0 → Disable retrigger
• CSK1 and CSK0: 00 → Count clock = f
• PGMS: 0 → Not mask output: (Bit 8: 0 → Unused bit. Anything may be set)
• EGS1 and EGS0: 01 → Trigger rising edge
• IREN: 1 → Enable interrupt request
• IRQF: 0 → Clear interrupt resource
• IRS1 and IRS0: 01 → Generate interrupt request at a counter-borrow timing
• POEN: 1 → Enable PWM output
• OSEL: 0 → Standard polarity
5. Writing data into GCN2 generates activation trigger.
• To use the above setting to activate channels 0 and 1 concurrently, write 1 into EN0 and EN1 in
GCN2. The rising edge is generated and the pulses are output from PWM0 and PWM1.
■ Activating Multiple PWM Timer Channels Using the 16-bit Reload Timer
In the above setting step 3), use GCN1 to select the 16-bit reload timer as the resource, and in setting step
5), activate the 16-bit reload timer without using GCN2.
Set the control status register as follows:
RTRG: 1 → Enable retrigger
EGS1 and EGS0: 11 → Trigger both edges
The 16-bit reload timer output can be set to toggle output to reactivate the PWM timer at specified time
intervals.
230
CHAPTER 8
U-TIMER
This chapter explains an outline of the U-TIMER, the
register configuration and its functions, and U-TIMER
operations.
8.1 Outline of the U-TIMER
8.2 Registers of the U-TIMER
8.3 U-TIMER Operations
231
CHAPTER 8 U-TIMER
8.1
Outline of the U-TIMER
The U-TIMER is the 16-bit timer used to generate the UART baud rate. A combination of
chip operation frequency and U-TIMER reload value enables setting of any baud rate.
Because a count underflow generates an interrupt, the U-TIMER can also be used as the
interval timer.
M91121 contains this timer for three channels.
An interval of up to 216 × φ can be counted.
■ Block Diagram of the U-TIMER
Figure 8.1-1 is a block diagram of the U-TIMER.
Figure 8.1-1 Block Diagram of the U-TIMER
15
0
UTIMR (reload register)
15
load
0
UTIM (timer)
φ
(Peripheral clock)
clock
underflow
control
f.f.
to UART
■ Registers of the U-TIMER
Figure 8.1-2 lists the registers of the U-TIMER.
Figure 8.1-2 Registers of the U-TIMER
15
8 7
0
UTIM
(R)
UTIMR
(W)
UTIMC
232
(R/W)
CHAPTER 8 U-TIMER
8.2
Registers of the U-TIMER
The U-TIMER has the following three registers:
• U-TIMER value register (UTIM0 to UTIM2)
• Reload register (UTIMR0 to UTIMR2)
• U-TIMER control register (UTIMC0 to UTIMC2)
■ U-TIMER Value Register: UTIM (U-TIMER)
UTIM indicates the timer value. Access this register with a 16-bit transfer instruction.
UTIM0 to UTIM2
Channel 0 address: 000078H
15
14
2
1
0
b15
b14
b2
b1
b0
Channel 1 address: 00007CH
R
Access
Channel 2 address: 000080H
0
Initial value
■ Reload Register: UTIMR (Reload Register)
UTIMR is the register used to store the value to be reloaded to UTIM when UTIM underflows.
Access this register with a 16-bit transfer instruction.
UTIMR0 to UTIMR2
Channel 0 address: 000078H
15
14
2
1
0
b15
b14
b2
b1
b0
Channel 1 address: 00007CH
W
Access
Channel 2 address: 000080H
0
Initial value
Note:
When U-TIMER is used as a baud rate in the UART mode 2 (CLK synchronous mode), the setting of
UTIMR=0 is prohibited.
■ U-TIMER Control Register: UTIMC (U-TIMER Control Register)
UTIMC controls U-TIMER operations.
UTIMC0 to UTIMC2
7
6
5
4
3
2
1
0
Channel 0 address: 00007BH
UCC1
-
-
UTIE UNDR CLKS UTST UTCR
Channel 1 address: 00007FH
R/W
-
-
R/W
R/W
R/W
R/W
R/W
Access
Channel 2 address: 000083H
0
-
-
0
0
0
0
1
Initial value
233
CHAPTER 8 U-TIMER
Bit 7: UCC1 (U-TIMER Count Control 1)
The UCC1 bit is used to control how the U-TIMER counts.
0
Ordinary operation.
α = 2n + 2 [Initial value]
1
+1 mode
α = 2n + 3
n: UTIMR setting value
a : Cycle of output clock for UART
The U-TIMER enables setting of an ordinary 2-cycle (n + 1) clock and odd division for UART.
Setting UCC1 to 1 generates 2n + 3 cycles.
[Setting example]
UTIMR = 5, UCC1 = 0 → Generated cycle = 2n +2 = 12 cycles
UTIMR = 25, UCC1 = 1 → Generated cycle = 2n + 3 = 53 cycles
UTIMR = 60, UCC1 = 0 → Generated cycle = 2n + 2 = 122 bytes
To use the U-TIMER as the interval timer, set the UCC1 value to 0.
Bits 6 and 5: Reserved
Bit 4: UTIE (U-TIMER Interrupt Enable)
The UTIE bit is used to enable an interrupt when a U-TIMER underflows.
0: Disable interrupt [initial value]
1: Enable
Bit 3: UNDR (UNDeR flow flag)
The UNDR flag indicates that an underflow has occurred. When UTIE is set to 1 and UNDR is set, an
underflow interrupt is generated.
Resetting or writing 0 clears UNDR. When the read-modify-write instruction is read, 1 is always read.
Writing 1 into UNDR is invalid.
Bit 2: CLKS (clock select)
In this model, always set 0.
Bit 1: UTST (U-TIMER STart)
This bit is used to enable U-TIMER operations.
0: Disable: Writing 0 stops the operation of the U-TIMER (initial value).
1: Enable: Writing 1 continues the operation of the U-TIMER.
Bit 0: UTCR (U-TIMER CleaR)
Writing 0 into UTCR clears the U-TIMER to 0000H (flip-flop is also cleared to 0).
A value of 1 is always read.
Notes:
• Asserting (starting) the start bit UTST from the stop status automatically effects reloading.
• Asserting the clear bit UTCR and start bit UTST concurrently from the stop status clears the
counter to 0 and results in an underflow immediately after decrementing the counter.
• Asserting the clear bit UTCR during operation also clears the counter to 0. A short pulse with a
whisker may be output to the output waveform and UART may malfunction. If the output clock is
used, do not use the clear bit to clear the counter during operation.
234
CHAPTER 8 U-TIMER
8.3
U-TIMER Operations
This section explains how to calculate the U-TIMER baud rate.
■ Calculating the Baud Rate
UART uses the underflow flip-flop (f.f in the diagram) of the corresponding U-TIMER (U-TIMERx →
UARTx, x=0, 1, 2) as the baud rate clock resource.
● Asynchronous (start-stop) mode
UART divides the U-TIMER output by 16.
φ
bps =
When UCC1 = 0
(2n+2)
16
φ
bps =
(2n+3)
n : UTIMR (reload value)
φ : Peripheral machine clock frequency
(varies depending on gear)
When UCC1 = 1
16
● Clock synchronous mode
b ps =
φ
When UCC1 = 0
(2n+2)
bps =
φ
n : UTIMR (reload value)
φ : Peripheral machine clock frequency
(varies depending on gear)
When UCC1 = 1
(2n+3 )
Note:
When U-TIMER is used as a baud rate in the UART mode 2 (CLK synchronous mode), the setting of
UTIMR=0 is prohibited.
235
CHAPTER 8 U-TIMER
236
CHAPTER 9
EXTERNAL INTERRUPT/NMI
CONTROL SECTION
This chapter gives an outline of the external interrupt/
NMI control section and explains the register
configuration and functions and the section operations.
9.1 Outline of the External Interrupt/NMI Control Section
9.2 Registers of the External Interrupt/NMI Control Section
9.3 External Interrupt Processing
9.4 External Interrupt Request Level
9.5 Non-maskable Interrupt (NMI) Processing
237
CHAPTER 9 EXTERNAL INTERRUPT/NMI CONTROL SECTION
9.1
Outline of the External Interrupt/NMI Control Section
The external interrupt/NMI control section controls external interrupt request input into
NMIX and INT0 to INT7.
The request detection level can be selected from H, L, rising edge, and falling edge
(other than NMI).
■ Block Diagram of the External Interrupt/NMI Control Section
Figure 9.1-1 shows a block diagram of the external interrupt/NMI control section.
Figure 9.1-1 Block Diagram of the External Interrupt/NMI Control Section
RB US
8
Interrupt request
238
9
Interrupt enable register
Gate
Resource F/F
8
Interrupt resource register
8
Request level setting register
Edge detection circuit
5
INT0 to INT7
NMIX
CHAPTER 9 EXTERNAL INTERRUPT/NMI CONTROL SECTION
9.2
Registers of the External Interrupt/NMI Control Section
Figure 9.2-1 shows the registers of the external interrupt/NMI control section.
■ Registers of the External Interrupt/NMI Control Section
Figure 9.2-1 Registers of the External Interrupt/NMI Control Section
Bit
7
6
5
4
3
2
1
0
EN7
EN6
EN5
EN4
EN3
EN2
EN1
EN0
Enable interrupt request register (ENIR)
000095H [R/W]
Bit
15
14
13
12
11
10
9
8
ER7
ER6
ER5
ER4
ER3
ER2
ER1
ER0
External interrupt request register (EIRR)
000094H [R/W]
Bit
15
14
13
12
11
10
9
8
LB7
LA7
LB6
LA6
LB5
LA5
LB4
LA4
External level register (ELVR)
000098H [R/W]
Bit
7
6
5
4
3
2
1
0
LB3
LA3
LB2
LA2
LB1
LA1
LB0
LA0
External level register (ELVR)
000099H [R/W]
239
CHAPTER 9 EXTERNAL INTERRUPT/NMI CONTROL SECTION
9.2.1
Enable Interrupt Request Register (ENIR)
The enable interrupt request register (ENIR) controls the masking of external interrupt
request output.
■ ENable Interrupt Request Register (ENIR)
The enable interrupt request register (ENIR) has the following configuration:
ENIR
7
6
5
4
3
2
1
0
Initial value
Address: 000095H EN7 EN6 EN5 EN4 EN3 EN2 EN1 EN0 00000000B
Access
R/W
The enable interrupt request register (ENIR) controls the masking of external interrupt request output.
When a bit in this register is set to 1, its corresponding interrupt request output is enabled (INT0 controlled
by EN0) and a request is output to the interrupt controller. When a bit in this register is set to 0, its
corresponding pin holds an error resource but does not issue a request to the interrupt controller.
The register has no mask bit for non-maskable interrupt (NMI).
240
CHAPTER 9 EXTERNAL INTERRUPT/NMI CONTROL SECTION
9.2.2
External Interrupt Request Register (EIRR)
The external interrupt request register (EIRR) indicates the presence of a corresponding
external interrupt request when reading and clears the contents of the flip-flop that
shows this request when writing.
■ External Interrupt Request Register (EIRR)
The external interrupt request register (EIRR) has the following configuration:
EIRR
15
14
13
12
11
10
9
8
Initial value
Address: 000094H ER7 ER6 ER5 ER4 ER3 ER2 ER1 ER0 00000000B
Access
R/W
The external interrupt request register (EIRR) indicates the presence or absence of a corresponding external
interrupt request when read and clears the contents of the request flip-flop when written.
If the read value of this register is 1, there is an external interrupt request to the pin corresponding to this
bit.
When 0 is written into this register, the request flip-flop of the corresponding bit is cleared.
Writing 1 has no effect.
The read value by a read-modify-write instruction is 1.
The user cannot read or write the NMI flag.
241
CHAPTER 9 EXTERNAL INTERRUPT/NMI CONTROL SECTION
9.2.3
External Level Register (ELVR)
The external level register (ELVR) is used to select request detection.
■ External LeVel Register (ELVR)
The external level register (ELVR) has the following configuration:
ELVR
15
14
13
12
11
10
9
8
Address: 000098H LB7 LA7 LB6 LA6 LB5 LA5 LB4 LA4
7
6
5
4
3
2
1
Initial value
Access
00000000B
R/W
00000000B
R/W
0
Address: 000099H LB3 LA3 LB2 LA2 LB1 LA1 LB0 LA0
The external level register (ELVR) is used to select request detection.
Two bits are allocated each from INT0 to INT7 as shown in Table 9.2-1.
If request input level is active even after each EIRR bit is cleared, the corresponding bits are set again.
Table 9.2-1 Allocation of External Interrupt Request Levels
LB7 to LB0
LA7 to LA0
0
0
1
1
0
1
0
1
Operation
Request on the "L" level
Request on the "H" level
Request at the rising edge
Request at the falling edge
An NMI is always detected by the falling edge (except in the stop status). In the stop status, the "L" level is
detected.
242
CHAPTER 9 EXTERNAL INTERRUPT/NMI CONTROL SECTION
9.3
External Interrupt Processing
If a request set in the ELVR register is input to the corresponding pin after the external
level register (ELVR) and enable interrupt request register (ENIR) are set, this module
generates an interrupt request signal to the interrupt controller.
■ External Interrupt Processing
The priorities of interrupts generated simultaneously in the interrupt controller are identified. If the
interrupt from this resource has the highest priority, the corresponding interrupt occurs.
Figure 9.3-1 shows the external interrupt processing.
Figure 9.3-1 External Interrupt Processing
External interrupt
Interrupt controller
CPU
Resource request
ELVR
ICR yy
EIRR
ENIR
IL
CMP
ICRxx
CMP
ILM
Resource
■ Returning from the Stop Status
When using an external interrupt for return from the stop status in the clock stop mode, set the input request
level to "H". A "L" level request may cause a malfunction.
An edge request cannot be used for return from the stop status in the clock stop mode.
■ External Interrupt Procedure
Set the registers in the external interrupt section as follows:
1. The general-purpose I/O port that is shared with the pin as using the external interrupt input is set to the
input port.
2. Disable the corresponding bit in the enable interrupt request register.
3. Set the corresponding bit in the external level register.
4. Clear the corresponding bit in the external interrupt request register.
5. Enable the corresponding bit in the enable interrupt request register.
The settings of 4. and 5. can be executed together using 16-bit data.
When setting registers in this module, be sure to disable the enable interrupt request register.
Before enabling the enable interrupt request register, be sure to clear the external interrupt request register.
This is to avoid an erroneous interrupt resource when registers are set or the interrupt request is enabled.
243
CHAPTER 9 EXTERNAL INTERRUPT/NMI CONTROL SECTION
9.4
External Interrupt Request Level
When the request detection level is set to rising or falling edge, the pulse width should
be at least three machine cycles (peripheral clock machine cycles).
When the request detection level is set to high or low level, a external request to the
interrupt controller remains active even canceled later because the interrupt resource is
not cleared from the resource hold circuit inside.
To cancel a request to the interrupt controller, the external interrupt request register
should be cleared.
■ External Interrupt Request Level
Figure 9.4-1 shows clearance of the resource hold circuit at level setting and Figure 9.4-2 shows an
interrupt resource and an interrupt request to the interrupt controller when interrupt is enabled.
Figure 9.4-1 Clearance of the Resource Hold Circuit at Level Setting
Interrupt input
Level detection
Resource F/F
(resource hold circuit)
Enable gate
To interrupt controller
Resource held until cleared
Figure 9.4-2 Interrupt Resource and Interrupt Request to the Interrupt Controller when Interrupt is
Enabled
"H" level
Interrupt input
Interrupt request to
interrupt controller
244
Deactivated by clearance of resource F/F
CHAPTER 9 EXTERNAL INTERRUPT/NMI CONTROL SECTION
■ Notes If Restoring from Clock Generation STOP Status Performed Using an External
Interrupt
During the clock generation STOP status, external interrupt signals that are first entered to the INT terminal
are entered asynchronously, to enable recovery from the STOP status. The period from that STOP being
released to the passage of oscillation stabilization wait time, however, there is a period during which other
external interrupt signal inputs cannot be identified. (Period b+c for Figure 9.4-3.) To synchronize external
input signals after the STOP has been released with the internal clock, while the clock is not stable,
interrupt requests cannot be stored.
Consequently, if sending external interrupt inputs after the STOP has been released, input external interrupt
signals after the oscillation stabilization wait time has elapsed.
The following example shows how INT1, used for level detection, is inputted after INT0, used for edge
detection. The input level inputted during oscillation stabilization wait time will not be detected.
Figure 9.4-3 Recovery Operation Sequence Using External Interrupts from STOP Status
INT1
INT0
Internal STOP
Internal operation (RUN)
Implement command (run)
Internal Clock
Interrupt flag clear
Interrupt request bit ER0
Interrupt request bit ER1
(c) Oscillation stabilization time
(a)STOP
(b) Oscillator oscillation time
245
CHAPTER 9 EXTERNAL INTERRUPT/NMI CONTROL SECTION
■ Recovery Operations from STOP Status
The STOP recovery operation using external interrupts from existing circuits is performed as described
below.
● Processing before changing to STOP
External Interrupt Configuration
The interrupt input path in the STOP status must be permitted before the device enters the STOP status.
Therefore, set the corresponding external interrupt input pin to a port input.
• External Interrupt Inputs
If recovering from STOP status, the external interrupt signals are asynchronous. When this interrupt
input is asserted, the internal STOP signal is immediately turned OFF. At the same time, the external
interrupt circuit is switched so as to synchronize other level interrupt inputs.
● Oscillator Oscillation Time
After detecting the external interrupt, the clock will start to oscillate. The oscillator oscillation time
depends on the oscillator used.
● Oscillation Stabilization Wait Time
After the oscillator oscillation time, an oscillation stabilization wait time is taken inside the device. The
oscillation stabilization wait time is specified by bits OS1 and OS0 on the standby control register. After
the oscillation stabilization wait time has ended, the internal clock is supplied, and in addition to the
activation of interrupt command operations from the external interrupt, it also becomes possible to
receive external interrupt requests other than the recovery from STOP request.
246
CHAPTER 9 EXTERNAL INTERRUPT/NMI CONTROL SECTION
9.5
Non-maskable Interrupt (NMI) Processing
NMI has the highest priority among user interrupts and cannot be masked. This
interrupt is exceptionally masked from immediately after reset until ILM setting.
■ NMI Processing
An NMI is accepted at the following timings:
• Ordinary status: Falling edge
• Stop status: Low level
An NMI can release the stop status. If a "L" level signal is input in the top status, the stop status is released
and the stabilization of oscillation is awaited.
If the NMIX pin is returned to a high level after the oscillation stabilization time, the NMI resource is
cleared and the NMI processing is not executed after restart. To execute the NMI processing after restart,
keep the NMIX pin at a low level and return the level to high only in the NMI processing routine.
The NMI request detection section has an NMI bit that is set by an NMI request and cleared by interrupt of
the NMI itself or reset. This bit cannot be read or written.
Figure 9.5-1 shows the NMI request detection section.
Figure 9.5-1 NMI Request Detection Section
0
NMI request
(stop status release)
Falling edge
detection
Q SX
R
1
NMIX
φ
STOP
clear (RST, interrupt acknowledge)
247
CHAPTER 9 EXTERNAL INTERRUPT/NMI CONTROL SECTION
248
CHAPTER 10
DELAYED INTERRUPT
MODULE
This chapter gives an outline of the delayed interrupt
module and explains the register configuration and
functions and the module operations.
10.1 Outline of the Delayed Interrupt Module
10.2 Delayed Interrupt Control Register (DICR)
10.3 Operations of the Delayed Interrupt Module
249
CHAPTER 10 DELAYED INTERRUPT MODULE
10.1
Outline of the Delayed Interrupt Module
The delayed interrupt module generates a task switching interrupt.
This module enables software to issue or cancel an interrupt request to the CPU.
■ Block Diagram of the Delayed Interrupt Module
Figure 10.1-1 shows a block diagram of the delayed interrupt module.
Figure 10.1-1 Block Diagram of the Delayed Interrupt Module
WRITE
Resource request
ICR
IL
CMP
DICR
CMP
ICR
Delayed interrupt
ILM
CPU
Interrupt controller
■ Registers of the Delayed Interrupt Module
Figure 10.1-2 shows the registers of the delayed interrupt module.
Figure 10.1-2 Registers of the Delayed Interrupt Module
Address: 000430H
250
bit 7
6
5
4
3
2
1
0
-
-
-
-
-
-
-
DLYI
DICR [R/W]
CHAPTER 10 DELAYED INTERRUPT MODULE
10.2
Delayed Interrupt Control Register (DICR)
The delayed interrupt control register (DICR) controls a delayed interrupt.
■ Delayed Interrupt Control Register (DICR)
The delayed interrupt control register (DICR) has the following register configuration:
bit 7
6
5
4
3
2
1
0
-
-
-
-
-
-
-
DLYI
Address: 000430H
-------0B
R/W
(Initial value)
[R/W]
Bit 0: DPLY1
0
Release or delayed interrupt resource or no request (Initial value)
1
Generation of delayed interrupt resource
This bit controls the generation or release of the corresponding resource.
251
CHAPTER 10 DELAYED INTERRUPT MODULE
10.3
Operations of the Delayed Interrupt Module
The delayed interrupt module generates a task switching interrupt.
This module enables software to issue or cancel an interrupt request to the CPU.
■ Interrupt Number
The delayed interrupt is allocated to the interrupt resource of the greatest interrupt number.
In this product having 48 resources, the interrupt is allocated to interrupt No. 63 (3FH).
■ DLYI Bit in DICR
A delayed interrupt resource is generated when this bit is set to 1 and cleared when set to 0.
This bit has the same function as the interrupt resource for a general interrupt. Clear this bit and switch the
task in the interrupt routine.
252
CHAPTER 11
INTERRUPT CONTROLLER
This chapter provides an outline of the interrupt
controller and explains the register configuration and
functions and provides an example of using the hold
request cancel function.
11.1 Outline of the Interrupt Controller
11.2 Block Diagram of the Interrupt Controller
11.3 Registers of the Interrupt Controller
11.4 Priority Judgment
11.5 Return from Standby Mode (Stop or Sleep)
11.6 Hold Request Cancel Request
11.7 Using the Hold Request Cancel Register (HRCR)
253
CHAPTER 11 INTERRUPT CONTROLLER
11.1
Outline of the Interrupt Controller
In the FR30 Series, the interrupt controller is in charge of interrupt reception and
arbitration processing.
■ Hardware Configuration of the Interrupt Controller
This module consists of the following registers and circuits:
• ICR register
• Interrupt priority judgment circuit
• Interrupt level and interrupt number (vector) generator
• Hold request cancel request generator
■ Main Functions of the Interrupt Controller
This module has the following functions:
• NMI/interrupt request detection
• Priority judgment (by level and number)
• Transmission of resource interrupt level (to CPU)
• Transmission of resource interrupt number (to CPU)
• Return from stop mode by NMI/interrupt
• Hold request cancel request to bus master
254
CHAPTER 11 INTERRUPT CONTROLLER
11.2
Block Diagram of the Interrupt Controller
Figure 11.2-1 shows a block diagram of the interrupt controller.
■ Block Diagram of the Interrupt Controller
Figure 11.2-1 Block Diagram of the Interrupt Controller
INTO*2
IM
Priority judgment
OR
5
NMI
processing
LVL4 to LVL0
4
Level judgment
ICR00
RI00
Vector
judgment
ICR47
6
Level, vector generation
NMI
Hold
request
cancel
request
HLDCAN*3
VCT5 to VCT0
RI47
(DLYIRQ)
DLYI*1
R-bus
*1: DLYI is the delayed interrupt section. (For details, see "CHAPTER 10 DELAYED INTERRUPT MODULE".)
*2: INT0 is a wakeup signal to the clock controller in the sleep or stop status.
*3: HLDCAN is a bus transfer request signal to a bus master other than CPU.
255
CHAPTER 11 INTERRUPT CONTROLLER
11.3
Registers of the Interrupt Controller
Figure 11.3-1 lists the registers of the interrupt controller.
■ Registers of the Interrupt Controller
Figure 11.3-1 lists the registers of the interrupt controller.
Figure 11.3-1 Registers of the Interrupt Controller
256
bit7
6
5
4
3
2
1
0
Address: 000400H
-
-
-
ICR4
ICR3
ICR2
ICR1
ICR0
ICR00
Address: 000401H
-
-
-
ICR4
ICR3
ICR2
ICR1
ICR0
ICR01
Address: 000402H
-
-
-
ICR4
ICR3
ICR2
ICR1
ICR0
ICR02
Address: 000403H
-
-
-
ICR4
ICR3
ICR2
ICR1
ICR0
ICR03
Address: 000404H
-
-
-
ICR4
ICR3
ICR2
ICR1
ICR0
ICR04
Address: 000405H
-
-
-
ICR4
ICR3
ICR2
ICR1
ICR0
ICR05
Address: 000406H
-
-
-
ICR4
ICR3
ICR2
ICR1
ICR0
ICR06
Address: 000407H
-
-
-
ICR4
ICR3
ICR2
ICR1
ICR0
ICR07
Address: 000408H
-
-
-
ICR4
ICR3
ICR2
ICR1
ICR0
ICR08
Address: 000409H
-
-
-
ICR4
ICR3
ICR2
ICR1
ICR0
ICR09
Address: 00040AH
-
-
-
ICR4
ICR3
ICR2
ICR1
ICR0
ICR10
Address: 00040BH
-
-
-
ICR4
ICR3
ICR2
ICR1
ICR0
ICR11
Address: 00040CH
-
-
-
ICR4
ICR3
ICR2
ICR1
ICR0
ICR12
Address: 00040DH
-
-
-
ICR4
ICR3
ICR2
ICR1
ICR0
ICR13
Address: 00040EH
-
-
-
ICR4
ICR3
ICR2
ICR1
ICR0
ICR14
Address: 00040FH
-
-
-
ICR4
ICR3
ICR2
ICR1
ICR0
ICR15
Address: 000410H
-
-
-
ICR4
ICR3
ICR2
ICR1
ICR0
ICR16
Address: 000411H
-
-
-
ICR4
ICR3
ICR2
ICR1
ICR0
ICR17
Address: 000412H
-
-
-
ICR4
ICR3
ICR2
ICR1
ICR0
ICR18
Address: 000413H
-
-
-
ICR4
ICR3
ICR2
ICR1
ICR0
ICR19
Address: 000414H
-
-
-
ICR4
ICR3
ICR2
ICR1
ICR0
ICR20
Address: 000415H
-
-
-
ICR4
ICR3
ICR2
ICR1
ICR0
ICR21
Address: 000416H
-
-
-
ICR4
ICR3
ICR2
ICR1
ICR0
ICR22
Address: 000417H
-
-
-
ICR4
ICR3
ICR2
ICR1
ICR0
ICR23
Address: 000418H
-
-
-
ICR4
ICR3
ICR2
ICR1
ICR0
ICR24
R/W
R/W
R/W
R/W
R/W
CHAPTER 11 INTERRUPT CONTROLLER
Figure 11.3-1 Registers of the Interrupt Controller (Continued)
bit7
6
5
4
3
2
1
0
Address: 000419H
-
-
-
ICR4
ICR3
ICR2
ICR1
ICR0
ICR25
Address: 00041AH
-
-
-
ICR4
ICR3
ICR2
ICR1
ICR0
ICR26
Address: 00041BH
-
-
-
ICR4
ICR3
ICR2
ICR1
ICR0
ICR27
Address: 00041CH
-
-
-
ICR4
ICR3
ICR2
ICR1
ICR0
ICR28
Address: 00041DH
-
-
-
ICR4
ICR3
ICR2
ICR1
ICR0
ICR29
Address: 00041EH
-
-
-
ICR4
ICR3
ICR2
ICR1
ICR0
ICR30
Address: 00041FH
-
-
-
ICR4
ICR3
ICR2
ICR1
ICR0
ICR31
Address: 000420H
-
-
-
-
-
-
-
-
ICR32
Address: 000421H
-
-
-
-
-
-
-
-
ICR33
Address: 000422H
-
-
-
-
-
-
-
-
ICR34
Address: 000423H
-
-
-
-
-
-
-
-
ICR35
Address: 000424H
-
-
-
-
-
-
-
-
ICR36
Address: 000425H
-
-
-
-
-
-
-
-
ICR37
Address: 000426H
-
-
-
-
-
-
-
-
ICR38
Address: 000427H
-
-
-
-
-
-
-
-
ICR39
Address: 000428H
-
-
-
-
-
-
-
-
ICR40
Address: 000429H
-
-
-
-
-
-
-
-
ICR41
Address: 00042AH
-
-
-
-
-
-
-
-
ICR42
Address: 00042BH
-
-
-
-
-
-
-
-
ICR43
Address: 00042CH
-
-
-
-
-
-
-
-
ICR44
Address: 00042DH
-
-
-
-
-
-
-
-
ICR45
Address: 00042EH
-
-
-
-
-
-
-
-
ICR46
Address: 00042FH
-
-
-
ICR4
ICR3
ICR2
ICR1
ICR0
ICR47
R/W
R/W
R/W
R/W
R/W
LVL4
LVL3
LVL2
LVL1
LVL0
R/W
R/W
R/W
R/W
R/W
Address: 000431H
-
-
-
HRCL
257
CHAPTER 11 INTERRUPT CONTROLLER
11.3.1
Interrupt Control Register (ICR00 to ICR47)
The interrupt control register (ICR00 to ICR47) is prepared for each interrupt input and
is used to set the interrupt level of the corresponding interrupt request.
■ Interrupt Control Register (ICR00 to ICR47)
The interrupt control register (ICR00 to ICR47) has the following configuration:
000400H to
00042FH
bit7
6
5
4
3
2
1
0
-
-
-
ICR4
ICR3
ICR2
ICR1
ICR0
R
R/W
R/W
R/W
R/W
---11111B
(Initial value)
Bits 4 to 0: ICR4 to ICR0
These bits are used to specify the interrupt level of the corresponding interrupt request.
If the interrupt level set in this register is higher than the level mask value set in the ILM register of the
CPU, an interrupt request is masked on the CPU side. Reset initializes this register to 11111B.
Table 11.3-1 lists the values of the interrupt level setting bits and their corresponding interrupt levels.
Table 11.3-1 Values of Interrupt Level Setting Bits and Their Corresponding Interrupt
Levels
ICR4
ICR3
ICR2
ICR1
ICR0
0
0
0
0
0
0
0
1
1
1
0
14
0
1
1
1
1
15
NMI
1
0
0
0
0
16
Highest level
1
0
0
0
1
17
1
0
0
1
0
18
1
0
0
1
1
19
1
0
1
0
0
20
1
0
1
0
1
21
1
0
1
1
0
22
1
0
1
1
1
23
1
1
0
0
0
24
1
1
0
0
1
25
1
1
0
1
0
26
1
1
0
1
1
27
1
1
1
0
0
28
1
1
1
0
1
29
1
1
1
1
0
30
1
1
1
1
1
31
The ICR4 bit is fixed at 1 and cannot be set to 0.
258
Interrupt level
Reserved for system
(Strong)
(Weak)
No interrupt
CHAPTER 11 INTERRUPT CONTROLLER
11.3.2
Hold Request Cancel Request Level Setting Register
(HRCL)
The hold request cancel request level setting register (HRCL) is used to cancel a hold
request.
■ Hold Request Cancel Request Level Setting Register (HRCL)
The hold request cancel request level setting register (HRCL) has the following configuration:
Address:
7
6
5
4
3
2
1
0
000431H
-
-
-
LVL4
LVL3
LVL2
LVL1
LVL0
R/W
R/W
R/W
R/W
R/W
---11111B
(Initial value)
Bits 4 to 0: LVL4 to LVL0
These bits are used to set the interrupt level for issuing a hold request cancel request to the bus master.
If an interrupt request having a higher level than that set in this register is generated, a hold request
cancel request is issued to the bus master.
The LVL4 bit is fixed at 1 and cannot be set to 0.
259
CHAPTER 11 INTERRUPT CONTROLLER
11.4
Priority Judgment
This module selects an interrupt resource of the highest priority among resources
occurring simultaneously and outputs its interrupt level and interrupt number to the
CPU.
NMI has the highest priority among the interrupt resources handled by this module.
■ Priority Judgment
The priority judgment criteria for interrupt resources are as follows:
1. NMI
2. Resources satisfying the following conditions:
• Resources of interrupt levels other than "31" (no interrupt for "31")
• Resources of the smallest interrupt level
• Resource of the smallest interrupt number among above
Table 11.4-1 lists the interrupt resources, numbers, and levels.
Table 11.4-1 Interrupt Resources, Numbers, and Levels (1 / 2)
Interrupt No.
Interrupt resource
Interrupt level
Offset
Interrupt vector
address to
default TBR
Dec
Hex
NMI request
15
0F
15(FH) Fixed
3C0H
000FFFC0H
External interrupt 0
16
10
ICR00
3BCH
000FFFBCH
External interrupt 1
17
11
ICR01
3B8H
000FFFB8H
External interrupt 2
18
12
ICR02
3B4H
000FFFB4H
External interrupt 3
19
13
ICR03
3B0H
000FFFB0H
UART 0 reception complete
20
14
ICR04
3ACH
000FFFACH
UART 1 reception complete
21
15
ICR05
3A8H
000FFFA8H
UART 2 reception complete
22
16
ICR06
3A4H
000FFFA4H
UART 0 transmission complete
23
17
ICR07
3A0H
000FFFA0H
UART 1 transmission complete
24
18
ICR08
39CH
000FFF9CH
UART 2 transmission complete
25
19
ICR09
398H
000FFF98H
DMAC 0 (end, error)
26
1A
ICR10
394H
000FFF94H
DMAC 1 (end, error)
27
1B
ICR11
390H
000FFF90H
DMAC 2 (end, error)
28
1C
ICR12
38CH
000FFF8CH
DMAC 3 (end, error)
29
1D
ICR13
388H
000FFF88H
DMAC 4 (end, error)
30
1E
ICR14
384H
000FFF84H
DMAC 5 (end, error)
31
1F
ICR15
380H
000FFF80H
DMAC 6 (end, error)
32
20
ICR16
37CH
000FFF7CH
260
CHAPTER 11 INTERRUPT CONTROLLER
Table 11.4-1 Interrupt Resources, Numbers, and Levels (2 / 2)
Interrupt No.
Interrupt resource
Interrupt level
Offset
Interrupt vector
address to
default TBR
Dec
Hex
DMAC 7 (end, error)
33
21
ICR17
378H
000FFF78H
A/D (successive type)
34
22
ICR18
374H
000FFF74H
Reload timer 0
35
23
ICR19
370H
000FFF70H
Reload timer 1
36
24
ICR20
36CH
000FFF6CH
Reload timer 2
37
25
ICR21
368H
000FFF68H
PWM 0
38
26
ICR22
364H
000FFF64H
PWM 1
39
27
ICR23
360H
000FFF60H
PWM 2
40
28
ICR24
35CH
000FFF5CH
PWM 3
41
29
ICR25
358H
000FFF58H
U-TIMER 0
42
2A
ICR26
354H
000FFF54H
U-TIMER 1
43
2B
ICR27
350H
000FFF50H
U-TIMER 2
44
2C
ICR28
34CH
000FFF4CH
External interrupt 4
45
2D
ICR29
348H
000FFF48H
External interrupt 5
46
2E
ICR30
344H
000FFF44H
External interrupt 6
47
2F
ICR31
340H
000FFF40H
External interrupt 7
48
30
ICR32
33CH
000FFF3CH
DSP macro soft interrupt
49
31
ICR33
338H
000FFF38H
DSP macro offset interrupt
50
32
ICR34
334H
000FFF34H
Reserved for system
51
33
ICR35
330H
000FFF30H
Reserved for system
52
34
ICR36
32CH
000FFF2CH
Reserved for system
53
35
ICR37
328H
000FFF28H
Reserved for system
54
36
ICR38
324H
000FFF24H
Reserved for system
55
37
ICR39
320H
000FFF20H
Reserved for system
56
38
ICR40
31CH
000FFF1CH
Reserved for system
57
39
ICR41
318H
000FFF18H
Reserved for system
58
3A
ICR42
314H
000FFF14H
Reserved for system
59
3B
ICR43
310H
000FFF10H
Reserved for system
60
3C
ICR44
30CH
000FFF0CH
Reserved for system
61
3D
ICR45
308H
000FFF08H
Reserved for system
62
3E
ICR46
304H
000FFF04H
Delay interrupt bit
63
3F
ICR47
300H
000FFF00H
261
CHAPTER 11 INTERRUPT CONTROLLER
■ Non-maskable Interrupt (NMI)
An NMI has the highest priority in the interrupt resources handled by this module. An NMI is selected even
if other types of interrupt resources occur simultaneously.
● If an NMI occurs, the following information is reported to the CPU:
• Interrupt level: 15 (01111B)
• Interrupt number: 15 (001111B)
● NMI detection
The external interrupt/NMI control section sets and detects an NMI. This module generates only an
interrupt level and an interrupt number on NMI request.
■ Release of Interrupt Resource
The instruction to release an interrupt resource is distinguished from the RETI instruction in the interrupt
routine. For details, see Section "3.10 Exception, Interrupt, and Trap (EIT)".
262
CHAPTER 11 INTERRUPT CONTROLLER
11.5
Return from Standby Mode (Stop or Sleep)
This module has a function for returning from the stop mode when an interrupt request
occurs.
■ Return from Standby Mode (Stop or Sleep)
If even one peripheral request including NMI occurs, this module issues a request to the clock controller to
return from standby mode.
Since the priority judgment section does not start again until the clock supply recovers after return, the
CPU continues to execute instructions until a judgment result is obtained. Even after returning from the
sleep status, this module operates in the same way.
The registers in this module can be accessed in sleep mode.
Notes:
• Even an NMI request causes return from the stop status.
• To prevent an interrupt resource from returning from the stop or sleep status, disable the interrupt
request output in the corresponding peripheral control register. Since the request signal for return
from standby mode is a mere logical sum of all interrupt resources, the interrupt level set in the
ICR is not reflected.
• For DMA transfer in the sleep status, set the DMA side not to convey an interrupt request to this
module. This prevents erroneous return from the sleep status.
263
CHAPTER 11 INTERRUPT CONTROLLER
11.6
Hold Request Cancel Request
If it is necessary to process a high-priority interrupt in the CPU hold status, a hold
request issuer should cancel its hold request. An interrupt level should be set in the
HRCL register as the cancellation standard.
■ Cancellation Standard for Hold Request
If an interrupt resource or a higher interrupt level than that set in the HRCL register occurs, a hold request
cancel request is issued.
• Interrupt level set in HRCL register greater than Interrupt level after priority judgment ==> Cancel
request
• Interrupt level set in HRCL register smaller than or equal to Interrupt level after priority judgment ==>
No cancel request
This cancel request remains valid until the interrupt resource that resulted in the request is cleared. If a hold
request cancel request is issued during DMA transfer, the interrupt request is not cleared and the DMA
transfer remains pending. Therefore, be sure to clear the interrupt resource.
■ Available Levels of Hold Request Cancel Request
The HRCL register allows the setting range from 10000B to 11111B like the ICR register.
If 11111B is set, a cancel request is issued for every level of interrupt. If 10000B is set, a cancel request is
issued for a NMI only.
Table 11.6-1 lists the cancel-applicable interrupt levels.
Table 11.6-1 Cancel-applicable Interrupt Levels
HRCL register
Cancel-applicable interrupt level
16
NMI only
17
NMI or interrupt level 16
18
NMI or interrupt level 16 or 17
to
31
to
NMI or interrupt levels 16 to 30 (Initial value)
DMA transfer to all interrupt levels is suppressed after reset.
If an interrupt occurs, DMA transfer is not executed. Therefore, set the necessary value in the HRCL
register.
264
CHAPTER 11 INTERRUPT CONTROLLER
11.7
Using the Hold Request Cancel Register (HRCR)
To execute a high-priority processing during DMA transfer, the CPU should request the
DMA to cancel the hold request for releasing the hold status. This allows priority
processing by the CPU.
■ Control Registers
● Hold request cancel register (HRCR): This module
If an interrupt request of a higher level than that set in this register is generated, a hold request cancel
request is issued to the DMA. This register is used to set the standard level.
● Interrupt control register (ICR): This module
A higher level than that in the HRCL register should be set in the ICR register corresponding to the
interrupt resource.
● DMA request suppression register (PDRR): Clock controller
This register is used to suppress the hold request from the DMA temporarily. Clearing an interrupt resource
prevents a return to the hold status. Only when this register value is 0000B, a hold request from the DMA is
conveyed to the CPU. To use this register, increment the register at the entry of the interrupt routine and
decrement it at the exit.
■ Hardware Configuration
Each signal flow is as follows:
Figure 11.7-1 Hardware Configuration for Using the Hold Request Cancel Request
Clock controller
This module
DHRQ: DMA hold request
IRQ
(ICR)
DMA
CPU
HRQ: Hold request
IRQ: Interrupt request
(HRCL)
HRCR
DHRQ (PDRR)
HRQ
HRCR: Hold request cancel request
265
CHAPTER 11 INTERRUPT CONTROLLER
■ Hold Request Cancel Request Sequence
● Example of interrupt routine
Figure 11.7-2 Hold Request Cancel Request Sequence (Interrupt Level: HRCL > a)
RUN
Bus hold
Interrupt processing
Bus hold (DMA transfer)
Example of interrupt routine
CPU
DHRQ
PDRR increment
HRQ
Interrupt resource clearance
HACK
to
IRQ
PDRR decrement
LEVEL
a
RETI
HRCR
PDRR
0000
0001
0000
If an interrupt request is generated and the interrupt level becomes higher than that set in the HRCL
register, the HRCR becomes active for the DMA. Then the DMA cancels the hold request and the CPU
returns from the hold status for interrupt processing. The interrupt routine increments the PDRR value
and clears the interrupt resource . The interrupt level then changes, the HRCR becomes inactive, and the
DMA becomes ready to issue a hold request again. However, since the PDRR value is not 0, the hold
request output is blocked. When the PDRR is decremented
the first time and the DMA transfer starts again.
266
, the hold request is conveyed to the CPU for
CHAPTER 11 INTERRUPT CONTROLLER
● Example of multi-interrupt routine
Figure 11.7-3 Hold Request Cancel Request Sequence (Interrupt Level: HRCL > a > b)
RUN
Bus hold
Interrupt routine I
Interrupt routine II
Interrupt routine I
Bus hold
CPU
DHRQ
HRQ
HACK
IRQ1
IRQ2
LEVEL
a
b
a
HRCR
PDRR
0000
0001
0002
0001
0000
Example of interrupt routine
,
PDRR increment
,
Interrupt resource clearance
to
,
PDRR decrement
,
RETI
In the above example, an interrupt level of a higher priority occurs in interrupt routine I.
The PDRR should be incremented at entry of each interrupt routine and decremented
at the exit to prevent a hold request from being issued by mistake.
Notes:
• Be sure to increment and decrement the PDRR at the entry and exit of the interrupt routine to be
processed during the DMA transfer (CPU hold status). Otherwise, the DMA transfer will start
again in the middle of the interrupt routine.
• Do not increment or decrement the PDRR in an ordinary interrupt routine. Otherwise,
performance will deteriorate because DMA transfer cannot be executed in an interrupt routine.
• Note the relationship between the HRCL register and the ICR-set interrupt level.
267
CHAPTER 11 INTERRUPT CONTROLLER
268
CHAPTER 12
A/D CONVERTER
This chapter gives an outline of the A/D converter and
explains the register configuration and functions and
the converter operations.
12.1 Outline of the A/D Converter
12.2 Block Diagram of the A/D Converter
12.3 Registers of the A/D Converter
12.4 Operations of the A/D Converter
12.5 Converted Data Protection Function
12.6 Notes on Using the A/D Converter
269
CHAPTER 12 A/D CONVERTER
12.1
Outline of the A/D Converter
The A/D converter converts an analog input voltage into a digital value.
■ Features of the A/D Converter
• Minimum conversion time: 5.6 µs/channel (system clock: 25 MHz)
• Built-in sample & hold circuit
• Resolution: 10 bits
• Analog input selection from 8 channels by programming
- Single conversion mode: Selective conversion on a single channel.
- Scan conversion mode: Conversion on several consecutive channels (Up to 8 channels can be
programmed.)
- Continuous conversion mode: Repetitive conversion on a specified channel.
- Stop conversion mode: Pause after single-channel conversion and wait until next activation
(Conversion start can be synchronized.)
• DMA transfer start by interrupt
• Activation resource selectable from software, external trigger (falling edge), and reload timer (rising
edge)
270
CHAPTER 12 A/D CONVERTER
12.2
Block Diagram of the A/D Converter
Figure 12.2-1 shows a block diagram of the A/D converter.
■ Block Diagram of the A/D Converter
Figure 12.2-1 Block Diagram of the A/D Converter
AVCC
AVRH
AVRL
Internal voltage
generator
MPX
Successive
approximation register
Input circuit
AN0
AN1
AN2
AN3
AN4
AN5
AN6
AN7
AVSS
Comparator
R
Sample & hold circuit
Decoder
b
u
s
Data register
ADCR
A/D control register
External trigger activation
ADCS
ATGX
Timer activation
TIM2
(internal connection)
Operation clock
(Reload timer channel 2)
φ
(Peripheral clock)
Prescaler
271
CHAPTER 12 A/D CONVERTER
12.3
Registers of the A/D Converter
The A/D converter has the following two registers:
• Control status register (ADCS)
• Data register (ADCR)
■ Registers of the A/D Converter
Figure 12.3-1 shows the registers of the A/D converter.
Figure 12.3-1 Registers of the A/D Converter
15
0
ADCS
ADCR
16bit
bit
15
Address:00003AH BUSY
14
INT
13
12
11
10
9
INTE PAUS STS1 STS0 STRT
8
-
Control status register (ADCS)
[R/W]
bit
7
MD1
bit
Address:000038H
6
5
4
3
2
1
0
MD0 ANS2 ANS1 ANS0 ANE2 ANE1 ANE0
15
14
13
12
11
10
9
8
-
-
-
-
-
-
9
8
Data register (ADCR)
[R]
bit
272
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
CHAPTER 12 A/D CONVERTER
12.3.1
Control Status Register (ADCS)
The control status register (ADCS) controls the A/D converter and displays its status.
Do not rewrite this register during A/D conversion.
■ Control Status Register (ADCS)
The control status register (ADCS) has the following configuration:
ADCS
bit
Address: 00003AH
bit
15
14
BUSY
INT
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
7
6
5
4
3
2
1
MD1
13
12
11
10
9
INTE PAUS STS1 STS0 STRT
8
0
←Initial value
R/W ←Access
0
MD0 ANS2 ANS1 ANS0 ANE2 ANE1 ANE0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
←Initial value
R/W ←Access
Bit 15: BUSY (BUSY flag and stop)
Read: The A/D converter operation status is displayed.
This bit is set when the A/D converter is activated and cleared when it is terminated.
Write: Writing 0 into this bit forces the converter to terminate.
This bit is used to terminate the A/D converter forcibly in continuous or stop conversion mode.
The operation display bit cannot be set to 1. The read value by a read-modify-write (RMW) command is 1.
This bit is cleared at the end of A/D conversion in single conversion mode but not until 0 is written in
continuous or stop conversion mode.
Reset initializes this bit to 0.
Do not apply forced termination and software activation simultaneously (BUSY=0, STRT=1).
Bit 14: INT (INTerrupt)
This bit displays data. When converted data is written into ADCR, this bit is set.
If this bit is set when INTE (bit 13) is 1, an interrupt request is issued.
Writing 1 has no effect.
Writing 0 clears this bit.
Reset initializes this bit to 0.
The read value by a read-modify-write instruction is 1.
Note:
Write 0 into this bit to clear when the A/D converter is not in operation.
273
CHAPTER 12 A/D CONVERTER
Bit 13: INTE (INTerrupt Enable)
This bit enables or disables an interrupt at the end of conversion.
0: Disable interrupt
1: Enable interrupt
Reset initializes this bit to 0.
Bit 12: PAUS (A/D converter PAUSE)
This bit is set when A/D conversion is paused.
If data is converted continuously because there is only one register for storing conversion results, the
previous data will be destroyed without DMA transfer of the conversion results.
To prevent this problem, the next conversion data can be stored only after DMA transfer of the
conversion results. A/D conversion is paused during this transfer.
Once DMA has finished the transfer, A/D conversion starts again.
This bit is valid only when DMA is used.
For details, see Section "12.5 Converted Data Protection Function".
Reset initializes this bit to 0.
Bits 11 and 10: STS1, STS0 (STart Source select)
Reset initializes these bits to 00B.
These bits specify an A/D activation resource.
Table 12.3-1 Selection of A/D Converter Activation Resources
STS1
STS0
Function
0
0
Software activation
0
1
External trigger and software activation
1
0
Internal reload timer and software activation
1
1
External trigger, timer, and software activation
If two or three resources are set, the first resource activates the A/D converter.
Note that the activation resource changes immediately after the bit settings are changed.
Note:
For external triggering, the falling edge of an input signal is detected.
The A/D converter may be activated if this bit is rewritten to set external trigger activation when the
external trigger input level is low.
For timer activation, reload timer channel 2 is selected. If these bits are changed to timer activation
when the reload timer output level is high, the A/D converter may be activated.
Bit 9: STRT (STaRT)
Writing 1 into this bit activates the A/D converter.
For reactivation, write the bit again.
In stop mode, however, reactivation is prohibited functionally.
Reset initializes this bit to 0.
Do not apply forced termination and software activation simultaneously (BUSY=0, STRT=1).
The read value by a read-modify-write instruction is 0.
274
CHAPTER 12 A/D CONVERTER
Bit 8:
Test bit.
Write 0 when necessary.
Bits 7 and 6: MD1, MD0 (A/D converter MoDe set)
These bits specify an operation mode.
Table 12.3-2 Specifying A/D Converter Operation Mode
MD1
MD0
0
0
Single conversion mode (Reactivation always possible)
0
1
Single conversion mode (Reactivation not possible)
1
0
Continuous conversion mode (Reactivation not possible)
1
1
Stop conversion mode (Reactivation not possible)
Single conversion mode:
Operation mode
The A/D converter sequentially processes digital input from the channels
set on the ANS2 to ANS0 bits and the ANE2 to ANE0 bits and stops after
the specified end channel.
Continuous conversion mode:The A/D converter repeatedly processes digital input from the channels set
on the ANS2 to ANS0 bits and the ANE2 to ANE0 bits.
Stop conversion mode:
The A/D converter sequentially processes digital input from the channels
set on the ANS2 to ANS0 bits and the ANE2 to ANE0 bits and stops after
every channel.
Conversion restarts when the activation resource occurs.
Reset initializes these bits to 00.
Note:
Once the A/D converter has been activated in continuous or stop conversion mode, A/D conversion
continues until stopped by the BUSY bit.
A/D conversion stops when the BUSY bit is set to 0.
"Reactivation not possible" in single, continuous, and stop conversion modes applies to timer,
external trigger, and software activation.
275
CHAPTER 12 A/D CONVERTER
Bits 5 to 3: ANS2 to ANS0 (ANalog Start channel set)
These bits specify a channel from which to start A/D conversion.
When activated, the A/D converter starts processing from the specified channel.
Table 12.3-3 Setting of A/D Conversion Start Channel
ANS2
ANS1
ANS0
Start channel
0
0
0
AN0
0
0
1
AN1
0
1
0
AN2
0
1
1
AN3
1
0
0
AN4
1
0
1
AN5
1
1
0
AN6
1
1
1
AN7
When A/D conversion is in progress, the current channel is read from these bits. When A/D conversion is
stopped in stop mode, the previous channel is read.
Reset initializes these bits to 000B.
Bits 2 to 0: ANE2 to ANE0 (ANalog End channel set)
These bits specify a channel to end A/D conversion at.
Table 12.3-4 Setting of A/D Conversion End Channel
ANE2
ANE1
ANE0
End channel
0
0
0
AN0
0
0
1
AN1
0
1
0
AN2
0
1
1
AN3
1
0
0
AN4
1
0
1
AN5
1
1
0
AN6
1
1
1
AN7
If the channel set on the ANS2 to ANS0 bits is set, A/D conversion is executed on a single channel
(single conversion).
In continuous or stop conversion mode, the A/D converter returns from the channel set on these bits to
the one set on the ANS2 to ANS0 bits.
Set the ANS channel that is equal to or smaller than the ANE channel.
Reset initializes these bits to 000B.
276
CHAPTER 12 A/D CONVERTER
Example:
When channel 1 is set on the ANS bits and channel 3 is set on the ANE bits in single mode, the order of
the conversion channels will be 1, 2, 3.
Note:
Please do not set the A/D conversion mode setting bit (MD1,MD0) and the A/D conversion end
channel selection bit (ANE2, ANE1, ANE0) by the read-modify-write type instruction after setting the
start channel to the A/D conversion start channel selection bit (ANS2, ANS1, ANS0).
From ANS2, ANS1, and the ANS0 bit, the last conversion channel is read until starting the A/D
conversion. Therefore, when MD1, the MD0 bit, ANE2, ANE1, and the ANE0 bit are set by the readmodify-write type instruction after setting the start channel to ANS2, ANS1, and the ANS0 bit, the
value of ANE2, ANE1, and the ANE0 bit may be written.
277
CHAPTER 12 A/D CONVERTER
12.3.2
Data Register (ADCR)
The data register (ADCR) stores digital values resulting from conversion.
■ Data Register (ADCR)
The data register (ADCR) has the following configuration:
ADCR
bit
Address: 000038H
bit
15
14
13
12
11
10
9
8
-
-
-
-
-
-
9
8
-
-
-
-
-
-
X
X
←Initial value
R
R
R
R
R
R
R
R
←Access
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
X
X
X
X
X
X
X
X
←Initial value
R
R
R
R
R
R
R
R
←Access
This register is updated at the end of every conversion. Usually, the final conversion value is stored.
The reset status of this register is not defined.
The read values of the upper bits 15 to 10 are 0.
A converted data protection function is supported. For details, see Section "12.5 Converted Data Protection
Function".
278
CHAPTER 12 A/D CONVERTER
12.4
Operations of the A/D Converter
The A/D converter is of the successive approximation type and has a 10-bit resolution.
Since this converter has only one register (16 bits) to store a conversion result, the
register (ADCR) is updated at the end of each conversion. Therefore, DMA transfer is
necessary for continuous conversion.
■ A/D Converter Operation Modes
The A/D converter operates in single conversion mode, continuous conversion mode, or stop conversion
mode.
● Single conversion mode
In this mode, the A/D converter sequentially processes analog input channels set on the ANS and ANE bits
of ADCS. After reaching the specified end channel, the A/D converter stops after the specified end channel.
If the start and end channels are the same (ANS=ANE), only one channel is processed.
Example:
ANS=000 and ANE=011
Start → AN0 → AN1 → AN2 → AN3 → End
ANS=010 and ANE=010
Start → AN2 → End
● Continuous conversion mode
In this mode, the A/D converter sequentially processes analog input channels set on the ANS and ANE bits
in ADCS. After reaching the specified end channel, the A/D converter returns to ANS analog input and
continues processing.
If the start and end channels are the same (ANS=ANE), only one channel is processed repeatedly.
Example:
ANS=000 and ANE=011
Start → AN0 → AN1 → AN2 → AN3 → AN0 ...→ Repeat
ANS=010 and ANE=010
Start → AN2 → AN2 → AN2 ...→ Repeat
Once the A/D converter has been activated in continuous conversion mode, processing continues until
stopped until 0 is written into the BUSY bit.
Writing 0 into the BUSY bit forces the processing to terminate.
Note that this stops even conversion in progress.
In the case of forced termination, the converted data register maintains the previous converted data.
279
CHAPTER 12 A/D CONVERTER
● Stop conversion mode
In this mode, the A/D converter sequentially processes analog input channels set on the ANS and ANE bits
in ADCS and stops after every channel. To cancel a stop, activate the A/D converter again.
After reaching the end channel set on the ANE bits, the A/D converter returns to the ANS-specified analog
input and continues A/D conversion.
If the start and end channels are the same (ANS=ANE), only one channel is processed.
Example:
When ANS=000 and ANE=011
Start → AN0 → Stop → Activation → AN1 → Stop → Activation → AN2 →
Stop → Activation → AN3 → Stop → Activation → AN0 ...→ Repeat
When ANS=010 and ANE=010
Start → AN2 → Stop → Activation → AN2 → Stop → Activation → AN2 ...→ Repeat
280
CHAPTER 12 A/D CONVERTER
12.5
Converted Data Protection Function
The A/D converter features a converted data protection function to accumulate data by
continuous data conversion using DMAC.
■ Converted Data Protection Function
Since there is only one conversion data register, new data replaces the previous data at the end of each
conversion. To prevent this from occurring, the A/D converter has a converted data protection function. If
the previous data has not been transferred to memory using DMAC by the end of conversion, this function
prohibits the converted data from being stored in the register and suspends A/D conversion.
The pause status is released after DMA transfer to memory.
If the previous data has been transferred, the A/D converter continues processing without a pause.
Note:
The converted data protection function is related to the INT and INTE bits in ADCS.
This function operates only when interrupt is enabled (INTE=1). When interrupt is disabled (INTE=0),
this function does not operate. If A/D conversion is continued, converted data is stored in the register
and the previous data is lost.
If DMA is not used in the interrupt enabled status (INTE=1), the protection function is activated and
suspends A/D conversion. In this case, clearing the INT bit by the interrupt sequence releases the
pause status.
If interrupt is disabled when the A/D converter is suspended during DMA operation, the contents of
the converted data register may change before data transfer.
The standby data is lost if the A/D converter is reactivated from the pause status.
281
CHAPTER 12 A/D CONVERTER
Figure 12.5-1 shows the flow of the data protection function when DMA transfer is used.
Figure 12.5-1 Flow of Data Protection Function when DMA Transfer is Used
The flow when the A/D conversion operation stop is omitted.
DMAC setting
A/D conversion start in
continuous mode
End of first
conversion
Storage in data register
End of second
conversion
DMAC activation
*
NO
End of transfer?
A/D pause
YES
YES
Storage in data register
End of third
conversion
NO
End of transfer?
DMAC activation
Continued
End of all conversion
DMAC activation and transfer
DMAC termination
interrupt routine
End
A/D stop
*: Reactivation during a pause destroys data waiting to be converted.
282
CHAPTER 12 A/D CONVERTER
12.6
Notes on Using the A/D Converter
This section explains what to be noted when using the A/D converter.
■ Notes on Using the A/D Converter
● If an external trigger or the internal timer is used for activation
If an external trigger or the internal timer is used to activate the A/D converter, the A/D activation resource
bits (STS1 and STS0) in the ADCS register are set. For this setting, the input values of the external trigger
and the internal timer should be inactive. If the input values are active, the A/D converter may malfunction.
The STS1 and STS0 bits should be set when ATGX = 1 (input) and reload timer (channel 2) = 0 (output).
283
CHAPTER 12 A/D CONVERTER
284
CHAPTER 13
UART
This chapter gives an outline of the UART and explains
the register configuration and functions and the UART
operations.
13.1 Outline of UART
13.2 UART Block Diagram
13.3 UART Registers
13.4 UART Operation Modes and Clock Selection
13.5 UART Interrupts and Flag Setting Timings
13.6 Notes on Use with Example of UART Application
13.7 Examples of Setting Baud Rates and U-TIMER Reload Values
285
CHAPTER 13 UART
13.1
Outline of UART
UART is a serial I/O port for asynchronous (step-synchronous) or CLK synchronous
communication.
The MB91121 contains a three-channel UART.
■ Features of UART
• Full-duplex double buffer
• Asynchronous (step-synchronous) communication or CLK synchronous communication
• Multiprocessor mode
• Fully programmable baud rate
- Built-in timer that can be used to set any baud rate (see Section "8.3 U-TIMER Operations").
• Free baud rate setting by external clock
• Error detection function (parity, framing, and overrun)
• NRZ-code transfer signal
• DMA transfer activation by interrupt
286
CHAPTER 13 UART
13.2
UART Block Diagram
Figure 13.2-1 shows a UART block diagram.
■ UART Block Diagram
Figure 13.2-1 UART Block Diagram
Control signal
Reception interrupt
(to CPU)
SC (clock)
Clock
selection
circuit
From U-timer
Transmission interrupt
(to CPU)
Transmission clock
Reception clock
External clock
SC
Reception control circuit
SI
(Reception data)
Transmission control circuit
Start bit detection
circuit
Transmission start
circuit
Receive bit counter
Transmit bit counter
Receive parity
counter
Transmit parity
counter
SO (transmission data)
Receiving status
evaluation circuit
Reception shifter
Transmission shifter
Reception
end
Transmission
start
SIDR
SODR
DMA reception
error signal (to DMAC)
R - bus
MD1
MD0
SMR
register
CS0
SCKE
SOE
SCR
register
PEN
P
SBL
CL
A/D
REC
RXE
TXE
SSR
register
PE
ORE
FRE
RDRF
TDRE
RIE
TIE
Control signal
287
CHAPTER 13 UART
13.3
UART Registers
Figure 13.3-1 shows the UART registers.
■ UART Registers
Figure 13.3-1 shows the UART registers.
Figure 13.3-1 UART Registers
15
000021H
000025H
00001CH
000020H
000024H
00001FH
000023H
000027H
00001EH
000022H
000026H
288
8 7
0
SCR
SMR
(R/W)
SSR
SIDR(R)/SODR(W)
(R/W)
8bit
8bit
7
6
5
4
3
2
1
0
D7
D6
D5
D4
D3
D2
D1
D0
15
14
13
12
11
10
9
8
PE
ORE
-
RIE
TIE
7
6
5
4
3
2
1
0
MD1
MD0
-
-
CS0
-
15
14
13
12
11
10
9
PEN
P
SBL
CL
A/D
REC
RXE
FRE RDRF TDRE
Serial input/output register (SIDR/SODR)
Serial status register (SSR)
SCKE SOE Serial mode register (SMR)
8
TXE Serial control register (SCR)
CHAPTER 13 UART
13.3.1
Serial Mode Register (SMR0 to SMR2)
The serial mode register (SMR0 to SMR2) specifies a UART operation mode. Set the
operation mode when UART is inactive. Do not write this register when UART is in
operation.
■ Serial Mode Register (SMR0 to SMR2)
The serial mode register (SMR0 to SMR2) has the following configuration:
SMR
bit
7
Address: 00001FH MD1
000023H R/W
000027H
6
5
4
3
2
MD0
-
-
CS0
-
R/W
R/W
1
0
SCKE SOE
R/W
Initial value
00--0-00B
R/W
Bits 7 and 6: MD1, MD0 (Mode Select)
These bits are used to select a UART operation mode.
Table 13.3-1 Selection of UART Operation Mode
Mode
MD1
MD0
Description
0
0
0
Asynchronous (step-synchronous): Normal mode [initial value]
1
0
1
Asynchronous (step-synchronous): Multiprocessor mode
2
1
0
CLK asynchronous mode
-
1
1
Do not set
Note:
In CLK asynchronous mode (mode 1 -Multiprocessor), several slave CPUs are connected to a single
host CPU. This resource supports only the master in multiprocessor mode only because the format
of received data cannot be discriminated.
Since the parity check function is not available, set the PEN flag in the SCR register to 0.
Bits 5 and 4: (reserved)
Always write 1.
Bit 3: CS0 (Clock Select)
This bit is used to select the UART operation clock.
0: Internal timer (U-TIMER) [initial value]
1: External clock
Bit 2: (reserved)
Always write 0.
289
CHAPTER 13 UART
Bit 1: SCKE (SCLK Enable)
This bit specifies whether the SC pin is used as a clock input or output pin for communication in CLK
synchronous mode (mode 2).
Set this bit to 0 in CLK asynchronous mode or external clock mode.
Set this bit to 0 for external clock mode.
0: Clock input pin [initial value]
1: Clock output pin
Note:
To use the pin for clock input, an external clock source should be selected with CS0 bit "1".
Bit 0: SOE (Serial Output Enable)
This bit specifies whether the external pin (SO) doubled as a general-purpose I/O port should be used as a
serial output pin or I/O port.
0: General-purpose I/O port [initial value]
1: Serial data output pin (SO)
290
CHAPTER 13 UART
13.3.2
Serial Control Register (SCR0 to SCR2)
The serial control register (SCR0 to SCR2) controls the transfer protocol for serial
communication.
■ Serial Control Register (SCR0 to SCR2)
The serial control register (SCR0 to SCR2) has the following configuration:
SMR
bit
7
Address: 00001EH PEN
000022H R/W
000026H
6
5
4
3
2
1
0
Initial value
P
SBL
CL
A/D
REC
RXE
TXE
00000100B
R/W
R/W
R/W
R/W
W
R/W
R/W
Bit 7: PEN (Parity Enable)
This bit specifies whether to add parity to serial communication for data communication.
0: No parity [initial value]
1: Parity
Note:
Parity can be added in normal asynchronous (step-synchronous) communication mode (mode 0)
only. No parity can be added in multiprocessor asynchronous communication mode (mode 1) or CLK
synchronous communication mode (mode 2).
Bit 6: P (Parity)
This bit specifies even or odd parity for data communication.
0: Even parity
1: Odd parity
Bit 5: SBL (Stop Bit Length)
This bit is specifies the length of stop bits that serve as a frame end mark for asynchronous (stepasynchronous) communication.
0: One stop bit [initial value]
1: Two stop bits
Bit 4: CL (Character Length)
This bit specifies the data length of a transmit or receive frame.
0: 7-bit data [initial value]
1: 8-bit data
Note:
Seven-bit data can be handled in normal asynchronous (step-synchronous) communication mode
(mode 0) only. Set the data length to 8 bits for communication in multiprocessor asynchronous
communication mode (mode 1) or CLK synchronous communication mode (mode 2).
291
CHAPTER 13 UART
Bit 3: A/D (Address/Data)
This bit specifies the data format of a transmit or receive frame in multiprocessor asynchronous
communication mode (mode 1).
0: Data frame [initial value]
1: Address frame
292
CHAPTER 13 UART
Bit 2: REC (Receive Error Clear)
Writing 0 clears SSR error flags (PE, ORE, and FRE).
Writing 1 has no effect. The read value is always 1.
Bit 1: RXE (Receive Enable)
This bit controls UART reception.
0: Disable reception [initial value]
1: Enable reception
Note:
If reception is disabled during reception (data input to the reception shift register), the receiving
operation stops after the frame is received and the received data is stored in the receive data buffer
(SIDR).
Bit 0: TXE (Transmitter Enable)
This bit controls UART transmission.
0: Disable transmission [initial value]
1: Enable transmission
Note:
If transmission is disabled during transmission (data output from the transmission register), the
transmitting operation stops if the SODR register in the transmission data buffer becomes empty.
To write 0, wait for the specified period after data is written to SODR0 to SODR3. The specified
period refers to a time that is 1/16 of the baud rate in clock asynchronous transfer mode, and a time
that is the baud rate in clock synchronous transfer mode.
293
CHAPTER 13 UART
13.3.3
Serial Input Data Register (SIDR0 to SIDR2)/
Serial Output Data Register (SODR0 to SODR2)
The serial input data register (SIDR0 to SIDR2) and serial output data register (SODR0 to
SODR2) are data buffer registers for reception and transmission.
When the data length is 7 bits, the upper one bit (D7) is invalid. Write SODR only when
the TDRE bit is 1 in SSR.
■ Serial Input Data Register (SIDR0 to SIDR2) and
Serial Output Data Register (SODR0 to SODR2)
The serial input data register (SIDR0 to SIDR2) and serial output data register (SODR) have the following
configurations:
SIDR
bit
Address: 00001DH
000021H
000025H
7
6
5
4
3
2
1
0
Initial value
D7
D6
D5
D4
D3
D2
D1
D0
XXXXXXXXB [R/W]
R
R
R
R
R
R
R
R
7
6
5
4
3
2
1
0
D7
D6
D5
D4
D3
D2
D1
D0
W
W
W
W
W
W
W
W
SODR
bit
Address: 00001DH
000021H
000025H
XXXXXXXXB [R/W]
Note:
Write access to this address means data write into the SODR register, and read access means data
read from the SIDR register.
294
CHAPTER 13 UART
13.3.4
Serial Status Register (SSR)
The serial status register (SSR) consists of flags indicating the UART operation status.
■ Serial Status Register (SSR)
The serial status register (SSR) has the following configuration:
SSR
bit
Address: 00001CH
000020H
000024H
7
6
PE
ORE
R
R
5
4
3
FRE RDRF TDRE
R
R
R
2
1
0
Initial value
-
RIE
TIE
00001-00B
R/W
R/W
Bit 7: PE (Parity Error)
This interrupt request flag is set if a parity error occurs during reception.
To clear a flag once set, write 0 to the REC bit (bit 10) in the SCR register.
Setting this bit makes the SIDR data invalid.
0: No parity [initial value]
1: Parity
Bit 6: ORE (Overrun Error)
This interrupt request flag is set if an overrun error occurs during reception.
To clear a flag once set, write 0 to the REC bit (bit 10) in the SCR register.
Setting this bit makes the SIDR data invalid.
0: No overrun error [initial value]
1: Overrun error
Bit 5: FRE (Framing Error)
This interrupt request flag is set if a framing error occurs during reception.
To clear a flag once set, write 0 to the REC bit (bit 10) in the SCR register.
Setting this bit makes the SIDR data invalid.
0: No framing error [initial value]
1: Framing error
Bit 4: RDRF (Receiver Data Register Full)
This interrupt request flag indicates that receive data is in the SIDR register.
This flag is set when receive data is loaded into the SIDR register and automatically cleared when the
SIDR register is read.
0: No receive data [initial value]
1: Receive data
295
CHAPTER 13 UART
Bit 3: TDRE (Transmitter Data Register Empty)
This interrupt request flag indicates that transmit data can be written into the SODR register.
This flag is cleared when transmit data is written into the SODR register. When the written data is loaded
to the transmission shifter and data transfer starts, this flag is set again to indicate that next data can be
written.
0: Disable transmit data write
1: Enable transmit data write [initial value]
Bit 2: (reserved)
Bit 1: RIE (Receiver Interrupt Enable)
This bit controls a reception interrupt.
0: Disable interrupt [initial value]
1: Enable interrupt
Note:
The reception interrupt resources are errors indicated on PE, ORE, and FRE or normal status
indicated on RDRF.
Bit 0: TIE (Transmitter Interrupt Enable)
This bit controls a transmission interrupt.
0: Disable interrupt [initial value]
1: Enable interrupt
Note:
The transmission interrupt resource is normal status indicated on the TDRE flag.
296
CHAPTER 13 UART
13.4
UART Operation Modes and Clock Selection
UART operates in the following three modes, depending on the settings of the SMR and
SCR registers.
• Asynchronous (step-synchronous): Normal mode
• Asynchronous (step-synchronous): Multiprocessor mode
• CLK asynchronous mode
■ UART Operation Modes
Table 13.4-1 lists the UART operation modes.
The stop bit length in asynchronous (step-synchronous) mode can be specified for transmission only. The
length is fixed at one bit for reception. Do not set the length in other modes because the setting becomes
invalid.
Table 13.4-1 UART Operation Modes
Mode
Parity
Data length
Yes/No
7
Yes/No
8
1
None
8+1
2
None
8
0
Operation mode
Stop bit length
Asynchronous (step-synchronous) mode: Normal
One or two bits
Asynchronous (step-synchronous) mode: Multiprocessor
CLK synchronous mode
None
■ UART Clock Selection
● Internal timer
If CS0 is set to 0 to select the U-TIMER, the reload value set in the U-TIMER determines the baud rate.
The baud rate calculation formulas are as follows:
• Asynchronous (step-synchronous): φ / (16 × b)
• CLK synchronous: (φ / b)
φ : Peripheral machine clock frequency
β : Cycle set in the U-TIMER (2n + 2 or 2n + 3; n is the reload value.)
In asynchronous (start-stop) mode, transfer is possible at -1% to +1% of the set baud rate.
● External clock
If CS0 is set to 1 to select an external clock, the baud rate can be calculated from the external clock
frequency (f) as follows:
• Asynchronous (step-synchronous): f/16
• CLK synchronous: f
Example: The maximum value of f is 3.125 MHz.
297
CHAPTER 13 UART
13.4.1
Asynchronous (Step-synchronous) Modes
UART handles data of the Non Return to Zero (NRZ) format only.
Data transfer always starts from the start bit (L-level data). After the specified number of
bits are transferred starting from the LSB, the data transfer ends at the stop bit (H-level
data). If an external clock is selected, always enter clock pulses.
■ Transfer Data Formats in Asynchronous (Step-synchronous) Modes
Figure 13.4-1 shows the transfer data formats in asynchronous (step-synchronous) modes.
The data length can be set to 7 or 8 bits in normal mode (mode 0) but must always be 8 bits in
multiprocessor mode (mode 1). No parity can be added in multiprocessor mode. Instead, the A/D bit is
always added.
Figure 13.4-1 Transfer Data Formats in Asynchronous (Step-synchronous) Modes (Modes 0 and 1)
SI,SO
0
Start
1
0
LSB
1
1
0
0
1
0
1
1
MSB Stop
A/D Stop
(Mode 0)
(Mode 1)
Transfer data: 01001101B
● Reception
Reception is always in progress when the RXE bit (bit 1) is 1.
If a start bit appears in the reception line, a frame of data is received in the SCR-specified data format.
Once a frame of data has been received and an error occurs, the RDRF flag (SSR bit 4) is set after an error
flag setting. If the RIE bit (bit 1) is set to 1, a reception interrupt is issued to the CPU. Each flag in SSR
should be checked. Read the SIDR register if the reception status is normal or execute necessary processing
if abnormal.
The RDRF flag is cleared when the SIDR register is read.
● Detecting the start bit
Implement the following settings to detect the start bit:
• Set the communication line level to H (attach the mark level) before the communication period.
• Specify reception permission (RXE = H) while the communication line level is H (mark level).
• Do not specify reception permission (RXE = H) for periods other than the communication period
(without mark level). Otherwise, data is not received correctly.
• After the stop bit is detected (the RDRF flag is set to 1), specify reception inhibition (RXE = L) while
the communication line level is H (mark level).
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CHAPTER 13 UART
Figure 13.4-2 Normal Operation
Communication period
Non-communication period
Mark level
Start bit
SIN
ST
Non-communication period
Stop bit
Data
D0
D1
D0
D1
D2
D3
D4
D5
D6
D7
SP
(Sending 01010101B)
RXE
Receive clock
Sampling clock
Receive clock (8 pulse)
Recognition by the microcontroller
ST
Generating sampling clocks by dividing the receive clock by 16
D2
D3
D4
D5
D6
D7
SP
(Receiving 01010101B)
Note that specifying reception permission at the timing shown below obstructs the correct recognition of
the input data (SIN) by the microcontroller.
• Example of operation if reception permission (RXE = H) is specified while the communication line
level is "L".
Figure 13.4-3 Abnormal Operation
Communication period
Non-communication period
Mark level
Start bit
SIN
(Sending 01010101B)
RXE
ST
D0
Non-communication period
Stop bit
Data
D0
D1
D1
D2
D2
D3
D3
D4
D4
D5
D6
D7
D5
D6
D7
SP
SP
Receive clock
Sampling clock
Recognition by the microcontroller
ST recognition
(Receiving 10101010B)
PE,ORE,FRE
Occurrence of a reception error
● Transmission
When the TDRE flag (SSR bit 11) is 1, transmit data is written into the SODR register. When TXE (SCR
bit 0) is 1, data is transmitted.
Data set in the SODR register is loaded to the transmission shift register and transmission starts. Then the
TDRE flag is set again to allow the setting of next transmit data. If TIE (SSR bit 0) is 1, however, a
transmission interrupt request is issued to the CPU for transmit data to be set in the SODR register.
The TDRE flag is cleared once when data is set in the SODR register.
299
CHAPTER 13 UART
13.4.2
CLK Synchronous Mode
UART handles data of the NRZ (Non Return to Zero) format only. Figure 13.4-4 shows
the transfer data format in CLK synchronous mode.
■ Transfer Data Format in CLK Synchronous Mode
Figure 13.4-4 Transfer Data Format in CLK Synchronous Mode (Mode 2)
SODR write
Mark
SCK
RXE,TXE
SI,SO
1
0
LSB
1
1
0
0
1
0
MSB
(Mode 2)
Transfer data: 01001101bB
If CS0 is set to 0 to select the output from the U-TIMER, data transmission automatically generates
synchronous clock pulses for data reception.
If an external clock is selected, check that the SODR data buffer of the transmission-side UART contains
data (TDRE flag is set to 0), then supply one byte of clock pulses accurately. Be sure to set the mark level
before and after the start of transmission.
Data is only 8 bits with no parity. Since the start and stop bits are not supported, all errors except overrun
errors can be detected.
● Initialization
In CLK synchronous mode, the set values of each control register are as follows:
• SMR
- MD1 and MD0: 10
- CS0: Clock input
- SCKE: 1 for internal timer, 0 for external clock
- SOE: 1 for transmission, 0 for reception
• SCR
- PEN: 0
- P, SBL, and A/D: No meaning
- CL: 1
- REC: 0 (for initialization)
- RXE and TXE: 1 (at least either one)
• SSR
300
CHAPTER 13 UART
- RIE: 1 for interrupt, 0 for no interrupt
- TIE: 0
● Start of communication
Communication starts when the SODR register is written. Even for reception only, temporary transmit data
should be written into the SODR register.
● End of communication
When communication ends in CLK synchronous mode, the RDRF flag in the SSR register changes to 1.
Check the ORE flag in the SSR register to see that the communication has finished normally.
301
CHAPTER 13 UART
13.5
UART Interrupts and Flag Setting Timings
UART has five flags and two interrupt resources.
The five flags are PE, ORE, FRE, RDRF, and TDRE.
The two interrupt resources are for reception and transmission.
■ UART Flags and Interrupts
PE stands for parity error, ORE for overrun error, and FRE for framing error. These errors are cleared when
0 is written to the REC bit in the SCR register.
The RDRF flag is set when receive data is loaded into the SIDR register and cleared when the SIDR
register is read. The parity detection function is not supported in mode 1 and the parity and framing error
detection functions are not supported in mode 2.
The TDRE flag is set when the SODR register becomes empty and ready for write and cleared when data is
written into the SODR register.
At reception, PE, ORE, FRE, or RDRF is used for an interrupt request.
At transmission, TDRE is used for an interrupt request.
■ UART Interrupts and Flag Setting Timings: Reception in Mode 0
When the last stop bit is detected at the end of reception, the PE, ORE, FRE, and RDRF flags are set to
issue an interrupt request to the CPU. The SIDR data is invalid when the PE, ORE, and FRE flags are
active.
Figure 13.5-1 PE, ORE, FRE, and RDRF Flag Setting Timings in Mode 0
Data
PE,ORE,FRE
RDRF
Reception interrupt
302
D6
D7
Stop
CHAPTER 13 UART
■ UART Interrupts and Flag Setting Timings: Reception in Mode 1
When the last stop bit is detected at the end of reception, the ORE, FRE, and RDRF flags are set to issue an
interrupt request to the CPU. Since the receivable data length is 8 bits, the last bit (bit 9) indicating an
address or data becomes invalid. The SIDR data is invalid when the ORE and FRE flags are active.
Figure 13.5-2 ORE, FRE, and RDRF Flag Setting Timings in Mode 1
Data
D7
Address/data
Stop
ORE,FRE
RDRF
Reception interrupt
■ UART Interrupts and Flag Setting Timings: Reception in Mode 2
When the last data (D7) is detected at the end of reception, the ORE and RDRF flags are set to issue an
interrupt request to the CPU. The SIDR data is invalid when the ORE flag is active.
Figure 13.5-3 ORE and RDRF Flag Setting Timings in Mode 2
Data
D5
D6
D7
ORE
RDRF
Reception interrupt
303
CHAPTER 13 UART
■ UART Interrupts and Flag Setting Timings: Transmission in Modes 0 to 2
The TDRE flag is cleared when transmit data is written into the SODR register and set when the SODR
register value is transferred to the internal shift register because the SODR register becomes ready for
write. When this flag is set, an interrupt request is issued to the CPU.
If 0 is written to the TXE bit in the SCR register (including RXE in mode 2) during transmission, the
TDRE flag in the SSR register becomes 1. After the transmission shifter stops, the UART transmission is
inhibited. During transmission, 0 is written to the TXE bit in the SCR register (including RXE in mode 2).
Data written into the SODR register before the end of transmission is transmitted anyway.
Figure 13.5-4 TDRE Setting Timings in Modes 0 and 1
SODR write
TDRE
Interrupt request to CPU
S0 interrupt
S0 output
ST
D0
D1
D2
D3
D4
D5
D6
D7
SP SP
A/D
ST
D0
D1
D2
D3
D3
D4
D5
D6
D7
ST: Start bit D0 to D7: Data bits SP: Stop bit A/D: Address/data multiplexer
Figure 13.5-5 TDRE Setting Timing in Mode 2
SODR write
TDRE
Interrupt request to CPU
S0 interrupt
S0 output
D0
D1
D2
D3
D4
D5
D6
D0 to D7: Data bits
304
D7
D0
D1
D2
CHAPTER 13 UART
13.6
Notes on Use with Example of UART Application
This section gives notes on using UART with an application example.
■ Notes on UART Use
Set the communication mode when UART is not in operation. Data transmitted and received during mode
setting cannot be guaranteed.
■ Example of UART Application
Mode 1is used when several slave CPUs are connected to a single host CPU (see Figure 13.6-1).
This resource supports the host-side communication interface only.
Figure 13.6-1 Example of System Construction in Mode 1
SO
SI
Host CPU
SO SI
SO SI
Slave CPU#0
Slave CPU#1
Address data transfer by the host CPU triggers communication. Address data is when the A/D bit in the
SCR register is 1. This data selects a slave CPU as the communication party to establish communication
with the host CPU.
Ordinary data is when the A/D bit in the SCR register is 0.
Figure 13.6-2 shows the flowchart.
Since the parity check function cannot be used in this mode, set the PEN bit in the SCR register to 0.
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CHAPTER 13 UART
Figure 13.6-2 Communication Flowchart in Mode 1
(Host CPU)
START
Set transfer mode to "1"
Set slave CPU selection data
at D0 to D7, A/D bit to "1",
and transfer one byte
Set A/D bit to "0"
Enable reception
Communicate with slave CPU
End of
No
communication?
Yes
Communicate
with another slave
CPU
No
Yes
Disable reception
END
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CHAPTER 13 UART
13.7
Examples of Setting Baud Rates and U-TIMER Reload
Values
Table 13.7-1 and Table 13.7-2 list examples of setting baud rates and U-TIMER reload
values.
The frequency in the tables indicates the peripheral machine clock frequency. UCC1 is
the value to be set in the UCC1 bit in the U-TIMER control (UTIMC) register.
A hyphen (-) in the tables indicates that the frequency cannot be used because the error
exceeds plus or minus 1%.
■ Examples of Setting Baud Rates and U-TIMER Reload Values
● Asynchronous (start-stop) mode
Table 13.7-1 Baud Rates and U-TIMER Reload Values in Asynchronous (Start-Stop) Mode
Baud rate
µs
25MHz
20MHz
12.5MHz
10MHz
1200
833.33
650(UCC1=0)
520(UCC1=0)
324(UCC1=1)
259(UCC1=1)
2400
416.67
324(UCC1=1)
259(UCC1=1)
162(UCC1=0)
129(UCC1=0)
4800
208.33
162(UCC1=0)
129(UCC1=0)
80(UCC1=1)
64(UCC1=0)
9600
104.17
80(UCC1=1)
64(UCC1=0)
39(UCC1=1)
31(UCC1=1)
19200
52.08
39(UCC1=1)
31(UCC1=1)
19(UCC1=1)
-
38400
26.04
19(UCC1=1)
-
12(UCC1=1)
-
57600
17.36
12(UCC1=1)
-
-
-
10400
96.15
74(UCC1=0)
59(UCC1=0)
36(UCC1=1)
29(UCC1=0)
31250
32.00
24(UCC1=0)
19(UCC1=0)
11(UCC1=1)
9(UCC1=0)
62500
16.00
11(UCC1=1)
9(UCC1=0)
-
4(UCC1=0)
● CLK synchronous mode
Table 13.7-2 Baud Rates and U-TIMER Reload Values in CLK Synchronous Mode
Baud rate
µs
25MHz
20MHz
12.5MHz
10MHz
250K
4.00
49(UCC1=0)
39(UCC1=0)
24(UCC1=0)
19(UCC1=0)
500K
2.00
24(UCC1=0)
19(UCC1=0)
11(UCC1=1)
9(UCC1=0)
1M
1.00
11(UCC1=1)
9(UCC1=0)
5(UCC1=0)*
4(UCC1=0)
*: There is an error of plus or minus 1% or more.
307
CHAPTER 13 UART
308
CHAPTER 14
DMA CONTROLLER (DMAC)
This chapter gives an outline of the DMA controller
(DMAC) and explains the register configuration and
functions and the controller operations.
14.1 Outline of the DMA Controller
14.2 Block Diagram of the DMA Controller
14.3 Registers of the DMA Controller
14.4 Transfer Modes of DMA Controller
14.5 Transfer Acknowledge Signal Output and Transfer End Signal
Output
14.6 Notes on DMA Controller
14.7 DMA Controller Timing Chart
14.8 DMA Controller Software Trigger Circuit (STRG)
309
CHAPTER 14 DMA CONTROLLER (DMAC)
14.1
Outline of the DMA Controller
The DMA controller is a module built into the MB91121 for executing direct memory
access (DMA) transfer.
■ Features of DMA Controller
• 8 channels
• Mode: Single/block transfer, burst transfer, and continuous transfer
• Transfer among the entire area of addresses
• Maximum transfer count of 65,536
• Transfer end interrupt function
• Incrementing and decrementing of transfer address selectable by software
• External transfer request input pin, external transfer request acknowledge output pin, and external
transfer end output pin
310
CHAPTER 14 DMA CONTROLLER (DMAC)
14.2
Block Diagram of the DMA Controller
Figure 14.2-1 shows a block diagram of the DMA controller.
■ Block Diagram of the DMA Controller
Figure 14.2-1 Block Diagram of the DMA Controller
DREQ0 to DREQ2
3
Edge/level
detection circuit
3
3
3
Sequencer
Internal resource
transfer request
5
Data buffer
8
DACK0 to DACK2
EOP0 to EOP2
Interrupt
request
Switcher
DPDP
DACSR
DATCR
Data bus
Mode
BLK DEC
BLK
DMACT
INC/DEC
SADR
DADR
311
CHAPTER 14 DMA CONTROLLER (DMAC)
14.3
Registers of the DMA Controller
Figure 14.3-1 shows the registers of the DMA controller.
■ Registers of the DMA Controller
Figure 14.3-1 Registers of the DMA Controller
[In DMAC: DMAC internal register]
31
0
000200H
DPDP [R/W]
000204H
DACSR [R/W]
000208H
DATCR [R/W]
[In RAM: DMA descriptor]
31
0
DPDP + 0H
DMA
ch0
Descriptor
DPDP + 0CH
DMA
ch1
Descriptor
:
:
DPDP + 54H
DMA
ch7
Descriptor
312
CHAPTER 14 DMA CONTROLLER (DMAC)
14.3.1
DMAC Parameter Descriptor Point (DPDP)
The DMAC parameter descriptor pointer (DPDP) is a DMAC internal register that stores
the first address of the DMAC descriptor table in RAM.
DPDB bits 6 to 0 are always 0, and the first address of the descriptor can be set in 128
bytes.
■ DMAC Parameter Descriptor Pointer (DPDP)
The DMAC parameter descriptor pointer (DPDP) has the following register configuration:
000200H
31
7 6
0
XXXXXXXX XXXXXXXX XXXXXXXX X
0000000
[R/W] Initial value
Reset does not initialize this register.
This register can be read and written to.
To access this register, use the 32-bit transfer instruction.
Table 14.3-1 lists the addresses specified in DPDP at which the descriptors that specify the channel
operation modes are placed.
Table 14.3-1 Channel Descriptor Addresses
DMA channel
Descriptor address
DMA channel
Descriptor address
0
DPDP + 0 (00H)
4
DPDP + 48 (30H)
1
DPDP + 12 (0CH)
5
DPDP + 60 (3CH)
2
DPDP + 24 (18H)
6
DPDP + 72 (48H)
3
DPDP + 36 (24H)
7
DPDP + 84 (54H)
313
CHAPTER 14 DMA CONTROLLER (DMAC)
14.3.2
DMAC Control/Status Register (DACSR)
The DMAC control/status register (DACSR) is a DMAC internal register that controls the
DMAC and indicates its status.
■ DMAC Control/Status Register (DACSR)
The DMAC control/status register (DACSR) has the following configuration:
000204H
Initial value
31
30
29
DER7
DED7
DIE7
R/W
R/W
R/W
R/W
23
22
21
20
DER5
DED5
DIE5
R/W
R/W
R/W
R/W
15
14
13
12
DER3
DED3
DIE3
R/W
R/W
R/W
R/W
7
6
5
4
DER1
DED1
DIE1
R/W
R/W
R/W
00000000H
28
27
26
25
24
DED6
DIE6
DOE6
R/W
R/W
R/W
R/W
19
18
17
16
DED4
DIE4
DOE4
R/W
R/W
R/W
R/W
11
10
9
8
DED2
DIE2
DOE2
R/W
R/W
R/W
R/W
3
2
1
0
DED0
DIE0
DOE0
R/W
R/W
R/W
DOE7 DER6
DOE5 DER4
DOE3 DER2
DOE1 DER0
R/W
00000000H
R/W
00000000H
00000000H
Bits 31, 27, 23, 19, 15, 11, 7, and 3: DER7 to DER0 (DMA ERror)
These bits indicate whether an error in the DMA request source on channel n has occurred, halting DMA
transfer processing.
0: No error occurred.
1: An error occurred.
Whether an error has occurred depends on the DMA request source (resource). For details, see "■DMA
Transfer Request Resources" in "14.6 Notes on DMA Controller".
Reset initializes these bits to 0.
These bits can be read and written to. The only valid value that can be written to these bits is 0.
The value read by a read-modify-write instruction is 1.
314
CHAPTER 14 DMA CONTROLLER (DMAC)
Bits 30, 26, 22, 18, 14, 10, 6, and 2: DED7 to DED0 (DMA EnD)
These bits indicate whether DMA transfer on channel n has ended.
0: DMA transfer operation has not ended.
1: The counter has become 0, or an error occurred in the transfer request source.
Reset initializes these bits to 0.
These bits can be read and written to. The only valid value that can be written to these bits is 0.
The value read by a read-modify-write instruction is 1.
Bits 29, 25, 21, 17, 13, 9, 5, and 1: DIE7 to DIE0 (DMA Interrupt Enable)
These bits specify whether an interrupt request is generated when DMA transfer on channel n ends
(DED7 to DED0 is set to "1").
0: Disable interrupt.
1: Enable interrupt.
Reset initializes these bits to 0.
These bits can be read and written to.
Bits 28, 24, 20, 16, 12, 8, 4, and 0: DOE7 to DOE0 (DMA Operation Enable)
These bits enable DMA transfer operation on channel n.
0: Disable operation.
1: Enable operation.
When DMA transfer on the relevant channel is completed (DED7 to DED0 is set to "1"), DOE7 to DOE0
is cleared to 0.
If a clear operation when transfer ends and a set operation for write from the bus are executed
concurrently, the set operation has priority.
Reset initializes these bits to 0.
These bits can be read and written to.
315
CHAPTER 14 DMA CONTROLLER (DMAC)
14.3.3
DMAC Pin Control Register (DATCR)
The DMAC pin control register (DATCR) is a DMAC internal register that controls the
external transfer request input pin, external transfer request acknowledge output pin,
and external transfer end output pin.
■ DMAC Pin Control Register (DATCR)
The DMAC pin control register (DATCR) has the following configuration:
31
24
000208H
Initial value
-
23
22
21
20
19
18
17
16
-
-
LS21
LS20 AKSE2 AKDE2 EPSE2 EPDE2
R/W
R/W
R/W
R/W
R/W
R/W
12
11
10
9
8
15
14
13
-
-
LS11
LS10 AKSE1 AKDE1 EPSE1 EPDE1
R/W
R/W
R/W
R/W
R/W
R/W
4
3
2
1
0
7
6
5
-
-
LS01
LS00 AKSE0 AKDE0 EPSE0 EPDE0
R/W
R/W
XXXXXXXXH
XXXX0000H
R/W
R/W
XXXX0000H
R/W
R/W
XXXX0000H
Bits 21, 20, 13, 12, 5, and 4: LSn1 and LSn0 (transfer request input detection level selection)
These bits are used to select the detection level of the relevant external transfer request input pin DREQn,
as shown in Table 14.3-2.
Table 14.3-2 Transfer Request Input Detection Level Selection
LSn1
LSn0
Operation control function
0
0
Rising edge detection.
0
1
Falling edge detection.
1
0
"H" level detection.
1
1
"L" level detection.
During reset, these bits are undefined.
These bits can be read and written to.
To use the continuous transfer mode, set H- or L-level detection.
316
CHAPTER 14 DMA CONTROLLER (DMAC)
Bits 19, 11, and 13: AKSE2 to AKSE0
Bits 18, 10, and 2: AKDE2 to AKDE0
These bits specify the timing of issuing the transfer request acknowledge output signal.
These bits also enable or disable output from the transfer request acknowledge output signal pin.
Table 14.3-3 Transfer Request Acknowledge Output Specification
AKSE2 to AKSE0 AKDE2 to AKDE0
Operation control function
0
0
Disable transfer acknowledge output.
0
1
Enable transfer acknowledge output. Output during transfer destination data
access.
1
0
Enable transfer acknowledge output. Output during transfer source data
access.
1
1
Enable transfer acknowledge output. Output during transfer source and
transfer destination data access.
Reset initializes these bits to 00B.
These bits can be read and written to.
Bits 17, 9, and 1: EPSE2 to EPSE0
Bits 16, 8, and 0: EPDE2 to EPDE0
These bits specify the timing for issuing the transfer end output signal. These bits also enable and disable
output from the transfer end output signal pin.
Table 14.3-4 Transfer End Output Specification
EPSE2 to EPSE0 EPDE2 to EPDE0
Operation control function
0
0
Disable transfer end output.
0
1
Enable transfer end output. Output during transfer destination data access.
1
0
Enable transfer end output. Output during transfer source data access.
1
1
Enable transfer end output. Output during transfer source and destination data
access.
Reset initializes these bits to 00B.
These bits can be read and written to.
317
CHAPTER 14 DMA CONTROLLER (DMAC)
14.3.4
Descriptor Register in RAM
The descriptor register stores setting information for each DMA transfer channel.
The register size is 12 bytes per channel, and the memory at the address specified in
DPDP is used.
See Table 14.3-1 for information about the first address of descriptor for each channel.
■ First Descriptor Word
The first descriptor word register has the following configuration:
31
16
DMACT
R/W
15
14
13
12
11
10
-
9
8
1
0
BLK
R/W
7
6
5
4
3
2
SCS1
SCS0
DCS1
DCS0
WS1
WS0
R/W
R/W
R/W
R/W
R/W
R/W
MOD1 MOD0
R/W
R/W
Initial value: Undefined
Bits 31 to 16: DMACT (transfer count specification)
These bits specify the DMA transfer count. If 0000H is set, 65,536 transfer operations are executed.
Each time a transfer is executed, the value is decremented by one.
Bits 15 to 12: Empty
Bits 11 to 8: Block size specification
These bits specify the transfer block size in single/block transfer mode.
If "0" is specified, the block size is assumed to be 16. To execute single transfer, specify 1.
Bits 7 and 6: SCS1 and SCS0 (transfer source address update mode specification)
Bits 5 and 4: DCS1 and DCS0 (transfer destination address update mode specification)
These bits specify the update mode for each transfer for the transfer source and transfer destination
addresses.
Table 14.3-5 lists the combinations that can be specified.
318
CHAPTER 14 DMA CONTROLLER (DMAC)
Table 14.3-5 Transfer Source and Transfer Destination Address Update Mode Specifications
SCS1
SCS0
DCS1
DCS0
Transfer source address
0
0
0
0
Address incremented
Address incremented
0
0
0
1
Address incremented
Address decremented
0
0
1
0
Address incremented
Fixed address
0
1
0
0
Address decremented
Address incremented
0
1
0
1
Address decremented
Address decremented
0
1
1
0
Address decremented
Fixed address
1
0
0
0
Fixed address
Address incremented
1
0
0
1
Fixed address
Address decremented
1
0
1
0
Fixed address
Fixed address
Other
Transfer destination address
Setting not allowed
The unit for incrementing and decrementing addresses in address update mode is determined by the
transfer data size as follows:
Table 14.3-6 Unit for Incrementing and Decrementing Addresses
Transfer data size
Unit for incrementing and decrementing addresses
byte (8 bit)
plus or minus 1 byte
halfword (16 bit)
plus or minus 2 byte
word (32 bit)
plus or minus 4 byte
Bits 3 and 2: WS1 and WS0
These bits specify the transfer data size.
Table 14.3-7 Transfer Data Size Specifications
WS1
WS0
Transfer data size
0
0
byte
0
1
halfword
1
0
word
1
1
Setting not allowed
319
CHAPTER 14 DMA CONTROLLER (DMAC)
Bits 1 and 0: MOD1 and MOD0 (transfer mode specification)
These bits specify the transfer mode.
Table 14.3-8 Transfer Mode Specification
MOD1
MOD0
Operation mode
0
0
Single/block mode
0
1
Burst mode
1
0
Continuous transfer mode
1
1
Setting not allowed
Only channels 0 to 2 can use continuous transfer mode.
■ Second Descriptor Word
31
0
SADR
R/W
This register stores the transfer source address.
The value is updated according to the transfer operation based on the address update mode specification
(SCS1 and SCS0 bits).
When the transfer data size is half-word length, specify an address that is a multiple of 2. When the transfer
size is word length, specify an address that is a multiple of 4.
■ Third Descriptor Word
31
0
DADR
R/W
This register stores the transfer destination address.
The value is updated according to the transfer operation based on the address update mode specification
(SCS1 and SCS0 bits).
When the transfer data size is half-word length, specify an address that is a multiple of 2. When the transfer
size is word length, specify an address that is a multiple of 4.
320
CHAPTER 14 DMA CONTROLLER (DMAC)
14.4
Transfer Modes of DMA Controller
The DMA controller has the following three transfer modes. The operating procedure for
them is explained below.
• Single/block transfer mode
• Continuous transfer mode
• Burst transfer mode
■ Single/Block Transfer Mode
1. The initialization routine is used to set the descriptor.
2. The program is used to initialize the DMA transfer request source. If the internal peripheral circuit is the
transfer request source, interrupt requests are enabled. Also, the interrupt controller ICR is disabled.
3. The program is used to write 1 to the desired DACSR DOEn bit.
--- The settings related to DMA are complete -4. When DMAC detects a DMA transfer request input, it requests the CPU to obtain a bus grant.
5. When the CPU transfers the bus grant, DMAC accesses 3-word information in the descriptor via the
bus.
6. DMACT is decreased, and the transfer based on information in the descriptor is executed the number of
times specified in BLK or until DMACT becomes 0. During data transfer, the transfer request
acknowledge output signal is output (if external transfer request input is used). When the decreasing
DMACT becomes 0, the transfer end output signal is output during data transfer.
7. The transfer request input is cleared.
8. SADR or DADR is incremented or decremented and written back to the descriptor together with the
DMACT value.
9. The bus grant is returned to the CPU.
10.If the DMACT value is 0, DACSR DEDn is set to 1. If interrupts are enabled, an interrupt is also
generated for the CPU.
If the descriptor is in internal RAM, data is being transferred to and from the external bus, and the data
length is byte, the minimum number of cycles required for one transfer is as follows:
• When both transfer source and destination addresses are fixed: (6 + 5 × BLK) cycles
• When only transfer the source or destination address is fixed: (7 + 5 × BLK) cycles
• When both the transfer source and destination addresses are incremented or decremented:
(8 + 5 × BLK) cycles
321
CHAPTER 14 DMA CONTROLLER (DMAC)
■ Continuous Transfer Mode
1. The initialization routine is used to set the descriptor.
2. The program is used to initialize the DMA transfer request source. The external transfer request input
pin is set to "H" level or "L" level detection.
3. The program is used to write 1 to the desired DACSR DOEn bit.
--- The settings related to DMA are complete -4. When DMAC detects a DMA transfer request input, it requests the CPU to secure the bus grant.
5. When the CPU transfers the bus grant, DMAC accesses 3-word information in the descriptor via the
bus.
6. DMACT is subtracted and the transfer based on information in the descriptor is executed once. During
data transfer, the transfer request acknowledge output signal is output. When the decreasing DMACT
becomes 0, the transfer end output signal is output during data transfer.
7. If the DMACT value is not 0 and the DMA request from the peripheral still exists, operation is repeated
from step 6) again (via step 8) depending on the bus status).
8. If the DMACT value is 0 or the DMA request from the peripheral is cleared, SADR or DADR is
incremented or decremented and written back to the descriptor together with the DMACT value.
9. The bus grant is returned to the CPU.
10.If the DMACT value is 0, DACSR DEDn is set to 1. If an interrupt is enabled, an interrupt is also
generated to the CPU.
If the descriptor is contained in the internal RAM, data is transferred to and from the external bus, and data
length is byte, the minimum number of cycles required for one transfer is as follows:
• When both transfer source and destination addresses are fixed: (6 + 5 × n) cycles
• When only transfer source or destination address is fixed: (7 + 5 × n) cycles
• When both transfer source and destination addresses are incremented or decremented: (8 + 5 × n) cycles
■ Burst Transfer Mode
1. The initialization routine is used to set the descriptor.
2. The program is used to initialize the DMA transfer request source. If the internal peripheral circuit is the
transfer request source, interrupt requests are enabled. The interrupt controller ICR is also disabled.
3. The program is used to write 1 to the desired DACSR DOEn bit.
--- The settings related to DMA are complete -4. When DMAC detects a DMA transfer request input, it requests the CPU to obtain a bus grant.
5. When the CPU transfers the bus grant, DMAC accesses 3-word information in the descriptor via the
bus.
6. As DMACT is being decreased, the transfer based on information in the descriptor is executed the
number of times specified in DMACT. During data transfer, the transfer request acknowledge output
signal is output (if external transfer request input is used).
When the decreasing DMACT becomes 0, the transfer end output signal is output during data transfer.
7. SADR or DADR is incremented or decremented and written back to the descriptor together with the
DMACT value.
8. The bus grant is returned to the CPU.
9. DACSR DEDn is set to 1, and an interrupt is generated sent to the CPU if an interrupt is enabled.
If the descriptor is in internal RAM, data is being transferred to and from the external bus, and the data
length is byte, the minimum number of cycles required for one transfer is as follows:
• When both transfer source and destination addresses are fixed: (6 + 5 × n) cycles
• When only the transfer source or destination address is fixed: (7 + 5 × n) cycles
• When both the transfer source and destination addresses are incremented or decremented:
(8 + 5 × n) cycles
322
CHAPTER 14 DMA CONTROLLER (DMAC)
■ Combinations of Sensing and Transfer Mode
Figure 14.4-1 shows the combination of sensing and transfer mode.
Figure 14.4-1 Combinations of Sensing and Transfer Mode
Sensing
Transfer mode
Transfer unit
Edge
Step operation mode
Single transfer
Block transfer
Level
Burst transfer mode
Continuous transfer mode
■ DREQ Signal Sensing Mode
● Edge sensing
Edge sensing can be used for step transfer (single or block) and burst transfer.
A DMA request is detected on the (active) edge.
During DMAC transfer, an external DREQ input is masked. The active edge for the next transfer must
follow the active edge of DACK that is the destination of DMA immediately before transferred. This
requirement must be kept in mind for step transfer.
● Level sensing
Level sensing can be used for step transfer (single or block) and continuous and burst transfers.
A DMA request is detected at the (active) level.
Note:
The electrical characteristics of the DACK signal are a minimum of 2t cycles [ns] for both level and
edge sensing. The DACK negation period must also be a minimum of 2t cycles [ns] for edge
sensing.
323
CHAPTER 14 DMA CONTROLLER (DMAC)
14.4.1
Step Transfer (Single or Block Transfer)
DMA transfer is executed once for each transfer request (the DREQ input can be
selected using either edge sensing or level sensing).
The bus right is transferred to the CPU during each DMA transfer (transfer is executed
on a cycle stealing basis).
The unit of transfer is determined by the block size. Increasing the block size improves
the DMAC transfer rate, but lowers the CPU throughput.
■ Step Transfer (Clock Doubler, Internal Descriptor, Block Size = 1)
Figure 14.4-2 Step Transfer (Clock Doubler, Internal Descriptor, Block Size = 1)
CLK
DREQ
DACK
Descriptor
access
Internal
D-bus
A-bus
External
A-bus
324
Transfer
source
Transfer
destination
Transfer
source
Transfer
destination
Period during which CPU
can use the data bus
CHAPTER 14 DMA CONTROLLER (DMAC)
14.4.2
Continuous Transfer
As long as the transfer request [DREQ] is kept at the active level, DMA transfer is
executed (DREQ input can only be selected using level sensing).
When the transfer count register becomes 0 or DREQ input is negated, the bus grant is
transferred to the CPU.
■ Continuous Transfer (Clock Doubler, Internal Descriptor)
Figure 14.4-3 Continuous Transfer (Clock Doubler, Internal Descriptor)
CLK
Descriptor
address
DREQ
DACK
Internal
D-bus
A-bus
External
A-bus
Period during which the
CPU can use the data bus
Transfer
source
Transfer Transfer
destination source
Transfer
destination
325
CHAPTER 14 DMA CONTROLLER (DMAC)
14.4.3
Burst Transfer
All DMA transfers that are set on a transfer request (DREQ) are executed (DREQ input
can be selected using either level sensing or edge sensing).
When the transfer count register becomes 0, DMA transfer is terminated and the bus
grant is transferred to the CPU.
■ Burst Transfer (Clock Doubler, Internal Descriptor)
Figure 14.4-4 Burst Transfer (Clock Doubler, Internal Descriptor)
CLK
DREQ
Descriptor access
DACK
Internal
D-bus
A-bus
External
A-bus
Period during which the CPU
can use the data bus
Transfer
source
Transfer
destination
Transfer
source
Transfer
destination
EOP
DMACT=1
326
DMACT=0
CHAPTER 14 DMA CONTROLLER (DMAC)
14.4.4
Differences in DREQ Sensing Modes (Note on Edge
Sensing)
In edge sensing, the next DREQ edge must be input at or after the clear point of the
DMAC request flag. An edge that is entered before the clear point is ignored.
The negation period must be a minimum of 2t cycles [ns] to recognize the edge.
Input the next DREQ after the DACK falling edge during transfer destination access.
■ Differences in DREQ Sensing Modes (Note on Edge Mode)
Figure 14.4-5 Differences in DREQ Sensing Modes (Note on Edge Mode)
CLK
DREQ
DACK
DREQ(NG)
Active edge is earlier.
DREQ(NG)
The minimum period of 2t
cycles [ns] is not satisfied.
DREQ(NG)
Destination write
Internal
D-bus
A-bus
External
A-bus
Descriptor write
Transfer
source
Transfer
destination
A
B
A: Clear point of request flag
Start point of the next DREQ in edge sensing mode
Start point of the next DREQ in continuous transfer mode
B: Start point of the next DREQ during single or
block transfer in level sensing mode
The fastest timing from DREQ to DMA activation is described.
327
CHAPTER 14 DMA CONTROLLER (DMAC)
14.4.5
Differences in DREQ Sensing Modes (Note on Level
Sensing)
In level sensing, be careful to avoid DMAC transfer overrun.
Negate DREQ with the rising edge of DACK during transfer destination access.
■ Differences in DREQ Sensing Modes (Note on Level Mode)
Figure 14.4-6 Differences in DREQ Sensing Modes (Note on Level Mode)
Up to 1 tcyc
CLK
DREQ
DREQ
DACK
Transfer is executed twice
for a transfer request.
DREQ(NG)
Destination write
Source read
Internal
D-bus
A-bus
Descriptor write
Descriptor read
External
A-bus
Transfer
source
Transfer
destination
A
B
A: Clear point of request flag
Start point of the next DREQ in edge sensing mode
Start point of the next DREQ in continuous transfer mode
B: Start point of the next DREQ during single or
block transfer in level sensing mode.
The fastest timing from DREQ to DMA activation is described.
328
CHAPTER 14 DMA CONTROLLER (DMAC)
14.5
Transfer Acknowledge Signal Output and Transfer End
Signal Output
Channels 0, 1, and 2 have functions for outputting the transfer request acknowledge
signal and transfer end signal from pins.
When a transfer request input from a pin is accepted for execution of a DMA transfer,
DMAC outputs a transfer request acknowledge signal.
When a transfer request input from a pin is accepted for execution of a DMA transfer
and the DMACT bit becomes 0, ending the transfer, DMAC outputs a transfer end signal.
■ Transfer Acknowledge Signal Output
The transfer request acknowledge signal is an active low pulse and is output for a transfer data access.
Output of this signal synchronized with transfer source access, transfer destination access, or both can be
specified by the AKSE and AKDE bits in DATCR.
■ Transfer End Signal Output
The transfer end signal is an active low pulse and is output for the last transfer data access.
Output of this signal synchronized with transfer source access, transfer destination access, or both can be
specified by the EPSE and EPDE bits in DATCR.
329
CHAPTER 14 DMA CONTROLLER (DMAC)
14.6
Notes on DMA Controller
This section provides notes on using the DMA controller.
■ Priority of Channels
Once the DMAC is activated for a DMA transfer request from a channel, transfer requests from other
channels are not accepted but are instead kept as pending until termination of the transfer being executed.
If transfer requests from more than one channel are active concurrently when DMAC detects a DMA
transfer request, the priority of the channels from which the requests are accepted are determined as
follows:
(High) channel 0 > channel 1 > channel 2 > channel 3 > channel 4 > channel 5 > channel 6 >
channel 7 (low)
If requests are issued concurrently from more than one channel, before DMA transfer on the next channel is
executed, bus control returns to the CPU when DMA transfer on the current channel has been executed.
■ Using a Resource Interrupt Request as a DMA Transfer Request
If DMAC transfer is to be executed, the level of the relevant interrupt in the interrupt controller must be
disabled.
If an interrupt is to be generated, the DMAC operation enable bit in DMAC must be disabled to set the
interrupt level to an appropriate value.
■ Suppressing DMA Transfer when a High-Priority Interrupt Occurs
The MB91121 has a function that stops DMA transfer if a higher-priority interrupt request is generated
during DMA transfer for a DMA transfer request.
● HRCL register
The Hold Request Cancel Level register (HRCL) in the interrupt controller can be used to stop DMA
transfer operation when an interrupt request is generated.
If the interrupt level set in an interrupt request generated from a peripheral circuit is a higher-priority value
than the level set in HRCL, DMAC DMA transfer operation is suppressed. If a DMA transfer operation is
being executed, the operation is stopped at a transfer operation break and the bus grant is released to the
CPU. When DMAC is waiting for generation of a DMA transfer request, a generated DMA transfer request
is kept pending.
After reset, HRCL is set to the lowest-priority level (31), at which DMA transfer operation is suppressed
for all interrupt requests. To carry out a DMA transfer when an interrupt request is generated, set the HRCL
register to the necessary value.
● PDRR register
The function that suppresses DMA transfer operation through specification in the HRCL register is valid
only when a higher-priority interrupt request is active. For example, when an interrupt request is cleared in
the interrupt handler program, suppression of DMA transfer based on the HRCL register is canceled,
possibly causing the CPU to lose the bus grant.
The PDRR register is provided in the clock controller to clear an interrupt request and suppress DMA
transfer so that other interrupt requests can be accepted.
330
CHAPTER 14 DMA CONTROLLER (DMAC)
Writing any value except 0 to PDRR in the interrupt handler suppresses DMA transfer operation.
To cancel suppression of DMA transfer operation, write 0 to PDRR.
■ DMA Transfer Operation in Sleep Mode
DMA transfer in sleep mode is not allowed.
■ Transfer to DMAC Internal Register
Do not specify the DMAC internal register as the transfer destination address.
■ Continuous Transfer
In continuous transfer mode, descriptor write-back may occur during transfer depending on the status of the
device’s internal bus buffer. The transfer operation continues, however.
■ DMA Transfer Request Resources
Table 14.6-1 lists the DMA transfer request resources.
Table 14.6-1 DMA Transfer Request Resources
Channel number
Transfer request resource
0
External transfer request input pin DREQ0
1
External transfer request input pin DREQ1
2
External transfer request input pin DREQ2
3
Software DMA activation
4
UART channel 0 reception
5
UART channel 0 transmission
6
DSP macro DMA transfer request 1
7
DSP macro DMA transfer request 2
● Error status for DMAC transfer request source
Only channel 4 can use the DACSR DERn bit to report that an error occurred at the DMA request source.
If the following error occurs when a UART channel 0 reception interrupt is used as a DMA transfer
request, the DER4 bit is set to 1:
• Parity error
• Overrun error
• Framing error
331
CHAPTER 14 DMA CONTROLLER (DMAC)
14.7
DMA Controller Timing Chart
This section shows the following timing charts for DMA controller operation:
• Timing chart for descriptor access section
• Timing chart for data transfer section
• Timing chart for stopping a transfer in continuous transfer mode
• Timing chart for transfer end operation
■ Symbols Used in the Timing Charts
Table 14.7-1 Symbols in Timing Charts
Symbol
#0
Descriptor 0
#0H
Descriptor 0, bits 31 to 16
#0L
Descriptor 0, bits 15 to 0
#1
Descriptor 1
#1H
Descriptor 1, bits 31 to 16
#1L
Descriptor 1, bits 15 to 0
#2
Descriptor 2
#2H
Descriptor 2, bits 31 to 16
#2L
Descriptor 2, bits 15 to 0
#1/2
Descriptor 1 or 2 (determined by SCS1, SCS0, DCS1, and DCS0)
#1/2H
Descriptor 1 or 2, bits 31 to 16
#1/2L
Descriptor 1 or 2, bits 15 to 0
S
332
Meaning
Transfer source
SH
Transfer source, bits 31 to 16
SL
Transfer source, bits 15 to 0
D
Transfer destination
DH
Transfer destination, bits 31 to 16
DL
Transfer destination, bits 15 to 0
CHAPTER 14 DMA CONTROLLER (DMAC)
14.7.1
Timing Chart for Descriptor Access Section
This section shows the timing chart for the descriptor access section.
■ Descriptor Access Section, 16/8-bit Data
● Request pin input mode: Level, descriptor address: External
(A)
CLK
DREQn
Addr pin
Data pin
#0L
#0H
#0H
#1H
#0L
#1H
#2L
#2H
#1L
#1L
#2H
S
#2L
S
RDX
WRnX
DACK
EOP
● Request pin input mode: Level, descriptor address: Internal
(A)
Internal KB
CLK
DREQn
Addr pin
S
Data pin
S
RDX
WRnX
DACK
EOP
● Request pin input mode: Edge, descriptor address: External
(A)
CLK
DREQn
Addr pin
Data pin
#0H
#0H
#0L
#0L
#1H
#1H
#1L
#1L
#2H
#2H
#2L
#2L
S
S
RDX
WRnX
DACK
EOP
333
CHAPTER 14 DMA CONTROLLER (DMAC)
● Request pin input mode: Edge, descriptor address: Internal
(A)
CLK
DREQn
Addr pin
Data pin
S
S
RDX
WRnX
DACK
EOP
Note:
The fastest timing from generation of DREQn to the start of DMAC operation is described.
Actually, bus contention caused by CPU instruction fetching and data access may delay the start of
DMAC operation.
334
CHAPTER 14 DMA CONTROLLER (DMAC)
14.7.2
Timing Chart for Data Transfer Section
This section shows the timing chart for the data transfer section.
■ Data Transfer Section, 16-/8-bit Data
● Transfer source area: External, transfer destination area: External
(A)
CLK
DREQn
Add pin
#2
Data pin
S
D
S
#2
S
D
S
D
S
D
S
D
D
S
D
S
D
RDX
W
WRnX
W
W
DACK
EOP
● Transfer source area: External, transfer destination area: Internal RAM
(A)
CLK
DREQn
Addr pin
S
#2
Data pin
#2
S
S
S
S
S
S
S
RDX
WRnX
DACK
EOP
● Transfer source area: Internal RAM, transfer destination area: External
(A)
CLK
DREQn
Addr pin
Data pin
#2
#2
D
D
D
D
D
D
D
D
W
W
W
W
RDX
WRnX
DACK
EOP
335
CHAPTER 14 DMA CONTROLLER (DMAC)
14.7.3
Timing Chart for Stopping a Transfer in Continuous
Transfer Mode
This section shows the timing chart for stopping a transfer in continuous transfer
mode.
■ Stopping a Transfer in Continuous Transfer Mode (If One of Addresses is Fixed),
16/8-bit Data
● Transfer source area: External, transfer destination area: External
CLK
DREQn
Addr pin
D
Data pin
D
S
S
D
#0H
#1/2H
#1/2L
D
#0H
#1/2H
#1/2L
W
W
W
W
#0H
#1/2H
#1/2L
#0H
#1/2H
#1/2L
W
W
W
RDX
WRnX
W
DACK
EOP
● Transfer source area: External, transfer destination area: Internal RAM
CLK
DREQn
Addr pin
S
S
Data pin
S
S
RDX
WRnX
DACK
EOP
● Transfer source area: Internal RAM, transfer destination area: External
CLK
DREQn
Addr pin
D
D
D
#0H
#1/2H
#1/2L
Data pin
D
D
D
#0H
#1/2H
#1/2L
W
W
W
W
W
W
RDX
WRnX
DACK
EOP
336
CHAPTER 14 DMA CONTROLLER (DMAC)
■ Stopping a Transfer in Continuous Transfer Mode (If Both Addresses Change),
16/8-bit Data
● Transfer source area: External, transfer destination area: External
CLK
DREQn
Addr pin
D
Data pin
D
S
S
D
#0H
#1H
#1L
#2H
#2L
D
#0H
#1H
#1L
#2H
#2L
W
W
W
W
W
W
RDX
WRnX
W
DACK
EOP
● Transfer source area: External, transfer destination area: Internal RAM
CLK
DREQn
Addr pin
S
Data pin
S
S
S
#0H
#1H
#1L
#2H
#2L
#0H
#1H
#1L
#2H
#2L
W
W
W
W
W
RDX
WRnX
DACK
EOP
● Transfer source area: Internal RAM, transfer destination area: External
CLK
DREQn
Addr pin
D
D
D
#0H
#1H
#1L
#2H
#2L
Data pin
D
D
D
#0H
#1H
#1L
#2H
#2L
W
W
W
W
W
W
W
W
RDX
WRnX
DACK
EOP
337
CHAPTER 14 DMA CONTROLLER (DMAC)
14.7.4
Timing Chart for Transfer End Operation
This section shows the timing chart for the transfer end operation.
■ Transfer End Operation (If One of Addresses is Fixed)
● Bus width: 16 bits, data length: 8 or 16 bits
CLK
Addr pin
D
Data pin
D
S
S
D
S
S
D
D
#0H
#1/2H
#1/2L
D
#0H
#1/2H
#1/2L
W
W
W
W
RDX
WRnX
W
W
AKSE=1
DACK
AKDE=1
Both are 1
EPSE=1
EOP
EPDE=1
Both are 1
● Bus width: 16 bits, data length: 32 bits
CLK
Addr pin
Data pin
SH
SL
SH
SL
DH
DL
DH
DL
W
W
SH
SH
SL
SL
DH
DL
#0H
#1/2H
#1/2L
DH
DL
#0H
#1/2H
#1/2L
W
W
W
W
W
RDX
WRnX
AKSE=1
DACK
AKDE=1
Both are 1
EPSE=1
EOP
EPDE=1
Both are 1
338
CHAPTER 14 DMA CONTROLLER (DMAC)
■ Transfer End Operation (If Both Addresses Change)
● Bus width: 16 bits, data length: 8 or 16 bits
CLK
Addr pin
S
D
Data pin
D
S
D
D
S
S
D
#0H
#1H
#1L
#2H
#2L
D
#0H
#1H
#1L
#2H
#2L
W
W
W
W
W
W
RDX
WRnX
W
W
AKSE=1
DACK
AKDE=1
Both are 1
EPSE=1
EOP
EPDE=1
Both are 1
● Bus width: 16 bits, data length: 32 bits
CLK
Addr pin
Data pin
SH
SL
SH
SL
DH
DL
DH
DL
W
W
SH
SH
SL
SL
DH
DL
#0H
#1H
#1L
DH
DL
#0H
#1H
#1L
W
W
W
W
W
RDX
WRnX
AKSE=1
DACK
AKDE=1
Both are 1
EPSE=1
EOP
EPDE=1
Both are 1
CLK
Addr pin
#2H
#2L
Data pin
#2H
#2L
W
W
RDX
WRnX
339
CHAPTER 14 DMA CONTROLLER (DMAC)
14.8
DMA Controller Software Trigger Circuit (STRG)
The DMA controller software trigger circuit uses a software trigger to activate DMA
controller.
■ Software Trigger Register (STRG)
The software trigger register (STRG) has the following configuration:
STRG
bit
Address: 000050H
15
14
13
12
11
10
-
-
-
-
-
-
9
8
CLRX TRG
R/W
Initial value
------00B
R/W
Bit 9: CLRX
This bit specifies whether the software trigger bit is cleared.
0: The TRG bit is automatically cleared by DACK from DMA controller.
1: The TRG bit is not cleared by DACK from DMA controller.
Do not rewrite this bit during DMA controller activation.
Bit 8: TRG
This bit is a software trigger bit.
0: No software trigger. Writing 0 and reset set this bit to 0.
1: DMA controller activation request by software trigger
■ Operation of DMA Controller Software Trigger Circuit
Writing 1 to the TRG bit in the STRG register activates DMA controller.
If the CLRX bit is set to 0, the TRG bit is automatically cleared by DACK from DMA controller.
Even if the specified transfer count is not reached, a value of 1 must be rewritten to the TRG bit to execute
the next transfer.
If the CLRX bit is set to 1, the TRG bit is not cleared by DACK from DMA controller.
Once DMA controller is activated, it automatically continues executing transfer until the specified transfer
count is reached.
If this mode is used, the TRG bit remains set to 1 at the end of DMA transfer and the CPU must clear this
bit.
340
CHAPTER 15
BIT SEARCH MODULE
This chapter gives an outline of the bit search module
and explains the register configuration and functions,
the module operations, and the save/return processing.
15.1 Outline of the Bit Search Module
15.2 Registers of the Bit Search Module
15.3 Bit Search Module Operations and Save/Restore Processing
341
CHAPTER 15 BIT SEARCH MODULE
15.1
Outline of the Bit Search Module
The bit search module searches data written into an input register for 0, 1 or a change
point and returns the detected position.
■ Block Diagram of the Bit Search Module
Figure 15.1-1 shows a block diagram of the bit search module.
Figure 15.1-1 Block Diagram of the Bit Search Module
D-bus
Input latch
Address
decoder
Detection
mode
Detection data
Bit search circuit
Retrieval result
■ Registers of the Bit Search Module
Figure 15.1-2 shows the registers of the bit search module.
Figure 15.1-2 Registers of the Bit Search Module
31
342
0
Address: 0003F0H
BSD0
Data register for 0-detection
Address: 0003F4H
BSD1
Data register for 1-detection
Address: 0003F8H
BSDC
Data register for change point detection
Address: 0003FCH
BSRR
Detection result register
CHAPTER 15 BIT SEARCH MODULE
15.2
Registers of the Bit Search Module
The bit search module has the following four registers:
• Data register for 0-detection (BSD0)
• Data register for 1-detection (BSD1)
• Data register for change point detection (BSDC)
• Detection result register (BSRR)
■ Data Register for 0-detection (BSD0)
31
0
0003F0H
Read/write → W
Initial value → XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
Write data is checked for 0.
Reset initializes this register to an undefined value.
The read value is not defined.
Use a 32-bit data transfer instruction for data transfer. (Do not use an 8-bit or 16-bit data transfer
instruction.)
■ Data Register for 1-detection (BSD1)
31
0
0003F4H
Read/write → R/W
Initial value → XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
Use a 32-bit data transfer instruction for data transfer. (Do not use an 8-bit or 16-bit data transfer
instruction.)
● Write
Write data is checked for 1.
● Read
The internal status save data of the bit search module is read. This register is used to save and restore the
original status when the interrupt handler uses the bit search module. Even when data is written into the
data register for 0 or change point detection or into the detection result register, the data can be saved and
restored using only this register for 1.
Reset initializes this register to an undefined value.
343
CHAPTER 15 BIT SEARCH MODULE
■ Data Register for Change Point Detection (BSDC)
31
0
0003F8H
Read/write → W
Initial value → XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
Write data is checked for a change point.
Reset initializes this register to an undefined value.
The read value is not defined.
Use a 32-bit data transfer instruction for data transfer. (Do not use an 8-bit or 16-bit data transfer
instruction.)
■ Detection Result Register (BSRR)
31
0003FCH
Read/write → R
Initial value → XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
The 0, 1, or change point detection data is read from this register.
The data type is determined by the last write data.
344
0
CHAPTER 15 BIT SEARCH MODULE
15.3
Bit Search Module Operations and Save/Restore
Processing
This section explains the 0-detection, 1-detection, and change point detection
operations of the bit search module and the save/restore processing.
■ 0-detection
Data written into the data register for 0-detection is scanned from MSB to LSB and the first 0 position is
returned.
The detection result is obtained by reading the detection result register.
Table 15.3-1 shows the relationships between detection positions and return values.
If 0 does not exist (i.e, FFFFFFFFH), 32 is returned as the search result.
[Example of execution]
Write data
Read value (decimal)
11111111 11111111 11110000 00000000B (FFFFF000H)
==>
20
11111000 01001001 11100000 10101010B (F849E0AAH)
==>
5
10000000 00000010 10101010 10101010B (8002AAAAH)
==>
1
11111111 11111111 11111111 11111111B (FFFFFFFFH)
==>
32
■ 1-detection
Data written into the data register for 1-detection is scanned from MSB to LSB and the first 1 position is
returned.
The detection result is obtained by reading the detection result register.
Table 15.3-1 shows the relationships between detection positions and return values.
If 1 does not exist (i.e, 00000000H), 32 is returned as the search result.
[Example of execution]
Write data
Read value (decimal)
00100000 00000000 00000000 00000000B (20000000H)
==>
2
00000001 00100011 01000101 01100111B (01234567H)
==>
7
00000000 00000011 11111111 11111111B (0003FFFFH)
==>
14
00000000 00000000 00000000 00000001B (00000001H)
==>
31
00000000 00000000 00000000 00000000B (00000000H)
==>
32
■ Change Point Detection
Data written into the data register for change point detection is scanned from bit 30 to LSB and compared
to the MSB value. The first non MSB value is returned.
The detection result is obtained by reading the detection result register.
Table 15.3-1 shows the relationships between detection positions and return values.
If no change points exist, "32" is returned as the search result.
This register never returns "0".
345
CHAPTER 15 BIT SEARCH MODULE
[Example of execution]
Write data
Read value (decimal)
00100000 00000000 00000000 00000000B (20000000H)
==>
2
00000001 00100011 01000101 01100111B (01234567H)
==>
7
00000000 00000011 11111111 11111111B (0003FFFFH)
==>
14
00000000 00000000 00000000 00000001B (00000001H)
==>
31
00000000 00000000 00000000 00000000B (00000000H)
==>
32
11111111 11111111 11110000 00000000B (FFFFF000H)
==>
20
11111000 01001001 11100000 10101010B (F849E0AAH)
==>
5
10000000 00000010 10101010 10101010B (8002AAAAH)
==>
1
11111111 11111111 11111111 11111111B (FFFFFFFFH)
==>
32
Table 15.3-1 Relationships between Detection Positions and Return Values
Detection
position
Return
value
Detection
position
Return
value
Detection
position
Return
value
Detection
position
Return
value
31
0
23
8
15
16
7
24
30
1
22
9
14
17
6
25
29
2
21
10
13
18
5
26
28
3
20
11
12
19
4
27
27
4
19
12
11
20
3
28
26
5
18
13
10
21
2
29
25
6
17
14
9
22
1
30
24
7
16
15
8
23
0
31
None
32
■ Save/Restore Processing
If it is necessary to save and restore the internal status of the bit search module, for example, when the bit
search module is used in the interrupt handler, proceed as follows:
1. Reading the data register for 1-detection and save the contents (Save)
2. Using the bit search module
3. Writing the data saved in 1) into the data register for 1-detection (Restore)
The read value from the detection result register depends on the contents written into the bit search module
before 1).
Even when the data register written last is for 0-detection or change point detection, the above procedure
restores the data correctly.
346
CHAPTER 16
SUM-OF-PRODUCTS MACRO
(SIMPLE DSP)
This chapter outlines the sum-of-products macro (DSP
hereafter) and explains the register configuration and
functions and DSP operations.
16.1 Outline of DSP
16.2 Block Diagram of the DSP
16.3 Registers of the DSP
16.4 DSP Instructions
16.5 DSP Operation Mode
16.6 DSP Functions
16.7 DMA Transfer When Y-RAM Bank Is Disabled
16.8 DMA Transfer When Y-RAM Bank Is Enabled
16.9 Y-RAM Expansion Configuration
16.10 Y-RAM Expansion Mode
16.11 Example of Using Y-RAM Expansion Mode
347
CHAPTER 16 SUM-OF-PRODUCTS MACRO (SIMPLE DSP)
16.1
Outline of DSP
The DSP is a sum-of-products unit with internal program RAM.
■ Features of the DSP
• High-speed sum-of-products operation (1 machine cycle)
• Data format: 16-bit fixed-point (16 × 16 + 40 bits)
• Instruction area: 256 × 16 bits
• Data area
- X-RAM 64 × 16 bits
- Y-RAM 1024 × 16 bits × 2
• Rounding
• Saturation
• Number of items to be added: Up to 64 items
• Instructions: MAC, STR, and JMP instructions
• Delayed processing: Transferable within 32 words
• Fixed-point method: Selectable from Q12 to Q15
• Program execution control: Eight calculation programs selectable externally
• Variable monitor: Monitoring of calculation results of up to 8 bytes without stopping the program
• Efficient data variable area
- Data variable area divisible into two banks, with other bank available for execution of the DSP
calculation program during data variable access from the CPU.
- Y-RAM expansion mode enables a space up to 2 K-byte to be used. If bank control is not used, bank
1 can be used as CPU data RAM. If the DSP is used, both banks 0 and 1 can be used as CPU data
RAM.
348
CHAPTER 16 SUM-OF-PRODUCTS MACRO (SIMPLE DSP)
16.2
Block Diagram of the DSP
Figure 16.2-1 shows a block diagram of the DSP, and Table 16.2-1 outlines each block.
■ Block Diagram of the DSP
Figure 16.2-1 Block Diagram of the DSP
DMA transfer request 1
DMA transfer request 2
CPU-D bus
DSP-CSR
Y-BANKC
Y bank control signal
DSP-PC
Instruction decoder
I-RAM
(256
16)
Software interrupt
IRQ33
I
F
DEC1
Y-RAM
expansion
function
DEC
Address
Offset interrupt
IRQ34
32
Operation section
X-RAM
(64
16)
40
16
Y-RAM
Extended
address
32
16
A
D
D
40
A
C
C
40
RND
CLP
SLQ
16
MUL
1024
16
1024
16
Delay register
DSP-LY
LY-DLY
MPX
Conversion monitor
DSP-OT3
DSP-OT2
DSP-OT1
DSP-OT0
349
CHAPTER 16 SUM-OF-PRODUCTS MACRO (SIMPLE DSP)
Table 16.2-1 Outline of DSP Blocks (1 / 2)
Configuration
Y-RAM
expansion
function
The maximum address space that can be specified in the macro instruction and
store instruction is 64 words.
This function is used to add an offset to each instruction space and expand it to a
1024-word space in Y-RAM.
The store instruction also has a mode in which data is sequentially stored from the
specified address in the 1024-word space.
Y-BANKC
Y-RAM bank control is disabled or enabled. If Y-RAM control is disabled, DMA
request 1 is output for an interrupt request.
Y-RAM bank selection and control
• There is one mode in which the bank is switched at the same time that GoDSP is
executed.
• The bank can also be switched according to the setting in the register.
DMA activation is enabled or disabled.
• The output of DMA request 1 that is output during execution of GoDSP or for an
interrupt request can be set. The output of DMA request 2 that is output after the
DMA transfer for DMA request ends 1 can be set.
DSP-CSR
DSP operation control register. The following are controlled from the CPU:
• Calculation start and end instructions
• Interrupt control
• Program flow control (used for conditional branch instructions in DSP.)
DSP-PC
Program counter.
Program execution starts from the first address set from the CPU.
I-RAM
256 × 16-bit instruction RAM.
This RAM can be read and written to from the CPU when the DSP is not
performing any calculations.
Before calculation starts, load the instruction code from the CPU.
IF *
Instruction fetch register
DEC1 *
DEC *
Instruction decoder
Operation control
Instruction control
350
Explanation
CHAPTER 16 SUM-OF-PRODUCTS MACRO (SIMPLE DSP)
Table 16.2-1 Outline of DSP Blocks (2 / 2)
Configuration
Explanation
X-RAM
64 × 16-bit data RAM.
This RAM can be read and written to from the CPU while the DSP is not
performing any calculations.
Before calculation starts, load the coefficient from the CPU.
Y-RAM
1024 × 16-bit data RAM (in Y-RAM expansion mode).
Before calculation starts, load the variable from the CPU.
While the DSP is in the calculating state, the bank RAM that is being used for
calculation cannot be read and written to from the CPU. The unused bank RAM
can be read and written to from the CPU.
When the DSP stops calculation, the bank RAM not selected by the bank selection
bit can be read and written to from the CPU.
MUL *
16 × 16 → 32-bit multiplier
ADD *
32 + 40 → 40-bit adder
ACC *
40-bit accumulator
CLP *
RND *
SLQ *
During 40→ to 16-bit transfer, 16-bit data outside the range is saturated to the
maximum value.
During 40→ to 16-bit transfer, the low-order bit is rounded.
During 40→ to 16-bit transfer, the transfer bit is selected.
Delay register
DSP-LY
LY-DLY *
Delay register.
During sum-of-products operation, the variable value can be retained and written
back to Y-RAM.
Variable monitor
output
DSP-OT0
DSP-OT1
DSP-OT2
DSP-OT3
Variable monitor output register
The same values as the contents of addresses 0 to 3 of the DSP bank in Y-RAM are
held.
During calculation (while Y-RAM access is disabled), the values at Y-RAM
addresses 0 to 3 can be monitored.
Operation section
*: Not accessible from the CPU
351
CHAPTER 16 SUM-OF-PRODUCTS MACRO (SIMPLE DSP)
16.3
Registers of the DSP
Figure 16.3-1 shows the DSP registers.
■ DSP Registers
Figure 16.3-1 DSP Registers
158
Address:000210H
Address:000212H
Address:000214H
Address:000216H
Address:000218H
Address:00021AH
Address:00021CH
Address:00021EH
Address:000220H
Address:000222H
Address:000224H
7
Mapping when YRAM bank is used
FR Address
002000H
DSP Address
Access disabled
0027FEH
002800H
002FFEH
00F000H
00F07EH
00F100H
00F2FEH
0
OFAS (offset address initial value setting)
STRS (store counter initial value setting)
OFSC (offset control)
OFSS (offset instruction address)
Y-BANKC (bank control)
OFSD (offset setting)
DSP-PC (program counter)
DSP-CSR (control/status)
DSP-LY (delay register) high order
DSP-LY (delay register) low order
DSP-OT0 (output queue 0) high order
DSP-OT0 (output queue 0) low order
DSP-OT1 (output queue 1) high order
DSP-OT1 (output queue 1) low order
DSP-OT2 (output queue 2) high order
DSP-OT2 (output queue 2) low order
DSP-OT3 (output queue 3) high order
DSP-OT3 (output queue 3) low order
Y-RAM
(variable RAM)...
2048 bytes
Banks 0 and 1
X-RAM
(coefficient RAM)...
128 bytes
I-RAM
(instruction RAM)...
512 bytes
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R
R
R
Mapping when YRAM bank is not used
FR Address
002000H
None
00H
0027FEH
002800H
3FFH
002FFEH
00H
00F000H
3FH
00F07EH
00H
00F100H
FFH
00F2FEH
DSP Address
Y-RAM
(variable RAM)...
2048 bytes
Bank 1
Y-RAM
(variable RAM)...
2048 bytes
Bank 0
X-RAM
(coefficient RAM)...
128 bytes
I-RAM
(instruction RAM)...
512 bytes
None
(data RAM for CPU)
00H
3FFH
00H
3FH
00H
FFH
Note:
To write data from the CPU to the DSP RAM (RAM that will be used for the DSP), always use an
instruction that transfers a word (half-word) to the even address.
352
CHAPTER 16 SUM-OF-PRODUCTS MACRO (SIMPLE DSP)
16.3.1
Offset Address Initial Value Setting Register (OFAS)
The offset address initial value setting register (OFAS) is used to set the initial value of
the offset address.
■ Offset Address Initial Value Setting Register (OFAS)
The offset address initial value setting register (OFAS) has the following configuration:
OFAS
bit
Address: 000210H
bit
15
14
13
12
11
10
9
8
-
-
-
-
X
X
X
X
0
0
0
0
7
6
5
4
3
2
1
0
OFA1 OFA1 OFA0 OFA0
(R/W) (R/W) (R/W) (R/W) ←Read and write
←Initial value
Address: 000211H OFA0 OFA0 OFA0 OFA0 OFA0 OFA0 OFA0 OFA0
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) ←Read and write
0
0
0
0
0
0
0
0
←Initial value
Bits 11 to 0: OFA11 to OFA00 (offset address initial value)
These bits are used to set the initial value of the offset address.
During calculation, rewriting of these bits is not allowed.
The read value is the Y-RAM offset address value.
Reset initializes these bits to 0.
353
CHAPTER 16 SUM-OF-PRODUCTS MACRO (SIMPLE DSP)
16.3.2
Store Address Initial Value Setting Register (STRS)
The store address initial value setting register is used to set the initial value of the store
address counter.
■ Store Address Initial Value Setting Register (STRS)
The store address initial value setting register (STRS) has the following configuration:
STRS
bit
Address: 000212H
bit
15
14
13
12
11
10
9
8
-
-
-
-
X
X
X
X
0
0
0
0
7
6
5
4
3
2
1
0
STA11 STA10 STA09 STA08
(R/W) (R/W) (R/W) (R/W) ←Read and write
←Initial value
Address: 000213H STA07 STA06 STA05 STA04 STA03 STA02 STA01 STA00
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) ←Read and write
0
0
0
0
0
0
0
Bits 11 to 0: STA11 to STA0 (store address counter initial value)
These bits are used to set the initial value of store address counter.
During calculation, rewriting of these bits is not allowed.
The read value is the value of the store address counter.
Reset initializes these bits to 0.
354
0
←Initial value
CHAPTER 16 SUM-OF-PRODUCTS MACRO (SIMPLE DSP)
16.3.3
Offset Control Setting Register (OFSC)
The offset control setting register is used to set offset control.
■ Offset Control Setting Register (OFSC)
The offset control setting register (OFSC) has the following configuration:
OFSC
bit
7
3
2
1
0
OFIC YRMD STRM
-
-
-
OFCC
(R/W) (R/W) (R/W) (R/W)
-
-
-
(R/W) ←Read and write
X
X
X
Address: 000214H OFIE
0
6
0
5
0
4
0
0
←Initial value
Bit 7: OFIE (interrupt request enable bit)
This bit controls interrupt requests (OFIC = 1) for the CPU as follows.
0
Disable interrupt request output (even if OFIC is set, an interrupt is not generated)
[initial value]
1
Enable interrupt request output (when OFIC is set, an interrupt is generated)
Reset initializes this bit to 0 (disable interrupt request output).
This bit can be read and written to.
Bit 6: OFIC (offset interrupt flag)
This bit is used as a flag to indicate that an interrupt request based on a limited offset count was
generated. When this bit is set to 1, the DSP stops calculation. The DSP cannot start calculation until the
CPU clears this flag.
When interrupt requests are enabled (OFIE = 1), setting this bit generates an interrupt request for the
CPU.
Set resource
Clear resource
Set when an interrupt request based on a limited offset count is generated
(DSP calculation stop)
Writing 0 [initial value]
Reset initializes this bit to 0 (no interrupt request).
This bit can be read and written to. However, only 0 can be written. Even if 1 is written, the bit value
does not change. The value read by a read-modify-write instruction is always 1 regardless of the bit
value.
355
CHAPTER 16 SUM-OF-PRODUCTS MACRO (SIMPLE DSP)
Bit 5: YRMD (Y-RAM expansion mode setting)
This bit specifies whether Y-RAM expansion mode is used. If expansion mode is not used, the maximum
space that can be used by Y-RAM is only a 64 × 16 space.
Writing 1
Enable Y-RAM expansion mode
Writing 0
Disable Y-RAM expansion mode
Reset initializes this bit to 0.
Bit 4: STRM (STR mode setting)
This bit is used to select how to specify the store destination during execution of the STR instruction.
During calculation, rewriting of this bit is not allowed.
Writing 1
Mode in which data is stored in Y-RAM at the address indicated by the store address
counter
Writing 0
Mode in which data is stored at the RAM address by the STR instruction
Reset initializes this bit to 0.
Bit 0: OFCC (offset clear)
This bit clears the offset count to 0.
The read value is always 0.
During calculation, rewriting of this bit is not allowed.
Writing 1
Set the offset addition counter value to 0.
Writing 0
Disable
Reset initializes this bit to 0.
356
CHAPTER 16 SUM-OF-PRODUCTS MACRO (SIMPLE DSP)
16.3.4
Offset Register (OFFSS)
An offset register is used to set the address of a JMP instruction to perform an offset
operation in I-RAM.
■ Offset Register (OFFSS)
The offset register has the following configuration:
OFSS
bit
7
6
5
4
3
2
1
0
Address: 000216H OFIA7 OFIA6 OFIA5 OFIA4 OFIA3 OFIA2 OFIA1 OFIA0
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) ←Read and write
0
0
0
0
0
0
0
0
←Initial value
Bits 7 to 0: OFIA7 to OFIA0: Address setting by performing the offset operation
The JMP instruction address to do operation of the offset in I-RAM is set.
During calculation, rewriting of this bit is not allowed.
Reset initializes this bit to 0.
357
CHAPTER 16 SUM-OF-PRODUCTS MACRO (SIMPLE DSP)
16.3.5
Y-RAM Bank Control Register (Y-BANKC)
The Y-RAM bank control register is used to switch between Y-RAM banks 0 and 1.
■ Y-RAM Bank Control Register (Y-BANKC)
The Y-RAM bank control register (Y-BANKC) has the following configuration:
Y-BANKC
bit
7
6
5
Address: 000217H YBEN
-
-
(R/W)
-
-
0
X
X
4
3
2
RDMAe WDMAe YBF
(R/W) (R/W)
0
0
1
0
YBSW YBMD
(R)
(W)
0
0
(R/W) ←Read and write
0
←Initial value
Bit 7: YBEN (Y-RAM bank control enable)
This bit is used to enable Y-RAM bank control.
During calculation, rewriting of this bit is not allowed.
Writing 1
The Y-RAM bank can be switched and a new bank used.
Writing 0
Y-RAM bank 0 is always used.
Reset initializes this bit to 0.
Bit 4: RDMe (DMA request 1 output enable)
This bit is used to enable or disable the output of DMA request 1.
When Y-RAM bank control is disabled, DMA request 1 is output by setting the software interrupt flag
(IrqDSP bit). When Y-RAM bank control is enabled, DMA request 1 is output during execution of
GoDSP.
Writing
Enable output of DMA request 1
Writing 0
Disable output of DMA request 1
Reset initializes this bit to 0.
Bit 3: WDMAe (DMA request 2 output enable)
This bit is used to enable or disable the output of DMA request 2 at the end of DMA transfer for DMA
request 1.
Writing 1
Enable output of DMA request 2 at the end of DMA transfer for DMA request 1
Writing 0
Disable output of DMA request 2 at the end of DMA transfer for DMA transfer request 1
Reset initializes this bit to 0.
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CHAPTER 16 SUM-OF-PRODUCTS MACRO (SIMPLE DSP)
Bit 2: YBF (bank status)
This bit is used to indicate the bank selection status.
Writing to this bit has no meaning.
Reading 1
Y-RAM bank 1 is connected to the DSP, and Y-RAM bank 0 is connected to the CPU
Reading 0
Y-RAM bank 0 is connected to the DSP and Y-RAM bank 1 is connected to the CPU
Reset initializes this bit to 0.
Bit 1: YBSW (bank switching)
This bit is used to switch the bank.
The read value is always 0.
During calculation, rewriting of this bit is not allowed.
When bank control is disabled, this bit is invalid.
Writing 1
Bank is switched
Writing 0
Bank is not switched
Reset initializes this bit to 0.
Bit 0: YBMD (bank switching condition setting)
This bit is used to switch the Y-RAM bank during execution of GoDSP.
When 1 is written to this bit and GoDSP is executed, the bank is switched to a different bank to execute
DSP calculation.
During calculation, rewriting of this bit is not allowed.
When bank control is disabled, this bit is invalid.
Writing 1
Y-RAM bank is switched during execution of GoDSP
Writing 0
Y-RAM bank is not switched during execution of GoDSP
Reset initializes this bit to 0.
359
CHAPTER 16 SUM-OF-PRODUCTS MACRO (SIMPLE DSP)
16.3.6
Offset Data Register (OFSD)
The offset data register is used to set the offset value to be added to the Y-RAM space
and the offset addition count limit.
■ Offset Data Register (OFSD)
The offset data register (OFSD) has the following configuration:
OFSD
bit
15
14
13
12
11
10
9
8
Address: 000218H OFS05 OFS04 OFS03 OFS02 OFS01 OFS00 OFC09 OFC08
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) ←Read and write
bit
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
←Initial value
Address: 000219H OFC07 OFC06 OFC05 OFC04 OFC03 OFC02 OFC01 OFC00
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) ←Read and write
0
0
0
0
0
0
0
0
←Initial value
Bits 15 to 10: OFS05 to OFS00: Additional offset value setting
The value set in this register is added to the offset address every time.
During calculation, rewriting of these bits is not allowed.
Reset initializes these bits to 0.
Bits 0 to 9: OFC09 to OFC00 (offset addition count limit setting)
When the count set in this register is reached, addition stops.
The addition count and additional offset value set in this register are added to the offset addresses.
When the last additional offset value is added to the offset address, the DSP stops calculation.
During calculation, rewriting of this bit is not allowed.
Reset initializes these bits to 0.
360
CHAPTER 16 SUM-OF-PRODUCTS MACRO (SIMPLE DSP)
16.3.7
Control/Status Register (DSP-CSR)
The control/status register is 8 bits long, and consists of a function that changes the
DSP states, a function that controls a software interrupt to the CPU, and flags indicating
the DSP states. This register is also used to set the conditions for a DSP conditional
branch instruction. This 8-bit register can always be read and written to externally.
• Control function
- Changing the DSP status (calculation start and stop) (GoDSP and HltDSP)
- Masking an interrupt to the CPU (IeDSP)
- Setting conditions of a DSP conditional branch instruction (USR2, USR1, and USR0)
• Status function
- Current DSP status acquisition flag (RunDSP)
- Software interrupt request flag (IrqDSP)
- Saturation processing flag (SatDSP)
■ Control/Status Register (DSP-CSR)
The control/status register has the following configuration:
DSP-CSR
bit
Address: 00021BH
7
6
5
4
3
2
1
0
HltDSP GoDSP
USR2 USR1 USR0 IrqDSP IeDSP
RunDSP
SatDSP
(R)
(R/W) (R/W) (R/W) (R/W) (R/W) (W) (R/W) ←Read and write
0
0
0
0
0
0
0
0
←Initial value
Bit 7: SatDSP (saturation processing flag)
This bit is used as the status flag to indicate that saturation processing was executed during calculation.
This bit is set if the STR instruction is used to specify saturation processing (CLP = 1) and the saturation
processing was actually executed. Once this bit is set during calculation, it holds the value until the next
calculation starts.
The start of calculation clears this bit.
Set resource
Clear resource
Set if saturation processing by the STR instruction is executed during calculation
Cleared by the start of calculation [initial value]
Reset initializes these bits to 0 (saturation processing is not executed).
These bits can only be read and cannot be changed by writing operations.
Bits 6, 5, and 4: USR2, USR1, and USR0 (jump condition setting bits)
These bits are referenced by the DSP conditional branch instruction. When these bit values and the UBP
flag of the conditional branch instruction match (the condition is established), the jump takes place.
Combining this conditional branch instruction and the calculation instruction enables switching among
the eight calculation routines from the CPU.
Reset initializes these bits to 000B.
361
CHAPTER 16 SUM-OF-PRODUCTS MACRO (SIMPLE DSP)
These bits can be read and written to.
Bit 3: IrqDSP (software interrupt request flag)
This bit is used as a flag to indicate that a DSP software interrupt request was generated. If this bit is set
when software interrupt requests are enabled (IeDSP = 1), a software interrupt request is generated for
the CPU.
Setting the SIRQ bit of an STR or JMP instruction to 1 generates a DSP software interrupt request.
When bank control is disabled, setting this flag enables the output of DMA transfer request 1.
Set resource
Clear resource
Set when a DSP software interrupt (STR or JMP instruction) is generated
Writing 0, or a clear signal from DMAC during DMA transfer without using
Y-RAM1 [initial value]
Reset initializes this bit to 0 (no software interrupt request).
This bit can be read and written to. Note that only 0 can be written to this bit. If 1 is written, the bit value
does not change. The value read by a read-modify-write instruction is always 1 regardless of the bit
value.
Bit 2: IeDSP (software interrupt request enable bit)
This bit is used to control a software interrupt request to the CPU (IrqDSP = 1) as follows.
When bank control is disabled, this bit does not affect the output of a DMA transfer request for a
software interrupt request.
0
Disable interrupt requests (an interrupt is not generated even if IrqDSP is set)
[initial value]
1
Enable interrupt requests (when IrqDSP is set, an interrupt is generated)
Reset initializes this bit to 0 (output of software interrupt requests is disabled).
This bit can be read and written to.
Bit 1: HltDSP (calculation stop)
This bit is used to forcibly stop calculation.
Writing 1 to this bit stops calculation and clears the RunDSP flag after the instruction being executed
terminates (after two cycles for a 2-cycle instruction) if calculation is being executed (RunDSP = 1).
This bit does not affect operation while calculation is stopped.
If this bit is used to forcibly stop calculation, DSP-PC refers to the next instruction address of the stopped
instruction. The instruction can be executed continuously.
Writing 1
Forcible stop
Writing 0
Invalid. The read value is always 0.
Reset initializes this bit to 0.
Note:
Do not write 1 to HltDSP and GoDSP at the same time.
362
CHAPTER 16 SUM-OF-PRODUCTS MACRO (SIMPLE DSP)
Bit 0: GoDSP (calculation stop)
RunDSP
Writing 1 to the GoDSP bit specifies the start of calculation. If calculation is stopped, calculation is
activated and the RunDSP flag is set. If calculation is already being executed (RunDSP = 1), this bit does
not affect the operation.
The RunDSP flag indicates that calculation is being executed. The start of calculation sets this flag.
Writing 1 to the HltDSP bit or executing the DSP HLT instruction clears this flag.
During execution of calculation (RunDSP = 1), DSP-PC, DSP-LY, X-RAM, Y-RAM, and IRAM cannot
be accessed from the CPU. Only DSP-OT0 to DSP-OT3 can be monitored.
The first address of the calculation routine must be stored in DSP-PC at the same time as or before
activation of calculation if calculation is to start.
Function during write (GoDSP: Calculation start)
0
No function or no effect on operation
1
If calculation is stopped: Calculation starts
If calculation is being executed: No effect
Function during read (RunDSP: Calculation execution flag)
0
Calculation is stopped [initial value]
Clear resource: HltDSP write and HLT
instruction execution
1
Calculation is being executed
Set resource: Calculation start
Reset initializes this bit to 0 (calculation is stopped).
Although this bit can be read and written to, its meaning varies between when it is read and when it is
written as shown above.
The value read by a read-modify-write instruction is always 0 regardless of the bit value.
Note:
Do not write 1 to HltDSP and GoDSP at the same time.
363
CHAPTER 16 SUM-OF-PRODUCTS MACRO (SIMPLE DSP)
16.3.8
Program Counter (DSP-PC)
The program counter is eight bits long and points to the address in memory (I-RAM)
containing the instruction code being executed by the DSP. The program counter is
automatically updated by executing the instruction but can be rewritten by the DSP JMP
instruction.
The program counter can be read and written to from the CPU only while calculation is
stopped. The first address of the calculation routine must be stored in DSP-PC at the
same time as or before calculation is started.
After execution of the HLT instruction or after 1 is written to HltDSP in DSP-CSR,
DSP-PC points to the next address of the stopped instruction. Setting GoDSP again
executes the program continuously.
■ Program Counter (DSP-PC)
The program counter (DSP-PC) has the following register configuration:
DSP-PC
bit
7
6
5
4
3
2
1
0
Address: 00021AH
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) ←Read and write
X
X
X
X
X
X
X
X
←Initial value
During reset, the program counter is undefined.
Although the program counter can be read and written to, it can be accessed only when the DSP is not
performing any calculations (DSP-CSR: RunDSP = 0). While calculations are being executed (DSP-CSR:
RunDSP = 1), the program counter cannot be accessed from the CPU because it is disconnected from the
bus.
364
CHAPTER 16 SUM-OF-PRODUCTS MACRO (SIMPLE DSP)
16.3.9
Delay Register (DSP-LY)
The DSP-LY register is 16 bits long, and is used if the delayed write bit (IDLY) of the DSP
MAC instruction is set to 1. During a calculation (DSP-CSR: RunDSP = 1), this register
cannot be accessed.
If the LDLY bit of the MAC instruction is set to 1, the following two operations are
executed sequentially:
• The contents of the DSP-LY register are transferred to the LY-DLY register.
• Data read from Y-RAM selected by the MAC instruction is stored in the DSP-LY
register.
If the STLY bit of the MAC instruction is set to 1, the LY-DLY register value is written to
the Y-RAM address selected by the MAC instruction after execution of the MAC
instruction. In this case, the execution time is two cycles.
■ Delay Register (DSP-LY)
The delay register (DSP-LY) has the following configuration:
DSP-LY
bit 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
Address: 00021CH
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) ←Read and write
X
X
X
X
X
X
X
X
←Initial value
During reset, this register is undefined.
Although this register can be read and written to, it can be accessed only when the DSP is not performing
any calculations (DSP-CSR: RunDSP = 0). During execution of a calculation (DSP-CSR: RunDSP = 1),
this register cannot be accessed from the CPU because it is disconnected from the bus.
365
CHAPTER 16 SUM-OF-PRODUCTS MACRO (SIMPLE DSP)
16.3.10
Variable Monitor Register (DSP-OT0 to DSP-OT3)
The variable monitor register has 16-bit registers for four words. This register holds the
same contents as the addresses 0 to 3 of the DSP bank in Y-RAM (bank 0 if YBF = 0 or
bank 1 if YBF = 1).
This register is always set read-only from the CPU. The contents of addresses 0 to 3 of
Y-RAM can be monitored even during calculation.
■ Variable Monitor Register (DSP-OT0 to DSP-OT3)
The variable monitor register (DSP-OT0 to DSP-OT3) has the following configuration:
DSP-OT0 to DSP-OT3
bit 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
OT0 address: 00021EH
OT1 address: 000220H
OT2 address: 000222H (R) (R) (R) (R) (R) (R) (R) (R) (R) (R) (R) (R) (R) (R) (R) (R) ←Read and write
OT3 address: 000224H X X X X X X X X X X X X X X X X ←Initial value
During reset, this register is undefined.
This register is always set read-only. It can be read even while the DSP is executing a program.
366
CHAPTER 16 SUM-OF-PRODUCTS MACRO (SIMPLE DSP)
16.4
DSP Instructions
DSP instructions consist of the following three types:
• MAC instructions
• STR instructions
• JMP instructions
■ DSP Instruction Definition
In this manual, the instructions other than MAC, STR, and JMP instructions are also used.
Such instructions have the following hierarchical structure:
● MAC instruction
• Sum-of-products instruction (CLAC bit is set to 0)
• Multiplication instruction (CLAC bit is set to 1)
● STR instruction
• HLT instruction (HLT bit is set to 1)
• INT instruction (SIRQ bit is set to 1)
● JMP instruction
• Unconditional branch instruction (COND bit is set to 0)
• Conditional branch instruction (COND bit is set to 1)
• HLT instruction (HLT bit is set to 1)
• INT instruction (SIRQ bit is set to 1)
■ DSP Instruction Operations
Writing 1 to the GoDSP bit in the DSP-CSR register causes the DSP to start instruction execution from the
current DSP-PC (program counter) value (concurrent operation with the CPU).
Before execution, set the I-RAM and DSP-PC values (DSP-CSR and DSP-PC can be set concurrently).
When DSP instruction execution is started, the following operation control is performed:
• When the DSP executes the HLT instruction, the state changes to the stopped state when instruction
execution ends. DSP-PC points to the next address of the HLT instruction and stops.
• During execution of the JMP and STR instructions, an interrupt request can be generated for the CPU
(interrupts can be masked).
• A conditional branch instruction that references the USR0 to USR2 bits in DSP-CSR is used to switch
the program flow.
Note:
The HLT instruction refers to an instruction whose HLT bit is set to 1 in the JMP and STR instruction.
367
CHAPTER 16 SUM-OF-PRODUCTS MACRO (SIMPLE DSP)
16.4.1
MAC Instruction
The MAC instruction adds the value obtained by multiplying X data in X-RAM and Y data
in Y-RAM to the accumulator value. The MAC instruction also transfers the contents of
the DSP-LY register to the LY-DLY register.
■ MAC Instruction
● Operation:
Acc ← Acc + X data × Y data
LY-DLY ← DSP-LY
DSP-LY ← Y data (if LDLY = 1)
Y-RAM ← LY-DLY (if STLY = 1)
● Number of words:
1 word
● Number of cycles:
1 machine cycle (2 cycles if STLY = 1)
● Operation code:
bit
15
1
14
13
12
CLAC STLY LDLY
11 to 6
5 to 0
X-Addr
Y-Addr
Bit 14: CLAC (Clear Acc.)
Setting this bit enables the MAC instruction to function as a multiplication instruction.
0: Acc ← Acc + X data × Y data [sum-of-products instruction]
1: Acc ← 0 + X data × Y data [multiplication instruction]
Bit 13: STLY (Store LY)
If this bit is set to 1, the following operation is executed. If this bit is set to 0, only an arithmetic operation
is executed.
After an arithmetic operation, the contents of the LY-DLY register are also stored at the Y-Addr address
in Y-RAM.
Only if this bit is set to 1 does the execution time become two cycles.
Bit 12: LDLY (Load LY)
If this bit is set to 1, the following operation is executed. If this bit is set to 0, only arithmetic operations
are executed.
During an arithmetic operation, the contents of the Y-Addr address in Y-RAM are also stored in the
DSP-LY register.
Bits 11 to 6: X-Addr (X-RAM Address)
These addressing bits are used to specify X data in X-RAM.
368
CHAPTER 16 SUM-OF-PRODUCTS MACRO (SIMPLE DSP)
Bits 5 to 0: Y-Addr (Y-RAM Address)
These addressing bits are used to specify Y data in Y-RAM.
Figure 16.4-1 shows how the MAC instruction operates.
Figure 16.4-1 MAC Instruction Operation
X-Addr
Y-Addr
X-RAM
Y-RAM
X
data
Y
data
if (STLY==1) then Store
if (LDLY==1) then Load
DSP-LY
Multiply-Add
LY-DLY
Calculator
CPU-Bus
369
CHAPTER 16 SUM-OF-PRODUCTS MACRO (SIMPLE DSP)
16.4.2
STR Instruction (Transfer Instruction)
The STR instruction converts 40-bit data in the accumulator to 16-bit data and stores it
in the data RAM specified by the SLY flag and X/Y-Addr as specified by the RND, CLD,
and SLQ flags.
■ STR Instruction (Transfer Instruction)
● Operation:
Data RAM ← accumulator
● Number of words:
1 word
● Number of cycles:
1 machine cycle
● Operation code:
bit
15
14
13
12
11
10
9~7
6
5~0
0
1
HLT
SIRQ
RND
CLP
SLQ
SLY
X/Y-Addr
Bit 13: HLT (HLT instruction specification flag)
Setting this bit causes the DSP to stop calculation after instruction execution. The RunDSP flag in the
DSP-CSR register is cleared.
Bit 12: SIRQ (INT instruction specification flag)
Setting this flag generates an interrupt request for the CPU and sets the IrqDSP flag in the DSP-CSR
register after instruction execution.
Bit 11: RND (Rounding)
This bit specifies rounding processing for 16-bit data specified by the SLQ bit.
Rounding processing discards 0 and includes 1 of a lower-order bit than the LSB of the 16-bit data.
Bit 10: CLP (Clipping)
If the calculation result value overflows 16-bit data specified by the SLQ bit, this bit specifies the
saturation processing for the 16-bit data.
Actually, if the MSB (39 bits) in the accumulator and MSB (specified in SLQ) in 16-bit data are not the
same values, saturation processing is executed. If rounding processing is specified, the value is compared
with the rounding result. If the accumulator value is positive before rounding processing, the maximum
positive value (7FFFH) is transferred. If it is negative, the maximum negative value (8000H) is
transferred.
Rounding processing and saturation processing save the sign of the accumulator value without inverting
it.
370
CHAPTER 16 SUM-OF-PRODUCTS MACRO (SIMPLE DSP)
Bits 9, 8, and 7: SLQ
These bits specify the positions of bits to be transferred from the accumulator to the data RAM.
SLQ bit
Overflow
determination bit
16-bit data to be
transferred
Rounded bit
Fixed-point
method
000
Bits 39 to 27
Bits 27 to 12
Bit 11
Q12
001
Bits 39 to 28
Bits 28 to 13
Bit 12
Q13
010
Bits 39 to 29
Bits 29 to 14
Bit 13
Q14
011
Bits 39 to 30
Bits 30 to 15
Bit 14
Q15
Bit 6: SLY
This bit specifies the transfer destination.
0: X-RAM
1: Y-RAM
Bits 5 to 0: X/Y-RAM (RAM Address)
These bits specify the data RAM address directly.
371
CHAPTER 16 SUM-OF-PRODUCTS MACRO (SIMPLE DSP)
16.4.3
JMP Instruction (Branch Instruction)
The JMP instruction branches if the condition is established and does nothing if it is
not established.
■ JMP Instruction (Branch Instruction)
● Operation:
When the condition is established: DSP-PC ← J-Addr8
When the condition is not established: DSP-PC ← DSP-PC + 1
● Number of words:
1 word
● Number of cycles:
● Operation code:
bit
15
14
13
0
0
HLT
12
11
SIRQ COND
10~8
7~0
UBP2, UBP1,
UBP0
J-Addr8
Bit 13: HLT (HLT instruction specification flag)
Setting this bit causes DSP to stop program execution after instruction execution. The RunDSP bit in the
DSP-CSR register is cleared.
Bit 12: SIRQ (INT instruction specification flag)
Setting this bit generates an interrupt request for the CPU and sets the IrqDSP bit in the DSP-CSR
register after instruction execution.
Bit 11: COND (CONDition)
0: Unconditional branch
1: Conditional branch
Bits 10, 9, and 8: UBP2, UBP1, and UBP0 (condition specification)
These bits are used to set the condition for a conditional branch. When USR2, USR1, and USR0 in the
DSP-CSP register and these bits match, the condition is established.
Bits 7 to 0: J-Addr8 (JumpAddress)
These bits specify the branch destination address.
372
CHAPTER 16 SUM-OF-PRODUCTS MACRO (SIMPLE DSP)
16.5
DSP Operation Mode
Operations on the DSP-CSR registers control the operation of the DSP.
The DSP has six states. Four states occur when bank control is enabled and two occur
when bank control is disabled.
■ DSP Operation Mode
● When bank control is disabled
Writing 1 to the GoDSP bit in the stopped state causes the DSP to start program execution.
Only Y-RAM bank 0 in Y-RAM is used. It can only be accessed from the CPU in the stopped state and can
only be accessed from the DSP in the calculating state.
● When bank control is enabled
Writing 1 to the GoDSP bit in the stopped state causes the DSP to start program execution.
The registers and memory that can be accessed from the CPU are not the same in the stopped and
calculating states.
The DSP operates for Y-RAM as follows:
• If YBMD is set to 1, calculation is started after the Y-RAM bank is switched.
• If YBMD is set to 0, calculation is started without switching the Y-RAM bank.
• Writing 1 to YBSW switches the Y-RAM bank in the stopped state. Writing 1 again returns the bank to
its original state.
Figure 16.5-1 shows the DSP operating states, and Table 16.5-1 explains the states.
373
CHAPTER 16 SUM-OF-PRODUCTS MACRO (SIMPLE DSP)
Figure 16.5-1 DSP Operating States
Y-RAM bank control disabled
Y-RAM bank control enabled
YBEN=0
Initial state
Stop
YBEN=1
YBEN=0
RunDSP=0
YBF=0
YBEN=0
GoDSP=1
HltDSP=1
or HLT instruction
YBSW=1
Stop
YBEN=1
RunDSP=0
YBF=0
Stop
YBEN=1
RunDSP=0
YBF=1
YBSW=1
GoDSP=1
YBMD=0
HltDSP=1
or HLT instruction
HltDSP=1
or HLT instruction
GoDSP=1
YBMD=1
GoDSP=1
YBMD=0
GoDSP=1
YBMD=1
Calculating
state
YBEN=0
RunDSP=1
YBF=0
374
Calculating
state
YBEN=1
RunDSP=1
YBF=0
Calculating
state
YBEN=1
RunDSP=1
YBF=1
Stopped state:
If YBEN = 0 and YBF = 0, Y-RAM
bank 0 is connected to the CPU
and the DSP is not connected to
Y-RAM.
Whether calculating or stopped state:
If YBEN = 1 and YBF = 0, Y-RAM bank 0 is connected to the
DSP and Y-RAM bank 1 is connected to the CPU.
Calculating state:
If YBEN = 0 and YBF = 0, Y-RAM
bank 0 is connected to the DSP
and the CPU is not connected to
Y-RAM.
Whether calculating or stopped state:
If YBEN = 1 and YBF = 1, Y-RAM bank 0 is connected to the
CPU and Y-RAM bank 1 is connected to the DSP.
CHAPTER 16 SUM-OF-PRODUCTS MACRO (SIMPLE DSP)
Table 16.5-1 Explanation of DSP States
Operation
State
Explanation
Stopped state
YBF=0
The DSP is in the stopped state.
Instruction RAM (I-RAM), data RAM (X-RAM and Y-RAM bank 0),
and all DSP registers can be accessed from the CPU.
System reset initializes the DSP to this state.
Calculating
state
YBF=0
The DSP is in the calculating state.
Writing 1 to the GoDSP bit in the stopped state switches to this state
and starts program execution from the current DSP-PC state (program
counter). Writing 1 to the HltDSP bit or executing the HLT
instruction switches to the stopped state and stops program execution.
Only DSP-CSR and DSP-OT0 to DSP-OT3 can be accessed from the
CPU (Access to other registers and RAM is disabled).
Stopped state
YBF=0
The DSP is in the stopped state.
Instruction RAM (I-RAM), data RAM (X-RAM and Y-RAM bank 1),
and all DSP registers can be accessed from the CPU.
Stopped state
YBF=1
The DSP is in the stopped state.
Instruction RAM (I-RAM), data RAM (X-RAM and Y-RAM bank 0),
and all DSP registers can be accessed from the CPU.
Calculating
state
YBF=0
The DSP is in the calculating state.
Writing 1 to the GoDSP bit in the stopped state switches to this state
and starts program execution from the current DSP-PC (program
counter). Writing 1 to the HltDSP bit or executing the HLT
instruction switches to the stopped state and stops program execution.
Only DSP-CSR, DSP-OT0 to DSP-OT3, and Y-RAM bank 1 can be
accessed from the CPU (Access to other registers and RAM is
disabled).
Calculating
state
YBF=1
The DSP is in the calculating state.
Writing 1 to the GoDSP bit in the stopped state switches to this state
and starts program execution from the current DSP-PC (program
counter). Writing 1 to the HltDSP bit or executing the HLT
instruction switches to the stopped state and stops program execution.
Only DSP-CSR, DSP-OT0 to DSP-OT3, and Y-RAM bank 0 can be
accessed from the CPU (Access to other registers and RAM is
disabled).
Y-RAM bank
disabled
Y-RAM bank
enabled
375
CHAPTER 16 SUM-OF-PRODUCTS MACRO (SIMPLE DSP)
16.6
DSP Functions
The DSP has the following functions:
• Arithmetic operation function
• Delayed write function
• Variable monitor output
■ Arithmetic Operation Function
The DSP has two kinds of 16-bit data RAM (X-RAM and Y-RAM). When sum-of-products (and
multiplication) instructions are executed, the DSP reads data from each type of RAM to perform signed
sum-of-products (and multiplication) operations and stores the result in the 40-bit accumulator.
Figure 16.6-1 shows the data format for the arithmetic operation function.
Figure 16.6-1 Data Format for Arithmetic Operation Function
15
S*1
0
X-RAM
S*1
39
S*1
31
S*1
Y-RAM
0
Multiplication result (32 bits)
S*1
Acc immediately before sum-of-products instruction
S*1
Acc (accumulator)*2
*1: S indicates the sign bit.
*2: When the multiplication instruction is executed, the value obtained by sign-extending
the multiplication result to 40 bits is stored in the accumulator (the contents of immediately
preceding accumulator are cleared to zero).
If the sum-of-products instruction is repeated many times, causing the accumulator to overflow, the result is
not guaranteed. Generally, do not repeat the sum-of-products instruction 16 times or more.
■ Result Transfer Processing
The calculation result contained in the accumulator is transferred to X-RAM or Y-RAM using 16-bit width
after the following scaling is executed:
● Output bit selection
The following bit widths can be selected from the 40-bit accumulator:
• Bits 27 to 12 (Q12 format)
• Bits 28 to 13 (Q13 format)
• Bits 29 to 14 (Q14 format)
• Bits 30 to 15 (Q15 format)
376
CHAPTER 16 SUM-OF-PRODUCTS MACRO (SIMPLE DSP)
● Rounding processing
Rounding processing discards 0 and includes 1 of the value immediately following the LSB in the selected
output bit.
● Saturation processing
If the sign bit (MSB) of the rounded 16-bit data and the high-order bit in the accumulator are compared and
a different value is found, saturation processing is executed. Saturation results in the following values
depending on the value of the sign bit (MSB) in the accumulator:
• If the sign of accumulator is 0 → Saturation to the maximum positive value (7FFFH).
• If the sign of accumulator is 1 → Saturation to the maximum negative value (8000H).
Figure 16.6-2 shows an example of result transfer processing.
Figure 16.6-2 Example of Result Transfer Processing
39
to
28
7FFH
27
to 12
FFFFH
11
to
0
FFFH
Accumulator
(Bits 27 to 12 selected): Scaling
FFFFH
1
(Accumulator bit 11): Rounding
0000H
0
Bit 15
Comparison
Saturation
(Saturated to maximum positive value): Saturation processing
processing
7FFFH
Transfer data
377
CHAPTER 16 SUM-OF-PRODUCTS MACRO (SIMPLE DSP)
■ Delayed Write Function
During execution of a sum-of-products (and multiplication) instruction, the following transfer operation can
also be performed. Combining this transfer and operation processing facilitates data delay processing using
the digital filter.
• Storing the value read from Y-RAM in the DSP-LY register
• Delayed writing of the DSP-LY register before instruction execution at the read address in Y-RAM via
the LY-DLY register
■ Variable Monitor Output
When data is written to addresses 0 to 3 of Y-RAM, the DSP can also write the that data in the DSP-OT0 to
DSP-OT3 registers.
When the DSP is in the calculating state, access to Y-RAM from the CPU is not allowed. The STR
instruction can be used to store the calculation result to be referenced by the CPU in addresses 0 to 3 of YRAM to ensure that the calculation result can always be referenced from the CPU.
Data is written to the variable monitor register (DSP-OT0 to DSP-OT3) under one of the following
conditions:
● Y-RAM bank not available, Y-RAM not in expansion mode
• Writing a word or half-word to 2800H, 2802H, 2804H, and 2806H from the CPU (when the DSP stops
calculation, a byte write is not allowed.)
• Writing data to Y0, Y1, Y2, and Y3 with an STR instruction
• Writing data to Y0, Y1, Y2, and Y3 with delayed writing
● Y-RAM bank available, Y-RAM not in expansion mode
Y-RAM expansion mode regardless of whether or not Y-RAM bank is available
• Writing data to Y0, Y1, Y2, and Y3 with an STR instruction (if the store address counter is used, data is
also written to DSP-OT0 to DSP-OT3 when the addresses indicated by the STR instruction are Y0, Y1,
Y2, and Y3.)
• Writing data to Y0, Y1, Y2, and Y3 with delayed writing
When data is written to the RAM from the CPU, data is not written to DSP-OT0 to DSP-OT3.
378
CHAPTER 16 SUM-OF-PRODUCTS MACRO (SIMPLE DSP)
16.7
DMA Transfer When Y-RAM Bank Is Disabled
DMA transfer requests 1 and 2 can be issued to the DMA controller.
■ DMA Transfer when Y-RAM Bank is Disabled
● Conditions under which transfer request 1 is issued
1. Output of DMA transfer request 1 is enabled (RDMAe bit: Bit 4 in the Y-BANKC register is set to 1).
2. If DSP operation is started in the state explained in 1) and a software interrupt request is generated,
DMA transfer request 1 is output.
● Conditions Under which DMA Transfer Request 2 is Issued
1. Output of DMA transfer request 2 is enabled (WDMAe bit: Bit 3 in the Y-BANKC register is set to 1.)
2. After the DMA transfer for DMA transfer request 1 in the state explained in 1) ends, DMA transfer
request 2 is output.
Figure 16.7-1 shows an example of a flowchart in which the DSP using DMA transfer is used when YBANC is not used.
Figure 16.7-1 Example of Flowchart in which the DSP Using DMA Transfer is Used
(When Y-BANKC is Not Used)
State
CPU bus
Bus master
CPU
DMA
Description
of
processing
DMA
setting
GoDSP
execution
DMA, DSP
termination confirmation
DMA transfer
request 1
DSP state
I-RAM
Stopped
Calculating
Program
write
DSP fetches
instruction and
executes
calculation
CPU
DMA termination
Bus release
Stopped
X-RAM
Coefficient
write
Y-RAM
BANK0
Variable 0
write
DSP fetches
coefficient
DSP fetches
variable 0 and
writes result 0
DMA fetches
result 0
Y-RAM
BANK1
379
CHAPTER 16 SUM-OF-PRODUCTS MACRO (SIMPLE DSP)
The operating state in the flowchart is as follows:
1. Load the DSP calculation program into I-RAM.
• This program ensures that the interrupt flag is set at the end of calculation.
• Interrupts to the CPU are disabled.
2. Load a coefficient into X-RAM.
3. Load a variable into Y-RAM.
4. Set the DMA controller.
• Set so that the result in Y-RAM is read for DMA transfer request 1.
5. Execute GoDSP.
• DMA transfer is executed after calculation terminates.
6. Confirm whether DSP calculation has terminated.
7. Confirm whether DMA terminated normally.
Note:
In the above flowchart, DMA transfer request 2 is not used.
380
CHAPTER 16 SUM-OF-PRODUCTS MACRO (SIMPLE DSP)
16.8
DMA Transfer When Y-RAM Bank Is Enabled
DMA transfer requests 1 and 2 can be issued to the DMA controller.
■ DMA Transfer when Y-RAM Bank is Enabled
● Conditions under which DMA request 1 is issued
1. Output of DMA transfer request 1 is enabled (RDMAe bit: Bit 4 in the Y-BANKC register is set to 1).
2. When GoDSP is executed in the state explained in 1), DMA transfer request 1 is output (GoDSP bit: 1 is
written to bit 0 in the DSP-CSR register).
● Conditions under which DMA transfer request 2 is issued
1. Output of DMA transfer request 2 is enabled (WDMAe bit: Bit 3 in the Y-BANKC register is set to 1.)
2. After the DMA transfer for DMA transfer request 1 in the state explained in 1) ends, DMA transfer
request 2 is output.
Figure 16.8-1 shows an example of a flowchart in which the DSP using DMA transfer is used when YBANKC is used.
Figure 16.8-1 Example of Flowchart in which DSP Using DMA Transfer is Used (When Y-BANKC is Used)
State
CPU bus
Bus master
CPU
DMA
Description
of
processing
GoDSP
DMA
setting execution
DMA transfer
request 1
DSP state
I-RAM
X-RAM
Y-RAM
BANK0
Y-RAM
BANK1
Stopped
Calculating
Program
write
Coefficient
write
Variable 0
write
CPU
DMA
DMA termination
Bus release
DMA transfer
request 1
Stopped
Calculating
DSP fetches
instruction and
executes
calculation
DSP fetches
coefficient
DSP fetches
variable 0 and
writes result 0
DMA fetches
result 0
DSP fetches
variable 1 and
writes result 1
CPU
DMA
DMA
DMA transfer
request 2
Stopped
DMA termination
Bus release
DMA transfer
request 1
Calculating
CPU
DMA, DSP
termination confirmation
DMA, DSP DMA GoDSP
termination setting execution
confirmation
DMA, DSP DMA GoDSP GoDSP
termination setting setting execution
confirmation
DSP fetches
instruction and
executes
calculation
DSP fetches
coefficient
DMA write
variable 1
DMA
DMA transfer
request 2
DMA termination
Bus release
Stopped
DSP fetches
instruction and
executes
calculation
DSP fetches
coefficient
DMA writes
variable 2
DSP fetches
variable 2 and
write result 2
DMA fetches
result 1
DMA writes
variable 3
381
CHAPTER 16 SUM-OF-PRODUCTS MACRO (SIMPLE DSP)
The operating state in the flowchart is as follows:
1. Load the DSP calculation program into I-RAM.
• This program ensures that the interrupt flag is set at termination of calculation.
• Interrupts to the CPU are disabled.
2. Load a coefficient into X-RAM.
3. Load variable 0 into Y-RAM.
4. Set the DMA controller.
• Set so that calculation variable 1 is written to Y-RAM for DMA transfer request 1.
• RDMAe is set to 1 so that a DMA request is output.
5. Execute GoDSP.
• DMA transfer is executed at the same time that calculation is executed.
6. Confirm whether DSP calculation terminated.
7. Confirm whether DMA terminated normally.
8. Set the DMA controller.
• Set so that result 0 in Y-RAM is read for DMA transfer request 1.
• Set so that calculation variable 2 is written to Y-RAM for DMA transfer request 2.
• RDMAe and WDMAe are set to 1 so that a DMA request is output.
9. Set so that the Y-RAM bank is switched during execution of GoDSP.
10.Execute GoDSP.
• DMA transfer is executed at the same time that calculation is executed.
11.Confirm whether DSP calculation terminated.
12.Confirm whether the DSP terminated normally.
13.Set the DMA controller.
• Set so that result 1 in Y-RAM is read for DMA transfer request 1.
• Set so that calculation variable 3 is written to Y-RAM for DMA transfer request 2.
14.Execute GoDSP.
• DMA transfer is executed at the same time that calculation is executed.
15.Confirm whether DSP calculation terminated.
16.Confirm whether the DSP terminated normally.
Calculation is subsequently executed the required number of times.
382
CHAPTER 16 SUM-OF-PRODUCTS MACRO (SIMPLE DSP)
16.9
Y-RAM Expansion Configuration
Figure 16.9-1 shows the Y-RAM expansion configuration.
■ Y-RAM Expansion Configuration
Figure 16.9-1 Y-RAM Expansion Configuration
FR-D bus
Offset interrupt
OFSC(bit6,7)
Offset interrupt
control
OFSC(bit5)
Y-RAM expansion
mode setting
DSP program
stop request
Y-RAM address
(6 bits)
OFSD(bit10 to bit15)
Additional offset
6bit
setting register
OFSD(bit0 to bit8)
ON
OFF
OFAS(bit11 to bit0)
Offset value
(initial value 0)
Offset addition count
setting register
Write
specification
12bit
Comparison circuit
6bit
DSP macro
Adder
12bit
Offset addition
counter
(10 bits)
CLRX
OFSC(bit0)
Offset addition specification
Offset clear
JMP instruction
executing
OFSS(bit0 to bit7)
I-RAM address
Comparison circuit
Offset specification
address set register
Expand 6 bits into
12 bits with zeros
OFSC(bit4)
STR mode setting
STRS(bit0 to bit11)
Store address counter
(12 bits)
Initial value setting
MAC
OF
Count value output
STR
Count clock input
ON
Expanded Y-RAM
address (12 bits)
Execution instruction
specification
(MAC or STR)
STR instruction
termination
specification
383
CHAPTER 16 SUM-OF-PRODUCTS MACRO (SIMPLE DSP)
16.10
Y-RAM Expansion Mode
Y-RAM expansion mode can be used to expand Y-RAM space that can be used by the
MAC and STR instructions from 128 to 2048 bytes.
If the JMP instruction execution count (offset count) specified by the DSP program in
I-RAM is incremented to the specified value, the DSP program can be stopped. When
DSP stops, an interrupt request can also be generated for the CPU.
■ Y-RAM Expansion Mode
In Y-RAM expansion mode, the Y-RAM address is as follows:
● Both MAC and STR instructions
Expanded Y-RAM address = Y-RAM address indicated by instruction
+ offset value (OFA11 to OFA00)
+ additional offset value (OFS05 to OFS00) × N
N is the offset addition count value, and its initial value is 0. The DSP program in I-RAM contains a JMP
instruction at the address with the value indicated by OFA00 to OFA11 in the OFSD register. N is
incremented by one each time DSP executes the JMP instruction.
Reset and offset clear (1 is written to bit 0 in the OFSC register) N.
● A MAC instruction has the same mode as the above, but an STR instruction has a different mode
If the mode is set so that data is stored in Y-RAM at the address specified in the store address counter when
Y-RAM expansion mode and STR mode are set. For details, see "Bit 4: STRM (STR mode setting)" in
"16.3.3 Offset Control Setting Register (OFSC)".
Expanded Y-RAM address = initial value of store address counter (STA11 to STA00) + N
N is the store address count value and is incremented by one each time execution of the instruction with YRAM specified by the STR instruction terminates.
Reset clears N to 0.
In this mode, the Y-RAM address in the STR instruction has no meaning.
Neither X-RAM nor I-RAM are affected by Y-RAM expansion mode.
384
CHAPTER 16 SUM-OF-PRODUCTS MACRO (SIMPLE DSP)
16.11
Example of Using Y-RAM Expansion Mode
This section presents an example of using the Y-RAM expansion mode.
■ Example of Calculation
The coefficients are K0, K1, K2, K3, K4, K5, K6, K7, and K8.
Variables include 340 data items each of R, G, and B.
The combinations of coefficients and variables are used for the following calculation:
• K0 . R + K1 . G + K2 . B = Y
• K3 . R + K4 . G + K5 . B = U
• K6 . R + K7 . G + K8 . B = V
340 data items Y, U, and V are calculated (Up to 340 data items of 16 bit length can be calculated because
the capacity of Y-RAM is 2,048 bytes).
■ Example of Transfer
Variables and coefficients are transferred to Y-RAM and X-RAM as follows:
DSP address
0
1
2
3
4
5
6
7
8
X-RAM
K0
K1
K2
K3
K4
K5
K6
K7
K8
DSP address
Y-RAM
0
1
2
3
4
5
6
7
8
9
A
Empty
Empty
Empty
r0
g0
b0
r1
g1
b1
r2
g2
3F9
3FA
3FB
3FC
3FD
3FE
3FF
b337
r338
g338
b338
r339
g339
b339
385
CHAPTER 16 SUM-OF-PRODUCTS MACRO (SIMPLE DSP)
■ Example of DSP Program
XA indicates data at address A in X-RAM, and YB indicates data at address B in Y-RAM.
I-RAM
address
Program contents
0
MAC instruction
MAC instruction
1
MAC instruction
X0 • Y3 → ACC
2
MAC instruction
ACC + X1 • Y4 → ACC
3
STR instruction
ACC + X2 • Y5 → ACCStores the result (addressing has no meaning).
4
MAC instruction
ACC → Y0
5
MAC instruction
ACC + X5 • Y4 → ACC
6
MAC instruction
ACC + X6 • Y5 → ACC
7
STR instruction
ACC → Y1 Stores the result (addressing has no meaning).
8
MAC instruction
X7 • Y3 → ACC
9
MAC instruction
ACC + X8 • Y4 → ACC
A
MAC instruction
ACC + X9 • Y5 → ACC
B
STR instruction
ACC → Y2 Stores the result (addressing has no meaning).
C
JMP instruction
Jumps to I-RAM address 0.
■ Example of Setting the DSP
● Setting the initial value of the store address counter
• Store the initial value of the store address counter to 000000000000B.
Write 0000H to the STRS register.
● Setting the initial value of the offset address
• Set the initial value of the offset address to 000000000000B.
Write 0000H to the OFAS register.
● Setting offset control
• Set the STR mode to the mode in which data is stored in Y-RAM at the address specified by the store
address counter.
• Set the Y-RAM expansion mode.
• Disable offset interrupts.
• Clear the offset interrupt flag.
• Clear the offset counter value.
Write 31H to the OFSC register.
386
CHAPTER 16 SUM-OF-PRODUCTS MACRO (SIMPLE DSP)
● Setting an additional offset value and offset addition count
• Set the additional offset value to 3.
- Because the DSP program uses three input data items in each program loop, three address offset
values may be increased at one time.
• Set the offset addition count to 340 times.
- Because 340 data items are processed, the offset count is supposed to be 340 - 1 times. However,
because calculation is stopped due to the count set in this register, set 340.
Write 0D54H to the OFSD register.
● Setting the offset specification
• Set the offset specification address to 0CH.
- Apply the offset in the JMP instruction at address 0CH of the DSP program in I-RAM.
Write 0CH to the OFSS register.
The Y-RAM has now been set. Next, execute the GoDSP command.
■ Example of DSP Operation
● First program loop
Y3-5 and X0-8 are used for calculation to obtain the results of y0, u0, and v0.
The results are stored at the address specified by the store address counter.
y0 is placed in Y0, u0 in Y1, and v0 in Y2.
JMP is executed, creating a loop. Offset 3 is set (first offset addition).
Y-RAM
Y0
Y1
Y2
Y3
Y4
Y5
Before calculation
Empty
Empty
Empty
r0
g0
b0
After calculation for 1st loop execution
Y0
Y1
Y2
Y3
Y4
Y5
y0
u0
v0
r0
g0
b0
● Second program loop
If Y3-5 and X0-8 are used for calculation, the Y-RAM address for the DSP program is Y3-5.
However, if the offset is added and Y6-8 is used for calculation, the results y1, u1, and v1 are obtained.
The results are stored at the address specified by the store address counter.
y1 is placed in Y3, u1 in Y4, and v1 in Y5.
JMP is executed, creating a loop. Offset 6 is set (second offset addition).
387
CHAPTER 16 SUM-OF-PRODUCTS MACRO (SIMPLE DSP)
Y-RAM
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
Before calculation
After calculation for 2nd loop execution
y0
u0
v0
r0
g0
b0
r1
g1
b1
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
y0
u0
v0
y1
u1
v1
r1
g1
b1
● Third program loop
Y3-5 and X0-8 are used for calculation to obtain the results y1, u1, and v1.
The Y-RAM address for the DSP program is Y3-5. However, if the offset is added and Y9-BH is used for
calculation, the results y2, u2, and v2 are obtained.
The results are stored at the address specified by the store address counter.
y2 is placed in Y6, u2 in Y7, and v2 in Y8.
JMP is executed, creating a loop. Offset 9 is set (third offset addition).
Y-RAM
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
Y9
YAH
YBH
388
Before calculation
y0
u0
v0
y1
u1
v1
r1
g1
b1
r2
g2
b2
After calculation for 3rd loop execution
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
Y9
YAH
YBH
y0
u0
v0
y1
u1
v1
y2
u2
v2
r2
g2
b2
CHAPTER 16 SUM-OF-PRODUCTS MACRO (SIMPLE DSP)
● 340th program loop after the DSP program repeats subsequent operations
Y3-5 and X0-8 are used for calculation to obtain the results y1, u1, and v1.
The Y-RAM address for the DSP program is Y3-5. However, if the offset is added and Y3FDH-3FFH is used
for calculation, the results y339, u339, and v339 are obtained.
The results are stored at the address specified by the store address counter.
y339 is placed in Y3FAH, u339 in Y3FBH, and v339 in Y3FCH.
If JMP is executed, the offset increases by 3 to become 400H. However, the offset count becomes 340,
which is the limit for offset addition count set in the OFSD register, and the DSP program is discontinued.
Y-RAM
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
Y9
YAH
YBH
Y3F7H
Y3F8H
Y3F9H
Y3FAH
Y3FBH
Y3FCH
Y3FDH
Y3FEH
Y3FFH
Before calculation
y0
u0
v0
y1
u1
v1
r1
g1
b1
r2
g2
b2
y338
u338
v338
r338
g338
b338
r339
g339
b339
After calculation for the 339th loop
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
Y9
YAH
YBH
y0
u0
v0
y1
u1
v1
y2
u2
v2
y2
u2
v2
Y3F7H
Y3F8H
Y3F9H
Y3FAH
Y3FBH
Y3FCH
Y3FDH
Y3FEH
Y3FFH
y338
u338
v338
y339
u339
v339
r339
g339
b339
389
CHAPTER 16 SUM-OF-PRODUCTS MACRO (SIMPLE DSP)
390
APPENDIX
These appendixes describe the I/O mapping, the
interrupt vectors, the pin status in the CPU state, the
notes on using little endian areas, and the instruction
list.
APPENDIX A I/O Mapping
APPENDIX B Interrupt Vectors
APPENDIX C Pin Status in Each CPU State
APPENDIX D Notes on Using Little Endian Area
APPENDIX E Instruction List
391
APPENDIX A I/O Mapping
APPENDIX A
I/O Mapping
Table A-1 shows address assignments to the registers of peripheral functions built in
MB91121.
■ Reading the I/O Mapping
Register
Address
Internal resource
+0
000000H
+1
+2
+3
PDR3
[R/W] PDR2
[R/W]
XXXXXXXX
XXXXXXXX
Read/write attribute
Register initial value after reset
Register name (first-column register at address 4n, second-column
register at address 4n + 1, and so on)
Leftmost register address (first-column register for MSB of data in word access)
Note:
The register bit values represent the initial values as follows:
- 1: Initial value "1"
- 0: Initial value "0"
- X: Initial value "X"
- -: No register physically at the position
392
Port data register
APPENDIX A I/O Mapping
■ I/O Mapping
Table A-1 I/O Mapping (1 / 6)
Register
Address
Internal resource
+0
000000H
-
000004H
-
000008H
PDRB [R/W]
XXXXXXXX
+1
PDR2 [R/W]
XXXXXXXX
PDR6 [R/W]
XXXXXXXX
PDRA [R/W]
-XXXXXX-
00000CH
-
-
000014H
PDRG [R/W]
--XXXXXX
PDRH [R/W]
XXXXXXXX
000018H
-
-
000020H
000024H
000028H
+3
-
-
-
-
-
PDR8 [R/W]
--X--XXX
Port data register
-
000010H
00001CH
+2
SSR0 [R/W, R]
SIDR0/SODR0[R/W]
00001-00
XXXXXXXX
SSR1 [R/W, R]
SIDR1/SODR1[R/W]
00001-00
XXXXXXXX
SSR2 [R/W, R]
SIDR2/SODR2[R/W]
00001-00
XXXXXXXX
TMRLR0 [W]
XXXXXXXX XXXXXXXX
PDRE [R/W]
----XXXX
PDRI [R/W]
XXXXXXXX
PDRF [R/W]
XXXXXXXX
-
SCR0 [R/W, R]
SMR0 [R/W]
00000100
00--0-00
SCR1 [R/W, R]
SMR1 [R/W]
00000100
00--0-00
SCR2 [R/W, R]
SMR2 [R/W]
00000100
00--0-00
TMR0 [R]
XXXXXXXX XXXXXXXX
TMCSR0 [R/W]
----0000 00000000
TMR1 [R]
XXXXXXXX XXXXXXXX
TMCSR1 [R/W]
----0000 00000000
00002CH
-
000030H
TMRLR1 [W]
XXXXXXXX XXXXXXXX
000034H
-
000038H
ADCR [R]
------XX XXXXXXXX
ADCS [R/W]
00000000 00000000
00003CH
TMRLR2 [W]
XXXXXXXX XXXXXXXX
TMR2 [R]
XXXXXXXX XXXXXXXX
TMCSR2 [R/W]
----0000 00000000
Reserved
UART0
UART1
UART2
Reload Timer 0
Reload Timer 1
A/D converter
(successive
approximation method)
Reload Timer 2
000040H
-
000044H
-
-
000048H
-
-
00004CH
-
-
Reserved
-
Software DMA
activation
000050H
STRG [R/W]
------00
000054H
000058H
-
-
-
-
00005CH
-
-
000060H
-
-
Reserved
Reserved
Reserved
393
APPENDIX A I/O Mapping
Table A-1 I/O Mapping (2 / 6)
Register
Address
Internal resource
+0
+1
+2
+3
000064H
-
-
Reserved
000068H
-
-
Reserved
00006CH
-
-
000070H
-
-
000074H
-
-
000080H
UTIM0/UTIMR0 [R/W]
00000000 00000000
UTIM1/UTIMR1 [R/W]
00000000 00000000
UTIM2/UTIMR2 [R/W]
00000000 00000000
000084H
-
-
000088H
-
-
00008CH
-
-
000090H
-
-
000078H
00007CH
000094H
000098H
-
0000A0H
-
0000A4H
-
0000A8H
-
0000ACH
-
0000B0H
-
0000B4H
-
0000B8H
-
0000BCH
-
0000C0H
-
0000C4H
-
0000C8H
-
0000CCH
-
-
0000D4H
DDRG [W]
00000000
DDRH [W]
0000----
0000D8H
394
U-TIMER 2
External interrupt/
NMI
Reserved
Reserved
DDRE [W]
00000000
DDRI [W]
------00
-
U-TIMER 1
Reserved
-
U-TIMER 0
Reserved
-
00009CH
0000D0H
Reserved
UTIMC0 [R/W]
0--00001
UTIMC1 [R/W]
0--00001
UTIMC2 [R/W]
0--00001
-
EIRR [R/W]
ENIR [R/W]
00000000
00000000
ELVR [R/W]
00000000 00000000
Reserved
DDRF [W]
00000000
-
Data direction
register
Reserved
APPENDIX A I/O Mapping
Table A-1 I/O Mapping (3 / 6)
Register
Address
Internal resource
+0
0000DCH
0000E0H
0000E4H
0000E8H
0000ECH
0000F0H
0000F4H
0000F8H
0000FCH
+1
+2
GCN1 [R/W]
00110010 00010000
PTMR0 [R]
11111111 11111111
PDUT0 [W]
XXXXXXXX XXXXXXXX
PTMR1 [R]
11111111 11111111
PDUT1 [W]
XXXXXXXX XXXXXXXX
PTMR2 [R]
11111111 11111111
PDUT2 [W]
XXXXXXXX XXXXXXXX
PTMR3 [R]
11111111 11111111
PDUT3 [W]
XXXXXXXX XXXXXXXX
000100H
to
0001FCH
+3
GCN2 [R/W]
00000000
PCSR0 [W]
XXXXXXXX XXXXXXXX
PCNH0 [R/W]
PCNL0 [R/W]
000000000000000
PCSR1 [W]
XXXXXXXX XXXXXXXX
PCNH1 [R/W]
PCNL1 [R/W]
000000000000000
PCSR2 [W]
XXXXXXXX XXXXXXXX
PCNH2 [R/W]
PCNL2 [R/W]
000000000000000
PCSR3 [W]
XXXXXXXX XXXXXXXX
PCNH3 [R/W]
PCNL3 [R/W]
000000000000000
-
-
Reserved
000208H
DPDP [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX X0000000
DACSR [R/W]
00000000 00000000 00000000 00000000
DATSR [R/W]
XXXXXXXX XXXX0000 XXXX0000 XXXX 000
00020CH
-
000200H
000204H
000210H
000214H
000218H
00021CH
000220H
000224H
OFAS [R/W]
XXXX0000 00000000
OFSC [R/W]
0000XXX0
OFSD [R/W]
00000000 00000000
DSP-LY [R/W]
XXXXXXXX XXXXXXXX
DSP-OT1 [R]
XXXXXXXX XXXXXXXX
DSP-OT3 [R]
XXXXXXXX XXXXXXXX
PWM
DMAC
Reserved
STRS [R/W]
XXXX0000 00000000
OFSS [R/W]
Y-BANKC [R/W, R]
00000000
0XX000000
DSP-PC [R/W]
DSP-CSR [R/W]
XXXXXXXX
00000000
DSP macro
DSP-OT0 [R]
XXXXXXXX XXXXXXXX
DSP-OT2 [R]
XXXXXXXX XXXXXXXX
-
395
APPENDIX A I/O Mapping
Table A-1 I/O Mapping (4 / 6)
Register
Address
Internal resource
+0
+1
+2
+3
000228H
to
000254H
-
000258H
-
00025CH
-
000260H
-
000264H
-
000268H
-
00026CH
-
000270H
-
000274H
-
000278H
to
0002FCH
-
Reserved
000300H
to
0003E3H
-
Reserved
0003E4H
ICHCR [R/W]
-------- -------- -------- --000000
0003E8H
-
0003ECH
-
0003F0H
0003F4H
0003F8H
0003FCH
396
BSD0 [W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
BSD1 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
BSDC [W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
BSRR [R]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
Reserved
Instruction Cache
Reserved
Bit search module
APPENDIX A I/O Mapping
Table A-1 I/O Mapping (5 / 6)
Register
Address
000400H
000404H
000408H
00040CH
000410H
000414H
000418H
00041CH
000420H
000424H
000428H
00042CH
000430H
Internal resource
+0
+1
+2
+3
ICR00 [R/W]
---11111
ICR04 [R/W]
---11111
ICR08 [R/W]
---11111
ICR12 [R/W]
---11111
ICR16 [R/W]
---11111
ICR20 [R/W]
---11111
ICR24 [R/W]
---11111
ICR28 [R/W]
---11111
ICR32 [R/W]
---11111
ICR36 [R/W]
---11111
ICR40 [R/W]
---11111
ICR44 [R/W]
---11111
DICR [R/W]
-------0
ICR01 [R/W]
---11111
ICR05 [R/W]
---11111
ICR09 [R/W]
---11111
ICR13 [R/W]
---11111
ICR17 [R/W]
---11111
ICR21 [R/W]
---11111
ICR25 [R/W]
---11111
ICR29 [R/W]
---11111
ICR33 [R/W]
---11111
ICR37 [R/W]
---11111
ICR41 [R/W]
---11111
ICR45 [R/W]
---11111
HRCL [R/W]
---11111
ICR02 [R/W]
---11111
ICR06 [R/W]
---11111
ICR10 [R/W]
---11111
ICR14 [R/W]
---11111
ICR18 [R/W]
---11111
ICR22 [R/W]
---11111
ICR26 [R/W]
---11111
ICR30 [R/W]
---11111
ICR34 [R/W]
---11111
ICR38 [R/W]
---11111
ICR42 [R/W]
---11111
ICR46 [R/W]
---11111
ICR03 [R/W]
---11111
ICR07 [R/W]
---11111
ICR11 [R/W]
---11111
ICR15 [R/W]
---11111
ICR19 [R/W]
---11111
ICR23 [R/W]
---11111
ICR27 [R/W]
---11111
ICR31 [R/W]
---11111
ICR35 [R/W]
---11111
ICR39 [R/W]
---11111
ICR43 [R/W]
---11111
ICR47 [R/W]
---11111
-
-
000434H
to
00047CH
000480H
000484H
000488H
RSRR/WTCR
[R/W]
1-XXX-00
GCR [R/W]
110011-1
PCTR [R/W]
00--0---
STCR [R/W]
000111--
PDRR [R/W]
----0000
CTBR [W]
XXXXXXXX
-
-
000604H
-
000608H
DDRB [W]
00000000
DDR2 [W]
00000000
DDR6 [W]
00000000
DDRA [W]
-000000-
Delayed interrupt
Clock controller
PLL control
-
000600H
Interrupt controller
Reserved
WPR [W]
XXXXXXXX
00048CH
to
0005FCH
Interrupt controller
Reserved
-
-
-
-
-
DDR8 [W]
--0--000
Data direction
register
397
APPENDIX A I/O Mapping
Table A-1 I/O Mapping (6 / 6)
Register
Address
Internal resource
+0
00060CH
000610H
000614H
000618H
00061CH
000620H
000624H
000628H
00062CH
+1
+2
ASR1 [W]
00000000 00000001
ASR2 [W]
00000000 00000010
ASR3 [W]
00000000 00000011
ASR4 [W]
00000000 00000100
ASR5 [W]
00000000 00000101
AMD0 [R/W]
AMD1 [R/W]
---00111
0--00000
AMD5 [R/W]
DSCR [W]
0--00000
00000000
EPCR0 [W]
----1100 -1111111
DMCR4 [R/W]
00000000 0000000-
000630H
to
0007F8H
+3
AMR1 [W]
00000000 00000000
AMR2 [W]
00000000 00000000
AMR3 [W]
00000000 00000000
AMR4 [W]
00000000 00000000
AMR5 [W]
00000000 00000000
AMD32 [R/W]
AMD4 [R/W]
00000000
0--00000
RFCR [R/W]
--XXXXXX 00---000
EPCR1 [W]
11111111
DMCR5 [R/W]
00000000 0000000-
External bus
interface
Reserved
LER [W]
-----000
MODR [W]
XXXXXXXX
0007FCH
-
002000H
to
002FFCH
Y-RAM (variable RAM) 4096 bytes (maximum)
00F000H
to
00F07CH
X-RAM (coefficient RAM) 128 bytes
00F100H
to
00F2FCH
I-RAM (instruction RAM) 512 bytes
Little endian
register Mode
register
DSP macro
Note:
RMW instructions (RMW: Read-modify-write)
AND
Rj,@Ri
OR
Rj,@Ri
EOR
Rj,@Ri
ANDH
Rj,@Ri
ORH
Rj,@Ri
EORH
Rj,@Ri
ANDB
Rj,@Ri
ORB
Rj,@Ri
EORB
Rj,@Ri
BANDL
#u4,@Ri
BORL
#u4,@Ri
BEORL
#u4,@Ri
BANDH
#u4,@Ri
BORH
#u4,@Ri
BEORH #u4,@Ri
Data in a reserved area or an area contain a hyphen (-) is undefined.
398
External bus
interface
APPENDIX B Interrupt Vectors
APPENDIX B
Interrupt Vectors
Table B-1 is an interrupt vector table.
The table lists the interrupt resources, interrupt vectors, and interrupt control registers
of MB91121.
■ Interrupt Vectors
Table B-1 Interrupt Vectors (1 / 3)
Interrupt No.
Offset
Interrupt vector address to
default TBR *2
Dec
Hex
Interrupt
level *1
Reset
0
00
-
3FCH
000FFFFCH
Reserved for system
1
01
-
3F8H
000FFFF8H
Reserved for system
2
02
-
3F4H
000FFFF4H
Reserved for system
3
03
-
3F0H
000FFFF0H
Reserved for system
4
04
-
3ECH
000FFFECH
Reserved for system
5
05
-
3E8H
000FFFE8H
Reserved for system
6
06
-
3E4H
000FFFE4H
Reserved for system
7
07
-
3E0H
000FFFE0H
Reserved for system
8
08
-
3DCH
000FFFDCH
Reserved for system
9
09
-
3D8H
000FFFD8H
Reserved for system
10
0A
-
3D4H
000FFFD4H
Reserved for system
11
0B
-
3D0H
000FFFD0H
Reserved for system
12
0C
-
3CCH
000FFFCCH
Reserved for system
13
0D
-
3C8H
000FFFC8H
Undefined instruction exception
14
0E
-
3C4H
000FFFC4H
NMI request
15
0F
Always FH
3C0H
000FFFC0H
External interrupt 0
16
10
ICR00
3BCH
000FFFBCH
External interrupt 1
17
11
ICR01
3B8H
000FFFB8H
External interrupt 2
18
12
ICR02
3B4H
000FFFB4H
External interrupt 3
19
13
ICR03
3B0H
000FFFB0H
UART 0 reception complete
20
14
ICR04
3ACH
000FFFACH
UART 1 reception complete
21
15
ICR05
3A8H
000FFFA8H
UART 2 reception complete
22
16
ICR06
3A4H
000FFFA4H
Interrupt resource
399
APPENDIX B Interrupt Vectors
Table B-1 Interrupt Vectors (2 / 3)
Interrupt No.
Offset
Interrupt vector address to
default TBR *2
Dec
Hex
Interrupt
level *1
UART 0 transmission complete
23
17
ICR07
3A0H
000FFFA0H
UART 1 transmission complete
24
18
ICR08
39CH
000FFF9CH
UART 2 transmission complete
25
19
ICR09
398H
000FFF98H
DMAC 0 (end or error)
26
1A
ICR10
394H
000FFF94H
DMAC 1 (end or error)
27
1B
ICR11
390H
000FFF90H
DMAC 2 (end or error)
28
1C
ICR12
38CH
000FFF8CH
DMAC 3 (end or error)
29
1D
ICR13
388H
000FFF88H
DMAC 4 (end or error)
30
1E
ICR14
384H
000FFF84H
DMAC 5 (end or error)
31
1F
ICR15
380H
000FFF80H
DMAC 6 (end or error)
32
20
ICR16
37CH
000FFF7CH
DMAC 7 (end or error)
33
21
ICR17
378H
000FFF78H
A/D (successive approximation)
34
22
ICR18
374H
000FFF74H
Reload timer 0
35
23
ICR19
370H
000FFF70H
Reload timer 1
36
24
ICR20
36CH
000FFF6CH
Reload timer 2
37
25
ICR21
368H
000FFF68H
PWM 0
38
26
ICR22
364H
000FFF64H
PWM 1
39
27
ICR23
360H
000FFF60H
PWM 2
40
28
ICR24
35CH
000FFF5CH
PWM 3
41
29
ICR25
358H
000FFF58H
U-TIMER 0
42
2A
ICR26
354H
000FFF54H
U-TIMER 1
43
2B
ICR27
350H
000FFF50H
U-TIMER 2
44
2C
ICR28
34CH
000FFF4CH
External interrupt 4
45
2D
ICR29
348H
000FFF48H
External interrupt 5
46
2E
ICR30
344H
000FFF44H
External interrupt 6
47
2F
ICR31
340H
000FFF40H
External interrupt 7
48
30
ICR32
33CH
000FFF3CH
DSP macro software interrupt
49
31
ICR33
338H
000FFF38H
DSP macro offset interrupt
50
32
ICR34
334H
000FFF34H
Reserved for system
51
33
ICR35
330H
000FFF30H
Reserved for system
52
34
ICR36
32CH
000FFF2CH
Interrupt resource
400
APPENDIX B Interrupt Vectors
Table B-1 Interrupt Vectors (3 / 3)
Interrupt No.
Offset
Interrupt vector address to
default TBR *2
Dec
Hex
Interrupt
level *1
Reserved for system
53
35
ICR37
328H
000FFF28H
Reserved for system
54
36
ICR38
324H
000FFF24H
Reserved for system
55
37
ICR39
320H
000FFF20H
Reserved for system
56
38
ICR40
31CH
000FFF1CH
Reserved for system
57
39
ICR41
318H
000FFF18H
Reserved for system
58
3A
ICR42
314H
000FFF14H
Reserved for system
59
3B
ICR43
310H
000FFF10H
Reserved for system
60
3C
ICR44
30CH
000FFF0CH
Reserved for system
61
3D
ICR45
308H
000FFF08H
Reserved for system
62
3E
ICR46
304H
000FFF04H
Delayed interrupt resource
63
3F
ICR47
300H
000FFF00H
Reserved for system
(used by REALOS) *3
64
40
-
2FCH
000FFEFCH
Reserved for system
(used by REALOS) *3
65
41
-
2F8H
000FFEF8H
66 to
255
42 to
FF
-
2F4H
to
000H
000FFEF4H
to
000FFD00H
Interrupt resource
For INT instruction
*1: ICR is an internal register of the interrupt controller to set an interrupt level for each interrupt request.
ICR is prepared for each interrupt request.
*2: TBR is a register indicating the first address of the vector table for EIT.
The TBR value and an offset value preset for each EIT resource are added to the address to determine the vector address.
*3: When using REALOS/FR, use interrupts of 0 × 40 and 0 × 41 for system codes.
Reference:
The 1K-byte area from the TBR address is the EIT vector area. The vector size is 4 bytes and the
relationship between vector number and vector address can be expressed as follows:
vctadr = TBR + vctofs
= TBR + (3FCH - 4 × vct)
vctadr: Vector address
vctofs: Vector offset
vct : Vector number
401
APPENDIX C Pin Status in Each CPU State
APPENDIX C
Pin Status in Each CPU State
Table C-1 explains the terms used in the pin status list and Table C-2 to Table C-4
explain the pin status in each CPU state.
■ Terms Used in the Pin Status List
The terms related to pin status have the following meanings:
Table C-1 Terms Used in the Pin Status List
Term
402
Meaning
Input possible
The input function is ready for use.
Input 0 fixed
External input is blocked at the input gate immediately after the pin and 0 is
conveyed inside.
Output Hi-Z
The pin drive transistor is disabled and the pin is set to a high impedance.
Output hold
The output status immediately before this mode is held.
If an output-set peripheral is in operation, signals are output according to the
internal peripheral. If a pin is used as an output port, its output is held.
Previous status
The output status immediately before this mode is held. If the pin is for input,
input is still acceptable.
APPENDIX C Pin Status in Each CPU State
■ Pin Status in Each CPU State
Table C-2 Pin Status (16-bit External Bus, 2CAS1WR Mode) (1 / 2)
Stop
Pin name
Function
Sleep
HIZX=0
P20 to P27
D16 to D23
-
D24 to D31
-
HIZX=1
Bus release
(BGRNTX)
Reset
Output held or
Hi-Z
Output held or
Hi-Z
A00 to D15
Output held
(address output)
Output held
(address output)
P60 to P67
A16 to A23
P: Previous
status
F: Address
output
P: Previous status
F: Address output
-
A24
Previous status
Previous status
P80
RDY
P: Previous
status
F: RDY input
P, F: Previous
status
P: Previous
status
F: RDY input
P81
BGRNTX
P: Previous
status
F: "H" output
P, F: Previous
status
"L" output
P82
BRQ
P: Previous
status
F: BRQ input
P, F: Previous
status
Previous status
Previous status
"H" output
Output Hi-Z
FFH output
BRQ input
Output Hi-Z/input
always 0
-
RDX
-
WR0X
P85
WR1X
P: Previous
status
F: "H" output
P, F: Previous
status
"H" output *2
-
CS0X
Previous status
Previous status
"L" output
PA1 to PA5
CS1X to
CS5X
P: Previous
status
F: CS output
P, F: Previous
status
"H" output
PA6
CLK
P: Previous
status
F: CLK output
P, F: Previous
status
PB0
RAS0
PB1
CS0L
PB2
CS0H
PB3
DW0X
PB4
RAS1
P: Previous
P: Previous status
status
F: Previous value F: Previous value
Operates when
In refresh mode*1
DRAM pin is set
CLK output
CLK output
P: Previous status
Output Hi-Z/
F: Previous value
input from all
Operates when
pins possible
DRAM pin is set
403
APPENDIX C Pin Status in Each CPU State
Table C-2 Pin Status (16-bit External Bus, 2CAS1WR Mode) (2 / 2)
Stop
Pin name
Function
Sleep
HIZX=0
PB5
CS1L
PB6
CS1H
PB7
DW1X
AN0 to
AN7
AN0 to AN7
PE0
SC2
PE1
DREQ0
PE2
DACK0
PE3
EOP0
PE4
DREQ1
PE5
DACK1
PE6
EOP1
PE7
DREQ2
PF0
SI0
PF1
SO0
PF2
SC0
PF3
SI1
PF4
SO1
PF5
SC1
PF6
SI2
PF7
SO2
PG0 to PG3 INT0 to INT3
INT4 to INT7
PG4 to PG7
PH4 to PH7
HIZX=1
P: Previous
P: Previous status
status
F: Previous value F: Previous value
Operates when
In refresh mode*1
DRAM pin is set
Bus release
(BGRNTX)
Reset
P: Previous status
F: Previous value
Operates when
DRAM pin is set
Output Hi-Z/input
always 0
Previous status
Output Hi-Z/
input from all
pins possible
Previous status
Previous status
Input possible
Input possible
Previous status
Output Hi-Z/input
always 0
TRG0 to
TRG3
OCPA0 to
OCPA3
PI0
DACK2
PI1
EOP2,ATGX
P : Specified as general-purpose port, F: Selected as the specified function
*1: Self-refresh status is entered when the self-refresh function is activated. The previous value is held when the self-refresh function is
canceled.
*2: There is the period when the Hi-Z state is entered immediately after reset.
404
APPENDIX C Pin Status in Each CPU State
Table C-3 Pin Status (16-bit External Bus, 1CAS2WR Mode) (1 / 2)
Stop
Pin name
Function
Sleep
HIZX=0
P20 to P27
D16 to D23
-
D24 to D31
-
HIZX=1
Bus release
(BGRNTX)
Reset
Output held or
Hi-Z
Output held or
Hi-Z
A00 to A15
Output held
(address output)
Output held
(address output)
P60 to P67
A16 to A23
P: Previous
status
F: Address
output
P: Previous status
F: Address output
-
A24
Previous status
Previous status
P80
RDY
P: Previous
status
F: RDY input
P, F: Previous
status
P: Previous
status
F: RDY input
P81
BGRNTX
P: Previous
status
F: "H" output
P, F: Previous
status
"L" output
P82
BRQ
P: Previous
status
F: BRQ input
P, F: Previous
status
Previous status
Previous status
"H" output
Output Hi-Z
FFH output
BRQ input
Output Hi-Z/input
always 0
-
RDX
-
WR0X
P85
WR1X
P: Previous
status
F: "H" output
P, F: Previous
status
"H" output*2
-
CS0X
Previous status
Previous status
"L" output
PA1 to PA5
CS1X to
CS5X
P: Previous
status
F: CS output
P, F: Previous
status
PA6
CLK
P: Previous
status
F: CLK output
P, F: Previous
status
PB0
RAS0
PB1
CS0L
PB2
CS0H
PB3
DW0X
PB4
RAS1
P: Previous
P: Previous status
status
F: Previous value F: Previous value
Operates when
In refresh mode*1
DRAM pin is set
CLK output
CLK output
P: Previous status
Output Hi-Z/
F: Previous value
input from all
Operates when
pins possible
DRAM pin is set
405
APPENDIX C Pin Status in Each CPU State
Table C-3 Pin Status (16-bit External Bus, 1CAS2WR Mode) (2 / 2)
Stop
Pin name
Function
Sleep
HIZX=0
PB5
CS1L
PB6
CS1H
PB7
DW1X
AN0 to
AN7
AN0 to AN7
PE0
SC2
PE1
DREQ0
PE2
DACK0
PE3
EOP0
PE4
DREQ1
PE5
DACK1
PE6
EOP1
PE7
DREQ2
PF0
SI0
PF1
SO0
PF2
SC0
PF3
SI1
PF4
SO1
PF5
SC1
PF6
SI2
PF7
SO2
PG0 to PG3 INT0 to INT3
INT4 to INT7
PG4 to PG7
PH4 to PH7
HIZX=1
P: Previous
P: Previous status
status
F: Previous value F: Previous value
Operates when
In refresh mode*1
DRAM pin is set
Bus release
(BGRNTX)
Reset
P: Previous status
F: Previous value
Operates when
DRAM pin is set
Output Hi-Z/input
always 0
Previous status
Output Hi-Z/
input from all
pins possible
Previous status
Previous status
Input possible
Input possible
Previous status
Output Hi-Z/input
always 0
TRG0 to
TRG3
OCPA0 to
OCPA3
PI0
DACK2
PI1
EOP2,ATGX
P : Specified as general-purpose port, F: Selected as the specified function
*1: Self-refresh status is entered when the self-refresh function is activated. The previous value is held when the self-refresh function is
canceled.
*2: There is a period when the Hi-Z state is entered immediately after reset.
406
APPENDIX C Pin Status in Each CPU State
Table C-4 Pin Status (8-bit External Bus) (1 / 2)
Stop
Pin name
Function
Sleep
HIZX=0
P20 to P27
Port
-
D24 to D31
-
A00 to A15
P60 to P67
A16 to A23
-
A24
P80
RDY
P81
BGRNTX
P82
BRQ
P85
-
RDX
WR0X
Port
CS0X
PA1 to PA5
CS1X to
CS5X
PA6
CLK
PB0
RAS0
PB1
CS0L
PB2
CS0H
Previous status
Output held or
Hi-Z
Output held
(address output)
P: Previous
status
F: Address
output
Previous status
P: Previous
status
F: RDY input
P: Previous
status
F: "H" output
P: Previous
status
F: BRQ input
Previous status
Output held or
Hi-Z
Output held
(address output)
Previous status
Previous status
Previous status
Previous status
Previous status
P: Previous
status
F: CS output
P: Previous
status
F: CLK output
Previous status
Previous status
P: Previous
status
F: Previous
value*2
P: Previous status
F: Previous
value*2
In refresh mode*1
HIZX=1
Bus open
(BGRNTX)
Reset
Previous status
Output Hi-Z
FFH output
P: Previous status
F: Address output
P, F: Previous
status
P: Previous
status
F: RDY input
P, F: Previous
status
"L" output
P, F: Previous
status
Output Hi-Z/input BRQ input
always 0
"H" output
Previous status
"L" output
P, F: Previous
status
P, F: Previous
status
P: Previous
P: Previous status
status
F: Previous value
F: Previous value
"H" output
CLK output
CLK output
P: Previous status
F: Previous
Output Hi-Z/
value*2
input from all
pins possible
Previous status
407
APPENDIX C Pin Status in Each CPU State
Table C-4 Pin Status (8-bit External Bus) (2 / 2)
Stop
Pin name
Function
Sleep
HIZX=0
PB3
PB4
DW0X
RAS1
PB5
CS1L
PB6
CS1H
PB7
DW1X
P: Previous
status
F: Previous
value*2
HIZX=1
P: Previous status
F: Previous
value*2
In refresh mode*1
Reset
P: Previous status
F: Previous
value*2
P: Previous
P: Previous status
status
F: Previous value
F: Previous value
P: Previous status
P: Previous
F: Previous
status
F: Previous
value*2
*2
value
In refresh mode*1
AN0 to
AN0 to AN7
AN7
PE0
SC2
PE1
DREQ0
PE2
DACK0
PE3
EOP0
PE4
DREQ1
PE5
DACK1
PE6
EOP1
PE7
DREQ2
PF0
SI0
PF1
SO0
PF2
SC0
Previous status
PF3
SI1
PF4
SO1
PF5
SC1
PF6
SI2
PF7
SO2
PG0 to PG3 INT0 to INT3
INT4 to INT7
PG4 to PG7
TRG0 to
TRG3
OCPA0 to
PH4 to PH7
OCPA3
PI0
DACK2
PI1
EOP2,ATGX
Bus open
(BGRNTX)
Previous status
Output Hi-Z/input
always 0
Output Hi-Z/
input from all
pins possible
Previous status
Previous status
Input possible
Input possible
P : Specified as general-purpose port, F: Selected as the specified function
*1: Self-refresh status is entered when the self-refresh function is activated. The previous value is held when the self-refresh function is canceled.
*2: Operates when the DRAM pin is set.
408
APPENDIX D Notes on Using Little Endian Area
APPENDIX D
Notes on Using Little Endian Area
This appendix gives notes on using a little endian area about the following items:
D.1 Compiler (fcc911)
D.2 Assembler (fasm911)
D.3 Linker (flnk911)
D.4 Debugger (sim911, eml911, mon911)
409
APPENDIX D Notes on Using Little Endian Area
D.1
Compiler (fcc911)
When using the C language for programming, avoid the following on a little endian to
ensure normal performance:
• Placing initial valued variables
• Assigning structures
• Using character array operation functions on other than character-type arrays
• Specifying the -K lib option when using character string operation functions
• Using double or long-double variables
• Placing a stack in a little endian area
■ Placing Initial Valued Variables
Initial valued variables cannot be placed in a little endian area.
A compiler does not have a function to generate initial values for a little endian.
A little endian area accepts variables but not initial values.
Set initial values at the beginning of a program.
Example: Setting an initial value to variable little_data in a little endian area
extern int little_data;
void little_init(void) {
little_data = Initial value;
}
void main(void) {
little_init();
...
}
■ Structure Assignment
When assigning structures each other, a compiler selects an optimum transfer method and transfers data by
bytes, half-words, or words. If a structure is assigned from a structural variable in an ordinary area to
another in a little endian area or vice versa, the correct result cannot be obtained.
Example: Assigning a structural variable to structural variable little_st in a little endian area
struct tag { char c; int i; }normal_st;
extern struct tag little_st;
#define STRMOVE(DEST,SRC) DEST.c=SRC.c;DEST.i=SRC.i;
void main(void) {
STRMOVE(little_st,normal_st);
}
Since the structural member placement differs between compilers, the structure may have a different
member placement from a structure compiled by another compiler.
In this case, even the above method cannot produce correct results.
If the member placement of the structure does not match, do not place a structural variable in a little endian
area.
410
APPENDIX D Notes on Using Little Endian Area
■ Using Character Array Operation Functions on Other than Character-Type Arrays
The character string operation functions prepared as a standard library does processing in bytes. Therefore,
correct results cannot be obtained if these functions are used on a little endian area of a type other than
"char", "unsigned char", or "signed char".
Avoid the following processing:
Example of problem: Word data transfer using memcpy
int big = 0x01020304;
/* Big endian area
*/
extern int little;
/* Little endian area
*/
memcpy(&little,&big,4);
/* Transfer by memcpy
*/
The above processing ends in the following result that is an error as a word data transfer result.
(Big endian area)
01
02
(Little endian area)
03
04
→ memcpy →
(Correct result)
01
02
03
04
04
03
02
01
■ Option Specifying the -K Lib Option when Using Character String Operation Functions
If the -K lib option is specified, a compiler applies inline development to several character string operation
functions. For optimum processing, the unit of processing may be changed to half-word or word.
Therefore, processing cannot be executed correctly on a little endian area.
Do not specify the -K lib option when using character string operation functions for processing on a little
endian area.
Do not use specify the -4 option containing the -K lib option or the -K speed option.
■ Using Double or Long-double Variables
Access to a double or long-double variable is made on the upper or lower word. Therefore, access to a
double or long-double variable in a little endian area does not produce the correct results.
Although variables of the same type can be assigned to each other in a little endian area, optimization may
substitute these variable assignments with constant assignments.
Do not use double or long-double variables in a little endian area.
Example of problem: Double-type data transfer
double big = 1.0;
/* Big endian area
*/
extern int little;
/* Little endian area
*/
little = big;
/* Double-type data transfer
*/
The above execution ends in the following result that is an error as a double-type data transfer result.
(Big endian area)
3f
f0
00
00
00
00
(Little endian area)
00
00
(Correct result)
→
00
00
f0
3f
00
00
00
00
00
00
00
00
00
00
f0
3f
■ Placing a Stack in a Little Endian Area
If a stack is placed in a little endian area partially or totally, normal performance cannot be guaranteed.
411
APPENDIX D Notes on Using Little Endian Area
D.2
Assembler (fasm911)
When using the FR family assembler, note the following on a little endian area.
• Section
• Data access
■ Section
The main purpose of a little endian area is to exchange data with a little-endian CPU.
Therefore, define a data section in a little endian area with no initial value.
If a data section with initial code or stack values are specified in a little endian area, the program may not
operate normally in MB91121.
[Example]
/* Correct section definition in a little endian area */
.SECTION Little_Area, DATA, ALIGN=4
Little_Word:
.RES.W 1
Little_Half:
.RES.H 1
Little_Byte:
.RES.B 1
■ Data Access
If data in a little endian area is accessed, the data value can be coded without minding the endian. To data
in a little endian area, however, make a data-size access.
[Example]
LDI
#0x01020304, r0
LDI
#Little_Word, r1
LDI
#0x0102, r2
LDI
#Little_Half, r3
LDI
#0x01, r4
LDI
#Little_Byte, r5
/* Use ST (or LD) instruction for access to 32-bit data */
ST
r0, @r1
/* Use STH (or LDH) instruction for access to 16-bit data */
STH
r2, @r3
/* Use STB (or LDB) instruction for access to 8-bit data */
STB
r4, @r5
Access of not the data size may not produce the correct result in MB91121. If two continuous 16-bit data
items are accessed using a 32-bit access instruction, the data value cannot be guaranteed.
412
APPENDIX D Notes on Using Little Endian Area
D.3
Linker (flnk911)
In programming with a little endian area, keep the following section placement notes at
linking:
• Restriction on section type
• No error detection
■ Restriction on Section Type
Only data sections with no initial values can be placed in a little endian area.
If data stack, or code sections with initial values are placed in a little endian area, normal program
performance cannot be guaranteed because the linker processes address solutions and other operations in
the big endian format.
■ No Error Detection
Even if the above restriction is not followed, no error message is issued because the linker does not
recognize a little endian area.
When using the linker, check the contents of sections in a little endian area well.
413
APPENDIX D Notes on Using Little Endian Area
D.4
Debugger (sim911, eml911, mon911)
When using the simulator debugger and emulator/monitor debugger, keep the notes
given below.
■ Simulator Debugger
The simulator debugger does not support any memory space specification command applicable to a little
endian area.
Therefore, this debugger assumes memory operation commands and their execution in a big endian area.
■ Emulator/Monitor Debugger
The emulator/monitor debugger does not handle the following access commands to a little endian area as
correct values:
● Set memory/show memory/enter/examine/set watch command
If floating-point (single or double) data is used, specified values cannot be set or displayed.
● Search memory command
Half-word or word data is not retrieved with specified values.
● Line/reverse assembling (including source window reverse assembling display)
Instruction codes cannot be set or displayed normally. (Do not place instruction codes in a little endian
area.)
● Call/show command
A stack area does not operate normally in a little endian area. (Do not place a stack area in a little endian
area.)
414
APPENDIX E Instruction List
APPENDIX E
Instruction List
This appendix describes the instruction list.
E.1 Instruction List
E.2 FR family Instruction List
415
APPENDIX E Instruction List
E.1
Instruction List
The FR family instructions are listed here. To assist in an understanding of the
instruction list, the following items are explained first:
• Reading the instruction list
• Addressing mode symbols
• Instruction formats
■ Reading the Instruction List
Mnemonic
ADD
*ADD
Rj,
#5,
,
,
1)
2)
Rj
Rj
Type
OP
CYCLE
NZVC
Operation
A
C
,
,
AG
A4
,
,
1
1
,
,
CCCC
CCCC
,
,
Ri + Rj --> Rj
Ri + s5 --> Ri
,
,
3)
4)
5)
6)
7)
Remarks
1. Instruction name
• An asterisk (*) indicates an extended instruction not in the CPU specifications but extended or added
in the assembler.
2. Addressing mode that can be specified in an operand
• See "Addressing mode symbols" for the meanings of the symbols.
3. Instruction format
4. Instruction code in a hexadecimal format
5. Number of machine cycles
• a: Memory access cycle that may be extended by the Ready function
• b: Memory access cycle that may be extended by the Ready function:
If a register is referenced for LD operation by the instruction immediately after, the processing is
interlocked and the number of execution cycles increments one.
• c: If the instruction immediately after is a read or write instruction to R15, SSP, or USP or a
instruction of format A, the processing is interlocked and the number of execution cycles
increases to 2.
• d: If the instruction immediately after references MDH or MDL, the processing is interlocked and the
number of execution cycles increases to 2.
• The minimum number of cycles is 1 for a, b, c, and d.
416
APPENDIX E Instruction List
6. Flag change
Flag change
Meaning of symbol
C: Change
N: Negative flag
-: No change
Z: Zero flag
0: Clear
V: Over flag
1: Set
C: Carry flag
7. Operation
417
APPENDIX E Instruction List
■ Addressing Mode Symbols
Table E.1-1 Meanings of the Addressing Mode Symbols (1 / 2)
Symbol
418
Meaning
Ri
Register direct (R0 to R15,AC,FP,SP)
Rj
Register direct (R0 to R15,AC,FP,SP)
R13
Register direct (R13,AC)
Ps
Register direct (Program status register)
Rs
Register direct (TBR,RP,SSP,USP,MDH,MDL)
CRi
Register direct (CR0 to CR15)
CRj
Register direct (CR0 to CR15)
#i8
Unsigned 8-bit immediate value (-128 to 255)
Note: -128 to -1 is handled as 128 to 255.
#i20
Unsigned 20-bit immediate value (-0X8000 to 0XFFFFF)
Note: -0X7FFFF to -1 is handled as 0X7FFFF to 0XFFFFF.
#i32
Unsigned 32-bit immediate value (-0X80000000 to 0XFFFFFFFF)
Note: -0X80000000 to -1 is handled as 0X80000000 to 0XFFFFFFFF.
#s5
Unsigned 5-bit immediate value (-16 to 15)
#s10
Unsigned 10-bit immediate value (-512 to 508, multiple of 4 only)
#u4
Unsigned 4-bit immediate value (0 to 15)
#u5
Unsigned 5-bit immediate value (0 to 31)
#u8
Unsigned 8-bit immediate value (0 to 255)
#u10
Unsigned 10-bit immediate value (0 to 1020, multiple of 4 only)
@dir8
Unsigned 8-bit direct address (0 to 0XFF)
@dir9
Unsigned 9-bit direct address (0 to 0X1FE, multiple of 2 only)
@dir10
Unsigned 10-bit direct address (0 to 0X3FC, multiple of 4 only)
label9
Signed 9-bit branch address (-0X100 to 0XFC, multiple of 2 only)
label12
Signed 12-bit branch address (-0X800 to 0X7FC, multiple of 2 only)
label20
Signed 20-bit branch address (-0X80000 to 0X7FFFF)
label32
Signed 32-bit branch address (-0X80000000 to 0X7FFFFFFF)
@Ri
Register indirect (R0 to R15, AC, FP, and SP)
@Rj
Register indirect (R0 to R15, AC, FP, and SP)
@(R13,Rj)
Register indirect (Rj: R0 to R15, AC, FP, and SP)
@(R14,disp10)
Register relative indirect (disp10: -0X200 to 0X1FC, multiple of 4 only)
@(R14,disp9)
Register relative indirect (disp9: -0X100 to 0XFE, multiple of 2 only)
APPENDIX E Instruction List
Table E.1-1 Meanings of the Addressing Mode Symbols (2 / 2)
Symbol
Meaning
@(R14,disp8)
Register relative indirect (disp8: -0X80 to 0X7F)
@(R15,udisp6)
Register relative indirect (udisp6: 0 to 60, multiple of 4 only)
@Ri+
Post-increment register indirect (R0 to R15, AC, FP, and SP)
@R13+
Post-increment register indirect (R13, AC)
@SP+
Stack pop
@-SP
Stack push
(reglist)
Register list
419
APPENDIX E Instruction List
■ Instruction Formats
Table E.1-2 Instruction Format
Type
A
Instruction format
MSB
LSB
16bit
OP
Rj
Ri
8
4
4
B
OP
i8/o8
Ri
4
8
4
C
C’
OP
u4/m4
Ri
8
4
4
ADD, ADDN, CMP, LSL, LSR, and ASR instructions only
OP
s5/u5
Ri
7
5
4
D
OP
u8/rel8/dir/
reglist
8
8
E
OP
OP
SUB-OP
SUB-OP
Ri
84
8
4
4
F
420
OP
rel11
5
11
APPENDIX E Instruction List
E.2
FR family Instruction List
The FR family instructions are listed in the following order.
■ FR Family Instruction List
Table E.2-1 Addition and Subtraction Instructions
Table E.2-2 Compare Operation Instructions
Table E.2-3 Logical Operation Instructions
Table E.2-4 Bit Operation Instructions
Table E.2-5 Multiplication and Division Instructions
Table E.2-6 Shift Instructions
Table E.2-7 Immediate Value Set and 16/32-bit Immediate Value Transfer Instructions
Table E.2-8 Memory Load Instructions
Table E.2-9 Memory Store Instructions
Table E.2-10 Inter-register Transfer Instructions
Table E.2-11 Ordinary Branch (No Delay) Instructions
Table E.2-12 Delayed Branch Instructions
Table E.2-13 Other Instructions
Table E.2-14 20-bit Ordinary Branch Macroinstructions
Table E.2-15 20-bit Delayed Branch Macroinstructions
Table E.2-16 32-bit Ordinary Branch Macroinstructions
Table E.2-17 32-bit Delayed Branch Macroinstructions
Table E.2-18 Direct Addressing Instructions
Table E.2-19 Resource Instructions
Table E.2-20 Coprocessor Control Instructions
421
APPENDIX E Instruction List
■ Addition and Subtraction Instructions
Table E.2-1 Addition and Subtraction Instructions
Mnemonic
Type
OP
CYCLE
NZVC
Operation
Remarks
ADD
*ADD
Rj, Ri
#s5, Ri
A
C’
A6
A4
1
1
CCCC
CCCC
Ri + Rj → Ri
Ri + s5 → Ri
ADD
ADD2
#u4, Ri
#u4, Ri
C
C
A4
A5
1
1
CCCC
CCCC
Ri + extu(i4) → Ri
Ri + extu(i4) → Ri
For the assembler, the
upper 1 bit is a sign.
Zero extension
Negative extension
ADDC
Rj, Ri
A
A7
1
CCCC
Ri + Rj + c → Ri
Addition with carry
ADDN
*ADDN
Rj, Ri
#s5, Ri
A
C'
A2
A0
1
1
-------
Ri + Rj → Ri
Ri + s5 → Ri
ADDN
ADDN2
#u4, Ri
#u4, Ri
C
C
A0
A1
1
1
-------
Ri + extu(i4) → Ri
Ri + extu(i4) → Ri
For the assembler, the
upper 1 bit is a sign.
Zero extension
Negative extension
SUB
Rj, Ri
A
AC
1
CCCC
Ri - Rj → Ri
SUBC
Rj, Ri
A
AD
1
CCCC
Ri - Rj - c → Ri
SUBN
Rj, Ri
A
AE
1
----
NZVC
Deduction with carry
Ri - Rj → Ri
■ Compare Operation Instructions
Table E.2-2 Compare Operation Instructions
Mnemonic
Type
OP
CYCLE
Operation
CMP
*CMP
Rj, Ri
#s5, Ri
A
C'
AA
A8
1
1
CCCC
CCCC
Ri - Rj
Ri - s5
CMP
CMP2
#u4, Ri
#u4, Ri
C
C
A8
A9
1
1
CCCC
CCCC
Ri - extu(i4)
Ri - extu(i4)
422
Remarks
For the assembler, the
upper 1 bit is a sign.
Zero extension
Negative extension
APPENDIX E Instruction List
■ Logical Operation Instructions
Table E.2-3 Logical Operation Instructions
Mnemonic
Type
OP
CYCLE
NZVC
Operation
RMW
Remarks
AND
AND
ANDH
ANDB
Rj, Ri
Rj, @Ri
Rj, @Ri
Rj, @Ri
A
A
A
A
82
84
85
86
1
1+2a
1+2a
1+2a
CC-CC-CC-CC--
Ri &= Rj
(Ri) &= Rj
(Ri) &= Rj
(Ri) &= Rj
❍
❍
❍
Word
Word
Half-word
Byte
OR
OR
ORH
ORB
Rj, Ri
Rj, @Ri
Rj, @Ri
Rj, @Ri
A
A
A
A
92
94
95
96
1
1+2a
1+2a
1+2a
CC-CC-CC-CC--
Ri |= Rj
(Ri)|= Rj
(Ri)|= Rj
(Ri)|= Rj
❍
❍
❍
Word
Word
Half-word
Byte
EOR
EOR
EORH
EORB
Rj, Ri
Rj, @Ri
Rj, @Ri
Rj, @Ri
A
A
A
A
9A
9C
9D
9E
1
1+2a
1+2a
1+2a
CC-CC-CC-CC--
Ri ^= Rj
(Ri)^= Rj
(Ri)^= Rj
(Ri)^= Rj
❍
❍
❍
Word
Word
Half-word
Byte
■ Bit Operation Instructions
Table E.2-4 Bit Operation Instructions
Mnemonic
Type
OP
CYCLE
NZVC
Operation
RMW
Remarks
BANDL
BANDH
*BAND
#u4, @Ri
#u4, @Ri
#u8, @Ri *1
C
C
80
81
1+2a
1+2a
----------
(Ri)&=(0xF0+u4)
(Ri)&=((u4<<4)+0x0F)
(Ri)&=u8
❍
❍
-
Lower 4-bit operation
Upper 4-bit operation
BORL
BORH
*BOR
#u4, @Ri
#u4, @Ri
#u8, @Ri *2
C
C
90
91
1+2a
1+2a
----------
(Ri)|= u4
(Ri)|= (u4<<4)
(Ri)|= u8
❍
❍
-
Lower 4-bit operation
Upper 4-bit operation
BEORL
BEORH
*BEOR
#u4, @Ri
#u4, @Ri
#u8, @Ri *3
C
C
98
99
1+2a
1+2a
----------
(Ri)^= u4
(Ri)^= (u4<<4)
(Ri)^= u8
❍
❍
-
Lower 4-bit operation
Upper 4-bit operation
BTSTL
BTSTH
#u4, @Ri
#u4, @Ri
C
C
88
89
2+a
2+a
0C-CC--
(Ri) & u4
(Ri) & (u4<<4)
-
Lower 4-bit test
Upper 4-bit test
*1: The assembler generates BANDL for u8&0x0F and BANDH for u8&0xF0. Both BANDL and BANDH may also be generated.
*2: The assembler generates BORL for u8&0x0F and BORH for u8&0xF0. Both BORL and BORH may also be generated.
*3: The assembler generates BEORL for u8&0x0F and BEORH for u8&0xF0. Both BEORL and BEORH may also be generated.
423
APPENDIX E Instruction List
■ Multiplication and Division Instructions
Table E.2-5 Multiplication and Division Instructions
Mnemonic
Type
OP
CYCLE
NZVC
MUL
MULU
MULH
MULUH
Rj,Ri
Rj,Ri
Rj,Ri
Rj,Ri
A
A
A
A
AF
AB
BF
BB
5
5
3
3
CCCCCCCC-CC--
DIV0S
DIV0U
DIV1
DIV2
DIV3
DIV4S
*DIV
Ri
Ri
Ri
Ri *3
E
E
E
E
E
E
97-4
97-5
97-6
97-7
9F-6
9F-7
Ri *1
1
1
d
1
1
1
36
-------C-C
-C-C
-------C-C
*DIVU
Ri *2
33
-C-C
Operation
Ri × Rj → MDH,MDL
Ri × Rj → MDH,MDL
Ri × Rj → MDL
Ri × Rj → MDL
Remarks
32 bits × 32 bits = 64 bits
Unsigned
16 bits × 16 bits = 32 bits
Unsigned
Step operation
32bit/32bit=32bit
MDL / Ri → MDL ,
MDL % Ri → MDH
MDL / Ri → MDL ,
MDL % Ri → MDH
*1: DIVOS, DIV × 32, DIV2, DIV3, and DIV4S are generated. The instruction code length is 72 bytes.
*2: DIVOU and DIV × 32 are generated. The instruction code length is 66
*3: Always place the DIV3 instruction after the DIV2 instruction.
■ Shift Instructions
Table E.2-6 Shift Instructions
Mnemonic
Type
OP
CYCLE
NZVC
Operation
Remarks
LSL
*LSL
LSL
LSL2
Rj, Ri
#u5, Ri (u5:0 to 31)
#u4, Ri
#u4, Ri
A
C'
C
C
B6
B4
B4
B5
1
1
1
1
CC-C
CC-C
CC-C
CC-C
Ri << Rj → Ri
Ri << u5 → Ri
Ri << u4 → Ri
Ri <<(u4+16) → Ri
Logical shift
LSR
*LSR
LSR
LSR2
Rj, Ri
#u5, Ri (u5:0 to 31)
#u4, Ri
#u4, Ri
A
C'
C
C
B2
B0
B0
B1
1
1
1
1
CC-C
CC-C
CC-C
CC-C
Ri >> Rj → Ri
Ri >> u5 → Ri
Ri >> u4 → Ri
Ri >>(u4+16) → Ri
Logical shift
ASR
*ASR
ASR
ASR2
Rj, Ri
#u5, Ri (u5:0 to 31)
#u4, Ri
#u4, Ri
A
C'
C
C
BA
B8
B8
B9
1
1
1
1
CC-C
CC-C
CC-C
CC-C
Ri >> Rj → Ri
Ri >> u5 → Ri
Ri >> u4 → Ri
Ri >>(u4+16) → Ri
Arithmetic shift
424
APPENDIX E Instruction List
■ Immediate Value Set and 16/32-bit Immediate Value Transfer Instructions
Table E.2-7 Immediate Value Set and 16/32-bit Immediate Value Transfer Instructions
Mnemonic
Type
OP
CYCLE
NZVC
Operation
LDI:32
LDI:20
#i32, Ri
#i20, Ri
E
C
9F-8
9B
3
2
-------
i32 → Ri
i20 → Ri
LDI:8
#i8, Ri
B
C0
1
----
i8 → Ri
*LDI
#{i8|i20|i32},Ri *1
Remarks
Upper 12 bits: Zero
extension
Upper 24 bits: Zero
extension
{i8|i20|i32} → Ri
*1: If the immediate value is an absolute value, the assembler automatically selects i8, i20, or i32.
If the immediate value is a relative value or contains an external reference symbol, i32 is selected.
■ Memory Load Instructions
Table E.2-8 Memory Load Instructions
Mnemonic
Type
OP
CYCLE
NZVC
Operation
Remarks
Rs: Special register *1
LD
LD
LD
LD
LD
LD
@Rj, Ri
@(R13,Rj), Ri
@(R14,disp10), Ri
@(R15,udisp6), Ri
@R15+, Ri
@R15+, Rs
A
A
B
C
E
E
04
00
20
03
07-0
07-8
b
b
b
b
b
b
-------------------
(Rj) → Ri
(R13+Rj) → Ri
(R14+disp10) → Ri
(R15+udisp6) → Ri
(R15) → Ri,R15+=4
(R15) → Rs, R15+=4
LD
@R15+, PS
E
07-9
1+a+b
CCCC
(R15) → PS, R15+=4
LDUH
LDUH
LDUH
@Rj, Ri
@(R13,Rj), Ri
@(R14,disp9), Ri
A
A
B
05
01
40
b
b
b
----------
(Rj) → Ri
(R13+Rj) → Ri
(R14+disp9) → Ri
Zero extension
Zero extension
Zero extension
LDUB
LDUB
LDUB
@Rj, Ri
@(R13,Rj), Ri
@(R14,disp8), Ri
A
A
B
06
02
60
b
b
b
----------
(Rj) → Ri
(R13+Rj) → Ri
(R14+disp8) → Ri
Zero extension
Zero extension
Zero extension
*1: Special register Rs: TBR, RP, USP, SSP, MDH, or MDL
Note:
The assembler calculates and sets values in the o8 and o4 fields of the hardware specifications as follows:
disp10/4 → o8, disp9/2 → o8, disp8 → o8 (disp10, disp9, and disp8 are signed.)
disp6/4 → o4 (udisp6 is unsigned.)
425
APPENDIX E Instruction List
■ Memory Store Instructions
Table E.2-9 Memory Store Instructions
Mnemonic
Type
OP
CYCLE
NZVC
Operation
Remarks
ST
ST
ST
ST
ST
ST
Ri, @Rj
Ri, @(R13,Rj)
Ri, @(R14,disp10)
Ri, @(R15,udisp6)
Ri, @-R15
Rs, @-R15
A
A
B
C
E
E
14
10
30
13
17-0
17-8
a
a
a
a
a
a
-------------------
Ri→(Rj)
Ri→(R13+Rj)
Ri→(R14+disp10)
Ri→(R15+udisp6)
R15-=4,Ri→(R15)
R15-=4, Rs→(R15)
ST
PS, @-R15
E
17-9
a
----
R15-=4, PS→(R15)
STH
STH
STH
Ri, @Rj
Ri, @(R13,Rj)
Ri, @(R14,disp9)
A
A
B
15
11
50
a
a
a
----------
Ri→(Rj)
Ri→(R13+Rj)
Ri→(R14+disp9)
Half word
Half word
Half word
STB
STB
STB
Ri, @Rj
Ri, @(R13,Rj)
Ri, @(R14,disp8)
A
A
B
16
12
70
a
a
a
----------
Ri→(Rj)
Ri→(R13+Rj)
Ri→(R14+disp8)
Byte
Byte
Byte
Word
Word
Word
Rs: Special register *1
*1: Special register Rs: TBR, RP, USP, SSP, MDH, or MDL
Note:
The assembler calculates and sets values in the o8 and o4 fields of the hardware specifications as follows:
disp10/4 → o8, disp9/2 → o8, disp8 → o8 (disp10, disp9, and disp8 are signed.)
udisp6/4 → o4 (udisp6 is unsigned.)
■ Inter-register Transfer Instructions
Table E.2-10 Inter-register Transfer Instructions
Mnemonic
Type
OP
CYCLE
NZVC
Operation
MOV
Rj, Ri
A
8B
1
----
Rj → Ri
MOV
MOV
MOV
MOV
Rs, Ri
Ri, Rs
PS, Ri
Ri, PS
A
A
E
E
B7
B3
17-1
07-1
1
1
1
c
---------CCCC
Rs → Ri
Ri → Rs
PS → Ri
Ri → PS
*1: Special register Rs: TBR, RP, USP, SSP, MDH, or MDL
426
Remarks
Transfer between generalpurpose registers
Rs: Special register *1
Rs: Special register *1
APPENDIX E Instruction List
■ Ordinary Branch (No Delay) Instructions
Table E.2-11 Ordinary Branch (No Delay) Instructions
Mnemonic
Type
OP
CYCLE
NZVC
Operation
JMP
@Ri
E
97-0
2
----
Ri → PC
CALL
CALL
label12
@Ri
F
E
D0
97-1
2
2
-------
PC+2→RP,PC+2+(label12-PC-2) →PC
PC+2→RP,Ri→PC
E
97-2
2
----
RP → PC
D
1F
3+3a
----
E
9F-3
3+3a
----
SSP-=4,PS→(SSP),SSP-=4,PC+2→(SSP),
0→T flag,0→S flag
(TBR+0x3FC-u8x4)→PC
SSP-=4,PS→(SSP),SSP-=4,PC+2→(SSP),
0→S flag,(TBR+0x3D8)→PC
RET
INT
#u8
INTE
Remarks
Return
For
emulator
RETI
E
97-3
2+2a
CCCC
BRA
BNO
BEQ
label9
label9
label9
D
D
D
E0
E1
E2
2
1
2/1
----------
BNE
BC
BNC
BN
BP
BV
BNV
BLT
BGE
BLE
BGT
BLS
BHI
label9
label9
label9
label9
label9
label9
label9
label9
label9
label9
label9
label9
label9
D
D
D
D
D
D
D
D
D
D
D
D
D
E3
E4
E5
E6
E7
E8
E9
EA
EB
EC
ED
EE
EF
2/1
2/1
2/1
2/1
2/1
2/1
2/1
2/1
2/1
2/1
2/1
2/1
2/1
----------------------------------------
(R15) →PC,R15-=4,(R15)→PS,R15-=4
PC+2+(label9-PC-2) →PC
No branch
if(Z==1) then
PC+2+(label9-PC-2) →PC
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
s/Z==0
s/C==1
s/C==0
s/N==1
s/N==0
s/V==1
s/V==0
s/V xor N==1
s/V xor N==0
s/(V xor N) or Z==1
s/(V xor N) or Z==0
s/C or Z==1
s/C or Z==0
Notes:
• "2/1" in the CYCLE column means branch (2) and no branch (1).
• The assembler calculates and sets values in the rel11 and rel8 fields of the hardware specifications as
follows:
(label12-PC-2)/2 → rel11, (label9-PC-2)/2 → rel8 (label12 and label19 are signed.)
• When the RETI instruction is executed, the S flag should be 0.
427
APPENDIX E Instruction List
■ Delayed Branch Instructions
Table E.2-12 Delayed Branch Instructions
Mnemonic
Type
OP
CYCLE NZVC
Operation
JMP:D
@Ri
E
9F-0
1
----
Ri → PC
CALL:D
CALL:D
label12
@Ri
F
E
D8
9F-1
1
1
-------
PC+4→RP,PC+2+(label12-PC-2) →PC
PC+4→RP,Ri→PC
E
9F-2
1
----
RP → PC
PC+2+(label9-PC-2)→PC
No branch
if(Z==1) then
PC+2+(label9-PC-2)→PC
RET:D
BRA:D
BNO:D
BEQ:D
label9
label9
label9
D
D
D
F0
F1
F2
1
1
1
----------
BNE:D
BC:D
BNC:D
BN:D
BP:D
BV:D
BNV:D
BLT:D
BGE:D
BLE:D
BGT:D
BLS:D
BHI:D
label9
label9
label9
label9
label9
label9
label9
label9
label9
label9
label9
label9
label9
D
D
D
D
D
D
D
D
D
D
D
D
D
F3
F4
F5
F6
F7
F8
F9
FA
FB
FC
FD
FE
FF
1
1
1
1
1
1
1
1
1
1
1
1
1
-------------------------------------
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
Remarks
Return
s/Z==0
s/C==1
s/C==0
s/N==1
s/N==0
s/V==1
s/V==0
s/V xor N==1
s/V xor N==0
s/(V xor N) or Z==1
s/(V xor N) or Z==0
s/C or Z==1
s/C or Z==0
Notes:
• The assembler calculates and sets values in the rel11 and rel8 fields of the hardware specifications as
follows:
(label12-PC-2)/2 → rel11, (label9-PC-2)/2 → rel8 (label12 and label19 are signed.)
• For delayed branch, control should be branched after executing the next instruction (delayed slot).
• All the 1-cycle (a, b, c, d) instructions can be placed at a delay slot.
Multi-cycle instructions are not permitted.
428
APPENDIX E Instruction List
■ Other Instructions
Table E.2-13 Other Instructions
Mnemonic
NOP
Typ
e
OP CYCLE NZVC
E
9F-A
1
----
Operation
No change
CCCC CCR and u8 → CCR
CCCC CCR or u8 → CCR
RMW
Remarks
-
ANDCCR
ORCCR
#u8
#u8
D
D
83
93
c
c
STILM
#u8
D
87
1
----
i8 → ILM
-
ILM immediate value set
ADDSP
#s10 *1
D
A3
1
----
R15 += s10
-
ADD SP instruction
EXTSB
EXTUB
EXTSH
EXTUH
Ri
Ri
Ri
Ri
E
E
E
E
97-8
97-9
97-A
97-B
1
1
1
1
-------------
Sign extension 8→32bit
Zero extension 8→32bit
Sign extension 16→32bit
Zero extension 16→32bit
-
LDM0
(reglist)
D
8C
----
-
Load multi-instruction (R0-R7)
LDM1
(reglist)
D
8D
----
-
Load multi-instruction (R8-R15)
*LDM
(reglist)*2
(R15) →reglist,
R15 increment
(R15) →reglist,
R15 increment
(R15) →reglist,
R15 increment
-
Load multi-instruction (R0-R15)
STM0
(reglist)
D
8E
----
-
Store multi-instruction (R0-R7)
STM1
(reglist)
D
8F
----
-
Store multi-instruction (R8-R15)
*STM
(reglist)*3
R15 decrement,
Reglist→(R15)
R15 decrement,
Reglist→(R15)
R15 decrement,
Reglist→(R15)
-
Store multi-instruction (R0-R15)
ENTER
#u10 *4
LEAVE
XCHB
@Rj, Ri
----
----
-
D
0F
1+a
----
R14 → (R15- 4),
R15 - 4 → R14,
R15 - u10 → R15
-
Function entry processing
E
9F-9
b
----
R14 + 4 → R15,
(R15 - 4) → R14
-
Function exit processing
A
8A
2a
----
Ri → TEMP
(Rj) → Ri
TEMP → (Rj)
❍
Byte data for semaphore
management
*1: For s10, the assembler calculates s10/4 and sets the result as s8. s10 is signed.
*2: The assembler generates LDM0 if one of R0 to R7 is specified in reglist and LDM1 if one of R8 to R15 is specified. Both LDM0 and
LDM1 may be generated.
*3: The assembler generates STM0 if one of R0 to R7 is specified in reglist and STM1 if one of R8 to R15 is specified. Both STM0 and
STM1 may be generated.
*4: For u10, the assembler calculates u10/4 and sets the result as u8. u10 is unsigned.
Notes:
• The number of execution cycles for LDM0 (reglist)/LDM1 (reglist) is a × (n-1)+b+1 if the specified
number of registers is n.
• The number of execution cycles for STM0 (reglist)/STM1 (reglist) is a × n+1 if the specified number of
registers is n.
429
APPENDIX E Instruction List
■ 20-bit Ordinary Branch Macroinstructions
Table E.2-14 20-bit Ordinary Branch Macroinstructions
Mnemonic
Operation
Remarks
*CALL20 label20,Ri
Next instruction address→RP, label20→PC
Ri:Temporary register (See Reference 1.)
*BRA20
*BEQ20
label20,Ri
label20,Ri
label20→PC
if(Z==1) then label20→PC
Ri:Temporary register (See Reference 2.)
Ri:Temporary register (See Reference 3.)
*BNE20
*BC20
*BNC20
*BN20
*BP20
*BV20
*BNV20
*BLT20
*BGE20
*BLE20
*BGT20
*BLS20
*BHI20
label20,Ri
label20,Ri
label20,Ri
label20,Ri
label20,Ri
label20,Ri
label20,Ri
label20,Ri
label20,Ri
label20,Ri
label20,Ri
label20,Ri
label20,Ri
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
s/Z==0
s/C==1
s/C==0
s/N==1
s/N==0
s/V==1
s/V==0
s/V xor N==1
s/V xor N==0
s/(V xor N) or Z==1
s/(V xor N) or Z==0
s/C or Z==1
s/C or Z==0
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
[Reference 1] CALL20
• If label20-PC-2 is -0x800 to +0x7fe, the instruction is generated as follows:
CALL label12
• If label20-PC-2 is outside the range of 1) or contains an external reference symbol, the instruction is
generated as follows:
LDI:20 #label20,Ri
CALL @Ri
[Reference 2] BRA20
• If label20-PC-2 is -0x100 to +0xfe, the instruction is generated as follows:
BRA label9
• If label20-PC-2 is outside the range of 1) or contains an external reference symbol, the instruction is
generated as follows:
LDI:20 #label20,Ri
JMP @Ri
[Reference 3] Bcc20
• If label20-PC-2 is -0x100 to +0xfe, the instruction is generated as follows:
Bcc label9
• If label20-PC-2 is outside the range of 1) or contains an external reference symbol, the instruction is
generated as follows:
Bxcc false xcc: Counter condition of cc
LDI:20 #label20,Ri
JMP @Ri
false:
430
APPENDIX E Instruction List
■ 20-Bit Delayed Branch Macroinstructions
Table E.2-15 20-bit Delayed Branch Macroinstructions
Mnemonic
Operation
Remarks
*CALL20:D label20,Ri
Next instruction address+2→RP,label20→PC
Ri:Temporary register (See Reference 1.)
*BRA20:D
*BEQ20:D
label20,Ri
label20,Ri
label20→PC
if(Z==1) then label20→PC
Ri:Temporary register (See Reference 2.)
Ri:Temporary register (See Reference 3.)
*BNE20:D
*BC20:D
*BNC20:D
*BN20:D
*BP20:D
*BV20:D
*BNV20:D
*BLT20:D
*BGE20:D
*BLE20:D
*BGT20:D
*BLS20:D
*BHI20:D
label20,Ri
label20,Ri
label20,Ri
label20,Ri
label20,Ri
label20,Ri
label20,Ri
label20,Ri
label20,Ri
label20,Ri
label20,Ri
label20,Ri
label20,Ri
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
s/Z==0
s/C==1
s/C==0
s/N==1
s/N==0
s/V==1
s/V==0
s/V xor N==1
s/V xor N==0
s/(V xor N) or Z==1
s/(V xor N) or Z==0
s/C or Z==1
s/C or Z==0
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
[Reference 1] CALL20:D
• If label20-PC-2 is -0x800 to +0x7fe, the instruction is generated as follows:
CALL:D label12
• If label20-PC-2 is outside the range of 1) or contains an external reference symbol, the instruction is
generated as follows:
LDI:20 #label20,Ri
CALL:D @Ri
[Reference 2] BRA20:D
• If label20-PC-2 is -0x100 to +0xfe, the instruction is generated as follows:
BRA:D label9
• If label20-PC-2 is outside the range of 1) or contains an external reference symbol, the instruction is
generated as follows:
LDI:20 #label20,Ri
JMP:D @Ri
[Reference 3] Bcc20:D
• If label20-PC-2 is -0x100 to +0xfe, the instruction is generated as follows:
Bcc:D label9
• If label20-PC-2 is outside the range of 1) or contains an external reference symbol, the instruction is
generated as follows:
Bxcc false xcc: Counter condition of cc
LDI:20 #label20,Ri
JMP:D @Ri
false:
431
APPENDIX E Instruction List
■ 32-bit Ordinary Branch Macroinstructions
Table E.2-16 32-bit Ordinary Branch Macroinstructions
Mnemonic
Operation
Remarks
*CALL32
label32,Ri
Next instruction address→RP, label32→PC
Ri:Temporary register (See Reference 1.)
*BRA32
*BEQ32
label32,Ri
label32,Ri
label32→PC
if(Z==1) then label32→PC
Ri:Temporary register (See Reference 2.)
Ri:Temporary register (See Reference 3.)
*BNE32
*BC32
*BNC32
*BN32
*BP32
*BV32
*BNV32
*BLT32
*BGE32
*BLE32
*BGT32
*BLS32
*BHI32
label32,Ri
label32,Ri
label32,Ri
label32,Ri
label32,Ri
label32,Ri
label32,Ri
label32,Ri
label32,Ri
label32,Ri
label32,Ri
label32,Ri
label32,Ri
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
s/Z==0
s/C==1
s/C==0
s/N==1
s/N==0
s/V==1
s/V==0
s/V xor N==1
s/V xor N==0
s/(V xor N) or Z==1
s/(V xor N) or Z==0
s/C or Z==1
s/C or Z==0
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
[Reference 1] CALL32
• If label32-PC-2 is -0x800 to +0x7fe, the instruction is generated as follows:
CALL label12
• If label32-PC-2 is outside the range of 1) or contains an external reference symbol, the instruction is
generated as follows:
LDI:32 #label32,Ri
CALL @Ri
[Reference 2] BRA32
• If label32-PC-2 is -0x100 to +0xfe, the instruction is generated as follows:
BRA label9
• If label32-PC-2 is outside the range of 1) or contains an external reference symbol, the instruction is
generated as follows:
LDI:32 #label32,Ri
JMP @Ri
[Reference 3] Bcc32
• If label32-PC-2 is -0x100 to +0xfe, the instruction is generated as follows:
Bcc label9
• If label32-PC-2 is outside the range of 1) or contains an external reference symbol, the instruction is
generated as follows:
Bxcc false xcc: Counter condition of cc
LDI:32 #label32,Ri
JMP @Ri
false:
432
APPENDIX E Instruction List
■ 32-bit Delayed Branch Macroinstructions
Table E.2-17 32-bit Delayed Branch Macroinstructions
Mnemonic
Operation
Remarks
*CALL32:D
label32,Ri
Next instruction address→RP, label32→PC
Ri:Temporary register (See Reference 1.)
*BRA32:D
*BEQ32:D
label32,Ri
label32,Ri
label32→PC
if(Z==1) then label32→PC
Ri:Temporary register (See Reference 2.)
Ri:Temporary register (See Reference 3.)
*BNE32:D
*BC32:D
*BNC32:D
*BN32:D
*BP32:D
*BV32:D
*BNV32:D
*BLT32:D
*BGE32:D
*BLE32:D
*BGT32:D
*BLS32:D
*BHI32:D
label32,Ri
label32,Ri
label32,Ri
label32,Ri
label32,Ri
label32,Ri
label32,Ri
label32,Ri
label32,Ri
label32,Ri
label32,Ri
label32,Ri
label32,Ri
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
s/Z==0
s/C==1
s/C==0
s/N==1
s/N==0
s/V==1
s/V==0
s/V xor N==1
s/V xor N==0
s/(V xor N) or Z==1
s/(V xor N) or Z==0
s/C or Z==1
s/C or Z==0
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
[Reference 1] CALL32:D
• If label32-PC-2 is -0x800 to +0x7fe, the instruction is generated as follows:
CALL:D label12
• If label32-PC-2 is outside the range of 1) or contains an external reference symbol, the instruction is
generated as follows:
LDI:32 #label32,Ri
CALL:D @Ri
[Reference 2] BRA32:D
• If label32-PC-2 is -0x100 to +0xfe, the instruction is generated as follows:
BRA:D label9
• If label32-PC-2 is outside the range of 1) or contains an external reference symbol, the instruction is
generated as follows:
LDI:32 #label32,Ri
JMP:D @Ri
[Reference 3] Bcc32:D
• If label32-PC-2 is -0x100 to +0xfe, the instruction is generated as follows:
Bcc:D label9
• If label32-PC-2 is outside the range of 1) or contains an external reference symbol, the instruction is
generated as follows:
Bxcc false xcc: Counter condition of cc
LDI:32 #label32,Ri
JMP:D @Ri
false:
433
APPENDIX E Instruction List
■ Direct Addressing Instructions
Table E.2-18 Direct Addressing Instructions
Mnemonic
Type
OP
CYCLE
NZVC
Operation
Remarks
DMOV
DMOV
DMOV
DMOV
DMOV
DMOV
@dir10,R13
R13,@dir10
@dir10,@R13+
@R13+,@dir10 *1
@dir10,@-R15
@R15+,@dir10
D
D
D
D
D
D
08
18
0C
1C
0B
1B
b
a
2a
2a
2a
2a
-------------------
(dir10) → R13
R13 →(dir10)
(dir10) →(R13),R13+=4
(R13) →(dir10),R13+=4
R15-=4,(R15) →(dir10)
(R15) →(dir10),R15+=4
Word
Word
Word
Word
Word
Word
DMOVH
DMOVH
DMOVH
DMOVH
@dir9,R13
R13,@dir9
@dir9,@R13+
@R13+,@dir9
D
D
D
D
09
19
0D
1D
b
a
2a
2a
-------------
(dir9) → R13
R13 →(dir9)
(dir9) →(R13),R13+=2
(R13) →(dir9),R13+=2
Half word
Half word
Half word
Half word
DMOVB
DMOVB
DMOVB
DMOVB
@dir8,R13
R13,@dir8
@dir8,@R13+
@R13+,@dir8
D
D
D
D
0A
1A
0E
1E
b
a
2a
2a
-------------
(dir8) → R13
R13 →(dir8)
(dir8) →(R13),R13++
(R13) →(dir8),R13++
Byte
Byte
Byte
Byte
*1: Place an NOP after the DMOV instruction specifying the R13+ as a transfer source.
Note:
The assembler calculates and sets values in the dir8, dir9, and dir10 fields:
dir8 → dir, dir9/2 → dir, dir10/4 → dir (dir dir8, dir9, and dir10 are unsigned.)
■ Resource Instructions
Table E.2-19 Resource Instructions
Mnemonic
Type
OP
CYCLE
NZVC
LDRES
@Ri+,#u4
C
BC
a
----
STRES
#u4,@Ri+
C
BD
a
----
Operation
(Ri) →u4 resource
Ri+=4
u4 resource →(Ri)
Ri+=4
Remarks
u4: Channel number
u4: Channel number
■ Coprocessor Control Instructions
Table E.2-20 Coprocessor Control Instructions
Mnemonic
COPOP
COPLD
COPST
COPSV
#u4,#u8,CRj,CRi
#u4,#u8,Rj,CRi
#u4,#u8,CRj,Ri
#u4,#u8,CRj,Ri
Type
OP
CYCLE
NZVC
E
E
E
E
9F-C
9F-D
9F-E
9F-F
2+a
1+2a
1+2a
1+2a
-------------
Operation
Operation instruction
Rj → CRi
CRj → Ri
CRj → Ri
Remarks
No error trap
Notes:
• {CRi|CRj}:=
CR0|CR1|CR2|CR3|CR4|CR5|CR6|CR7|CR8|CR9|CR10|CR11|CR12|CR13|CR14|CR15
4:= Channel specification
u8:= Command specification
• These instructions are not used because no coprocessor is mounted on this product.
434
INDEX
INDEX
The index follows on the next page.
This is listed in alphabetic order.
435
INDEX
Index
Numerics
A
0-detection
0-detection....................................................... 345
Data Register for 0-detection (BSD0) ................. 343
16/32-bit Immediate Value Transfer
Immediate Value Set and 16/32-bit Immediate Value
Transfer Instructions............................ 425
16/8-bit Data
Data Transfer Section, 16/8-bit Data .................. 335
Stopping a Transfer in Continuous Transfer Mode
(If Both Addresses Change),
16/8-bit Data....................................... 337
Stopping a Transfer in Continuous Transfer Mode
(If One of Addresses is Fixed),
16/8-bit Data....................................... 336
16-bit Reload Timer
Activating Multiple PWM Timer Channels
Using the 16-bit Reload Timer.............. 230
Block Diagram of the 16-bit Reload Timer ......... 200
Registers of the 16-bit Reload Timer .................. 201
16-bit Timer Register
16-bit Timer Register (TMR)............................. 204
16-bit Timer Register (TMRLR) ........................ 204
1-detection
1-detection....................................................... 345
Data Register for 1-detection (BSD1) ................. 343
20-bit Delayed Branch
20-Bit Delayed Branch
Macroinstructions................................ 431
20-bit Ordinary Branch
20-bit Ordinary Branch
Macroinstructions................................ 430
32-bit Delayed Branch
Instructions...................................................... 433
32-bit Ordinary Branch
Instructions...................................................... 432
A/D Converter
A/D Converter ................................................... 21
A/D Converter Operation Modes ....................... 279
Block Diagram of the A/D Converter................. 271
Features of the A/D Converter........................... 270
Notes on Using the A/D Converter .................... 283
Registers of the A/D Converter ......................... 272
Acquisition
Acquisition of Bus Privilege ............................. 186
Activating
Activating the Clock Doubler Function ................ 92
Activating Multiple PWM Timer Channels
Activating Multiple PWM Timer Channels
by Software ........................................ 230
Activating Multiple PWM Timer Channels
Using the 16-bit Reload Timer ............. 230
ADCR
Data Register (ADCR) ..................................... 278
ADCS
Control Status Register (ADCS) ........................ 273
Addition
Addition and Subtraction Instructions ................ 422
Addressing Mode
Addressing Mode Symbols ............................... 418
All-"H" Level
Example of Setting PWM Output
to All-"H" Level ................................. 229
All-L or All-H
All-L or All-H PWM Output Method................. 228
AMD
Area Mode Register 0 (AMD0) ......................... 118
Area Mode Register 1 (AMD1) ......................... 120
Area Mode Register 32 (AMD32) ..................... 121
Area Mode Register 4 (AMD4) ......................... 122
Area Mode Register 5 (AMD5) ......................... 123
AMR
Area Selection Register (ASR) and
Area Mask Register (AMR) ................. 115
Area Mask Register
Area Selection Register (ASR) and
Area Mask Register (AMR) ................. 115
Area Mode Register
Area Mode Register 0 (AMD0) ......................... 118
Area Mode Register 1 (AMD1) ......................... 120
Area Mode Register 32 (AMD32) ..................... 121
Area Mode Register 4 (AMD4) ......................... 122
Area Mode Register 5 (AMD5) ......................... 123
436
INDEX
Area Selection Register
Area Selection Register (ASR) and
Area Mask Register (AMR) ................. 115
Arithmetic Operation
Arithmetic Operation Function .......................... 376
ASR
Area Selection Register (ASR) and
Area Mask Register (AMR) ................. 115
Asynchronous
Transfer Data Formats in Asynchronous
(Step-synchronous) Modes................... 298
Automatic Wait Cycle
Automatic Wait Cycle for CBR Refresh ............. 185
Automatic Wait Cycle Timings ......................... 165
Automatic Wait Cycle Timings of the Ordinary
DRAM Interface ................................. 175
Available Levels
Available Levels of Hold Request Cancel
Request .............................................. 264
B
Basic Block Diagram
Basic Block Diagram of I/O Port ....................... 192
Basic Read Cycle Timings
Basic Read Cycle Timings ................................ 157
Basic Write Cycle Timings
Basic Write Cycle Timings ............................... 158
Baud Rate
Calculating the Baud Rate................................. 235
Examples of Setting Baud Rates and
U-TIMER Reload Values..................... 307
Big Endian
Big-endian Bus Access ..................................... 134
Differences between Little and Big Endians ....... 142
Bit Operation Instructions
Bit Operation Instructions ................................. 423
Bit Ordering
Bit Ordering ...................................................... 47
Bit Search Module
Block Diagram of the Bit Search Module ........... 342
Registers of the Bit Search Module .................... 342
Block
Blocks Using the Peripheral Clock....................... 87
Block Diagram
Basic Block Diagram of I/O Port ....................... 192
Block Diagram of the 16-bit Reload Timer ......... 200
Block Diagram of the A/D Converter ................. 271
Block Diagram of the Bit Search Module ........... 342
Block Diagram of the Bus Interface ................... 113
Block Diagram of the Clock Generator ................ 73
Block Diagram of the Delayed Interrupt
Module .............................................. 250
Block Diagram of the DMA Controller .............. 311
Block Diagram of the DMA Suppression
Circuit ..................................................90
Block Diagram of the DSP ................................349
Block Diagram of the Entire PWM Timer ...........211
Block Diagram of the External Interrupt/NMI Control
Section ...............................................238
Block Diagram of the Gear Control Section ..........85
Block Diagram of the Interrupt Controller...........255
Block Diagram of the PWM Timer
for One Channel ..................................212
Block Diagram of the Reset Source Hold
Circuit ..................................................88
Block Diagram of the Sleep Control Section .......102
Block Diagram of the Stop Control Section.........100
Block Diagram of the U-TIMER ........................232
Block Diagram of the Watchdog Control
Section .................................................83
General Block Diagram of MB91121 .....................6
UART Block Diagram ......................................287
Block Size
Step Transfer (Clock Doubler, Internal Descriptor,
Block Size=1) .....................................324
Branch
20-Bit Delayed Branch
Macroinstructions ................................431
20-bit Ordinary Branch
Macroinstructions ................................430
Branch Instruction with Delay Slot.......................53
Branch Instruction with No Delay Slot .................56
Delayed Branch Instructions ..............................428
Instructions ..............................................432, 433
JMP Instruction (Branch Instruction) ..................372
Limitations on the Operation of Branch Instruction
with Delay Slot......................................54
Operation of Branch Instruction
with Delay Slot......................................53
Operation of Branch Instruction
with No Delay Slot ................................56
Ordinary Branch (No Delay) Instructions............427
BSD
Data Register for 0-detection (BSD0) .................343
Data Register for 1-detection (BSD1) .................343
BSDC
Data Register for Change Point Detection
(BSDC) ..............................................344
BSRR
Detection Result Register (BSRR)......................344
Burst Transfer
Burst Transfer
(Clock Doubler, Internal Descriptor) .....326
Burst Transfer Mode .........................................322
Bus Access
Big-endian Bus Access......................................134
Little-endian Bus Access ...................................134
437
INDEX
Bus Interface
Block Diagram of the Bus Interface ................... 113
Features of the Bus Interface ............................. 110
Bus Interface Registers
Bus Interface Registers ..................................... 114
Bus Privilege
Acquisition of Bus Privilege.............................. 186
Release of Bus Privilege ................................... 186
Bus Widths
Combinations of Bus Widths ............................. 126
Byte Access
Byte Access ..................................................... 148
Byte Ordering
Byte Ordering .................................................... 47
C
Cache
Cache Entry Update............................................ 36
Cache Status in Each Operation Mode.................. 35
Cacheable Areas of the Instruction Cache ............. 29
Configuration of the Instruction Cache ................. 29
Configuration of the Instruction Cache Tag........... 31
Instruction Cache Control Register (ICHCR) ........ 33
Instruction Cache Setting Method ........................ 37
Cacheable Areas
Cacheable Areas of the Instruction Cache ............. 29
Calculating the Baud Rate
Calculating the Baud Rate ................................. 235
Calculation
Example of Calculation..................................... 385
Cancellation Standard
Cancellation Standard for Hold Request ............. 264
CAS
CAS before RAS (CBR) Refresh ....................... 184
Causes of Reset Delays
Causes of Reset Delays Other than Programs ........ 84
CBR
Automatic Wait Cycle for CBR Refresh ............. 185
CAS before RAS (CBR) Refresh ....................... 184
Change Point Detection
Change Point Detection .................................... 345
Data Register for Change Point Detection
(BSDC) .............................................. 344
Changing
Changing to the Sleep Status ............................. 102
Changing to the Stop Status............................... 100
Channels
Priority of Channels.......................................... 330
Character
Option Specifying the -K Lib Option
when Using Character String Operation
Functions............................................ 411
438
Using Character Array Operation Functions on Other
than Character-Type Arrays ................. 411
Chip Select Area
Chip Select Area .............................................. 110
CLK
Transfer Data Format in CLK Synchronous
Mode ................................................. 300
CLK Synchronous Mode
Transfer Data Format in CLK Synchronous
Mode ................................................. 300
Clock Doubler
Activating the Clock Doubler Function ................ 92
Burst Transfer
(Clock Doubler, Internal Descriptor)..... 326
Combination of Operating Frequencies by Clock
Doubler Function ON/OFF .................... 93
Continuous Transfer (Clock Doubler, Internal
Descriptor) ......................................... 325
Deactivating the Clock Doubler Function ............. 92
Precaution on Clock Doubler Function
ON/OFF............................................... 93
Step Transfer (Clock Doubler, Internal Descriptor,
Block Size=1)..................................... 324
Clock Generation STOP Status
Notes If Restoring from Clock Generation STOP
Status Performed Using an External
Interrupt ............................................. 245
Clock Generator
Block Diagram of the Clock Generator ................ 73
Registers of the Clock Generator ......................... 72
Clock Selection
UART Clock Selection ..................................... 297
Clock System
Reference Drawing of the Clock System .............. 95
Column Address
Row Address and Column Address.................... 151
Combination
Combination of Operating Frequencies by Clock
Doubler Function ON/OFF .................... 93
Combinations of Bus Widths............................. 126
Combinations of Sensing and Transfer Mode...... 323
Common Memory Mapping
Common Memory Mapping of the FR Family ...... 50
Compare
Compare Operation Instructions ........................ 422
Comparison
Comparison of External Access......................... 134
Configuration
Configuration of the Instruction Cache................. 29
Configuration of the Instruction Cache Tag .......... 31
Continuous Transfer
Continuous Transfer......................................... 331
Continuous Transfer (Clock Doubler, Internal
Descriptor) ......................................... 325
INDEX
Continuous Transfer Mode................................ 322
Stopping a Transfer in Continuous Transfer Mode
(If Both Addresses Change),
16/8-bit Data ...................................... 337
Stopping a Transfer in Continuous Transfer Mode
(If One of Addresses is Fixed),
16/8-bit Data ...................................... 336
Control Pin
Selection of External Pin Function
(I/O Port or Control Pin) ...................... 195
Control Register
Control Registers ............................................. 265
External Pin Control Register 0 (EPCR0) ........... 129
External Pin Control Register 1 (EPCR1) ........... 131
Control Signals
Relationships between Data Bus Widths and
Control Signals ........................... 134, 135
Control Status Register
Control Status Register (ADCS) ........................ 273
Control Status Register (TMCSR) ..................... 202
Control/Status Register (DSP-CSR) ................... 361
Control/Status Register (PCNH0 to PCNH3,
PCNL0 to PCNL3).............................. 214
Converted Data Protection Function
Converted Data Protection Function .................. 281
Coprocessor Control
Coprocessor Control Instructions....................... 434
Counter Operation
Counter Operation Statuses ............................... 207
CPU
Features of the CPU Architecture ........................ 26
Pin Status in Each CPU State ............................ 403
CSR
Control/Status Register (DSP-CSR) ................... 361
CTBR
Timebase Timer Clear Register (CTBR)............... 77
D
DACSR
DMAC Control/Status Register (DACSR) .......... 314
Data Access
Data Access............................................... 48, 412
Data Bus Width
Data Bus Width ....................................... 138, 144
Relationships between Data Bus Widths and
Control Signals ........................... 134, 135
Data Format
Data Format ............................................ 137, 143
Transfer Data Format in CLK Synchronous
Mode ................................................. 300
Transfer Data Formats in Asynchronous
(Step-synchronous) Modes................... 298
Data Protection
Converted Data Protection Function .................. 281
Data Register
Data Register (ADCR) ......................................278
Data Register for 0-detection (BSD0) .................343
Data Register for 1-detection (BSD1) .................343
Data Register for Change Point Detection
(BSDC) ..............................................344
Data Transfer
Data Transfer Section, 16/8-bit Data...................335
DATCR
DMAC Pin Control Register (DATCR) ..............316
DDR
Port Direction Register (DDR2 to DDRI)............194
Deactivating
Deactivating the Clock Doubler Function..............92
Debugger
Emulator/Monitor Debugger ..............................414
Simulator Debugger ..........................................414
Dedicated Registers
Dedicated Registers ............................................40
Delay
Branch Instruction with Delay Slot.......................53
Branch Instruction with No Delay Slot .................56
Causes of Reset Delays Other than Programs ........84
Delay Register (DSP-LY)..................................365
Limitations on the Operation of Branch Instruction
with Delay Slot......................................54
Operation of Branch Instruction
with Delay Slot......................................53
Operation of Branch Instruction
with No Delay Slot ................................56
Ordinary Branch (No Delay) Instructions............427
Delay Register
Delay Register (DSP-LY)..................................365
Delayed Branch
20-Bit Delayed Branch
Macroinstructions ................................431
Delayed Branch Instructions ..............................428
Instructions ......................................................433
Delayed Interrupt
Block Diagram of the Delayed Interrupt
Module ...............................................250
Registers of the Delayed Interrupt Module ..........250
Delayed Interrupt Control Register
Delayed Interrupt Control Register (DICR) .........251
Delayed Write Function
Delayed Write Function ....................................378
Descriptor Access
Descriptor Access Section, 16/8-bit Data ............333
Detection Result Register
Detection Result Register (BSRR)......................344
DICR
Delayed Interrupt Control Register (DICR) .........251
DLYI Bit in DICR ............................................252
439
INDEX
Differences
Differences between Little and Big Endians........ 142
Differences in DREQ Sensing Modes
(Note on Edge Mode) .......................... 327
Differences in DREQ Sensing Modes
(Note on Level Mode).......................... 328
Direct Addressing
Direct Addressing Instructions........................... 434
Division
Multiplication and Division Instructions ............. 424
DLYI
DLYI Bit in DICR............................................ 252
DMA
Block Diagram of the DMA Controller............... 311
Block Diagram of the DMA Suppression
Circuit .................................................. 90
DMA Request Suppression Register (PDRR) ........ 76
DMA Transfer Operation in Sleep Mode ............ 331
DMA Transfer Request Resources ..................... 331
DMA Transfer when Y-RAM Bank is
Disabled ............................................. 379
DMA Transfer when Y-RAM Bank is
Enabled .............................................. 381
Features of DMA Controller.............................. 310
Operation of DMA Controller Software Trigger
Circuit ................................................ 340
Registers of the DMA Controller ....................... 312
Setting the DMA Suppression Function ................ 90
Suppressing DMA Transfer when a High-Priority
Interrupt Occurs .................................. 330
Using a Resource Interrupt Request as a DMA
Transfer Request ................................. 330
DMA Request Suppression Register
DMA Request Suppression Register (PDRR) ........ 76
DMA Transfer
DMA Transfer Operation in Sleep Mode ............ 331
DMA Transfer Request Resources ..................... 331
DMA Transfer when Y-RAM Bank is
Disabled ............................................. 379
DMA Transfer when Y-RAM Bank is
Enabled .............................................. 381
Suppressing DMA Transfer when a High-Priority
Interrupt Occurs .................................. 330
Using a Resource Interrupt Request as a DMA
Transfer Request ................................. 330
DMAC
DMAC Control/Status Register (DACSR) .......... 314
DMAC Parameter Descriptor Pointer (DPDP)..... 313
DMAC Pin Control Register (DATCR) .............. 316
Transfer to DMAC Internal Register .................. 331
DMAC Control/Status Register
DMAC Control/Status Register (DACSR) .......... 314
DMAC Internal Register
Transfer to DMAC Internal Register .................. 331
440
DMAC Parameter Descriptor Pointer
DMAC Parameter Descriptor Pointer (DPDP) .... 313
DMAC Pin Control Register
DMAC Pin Control Register (DATCR).............. 316
DMCR
DRAM Control Registers 4 and 5
(DMCR4 and DMCR5) ....................... 124
Double
Using Double or Long-double Variables ............ 411
DPDP
DMAC Parameter Descriptor Pointer (DPDP) .... 313
DRAM
Automatic Wait Cycle Timings of the Ordinary
DRAM Interface ................................. 175
DRAM Connection .......................................... 134
DRAM Control Pins......................................... 150
DRAM Control Registers 4 and 5
(DMCR4 and DMCR5) ....................... 124
DRAM Interface ...................................... 112, 154
DRAM Interface Timings in High-speed Page
Mode ................................................. 176
DRAM Refresh................................................ 156
DRAM Signal Control Register (DSCR) ............ 132
Example of DRAM Device Connection ............. 153
Hyper DRAM Interface Timings ....................... 183
Ordinary DRAM Read Cycle Timings ............... 171
Ordinary DRAM Write Cycle Timings .............. 173
Read Cycle Timings of the Hyper DRAM
Interface............................................. 181
Read Cycle Timings of the Ordinary DRAM
Interface............................................. 167
Read Cycle Timings of the Single DRAM
Interface............................................. 178
Single DRAM Interface Timings ....................... 180
Write Cycle Timings of the Hyper DRAM
Interface............................................. 182
Write Cycle Timings of the Ordinary DRAM
Interface............................................. 169
Write Cycle Timings of the Single DRAM
Interface............................................. 179
DRAM Control Registers
DRAM Control Registers 4 and 5
(DMCR4 and DMCR5) ....................... 124
DRAM Interface Timings
DRAM Interface Timings in High-speed Page
Mode ................................................. 176
DRAM Signal Control Register
DRAM Signal Control Register (DSCR) ............ 132
DREQ
Differences in DREQ Sensing Modes
(Note on Edge Mode) .......................... 327
Differences in DREQ Sensing Modes
(Note on Level Mode) ......................... 328
DREQ Signal Sensing Mode ............................. 323
INDEX
DSCR
DRAM Signal Control Register (DSCR) ............ 132
DSP
Block Diagram of the DSP................................ 349
Control/Status Register (DSP-CSR) ................... 361
Delay Register (DSP-LY) ................................. 365
DSP Instruction Definition................................ 367
DSP Instruction Operations............................... 367
DSP Operation Mode ....................................... 373
DSP Registers.................................................. 352
Example of DSP Operation ............................... 387
Example of DSP Program ................................. 386
Example of Setting the DSP .............................. 386
Features of the DSP.......................................... 348
Program Counter (DSP-PC) .............................. 364
Sum-of-products Macro (Simple DSP) ................... 3
Variable Monitor Register
(DSP-OT0 to DSP-OT3)...................... 366
DSP-CSR
Control/Status Register (DSP-CSR) ................... 361
DSP-LY
Delay Register (DSP-LY) ................................. 365
DSP-OT
Variable Monitor Register
(DSP-OT0 to DSP-OT3)...................... 366
DSP-PC
Program Counter (DSP-PC) .............................. 364
E
Edge Mode
Differences in DREQ Sensing Modes
(Note on Edge Mode) .......................... 327
EIRR
External Interrupt Request Register (EIRR) ........ 241
EIT
EIT Sources....................................................... 57
EIT Vector Table ............................................... 64
Features of EIT .................................................. 57
Notes on EIT ..................................................... 57
Priority of EIT Source Received and Masking
of Other Sources ................................... 66
Return from EIT ................................................ 57
ELVR
External LeVel Register (ELVR) ....................... 242
Emulator
Emulator/Monitor Debugger ............................. 414
ENable Interrupt Request Register
ENable Interrupt Request Register (ENIR) ......... 240
ENIR
ENable Interrupt Request Register (ENIR) ......... 240
Entire PWM Timer
Block Diagram of the Entire PWM Timer .......... 211
EPCR
External Pin Control Register 0 (EPCR0) ........... 129
External Pin Control Register 1 (EPCR1)............131
Error
No Error Detection ...........................................413
Example
Example of Calculation .....................................385
Example of DRAM Device Connection ..............153
Example of DSP Operation................................387
Example of DSP Program..................................386
Example of External Device Connection.............141
Example of PLL Clock Setting.............................94
Example of Setting PWM Output
to All-"H" Level ..................................229
Example of Setting the DSP...............................386
Example of Transfer .........................................385
Example of UART Application ..........................305
Examples of External Device Connection ...........145
Examples of Setting Baud Rates and
U-TIMER Reload Values .....................307
Explanations
Explanations of the Pin Functions ..........................9
External Access
Comparison of External Access .........................134
External Bus Access
External Bus Access .........................................139
External Bus Operations
Program Specifications for External Bus
Operations ..........................................188
Sample Program for External Bus Operations......189
External Bus Request
External Bus Request ........................................156
External Clock
Note on Using the External Clock ........................20
External Device Connection
Example of External Device Connection.............141
Examples of External Device Connection ...........145
External Interrupt
Block Diagram of the External Interrupt/NMI Control
Section ...............................................238
External Interrupt Procedure ..............................243
External Interrupt Processing .............................243
External Interrupt Request Level ........................244
External Interrupt Request Register (EIRR).........241
Notes If Restoring from Clock Generation STOP
Status Performed Using an External
Interrupt..............................................245
Registers of the External Interrupt/NMI Control
Section ...............................................239
External Interrupt Request Register
External Interrupt Request Register (EIRR).........241
External LeVel Register
External LeVel Register (ELVR) .......................242
External Pin Control Register
External Pin Control Register 0 (EPCR0)............129
External Pin Control Register 1 (EPCR1)............131
441
INDEX
External Pin Function
Selection of External Pin Function
(I/O Port or Control Pin) ...................... 195
External Reset
Note on Using External Reset Input ..................... 20
External Wait Cycle Timings
External Wait Cycle Timings............................. 166
F
Features
Features of DMA Controller.............................. 310
Features of EIT .................................................. 57
Features of MB91121 ........................................... 2
Features of the A/D Converter ........................... 270
Features of the Bus Interface ............................. 110
Features of the CPU Architecture......................... 26
Features of the DSP .......................................... 348
Features of the PWM Timer .............................. 210
Features of UART ............................................ 286
First Descriptor Word
First Descriptor Word ....................................... 318
Flag
UART Flags and Interrupts ............................... 302
UART Interrupts and Flag Setting Timings: Reception
in Mode 0 ........................................... 302
UART Interrupts and Flag Setting Timings: Reception
in Mode 1 ........................................... 303
UART Interrupts and Flag Setting Timings: Reception
in Mode 2 ........................................... 303
UART Interrupts and Flag Setting Timings:
Transmission in Modes 0 to 2 ............... 304
Format
Data Format............................................. 137, 143
Instruction Formats........................................... 420
Transfer Data Formats in Asynchronous
(Step-synchronous) Modes ................... 298
FR Family
Common Memory Mapping of the FR Family....... 50
FR Family Instruction List ................................ 421
Functions
Main Functions of the Interrupt Controller.......... 254
Option Specifying the -K Lib Option
when Using Character String Operation
Functions............................................ 411
Using Character Array Operation Functions on Other
than Character-Type Arrays ................. 411
G
GCN
General Control Register 1 (GCN1) ................... 221
GCR
Gear Control Register (GCR) .............................. 78
General Control Register 2 (GCR2) ................... 224
442
Gear Control Register
Gear Control Register (GCR) .............................. 78
Gear Control Section
Block Diagram of the Gear Control Section.......... 85
Gear Ratio
Setting the Gear Ratio ........................................ 86
General Block Diagram
General Block Diagram of MB91121..................... 6
General Control Register
General Control Register 1 (GCN1) ................... 221
General Control Register 2 (GCR2) ................... 224
General-purpose Registers
General-purpose Registers .................................. 46
H
Half-word Access
Half-word Access ............................................ 147
Handling
Handling of Circuit ............................................ 19
Handling when the Power-supply Voltage is Unstable
or the Power Supply is Intercepted.......... 21
Hardware Configuration
Hardware Configuration ................................... 265
Hardware Configuration of the Interrupt
Controller........................................... 254
High-Priority Interrupt
Suppressing DMA Transfer when a High-Priority
Interrupt Occurs.................................. 330
High-speed Page Mode
DRAM Interface Timings in High-speed Page
Mode ................................................. 176
Hold
Setting the Reset Source Hold Function ............... 89
Hold Function
Setting the Reset Source Hold Function ............... 89
Hold Request
Cancellation Standard for Hold Request ............. 264
Hold Request Cancel Request
Available Levels of Hold Request Cancel
Request .............................................. 264
Hold Request Cancel Request Sequence............. 266
Hold Request Cancel Request Level Setting Register
Hold Request Cancel Request Level Setting Register
(HRCL) ............................................. 259
HRCL
Hold Request Cancel Request Level Setting Register
(HRCL) ............................................. 259
Hyper DRAM Interface
Hyper DRAM Interface Timings ....................... 183
Read Cycle Timings of the Hyper DRAM
Interface............................................. 181
Write Cycle Timings of the Hyper DRAM
Interface............................................. 182
INDEX
I
I Flag
I Flag ................................................................ 58
I/O Circuit
I/O Circuit Types ............................................... 15
I/O Mapping
I/O Mapping.................................................... 393
Reading the I/O Mapping.................................. 392
I/O Port
Basic Block Diagram of I/O Port ....................... 192
I/O Port Registers............................................. 192
Selection of External Pin Function
(I/O Port or Control Pin) ...................... 195
I/O Port Registers
I/O Port Registers............................................. 192
ICHCR
Instruction Cache Control Register (ICHCR) ........ 33
ICR
Interrupt Control Register (ICR) .......................... 60
Interrupt Control Register (ICR00 to ICR47) ...... 258
Mapping of the Interrupt Control Register
(ICR) ................................................... 60
ILM
Interrupt Level Mask Register (ILM) ................... 59
Immediate Value Set
Immediate Value Set and 16/32-bit Immediate Value
Transfer Instructions ........................... 425
Initial Valued Variables
Placing Initial Valued Variables ........................ 410
Initialization
Initialization by Reset......................................... 71
Instruction
Addition and Subtraction Instructions ................ 422
Bit Operation Instructions ................................. 423
Branch Instruction with Delay Slot ...................... 53
Branch Instruction with No Delay Slot................. 56
Cacheable Areas of the Instruction Cache............. 29
Compare Operation Instructions ........................ 422
Configuration of the Instruction Cache................. 29
Configuration of the Instruction Cache Tag .......... 31
Coprocessor Control Instructions....................... 434
Delayed Branch Instructions ............................. 428
Direct Addressing Instructions .......................... 434
DSP Instruction Definition................................ 367
DSP Instruction Operations............................... 367
FR Family Instruction List ................................ 421
Immediate Value Set and 16/32-bit Immediate Value
Transfer Instructions ........................... 425
Instruction Cache Control Register (ICHCR) ........ 33
Instruction Cache Setting Method ........................ 37
Instruction Formats .......................................... 420
Instructions.............................................. 432, 433
Inter-register Transfer Instructions..................... 426
JMP Instruction (Branch Instruction) ................. 372
Limitations on the Operation of Branch Instruction
with Delay Slot......................................54
Logical Operation Instructions ...........................423
MAC Instruction ..............................................368
Memory Load Instructions.................................425
Memory Store Instructions ................................426
Multiplication and Division Instructions .............424
Operation of Branch Instruction
with Delay Slot......................................53
Operation of Branch Instruction
with No Delay Slot ................................56
Ordinary Branch (No Delay) Instructions............427
Other Instructions .............................................429
Outline of Instructions.........................................51
Processing of INT Instruction ..............................69
Processing of INTE Instruction ............................69
Processing of RETI Instruction ............................70
Processing of Undefined Instruction
Exception..............................................70
Reading the Instruction List ...............................416
Resource Instructions ........................................434
Shift Instructions ..............................................424
STR Instruction (Transfer Instruction) ................370
Instruction Cache Control Register
Instruction Cache Control Register (ICHCR).........33
Instruction List
FR Family Instruction List.................................421
Reading the Instruction List ...............................416
INT
Processing of INT Instruction ..............................69
INTE
Processing of INTE Instruction ............................69
Interface
Interface ..........................................................111
Internal Architecture
Structure of the Internal Architecture....................27
Internal Clock
Internal Clock Multiplication .............................187
Internal Clock Operation ...................................205
Internal Descriptor
Burst Transfer
(Clock Doubler, Internal Descriptor) .....326
Continuous Transfer (Clock Doubler, Internal
Descriptor)..........................................325
Step Transfer (Clock Doubler, Internal Descriptor,
Block Size=1) .....................................324
Inter-register Transfer
Inter-register Transfer Instructions .....................426
Interrupt
Block Diagram of the Delayed Interrupt
Module ...............................................250
Block Diagram of the External Interrupt/NMI Control
Section ...............................................238
Block Diagram of the Interrupt Controller...........255
Delayed Interrupt Control Register (DICR) .........251
443
INDEX
ENable Interrupt Request Register (ENIR) ......... 240
External Interrupt Procedure.............................. 243
External Interrupt Processing............................. 243
External Interrupt Request Level........................ 244
External Interrupt Request Register (EIRR) ........ 241
Hardware Configuration of the Interrupt
Controller ........................................... 254
Interrupt Control Register (ICR) .......................... 60
Interrupt Control Register (ICR00 to ICR47) ...... 258
Interrupt Level ................................................... 58
Interrupt Level Mask Register (ILM) ................... 59
Interrupt Number.............................................. 252
Interrupt Stack ................................................... 62
Interrupt Vectors .............................................. 399
Interrupt/NMI Level Masking.............................. 59
Main Functions of the Interrupt Controller.......... 254
Mapping of the Interrupt Control Register
(ICR) ................................................... 60
Non-maskable Interrupt (NMI) .......................... 262
Notes If Restoring from Clock Generation STOP
Status Performed Using an External
Interrupt ............................................. 245
Processing of User Interrupt/NMI ........................ 68
PWM Timer Interrupt Resources and Timing Chart
(PWM Output is Ordinary Polarity) ...... 228
Registers of the Delayed Interrupt Module.......... 250
Registers of the External Interrupt/NMI Control
Section ............................................... 239
Registers of the Interrupt Controller ................... 256
Release of Interrupt Resource ............................ 262
Suppressing DMA Transfer when a High-Priority
Interrupt Occurs .................................. 330
UART Flags and Interrupts ............................... 302
UART Interrupts and Flag Setting Timings: Reception
in Mode 0 ........................................... 302
UART Interrupts and Flag Setting Timings: Reception
in Mode 1 ........................................... 303
UART Interrupts and Flag Setting Timings: Reception
in Mode 2 ........................................... 303
UART Interrupts and Flag Setting Timings:
Transmission in Modes 0 to 2 ............... 304
Using a Resource Interrupt Request as a DMA
Transfer Request ................................. 330
Interrupt Control Register
Interrupt Control Register (ICR) .......................... 60
Interrupt Control Register (ICR00 to ICR47) ...... 258
Mapping of the Interrupt Control Register
(ICR) ................................................... 60
Interrupt Controller
Block Diagram of the Interrupt Controller .......... 255
Hardware Configuration of the Interrupt
Controller ........................................... 254
Main Functions of the Interrupt Controller.......... 254
Registers of the Interrupt Controller ................... 256
Interrupt Level
Interrupt Level ................................................... 58
444
Interrupt Level Mask Register
Interrupt Level Mask Register (ILM) ................... 59
Interrupt Vectors
Interrupt Vectors.............................................. 399
J
JMP
JMP Instruction (Branch Instruction) ................. 372
K
-K Lib
Option Specifying the -K Lib Option
when Using Character String Operation
Functions ........................................... 411
L
Latch-up
Latch-up Prevention ........................................... 18
LER
Little Endian Register (LER)............................. 133
Level Masking
Interrupt/NMI Level Masking ............................. 59
Level Mode
Differences in DREQ Sensing Modes
(Note on Level Mode) ......................... 328
Limitations
Limitations on the Operation of Branch Instruction
with Delay Slot ..................................... 54
List
List of Operations in Low-power Consumption
Mode ................................................... 98
Little
Differences between Little and Big Endians ....... 142
Little Endian
Little Endian Register (LER)............................. 133
Little-endian Bus Access .................................. 134
Placing a Stack in a Little Endian Area .............. 411
Little Endian Register
Little Endian Register (LER)............................. 133
Logical
Logical Operation Instructions .......................... 423
Long-double
Using Double or Long-double Variables ............ 411
Low-power Consumption Mode
List of Operations in Low-power Consumption
Mode ................................................... 98
Status Transition in Low-power Consumption
Mode ................................................. 104
LQFP-120
Outside Dimension Drawing of LQFP-120 ............. 7
Pin Arrangement Diagram of LQFP-120 ................ 8
INDEX
M
MAC
MAC Instruction.............................................. 368
Macro
Instructions.............................................. 432, 433
Sum-of-products Macro (Simple DSP) ................... 3
Macroinstruction
20-Bit Delayed Branch
Macroinstructions ............................... 431
20-bit Ordinary Branch
Macroinstructions ............................... 430
Main Functions
Main Functions of the Interrupt Controller ......... 254
Mapping
Mapping of the Interrupt Control Register
(ICR) ................................................... 60
MB91121
Features of MB91121 ........................................... 2
General Block Diagram of MB91121..................... 6
Memory Mapping of MB91121 ........................... 49
Memory Load
Memory Load Instructions ................................ 425
Memory Mapping
Common Memory Mapping of the FR Family ...... 50
Memory Mapping .............................................. 24
Memory Mapping of MB91121 ........................... 49
Memory Store
Memory Store Instructions................................ 426
Mode
A/D Converter Operation Modes ....................... 279
Addressing Mode Symbols ............................... 418
Area Mode Register 0 (AMD0) ......................... 118
Area Mode Register 1 (AMD1) ......................... 120
Area Mode Register 32 (AMD32)...................... 121
Area Mode Register 4 (AMD4) ......................... 122
Area Mode Register 5 (AMD5) ......................... 123
Burst Transfer Mode ........................................ 322
Cache Status in Each Operation Mode ................. 35
Combinations of Sensing and Transfer Mode...... 323
Continuous Transfer Mode................................ 322
Differences in DREQ Sensing Modes
(Note on Edge Mode) .......................... 327
Differences in DREQ Sensing Modes
(Note on Level Mode) ......................... 328
DMA Transfer Operation in Sleep Mode ............ 331
DRAM Interface Timings in High-speed Page
Mode ................................................. 176
DREQ Signal Sensing Mode ............................. 323
DSP Operation Mode ....................................... 373
List of Operations in Low-power Consumption
Mode ................................................... 98
Mode Data ...................................................... 106
Mode Pins ....................................................... 106
Mode Register (MODR) ................................... 106
Notes on During Operation of PLL Clock
Mode....................................................20
Notes on Mode Register (MODR) Write .............107
One-shot Mode Timing Charts ...........................227
Operation Modes ..............................................105
PWM Mode Timing Charts ...............................225
Read Cycle Timings in Each Mode ....................160
Return from Standby Mode (Stop or Sleep).........263
Serial Mode Register (SMR0 to SMR2) ..............289
Single/Block Transfer Mode ..............................321
Status Transition in Low-power Consumption
Mode..................................................104
Stopping a Transfer in Continuous Transfer Mode
(If Both Addresses Change),
16/8-bit Data .......................................337
Stopping a Transfer in Continuous Transfer Mode
(If One of Addresses is Fixed),
16/8-bit Data .......................................336
Transfer Data Format in CLK Synchronous
Mode..................................................300
Transfer Data Formats in Asynchronous
(Step-synchronous) Modes ...................298
UART Interrupts and Flag Setting Timings: Reception
in Mode 0 ...........................................302
UART Interrupts and Flag Setting Timings: Reception
in Mode 1 ...........................................303
UART Interrupts and Flag Setting Timings: Reception
in Mode 2 ...........................................303
UART Interrupts and Flag Setting Timings:
Transmission in Modes 0 to 2 ...............304
UART Operation Modes ...................................297
Write Cycle Timings in Each Mode....................162
Y-RAM Expansion Mode..................................384
Mode Data
Mode Data .......................................................106
Mode Pins
Mode Pins........................................................106
Mode Register
Mode Register (MODR)....................................106
Notes on Mode Register (MODR) Write .............107
MODR
Mode Register (MODR)....................................106
Notes on Mode Register (MODR) Write .............107
Module
Block Diagram of the Bit Search Module............342
Block Diagram of the Delayed Interrupt
Module ...............................................250
Registers of the Bit Search Module ....................342
Registers of the Delayed Interrupt Module ..........250
Monitor
Emulator/Monitor Debugger ..............................414
Variable Monitor Output ...................................378
Variable Monitor Register
(DSP-OT0 to DSP-OT3) ......................366
Multiplication
Multiplication and Division Instructions .............424
445
INDEX
N
NMI
Block Diagram of the External Interrupt/NMI Control
Section ............................................... 238
Interrupt/NMI Level Masking.............................. 59
NMI Processing ............................................... 247
Non-maskable Interrupt (NMI) .......................... 262
Processing of User Interrupt/NMI ........................ 68
Registers of the External Interrupt/NMI Control
Section ............................................... 239
No Delay
Branch Instruction with No Delay Slot ................. 56
Operation of Branch Instruction
with No Delay Slot ................................ 56
Ordinary Branch (No Delay) Instructions ........... 427
No Error Detection
No Error Detection ........................................... 413
Non-maskable Interrupt
Non-maskable Interrupt (NMI) .......................... 262
Note
Note on Source Oscillation Input ......................... 21
Note on Using External Reset Input ..................... 20
Note on Using the External Clock ........................ 20
Notes If Restoring from Clock Generation STOP
Status Performed Using an External
Interrupt ............................................. 245
Notes on During Operation of PLL Clock
Mode ................................................... 20
Notes on EIT ..................................................... 57
Notes on Mode Register (MODR) Write............. 107
Notes on UART Use......................................... 305
Notes on Using the A/D Converter..................... 283
O
OFAS
Offset Address Initial Value Setting Register
(OFAS) .............................................. 353
Offset Address Initial Value Setting Register
Offset Address Initial Value Setting Register
(OFAS) .............................................. 353
Offset Control Setting Register
Offset Control Setting Register (OFSC).............. 355
Offset Data Register
Offset Data Register (OFSD)............................. 360
Offset Register
Offset Register (OFFSS) ................................... 357
OFFSS
Offset Register (OFFSS) ................................... 357
OFSC
Offset Control Setting Register (OFSC).............. 355
OFSD
Offset Data Register (OFSD)............................. 360
One-shot Mode Timing
One-shot Mode Timing Charts........................... 227
446
Operation
Bit Operation Instructions ................................. 423
Compare Operation Instructions ........................ 422
DMA Transfer Operation in Sleep Mode............ 331
Example of DSP Operation ............................... 387
Internal Clock Operation .................................. 205
Limitations on the Operation of Branch Instruction
with Delay Slot ..................................... 54
Logical Operation Instructions .......................... 423
Notes on During Operation of PLL Clock
Mode ................................................... 20
Operation of Branch Instruction
with Delay Slot ..................................... 53
Operation of Branch Instruction
with No Delay Slot................................ 56
Operation of DMA Controller Software Trigger
Circuit ............................................... 340
Option Specifying the -K Lib Option
when Using Character String Operation
Functions ........................................... 411
Transfer End Operation
(If Both Addresses Change) ................. 339
Transfer End Operation
(If One of Addresses is Fixed).............. 338
Operation Mode
A/D Converter Operation Modes ....................... 279
Cache Status in Each Operation Mode ................. 35
DSP Operation Mode ....................................... 373
Operation Modes ............................................. 105
UART Operation Modes................................... 297
Option
Option Specifying the -K Lib Option
when Using Character String Operation
Functions ........................................... 411
Ordinary Branch
20-bit Ordinary Branch
Macroinstructions ............................... 430
Instructions ..................................................... 432
Ordinary Branch (No Delay) Instructions ........... 427
Ordinary Bus Access
Ordinary Bus Access ........................................ 154
Ordinary DRAM Interface
Automatic Wait Cycle Timings of the Ordinary
DRAM Interface ................................. 175
Read Cycle Timings of the Ordinary DRAM
Interface............................................. 167
Write Cycle Timings of the Ordinary DRAM
Interface............................................. 169
Ordinary DRAM Read Cycle Timings
Ordinary DRAM Read Cycle Timings ............... 171
Ordinary DRAM Write Cycle Timings
Ordinary DRAM Write Cycle Timings .............. 173
Ordinary Polarity
PWM Timer Interrupt Resources and Timing Chart
(PWM Output is Ordinary Polarity) ...... 228
INDEX
Other Instructions
Other Instructions ............................................ 429
Outline
Outline of Instructions ........................................ 51
Outline of the Sleep Status .................................. 97
Outline of the Stop Status ................................... 97
Outside Dimension Drawing
Outside Dimension Drawing of LQFP-120 ............. 7
P
PC
Program Counter (DSP-PC) .............................. 364
PCNH
Control/Status Register (PCNH0 to PCNH3,
PCNL0 to PCNL3).............................. 214
PCNL
Control/Status Register (PCNH0 to PCNH3,
PCNL0 to PCNL3).............................. 214
PCSR
PWM Cycle Setting Register
(PCSR0 to PCSR3) ............................. 218
PCTR
PLL Control Register (PCTR) ............................. 82
PDR
Port Data Register (PDR2 to PDRI) ................... 193
PDRR
DMA Request Suppression Register (PDRR)........ 76
PDUT
PWM Duty Setting Register
(PDUT0 to PDUT3) ............................ 219
Peripheral Clock
Blocks Using the Peripheral Clock....................... 87
Pin Arrangement Diagram
Pin Arrangement Diagram of LQFP-120 ................ 8
Pin Control
DMAC Pin Control Register (DATCR).............. 316
External Pin Control Register 0 (EPCR0) ........... 129
External Pin Control Register 1 (EPCR1) ........... 131
Pin Functions
Explanations of the Pin Functions.......................... 9
Pin Status
Pin Status .......................................................... 21
Pin Status in Each CPU State ............................ 403
Terms Used in the Pin Status List ...................... 402
Pin Treatment
Pin Treatment .................................................... 18
Placing a Stack
Placing a Stack in a Little Endian Area .............. 411
Placing Initial Valued Variables
Placing Initial Valued Variables ........................ 410
PLL
Notes on During Operation of PLL Clock
Mode ................................................... 20
PLL Clock
Example of PLL Clock Setting.............................94
PLL Clock Mode
Notes on During Operation of PLL Clock
Mode....................................................20
PLL Control Register
PLL Control Register (PCTR)..............................82
Port Data Register
Port Data Register (PDR2 to PDRI)....................193
Port Direction Register
Port Direction Register (DDR2 to DDRI)............194
Power-on Reset
Power-on Reset ..................................................21
Power-supply Voltage
Handling when the Power-supply Voltage is Unstable
or the Power Supply is Intercepted ..........21
PPG Timer
Registers of the PPG Timer ...............................213
Precaution
Precaution on Clock Doubler Function
ON/OFF ...............................................93
Priority
Priority Judgment .............................................260
Priority of Channels ..........................................330
Priority of EIT Source Received and Masking
of Other Sources....................................66
Processing
Processing of INT Instruction ..............................69
Processing of INTE Instruction ............................69
Processing of RETI Instruction ............................70
Processing of Step Trace Trap..............................69
Processing of Undefined Instruction
Exception..............................................70
Processing of User Interrupt/NMI ........................68
Program
Causes of Reset Delays Other than Programs ........84
Example of DSP Program..................................386
Program Access
Program Access..................................................48
Program Counter
Program Counter (DSP-PC)...............................364
Program Specifications
Program Specifications for External Bus
Operations ..........................................188
Program Status Register
Program Status Register (PS) ...............................43
Protection Function
Converted Data Protection Function ...................281
PS
Program Status Register (PS) ...............................43
PTMR
PWM Timer Register (PTMR0 to PTMR3).........220
447
INDEX
PWM Cycle Setting Register
PWM Cycle Setting Register
(PCSR0 to PCSR3).............................. 218
PWM Duty Setting Register
PWM Duty Setting Register
(PDUT0 to PDUT3) ............................ 219
PWM Mode Timing
PWM Mode Timing Charts ............................... 225
PWM Output
Example of Setting PWM Output
to All-"H" Level.................................. 229
PWM Output Method
All-L or All-H PWM Output Method ................. 228
PWM Timer
Activating Multiple PWM Timer Channels
by Software ........................................ 230
Activating Multiple PWM Timer Channels
Using the 16-bit Reload Timer.............. 230
Block Diagram of the Entire PWM Timer........... 211
Block Diagram of the PWM Timer
for One Channel .................................. 212
Features of the PWM Timer .............................. 210
PWM Timer Interrupt Resources
PWM Timer Interrupt Resources and Timing Chart
(PWM Output is Ordinary Polarity) ...... 228
PWM Timer Register
PWM Timer Register (PTMR0 to PTMR3)......... 220
R
RAM
Y-RAM Expansion Configuration...................... 383
Y-RAM Expansion Mode ................................. 384
RAS
CAS before RAS (CBR) Refresh ....................... 184
Read Cycle Timings
Read Cycle Timings in Each Mode .................... 160
Read Cycle Timings of the Hyper DRAM
Interface ............................................. 181
Read Cycle Timings of the Ordinary DRAM
Interface ............................................. 167
Read Cycle Timings of the Single DRAM
Interface ............................................. 178
Reading
Reading the I/O Mapping .................................. 392
Reading the Instruction List............................... 416
Read-write Cycle Timings
Read-write Cycle Timings................................. 164
Recovery Operation
Recovery Operations from STOP Status ............. 246
Reference Drawing
Reference Drawing of the Clock System............... 95
Refresh
Automatic Wait Cycle for CBR Refresh ............. 185
CAS before RAS (CBR) Refresh ....................... 184
448
DRAM Refresh................................................ 156
Self-Refresh .................................................... 185
Refresh Control Register
Refresh Control Register (RFCR) ...................... 127
Register
16-bit Timer Register (TMR) ............................ 204
16-bit Timer Register (TMRLR)........................ 204
Area Mode Register 0 (AMD0) ......................... 118
Area Mode Register 1 (AMD1) ......................... 120
Area Mode Register 32 (AMD32) ..................... 121
Area Mode Register 4 (AMD4) ......................... 122
Area Mode Register 5 (AMD5) ......................... 123
Area Selection Register (ASR) and
Area Mask Register (AMR) ................. 115
Bus Interface Registers ..................................... 114
Control Registers ............................................. 265
Control Status Register (ADCS) ........................ 273
Control Status Register (TMCSR) ..................... 202
Control/Status Register (DSP-CSR) ................... 361
Control/Status Register (PCNH0 to PCNH3,
PCNL0 to PCNL3).............................. 214
Data Register (ADCR) ..................................... 278
Data Register for 0-detection (BSD0) ................ 343
Data Register for 1-detection (BSD1) ................ 343
Data Register for Change Point Detection
(BSDC).............................................. 344
Dedicated Registers............................................ 40
Delay Register (DSP-LY) ................................. 365
Delayed Interrupt Control Register (DICR) ........ 251
Detection Result Register (BSRR) ..................... 344
DMA Request Suppression Register (PDRR) ....... 76
DMAC Control/Status Register (DACSR).......... 314
DMAC Pin Control Register (DATCR).............. 316
DRAM Control Registers 4 and 5
(DMCR4 and DMCR5) ....................... 124
DRAM Signal Control Register (DSCR) ............ 132
DSP Registers.................................................. 352
ENable Interrupt Request Register (ENIR) ......... 240
External Interrupt Request Register (EIRR) ........ 241
External LeVel Register (ELVR)....................... 242
External Pin Control Register 0 (EPCR0) ........... 129
External Pin Control Register 1 (EPCR1) ........... 131
Gear Control Register (GCR) .............................. 78
General Control Register 1 (GCN1) ................... 221
General Control Register 2 (GCR2) ................... 224
General-purpose Registers .................................. 46
Hold Request Cancel Request Level Setting Register
(HRCL) ............................................. 259
I/O Port Registers ............................................ 192
Instruction Cache Control Register (ICHCR) ........ 33
Interrupt Control Register (ICR).......................... 60
Interrupt Control Register (ICR00 to ICR47) ...... 258
Interrupt Level Mask Register (ILM) ................... 59
Little Endian Register (LER)............................. 133
Mapping of the Interrupt Control Register
(ICR) ................................................... 60
INDEX
Mode Register (MODR) ................................... 106
Notes on Mode Register (MODR) Write ............ 107
Offset Address Initial Value Setting Register
(OFAS) .............................................. 353
Offset Control Setting Register (OFSC) ............. 355
Offset Data Register (OFSD) ............................ 360
Offset Register (OFFSS)................................... 357
PLL Control Register (PCTR) ............................. 82
Port Data Register (PDR2 to PDRI) ................... 193
Port Direction Register (DDR2 to DDRI) ........... 194
Program Status Register (PS) .............................. 43
PWM Cycle Setting Register
(PCSR0 to PCSR3) ............................. 218
PWM Duty Setting Register
(PDUT0 to PDUT3) ............................ 219
PWM Timer Register (PTMR0 to PTMR3) ........ 220
Refresh Control Register (RFCR) ...................... 127
Registers of the 16-bit Reload Timer.................. 201
Registers of the A/D Converter.......................... 272
Registers of the Bit Search Module .................... 342
Registers of the Clock Generator ......................... 72
Registers of the Delayed Interrupt Module ......... 250
Registers of the DMA Controller ....................... 312
Registers of the External Interrupt/NMI Control
Section............................................... 239
Registers of the Interrupt Controller................... 256
Registers of the PPG Timer............................... 213
Registers of the U-TIMER ................................ 232
Reload Register: UTIMR (Reload Register)........ 233
Reset Source Register (RSRR) and Watchdog Cycle
Control Register (WTCR) ...................... 74
Serial Control Register (SCR0 to SCR2) ............ 291
Serial Input Data Register (SIDR0 to SIDR2) and
Serial Output Data Register
(SODR0 to SODR2)............................ 294
Serial Mode Register (SMR0 to SMR2) ............. 289
Serial Status Register (SSR).............................. 295
Software Trigger Register (STRG) .................... 340
Standby Control Register (STCR)........................ 99
Store Address Initial Value Setting Register
(STRS)............................................... 354
Table Base Register (TBR) ................................. 63
Timebase Timer Clear Register (CTBR)............... 77
Transfer to DMAC Internal Register .................. 331
UART Registers .............................................. 288
U-TIMER Control Register: UTIMC
(U-TIMER Control Register) ............... 233
U-TIMER Value Register: UTIM (U-TIMER).... 233
Variable Monitor Register
(DSP-OT0 to DSP-OT3)...................... 366
Watchdog Reset Defer Register (WPR)................ 81
Y-RAM Bank Control Register (Y-BANKC)...... 358
Relationships
Relationships between Data Bus Widths and
Control Signals ........................... 134, 135
Release
Release of Bus Privilege....................................186
Release of Interrupt Resource ............................262
Reload Register
Reload Register: UTIMR (Reload Register) ........233
Reload Timer
Activating Multiple PWM Timer Channels
Using the 16-bit Reload Timer ..............230
Block Diagram of the 16-bit Reload Timer..........200
Registers of the 16-bit Reload Timer ..................201
Reload Values
Examples of Setting Baud Rates and
U-TIMER Reload Values .....................307
Reset
Block Diagram of the Reset Source Hold
Circuit ..................................................88
Causes of Reset Delays Other than Programs ........84
Initialization by Reset .........................................71
Note on Using External Reset Input......................20
Power-on Reset ..................................................21
Reset Defer Method ............................................84
Reset Sequence ..................................................71
Reset Source Register (RSRR) and Watchdog Cycle
Control Register (WTCR).......................74
Reset Sources .....................................................71
Setting the Reset Source Hold Function ................89
Watchdog Reset Defer Register (WPR) ................81
Reset Source Register
Reset Source Register (RSRR) and Watchdog Cycle
Control Register (WTCR).......................74
Resource
Resource Instructions ........................................434
Resource Interrupt Request
Using a Resource Interrupt Request as a DMA
Transfer Request..................................330
Restore
Notes If Restoring from Clock Generation STOP
Status Performed Using an External
Interrupt..............................................245
Save/Restore Processing....................................346
Restriction
Restriction on Section Type ...............................413
Restrictions on Standby Status .............................98
Result Transfer Processing
Result Transfer Processing ................................376
RETI
Processing of RETI Instruction ............................70
Return
Return from EIT .................................................57
Return from Standby Mode (Stop or Sleep).........263
Returning from the Sleep Status .........................103
Returning from the Stop Status ..................101, 243
RFCR
Refresh Control Register (RFCR).......................127
449
INDEX
Row Address
Row Address and Column Address .................... 151
RSRR
Reset Source Register (RSRR) and Watchdog Cycle
Control Register (WTCR) ...................... 74
RSTX Pin
Treatment of RSTX Pin ...................................... 21
S
Sample Assembler Source
Sample Assembler Source................................... 95
Sample Program
Sample Program for External Bus Operations ..... 189
Save
Save/Restore Processing ................................... 346
SCR
Serial Control Register (SCR0 to SCR2)............. 291
Second Descriptor Word
Second Descriptor Word ................................... 320
Section
Section ............................................................ 412
Section Type
Restriction on Section Type............................... 413
Selection
Selection of External Pin Function
(I/O Port or Control Pin) ...................... 195
Self-Refresh
Self-Refresh..................................................... 185
Sensing and Transfer Mode
Combinations of Sensing and Transfer Mode ...... 323
Serial Control Register
Serial Control Register (SCR0 to SCR2)............. 291
Serial Input Data Register
Serial Input Data Register (SIDR0 to SIDR2) and
Serial Output Data Register
(SODR0 to SODR2) ............................ 294
Serial Mode Register
Serial Mode Register (SMR0 to SMR2).............. 289
Serial Output Data Register
Serial Input Data Register (SIDR0 to SIDR2) and
Serial Output Data Register
(SODR0 to SODR2) ............................ 294
Serial Status Register
Serial Status Register (SSR) .............................. 295
Setting
Setting the DMA Suppression Function ................ 90
Setting the Gear Ratio......................................... 86
Setting the Reset Source Hold Function................ 89
Shift
Shift Instructions .............................................. 424
450
SIDR
Serial Input Data Register (SIDR0 to SIDR2) and
Serial Output Data Register
(SODR0 to SODR2)............................ 294
Simple DSP
Sum-of-products Macro (Simple DSP)................... 3
Simulator
Simulator Debugger ......................................... 414
Single DRAM Interface
Read Cycle Timings of the Single DRAM
Interface............................................. 178
Single DRAM Interface Timings ....................... 180
Write Cycle Timings of the Single DRAM
Interface............................................. 179
Single/Block Transfer
Single/Block Transfer Mode ............................. 321
Sleep
Block Diagram of the Sleep Control Section....... 102
Changing to the Sleep Status ............................. 102
Outline of the Sleep Status.................................. 97
Return from Standby Mode (Stop or Sleep) ........ 263
Returning from the Sleep Status ........................ 103
Sleep Mode
DMA Transfer Operation in Sleep Mode............ 331
SMR
Serial Mode Register (SMR0 to SMR2) ............. 289
SODR
Serial Input Data Register (SIDR0 to SIDR2) and
Serial Output Data Register
(SODR0 to SODR2)............................ 294
Software
Activating Multiple PWM Timer Channels
by Software ........................................ 230
Operation of DMA Controller Software Trigger
Circuit ............................................... 340
Software Trigger Register (STRG) .................... 340
Software Trigger Register
Software Trigger Register (STRG) .................... 340
Source Oscillation
Note on Source Oscillation Input ......................... 21
SSP
System Stack Pointer (SSP) ................................ 61
SSR
Serial Status Register (SSR).............................. 295
Standby Control Register
Standby Control Register (STCR)........................ 99
Standby Mode
Return from Standby Mode (Stop or Sleep) ........ 263
Standby Status
Restrictions on Standby Status ............................ 98
State
Pin Status in Each CPU State ............................ 403
Status
Cache Status in Each Operation Mode ................. 35
INDEX
Changing to the Sleep Status ............................. 102
Changing to the Stop Status .............................. 100
Control Status Register (ADCS) ........................ 273
Control Status Register (TMCSR) ..................... 202
Control/Status Register (DSP-CSR) ................... 361
Control/Status Register (PCNH0 to PCNH3,
PCNL0 to PCNL3).............................. 214
Counter Operation Statuses ............................... 207
DMAC Control/Status Register (DACSR) .......... 314
Notes If Restoring from Clock Generation STOP
Status Performed Using an External
Interrupt ............................................. 245
Outline of the Sleep Status .................................. 97
Outline of the Stop Status ................................... 97
Pin Status .......................................................... 21
Pin Status in Each CPU State ............................ 403
Program Status Register (PS) .............................. 43
Recovery Operations from STOP Status............. 246
Restrictions on Standby Status ............................ 98
Returning from the Sleep Status ........................ 103
Returning from the Stop Status.................. 101, 243
Serial Status Register (SSR).............................. 295
Status Transition in Low-power Consumption
Mode ................................................. 104
Terms Used in the Pin Status List ...................... 402
Status Transition
Status Transition in Low-power Consumption
Mode ................................................. 104
STCR
Standby Control Register (STCR)........................ 99
Step Trace Trap
Processing of Step Trace Trap ............................. 69
Step Transfer
Step Transfer (Clock Doubler, Internal Descriptor,
Block Size=1)..................................... 324
Step-synchronous
Transfer Data Formats in Asynchronous
(Step-synchronous) Modes................... 298
Stop
Block Diagram of the Stop Control Section ........ 100
Changing to the Stop Status .............................. 100
Notes If Restoring from Clock Generation STOP
Status Performed Using an External
Interrupt ............................................. 245
Outline of the Stop Status ................................... 97
Recovery Operations from STOP Status............. 246
Return from Standby Mode (Stop or Sleep) ........ 263
Returning from the Stop Status.................. 101, 243
Stopping a Transfer
Stopping a Transfer in Continuous Transfer Mode
(If Both Addresses Change),
16/8-bit Data ...................................... 337
Stopping a Transfer in Continuous Transfer Mode
(If One of Addresses is Fixed),
16/8-bit Data ...................................... 336
Store Address Initial Value Setting Register
Store Address Initial Value Setting Register
(STRS) ...............................................354
STR
STR Instruction (Transfer Instruction) ................370
STRG
Software Trigger Register (STRG) .....................340
STRS
Store Address Initial Value Setting Register
(STRS) ...............................................354
Structure
Structure of the Internal Architecture....................27
Structure Assignment
Structure Assignment ........................................410
Subtraction
Addition and Subtraction Instructions .................422
Sum-of-products Macro
Sum-of-products Macro (Simple DSP) ...................3
Suppressing
Suppressing DMA Transfer when a High-Priority
Interrupt Occurs...................................330
Symbols
Addressing Mode Symbols ................................418
Symbols Used in the Timing Charts ...................332
Synchronous Mode
Transfer Data Format in CLK Synchronous
Mode..................................................300
System Stack Pointer
System Stack Pointer (SSP) .................................61
T
Table Base Register
Table Base Register (TBR) ..................................63
TBR
Table Base Register (TBR) ..................................63
Terms
Terms Used in the Pin Status List.......................402
Third Descriptor Word
Third Descriptor Word ......................................320
Timebase Timer
Timebase Timer .................................................84
Timebase Timer Clear Register (CTBR) ...............77
Timebase Timer Clear Register
Timebase Timer Clear Register (CTBR) ...............77
Timing Chart
PWM Timer Interrupt Resources and Timing Chart
(PWM Output is Ordinary Polarity) .......228
Symbols Used in the Timing Charts ...................332
TMCSR
Control Status Register (TMCSR) ......................202
TMR
16-bit Timer Register (TMR) .............................204
451
INDEX
TMRLR
16-bit Timer Register (TMRLR) ........................ 204
Transfer
Burst Transfer
(Clock Doubler, Internal Descriptor) ..... 326
Burst Transfer Mode......................................... 322
Combinations of Sensing and Transfer Mode ...... 323
Continuous Transfer ......................................... 331
Continuous Transfer (Clock Doubler, Internal
Descriptor) ......................................... 325
Data Transfer Section, 16/8-bit Data .................. 335
DMA Transfer when Y-RAM Bank is
Disabled ............................................. 379
DMA Transfer when Y-RAM Bank is
Enabled .............................................. 381
Example of Transfer ......................................... 385
Result Transfer Processing ................................ 376
Single/Block Transfer Mode.............................. 321
Step Transfer (Clock Doubler, Internal Descriptor,
Block Size=1) ..................................... 324
Stopping a Transfer in Continuous Transfer Mode
(If Both Addresses Change),
16/8-bit Data....................................... 337
Stopping a Transfer in Continuous Transfer Mode
(If One of Addresses is Fixed),
16/8-bit Data....................................... 336
Suppressing DMA Transfer when a High-Priority
Interrupt Occurs .................................. 330
Transfer to DMAC Internal Register .................. 331
Transfer Acknowledge Signal Output
Transfer Acknowledge Signal Output................. 329
Transfer Data Format
Transfer Data Format in CLK Synchronous
Mode ................................................. 300
Transfer Data Formats in Asynchronous
(Step-synchronous) Modes ................... 298
Transfer End Operation
Transfer End Operation
(If Both Addresses Change).................. 339
Transfer End Operation
(If One of Addresses is Fixed) .............. 338
Transfer End Signal Output
Transfer End Signal Output ............................... 329
Transfer Instruction
Immediate Value Set and 16/32-bit Immediate Value
Transfer Instructions............................ 425
Inter-register Transfer Instructions ..................... 426
STR Instruction (Transfer Instruction)................ 370
Transfer Operation
DMA Transfer Operation in Sleep Mode ............ 331
Transfer Request
DMA Transfer Request Resources ..................... 331
Using a Resource Interrupt Request as a DMA
Transfer Request ................................. 330
452
Treatment
Treatment of RSTX Pin ...................................... 21
U
UART
Example of UART Application ......................... 305
Features of UART............................................ 286
Notes on UART Use ........................................ 305
UART Block Diagram...................................... 287
UART Clock Selection ..................................... 297
UART Flags and Interrupts ............................... 302
UART Interrupts and Flag Setting Timings: Reception
in Mode 0........................................... 302
UART Interrupts and Flag Setting Timings: Reception
in Mode 1........................................... 303
UART Interrupts and Flag Setting Timings: Reception
in Mode 2........................................... 303
UART Interrupts and Flag Setting Timings:
Transmission in Modes 0 to 2............... 304
UART Operation Modes................................... 297
UART Registers .............................................. 288
Undefined Instruction Exception
Processing of Undefined Instruction
Exception ............................................. 70
Underflow Operation
Underflow Operation........................................ 205
Using a Resource Interrupt Request
Using a Resource Interrupt Request as a DMA
Transfer Request................................. 330
Using Character Array Operation Functions
Using Character Array Operation Functions on Other
than Character-Type Arrays ................. 411
Using Double or Long-double Variables
Using Double or Long-double Variables ............ 411
UTIM
U-TIMER Value Register: UTIM (U-TIMER).... 233
UTIMC
U-TIMER Control Register: UTIMC
(U-TIMER Control Register) ............... 233
U-TIMER
Block Diagram of the U-TIMER ....................... 232
Examples of Setting Baud Rates and
U-TIMER Reload Values..................... 307
Registers of the U-TIMER ................................ 232
U-TIMER Control Register: UTIMC
(U-TIMER Control Register) ............... 233
U-TIMER Value Register: UTIM (U-TIMER).... 233
U-TIMER Control Register
U-TIMER Control Register: UTIMC
(U-TIMER Control Register) ............... 233
U-TIMER Value Register
U-TIMER Value Register: UTIM (U-TIMER).... 233
UTIMR
Reload Register: UTIMR (Reload Register) ....... 233
INDEX
V
Variable
Placing Initial Valued Variables ........................ 410
Using Double or Long-double Variables ............ 411
Variable Monitor Output
Variable Monitor Output................................... 378
Variable Monitor Register
Variable Monitor Register
(DSP-OT0 to DSP-OT3)...................... 366
Vector Table
EIT Vector Table ............................................... 64
Y-RAM Bank Control Register
Y-RAM Bank Control Register (Y-BANKC) ......358
W
Wait Cycle
Wait Cycle ...................................................... 154
Watchdog Control
Block Diagram of the Watchdog Control
Section................................................. 83
Watchdog Cycle Control Register
Reset Source Register (RSRR) and Watchdog Cycle
Control Register (WTCR) ...................... 74
Watchdog Reset Defer Register
Watchdog Reset Defer Register (WPR)................ 81
Watchdog Timer
Watchdog Timer Activation Method .................... 83
Watchdog Timer Function .................................. 20
Word Access
Word Access ................................................... 146
WPR
Watchdog Reset Defer Register (WPR)................ 81
Write Cycle Timings
Write Cycle Timings in Each Mode ................... 162
Write Cycle Timings of the Hyper DRAM
Interface............................................. 182
Write Cycle Timings of the Ordinary DRAM
Interface............................................. 169
Write Cycle Timings of the Single DRAM
Interface............................................. 179
WTCR
Reset Source Register (RSRR) and Watchdog Cycle
Control Register (WTCR) ...................... 74
Y
Y-BANKC
Y-RAM Bank Control Register (Y-BANKC)...... 358
Y-RAM
Y-RAM Expansion Configuration ..................... 383
Y-RAM Expansion Mode ................................. 384
Y-RAM Bank
DMA Transfer when Y-RAM Bank is
Disabled............................................. 379
DMA Transfer when Y-RAM Bank is
Enabled.............................................. 381
453
INDEX
454
CM71-10107-2E
FUJITSU SEMICONDUCTOR • CONTROLLER MANUAL
FR30
32-BIT MICROCONTROLLER
MB91121 Series
HARDWARE MANUAL
August 2006 the second edition
Published
FUJITSU LIMITED
Edited
Business Promotion Dept.
Electronic Devices
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