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FUJITSU SEMICONDUCTOR
CONTROLLER MANUAL
CM71-10116-2E
FR30
32-BIT MICROCONTROLLER
MB91151A Series
HARDWARE MANUAL
FR30
32-BIT MICROCONTROLLER
MB91151A Series
HARDWARE MANUAL
Be sure to refer to the “Check Sheet” for the latest cautions on development.
“Check Sheet” is seen at the following support page
URL : http://www.fujitsu.com/global/services/microelectronics/product/micom/support/index.html
“Check Sheet” lists the minimal requirement items to be checked to prevent problems beforehand in system development.
FUJITSU LIMITED
PREFACE
■ Objectives and Intended Reader
The MB91151A Series, hereafter referred to as MB91151A, is a member of the "32-bit singlechip microcontroller FR30 and has a CPU based on a new RISC architecture at its core. This
microcontroller is suitable for CD and DVD drives.
This manual is for engineers who develop products incorporating the MB91151A. It also
describes the functions and operation of the MB91151A. Read this manual thoroughly. For
details on each instruction, see the Instructions Manual.
■ Trademarks
FR is an abbreviation of FUJITSU RISC controller and a product of FUJITSU LIMITED.
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■ Structure of This Manual
This manual contains 19 chapters and one appendix.
CHAPTER 1 "OVERVIEW OF THE MB91151A"
This chapter provides basic information required to fully understand the MB91151A, such as
a description of MB91151A features, block diagrams, and an outline of functions.
CHAPTER 2 "HANDLING THE DEVICE"
This chapter provides notes on handling the MB91151A.
CHAPTER 3 "MEMORY SPACE, CPU, AND CONTROL UNIT"
This chapter provides basic information regarding the architecture, specifications,
instructions, and other topics, that is required to understand the CPU core functions of the
FR family.
CHAPTER 4 "BUS INTERFACE"
This chapter provides an outline of the bus interface and describes bus operation.
CHAPTER 5 "I/O PORTS"
This chapter describes the overview of the I/O ports and provides the block diagrams of
individual ports. It also describes the register configurations.
CHAPTER 6 "8/16-BIT UP/DOWN COUNTERS/TIMERS"
This chapter describes the overview of the 8/16-bit up/down counters/timers, their block
diagrams, their configurations and functions of the registers, as well as the operation of the
8/16-bit up/down counters/timers.
CHAPTER 7 "16-BIT RELOAD TIMERS"
This chapter describes the overview of the 16-bit reload timer, the configuration and
functions of the timer registers, and the operations of the 16-bit reload timer. The chapter
also provides a block diagram of the 16-bit reload timer.
CHAPTER 8 "PPG TIMERS"
This chapter describes the overview of the PPG timer, register configurations and functions,
and PPG timer operation. The chapter also provides a block diagram of the PPG timer.
CHAPTER 9 "MULTIFUNCTIONAL TIMERS"
This chapter gives an overview of the multifunctional timer, its block diagram, the
configuration and functions of its registers, and its operation.
CHAPTER 10 "EXTERNAL-INTERRUPT CONTROL BLOCK"
This chapter gives an overview of the external-interrupt control block, the structure and
functions of the registers, and the operation of the external-interrupt control block.
CHAPTER 11 "DELAYED-INTERRUPT MODULE"
This chapter gives an overview of the delayed-interrupt module, the structure and functions
of the registers, and the operation of the delayed-interrupt module.
CHAPTER 12 "INTERRUPT CONTROLLER"
This chapter provides an overview of the interrupt controller, its block diagram, the structure
and functions of the registers, the operation of the interrupt controller.
CHAPTER 13 "8/10-BIT A/D CONVERTER"
This chapter provides an overview of the 8/10-bit A/D converter, its block diagram, its pin,
configuration and functions of its registers, and operation of the 8/10-bit A/D converter.
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CHAPTER 14 "8-BIT D/A CONVERTER"
This chapter provides an overview of the 8-bit D/A converter, the block diagram, the
configuration and functions of the registers, and the operation of the 8-bit D/A converter.
CHAPTER 15 "UART"
This chapter describes the overview of the UART, its block diagram, its pin, the configuration
and functions of UART registers, and UART operations.
CHAPTER 16 "DMA CONTROLLER"
This chapter describes the overview of the DMA controller, its block diagram, configuration
and functions of its registers, and its operations.
CHAPTER 17 "BIT-SEARCH MODULE"
This chapter describes the overview of the bit-search module, the register configuration and
functions, and the operation of the bit-search module.
CHAPTER 18 "PERIPHERAL STOP CONTROL"
This chapter provides an overview of peripheral stop control and explains the configuration
and the function of registers.
CHAPTER 19 "SERIAL - START"
This chapter provides an outline of the serial-start and describes the communication mode.
APPENDIX
These appendixes provide the I/O map, notes on using the little-endian area, and instruction
lists. They also explain interrupt vectors and the pin status in each CPU state.
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• The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales
representatives before ordering.
• The information, such as descriptions of function and application circuit examples, in this document are presented solely for the
purpose of reference to show examples of operations and uses of FUJITSU semiconductor device; FUJITSU does not warrant
proper operation of the device with respect to use based on such information. When you develop equipment incorporating the
device based on such information, you must assume any responsibility arising out of such use of the information. FUJITSU
assumes no liability for any damages whatsoever arising out of the use of the information.
• Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license
of the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of FUJITSU or any
third party or does FUJITSU warrant non-infringement of any third-party's intellectual property right or other right by using such
information. FUJITSU assumes no liability for any infringement of the intellectual property rights or other rights of third parties
which would result from the use of information contained herein.
• The products described in this document are designed, developed and manufactured as contemplated for general use, including
without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed
and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured,
could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss
(i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life
support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible
repeater and artificial satellite). Please note that FUJITSU will not be liable against you and/or any third party for any claims or
damages arising in connection with above-mentioned uses of the products.
• Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such
failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and
prevention of over-current levels and other abnormal operating conditions.
• If any products described in this document represent goods or technologies subject to certain restrictions on export under the
Foreign Exchange and Foreign Trade Law of Japan, the prior authorization by Japanese government will be required for export
of those products from Japan.
Copyright ©2002-2006 FUJITSU LIMITED Printed in Japan
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READING THIS MANUAL
■ Details Regarding the Manual Format
An explanation of the most important terms in this manual is given in the table below.
Term
Meaning
I-bus
16-bit bus for internal instructions. The FR family employs internal Harvard
architecture; there are independent buses for instructions and data. A bus
converter is connected to the I-bus.
D-bus
Internal 32-bit data bus. An internal resource is connected to the D-bus.
C-bus
Internal multiplex bus. The C-bus is connected to both the I-bus and D-bus
through a switch. An external interface module is connected to the C-bus. On
external data buses, data and instructions are multiplexed.
R-bus
Internal 16-bit data bus. The R-bus is connected to the D-bus via an adapter.
Various I/O devices, a clock generator, and an interrupt controller are connected
to the R-bus. The R-bus has a bandwidth of 16 bits over which addresses and
data are multiplexed; CPU access time of these resources is several cycles.
E-unit
Arithmetic execution unit
φ
System clock. It provides the clock signals output to each of the built-in
resources connected to the R-bus from the clock generator. The maximum clock
speed (cycle) is identical to the original clock oscillation. The clock cycle can be
divided by 1, 1/2, 1/4, and 1/8 (or 1/2, 1/4, 1/8, and 1/16) depending on the
setting of the PCK1 and PCK0 bits of the GCR register in the clock generator.
θ
System clock. Clock used by the CPU and resources connected to a bus other
than the R-bus. The maximum clock speed (cycle) is identical to the original
clock oscillation. The clock cycle can be divided by 1, 1/2, 1/4, and 1/8 (or 1/2, 1/
4, 1/8, and 1/16) depending on the setting of the CCK1 and CCK0 bits of the
GCR register in the clock generator.
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CONTENTS
CHAPTER 1
1.1
1.2
1.3
1.4
1.5
1.6
MB91151A Features .............................................................................................................................. 2
Block Diagrams ...................................................................................................................................... 5
Package Dimensions ............................................................................................................................. 6
Pin Assignments .................................................................................................................................... 8
Pin Functions ....................................................................................................................................... 11
I/O Circuit Types .................................................................................................................................. 18
CHAPTER 2
2.1
2.2
2.3
OVERVIEW OF THE MB91151A .................................................................. 1
HANDLING THE DEVICE ........................................................................... 21
Notes on Handling Devices ................................................................................................................. 22
Notes on Using Devices ...................................................................................................................... 24
Power-On ............................................................................................................................................. 25
CHAPTER 3
MEMORY SPACE, CPU, AND CONTROL UNIT ........................................ 27
3.1 Memory Space ..................................................................................................................................... 28
3.2 CPU Architecture ................................................................................................................................. 30
3.3 Instruction Cache ................................................................................................................................. 33
3.4 Programming Model ............................................................................................................................ 40
3.5 Data Structure ...................................................................................................................................... 47
3.6 Word Alignment ................................................................................................................................... 48
3.7 Special Memory Areas ......................................................................................................................... 49
3.8 Overview of Instructions ...................................................................................................................... 50
3.8.1 Branch Instructions with Delay Slots .............................................................................................. 52
3.8.2 Branch Instructions without a Delay Slot ........................................................................................ 55
3.9 EIT (Exception, Interrupt, and Trap) .................................................................................................... 56
3.9.1 Interrupt Level ................................................................................................................................. 57
3.9.2 Interrupt Stack Operation ............................................................................................................... 58
3.9.3 EIT Vector Table ............................................................................................................................. 59
3.9.4 Multiple EIT Processing .................................................................................................................. 61
3.9.5 EIT Operation ................................................................................................................................. 63
3.10 Reset Sequence .................................................................................................................................. 67
3.11 Operation Mode ................................................................................................................................... 68
3.12 Clock Generator (Low-Power Consumption Mechanism) .................................................................... 71
3.12.1 Reset Source Register (RSRR) and Watchdog Cycle Control Register (WTCR) .......................... 73
3.12.2 Standby Control Register (STCR) .................................................................................................. 75
3.12.3 Timebase Timer Clear Register (CTBR) ........................................................................................ 76
3.12.4 Gear Control Register (GCR) ......................................................................................................... 77
3.12.5 Watchdog Reset Generation Delay Register (WPR) ...................................................................... 79
3.12.6 DMA Request Suppression Register (PDRR) ................................................................................ 80
3.12.7 PLL Control Register (PCTR) ......................................................................................................... 81
3.12.8 Watchdog Function ......................................................................................................................... 82
3.12.9 Gear Function ................................................................................................................................. 84
3.12.10 Retaining a Reset Source ............................................................................................................... 86
3.12.11 Example of Setting the PLL Clock .................................................................................................. 88
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3.13 Low-Power Consumption Mode ..........................................................................................................
3.13.1 Stop Status ....................................................................................................................................
3.13.2 Sleep Status ..................................................................................................................................
3.13.3 Status Transition of the Low-power Consumption Mode ...............................................................
CHAPTER 4
BUS INTERFACE ..................................................................................... 101
4.1 Outline of Bus Interface ....................................................................................................................
4.2 Block Diagram of the Bus Interface ..................................................................................................
4.3 Registers of the Bus Interface ...........................................................................................................
4.3.1 Area Select Registers (ASR1 to ASR5) and Area Mask Registers (AMR1 to AMR5) .................
4.3.2 Area Mode Register (AMD0) ........................................................................................................
4.3.3 Area Mode Register 1 (AMD1) .....................................................................................................
4.3.4 Area Mode Register 32 (AMD32) .................................................................................................
4.3.5 Area Mode Register 4 (AMD4) .....................................................................................................
4.3.6 Area Mode Register 5 (AMD5) .....................................................................................................
4.3.7 External Pin Control Register 0 (EPCR0) ....................................................................................
4.3.8 External Pin Control Register 1 (EPCR1) ....................................................................................
4.3.9 Little-endian Register (LER) ........................................................................................................
4.4 Bus Operation ...................................................................................................................................
4.4.1 Relationship Between Data Bus Width and Control Signals ........................................................
4.4.2 Bus Access in Big-endian Mode ..................................................................................................
4.4.3 Bus Access in Little-endian Mode ................................................................................................
4.4.4 Comparison of External Access in Big-endian and Little-endian Mode .......................................
4.5 Bus Timing ........................................................................................................................................
4.5.1 Basic Read Cycle ........................................................................................................................
4.5.2 Basic Write Cycle .........................................................................................................................
4.5.3 Read Cycle in Each Mode ...........................................................................................................
4.5.4 Write Cycle in Each Mode ...........................................................................................................
4.5.5 Mixed Read/Write Cycles .............................................................................................................
4.5.6 Automatic Wait Cycle ...................................................................................................................
4.5.7 External Wait Cycle .....................................................................................................................
4.5.8 External Bus Request ..................................................................................................................
4.6 Internal Clock Multiply Operation (Clock Doubler) ............................................................................
4.7 Program Examples for the External Bus ...........................................................................................
CHAPTER 5
91
93
96
99
102
104
105
106
108
110
111
112
113
114
116
117
118
119
120
126
130
135
136
138
140
142
144
145
146
147
148
150
I/O PORTS ................................................................................................ 153
5.1
5.2
5.3
5.4
Overview of I/O Ports ........................................................................................................................
Block Diagram of Basic I/O Port .......................................................................................................
Block Diagram of I/O Ports (Including the Pull-up Resistor) .............................................................
Block Diagram of I/O Ports (Including the Open-Drain Output Function and the Pull-up Resistor)
...........................................................................................................................................................
5.5 Block Diagram of I/O Port (With Open-Drain Output Function) ........................................................
5.6 Port Data Register (PDR2 to PDRL) .................................................................................................
5.7 Data Direction Register (DDR2 to DDRL) .........................................................................................
5.8 Pull-up Resistor Control Register (PCR6 to PCRI) ...........................................................................
5.9 Open-Drain Control Register (OCRH and OCRI) .............................................................................
5.10 Analog Input Control Register (AICR) ...............................................................................................
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154
155
156
157
159
160
161
162
163
164
CHAPTER 6
8/16-BIT UP/DOWN COUNTERS/TIMERS ............................................... 165
6.1 Overview of 8/16-bit Up/Down Counters/Timers ............................................................................... 166
6.2 Block diagram of the 8/16-bit Up/Down Counters/Timers .................................................................. 168
6.3 List of Registers of the 8/16-bit Up/Down Counters/Timers ............................................................... 170
6.3.1 Counter Control Register H/L ch0 (CCRH/CCRL) ........................................................................ 171
6.3.2 Counter Control Register H/L ch1 (CCRH/CCRL) ........................................................................ 175
6.3.3 Counter status register 0/1 (CSR0, CSR1) ................................................................................... 176
6.3.4 Up/down count register 0/1 (UDCR0, UDCR1) ............................................................................ 178
6.3.5 Reload/compare register 0/1 (RCR0, RCR1) ............................................................................... 179
6.4 Selection of Counting Mode ............................................................................................................... 180
6.5 Reload and Compare Functions ........................................................................................................ 183
6.6 Writing data to the up/down count register (UDCR0, UDCR1) .......................................................... 187
CHAPTER 7
16-BIT RELOAD TIMERS ......................................................................... 189
7.1 Overview of 16-bit Reload Timer ....................................................................................................... 190
7.2 Block diagram of a 16-bit Reload Timer ............................................................................................ 191
7.3 Registers of 16-bit Reload Timer ....................................................................................................... 192
7.3.1 Control status register (TMCSR0 to TMCSR3) ............................................................................ 193
7.3.2 16-bit Timer Register (TMR0 to TMR3) and 16-bit Reload Register (TMRLR0 to TMRLR3) ....... 195
7.4 Internal Clock Operation .................................................................................................................... 196
7.5 Underflow Operation .......................................................................................................................... 197
7.6 Counter Operation States .................................................................................................................. 199
CHAPTER 8
PPG TIMERS ............................................................................................. 201
8.1 Overview of PPG Timers ................................................................................................................... 202
8.2 Block Diagram of PPG Timers ........................................................................................................... 203
8.3 Registers of PPG Timers ................................................................................................................... 205
8.3.1 Control status registers (PCNH0 to PCNH5, PCNL0 to PCNH5) ................................................. 207
8.3.2 PWM cycle set register (PCSR0 to PCSR5) ................................................................................ 211
8.3.3 PWM duty set register (PDUT0 to PDUT5) .................................................................................. 212
8.3.4 PWM timer register (PTMR0 to PTMR5) ...................................................................................... 213
8.3.5 General control register 1 (GCN1) ................................................................................................ 214
8.3.6 General control register 2 (GCN2) ................................................................................................ 217
8.4 PWM Operation ................................................................................................................................. 218
8.5 One-shot Operation ........................................................................................................................... 220
8.6 PWM Timer Interrupt Source and Timing Chart ................................................................................ 222
8.7 Activating Multiple Channels by Using the General Control Register (GCN) .................................... 224
CHAPTER 9
MULTIFUNCTIONAL TIMERS .................................................................. 227
9.1 Overview of Multifunctional Timers .................................................................................................... 228
9.2 Block Diagram of the Multifunctional Timer ....................................................................................... 230
9.3 Registers of Multifunctional Timers .................................................................................................... 231
9.3.1 Registers of 16-bit Free-run Timer ............................................................................................... 232
9.3.2 Registers of the Output Compare ................................................................................................. 235
9.3.3 Registers of Input Capture ............................................................................................................ 238
9.4 Operations of Multifunctional Timer ................................................................................................... 240
9.4.1 Operation of 16-bit Free-run Timer ............................................................................................... 241
9.4.2 Operation of 16-bit Output Compare ............................................................................................ 243
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9.4.3
Operation of 16-bit Input Capture ................................................................................................ 246
CHAPTER 10 EXTERNAL-INTERRUPT CONTROL BLOCK ......................................... 249
10.1 Overview of External Interrupt ..........................................................................................................
10.2 External-Interrupt Registers ..............................................................................................................
10.2.1 Enable Interrupt Register (ENIR0, ENIR1) ..................................................................................
10.2.2 External-Interrupt Request Register (EIRR0, EIRR1) ..................................................................
10.2.3 External-Interrupt Level Setting Register (ELVR0, ELVR1: External Level Register) ..................
10.3 External-Interrupt Operation .............................................................................................................
10.4 External-Interrupt Request Level ......................................................................................................
250
251
252
253
254
255
256
CHAPTER 11 DELAYED-INTERRUPT MODULE ........................................................... 257
11.1 Overview of Delayed-Interrupt Module ............................................................................................. 258
11.2 Delayed-Interrupt Control Register (DICR) ....................................................................................... 259
11.3 Operation of Delayed-Interrupt Module ............................................................................................. 260
CHAPTER 12 INTERRUPT CONTROLLER .................................................................... 261
12.1 Overview of Interrupt Controller ........................................................................................................
12.2 Block Diagram of the Interrupt Controller ..........................................................................................
12.3 List of Interrupt Controller Registers .................................................................................................
12.3.1 Interrupt Control Register (ICR00 to ICR47) ................................................................................
12.3.2 Hold-Request Cancellation-Request Level-Set Register (HRCL) ................................................
12.4 Priority Evaluation .............................................................................................................................
12.5 Return from Standby (Stop or Sleep) Mode ......................................................................................
12.6 Hold-Request Cancellation Request .................................................................................................
12.7 Example of Using Hold-Request Cancellation-Request Function (HRCR) .......................................
262
263
264
266
268
269
272
273
274
CHAPTER 13 8/10-BIT A/D CONVERTER ...................................................................... 277
13.1 Overview of the 8/10-bit A/D Converter ............................................................................................
13.2 8/10-bit A/D Converter Block Diagram ..............................................................................................
13.3 8/10-bit A/D Converter Pins ..............................................................................................................
13.4 8/10-bit A/D Converter Registers ......................................................................................................
13.4.1 A/D Control Status Register 1 (ADCS1) ......................................................................................
13.4.2 A/D Control Status Register 0 (ADCS0) ......................................................................................
13.4.3 A/D Data Register (ADCR) ..........................................................................................................
13.5 8/10-bit A/D Converter Interrupt ........................................................................................................
13.6 Operation of the 8/10-bit A/D Converter ...........................................................................................
13.7 A/D Converted Data Preservation Function ......................................................................................
13.8 Notes on Using the 8/10-bit A/D Converter .......................................................................................
278
279
281
283
284
287
290
292
293
295
296
CHAPTER 14 8-BIT D/A CONVERTER ........................................................................... 297
14.1 Overview of the 8-bit D/A Converter .................................................................................................
14.2 8-bit D/A Converter Block Diagram ...................................................................................................
14.3 8-bit D/A Converter Registers ...........................................................................................................
14.3.1 D/A Control Registers (DACR0, DACR1, DACR2) ......................................................................
14.3.2 D/A Data Registers (DADR2, DADR1, DADR0) ..........................................................................
14.4 8-bit D/A Converter Operation ..........................................................................................................
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298
299
300
301
302
303
CHAPTER 15 UART ......................................................................................................... 305
15.1 Overview of the UART ....................................................................................................................... 306
15.2 UART Block Diagram ......................................................................................................................... 308
15.3 UART Pins ......................................................................................................................................... 310
15.4 UART Registers ................................................................................................................................. 313
15.4.1 Control register (SCR0 to SCR3) ................................................................................................. 314
15.4.2 Mode register (SMR0 to SMR3) ................................................................................................... 316
15.4.3 Status register (SSR0 to SSR3) ................................................................................................... 318
15.4.4 Input-data register (SIDR0 to SIDR3), Output-data register (SODR0 to SODR3) ........................ 320
15.4.5 Communication prescaler control register (CDCR) ...................................................................... 322
15.5 Interrupts ........................................................................................................................................... 324
15.6 Receive-Interrupt Generation and Flag Set Timing ........................................................................... 326
15.7 Send-Interrupt Generation and Flag Set Timing ................................................................................ 327
15.8 Baud Rate .......................................................................................................................................... 328
15.8.1 Baud Rate Based on the Dedicated Baud-Rate Generator .......................................................... 330
15.8.2 Baud Rate Based on the Internal Timer (16-bit Reload Timer 0) ................................................. 333
15.8.3 Baud Rate Based on the External clock ....................................................................................... 335
15.9 UART Operations .............................................................................................................................. 336
15.9.1 Operation in asynchronous mode (operation modes 0, 1) ........................................................... 338
15.9.2 Operation in synchronous mode (operation mode 2) ................................................................... 341
15.9.3 Bidirectional communication function (normal mode) ................................................................... 343
15.9.4 Master/slave-type communication function (multiprocessor mode) .............................................. 345
15.10 Notes on Using UART ....................................................................................................................... 347
CHAPTER 16 DMA CONTROLLER ................................................................................. 349
16.1 Overview of the DMA Controller ........................................................................................................ 350
16.2 Block Diagram of the DMA Controller ................................................................................................ 351
16.3 Registers of the DMA Controller ........................................................................................................ 352
16.3.1 DMAC parameter descriptor pointer (DPDP) ............................................................................... 353
16.3.2 MAC control status register (DACSR) .......................................................................................... 354
16.3.3 DMAC pin control register (DATCR) ............................................................................................. 356
16.3.4 Register of the descriptor in RAM ................................................................................................. 358
16.4 Transfer Modes Supported by the DMA Controller ............................................................................ 361
16.4.1 Step Transfer (Single/Block Transfer) .......................................................................................... 364
16.4.2 Continuous Transfer ..................................................................................................................... 365
16.4.3 Burst Transfer ............................................................................................................................... 366
16.4.4 Differences Because of DREQ Sense Mode ................................................................................ 367
16.5 Transfer-Acceptance Signal Output and Transfer-End Signal Output ............................................... 369
16.6 Notes on the DMA Controller ............................................................................................................. 370
16.7 Timing Charts for the DMA Controller ................................................................................................ 372
16.7.1 Timing charts for the descriptor access section ........................................................................... 373
16.7.2 Timing charts for the data transfer section ................................................................................... 375
16.7.3 Timing charts for transfer termination in continuous transfer mode ............................................. 376
16.7.4 Timing charts for the transfer termination operation ..................................................................... 378
CHAPTER 17 BIT-SEARCH MODULE ............................................................................ 381
17.1 Overview of the Bit-Search Module ................................................................................................... 382
17.2 Registers of the Bit-Search Module ................................................................................................... 383
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17.3 Operation of the Bit-Search Module .................................................................................................. 385
CHAPTER 18 PERIPHERAL STOP CONTROL .............................................................. 387
18.1 Overview of Peripheral Stop Control ................................................................................................. 388
18.2 Peripheral Stop Control Registers .................................................................................................... 389
CHAPTER 19 SERIAL - START ...................................................................................... 393
19.1 Outline of Serial-Start and How to Set .............................................................................................. 394
19.2 Communication Mode of Serial-Start ................................................................................................ 395
APPENDIX .......................................................................................................................... 409
APPENDIX A I/O Map ................................................................................................................................
APPENDIX B Interrupt Vectors ...................................................................................................................
APPENDIX C Pin Status in Each CPU State ..............................................................................................
APPENDIX D Notes on Using the Little-Endian Area .................................................................................
D.1 C Compiler (fcc911) .......................................................................................................................
D.2 Assembler (fasm911) .....................................................................................................................
D.3 Linker (flnk911) ...............................................................................................................................
D.4 Debuggers (sim911, eml911, and mon911) ...................................................................................
APPENDIX E Instruction Lists ....................................................................................................................
410
417
421
428
429
432
433
434
435
INDEX .................................................................................................................................. 453
xii
Main changes in this edition
Page
Changes (For details, refer to main body.)
-
Register names are changed.
(analog input permission register (AICK) → analog input control register (AICR))
(analog input control register of port-K (AICK) → analog input control register (AICR))
(Enable Interrupt Register (ENIRn) → Enable Interrupt Register (ENIR0, ENIR1))
(External-Interrupt Request Register (EIRRn) → External-Interrupt Request Register (EIRR0, EIRR1))
-
Pin names are changed.
(DREQn → DREQ0 to DREQ2)
(DACKn → DACK0 to DACK2)
(DACKn → DREQ0 to DREQ2)
(WRn → WR0, WR1)
(DEOPn → DEOP0 to DEOP2)
5
Figure 1.2-1 Block Diagram (MB91V151A and MB91151A) is changed.
12
Table 1.5-1 Functions of the MB91151A Pins (2 / 7) Pin No.55 is changed.
(External reset output → External reset input)
17
Table 1.5-1 Functions of the MB91151A Pins (7 / 7) Pin No.132 to 139 is changed.
(AIC register → AICR register)
19
Classification N in Table 1.6-1 I/O Circuit Types is changed.
(AIC → AICR)
23
❍ Crystal oscillation circuit is changed.
(Please ask the crystal maker to evaluate the oscillational characteristics of the crystal and this device. is
added.)
24
■ Watchdog Timer Function is added.
25
❍ Treatment of unstable power supply voltage or when shutting off power supply is added.
29
Figure 3.1-1 Memory Map for MB91V151A and MB91151A is changed.
34
[bit7 to bit4] SBV3 to SBV0: Sub-block valid is changed.
(If SBV* = 1, → If sub-block valid is set to "1",)
79
[bit7 to bit0] D7 to D0 is changed.
(The flip-flop is automatically cleared when it is in stop or sleep status.Therefore, if these conditions occur,
watchdog reset is automatically delayed. is deleted.)
82
Figure 3.12-3 Block Diagram of the Watchdog Control Block is changed.
(clr → clear)
(WTx → WT1,WT0)
83
■ Causes of Reset Delays Other than Programs is added.
84
Figure 3.12-6 Block Diagram of the Gear Control Block is changed.
88
Figure 3.12-9 Example of Setting the PLL Clock is changed.
(DBLACK → DBLAK)
88
Notes: is changed.
(For a restart of PLL VC0, → For a restart of PLL,)
xiii
Page
Changes (For details, refer to main body.)
90
■ Example of the Related Assembler Source Code (Example of Switching to the PLL System) is changed.
(DBLACK → DBLAK)
(PTCR → PCTR)
135
■ Wait Cycle is changed.
(by the WTC bits → the WTC2 to WTC0 bits)
139
[Operation] is changed.
(High-Z. → high impedance (Hi-Z).)
145
[Operation] is changed.
(the WTC bits → the WTC2 to WTC0 bits)
146
[Operation] is changed.
(the WTC bits → the WTC2 to WTC0 bits)
(The RDY is detected in an automatic wait cycle. → The RDY is detected in the last cycle of an automatic
wait.)
168
Figure 6.2-1 Block Diagram of the 8/16-bit Up/Down Counters/Timers (Channel 0) is changed.
169
Figure 6.2-2 Block Diagram of the 8/16-bit Up/Down Counters/Timers (Channel 1) is changed.
170
Figure 6.3-1 List of Registers of the 8/16-bit Up/Down Counters/Timers is changed.
(D17 D16 D15 D14 D13 D12 D11 D10 → D07 D06 D05 D04 D03 D02 D01 D00)
178
■ Up/Down Count Register 0/1 (UDCR0, UDCR1) is changed.
(D17 D16 D15 D14 D13 D12 D11 D10 → D07 D06 D05 D04 D03 D02 D01 D00)
179
■ Reload/Compare Register 0/1 (RCR0, RCR1) is changed.
(D17 D16 D15 D14 D13 D12 D11 D10 → D07 D06 D05 D04 D03 D02 D01 D00)
182
❍ Multiply-by-4 mode is changed.
(with USS1, USS0,DSS1 and DSS0 is invalid. → with CES1 and CES0 of CCRM is invalid.)
187
Table 6.6-1 Selecting the ZIN Pin Function is changed.
191
Figure 7.2-1 Block Diagram of the 16-bit Reload Timer is changed.
204
Figure 8.2-2 Block Diagram of One Channel of the PPG Timer is changed.
(CK → Clock)
205, 206
Figure 8.3-1 Register List of PPG Timers is changed.
207
[bit14] STGR: Software trigger bit is changed.
(TGR → STGR)
230
Figure 9.2-1 Block Diagram of Multifunctional Timer is changed.
234
[bit4] MODE is changed.
(bit 3: CLR → bit3: SCLR)
236
[bit9, bit8] OTD1 and OTD0 is changed.
(the output compare register → the compare register)
238
[bit7, bit6] ICP3, ICP2, ICP1, and ICP0 is changed.
([Bits 15, 14, 7 and 6] → [bit7, bit6])
239
[bit5, bit4] ICE3, ICE2, ICE1, and ICE0 is changed.
([Bits 13, 12, 5 and 4] → [bit5, bit4])
239
[bit3 to bit0] EG31, EG30, EG21, EG20, EG11, EG10, EG01, and EG00 is changed.
([Bits 11 to 8, 3 to 0] → [bit3 to bit0])
xiv
Page
Changes (For details, refer to main body.)
243, 244
Figure 9.4-5 Example of the Output Waveform when Compare Registers 0 and 1 are Used (At the Beginning
of Output, 0 is Assumed.) and Figure 9.4-6 Example of the Output Waveform when Compare Registers 0 and
1 are Used (At the Beginning of Output, 0 is Assumed.) are changed.
(RTO0 → Compare register 0)
(RTO1 → Compare register 1)
246
Figure 9.4-8 Example of Capture Timing for the 16-bit Input Capture is changed.
251
Figure 10.2-1 List of External-Interrupt Registers is changed.
254
Table 10.2-1 External-Interrupt Level Setting Table is changed.
(LBx → LB15 to LB0)
(LAx → LA15 to LA0)
255
Figure 10.3-1 External-Interrupt Operation is changed.
(IL → Interrupt level)
255
■ Setting Procedure for an External Interrupt is changed.
(1. The general-purpose I/O port that is shared with the terminal used as external interrupt input is set to the
input port. is added.)
262
■ Hardware Configuration of Interrupt Controller is changed.
(• ICR register → • Interrupt control register (ICR register: ICR00 to ICR47))
263
Figure 12.2-1 Block Diagram of the Interrupt Controller is changed.
(RI00 → Resource interrupt 00)
(RI47 → Resource interrupt 47)
(HLDREQ → Hold request )
269 to 271
Table 12.4-1 Relationship Among Interrupt Sources, Interrupt Numbers, and Interrupt Levels is changed.
273
■ Levels that Can Be Set for Hold Request Cancellation Requests is changed.
(can be set in the HRCL register. → can ICR register be set in the HRCL register.)
274
Figure 12.7-1 Sample Hardware Configuration for Using a Hold-request Cancellation-request signal is
changed.
279
Figure 13.2-1 8/10-bit A/D Converter Block Diagram is changed.
(AVR ± → AVRH AVRL)
282
Figure 13.3-1 Block Diagram of the Pins PK0/AN0 to PK7/AN7 is changed.
(ADER → AICR)
((SPL=1) is deleted.)
284
Figure 13.4-2 Configuration and Functional Outline of A/D Control Status Register 1 (ADCS1) is changed.
285
[bit15] BUSY (Converting bit) is changed.
(Bit indicating conversion is in progress → Converting bit)
289
Notes: is added.
290
Figure 13.4-4 Configuration and Functional Outline of the A/D Data Register (ADCR0, 1) is changed.
(AD data bit → A/D conversion resolution selection bit)
296
❍ Analog input pin is changed.
301
■ D/A Control Registers (DACR0, DACR1, DACR2) is changed.
xv
Page
Changes (For details, refer to main body.)
302
■ D/A Data Registers (DADR2, DADR1, DADR0) is changed.
([Bits 23 to 16] DADR2 → [bit23 to bit16] DA27 to DA20)
([Bits 15 to 8] DADR1 → [bit15 to bit8] DA17 to DA10)
([Bits 7 to 0] DADR0 → [bit7 to bit0] DA07 to DA00)
323
Notes: is added.
331
Table 15.8-2 Selection of Synchronous Baud-rate Division Ratio and Table 15.8-3 Selection of Asynchronous Baud-rate Division Ratio are changed.
(The column of SCKI is deleted.)
331
Notes: is added.
335
■ Baud Rate Based on the External Clock is changed.
(• The port for inputting the external clock is set to input. is added.)
338
❍ Transfer-data format is changed.
(In operation mode 0, data has either a fixed length of eight bits without parity or a fixed length of 8 bits with
parity. → In normal mode of operation mode 0, data length can be set to 7 bits or 8 bits.)
344
Figure 15.9-8 Example of Bidirectional Communication Flow is changed.
(UODR → SODR)
354, 355
■ DMAC Control Status Register (DACSR) is changed.
(DERn → DER7 to DER0)
(DEDn → DED7 to DED0)
(DIEn → DIE7 to DIE0)
(DOEn → DOE7 to DOE0)
356, 357
■ DMAC Pin Control Register (DATCR) is changed.
(LSn1 and LSn0 → LS21, LS10, LS11, LS10, LS01 and LS00)
(AKSEn → AKSE2 to AKSE0)
(AKDEn → AKDE2 to AKDE0)
(EPSEn → EPSE2 to EPSE0)
(EPDEn → EPDE2 to EPDE0)
411 to 416
Table A-1 I/O Map is changed.
417 to 420
Table B-1 Interrupt Vectors is changed.
xvi
CHAPTER 1 OVERVIEW OF THE MB91151A
CHAPTER 1
OVERVIEW OF THE MB91151A
This chapter provides basic information required to fully understand the MB91151A,
such as a description of MB91151A features, block diagrams, and an outline of
functions.
1.1 MB91151A Features
1.2 Block Diagrams
1.3 Package Dimensions
1.4 Pin Assignments
1.5 Pin Functions
1.6 I/O Circuit Types
1
CHAPTER 1 OVERVIEW OF THE MB91151A
1.1
MB91151A Features
The MB91151A is a single-chip microcontroller suited for controlling devices such as
CD and DVD drives. The core of the MB91151A is a 32-bit RISC CPU (FR30).
■ MB91151A Features
❍ CPU
•
32-bit RISC (FR30), load/store architecture, 5-stage pipeline
•
32-bit general-purpose register × 16
•
16-bit fixed-length instructions (basic instruction), one instruction per cycle
•
Instructions for memory-to-memory transfer, bit processing, barrel shift, etc.
The instructions are suited for embedded-type usage.
•
Instructions for entry/exit functions, multiple load/store instructions for the register contents,
instructions for high-level languages.
•
Register interlock function allowing simpler assembler code
•
Branch instruction with a delay slot allowing a decrease in overhead for branch processing
•
Built-in multiplier, supported on the instruction level
•
Signed 32-bit multiplication: 5 cycles
•
Signed 16-bit multiplication: 3 cycles
•
Interrupt (PC and PS saving): 6 cycles, 16 priority levels
❍ Bus interface
•
16-bit address output, 8-bit and 16-bit data I/O
•
Basic bus cycle: 2 clock cycles
•
Interface for supporting various memory types
•
Unused data and address pins can be used as I/O ports.
•
Support of little endian mode
❍ Internal RAM
•
Instruction RAM: 2K bytes
•
Data RAM: 32K bytes
❍ DMA controller (DMAC)
2
•
DMAC of the descriptor type according to which transfer parameters are allocated in main
storage
•
Capable of transferring up to eight internal and external sources
•
External source: 3 channels
CHAPTER 1 OVERVIEW OF THE MB91151A
❍ Bit search module
The bit search module makes a one-cycle search for the location of the first I/O bit change
starting with the MSB of a word.
❍ Timer
•
16-bit OCU × 8 channels, ICU × 4 channels, free-run timer × 1 channel
•
8-bit or 16-bit up-down timer/counter (8-bit × 2 channels or 16-bit × 1 channel)
•
16-bit PPG timer × 6 channels. The cycle and duty of an output pulse can be changed to an
arbitrary value.
•
16-bit reload timer × 4 channels
❍ D/A converter
8 bits × 3 channels
❍ A/D converter (successive approximation type)
•
10 bits × 8 channels
•
Successive approximation type (conversion time: 5.0 µ[email protected] MHz)
•
Single and scan conversions can be selected, and single, continuous, and stop conversion
modes can be set.
•
Hardware-driven or software-driven conversion function
❍ Serial I/O
•
UART × 4 channels. Each UART can perform clock-synchronized serial transfer with the
LSB/MSB switching function.
•
Serial data output and serial clock output can be selected by open-drain or push-pull
software.
•
Built-in 16-bit timer (U-Timer) as a dedicated baud rate generator, which can generate any
baud rate
❍ Clock switching function
The ratio of the operating clock to the base clock can independently be set with the gear
function to 1:1. 1:2, 1:4, or 1:8 for the CPU and for each peripheral device.
❍ Interrupt controller
•
External interrupt input (up to 16 channels)
•
•
The leading edge, trailing edge, "H" level, or "L" level can be set.
Internal interrupt source
•
Resource interrupt, delayed interrupt
3
CHAPTER 1 OVERVIEW OF THE MB91151A
❍ Other features
•
Reset sources
•
•
Low-power consumption mode
•
•
Sleep mode and stop mode
Packages
•
PGA-299 (MB91V151A)
•
LQFP-144 (MB91151A)
•
CMOS technology (0.35 µm)
•
Power supply
•
4
Power-on reset, watchdog timer, software reset, and external reset
3.15 V to 3.6 V
CHAPTER 1 OVERVIEW OF THE MB91151A
1.2
Block Diagrams
This section provides MB91151A block diagrams.
■ Block Diagram for MB91V151A and MB91151A
Figure 1.2-1 is a block diagram for the MB91V151A and MB91151A.
Figure 1.2-1 Block Diagram (MB91V151A and MB91151A)
M
O
D
E
MD0
MD1
MD2
…
…
P37/D31(IO)
Instruction
Cache
1K byte
P
O
R
T
3
/
2
Data RAM
32K bytes
…
P30/D24
P27/D23
…
D-bus
(4)
RST
DATA
FR30 CPU Core
I-bus
(16)
P50/A08
P47/A07
P
O
R
T
6
/
5
/
4
Bit Search
D-bus
R-bus
E
(8)
P
O
R
T
G
(6)
…
Address
…
P60/A16
P57/A15
DMAC 8ch
…
…
P20/D16
P67/A23(O)
P
O
R
T
P40/A00
Bus
Control
DMAC
Clock
A/D
DMAC
Up/Down
Counter
External
Interrupt
P86/CLK(O)
P85/WR1(O)
P84/WR0
P83/RD(O)
P82/BRQ(I)
P81/BGRNT(O)
P80/RDY(I)
PL7/DACK2
PL6/DREQ2
PL5/DEOP1
PL4/DACK1
PL3/DREQ1
PL2/DEOP0(O)
PL1/DACK0(O)
PL0/DREQ0(I)
X0 (I)
X1 (I)
PD7/INT15/ATG(I)
PD6/INT14/DEOP2
PD5/INT13/ZIN1/TRG5
PD4/INT12/ZIN0/TRG4
PD3/INT11/BIN1/TRG3
PD2/INT10/AIN1/TRG2
PD1/INT9/BIN0/TRG1
PD0/INT8/AIN0/TRG0
PC7/INT7/CS3
PC6/INT6/CS2
PC5/INT5/CS1
PC4/INT4/CS0
PC3/INT3
PC2/INT2
PC1/INT1
PC0/INT0(I)
(24)
P
O
R
T
8
D-bus
I-bus
C-bus
External
Bus CTL
(7)
P
O
R
T
UART 4ch
U-Timer 4ch
16-bit
Reload Timer
4ch
RAM
2K bytes
16-bit
Free-run Timer
1ch
L
16-bit PPG
6ch
(8)
P
O
R
T
H
(6)
P
O
R
T
I
(6)
P
O
R
T
J
(2)
16-bit
OSC
(2)
P
O
R
T
D
(8)
4ch
P
O
R
T
16-bit
K
Input Capture
Clock Control
Output Compare
Interrupt
Controller
8ch
10-bit 8input
A/D converter
8-bit Up/Down
Counter
P
O
R
T
C
(8)
P
O
R
T
F
2ch
External
(8)
(5)
10-bit 3output
D/A converter
I 2CInterrupt
Interface
D
A
16ch1ch
(3)
PE7/OC7
PE6/OC6
PE5/OC5
PE4/OC4
PE3/OC3
PE2/OC2
PE1/OC1
PE0/OC0
Output
Compare
PG5/PPG5
PG4/PPG4
PG3/PPG3
PG2/PPG2
PG1/PPG1
PG0/PPG0
PPG
PH0/SIN0
PH1/SOT0
PH2/SCK0/T00
PH3/SIN1
PH4/SOT1
PH5/SCK1/T01
PI0/SIN2
PI1/SOT2
PI2/SCK2/T02
PI3/SIN3
PI4/SOT3
PI5/SCK3/T03
UART
TOX:
Reload
Timer
PJ0
PJ1
PK0/AN0
PK1/AN1
PK2/AN2
PK3/AN3
PK4/AN4
PK5/AN5
PK6/AN6
PK7/AN7
PF4
PF3/IN3
PF2/IN2
PF1/IN1
PF0/IN0
A/D
Input
Capture
DA2
DA1
DA0
5
CHAPTER 1 OVERVIEW OF THE MB91151A
1.3
Package Dimensions
Two types of MB91151A packages are provided.
■ Package Dimensions of PGA-299C-A01
Figure 1.3-1 Package Dimensions of PGA-299C-A01
256-pin ceramic PGA
Lead pitch
2.54mm(100mil)
Pin matrix
20
Sealing method
Metal seal
(PGA-299C-A01)
299-pin ceramic PGA
(PGA-299C-A01)
2.41 ± 0.10
(.095 ± .004)
1.65 ± 0.10
(.065 ± .004)
0.46 +– 0.13
0.05
(.018 +– .005
.002 )
30.48 ± 0.31
(1.200 ± .012)
35.56 ± 0.41
(1.400 ± .016)
INDEX AREA
3.94 ± 0.10
(.155 ± .004)
52.32 ± 0.56 SQ
(2.060 ± .022)
5.59 (.220) MAX
C
6
1994 FUJITSU LIMITED R299001SC-2-2
2.54 (.100) MAX
1.27 (.050) DIA TYP
(4 PLCS)
48.26 (19.00)
REF
2.54 ± 0.25
(.100 ± .010)
1.27 ± 0.25
(.050 ± .010)
0.41
.016
3.40 +– 0.36
(.134 +– .014
)
INDEX AREA
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
CHAPTER 1 OVERVIEW OF THE MB91151A
■ Package Dimensions of FPT-144P-M08
Figure 1.3-2 Package Dimensions of FPT-144P-M08
144-pin plastic LQFP
(FPT-144P-M08)
144-pin plastic LQFP
(FPT-144P-M08)
0.50 mm
Package width ×
package length
20.0 × 20.0 mm
Lead shape
Gullwing
Sealing method
Plastic mold
Mounting height
1.70 mm MAX
Weight
1.20g
Code
(Reference)
P-LFQFP144-20×20-0.50
Note 1) *:Values do not include resin protrusion.
Resin protrusion is +0.25(.010)Max(each side).
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
22.00±0.20(.866±.008)SQ
* 20.00±0.10(.787±.004)SQ
108
Lead pitch
0.145±0.055
(.006±.002)
73
109
72
0.08(.003)
Details of "A" part
+0.20
1.50 –0.10
+.008
.059 –.004
0, ~8,
INDEX
144
37
"A"
LEAD No.
1
36
0.50(.020)
C
2003 FUJITSU LIMITED F144019S-c-4-6
0.22±0.05
(.009±.002)
0.08(.003)
0.50±0.20
(.020±.008)
0.60±0.15
(.024±.006)
(Mounting height)
0.10±0.10
(.004±.004)
(Stand off)
0.25(.010)
M
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
7
CHAPTER 1 OVERVIEW OF THE MB91151A
1.4
Pin Assignments
This section shows the MB91151A pin assignment for each type of package.
■ Pin Assignments of MB91151A (PGA-299C-A01)
Figure 1.4-1 shows the MB91151A (PGA-299C-A01) pin assignment. Table 1.4-1 lists the
correspondences between pin numbers and pin names.
Figure 1.4-1 Pin Assignment (MB91151A (PGA-299C-A01))
8
3
299
296 293 277 274 270 268 278 275 262 254 247 257 252 250 245 233 230 224
2
298
292 289 286 283 280 276 269 264 263 258 251 248 243 240 237 234 225 221
5
10
4
297 291 287 284 279 271 265 261 256 249 242 239 235 229 228 219 218
8
13
6
300 295 290 285 281 272 267 259 255 246 241 236 231 226 223 215 207
25 16
11
7
1
294 288 282 273 266 260 253 244 238 232 227 222 217 212 202
27 19
15
12
9
220 216 213 209 199
32 23
18
17 14
214 211 210 205 195
34 26
24
21 20
208 206 204
22 33
31
30 28
29 39
38
35 36
37 40
41
43 42
50 44
46
47 48
178 180 181 183 172
53 51
54
56 58
170 171 174 176 184
45 55
60
61 64
164 167 168 173 182
49 59
63
66 70
159 162 165 169 177
52 62
67
72 77 82
88 94 103 110 116 123 133 139 145 153 157 161 166 175
57 65
73
76 81 86
91 96 105 109 117 122 131 136 141 147 151 156 163 158
68 69
78
79 85 89
92 99 106 111 115 121 129 135 138 142 148 154 160 155
71 75
84
87 90 93
98 101 108 113 114 119 126 130 134 137 140 144 150 152
74 80
83
95 100 102 107 97 104 112 125 128 118 120 124 127 132 143 146 149
PGA-299C-A01
201 203
198 197 196 194 200
192 193 191 190 187
(Bottom View)
186 185 188 189 179
CHAPTER 1 OVERVIEW OF THE MB91151A
Table 1.4-1 Correspondence Between Pin Numbers and Pin Names (MB91151A (PGA-299C-A01))
(Device: MB91V151A Package: PGA-299C-A01)
No.
Pin name
No.
Pin name
No.
Pin name
No.
Pin name
No.
Pin name
No.
1
P20/D16
51
P81/BGRNT
101
PK1/AN1
151
PD4/INT12/ZIN0
201
OPEN
251
OPEN
2
VSS
52
P82/BRQ
102
PK2/AN2
152
VSS
202
OPEN
252
OPEN
3
OPEN
53
VCC
103
PK3/AN3
153
PD5/INT13/ZIN1
203
VCC
253
OPEN
4
P21/D17
54
P83/RD
104
OPEN
154
PD6/INT14/DEOP2 204
IHIT3
254
VCC
5
VCC
55
P84/WR0
105
PK4/AN4
155
VCC
IHIT2
255
TDT31
6
P22/D18
56
P85/WR1
106
PK5/AN5
156
PD7/INT15/ATG
206
IHIT1
256
TDT32
7
P23/D19
57
P86/CLK
107
PK6/AN6
157
PE0/OC0
207
IHIT0
257
TDT33
8
VSS
58
PL0/DREQ0
108
PK7/AN7
158
VSS
208
OPEN
258
TDT34
9
P24/D20
59
PL1/DACK0
109
DAVC
159
PE1/OC1
209
OPEN
259
OPEN
10
P25/D21
60
PL2/DEOP0
110
DAVS
160
PE2/OC2
210
OPEN
260
OPEN
205
Pin name
11
P26/D22
61
PL3/DREQ1
111
DA0
161
PE3/OC3
211
VCC
261
OPEN
12
P27/D23
62
PL4/DACK1
112
VSS
162
PE4/OC4
212
MOD31
262
VSS
13
P30/D24
63
PL5/DEOP1
113
DA1
163
PE5/OC5
213
MOD30
263
VCC
14
P31/D25
64
PL6/DREQ2
114
DA2
164
PE6/OC6
214
MOD29
264
OPEN
15
P32/D26
65
PL7/DACK2
115
PH0/SIN0
165
PE7/OC7
215
MOD28
265
OPEN
16
P33/D27
66
OPEN
116
PH1/SOT0
166
VCC
216
MOD27
266
OPEN
17
P34/D28
67
OPEN
117
PH2/SCK0/T00
167
PF0/IN0
217
MOD26
267
VSS
18
P35/D29
68
VCC
118
PI0/SIN1
168
PF1/IN1
218
VSS
268
OPEN
19
P36/D30
69
OPEN
119
PI1/SOT1
169
PF2/IN2
219
MOD25
269
VCC
20
P37/D31
70
OPEN
120
PI2/SCK1/T01
170
PF3/IN3
220
MOD24
270
OPEN
21
P40/A00
71
VSS
121
PI3/SIN2
171
PF4
221
VCC
271
OPEN
22
VCC
72
OPEN
122
PI4/SOT2
172
VCC
222
MOD23
272
OPEN
23
P41/A01
73
OPEN
123
PI5/SCK2/T02
173
PG0/PPG0
223
MOD22
273
OPEN
24
P42/A02
74
VCC
124
PJ0/SIN3
174
PG1/PPG1
224
VSS
274
OPEN
25
P43/A03
75
OPEN
125
VCC
175
PG2/PPG2
225
MOD21
275
VCC
26
P44/A04
76
MD0
126
PI4/SOT3
176
PG3/PPG3
226
MOD20
276
OPEN
27
P45/A05
77
MD1
127
PI5/SCK3/T03
177
PG4/PPG4
227
MOD19
277
OPEN
28
P46/A06
78
MD2
128
VSS
178
PG5/PPG5
228
MOD18
278
VSS
29
VSS
79
VCC
129
OPEN
179
VSS
229
MOD17
279
OPEN
30
P47/A07
80
VSS
130
OPEN
180
OPEN
230
VCC
280
OPEN
31
P50/A08
81
X0
131
OPEN
181
OPEN
231
MOD16
281
OPEN
32
P51/A09
82
X1
132
OPEN
182
OPEN
232
MOD15
282
OPEN
33
P52/A10
83
VCC
133
PJ0
183
OPEN
233
VSS
283
OPEN
34
P53/A11
84
RST
134
PJ1
184
OPEN
234
MOD14
284
OPEN
35
P54/A12
85
OPEN
135
VSS
185
OPEN
235
MOD13
285
OPEN
36
P55/A13
86
ICLK
136
PC0/INT0
186
OPEN
236
MOD12
286
VCC
37
VCC
87
ICS0
137
PC1/INT1
187
VCC
237
MOD11
287
OPEN
38
P56/A14
88
ICS1
138
PC2/INT2
188
OPEN
238
MOD10
288
OPEN
39
P57/A15
89
ICS2
139
PC3/INT3
189
OPEN
239
MOD9
289
OPEN
40
P60/A16
90
ICD0
140
PC4/INT4/CS0
190
OPEN
240
VCC
290
OPEN
41
P61/A17
91
ICD1
141
PC5/INT5/CS1
191
MCLK
241
MOD8
291
OPEN
42
P62/A18
92
ICD2
142
PC6/INT6/CS2
192
MRST
242
MOD7
292
OPEN
43
P63/A19
93
ICD3
143
VCC
193
VCC
243
MOD6
293
VCC
44
P64/A20
94
BREAK
144
PC7/INT7/CS3
194
DHIT5
244
MOD5
294
OPEN
45
P65/A21
95
AVCC
145
PD0/INT8/AIN0
195
DHIT4
245
MOD4
295
OPEN
46
P66/A22
96
AVRH
146
VSS
196
DHIT3
246
MOD3
296
VSS
47
P67/A23
97
VSS
147
PD1/INT9/BIN0
197
DHIT2
247
VSS
297
OPEN
48
P80/RDY
98
AVRL
148
PD2/INT10/AIN1
198
DHIT1
248
MOD2
298
OPEN
49
VCC
99
AVSS
149
VCC
199
DHIT0
249
MOD1
299
VCC
50
VSS
100
PK0/AN0
150
PD3/INT11/BIN1
200
VSS
250
MOD0
300
OPEN
9
CHAPTER 1 OVERVIEW OF THE MB91151A
■ Pin Assignments of MB91151A (FPT-144P-M08)
Figure 1.4-2 shows the MB91151A (FPT-144P-M08) pin assignments.
10
DAVC
DAVS
DA0
DA1
DA2
VCC
PL7/DACK2
PL6/DREQ2
PL5/DEOP1
PL4/DACK1
PL3/DREQ1
PL2/DEOP0
PL1/DACK0
PL0/DREQ0
PH0/SIN0
PH1/SOT0
PH2/SCK0/TO0
PH3/SIN1
PH4/SOT1
121
120
119
118
117
116
115
114
113
112
111
110
109
AVRL
AVRH
AVCC
129
128
127
126
125
124
123
122
AVSS
131
130
132
PK2/AN2
PK1/AN1
PK0/AN0
135
134
133
PK5/AN5
PK4/AN4
PK3/AN3
VCC
PK7/AN7
PK6/AN6
139
138
137
136
OPEN
141
140
OPEN
OPEN
142
144
143
VSS
Figure 1.4-2 Pin Assignments (MB91151A (FPT-144P-M08))
P20/D16
1
108
PH5/SCK1/TO1
P21/D17
2
107
PI0/SIN2
P22/D18
3
106
PI1/SOT2
P23/D19
4
105
PI2/SCK2/TO2
P24/D20
5
104
PI3/SIN3
P25/D21
6
103
PI4/SOT3
P26/D22
7
102
PI5/SCK3/TO3
P27/D23
8
101
VSS
VSS
PJ0
9
100
P30/D24
10
99
PJ1
P31/D25
11
98
VSS
P32/D26
12
97
VCC
P33/D27
13
96
PG5/PPG5
P34/D28
14
95
PG4/PPG4
P35/D29
15
94
PG3/PPG3
P36/D30
16
93
PG2/PPG2
92
PG1/PPG1
91
PG0/PPG0
P37/D31
17
P40/A00
18
P41/A01
19
90
PF4
P42/A02
20
89
P43/A03
21
88
PF3/IN3
PF2/IN2
P44/A04
22
87
PF1/IN1
P45/A05
23
86
PF0/IN0
P46/A06
24
85
PE7/OC7
P47/A07
25
84
PE6/OC6
VSS
26
83
PE5/OC5
VCC
27
82
PE4/OC4
P50/A08
28
81
PE3/OC3
P51/A09
29
80
PE2/OC2
P52/A10
30
79
PE1/OC1
P53/A11
31
78
PE0/OC0
P54/A12
32
77
VCC
P55/A13
33
76
PD7/ATG/INT15
P56/A14
34
75
PD6/DEOP2/INT14
P57/A15
35
74
PD5/ZIN1/INT13/TRG5
P60/A16
36
73
PD4/ZIN0/INT12/TRG4
Top View
PD3/BIN1/INT11/TRG3
69
70
71
72
PD0/AIN0/INT8/TRG0
PD1/BIN0/INT9/TRG1
PD2/AIN1/INT10/TRG2
50
51
P85/WR1
P86/CLK
MD2
MD1
MD0
RST
VCC
60
61
62
63
64
65
66
67
68
47
48
49
P82/BRQ
P83/RD
P84/WR0
PC0/INT0
PC1/INT1
PC2/INT2
PC3/INT3
PC4/INT4/CS0
PC5/INT5/CS1
PC6/INT6/CS2
PC7/INT7/CS3
VCC
44
45
46
P80/RDY
P81/BGRNT
X1
X0
VSS
41
42
43
P65/A21
P66/A22
P67/A23
52
53
54
55
56
57
58
59
40
P64/A20
VSS
37
38
39
P61/A17
P62/A18
P63/A19
FPT-144P-M08
CHAPTER 1 OVERVIEW OF THE MB91151A
1.5
Pin Functions
Table 1.5-1 lists the functions of the MB91151A pins.
■ Functions of the MB91151A Pins
Table 1.5-1 Functions of the MB91151A Pins (1 / 7)
Pin No.
Pin name
Circuit type
Function description
1
2
3
4
5
6
7
8
P20/D16
P21/D17
P22/D18
P23/D19
P24/D20
P25/D21
P26/D22
P27/D23
C
External data bus bits 16 to 23
Effective only in external bus 16-bit mode.
Can be used as a port in single-chip or external bus 8bit mode.
10
11
12
13
14
15
16
17
P30/D24
P31/D25
P32/D26
P33/D27
P34/D28
P35/D29
P36/D30
P37/D31
C
External data bus bits 24 to 31
Can be used as a port in single-chip mode.
18
19
20
21
22
23
24
25
28
29
30
31
32
33
34
35
P40/A00
P41/A01
P42/A02
P43/A03
P44/A04
P45/A05
P46/A06
P47/A07
P50/A08
P51/A09
P52/A10
P53/A11
P54/A12
P55/A13
P56/A14
P57/A15
F
External address bus bits 0 to 15
Effective in external bus mode.
Can be used as a port in single-chip mode.
11
CHAPTER 1 OVERVIEW OF THE MB91151A
Table 1.5-1 Functions of the MB91151A Pins (2 / 7)
Pin No.
Pin name
Circuit type
36
37
38
39
40
41
42
43
P60/A16
P61/A17
P62/A18
P63/A19
P64/A20
P65/A21
P66/A22
P67/A23
O
External address bus bits 16 to 23
Can be used as a port when the address bus is not
used.
45
P80/RDY
C
External RDY input
Effective when external RDY input is enabled.
"0" is inputted if the bus cycle in progress fails to be
completed.
Can be used as a port when external RDY input is not
used.
46
P81/BGRNT
F
External bus open acceptance output
Effective when external bus open acceptance output is
enabled.
Outputs L when the external bus is opened.
Can be used as a port when external bus open
acceptance output is disabled.
47
P82/BRQ
C
External bus open request input
Effective when external bus open request input is
enabled.
Input "1" to open the external bus.
Can be used as a port when external bus open
request input is disabled.
48
P83/RD
F
External bus read strobe output
Effective when external bus read strobe output is
enabled.
Can be used as a port when external bus read strobe
output is disabled.
49
P84/WR0
F
External bus write strobe output
Effective in external bus mode.
Can be used as a port in single-chip mode.
50
P85/WR1
F
External bus write strobe output
Effective when MB91151A is in external bus mode and
bus width is 16 bits.
Can be used as a port when MB91151A is in singlechip mode or 8-bit external bus mode.
51
P86/CLK
F
System clock output
Outputs a clock signal that is equal to the operating
frequency of the external bus. Can be used as a port
when the system clock is not used.
52
53
54
MD2
MD1
MD0
G
Mode pins
Connect these pins directly to VCC or VSS.
These pins set the basic MCU operation mode.
55
RST
B
External reset input
12
Function description
CHAPTER 1 OVERVIEW OF THE MB91151A
Table 1.5-1 Functions of the MB91151A Pins (3 / 7)
Pin No.
Pin name
Circuit type
Function description
57
58
X1
X0
A
High-speed clock oscillation pins
60
61
62
63
PC0/INT0
PC1/INT1
PC2/INT2
PC3/INT3
H
External interrupt request inputs 0 to 3
These inputs are always in use while the
corresponding external interrupts are enabled. Stop
port output in advance unless the resulting processing
is intentional.
This port can be used to release the standby status
because its input is enabled even during standby.
Can be used as a port when the pin is not used for
external interrupt request input.
64
65
66
67
PC4/INT4/CS0
PC5/INT5/CS1
PC6/INT6/CS2
PC7/INT7/CS3
H
Used for both chip select outputs and external interrupt
request inputs 4 to 7
Can be used for external interrupt request input or as a
port when chip select output is disabled.
These inputs are always in use while the
corresponding external interrupts are enabled. Stop
port output in advance unless the resulting processing
is intentional.
This port can be used to release the standby status
because its input is enabled even during standby.
Can be used as a port when the pin is not used for
external interrupt request input and chip select output.
69
70
71
72
73
74
PD0/AIN0/INT8/TRG0
PD1/BIN0/INT9/TRG1
PD2/AIN1/INT10/TRG2
PD3/BIN1/INT11/TRG3
PD4/ZIN0/INT12/TRG4
PD5/ZIN1/INT13/TRG5
H
External interrupt request inputs 8 to 13
These inputs are always in use while the
corresponding external interrupts are enabled. Stop
port output in advance unless the resulting processing
is intentional.
[AIN0, AIN1, BIN0, BIN1, ZIN0, ZIN1] Up-down timer
input
[TRG0 to TRG5] PPG external trigger input
These inputs are always in use while they are enabled.
Stop port output in advance unless the resulting
processing is intentional.
Can be used as a port when the pin is not used for
external interrupt request input, up timer counter input,
and PPG external trigger input.
75
PD6/DEOP2/INT14
H
External interrupt request input 14
This input is always in use while the corresponding
external interrupt is enabled. Stop port output in
advance unless the resulting processing is intentional.
[DEOP2] DMA external transfer end output
Effective when DMAC external transfer end output
specification is enabled.
Can be used as a port when the pin is not used for
external interrupt request input or DMA external
transfer end output.
13
CHAPTER 1 OVERVIEW OF THE MB91151A
Table 1.5-1 Functions of the MB91151A Pins (4 / 7)
Pin No.
Pin name
Circuit type
Function description
76
PD7/ATG/INT15
H
External interrupt request input 15
This input is always in use while the corresponding
external interrupt is enabled. Stop port output in
advance unless the resulting processing is intentional.
[ATG] A/D converter external trigger input
This input is always in use when the pin is selected for
A/D start source. Stop port output in advance unless
the resulting processing is intentional.
Can be used as a port when the pin is not used for
external interrupt request input and A/D converter
external trigger input.
78
79
80
81
82
83
84
85
PE0/OC0
PE1/OC1
PE2/OC2
PE3/OC3
PE4/OC4
PE5/OC5
PE6/OC6
PE7/OC7
F
Output compare output
Can be used as a port when output compare output
specification is disabled.
86
87
88
89
PF0/IN0
PF1/IN1
PF2/IN2
PF3/IN3
F
Input capture input
Effective for input with input capture.
Can be used as a port when the pin is not used as
input capture input.
90
PF4
F
General-purpose I/O port
91
92
93
94
95
96
PG0/PPG0
PG1/PPG1
PG2/PPG2
PG3/PPG3
PG4/PPG4
PG5/PPG5
F
PPG timer output
Effective when PPG timer output specification is
enabled.
Can be used as a port when PPG timer output
specification is disabled.
99
PJ1
Q
General-purpose I/O port
100
PJ0
Q
General-purpose I/O port
102
PI5/SCK3/TO3
P
UART3 clock I/O, reload timer 3 output
Acts as output for reload timer 3 when UART3 clock
output is disabled and reload timer 3 output is enabled.
Can be used as port when UART3 clock output and
reload timer output are disabled.
103
PI4/SOT3
P
UART3 data output
Effective when UART3 data output specification is
enabled.
Can be used as a port when UART3 clock output
specification is disabled.
14
CHAPTER 1 OVERVIEW OF THE MB91151A
Table 1.5-1 Functions of the MB91151A Pins (5 / 7)
Pin No.
Pin name
Circuit type
Function description
104
PI3/SIN3
P
UART3 data input
This input is always in use while UART3 is performing
input processing. Stop port output in advance unless
the resulting processing is intentional.
Can be used as a port when the pin is not used for
UART3 data input.
105
PI2/SCK2/TO2
P
UART2 clock I/O, reload timer 2 output
Acts as output for reload timer 2 when UART2 clock
output is disabled and reload timer 2 output is enabled.
Can be used as port when UART2 clock output and
reload timer output are disabled.
106
PI1/SOT2
P
UART2 data output
Effective when UART2 data output specification is
enabled.
Can be used as a port when UART2 clock output
specification is disabled.
107
PI0/SIN2
P
UART2 data input
This input is always in use while UART2 is performing
input processing. Stop port output in advance unless
the resulting processing is intentional.
Can be used as a port when the pin is not used for
UART2 data input.
108
PH5/SCK1/TO1
P
UART1 clock I/O, reload timer 1 output
Acts as output for reload timer 1 when UART1 clock
output is disabled and reload timer 1 output is enabled.
Can be used as port when UART1 clock output and
reload timer output are disabled.
109
PH4/SOT1
P
UART1 data output
Effective when UART1 data output specification is
enabled.
Can be used as a port when UART1 clock output
specification is disabled.
110
PH3/SIN1
P
UART1 data input
This input is always in use while UART1 is performing
input processing. Stop port output in advance unless
the resulting processing is intentional.
Can be used as a port when the pin is not used for
UART1 data input.
111
PH2/SCK0/TO0
P
UART0 clock I/O, reload timer 0 output
Acts as output for reload timer 0 when UART0 clock
output is disabled and reload timer 0 output is enabled.
Can be used as port when UART0 clock output and
reload timer output are disabled.
112
PH1/SOT0
P
UART0 data output
Effective when UART0 data output specification is
enabled.
Can be used as a port when UART0 clock output
specification is disabled.
15
CHAPTER 1 OVERVIEW OF THE MB91151A
Table 1.5-1 Functions of the MB91151A Pins (6 / 7)
Pin No.
Pin name
Circuit type
Function description
113
PH0/SIN0
P
UART0 data input
This input is always in use while UART0 is performing
input processing. Stop port output in advance unless
the resulting processing is intentional.
Can be used as a port when the pin is not used for
UART0 data input.
114
PL0/DREQ0
F
DMA external transfer request input
This pin is always in use when the pin is selected for a
DMA controller transfer source. Stop port output in
advance unless the resulting processing is intentional.
Can be used as a port when the pin is not used for
DMA external transfer request input.
115
PL1/DACK0
F
DMA external transfer request acceptance output
Effective when external transfer request acceptance
output specification of the DMA controller is enabled.
Can be used as a port when external transfer request
acceptance output specification of the DMA controller
is disabled.
116
PL2/DEOP0
F
DMA external transfer end output
Effective when external transfer end output
specification of the DMA controller is enabled.
Can be used as a port when DMA external transfer
end output is disabled.
117
PL3/DREQ1
F
DMA external transfer request input
This pin is always in use when the pin is selected for a
DMA controller transfer source. Stop port output in
advance unless the resulting processing is intentional.
Can be used as a port when the pin is not used for
DMA external transfer request input.
118
PL4/DACK1
F
DMA external transfer request acceptance output
Effective when external transfer request acceptance
output specification of the DMA controller is enabled.
Can be used as a port when external transfer request
acceptance output specification of the DMA controller
is disabled.
119
PL5/DEOP1
F
DMA external transfer end output
Effective when external transfer end output
specification of the DMA controller is enabled.
Can be used as a port when DMA external transfer
end output is disabled.
120
PL6/DREQ2
F
DMA external transfer request input
This pin is always in use when the pin is selected for a
DMA controller transfer source. Stop port output in
advance unless the resulting processing is intentional.
Can be used as a port when the pin is not used as
DMA external transfer request input.
16
CHAPTER 1 OVERVIEW OF THE MB91151A
Table 1.5-1 Functions of the MB91151A Pins (7 / 7)
Pin No.
Pin name
Circuit type
Function description
121
PL7/DACK2
F
DMA external transfer request acceptance output
Effective when external transfer request acceptance
output specification of the DMA controller is enabled.
Can be used as a port when external transfer request
acceptance output specification of the DMA controller
is disabled.
123
124
125
DA2
DA1
DA0
-
D/A converter output
Effective when D/A converter output specification is
enabled.
126
DAVS
-
Power supply pin of D/A converter
127
DAVC
-
Power supply pin of D/A converter
128
AVCC
-
VCC power supply for A/D converter
129
AVRH
-
A/D converter reference voltage (high potential side)
Be sure to turn on or off this pin when a potential of
AVRH or higher is applied to VCC.
130
AVRL
-
A/D converter reference voltage (low potential side)
131
AVSS
-
VSS power supply for A/D converter
132
133
134
135
136
137
138
139
PK0/AN0
PK1/AN1
PK2/AN2
PK3/AN3
PK4/AN4
PK5/AN5
PK6/AN6
PK7/AN7
N
A/D converter analog input
Effective when the AICR register specifies analog
input.
Can be used as a port when A/D converter analog
input is not used.
27, 56,
68, 77,
97, 122,
140
VCC
-
Power supply pin of digital circuit
Be sure to connect the power supply to all VCC pins.
9,26,
44, 59,
98, 101,
144
VSS
-
Ground level of digital circuit
Be sure to ground the power supply to all VSS pins.
Note:
For most of the above pins, port I/O and resource I/O are multiplexed as in xxxx/Pxx.
If port and resource outputs compete at these pins, resource output precedes port output.
17
CHAPTER 1 OVERVIEW OF THE MB91151A
1.6
I/O Circuit Types
Table 1.6-1 shows the MB91151A I/O circuit types.
■ I/O Circuit Types
Table 1.6-1 I/O Circuit Types
Classification
Circuit
Remarks
•
High-speed oscillator
Oscillation feedback resistor:
about 1 MΩ
•
CMOS hysteresis input pin
CMOS hysteresis input
(Without standby control)
With pull-up resistance
•
CMOS level I/O pin
CMOS level output
CMOS level input
(With standby control)
IOL=4mA
X1
Xout
A
X0
Standby control signal
B
Digital input
Pout
C
Nout
CMOS input
Standby control
18
CHAPTER 1 OVERVIEW OF THE MB91151A
Table 1.6-1 I/O Circuit Types
Classification
Circuit
Remarks
•
CMOS hysteresis I/O pin
CMOS level output
CMOS hysteresis input
(With standby control)
IOL=4mA
•
CMOS level input pin
CMOS level input
(Without standby control)
•
CMOS hysteresis I/O pin with
pull-up control
CMOS level output
CMOS hysteresis input
(Without standby control)
Pull-up resistance: about 50 kΩ
(Typ)
IOL=4mA
•
Analog/CMOS level I/O pin
CMOS level output
CMOS level input
(With standby control)
Analog input
(Analog input is enabled when
the bit corresponding to AICR is
1.)
IOL=4mA
Pout
F
Nout
CMOS
Hysteresis input
Standby control
G
Digital input
Pull-up control
R
Pout
H
Nout
CMOS
Hysteresis input
Pout
N
Nout
CMOS input
Standby control
Analog input
19
CHAPTER 1 OVERVIEW OF THE MB91151A
Table 1.6-1 I/O Circuit Types
Classification
Circuit
Remarks
•
CMOS hysteresis I/O pin with
pull-up control
CMOS level output
CMOS hysteresis input
(With standby control)
Pull-up resistance: about 50 kΩ
(Typ)
IOL=4mA
•
CMOS hysteresis I/O pin with
pull-up control
CMOS level output
(With open-drain control)
CMOS hysteresis input
(With standby control)
Pull-up resistance: about 50 kΩ
(Typ)
IOL=4mA
•
•
•
Open drain I/O pin
5 V dielectric strength
CMOS hysteresis input
(With standby control)
IOL=15mA
Pull-up control
Pout
O
Nout
CMOS
Hysteresis input
Standby control
Pull-up control
R
Open-drain control
P
Nout
CMOS
Hysteresis input
Standby control
Nout
Q
CMOS
Hysteresis input
Standby control
20
CHAPTER 2 HANDLING THE DEVICE
CHAPTER 2
HANDLING THE DEVICE
This chapter provides notes on handling the MB91151A.
2.1 Notes on Handling Devices
2.2 Notes on Using Devices
2.3 Power-On
21
CHAPTER 2 HANDLING THE DEVICE
2.1
Notes on Handling Devices
This section describes latch-up prevention, pin processing, and circuit handling.
■ Latch-up Prevention
CMOS ICs may suffer a latch-up when a higher voltage than VCC or a lower voltage than VSS is
applied to an input or output pin or when a voltage exceeding the applicable rating is applied
between VCC and VSS. This latch-up may rapidly increase power supply current, resulting in
thermal damage to an element. For this reason, ensure that the voltage to be applied does not
exceed the absolute maximum ratings.
■ Pin Processing
❍ Unused pin processing
Leaving unused input pins open may result in a malfunction; pull them up or down.
❍ OPEN pin processing
Be sure to open the OPEN pin when using it.
❍ Output pin processing
Connecting one output pin with another, connecting an output pin with the power supply, or
connecting a large capacity load may cause flow of high current. Over a long period, this
condition results in device deterioration. For this reason, ensure that the current does not
exceed the absolute maximum ratings.
❍ Mode pins (MD0 to MD2)
Connect the MD0 to MD2 pins direct to VCC or VSS when using them. To prevent MB91151A
from entering the test mode mistakenly due to noise, make the pattern length between each
mode pin and VCC or VSS on a PC board as short as possible and connect these in low
impedance.
❍ Power supply pins
If there are several VCC and VSS pins, those that must be set to the same potential in the device
are connected to each other in device design to prevent such malfunctions as latch-up. To
prevent the strobe signal from malfunctioning due to fluctuations in background radiation and
increase in ground level current or to observe the total output current regulations, be sure to
externally connect all these power supply pins to the power supply and ground.
Also, connect the power supply pins from the power supply source to the VCC and VSS pins of
this device at low impedance as far as possible. In addition, a ceramic capacitor of about 0.1µF
should be connected between VCC and VSS pins near this device as a bypass capacitor.
22
CHAPTER 2 HANDLING THE DEVICE
■ Circuit Handling
❍ Crystal oscillation circuit
Noise near the X0 or X1 pin causes this device to malfunction. Design PC boards so that the
X0 and X1 pins, crystal oscillators (or ceramic oscillators), and bypass capacitors to the ground
can be placed as close as possible.
In the interest of stable operation, it is strongly recommended that a PC board artwork that
encloses the surroundings of the X0 and X1 pins with the ground should be used.
Please ask the crystal maker to evaluate the oscillational characteristics of the crystal and this
device.
23
CHAPTER 2 HANDLING THE DEVICE
2.2
Notes on Using Devices
This section provides notes on using external reset input and external clocks.
■ External Reset Input
To securely put the device into the reset state, at least five machine cycles of L level input to the
RST pin are required.
■ External Clock
When an external clock is used, feed the clock to the X0 pin and antiphase clock to the X1 pin
simultaneously. However, when the STOP mode (oscillation stop mode) is also used, the X1
pin stops with H output in STOP mode. To prevent output collision, provide an external resistor
of about 1 kΩ.
Figure 2.2-1 shows an example of using an external clock.
Figure 2.2-1 Example of Using an External Clock
X0
X1
MB91151A
■ Note on During Operation of PLL Clock Mode
If the PLL clock mode is selected, the microcontroller attempts to be working with the selfoscillating circuit even when there is no external oscillator or external clock input is stopped.
Performance of this operation, however, cannot be guaranteed.
■ Watchdog Timer Function
The watchdog timer supported by the FR family monitors the program that performs the reset
delay operation for a specified time. If the program hangs and the reset delay operation is not
performed, the watchdog timer resets the CPU. Therefore, once the watchdog timer is enabled,
operation continues until the CPU is reset.
As an exception, a reset delay automatically occurs if the CPU stops program execution. For the
conditions that apply to this exception, refer to "3.12.8 Watchdog Function".
24
CHAPTER 2 HANDLING THE DEVICE
2.3
Power-On
This section provides notes on power-on and notes applicable when the clock function
and power-on are not used.
■ Notes on Power-On
❍ Power-on
At power-on, be sure to start the RST pin at the L level. After the power supply level becomes
the VCC level, wait until the time for at least five cycles of the internal operating clock has
elapsed, then set the RST pin to the H level.
❍ Oscillation input
At power-on, be sure to continue inputting clock signals until the oscillation stabilization wait
status is released.
❍ Power-on reset
Be sure to perform a power-on reset to turn on power. Perform a power-on reset also when
powering on again if the power supply voltage has dropped to less than the voltage for assuring
operation.
❍ Power on order
Turn on power in the order of VCC → AVCC → AVRH and turn off power in the reverse order.
❍ A/D converter
Even when the A/D converter is not used, connect AVCC to the VCC level and AVSS to the VSS
level.
❍ D/A converter
Even when the D/A converter is not used, connect DAVC to the VCC level and DAVS to the VSS
level.
❍ Treatment of unstable power supply voltage or when shutting off power supply
When the power supply voltage is lower than the under limit of the operation assurance voltage,
initialize a device using one of the following methods because the internal status of the device
becomes undefined.
• Method 1: Input an external reset for source oscillation of 221 cycles or more.
• Method 2: Turn on the power supply from the voltage (VCC = 0.2V or less) that power-on
reset occurs.
25
CHAPTER 2 HANDLING THE DEVICE
26
CHAPTER 3 MEMORY SPACE, CPU, AND CONTROL UNIT
CHAPTER 3
MEMORY SPACE, CPU, AND CONTROL
UNIT
This chapter provides basic information regarding the architecture, specifications,
instructions, and other topics, that is required to understand the CPU core functions of
the FR family.
3.1 Memory Space
3.2 CPU Architecture
3.3 Instruction Cache
3.4 Programming Model
3.5 Data Structure
3.6 Word Alignment
3.7 Special Memory Areas
3.8 Overview of Instructions
3.9 EIT (Exception, Interrupt, and Trap)
3.10 Reset Sequence
3.11 Operation Mode
3.12 Clock Generator (Low-Power Consumption Mechanism)
3.13 Low-Power Consumption Mode
27
CHAPTER 3 MEMORY SPACE, CPU, AND CONTROL UNIT
3.1
Memory Space
The logical address space of the FR family is 4G bytes (232 addresses). The CPU
accesses this space linearly.
■ Direct Addressing Area
The following area of the address space is used for I/O operations.
This area is called the direct addressing area. The addresses in this area can directly be
specified in instruction operands.
The size of the direct area varies depending on the size of data to be accessed as follows:
28
•
Byte data access:
000H to 0FFH
•
Halfword data access:
000H to 1FFH
•
Word data access:
000H to 3FFH
CHAPTER 3 MEMORY SPACE, CPU, AND CONTROL UNIT
■ Memory Map for MB91V151A and MB91151A
Figure 3.1-1 shows the memory map for the MB91V151A and MB91151A.
Figure 3.1-1 Memory Map for MB91V151A and MB91151A
External bus mode
Single-Start mode
0000 0000 H
I/O
I/O
I/O
I/O
Access disabled
Access disabled
Built-in RAM
32K bytes
Built-in RAM
32K bytes
Access disabled
Access disabled
Direct addressing area
0000 0400 H
I/O map reference
0000 0800 H
0000 1000 H
0000 9000 H
0001 0000 H
0008 0000H
0008 0800 H
Access disabled
Access disabled
Built-in RAM
2K bytes
Built-in RAM
2K bytes
Access disabled
Access disabled
External area
Serial ROM
2K bytes
0009 0000 H
Access disabled
FFFF FFFFH
0001 0000
H
0008 0000
H
0008 0800
H
000F F800
H
0010 0000
H
FFFF FFFFH
29
CHAPTER 3 MEMORY SPACE, CPU, AND CONTROL UNIT
3.2
CPU Architecture
The FR CPU is a high-performance core employing RISC architecture and using highlevel function instructions for insertion.
■ Features
❍ Use of the RISC architecture
❍ Basic instructions, one instruction for one cycle
❍ 32-bit architecture
•
32-bit general-purpose registers: 16
❍ Linear 4G bytes memory space
❍ Multiplier mounted
•
Multiplication of 32 bits × 32 bits: 5 cycles
•
Multiplication of 16 bits × 16 bits: 3 cycles
❍ Enforced interrupt processing functions
•
High-speed response (6 cycles)
•
Multiple interrupts supported
•
Level mask function (16 levels)
❍ Enforced I/O operation instructions
•
Memory-to-memory transfer instructions
•
Bit processing instructions
❍ High code efficiency
•
Word length of a basic instruction: 16 bits
❍ Low-power consumption
•
30
Sleep mode and stop mode
CHAPTER 3 MEMORY SPACE, CPU, AND CONTROL UNIT
■ Internal Architecture
The FR family CPU uses the Harvard architecture in which the instruction bus and data bus are
mutually independent.
The bus converter for 32 bits ↔ 16 bits is connected to the data bus (D-bus) to provide the
interface between the CPU and peripheral resources.
The bus converter for Harvard ↔ Princeton is connected to both I-bus and D-bus to provide the
interface between the CPU and bus controller.
Figure 3.2-1 shows the internal architecture of the device.
Figure 3.2-1 Internal Architecture
FR
CPU
D-bus
I-bus
Harvard
Princeton
32-bit
Bus-Converter
16-bit
Bus-Converter
R-bus
C-bus
Bus-Controller
Resource
❍ CPU
The FR architecture of 32-bit RISC is compactly implemented in the CPU of this product. The
CPU uses the 5-stage instruction pipeline method to execute one instruction per cycle. The
pipeline consists of the following stages:
•
Instruction fetch (IF):
Outputs an instruction address and fetches the instruction.
•
Instruction decode (ID): Decodes the fetched instruction. Also reads a register.
•
Execution (EX):
Executes arithmetic operations.
•
Memory access (MA):
Accesses the memory (loads or stores data in the memory).
•
Write back (WB):
Writes the arithmetic operation results (or loaded memory data) to
the register.
Figure 3.2-2 shows the instruction pipeline.
31
CHAPTER 3 MEMORY SPACE, CPU, AND CONTROL UNIT
Figure 3.2-2 Instruction Pipeline
CLK
Instruction 1
Instruction 2
Instruction 3
Instruction 4
Instruction 5
Instruction 6
WB
MA
EX
ID
IF
WB
MA
EX
ID
IF
WB
MA
EX
ID
WB
MA
EX
WB
MA
WB
Instructions are not executed out of sequence. In other words, when instruction A enters the
pipeline before instruction B, it will reach the write back stage before instruction B.
Instructions are generally executed at the speed of one instruction per cycle. However, the
following instructions require multiple cycles for their execution: load and store instructions
accompanied by memory wait, branch instructions having no delay slot, and instructions having
multiple cycles.
In addition, the instruction execution speed decreases when the instruction supply is slow.
❍ Bus converter for conversion between 32 bits and 16 bits
Provides an interface between the D-bus for high-speed 32-bit access and the R-bus for 16-bit
access to enable the CPU to access the built-in peripheral circuits.
When a 32-bit access is instructed from the CPU, this bus converter converts it into two 16-bit
accesses for R-bus access. Some built-in peripheral circuits have restrictions with respect to the
access width.
❍ Bus converter for conversion between Harvard and Princeton architecture
Matches instruction and data accesses of the CPU to provide a smooth interface with external
buses.
The CPU employs the Harvard architecture, in which the instruction and data buses are
mutually independent.
The bus controller that controls the external buses employs the Princeton architecture and has a
single bus.
This bus converter assigns priority to instruction and data accesses of the CPU to control
accesses to the bus controller. With this function, the order of bus accesses to the outside is
always optimized.
This bus converter has a two-word write buffer for eliminating the bus wait time of the CPU and
a one-word prefetch buffer for fetching instructions.
32
CHAPTER 3 MEMORY SPACE, CPU, AND CONTROL UNIT
3.3
Instruction Cache
The instruction cache is temporary memory. When accessing instruction code from
external low-speed memory, the instruction cache is used to hold the code that has
been accessed once internally so that the access speed can be increased when the
same code is accessed again.
The instruction cache and instruction cache tag cannot directly be accessed for read/
write operations by software. To turn OFF the instruction cache after turning it ON, be
sure to use the subroutine described in Notes of "■Setting Method when Using ICache of This Type".
■ Configuration of the Instruction Cache
•
Basic instruction length of FR family: 2 bytes
•
Block placement method: 2-way set associative method
•
Block: One way is made up of 32 blocks.
One block has 16 bytes (= 4 sub-blocks).
One sub-block has 4 bytes (= 1 bus access unit)
Figure 3.3-1 Instruction Cache Configuration
4 bytes
4 bytes
4 bytes
4 bytes
4 bytes
I3
I2
I1
I0
Cache tag
Sub-block 3
Sub-block 2
Sub-block 1
Sub-block 0
Block 0
Cache tag
Sub-block 3
Sub-block 2
Sub-block 1
Sub-block 0
Block 31
Cache tag
Sub-block 3
Sub-block 2
Sub-block 1
Sub-block 0
Block 0
Cache tag
Sub-block 3
Sub-block 2
Sub-block 1
Sub-block 0
Block 31
Way 1
32 blocks
Way 2
32 blocks
33
CHAPTER 3 MEMORY SPACE, CPU, AND CONTROL UNIT
Figure 3.3-2 Instruction Cache Tag
Way 1
31
09
Address tag
07
SBV3
06
SBV2
05
SBV1
Sub-block valid
LRU
Entry lock
04
SBV0
03
02
TAGV Vacancy
01
LRU
00
ETLK
TAG valid
Way 2
31
09
Address tag
07
SBV3
08
Vacancy
06
SBV2
05
SBV1
Sub-block valid
04
SBV0
03
TAGV
08
Vacancy
02
01
Vacancy
00
ETLK
TAG valid
Entry lock
[bit31 to bit9] Address tag
The upper 23 bits of the memory address for the instruction cached in the corresponding
block are stored.
The memory address IA of the instruction data stored in the sub-block k of the block i is
given by:
IA = address tag × 211 + i × 24 + k × 22
IA is used to check the matching of the instruction address whose access is requested from
the CPU. The operation depends on the result of tag checking as follows:
1) If the requested instruction data exists in the cache (hit), data is transferred from the
cache to the CPU within a cycle.
2) If the requested instruction data does not exist in the cache (error), data obtained by
external access is obtained simultaneously by the CPU and the cache.
[bit7 to bit4] SBV3 to SBV0: Sub-block valid
If sub-block valid is set to "1", the current instruction data of the address indicated by the tag
in the corresponding sub-block is entered. In the sub-block, two instructions are normally
stored (excluding immediate transfer instructions).
[bit3] TAGV: TAG valid
This bit indicates whether the value of the address tag is valid. If this bit is "0", this block
becomes invalid regardless of the sub-block valid bits (for flushing).
[bit1] LRU (Way1 only)
LRU exists only in the instruction cache tag of Way1. This bit indicates, for the selected set,
whether the entry accessed last belongs to Way1 or Way2. This bit indicates that an entry in
the set of Way1 was accessed last if LRU = 1, and that an entry in the set of Way2 was
accessed last if LRU = 0.
34
CHAPTER 3 MEMORY SPACE, CPU, AND CONTROL UNIT
[bit0] ETLK: Entry lock
This bit locks all entries in the block corresponding to the tag in the cache. If ETLK = 1, all
entries are locked and are not updated when a cache error occurs. However, invalid subblocks are updated.
If a cache error occurs when both Way1 and Way2 are entry-locked, external memory is
accessed after using one cycle for determining the cache error.
■ Control Register Configuration
ICHCR (I-Cache Control Register) controls the operations of the instruction cache. Writing to
ICHCR does not affect the cache operations of instructions to be fetched within the following
three cycles.
Figure 3.3-3 Instruction Cache Control Register ICHCR (I-CacHe Control Register)
(One register shared by Way1 and Way2)
bit
7
ICHCR
Address : 000003E7H
6
5
GBLK
R/W
4
ALFL
R/W
3
EOLK
R/W
2
ELKR
R/W
1
FLSH
R/W
0
ENAB
R/W
Initial value
--000000B
Global lock
Auto-lock fail
Entry auto-lock
Entry unlock
Flush
Enable
[bit5] GBLK: Global lock
This bit locks all current entries to the cache. If GBLK = 1, valid entries in the cache will not
be updated when a cache error occurs. However, invalid sub-blocks are updated. The
instruction data fetch operation in that case is the same as that when entries are not locked.
[bit4] ALFL: Auto-lock fail
If an attempt is made to lock entries that are already locked, ALFL = 1 is set. If an attempt is
made to update an entry auto-locked entry, contrary to the user's intention, a new entry is not
locked in the cache. This bit is referred when debugging such programs. This bit can be
cleared by writing "0" to it.
[bit3] EOLK: Entry auto-lock
This bit toggles enable/disable of the auto-locking on each entry in the instruction cache.
If EOLK = 1, accessed (only when a cache error occurs) entries are locked when the entry
lock bit in the cache tag is set to "1" by hardware. Locked entries will then be excluded from
an update when a cache error occurs. However, invalid sub-blocks are updated. Set this bit
after once flushing so that locking can be carried out reliably.
[bit2] ELKR: Entry unlock
This bit specifies to clear the entry lock bit in all cache tags. The entry lock bit in all cache
tags will be cleared to "0" in the next cycle after ELKR = 1 is set. However the content in this
bit is held in only one clock cycle and will be cleared to "0" in the subsequent clock cycles.
Note:
Do not perform entry unlocking (ELKR = 1) while the instruction cache is enabled (ENAB = 1).
35
CHAPTER 3 MEMORY SPACE, CPU, AND CONTROL UNIT
[bit1] FLSH Flush
This bit specifies the flushing of the instruction cache. If FLSH = 1, contents in the cache are
flushed. However the content in this bit is held in only one clock cycle and will be cleared to
"0" in the subsequent clock cycles.
Note:
Do not perform flushing (FLSH = 1) while the instruction cache is enabled (ENAB = 1).
[bit0] ENAB Enable
This bit toggles enable/disable of the instruction cache. If ENAB = 0, the instruction cache is
disabled and the external memory is directly accessed from the CPU for instructions without
using the cache. While disabled, the contents in the cache are held.
■ Status in Each Operation Mode
❍ Cache status in each operation mode
Disable and flush indicate the status when their bits are changed by bit manipulation
instructions.
Table 3.3-1 Cache Status in Each Operation Mode
Just after
resetting
Disable
Flush
Undefined content
Immediately prior status is held.
Rewriting is not possible while disabled.
Immediately prior status is held.
Address tag
Undefined content
Immediately prior status is held.
Rewriting is not possible while disabled.
Immediately prior status is held.
Sub-block valid
Undefined content
Immediately prior status is held.
Rewriting is not possible while disabled.
Immediately prior status is held.
LRU
Undefined content
Immediately prior status is held.
Rewriting is not possible while disabled.
Immediately prior status is held.
Entry lock
Undefined content
Immediately prior status is held.
Rewriting is not possible while disabled.
Immediately prior status is held.
(Entry unlocking is required.)
TAG valid
Undefined content
Status just before is held. Flushing is
possible while disabled.
All entries are invalid.
Global lock
Unlock
Status just before is held. Rewriting is
possible while disabled.
Immediately prior status is held.
Auto-lock fail
No fail
Status just before is held. Rewriting is
possible while disabled.
Immediately prior status is held.
Entry auto-lock
Unlock
Status just before is held. Rewriting is
possible while disabled.
Immediately prior status is held.
Entry unlock
No unlocking
Status just before is held. Rewriting is
possible while disabled.
Immediately prior status is held.
Enable
Disable
Disable
Immediately prior status is held.
Flush
No flushing
Status just before is held. Rewriting is
possible while disabled.
After flushed in the cycle just
after memory access, returned
to 0.
Control register
Tag
Cache memory
36
CHAPTER 3 MEMORY SPACE, CPU, AND CONTROL UNIT
❍ Update of cache entries
Entries in the cache are updated in accordance with Table 3.3-2.
Table 3.3-2 Update of Cache Entries
Unlock
Hit
Error
Lock
Do not update.
Do not update.
Update cache entries by memory loading.
Do not update when a tag error occurs.
Update if a sub-block is invalid.
■ Area That can be Used for the Instruction Cache
•
All space can be used for instruction caching.
•
The built-in ROM is also intended for caching on a machine with a built-in ROM.
•
No instruction access to space other than the external area and built-in ROM is assumed.
Therefore, instruction access to the control register in the I/O area is intended for caching.
•
Even if the contents in the external memory are updated by DMA transfer, coherence with
the cache contents may be lost. In such case, coherence should be maintained by flushing
the cache.
■ Setting Method when Using I-Cache of This Type
1) Initialization
Before starting to use I-Cache, cache contents need to be cleared.
Delete past data by setting the Flush bit and ELKR bit of the register to "1".
ldi
ldi
#0x000003e7,r0
#0B00000110,r1
stb
r1,@r0
//
//
//
//
Address of the I-Cache control register
FLSH bit (bit1)
ELKR bit (bit2)
Write to the register.
With the above operation, the cache is initialized.
To clear the cache after starting to use it, be sure to do so while the cache is disabled.
ldi
ldi
ldi
ldi
stb
#0x000003e7,r0
#0B00000000,r1
r1,@r0
#0B00000010,r1
r1,@r0
//
//
//
//
//
Address of the I-Cache control register
FLSH bit (bit1)
Write to the register.
FLSH bit (bit1)
Write to the register.
2) Enabling (ON) the cache
To enable I-Cache, set the ENAB bit to "1".
ldi
ldi
stb
#0x000003e7,r0
#0B00000001,r1
r1,@r0
// Address of the I-Cache control register
// ENAB bit (bit0)
// Write to the register.
Instruction access hereafter will be fetched into the cache. It is also possible to simultaneously
enable the cache when it is initialized.
ldi
ldi
#0x000003e7,r0
#0B00000111,r1
stb
r1,@r0
//
//
//
//
//
Address of the I-Cache control register
ENAB bit (bit0)
FLSH bit (bit1)
ELKR bit (bit2)
Write to the register.
37
CHAPTER 3 MEMORY SPACE, CPU, AND CONTROL UNIT
3) Disabling (OFF) the cache
To disable I-Cache, set the ENAB bit to "0".
When disabling (OFF) the cache, to maintain address consistency between the instruction
cache and the CPU, perform timing synchronization using NOP, RET, and JMP after
implementing the disabling procedure as shown in the following program examples:
❍ Disabling the cache using a subroutine
ldi
ldi
stb
nop
#0x000003e7,r0
#0B00000000,r1
r1,@r0
nop
nop
ret
//
//
//
//
Address of the I-Cache control register
ENAB bit (bit0)
Write to the register.
Execute nop three times for timing
synchronization.
// Execute ret three times for timing
synchronization.
ret
ret
❍ Disabling the cache halfway through the program
ldi
#chche_off,r2
ldi
ldi
stb
nop
#0x000003e7,r0
#0B00000000,r1
r1,@r0
nop
nop
jmp
@r2
jmp
@r2
jmp
@r2
chche_off:
// Specify the jump destination after disabling
the cache.
// Address of the I-Cache control register
// ENAB bit (bit0)
// Write to the register.
// Execute nop three times for timing
synchronization.
// Execute jmp three times for timing
synchronization.
// Label
This state (same as that after the reset) is equivalent to that without cache and nothing is done
by the system.
It might be better to disable the cache if the cache overhead may be slightly high.
4) Locking all contents in the cache
Lock the cache so that instructions currently contained in the I-Cache are not driven out of the
cache. Set the GBLK bit of the register to "1".
The ENAB bit must also be set to "1". Otherwise, the cache is disabled and locked instructions
in the cache are not used.
38
ldi
ldi
#0x000003e7,r0
#0B00100001,r1
stb
r1,@r0
//
//
//
//
Address of the I-Cache control register
ENAB bit (bit0)
GBLK bit (bit5)
Write to the register.
CHAPTER 3 MEMORY SPACE, CPU, AND CONTROL UNIT
5) Locking specific instructions in the cache
To lock a specific group of instructions (such as subroutines) in the cache, set the EOLK bit to
"1" before executing them.
Locked instructions are accessed in the same manner as a high-speed internal ROM is.
ldi
ldi
#0x000003e7,r0
#0B00001001,r1
stb
r1,@r0
//
//
//
//
Address of the I-Cache control register
ENAB bit (bit0)
EOLK bit (bit3)
Write to the register.
Depending on the memory wait count, instructions after the stb instructions will be enabled.
After a group of instructions to be locked, set the EOLK bit to "0".
ldi
ldi
#0x000003e7,r0
#0B00000001,r1
stb
r1,@r0
//
//
//
//
Address of the I-Cache control register
ENAB bit (bit0)
EOLK bit (bit3)
Write to the register.
6) Unlocking the cache
Release the lock information of instructions locked in 5).
ldi
ldi
stb
ldi
stb
#0x000003e7,r0
#0B00000000,r1
r1,@r0
#0B00000100,r1
r1,@r0
//
//
//
//
//
Address of the I-Cache control register
Cache disable
Write to the register.
ELKR bit (bit2)
Write to the register.
Because only the lock information is released, locked instructions will be replaced with new
ones one after another, depending on the status of the LRU bit.
39
CHAPTER 3 MEMORY SPACE, CPU, AND CONTROL UNIT
3.4
Programming Model
This section describes the basic programming model and each register of the device.
■ Basic Programming Model
Figure 3.4-1 shows the basic programming model.
Figure 3.4-1 Basic Programming Model
32 bits
[Initial value]
R0
R1
40
…
R12
R13
R14
R15
AC
FP
SP
…
…
General-purpose register
XXXX XXXX H
XXXX XXXX H
XXXX
XXXX
XXXX
0000
XXXX H
XXXX H
XXXX H
0000 H
Program counter
Program status
Table base register
PC
PS
TBR
Return pointer
RP
XXXX XXXX H
System stack pointer
SSP
0000 0000 H
User stack pointer
USP
XXXX XXXX H
Multiplication or division
result register
MDH
MDL
XXXX XXXX H
XXXX XXXX H
⎯
ILM
⎯
XXXX XXXX H
SCR CCR
000F FC00 H
CHAPTER 3 MEMORY SPACE, CPU, AND CONTROL UNIT
■ General-purpose Registers
Figure 3.4-2 shows the configuration of the general-purpose register.
Figure 3.4-2 General-purpose Register Configuration
32 bits
R0
R1
[Initial value]
XXXX XXXXH
XXXX XXXXH
:
:
:
R12
R13
R14
R15
AC
FP
SP
XXXX XXXXH
XXXX XXXXH
XXXX XXXXH
0000 0000 H
Registers R0 to R15 are general-purpose registers. They are used as accumulators for various
types of operation or as for storing memory access pointers.
Of the 16 registers, those shown below are supposed to be used for special purposes, and
therefore some instructions have been enhanced.
•
R13: Virtual accumulator
•
R14: Frame pointer
•
R15: Stack pointer
The initial values of R0 to R14 after resetting are undefined. The initial value of R15 is
00000000H (SSP value).
41
CHAPTER 3 MEMORY SPACE, CPU, AND CONTROL UNIT
■ Program Status (PS)
This register stores the program status. It is divided into three parts: ILM, SCR, and CCR.
All the undefined bits in the figure are reserved. They always return 0 in read access. Writing
operations have no effect.
Bit position -->
31
20
16
10
8 7
0
PS
ILM
SCR
CCR
❍ Condition code register (CCR)
7
−
CCR
6
−
5
S
4
I
3
N
2
Z
1
V
0
C
(Initial value)
--00XXXXB
[bit5] S: Stack flag
Specifies the stack pointer to be used as R15.
Value
Content
0
SSP is used as R15. When EIT is generated, the flag is automatically set to 0.
(However, the value to be saved on the stack is the value before clearing.)
1
USP is used as R15.
The flag is cleared to 0 by resetting.
To execute the RETI instruction, select SSP.
[bit4] I: Interrupt enable flag
Allows or prohibits user interrupt requests.
Value
Content
0
Disables user interrupts. The flag is cleared to 0 when an INT instruction is
executed.
(However, the value to be saved on the stack is the value before clearing.)
1
Enables user interrupts.
Masking of user interrupt requests is controlled by the value stored in the ILM.
The flag is cleared to 0 by resetting.
42
CHAPTER 3 MEMORY SPACE, CPU, AND CONTROL UNIT
[bit3] N: Negative flag
Indicates the sign when the arithmetic operation result is assumed to be an integer
represented in twos-complement form.
Value
Content
0
Indicates that the result of an arithmetic operation was a positive value.
1
Indicates that the result of an arithmetic operation was a negative value.
The initial value after resetting is undefined.
[bit2] Z: Zero flag
Indicates whether the result of an arithmetic operation is "0".
Value
Content
0
Indicates that the result of an arithmetic operation is not "0".
1
Indicates that the result of an arithmetic operation is "0".
The initial value after resetting is undefined.
[bit1] V: Overflow flag
Indicates whether an overflow occurred as a result of an arithmetic operation, assuming that
the operand for the arithmetic operation is integer represented in twos-complement form.
Value
Content
0
Indicates that no overflow occurred as the result of an arithmetic operation.
1
Indicates that an overflow occurred as the result of an arithmetic operation.
The initial value after resetting is undefined.
[bit0] C: Carry flag
Indicates whether a carry or borrow from the highest bit occurred by operation.
Value
Content
0
Indicates that neither a carry nor borrow occurred.
1
Indicates that a carry or borrow occurred.
The initial value after resetting is undefined.
❍ System condition code register (SCR)
SCR
10
D1
9
D0
8
T
(Initial value)
XX0B
43
CHAPTER 3 MEMORY SPACE, CPU, AND CONTROL UNIT
[bit10, bit9] D1, D0: Step division flag
Stores intermediate data when executing step division. The flag must not be changed during
the division operation.
When another operation is performed while step division is being executed, the restart of the
step division operation is assured by saving and restoring the value of the PS register. The
initial status after resetting is undefined.
This flag is set after referring a divisor and dividend when a DIV0S instruction is executed.
This flag is forcibly cleared by the DIV0U instruction.
[bit8] T: Step trace trap flag
Specifies whether to make the step trace trap instruction effective.
Value
Content
0
Disables the step trace trap instruction.
1
Makes the step trace trap instruction effective. In this case, all user NMIs and
user interrupts are disabled.
This flag is initialized to "0" by resetting. The emulator uses the step trace trap function.
When the emulator is used, the step trace trap function cannot be used in a user program.
❍ ILM
ILM
20
ILM4
19
ILM3
18
ILM2
17
ILM1
16
ILM0
(Initial value)
01111B
This register stores an interrupt level mask value that is used for level masking.
An interrupt request to be inputted to the CPU is accepted only when the associated interrupt
level is higher than the level indicated by this ILM. The highest level value is 0 (00000B) and the
lowest level value is 31 (11111B).
Restrictions apply to the value that can be set from programs. If the original values are 16 to 31,
the values that can be set as new ones are 16 to 31. When an instruction that sets 0 to 15 is
executed, the value that is transferred is the result of adding 16 to the specified value. If the
original values are 0 to 15, any value from 0 to 31 can be set.
The register value is initialized to 15 (01111B) by resetting.
44
CHAPTER 3 MEMORY SPACE, CPU, AND CONTROL UNIT
■ Program Counter (PC)
31
0
PC
(Initial value)
XXXXXXXXH
This register indicates the address of the instruction being executed. Bit0 is set to 0 when
updating the PC during instruction execution.
Bit0 may be set to 1 only when an odd address is specified as a branch destination address.
However, bit0 is invalid in this case, and the instruction must be placed at an address that is a
multiple of 2.
The initial value at reset is undefined.
■ Table Base Register (TBR)
31
0
TBR
(Initial value)
000FFC00H
This register stores the starting address of the vector table used for EIT processing. The initial
value at reset is 000FFC00H.
■ Return Pointer (RP)
31
0
RP
(Initial value)
XXXXXXXXH
This register stores the address for return from a subroutine. When the CALL instruction is
executed, a PC value is transferred to this register. When the RET instruction is executed, the
content of the RP is transferred to the PC.
The initial value at reset is undefined.
■ System Stack Pointer (SSP)
31
SSP
0
(Initial value)
00000000H
The SSP is a system stack pointer.
When the S flag is 0, this register functions as R15. The SSP can be explicitly specified.
At EIT generation, this register is also used for the stack pointer specifying the stack for saving
the values of the PS and PC.
The initial value at reset is 00000000H.
45
CHAPTER 3 MEMORY SPACE, CPU, AND CONTROL UNIT
■ User Stack Pointer (USP)
31
0
USP
(Initial value)
XXXXXXXXH
The USP is a user stack pointer. When the S flag is 1, this register functions as R15. The USP
can be explicitly specified.
The initial value at reset is undefined.
To use the RETI instruction, use the SSP.
■ Multiplication and Division Result Registers (MDH and MDL)
31
Multiplication or division
result storage register
0
MDH
MDL
(Initial value)
XXXXXXXXH
XXXXXXXXH
These registers are used for multiplication and division. Each of them is 32 bits long. Their initial
values at reset are undefined.
❍ For multiplication
For a multiplication of 32 bits × 32 bits, the arithmetic operation result of a 64-bit length is stored
in the multiplication and division result storage registers as follows:
•
MDH: Higher 32 bits
•
MDL: Lower 32 bits
For a multiplication of 16 bits × 16 bits, the result is stored as follows:
•
MDH: Undefined
•
MDL: Result of 32 bits
❍ For division
At the start of the operation, the dividend is stored in the MDL.
When a division is performed by executing the DIV0S, DIV0U, DIV1, DIV2, DIV3, and DIV4
instructions, the result is stored in the MDL and MDH.
46
•
MDH: Remainder
•
MDL: Quotient
CHAPTER 3 MEMORY SPACE, CPU, AND CONTROL UNIT
3.5
Data Structure
The following data structures are used in the FR family:
• Bit ordering: Little endian
• Byte ordering: Big endian
■ Bit Ordering
FR family uses little-endian as bit ordering.
Figure 3.5-1 shows the bit configuration of data items according to the specified bit ordering.
Figure 3.5-1 Bit Configuration of Data Items According to Bit Ordering
bit
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MSB
LSB
■ Byte Ordering
FR family uses big-endian as byte ordering.
Figure 3.5-2 shows the byte configuration of data items according to byte ordering.
Figure 3.5-2 Byte Configuration According to Byte Ordering
MSB
bit 31
Memory
bit
7
LSB
23
15
7
0
10101010 11001100 11111111 00010001
0
10101010
11001100
11111111
Address (n + 3) 0 0 0 1 0 0 0 1
Address n
Address (n + 1)
Address (n + 2)
47
CHAPTER 3 MEMORY SPACE, CPU, AND CONTROL UNIT
3.6
Word Alignment
Instructions and data are accessed in units of bytes. The address structure depends
on the instruction length and data width.
■ Program Access
An FR family program must be located at an address that is a multiple of "2". Bit0 of the PC is
set to 0 when the PC is updated during instruction execution. Bit0 of the PC may be set to "1"
only when an odd address is specified as a branch destination address. However, bit0 is invalid
in this case, and the instruction must be placed at the address that is a multiple of "2".
There is exception allowing odd addresses.
■ Data Access
For data access, the FR family performs the following forcible alignment of addresses in
accordance with the bandwidth for data access:
Word access: Addresses are a multiple of "4" (the lower two bits are forcibly set to "00".)
Forward access: Addresses are a multiple of "2" (the lowest bit is forcibly set to "0".)
Byte access: At word or halfword data access, some bits are forcibly set to "0" for calculating the effective
address. For example, in the addressing mode of @ (R13, Ri), the register value before addition
is used for calculation (even if the LSB is "1") and the lower bits of the addition result are
masked.
The register before calculation is not masked.
[Example] LD @ (R13, R2), R0
R13
R2
00002222H
00000003H
Addition result
00002225H
+)
Lower two bits forcibly masked
Address pin
48
00002224H
CHAPTER 3 MEMORY SPACE, CPU, AND CONTROL UNIT
3.7
Special Memory Areas
This section shows a memory map of the MB91151A.
■ Memory Map of MB91151A
The address space for special memory areas is a 32-bit linear space.
Figure 3.7-1 shows a memory map of the MB91151A.
Figure 3.7-1 MB91151A Memory Map
0000 0000H
Byte data
0000 0100H
Halfword data
Direct addressing area
0000 0200H
Word data
0000 0400H
000F FC00H
Vector table initialization area
000F FFFFH
FFFF FFFFH
❍ Direct addressing area
The following area of the address space is an I/O area. This area enables an operand address
to be directly specified in an instruction by direct addressing.
The size of the address area for which direct addressing is possible differs for each data length.
•
Byte data (8 bits)
: 000H to 0FFH
•
Halfword data (16 bits) : 000H to 1FFH
•
Word data (32 bits)
: 000H to 3FFH
❍ Vector table initialization area
The area of 000FFC00H to 000FFFFFH is an EIT vector table initialization area.
The vector table used for EIT processing can be located at any address by rewriting the
contents of the TBR. However, it is located at this address after initialization by reset.
49
CHAPTER 3 MEMORY SPACE, CPU, AND CONTROL UNIT
3.8
Overview of Instructions
In addition to the general RISC instruction system, the FR family supports logical
operation instructions and bit operation instructions that were optimized for insertion,
and direct addressing instructions. See APPENDIX E "Instruction Lists" for the list of
instruction set. Each instruction is at least 16 bits long (some instructions are 32 or 48
bits long), which makes for excellent memory use efficiency.
The instruction sets can be divided into the following functional groups:
• Arithmetic operation
• Load and store
• Branch
• Logical operation and bit operation
• Direct addressing
• Others
■ Overview of Instructions
❍ Arithmetic operation
This functional group includes the standard arithmetic operation instructions (addition,
subtraction, and comparison) and shift instructions (logical shift and arithmetic operation shift).
The operations for addition and subtraction that are supported include multi-word length
operations with carry-over and operations in which flag values that are used to support address
calculation remain unchanged.
In addition, multiplication instructions of 32 bits × 32 bits and of 16 bits × 16 bits and the step
division instruction of 32 bits divided by 32 bits are provided.
The immediate data transfer instructions for setting immediate data in registers and the registerto-register transfer instructions are also provided.
The arithmetic operation instructions can use all of the general-purpose registers and
multiplication and division registers in the CPU to perform operation.
❍ Load and store
The load and store instructions are used for read and write-accesses to external memory. They
are also used for read and write-accesses to the peripheral circuit (I/O) on the chip.
The load and store instructions support three types of access lengths: byte, halfword, and word.
In addition to indirect memory addressing between general registers, some instructions support
register indirect memory addressing with displacement or with register increment and
decrement.
❍ Branch
This functional group includes branch, call, interrupt, and return instructions. Some branch
instructions have delay slots and others do not, which allows optimization in accordance with
usage.
The branch instructions are refer to "3.8.1 Branch Instructions with Delay Slots".
50
CHAPTER 3 MEMORY SPACE, CPU, AND CONTROL UNIT
❍ Logical operation and bit operation
The logical operation instructions can perform the logical operations AND, OR, and EOR
between general-purpose registers or between a general-purpose register and memory (and
I/O). The bit operation instructions can directly change the contents of the memory (and I/O).
General register indirect memory addressing is supported.
❍ Direct addressing
The direct addressing instructions are used for accesses between I/O and general-purpose
registers or between I/O and memory. High-speed and high-efficiency accesses can be
implemented by directly specifying an I/O address in an instruction, not by using register indirect
memory addressing. Some instructions support register indirect memory addressing with
register increment and decrement.
❍ Others
The following other instructions are supported: Instructions for setting flags in the PS register,
instructions for stack operations, instructions for sign and zero expansion, instructions for
function entry and exit that support high-level languages, and instructions for register multiload
and multistore.
51
CHAPTER 3 MEMORY SPACE, CPU, AND CONTROL UNIT
3.8.1
Branch Instructions with Delay Slots
During operations with delay slots, a branch occurs at an instruction immediately after
a branch instruction (called a delay slot) before the branch destination instruction is
executed.
■ Branch Instructions with Delay Slots
The following branch instructions with delay slots are provided:
JMP:D
BRA:D
BC:D
BV:D
BLE:D
@Ri
label9
label9
label9
label9
CALL:D
BNO:D
BNC:D
BNV:D
BGT:D
label12
label9
label9
label9
label9
CALL:D
BEQ:D
BN:D
BLT:D
BLS:D
@Ri
label9
label9
label9
label9
RET:D
BNE:D
BP:D
BGE:D
BHI:D
label9
label9
label9
label9
■ Explanation of the Operation for Branch Instructions with Delay Slots
During operation with delay slots, a branch occurs after an instruction immediately after the
branch instruction (called a delay slot) is executed before a branch destination instruction is
executed.
A delay slot instruction is executed before the branch operation. Consequently, the execution
speed appears to be one cycle. If an effective instruction cannot be placed in a delay slot, the
NOP instruction must be placed instead.
[Example]
; Instruction list
ADD
R1, R2
;
BRA:D LABEL
; Branch instruction
MOV
R2, R3
; Delay slot: Executed before a branch.
...
LABEL : STR3, @R4 ; Branch destination
In a conditional branch instruction, an instruction placed in a delay slot is executed regardless of
whether a branch condition is met.
For the delayed branch instruction, the execution order of some instructions appears to be
reversed. However, this appearance of reversal applies only for the PC update operation. In
other operations (register update and reference, etc.), the instructions are executed in the
specified order.
A specific example is given below.
52
CHAPTER 3 MEMORY SPACE, CPU, AND CONTROL UNIT
❍ Ri to be referred by the JMP:D @Ri or CALL:D @Ri instruction is not affected even if an
instruction in a delayed slot updates Ri.
[Example]
LDI:32
JMP:D
LDI:8
...
#Label, R0
@R0
#0, R0
; Branch to Label
; No effect on the branch destination address
❍ RP to be referred by the RET:D instruction is not affected even if an instruction in a
delayed slot updates the RP.
[Example]
RET:D
MOV R8, RP
...
; Branch to the address indicated by the previous
; value of the RP
; No effect on the return operation
❍ The flag to be referred by the Bcc: D rel instruction is not affected by a delayed slot
instruction.
[Example]
ADD
BC:D
#1, R0
Overflow
ANDCCR
#0
;
;
;
;
;
Flag change
Branch is made in accordance with the
execution result of the above instruction.
The above branch instruction does not
refer this flag update.
...
❍ When an instruction in the delayed slot of the CALL:D instruction refers the RP, the
content updated by the CALL:D instruction is read.
[Example]
CALL:D Label
MOV
RP, R0
; Branch after RP is updated
; Transfer of RP as an execution result of the above
; CALL:D
...
53
CHAPTER 3 MEMORY SPACE, CPU, AND CONTROL UNIT
■ Restrictions on Branch Instructions with Delay Slots
❍ Instructions that can be placed in delay slots
Only instructions that satisfy the following conditions can be executed in delay slots:
•
One-cycle instructions
•
Instructions other than branch instructions
•
Instructions that do not affect the operation although the execution order changes
A one-cycle instruction is indicated by writing 1, a, b, c, or d in the cycle count column of the
instruction list.
❍ Step trace trap
No step trace trap occurs between the execution of a branch instruction with the delay slot and
the delay slot.
❍ Interrupt and NMI
An interrupt and NMI are not accepted between the execution of a branch instruction with the
delay slot and the delay slot.
❍ Undefined instruction execution
No undefined instruction exception occurs if an undefined instruction exists in the delay slot. In
this case, the undefined instruction operates as the NOP instruction.
54
CHAPTER 3 MEMORY SPACE, CPU, AND CONTROL UNIT
3.8.2
Branch Instructions without a Delay Slot
This section explains the branch instructions without a delay slot. During operation
without a delay slot, the instructions are executed in the order of the instruction list.
■ Branch Instructions without a Delay Slot
The following branch instructions without a delay slot are supported:
JMP
BRA
BC
BV
BLE
@Ri
label9
label9
label9
label9
CALL
BNO
BNC
BNV
BGT
label12
label9
label9
label9
label9
CALL
BEQ
BN
BLT
BLS
@Ri
label9
label9
label9
label9
RET
BNE
BP
BGE
BHI
label9
label9
label9
label9
■ Explanation of Operation for Branch Instructions without a Delay Slot
During operation without a delay slot, the instructions are executed in the order of the instruction
list. The succeeding instruction is not executed before a branch.
[Example]
; Instruction
ADD
BRA
MOV
...
LABEL ST
list
R1, R2
LABEL
2, R3
;
; Branch instruction (without a delay slot)
; Not executed
R3, @R4 ; Branch destination
The execution cycle count of a branch instruction without a delay slot is two cycles for an
instruction with a branch and one cycle for an instruction without a branch. This increases the
instruction code efficiency as compared with branch instructions with a delay slot for which NOP
was specified because an appropriate instruction could not be entered in the delay slot. When
an effective instruction can be placed in the delay slot, the operation with a delay slot is
selected. If not, the operation without a delay slot is selected. This enables improvements with
respect to both execution speed and code efficiency.
55
CHAPTER 3 MEMORY SPACE, CPU, AND CONTROL UNIT
3.9
EIT (Exception, Interrupt, and Trap)
EIT indicates that a program being executed is suspended by an event for the purpose
of executing another program. EIT is the generic name for exception, interrupt, and
trap.
■ Notes on EIT
❍ Exception
An exception is an event that is thrown in accordance with the context of program execution.
Execution resumes later, starting at the instruction that caused the exception.
❍ Interrupt
An interrupt is an event that is thrown by hardware with no relationship to the context of the
program execution.
❍ Trap
A trap is an event that is thrown in accordance with the context of the program execution. As
with system calls, some traps are instructed by the program. Execution resumes, beginning
from the instruction following the instruction that caused the trap.
■ EIT Sources
The EIT sources are as follows:
•
Reset
•
User interrupt (internal resource, external interrupt)
•
Delayed interrupt
•
Undefined instruction exception
•
Trap instruction (INT)
•
Trap instruction (INTE)
•
Step trace trap
•
Coprocessor absence trap
•
Coprocessor error trap
■ Return from EIT
Use the RETI instruction to return from EIT.
■ Delay Slot
EIT restrictions apply to the delay slots of branch instructions.
For more information, see Section "3.8.1 Branch Instructions with Delay Slots".
56
CHAPTER 3 MEMORY SPACE, CPU, AND CONTROL UNIT
3.9.1
Interrupt Level
The interrupt levels are 0 to 31 and are controlled with five bits.
■ Interrupt Level
Table 3.9-1 shows the assignment of each interrupt level.
Table 3.9-1 Interrupt Level
Interrupt level
Binary
number
Decimal
number
Interrupt source
00000
0
-
00001
1
-
00010
2
-
00011
3
-
00100
4
INTE instruction, step trace
trap
00101 to
01110
5 to 14
01111
15
10000 to
11110
16 to 30
11111
31
Note
When the original value of the
ILM is 16 to 31, the values in
this range cannot be set in the
ILM with a program.
(System-reserved)
(System-reserved: NMI)
User interrupt is disabled while
making the ILM settings.
Interrupt
-
Interrupt is disabled while
making the ICR settings.
Operation is possible for levels 16 to 31.
Undefined instruction exceptions, coprocessor absence traps, coprocessor error traps, and INT
instructions are not affected by the interrupt levels. The level does not change the ILM, either.
■ Level Mask for Interrupts
If an interrupt request occurs, the interrupt level of the interrupt source is compared with the
level mask value stored in the ILM. When the following condition is met, the interrupt request is
masked and is not accepted:
Interrupt level of the source greater than or equal to level mask value
57
CHAPTER 3 MEMORY SPACE, CPU, AND CONTROL UNIT
3.9.2
Interrupt Stack Operation
This area is indicated by the system stack pointer (SSP). PC and PS values are saved
in or restored from this area.
After an interrupt, the PC is stored at the address indicated by the SSP and the PS is
stored at the address of (SSP + 4).
■ Interrupt Stack
Figure 3.9-1 gives an example of using the interrupt stack.
Figure 3.9-1 Interrupt Stack Operation
[Example]
SSP
[Before the interrupt]
80000000
[Example] [After the interrupt]
SSP
Memory
80000000
7FFFFFFC
7FFFFFF8
58
7FFFFFF8
Memory
80000000
7FFFFFFC
7FFFFFF8
PS
PC
CHAPTER 3 MEMORY SPACE, CPU, AND CONTROL UNIT
3.9.3
EIT Vector Table
The table base register (TBR) indicates the first address of the EIT vector table.
The vector area for EIT is a 1K byte area starting at the address indicated by the table
base register (TBR).
■ EIT Vector Table
The size per vector is four bytes. The relationship between a vector number and vector address
can be expressed as follows:
vctadr = TBR + vctofs = TBR + (03FCH - 4 × vct)
vctadr: Vector address
vctofs: Vector offset
vct: Vector number
The lower two bits of the addition result are always handled as 00.
The area of 000FFC00H to 000FFFFFH is the initial area of the vector table for reset. Some
vectors are assigned special functions. Table 3.9-2 shows the vector table for the architecture.
59
CHAPTER 3 MEMORY SPACE, CPU, AND CONTROL UNIT
Table 3.9-2 Vector Table
Vector No.
Vector address
Explanation
0
00H
000FFFFCH
Reset
1
01H
TBR + 03F8H
System-reserved
2
02H
TBR + 03F4H
System-reserved
3
03H
TBR + 03F0H
System-reserved
4
04H
TBR + 03ECH
System-reserved
5
05H
TBR + 03E8H
System-reserved
6
06H
TBR + 03E4H
System-reserved
7
07H
TBR + 03E0H
Coprocessor absence trap
8
08H
TBR + 03DCH
Coprocessor error trap
9
09H
TBR + 03D8H
INTE instruction
10
0AH
TBR + 03D4H
Instruction break exception
11
0BH
TBR + 03D0H
Operand break trap
12
0CH
TBR + 03CCH
Step trace trap
13
0DH
TBR + 03C8H
System-reserved NMI (for emulator)
14
0EH
TBR + 03C4H
Undefined instruction exception
15
0FH
TBR + 03C0H
System-reserved (NMI)
16
10H
TBR + 03BCH
Interrupt source that can be masked #0 (IRQ0)
17 to 63
11H to 3FH
TBR + 03B8H
to
TBR + 0300H
Interrupt source that can be masked #1 (IRQ2)
to
Interrupt source that can be masked #47 (IRQ47)
64
40H
TBR + 02FCH
System-reserved (used for REALOS)
65
41H
TBR + 02F8H
System-reserved (used for REALOS)
66 to 255
42H to FFH
TBR + 02F4H
to
TBR + 0000H
INT instruction
60
CHAPTER 3 MEMORY SPACE, CPU, AND CONTROL UNIT
3.9.4
Multiple EIT Processing
If two or more EIT sources occur at the same time, the CPU selects and accepts one
EIT source. After executing the EIT sequence, the CPU repeats monitoring for EIT
sources.
If no acceptable EIT source can be found at EIT source detection, the CPU executes
the instruction of the handler for the EIT source it accepted last.
Therefore, if two or more EIT sources occur at the same time, the handler execution
order of the sources depends on the following two elements:
• EIT source acceptance priority
• How other sources were masked when the source was accepted
■ EIT Source Acceptance Priority
EIT source acceptance priority means the order in which a source for EIT sequence execution is
selected after the PS and PC are saved, the PC updated as necessary, and other sources
masked. The handler of the source previously accepted is not always executed first.
Table 3.9-3 shows the EIT source acceptance priority.
Table 3.9-3 EIT Source Acceptance Priority and Masking of Other Sources
Acceptance
priority
Source
Masking for other sources
1
Reset
Other sources are discarded.
2
Undefined instruction exception
Canceled
INT instruction
I flag = 0
3
Coprocessor absence trap
None
Coprocessor error trap
4
User interrupt
ILM = level of the accepted source
5
(NMI)
ILM=15
7
INTE instruction
ILM=4
8
Step trace trap
ILM=4
Table 3.9-4 shows the execution order of the handlers for the concurrent EIT sources,
considering the mask processing for other EIT sources after an EIT source is accepted.
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CHAPTER 3 MEMORY SPACE, CPU, AND CONTROL UNIT
Table 3.9-4 EIT Handler Execution Order
Handler execution order
Source
1
Reset*1
2
Undefined instruction exception
3
Step trace trap*2
4
INTE instruction*2
5
(NMI)
6
INT instruction
7
User interrupt
Coprocessor absence trap
8
Coprocessor error trap
*1: The other sources are discarded.
*2: If the INTE instruction is subject to step execution, only the EIT for the step trace trap
occurs.
Sources caused by INTE are ignored.
Figure 3.9-2 gives an example for multiple EIT processing.
Figure 3.9-2 Example for Multiple EIT Processing
Main routine
NMI handler
Priority
(High) NMI generation
INT instruction
handler
(1) Executed first
(Low) INT instruction
execution
62
(2) Executed next
CHAPTER 3 MEMORY SPACE, CPU, AND CONTROL UNIT
3.9.5
EIT Operation
This section describes EIT operation.
Assume that the PC of the transfer source in the explanation below indicates the
address of the instruction for which an EIT source was detected.
"Address of the next instruction" means that the instruction for which EIT was
detected satisfies the following conditions:
• LDI:32: PC + 6
• LDI:20, COPOP, COPLD, COPST, and COPSV: PC + 4
• Other instructions: PC + 2
■ User Interrupt Operation
If a user interrupt request occurs, the system determines whether the request can be accepted
in the following order:
❍ Determination of whether the interrupt request can be accepted
1. The interrupt levels of concurrent requests are compared with each other. The request with
the highest level (smallest value) is selected. For an interrupt that can be masked, the value
stored by the associated ICR is used as the level for comparison.
2. If two or more interrupt requests with the same level occur, the interrupt request having the
smallest number is selected.
3. The interrupt level of the selected interrupt request is compared with the level mask value
determined by the ILM.
•
In case the interrupt level is equal to or greater than the level mask value, the interrupt
request is masked and is not accepted.
•
If the interrupt level is smaller than the level mask value, the system proceeds with step 4.
4. When the selected interrupt request can be masked and the I flag is "0", the interrupt request
is masked and is not accepted.
•
If the I flag is "1", the system proceeds with step 5.
5. When the above condition is met, the interrupt request is accepted at a pause of instruction
processing.
❍ Operation
When a user interrupt request is accepted at EIT request detection, the CPU operates as shown
below while using the interrupt number associated with the accepted interrupt request.
The items in parentheses in 1) to 7) below show the address indicated by the register.
1. SSP-4 --> SSP
2. PS --> (SSP)
3. SSP-4 --> SSP
4. Address of the next instruction --> (SSP)
5. Interrupt level of the accepted request --> ILM
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CHAPTER 3 MEMORY SPACE, CPU, AND CONTROL UNIT
6. 0 --> S flag
7. (TBR + vector offset of the accepted interrupt request) --> PC
At the end of the interrupt sequence, the CPU detects a new EIT before executing the first
instruction of the handler. If there is an acceptable EIT at this time, the CPU proceeds with the
EIT processing sequence.
■ Operation for INT Instruction
The INT #u8 instruction operates as follows:
Control branches to the interrupt handler of the vector indicated by u8.
Each item in parentheses in 1) to 7) below shows the address indicated by the register.
❍ Operation
1. SSP-4 --> SSP
2. PS --> (SSP)
3. SSP-4 --> SSP
4. PC + 2 --> (SSP)
5. 0 --> I flag
6. 0 --> S flag
7. (TBR + 3FCH - 4 × u8) --> PC
■ Operation for INTE Instruction
The INTE instruction operates as follows:
Control branches to the interrupt handler of the vector with vector number 9.
Each item in parentheses in 1) to 7) below shows the address indicated by the register.
❍ Operation
1. SSP-4 --> SSP
2. PS --> (SSP)
3. SSP-4 --> SSP
4. PC + 2 --> (SSP)
5. 00100 --> ILM
6. 0 --> S flag
7. (TBR + 3D8H) --> PC
Do not use the INTE instruction within another INTE instruction or in the step trace trap
processing routine.
No EIT is generated by INTE during step execution.
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CHAPTER 3 MEMORY SPACE, CPU, AND CONTROL UNIT
■ Operation for Step Trace Trap
If the T flag in SCR of the PS is set and the step trace function is enabled, a trap occurs and a
break in processing occurs each time one instruction is executed.
❍ The conditions for detecting a step trace trap are as follows:
1. T flag = 1
2. The instruction in execution is not a delayed branch instruction
3. An operation other than execution of the INTE instruction or the step trace trap processing
routine is being executed.
4. When the above conditions are met, a processing break occurs at a pause in operation for
the instruction.
❍ Operation
Each item in parentheses in 1) to 7) below shows the address indicated by the register.
1. SSP-4 --> SSP
2. PS --> (SSP)
3. SSP-4 --> SSP
4. Address of the next instruction --> (SSP)
5. 00100 --> ILM
6. 0 --> S flag
7. (TBR + 3CCH) --> PC
When the T flag is set and the step trace trap is enabled, both user NMI and user interrupt are
disabled.
No EIT is generated by the INTE instruction in this case.
■ Operation for an Undefined Instruction Exception
If an undefined instruction is detected at instruction decoding, an undefined instruction
exception occurs.
❍ The conditions for detecting the undefined instruction exception are as follows:
1. An undefined instruction is detected at instruction decoding.
2. The instruction is located outside the delay slot (not immediately after the delayed branch
instruction).
3. When the above conditions are met, an undefined instruction exception occurs, causing a
break.
❍ Operation
Each item in parentheses in 1) to 6) below shows the address indicated by the register.
1. SSP-4 --> SSP
2. PS --> (SSP)
3. SSP-4 --> SSP
4. PC --> (SSP)
5. 0 --> S flag
6. (TBR + 3C4H) --> PC
The address of the instruction that detected the undefined instruction exception is saved in the
PC.
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CHAPTER 3 MEMORY SPACE, CPU, AND CONTROL UNIT
■ Coprocessor Absence Trap
If there is an attempt to execute a coprocessor instruction for a coprocessor that is not mounted,
a coprocessor absence trap occurs.
❍ Operation
Each item in parentheses in 1) to 6) below shows the address indicated by the register.
1. SSP-4 --> SP
2. PS --> (SSP)
3. SSP-4 --> SSP
4. Address of the next instruction --> (SSP)
5. 0 --> S flag
6. (TBR + 3E0H) --> PC
■ Coprocessor Error Trap
Assume that an error occurred while the coprocessor was used. When a coprocessor instruction
using that coprocessor is executed next, a coprocessor error trap occurs.
Note:
The MB91151A is not equipped with a coprocessor.
❍ Operation
Each item in parentheses in 1) to 6) below shows the address indicated by the register.
1. SSP-4 --> SP
2. PS --> (SSP)
3. SSP-4 --> SSP
4. Address of the next instruction --> (SSP)
5. 0 --> S flag
6. (TBR + 3DCH) --> PC
■ Operation for RETI Instruction
The RETI instruction returns from the EIT processing routine.
❍ Operation
Each item in parentheses in 1) to 4) below shows the address indicated by the register.
1. (R15) --> PC
2. R15 + 4 --> R15
3. (R15) --> PS
4. R15 + 4 --> R15
Note that the stack pointer to be referred for returning the PS and PC is selected in accordance
with the content of the S flag. To execute the instruction that manipulates R15 (stack pointer) in
the interrupt handler, set the S flag to 1 to use the USP as R15. In this case, be sure to return
the S flag to 0 before executing the RETI instruction.
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CHAPTER 3 MEMORY SPACE, CPU, AND CONTROL UNIT
3.10 Reset Sequence
This section describes the reset operation for placing the CPU in operation status.
■ Reset Sources
The causes for reset are as follows:
•
Input from an external reset pin
•
Software reset by the SRST bit operation of the standby control register (STCR)
•
Count-up of the watchdog timer
•
Power-on reset
■ Initialization by Reset
If a reset source occurs, the CPU is initialized.
❍ Releasing the reset source from an external reset pin or software reset
•
Set the pin to the specified status.
•
Set each resource in the device to reset status. The control register is initialized to the
predetermined value.
•
The slowest gear is selected as a clock.
■ Reset Sequence
When a reset source is released, the CPU executes the following reset sequence:
(000FFFFCH) --> PC
Note:
After reset, the operating mode must be set via the mode register.
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CHAPTER 3 MEMORY SPACE, CPU, AND CONTROL UNIT
3.11 Operation Mode
The FR family controls the operation mode using the mode pins (MD2, MD1, MD0) and
mode register (MODR).
■ Operation Mode
Two operation modes, bus mode and access mode, are used.
Bus mode
Access mode
Single chip
Internal ROM external bus
32-bit bus
16-bit bus
8-bit bus
External ROM external bus
❍ Bus mode
In bus mode, the FR family controls the operations of the internal ROM and external access
function. The mode setting pins (MD2, MD1, MD0) and the M1 and M0 bits of the mode register
(MODR) are used to specify the bus mode.
❍ Access mode
In access mode, the FR family controls the width of the external data bus. The mode setting
pins (MD2, MD1, MD0) and BW1 and BW0 bits of AMD0, AMD1, AMD32, AMD4, and AMD5
address mode registers are used to specify the access mode.
■ Mode Pins
Three pins MD2, MD1, and MD0 are used to specify operation modes as shown in Table 3.11-1.
Table 3.11-1 Mode Pins and Set Mode
Mode pin
Mode name
Reset
vector
access
area
Width of
external
data bus
Remarks
MD2
MD1
MD0
0
0
0
External vector mode 0
External
8 bits
0
0
1
External vector mode 1
External
16 bits
0
1
0
External vector mode 2
External
32 bits
Cannot be used in this model
0
1
1
Internal vector mode
Internal
(Mode register)
Single-chip mode*
1
-
-
-
-
External bus mode
-
*: Cannot be used in this model
68
Cannot be used
CHAPTER 3 MEMORY SPACE, CPU, AND CONTROL UNIT
■ Mode Data
The data written at "0000 07FFH" by the CPU after a reset is called mode data.
A mode register (MODR) is allocated at "0000 07FFH". After data is set in this register, the
system runs in the mode specified by this register. Data can be written to the mode register only
once after resetting.
The setting in this register becomes effective immediately after writing.
MODR
bit
Address:
0000 07FFH
7
M1
6
M0
5
*
4
*
3
*
2
*
1
*
0
*
Initial value
XXXXXXXXB
Access
W
Bus mode setting bits
[bit7, bit6] M1, M0
These bits set the bus mode. Specify the bus mode to be used after mode register writing.
M1
M0
Function
0
0
0
1
Internal RAM external bus mode
-
1
0
External bus mode
-
1
1
Single-chip mode
-
Remarks
This setting is not allowed in this
model
This setting is not allowed
Note:
The value of 01B and 10B are allowed in this model.
[bit5 to bit0] *
These bits are reserved for the system.
Note:
Keep these bits set to 0.
❍ Notes on writing to MODR
Before writing to MODR, be sure to set AMD0 to AMD5 to decide the bus width of each Chip
Select (CS) area.
MODR has no bits for setting the bus width.
As for bus width, the value set for mode pins MD2 to MD0 is effective before MODR writing, and
the value set in BW1 and BW0 of AMD0 to AMD5 is effective after MODR writing.
For instance, an external reset vector is normally handled in Area 0 (in which CS0 is active) and
the bus width is determined by mode pins MD2 to MD0. Suppose MD2 to MD0 are set to
determine the bus width as 32 bits or 16 bits, while nothing is set in AMD0 (default bus width of
8 bits). If MODR is written under this condition, area 0 enters 8-bit bus mode, which results in a
malfunction.
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CHAPTER 3 MEMORY SPACE, CPU, AND CONTROL UNIT
To prevent this problem, always set AMD0 to AMD5 before writing to MODR.
MODR writing
RST (reset)
Bus width specification: MD2, MD1, MD0 → BW1, BW0 of AMD0 to AMD5
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CHAPTER 3 MEMORY SPACE, CPU, AND CONTROL UNIT
3.12 Clock Generator (Low-Power Consumption Mechanism)
The clock generator is a module for the following functions:
• CPU clock generation (this includes the gear function)
• Peripheral clock generation (this includes the gear function)
• Generating resets and storing sources
• Standby function
• Built-in PLL (gradual-double circuit)
■ Register Configuration of Clock Generator
Figure 3.12-1 shows the registers of the clock generator.
Figure 3.12-1 Registers of the Clock Generator
Address
000480H
000481H
000482H
000483H
000484H
000485H
000488H
7
0
RSRR/WTCR
STCR
PDRR
CTBR
GCR
WPR
PCTR
Reset source and watchdog cycle control register
Standby control register
DMA request suppression register
Timebase timer clear register
Gear control register
Watchdog reset generation delay register
PLL control register
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CHAPTER 3 MEMORY SPACE, CPU, AND CONTROL UNIT
■ Block Diagram of the Clock Generator
Figure 3.12-2 shows the block diagram of the clock generator.
Figure 3.12-2 Block Diagram of the Clock Generator
[Gear control block]
GCR register
CPU gear
Peripheral
gear
1/2
Oscillation
circuit
X0
X1
PLL
Internal clock
generation
circuit
M
P
X
CPU Clock
Internal bus clock
Internal peripheral clock
[Stop and sleep control block]
Internal interrupt
Internal reset
STCR register
DMA request
PDRR register
STOP status
SLEEP status
CPU hold request
Status
transition
control circuit
Reset
generation
F/F
Power-on detection circuit
[Reset source circuit]
VCC
R
GND
RSRR register
RST pin
[Watchdog control block]
WPR register
Watchdog F/F
Count clock
CTBR register
Timebase timer
72
Internal reset
CHAPTER 3 MEMORY SPACE, CPU, AND CONTROL UNIT
3.12.1 Reset Source Register (RSRR) and Watchdog Cycle
Control Register (WTCR)
The reset source register (RSRR) is used to store the type of the generated reset. The
watchdog cycle control register (WTCR) is used to specify the cycle of the watchdog
timer.
■ Reset Source Register (RSRR) and Watchdog Cycle Control Register (WTCR)
The reset source register (RSRR) and watchdog cycle control register (WTCR) are configured
as follows:
RSRR/WTCR
bit
Address: 000480H
7
6
PONR
−
(R)
(−)
5
4
WDOG ERST
(R)
(R)
3
2
1
0
SRST
−
WT1
WT0
(R)
(−)
(W)
(W)
Initial value after
power-on
1-XX X-00B
[bit7] PONR
If this bit is 1, the last reset was a power-on reset, and bits other than this bit are invalid.
[bit6] (Reserved)
This bit is a reserved bit. Its value during read accesses is undefined.
[bit5] WDOG
If this bit is 1, the last reset was a watchdog reset.
[bit4] ERST
If this bit is 1, the last reset was caused by the external reset pin.
[bit3] SRST
If this bit is 1, the last reset was caused by a software reset request.
[bit2] (Reserved)
This bit is reserved. Its value during read accesses is undefined.
[bit1, bit0] WT1 and WT0
These bits specify the watchdog cycle. The relationship between these bits and the cycle to
be selected is shown below. These bits are initialized by all resets.
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CHAPTER 3 MEMORY SPACE, CPU, AND CONTROL UNIT
WT1
WT0
Interval of writing to the
required minimum WPR to
suppress watchdog reset
generation
0
0
φ × 215 (Initial value)
φ × 215 to φ × 216
0
1
φ × 217
φ × 217 to φ × 218
1
0
φ × 219
φ × 219 to φ × 220
1
1
φ × 221
φ × 221 to φ × 222
Time from writing the last
5AH to the WPR to
watchdog reset generation
However, for GCR CHC = 1, the cycle of φ is two cycles of X0. For GCR CHC = 0, it is one
cycle of X0.
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CHAPTER 3 MEMORY SPACE, CPU, AND CONTROL UNIT
3.12.2 Standby Control Register (STCR)
The standby control register (STCR) controls standby operation and specifies the
oscillation stabilization wait time.
■ Standby Control Register (STCR)
The register is configured as follows:
STCR
bit
7
6
5
4
3
2
HIZX SRST OSC1 OSC0
(R/W) (R/W) (R/W) (W) (R/W) (R/W)
Address: 000481H STOP SLEP
1
−
(−)
0
−
(−)
Initial value
0001 11--B
[bit7] STOP
If this bit is set to 1, the stop status is entered to stop the internal peripheral clock, internal
CPU clock, and oscillation.
[bit6] SLEP
If this bit is set to 1, the standby status is entered to stop the internal CPU clock. If both the
STOP bit and this bit are set to 1, the STOP bit is given priority and stop status is entered.
[bit5] HIZX
If the stop status is entered while this bit is 1, the device pin is set to high impedance.
[bit4] SRST
If this bit is set to 0, a software reset request is generated.
Its value during read access is undefined.
[bit3, bit2] OSC1 and OSC0
These bits specify the oscillation stabilization wait time. The relationship between these bits
and the cycle to be selected is shown below. These bits are initialized by power-on reset and
are not affected by other reset sources.
OSC1
OSC0
Oscillation stabilization wait time
0
0
φ × 23 80msx2x8
0
1
φ × 216
1
0
φ × 218
1
1
φ × 213 (Initial value)
However, for GCR CHC = 1, the cycle of φ is two cycles of X0. For GCR CHC = 0, it is one
cycle of X0.
[bit1, bit0] (Reserved)
These bits are reserved. Their values during read accesses are undefined.
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CHAPTER 3 MEMORY SPACE, CPU, AND CONTROL UNIT
3.12.3 Timebase Timer Clear Register (CTBR)
This register is used to initialize the timebase timer to 0.
■ Timebase Timer Clear Register (CTBR)
The register is configured as follows:
CTBR
bit
Address: 000483H
7
D7
(W)
6
D6
(W)
5
D5
(W)
4
D4
(W)
3
D3
(W)
2
D2
(W)
1
D1
(W)
0
D0
(W)
Initial value
XXXX XXXXB
[bit7 to bit0] D7 to D0
If A5H and 5AH are consecutively written to this register, the timebase timer is set to "0"
immediately after 5AH was written. The value of this register during read accesses is
undefined. There are no restrictions with respect to the time between writing A5H and 5AH.
Note:
If the timebase timer is cleared by using this register, the oscillation stabilization wait interval,
watchdog cycle, and peripheral cycle using the timebase change temporarily.
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CHAPTER 3 MEMORY SPACE, CPU, AND CONTROL UNIT
3.12.4 Gear Control Register (GCR)
This register controls the gear function of the CPU and peripheral system clocks.
■ Gear Control Register (GCR)
The register is configured as follows:
GCR
bit
7
Address: 000484H CCK1
(R/W)
6
CCK0
(R/W)
5
4
DBLAK DBLON
(R)
(R/W)
3
2
1
0
PCK1
PCK0
−
CHC
(R/W)
(R/W)
(−)
(R/W)
Initial value
1100 11-1B
❍ [bit7, bit6] CCK1 and CCK0
These bits specify the CPU system gear cycle. The relationship between these bits and the
cycle to be selected is shown below. These bits are initialized at reset.
CPU machine clock (oscillation: input frequency
from X0)
CCK1
CCK0
CHC
0
0
0
PLL × 1
0
1
0
PLL × 1/2
1
0
0
PLL × 1/4
1
1
0
PLL × 1/8
0
0
1
Oscillation × 1/2
0
1
1
Oscillation × 1/2 × 1/2
1
0
1
Oscillation × 1/2 × 1/4
1
1
1
Oscillation × 1/2 × 1/8 (Initial value)
❍ [bit5] DBLAK
This bit indicates a clock doubler operation status. This bit is read-only, and attempts to access
it for writing are ignored. The bit is initialized at reset.
A time lag occurs when switching the bus frequency. However, this bit allows checking whether
switching was actually performed.
DBLAK
Internal operating frequency: same as external operating frequency
0
Operating in 1:1 relationship (Initial value)
1
Operating in 2:1 relationship
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CHAPTER 3 MEMORY SPACE, CPU, AND CONTROL UNIT
❍ [bit4] DBLON
This bit specifies the operation status of the clock doubler. It is initialized at reset.
DBLON
Internal operating frequency: same as external operating frequency
0
Operating in 1:1 relationship (Initial value)
1
Operating in 2:1 relationship
[bit3, bit2] PCK1 and PCK0
These bits specify the peripheral system gear cycle. The relationship between these bits and
the cycle to be selected is shown below. These bits are initialized at reset.
Peripheral machine clock (oscillation: input
frequency from X0)
PCK1
PCK0
CHC
0
0
0
PLL × 1
0
1
0
PLL × 1/2
1
0
0
PLL × 1/4
1
1
0
PLL × 1/8
0
0
1
Oscillation × 1/2
0
1
1
Oscillation × 1/2 × 1/2
1
0
1
Oscillation × 1/2 × 1/4
1
1
1
Oscillation × 1/2 × 1/8 (Initial value)
[bit0] CHC
This bit specifies the divided-by-2 system or PLL system of the oscillation circuit as the basic
clock.
Setting this bit to 1 specifies the divided-by-2 system. Setting this bit to 0 specifies the PLL
system.
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CHAPTER 3 MEMORY SPACE, CPU, AND CONTROL UNIT
3.12.5 Watchdog Reset Generation Delay Register (WPR)
The watchdog reset generation delay register (WPR) is used for clearing the watchdog
timer flip-flop. It can delay the watchdog reset generation.
■ Watchdog Reset Generation Delay Register (WPR)
The register is configured as follows:
WPR
bit
Address: 000485H
7
D7
(W)
6
D6
(W)
5
D5
(W)
4
D4
(W)
3
D3
(W)
2
D2
(W)
1
D1
(W)
0
D0
(W)
Initial value
XXXX XXXXB
[bit7 to bit0] D7 to D0
When A5H and 5AH are consecutively written to this register, the watchdog timer flip-flop is
cleared to 0 immediately after 5AH in order to delay watchdog reset generation.
The value of this register during read accesses is undefined. The time between A5H and 5AH
is not restricted. However, if neither of these values is written within the period listed in the
table below, a watchdog reset occurs.
STCR
Minimum interval required for
writing to WPR to suppress
watchdog reset generation
Time from the last time 5AH was
written to the WPR to watchdog reset
generation
WT1
WT0
0
0
φ × 215
φ × 215 to φ × 216
0
1
φ × 217
φ × 217 to φ × 218
1
0
φ × 219
φ × 219 to φ × 220
1
1
φ × 221
φ × 221 to φ × 222
However, for GCR CHC = 1, the cycle of φ is two cycles of X0. For GCR CHC = 0, it is one
cycle of PLL.
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CHAPTER 3 MEMORY SPACE, CPU, AND CONTROL UNIT
3.12.6 DMA Request Suppression Register (PDRR)
The DMA request suppression register (PDRR) temporarily suppresses a DMA request
so as to enable CPU operation.
■ DMA Request Suppression Register (PDRR)
The register is configured as follows:
PDRR
bit
Address: 000482H
15
−
(−)
14
−
(−)
13
−|
(−)
12
−
(−)
11
10
9
8
D3
D2
D1
D0
(R/W) (R/W) (R/W) (R/W)
Initial value
---- 0000B
[bit11 to bit8] D3 to D0
If these bits are set to a value other than 0, DMA transfer from subsequent DMAs to the CPU
is suppressed. Afterwards, DMA can be used only when these bits are set to 0.
Note:
Do not use the PDRR register alone. Be sure to use it together with HRCL register.
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CHAPTER 3 MEMORY SPACE, CPU, AND CONTROL UNIT
3.12.7 PLL Control Register (PCTR)
The PLL control register (PCTR) controls PLL oscillations.
The setting of this register can be changed only when GCR CHC is 1.
■ PLL Control Register (PCTR)
The PLL control register (PCTR) has the following configuration:
PCTR
bit
15
14
SLCT1
SLCT0
Address: 000488H
(R/W) (R/W)
13
12
11
10
9
8
−
−
VSTP
−
−
−
(−)
(−)
(R/W)
(−)
(−)
(−)
Initial value
00XX 0XXXB
[bit15, bit14] SLCT1 and SLCT0
These bits control the multiply ratio of the PLL. They are initialized only at power-on.
The setting of these bits indicates the internal operating frequency when GCR CHC is set to
0.
SLCT1
SLCT0
Internal operating frequency (oscillation: 16.5 MHz)
0
0
8.25MHz operation (Initial value)
0
1
16.5MHz operation
1
X
33.0MHz operation
[bit13, bit12, bit10 to bit8] Reserved
Always set these bits to 0. Their values during read access are undefined.
[bit11] VSTP
This bit controls the PLL oscillation. It is initialized at power-on or an external reset.
If PLL is used in stopped state, it must be stopped every time the reset is canceled.
VSTP
PLL operation
0
Oscillation (Initial value)
1
Stop of oscillation
Note:
When the stop mode is entered, the PLL stops regardless of the setting of this bit.
81
CHAPTER 3 MEMORY SPACE, CPU, AND CONTROL UNIT
3.12.8 Watchdog Function
The watchdog function can detect a "program crashed" status. Assume that A5H and
5AH could not be written to the watchdog reset delay register within the given time due
to a program crash. In this case, the watchdog timer generates a watchdog reset
request.
■ Block Diagram of the Watchdog Control Block
Figure 3.12-3 shows a block diagram of the watchdog control block.
Figure 3.12-3 Block Diagram of the Watchdog Control Block
M
P
X
Edge
Detect
Reset
generation F/F
Watchdog
F/F
Time-base
timer
Latch
Status decoder
Reset status transition
request signal
clear
CTBR
WT1,
WT0
Internal reset
Status transition
control circuit
WPR
A5&5A
RSRR
WDOG
Internal bus
■ Activating the Watchdog Timer
The watchdog timer starts its operation when a value is written to the watchdog control register
(WTCR). The interval time of the watchdog timer is set with bits WT1 and WT0. Only the time
set in the first writing operation becomes valid as the interval time. Subsequent settings are
ignored.
[Example]
LDI:8
LDI:32
STB
82
#10000000B ,R1 ; WT1,0=10
#WTCR,R2
R1,@R2
; Watchdog activation
CHAPTER 3 MEMORY SPACE, CPU, AND CONTROL UNIT
■ Delaying Reset Generation
Once the watchdog timer is activated, the program must periodically write A5H and 5AH to the
watchdog reset delay register (WPR).
The watchdog reset flip-flop stores the falling edge of the tap selected by the timebase timer. If
this flip-flop is not cleared at the second falling edge, a reset is generated.
Figure 3.12-4 shows the timing of watchdog timer operation.
Figure 3.12-4 Timing of Watchdog Timer Operation
Time-base timer overflow
Watchdog flip-flop
WTE write
Watchdog activation
watchdog reset generation
Watchdog clear
■ Causes of Reset Delays Other than Programs
The following cause the watchdog timer to automatically delay generation of a reset:
1. Stop or sleep state
2. DMA transfer
3. A break occurs when the emulator debugger or the monitor debugger is being used.
4. The INTE instruction is executed.
5. Step trace trap (a break occurs at each instruction by specifying 1 for T in the PS register)
Notes:
• There is no rule for the writing interval between the first A5H and the next 5AH. The watchdog
reset can be delayed only when the interval between two instances of writing 5AH is within the
time specified by the WT1, WT0 bit and A5H is written at least once between these two
instances of writing 5AH.
• If a value other than 5AH is written after the first A5H, the first A5H written is invalidated. In this
case, A5H must be written again.
■ Timebase Timer
The timebase timer is used for supplying clock pulses to the watchdog timer and for waiting for
oscillation stabilization time. For GCR CHC = 1, the cycle of the operating clock φ is two cycles
of X0. For GCR CHC = 0, it is one cycle of X0.
Figure 3.12-5 shows the configuration of timebase timer.
Figure 3.12-5 Timebase Timer Configuration
1/21
1/2 2
1/2 3
.
.
.
.
.
.
1/2 18
1/2 19
1/2 20
1/2 21
83
CHAPTER 3 MEMORY SPACE, CPU, AND CONTROL UNIT
3.12.9 Gear Function
The gear function allows the elimination of some clock pulses from clock signals. It
has two independent circuits: A CPU and a peripheral circuit. These circuits allow the
exchange of data between the CPU and peripherals even when the gear ratio is
different. This function also allows to specify whether to use the same clock cycle as
that of the oscillation circuit or that from the divided-by-2 circuit.
■ Block Diagram of the Gear Control Block
Figure 3.12-6 shows a block diagram of the gear control block.
Figure 3.12-6 Block Diagram of the Gear Control Block
X0
X1
Oscillation
circuit
CPU clock system
gear interval
generation circuit
CHC
Peripheral clock
system gear
interval generation
circuit
1/2
(Gradually doubled)
PLL
Selection
circuit
Internal bus
CCK1,
CCK0
PCK1,
PCK0
Internal clock generation circuit selection circuit
CPU system gear interval
indication signal
Peripheral system gear
interval indication signal
84
CPU clock
Internal bus clock
Internal
peripheral clock
CHAPTER 3 MEMORY SPACE, CPU, AND CONTROL UNIT
■ Settings of the Gear Function
For the CPU clock control, the desired gear ratio can be set by setting the CCK1 and CCK0 bits
of the gear control register (GCR) to the desired values. For the peripheral clock control, the
desired gear ratio can be set by setting the PCK1 and PCK0 bits of that register to the desired
values.
[Example 1]
LDI:32 #GCR,R2
LDI:8 #11111100B,R1 ; CCK=11,PCK=11,CHC=0
STB
R1,@R2
; CPU clock=1/8f, Peripheral clock=1/8f,
f=direct
LDI:8 #01111000B,R1 ; CCK=01,PCK=10,CHC=0
STB
R1,@R2
; CPU clock=1/2f, Peripheral clock=1/4f,
f=direct
LDI:8 #00111000B,R1 ; CCK=00,PCK=10,CHC=0
STB
R1,@R2
; CPU clock=f, Peripheral clock=1/4f, f=direct
LDI:8 #00110000B,R1 ; CCK=00,PCK=00,CHC=0
STB
R1,@R2
; CPU clock=f, Peripheral clock=f, f=direct
LDI:8 #10110000B,R1 ; CCK=10,PCK=00,CHC=0
STB
R1,@R2
; CPU clock=1/4f, Peripheral clock=f, f=direct
When the CHC bit of the gear control register is set to 1, the output of the divided-by-2 circuit is
selected as the original clock. When it is set to 0, the same clock cycle as that from the
oscillation circuit is used as it is.
To switch the original clock, the change with respect to the CPU and peripheral system is made
at the same time.
[Example 2]
LDI:8
LDI:32
STB
LDI:8
STB
LDI:8
STB
#01110001B,R1
#GCR,R2
R1,@R2
#00110001B,R1
R1,@R2
#00110000B,R1
R1,@R2
; CCK=01,PCK=00,CHC=1
;
;
;
;
;
CPU clock=1/2f, Peripheral clock=f, f=1/2xtal
CCK=00,PCK=00,CHC=1
CPU clock=f, Peripheral clock=f, f=1/2xtal
CCK=00,PCK=00,CHC=0
CPU clock=f, Peripheral clock=f, f=direct
Figure 3.12-7 shows the timing for gear switching.
Figure 3.12-7 Timing for Gear Switching
Original clock
CPU clock (a)
CPU clock (b)
Peripheral clock (a)
Peripheral clock (b)
CHC
CCK value
PCK value
01
00
00
85
CHAPTER 3 MEMORY SPACE, CPU, AND CONTROL UNIT
3.12.10 Retaining a Reset Source
The system stores the last generated reset source. All related flags are set to 0 during
a read access.
A source flag that was set remains as long as it is not read.
■ Block Diagram of the Reset Source Retention Circuit
Figure 3.12-8 shows the block diagram of the reset source retention circuit.
Power-on detection
PONR
PONR
WDOG
WDOG
ERST
ERST
SRST
SRST
watch-dog Timer
reset detect Circuit
RST pin
Reset input circuit
Internal bus
Figure 3.12-8 Block Diagram of the Reset Source Retention Circuit
SRST
Status
transition
circuit
decoder
.or.
■ Setting
No special setting is required to use this function. Set the instruction for reading the reset source
register and the instruction for branching to an appropriate program at the beginning of the
program to be stored at the reset entry address.
[Example]
RESET-ENTRY
LDI:32 #RSRR,R10
LDI:8 #10000000B ,R2
LDUB
@R10,R1
MOV
R1,R10
AND
R2,R10
BNE
PONR-RESET
LSR
#1,R2
MOV
R1,R10
AND
R2,R10
BNE
WDOG-RESET
...
86
; GET RSRR VALUE INTO R1
; R10 USED AS A TEMPORARY REGISTER
; WAS PONR RESET?
; POINT NEXT BIT
; R10 USED AS A TEMPORARY REGISTER
; WAS WATCH DOG RESET?
CHAPTER 3 MEMORY SPACE, CPU, AND CONTROL UNIT
Notes:
• If the PONR bit is "1", consider the other bits as being undefined. When a check of reset sources
is to be performed afterwards, be sure to place the instruction for confirming power-on reset at
the beginning.
• Any reset source check other than a power-on reset check can be performed at any location.
The priority of the sources depends on the order in which the check was performed.
87
CHAPTER 3 MEMORY SPACE, CPU, AND CONTROL UNIT
3.12.11 Example of Setting the PLL Clock
This section gives an example of setting the PLL clock and also provides an example
of the related assembler source code.
■ Example of Setting the PLL Clock
Figure 3.12-9 gives an example of the procedure for switching to 33-MHz operation using the
PLL.
Figure 3.12-9 Example of Setting the PLL Clock
CHC = 1
Yes
DBLON = 1
Yes
No
Before making the PLL-related settings, be sure to
switch to the clock signal of the divided-by-2
system.
CHC ← 1
No
The gear is fixed to CPU = 1/1 by setting the
doubler to ON. The peripheral system can be set
arbitrarily.
(Note: If no external bus is used, the doubler need
not be used. In this case, the CPU gear can
arbitrarily be set as well.)
DBLON ← 1
DBLAK = 1
No
Yes
VSTP = 0
Yes
No
VSTP ← 0
If the PLL stops, it restarts automatically. However,
for PLL restart, the software needs a stabilization
wait time of 300 s or more.
WAIT 300 s
SLCTO ← 1
CHC ← 0
The output tap from the PLL is switched to 33 MHz.
The clock is switched from the divided-by-2 system
to the PLL system.
Notes:
• No particular setting order of the DBLON, VSTP, and SLCT1 bits shown here was specified in
the example.
• For a restart of PLL, be sure to program a wait time of at least 300µs or more to ensure
stabilization.
Ensure that the wait time does not become insufficient by cache ON or OFF operations.
88
CHAPTER 3 MEMORY SPACE, CPU, AND CONTROL UNIT
■ Reference Chart for the Clock System
Figure 3.12-10 shows the reference chart for the clock system.
Figure 3.12-10 Reference Chart for the Clock System
16.5MHz
Oscillation input
1/2
PLL system input
PLL
1/2
VSTP
Divided-by-2
system input
1/2
33MHz
16.5MHz
SLCT0
1x
01
00
1/2
8..25 MHz
PCTR register
CHC
1
0
CCK1,0
1/1
1/2
1/4
1/8
DBLON
CPU system
Bus system
CPU system gear
Peripheral system gear
PCK1,0
1/1
1/2
1/4
1/8
Peripheral system
GCR register
89
CHAPTER 3 MEMORY SPACE, CPU, AND CONTROL UNIT
■ Example of the Related Assembler Source Code (Example of Switching to the PLL System)
; *******************************************
;
PLL Sample Program
; *******************************************
; Load Setting Data
ldi:20 #GCR, R0
ldi:20 #PCTR,R1
ldi:8
#GCR_MASK,R2
; GCR_MASK = 0000 0001 b
ldi:8
#PCTR_MASK,R3
; PCTR_MASK = 0000 1000 b
ldub
@R0,R4
; read GCR register
ldub
@R1,R5
; read PCTR register
st
PS,@-R15
; push processor status
stilm
#0x0
; disable interrupt
;
and
R4,R2
beq
CHC_0
bra
CHC_1
CHC_0:
borl
#0001B ,@r0
; to 1/2 clock @r0=GCR register
CHC_1:
call
VCO_RUN
call
DOUBLER_ON
PLL_SET_END:
ld
@R15+,PS
; pop processor status
; *******************************************
;
VCO Setting
; *******************************************
VCO_RUN:
st
R3,@-R15
; push R3
ldi:8
#PCTR _MASK,R3
; PCTR_MASK = 0000 1000 b
and
R5,R3
; PCTR->VSTP=1 ?
beq
LOOP_300US_END
; if VSTP = 0 return
st
R2, @-R15
; push R2 for Loop counter
bandl
#0111B ,@r1
; set VSTP = 0
ldi:20 #0x41A,R2
; wait 300µS
WAIT_300US:
; 300µs = 160ns(6.25MHz) * 7 * 300 (834)cycle
add2
#(-1),R2
; 834h/2 = 41Ah (if cache on)
bne
WAIT_300US
;
LOOP_300US_END:
ld
@R15+,R2
; Pop R2
ld
@R15+,R3
; Pop R3
ret
; *******************************************
;
doubler ON
; *******************************************
DOUBLER_ON:
borh
#0001B ,@r0
; doubler ON
LOOP_DBLON1:
btsth
#0010B ,@r0
; check DBLAK
beq
LOOP_DBLON1
; loop while DBLAK = 0
bandl
#1110B ,@r0
; to 1/1(PLL) clock
nop
nop
nop
nop
nop
nop
ret
90
CHAPTER 3 MEMORY SPACE, CPU, AND CONTROL UNIT
3.13 Low-Power Consumption Mode
The low-power consumption mode has stop and sleep status.
■ Overview of the Stop Status
The stop status means a state in which all internal clocks and oscillation circuit operation are
stopped. It can minimize power consumption.
To enter the stop status, use an instruction to write to the standby control register (STCR).
To return from the stop status, use one of the following methods:
•
Set an interrupt request (However, there are restrictions with respect to the peripherals that
can generate interrupt requests even in stop status.)
•
Applying the "L" level to the RST pin
In stop status, all internal clocks stop. In this state, built-in peripherals other than those that can
generate a return interrupt enter stop status.
■ Overview of the Sleep Status
The sleep status means a status in which the CPU clock and internal bus clock are stopped. It
can suppress power consumption to some extent in a situation in which no CPU operation is
required.
To enter the sleep status, use an instruction to write to the standby control register (STCR).
To return from the sleep status, use one of the following methods:
•
Setting an interrupt request
•
Generate a reset source
In sleep status, operation of the peripheral clock resumes. This allows releasing an interrupt
caused by the built-in circuits for peripherals.
91
CHAPTER 3 MEMORY SPACE, CPU, AND CONTROL UNIT
■ Low-power Consumption Mode Operations
Table 3.13-1 lists the low-power consumption mode operations.
Table 3.13-1 Low-power Consumption Mode Operations
Oscillator
Operation
status
Run
Transition
condition
-
Internal clock
Peripheral
Pin
O
O
O
Standard
CPU and
internal
bus
Peripheral
O
O
Release method
Sleep
STCR
SLEP = 1
O
X
O
O
O
Reset
Interrupt
Stop
STCR
STOP = 1
X
X
X
X
*
External reset
External interrupt
O: Operation
X: Stop
* : STCR HIZX = 0: The previous status is retained.
STCR HIZX = 1: High impedance status is set.
92
CHAPTER 3 MEMORY SPACE, CPU, AND CONTROL UNIT
3.13.1 Stop Status
Stop status means the stoppage of all internal clocks and stoppage of the oscillation
circuit. This status allows the minimizing of power consumption.
■ Block Diagram of the Stop Control Block
Figure 3.13-1 shows a block diagram of the stop control block.
Figure 3.13-1 Block Diagram of the Stop Control Block
STOP status transition
request signal
Stop signal
Internal interrupt
Internal reset
CPU Hold Enable
CPU
clock
generation
Internal
bus clock
generation
Internal
DMA
clock
generation
Internal
peripheral
clock
generation
CPU Hold Request
STOP status
display signal
Clock stop
request signal
CPU clock
Internal clock generation circuit
clear
Status decoder
STOP
Status transition control circuit
STCR
Internal bus
Internal bus clock
Internal DMA clock
External bus clock
Internal peripheral clock
Clock release
request signal
■ Transition to Stop Status
❍ Method of setting the stop status by using an instruction
To enter stop status, set bit7 of STCR to 1.
After a stop request is issued, the CPU enters a status in which it is not using the internal bus.
The clocks then stop in the following order:
CPU clock --> internal bus clock --> internal DMA clock --> internal peripheral clock
The oscillation circuit stops simultaneously with the internal peripheral clock.
93
CHAPTER 3 MEMORY SPACE, CPU, AND CONTROL UNIT
Note:
To enter the stop status by using an instruction, be sure to use the following routines:
1. Before writing to STCR, set the [CCK1, CCK0] and [PCK1, PCK0] bits of GCR to the same value
and set the same gear ratios for the CPU system clock and peripheral system clock.
2. In this case, be sure to set the GCR CHC bit to 1 to select the divided-by-2 system clock. Never
enter the stop status with the GCR CHC bit set to 0.
3. At least six consecutive NOP instructions are required immediately after writing to STCR.
4. Set the clock doubler to OFF before entering the stop status.
[Setting method]
LDI:8
LDI:32
STB
LDI:8
LDI:32
STB
NOP
NOP
NOP
NOP
NOP
NOP
94
#00000001B,R1
#GCR,R2
R1,@R2
#10010000B,R1
#STCR,R2
R1,@R2
; CPU=Peripheral gear ratio,CHC=1
; STOP=1
;
;
;
;
;
;
CHAPTER 3 MEMORY SPACE, CPU, AND CONTROL UNIT
■ Return from the Stop Status
A return from the stop status can be achieved by an interrupt or by reset generation.
❍ Return with an interrupt
When the interrupt enable bit for the peripheral function is valid, a return from the stop status is
performed by generating a peripheral interrupt.
The status changes from stop status to ordinary operation status in the following order:
1. Interrupt generation
2. Restart of oscillation circuit operation
3. Wait for oscillation stabilization
4. Restart of supplying the internal peripheral clock signal after stabilization
5. Restart of supplying the internal bus clock signal
6. Restart of supplying the internal CPU clock signal
After the oscillation stabilization wait time elapses, the program is executed as follows:
•
When the ILM I flag of the CPU permits the level of the generated interrupt:
After register saving, the interrupt vector is fetched and then the program is executed from
the interrupt processing routine.
•
When the ILM I flag of the CPU does not allow the level of the generated interrupt:
The program is executed from the next instruction after the instruction at which the stop
status was entered.
❍ Return with the RST pin
The stop status is changed to the ordinary operation status in the following procedure:
1. Applying of the "L" level to the RST pin
2. Internal reset generation
3. Restart of the oscillation circuit operation
4. Wait for the oscillation stabilization
5. Restart of the internal peripheral clock supply after stabilization
6. Restart of the internal bus clock supply
7. Restart of the internal CPU clock supply
8. Fetching the reset vector
9. Restart of the instruction execution from the reset entry address
Notes:
• If an interrupt request was already generated from a peripheral, the stop status is not entered
and the writing operation is ignored.
• At a reset other than the power-on reset, no internal clock signal is supplied during the
oscillation stabilization wait time.
Because the power-on reset requires an initialization of all internal status, signals from all
internal clocks are supplied.
95
CHAPTER 3 MEMORY SPACE, CPU, AND CONTROL UNIT
3.13.2 Sleep Status
Sleep status means the stoppage of the CPU clock and internal bus clock.
This status can reduce power consumption to some extent when no CPU operation is
necessary.
■ Block Diagram of the Sleep Control Block
Figure 3.13-2 shows a block diagram of the sleep control block.
Figure 3.13-2 Block Diagram of the Sleep Control Block
clear
Internal interrupt
Internal reset
CPU
clock
generation
Internal
bus clock
generation
Internal
DMA
clock
generation
External
bus clock
generation
Internal
peripheral
clock
generation
Sleep status display signal
Clock stop
request signal
CPU clock
Internal clock generation circuit
STCR
SLEP
Status decoder
Internal bus
Status transition control circuit
Sleep status transition
request signal
Stop signal
Internal bus clock
Internal DMA clock
External bus clock
Internal peripheral clock
Clock release
request signal
■ Transition to the Sleep Status
To enter the sleep status, set bit7 of STCR to 0 and bit6 to 1.
After a sleep request is issued, the CPU enters a status in which it is not using the internal bus.
After this, the clocks stop in the following order:
CPU clock --> internal bus clock
Note:
To enter the sleep status, be sure to use the following routines:
1. Before writing to STCR, set the [CCK1, CCK0] and [PCK1, PCK0] bits of GCR to the same value
and then set the gear ratios of the CPU system clock and peripheral system clock to the same
value.
2. The value of the GCR CHC bit is arbitrary.
3. At least six consecutive NOP instructions are required immediately after writing to STCR.
96
CHAPTER 3 MEMORY SPACE, CPU, AND CONTROL UNIT
[Setting method]
LDI:8
LDI:32
STB
LDI:8
LDI:32
STB
NOP
NOP
NOP
NOP
NOP
NOP
#11001100B ,R1 ;
;
;
#GCR,R2
R1,@R2
#01010000B ,R1 ;
#STCR,R2
R1,@R2
;
;
;
;
;
;
CPU=Peripheral gear ratio(The following is
an example of oscillation x 1/8),
The value of CHC is arbitrary.
SLEP=1
■ Return from the Sleep Status
The return from the sleep status can be performed with an interrupt and by reset generation.
❍ Return with an Interrupt
When the interrupt enable bit for the peripheral function is valid, a return from sleep status is
performed by generating a peripheral interrupt.
The system changes from sleep status to ordinary operation status in the following order:
1. Interrupt generation
2. Restart of supplying the internal bus clock signal
3. Restart of supplying the internal CPU clock signal
After the required clock signals are supplied, the program is executed as follows:
•
When the ILM I flag of the CPU permits the level of the generated interrupt:
After register saving, the interrupt vector is fetched and then the program is executed from
the interrupt processing routine.
•
When the ILM I flag of the CPU does not allow the level of the generated interrupt:
The program is executed from the next instruction after the instruction at which the sleep
status was entered.
97
CHAPTER 3 MEMORY SPACE, CPU, AND CONTROL UNIT
❍ Return by a Reset Request
The system status changes from sleep status to ordinary operation status in the following order:
1. Internal reset generation
2. Restart of supplying the internal bus clock signal
3. Restart of supplying the internal CPU clock signal
4. Fetching the reset vector
5. Restart of instruction execution from the reset entry address
Notes:
• An instruction following the instruction for writing to STCR may be able to complete its operation.
So, if an interrupt request cancellation instruction or branch instruction is issued immediately
after that instruction, the operation results appear to be other than expected.
• If an interrupt request was already generated from a peripheral, sleep status is not entered.
• The DMA transfer operation in sleep status cannot use. Before entering to the sleep status, be
sure to disable the DMA transfer operation.
• Set the clock doubler to OFF before the sleep status is entered.
98
CHAPTER 3 MEMORY SPACE, CPU, AND CONTROL UNIT
3.13.3 Status Transition of the Low-power Consumption Mode
Figure 3.13-3 shows the status transition of the low-power consumption mode.
■ Status Transition of the Low-power Consumption Mode
Figure 3.13-3 Status Transition of the Low-power Consumption Mode
Power ON
Reset status
Oscillation stabilization wait
Start of main oscillation
(1)
CPU in stop status
Stop of main oscillation
(2)
Reset status
Main oscillation
(2)
(5)
(2)
(2)
CPU in stop status
Start of main oscillation
(1)
(3)
Sleep
Main oscillation
(9)
(6)
(4)
1/2 division clock operation
Main oscillation
(7)
(8)
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
PLL clock operation
Main oscillation
(2)
End of oscillation stabilization
Resetting
Cancel of resetting
Interrupt
External interrupt
Stop mode
PLL
1/2 frequency division
Sleep mode
99
CHAPTER 3 MEMORY SPACE, CPU, AND CONTROL UNIT
100
CHAPTER 4 BUS INTERFACE
CHAPTER 4
BUS INTERFACE
This chapter provides an outline of the bus interface and describes bus operation.
4.1 Outline of Bus Interface
4.2 Block Diagram of the Bus Interface
4.3 Registers of the Bus Interface
4.4 Bus Operation
4.5 Bus Timing
4.6 Internal Clock Multiply Operation (Clock Doubler)
4.7 Program Examples for the External Bus
101
CHAPTER 4 BUS INTERFACE
4.1
Outline of Bus Interface
The bus interface controls the interface with external memory and external I/O units.
■ Bus Interface Features
•
24-bit (16M bytes) address output
•
A bus width of 16 or 8-bit can be specified
•
Programmable automatic memory wait (up to seven cycles)
•
Support of little-endian mode
•
Unused addresses and data pins can be used as I/O ports
•
Use of an external bus exceeding 25 MHz is prohibited.
•
When a clock doubler is used, the bus speed is half the CPU speed.
■ Chip Select Area
Six types of chip select areas are provided in the bus interface.
Each area can be allocated as desired in minimum units of 64K bytes in a 4G bytes space by
using the area select registers (ASR1 to ASR5) and area mask registers (AMR1 to AMR5).
Note:
Area 0 is allocated in a space other than the areas specified by ASR1 to ASR5. When the system
is reset, area 0 is allocated in an external area other than 00010000H to 0005FFFFH.
(This model uses only four chip select output pins of chip select areas 0 to 3.)
Figure 4.1-1 (a) shows an example of allocating areas 1 to 5 in units of 64K bytes from
00100000H to 0014FFFFH. Figure 4.1-1 (b) shows an example of allocating area 1 of 512K bytes
from 00000000H to 0007FFFFH and areas 2 to 5 in units of 1M bytes from 00100000H to
004FFFFFH.
102
CHAPTER 4 BUS INTERFACE
Figure 4.1-1 Examples of Allocating Chip Select Areas
00000000 H
00000000
H
00080000
H
CS1 (512K)
CS0 (512K)
00080000 H
CS0 (1M byte)
000FFFFF H
CS2 (1M byte)
000FFFFFH
001FFFFF H
CS1 (64k byte)
0010FFFF H
CS3 (1M byte)
CS2 (64k byte)
0011FFFF H
002FFFFF H
CS3 (64k byte)
0012FFFF H
CS4 (1M byte)
CS4 (64k byte)
0013FFFF H
003FFFFF H
CS5 (64k byte)
0014FFFF H
CS5 (1M byte)
004FFFFF H
CS0
CS0
(a)
(b)
■ Bus Interface
The bus interface only operates in a predetermined area in normal bus interface mode.
Table 4.1-1 lists the correspondence between each chip select area and usable interface
functions. The area mode register (AMD) determines which interface mode is to be used.
Table 4.1-1 Chip Select Area and Usable Interface Mode
Selectable bus interface mode
Area
Remark
Normal bus
Time
sharing
DRAM
0
O
-
-
-
1 to 3
O
-
-
-
4 to 5
O
-
-
-
Note:
For the MB91151A, time sharing and DRAM mode cannot be used.
❍ Bus Size Specification
The required bus width for each area can be specified by a register.
103
CHAPTER 4 BUS INTERFACE
4.2
Block Diagram of the Bus Interface
Figure 4.2-1 shows a block diagram of the bus interface.
■ Bus Interface Block Diagram
Figure 4.2-1 Block Diagram of the Bus Interface
DATA BUS
ADDRESS BUS
A-Out
External
write
buffer
switch
read
buffer
switch
DATA Bus
DATA BLOCK
ADDRESS BLOCK
+1 or +2
address
buffer
External
Address Bus
shifter
inpage
4
compa-
ASR
AMR
CS0 to CS3
rator
External pin control block
3
RD
WR0, WR1
Control of all blocks
registers
&
Control
104
4
BRQ
BGRNT
RDY
CLK
CHAPTER 4 BUS INTERFACE
4.3
Registers of the Bus Interface
Figure 4.3-1 shows the registers of the bus interface.
■ Registers of the Bus Interface
Figure 4.3-1 Registers of the Bus Interface
Address 15
8 7
00060CH
ASR1
00060EH
AMR1
000610H
ASR2
000612H
AMR2
000614H
ASR3
000616H
AMR3
000618H
ASR4
00061AH
AMR4
00061CH
ASR5
00061EH
AMR5
000620H
AMD0
AMD1
000622H
AMD32
AMD4
000624H
AMD5
−
000626H
RFCR
00062CH
00062EH
DMCR4
DMCR5
0
Area Select Register 1
Area Mask Register 1
Area Select Register 2
Area Mask Register 2
Area Select Register 3
Area Mask Register 3
Area Select Register 4
Area Mask Register 4
Area Select Register 5
Area Mask Register 5
Area Mode Register 0 / Area Mode Register 1
Area Mode Register 32 / Area Mode Register 4
Area Mode Register 5
ReFresh Control Register
DRAM Control Register 4
DRAM Control Register 5
000628H
00062AH
−
EPCR1
External Pin Control Register 0
External Pin Control Register 1
0007FEH
LER
MODR
Little Endian Register / MODe Register
EPCR0
Note:
Since the MB91151A does not have function pins that would correspond to the shaded registers,
do not access these registers.
105
CHAPTER 4 BUS INTERFACE
4.3.1
Area Select Registers (ASR1 to ASR5) and Area Mask
Registers (AMR1 to AMR5)
The area select registers (ASR1 to ASR5) and area mask registers (AMR1 to AMR5)
specify the ranges at which chip select areas 1 to 5 are allocated in address space.
■ Area Select Registers (ASR) and Area Mask Registers (AMR)
The configurations of the ASRs and AMRs are as follows.
❍ Area Select Register (ASR1 to ASR5)
ASR1
ASR2
ASR3
ASR4
ASR5
15
A31
A31
A31
A31
A31
14
A30
A30
A30
A30
A30
13
A29
A29
A29
A29
A29
12
2
A18
A18
A18
A18
A18
1
A17
A17
A17
A17
A17
0
A16
A16
A16
A16
A16
Initial value
0001H
0002H
0003H
0004H
0005H
Access
W
W
W
W
W
2
A18
A18
A18
A18
A18
1
A17
A17
A17
A17
A17
0
A16
A16
A16
A16
A16
Initial value
Access
0000H
0000H
0000H
0000H
0000H
W
W
W
W
W
❍ Area Mask Register (AMR1 to AMR5)
AMR1
AMR2
AMR3
AMR4
AMR5
15
A31
A31
A31
A31
A31
14
A30
A30
A30
A30
A30
13
A29
A29
A29
A29
A29
12
ASR1 to ASR5 and AMR1 to AMR5 specify the ranges at which chip select areas 1 to 5 are
allocated in address space.
ASR1 to ASR5 specify the higher 16 bits (A31 to A16) of an address and AMR1 to AMR5 mask
the corresponding address bits. Each bit of AMR1 to AMR5 indicates "care" if it is set to 0. The
bit indicates "don’t care" if it is set to 1.
"care" indicates that a value of 0 or 1 in the corresponding ASR bit is treated as such in the
selection of the address space. On the other hand, "don’t care" indicates that the address
space for both 0 and 1 is selected regardless of the actual value of the corresponding ASR bit.
Some examples of chip select area specification with the ASR and AMR are shown below.
Example 1
ASR1 = 00000000 00000011B
AMR1 = 00000000 00000000B
In this example, a 64K bytes area in address space is allocated to area 1 as follows because
the ASR1 bits are set to 1 and the corresponding AMR1 bits are set to 0:
106
CHAPTER 4 BUS INTERFACE
00000000 00000011 00000000 00000000B (00030000H)
|
00000000 00000011 11111111 11111111B (0003FFFFH)
Example 2
ASR2 = 00001111 11111111B
AMR2 = 00000000 00000011B
In this example, "care" is set for the ASR2 bit when the corresponding AMR2 bit is 0, and a
value of "1" or "0" in the ASR2 bits is therefore used as such. When the corresponding AMR2
bit is 1, "don’t care" is set for the ASR2 bit and it does not matter whether the bit value is 0 or 1.
Consequently, a 256K bytes area is allocated in address space for area 2 as follows.
00001111 11111100 00000000 00000000B (0FFC0000H)
|
00001111 11111111 11111111 11111111B (0FFFFFFFH)
Areas 1 to 5 can be allocated in the 4G bytes address space in units of 64K bytes based on the
values of ASR1 to ASR5 and AMR1 to AMR5. If area 1 of the areas specified by these registers
is accessed through the bus, the output of the corresponding read/write pins (RD, WR0, WR1)
is set to the "L" level.
Area 0 is allocated at a location excluding the areas specified by ASR1 to ASR5 and AMR1 to
AMR5. To be more precise, area 0 is allocated at a location excluding the space from area 1
starting with address 0001000H to area 5 starting with 0005FFFFH according to the initial values
of ASR1 to ASR5 and AMR1 to AMR5 when the system is reset.
Note:
Be sure to ensure that chip select areas do not overlap with each other.
Figure 4.3-2 shows an example of mapping chip select areas.
Figure 4.3-2 Example of Chip Select Area Mapping
(Initial value)
(Examples 1 and 2)
00000000
00000000
Area 0
00010000
Area 0
Area 1
64K bytes
00030000
00020000
Area 2
Area 1
64K bytes
00040000
00030000
Area 3
Area 0
64K bytes
0FFC0000
00040000
Area 4
64K bytes
00050000
Area 2
Area 5
256 K bytes
64K bytes
10000000
00060000
Area 0
Area 0
FFFFFFFF
64K bytes
FFFFFFFF
107
CHAPTER 4 BUS INTERFACE
4.3.2
Area Mode Register (AMD0)
AMD0 specifies the operating mode of chip select area 0 (space excluding the areas
specified by ASR1 to ASR5 and AMR1 to AMR5). Area 0 is selected when the system
is reset.
■ AMD0
The configuration of AMD0 is as follows:
AMD0
bit
Address: 000620H
7
6
5
4
3
−
−
−
BW1
BW0
2
1
0
WTC2 WTC1 WTC0
Initial value
Access
---00111B
R/W
[bit4, bit3] Bus Width bits (BW1, BW0)
BW1 and BW0 specify the bus width of area 0.
BW1
BW0
Bus width
0
0
8 bits
0
1
16 bits
1
0
Reserved
1
1
Reserved
Note:
The initial values of BW1 and BW0 are 0, however, the levels of the MD1 and MD0 pins
are read until writing to the MODR during reading.
108
CHAPTER 4 BUS INTERFACE
[bit2 to bit0] Wait Cycle bits (WTC2 to WTC0)
WTC2 to WTC0 specify the number of wait cycles to be automatically inserted during normal
bus interfacing.
WTC2
WTC1
WTC0
Number of wait cycles to be inserted
0
0
0
0
0
0
1
1
0
1
0
2
0
1
1
3
1
0
0
4
1
0
1
5
1
1
0
6
1
1
1
7
Note:
WTC2 to WTC0 of AMD0 are set to 111B when the system is reset. Seven wait cycles
are automatically inserted when the bus is accessed immediately after the reset is
released.
Notes:
• Be sure to set BW1 and BW0 of the area mode register to be used (AMD0 to AMD5) before
writing to the MODR.
• After the mode register (MODR) is set, the bus width specified by AMD0 to AMD5 is valid for
external areas.
• Be sure not to change the settings of BW1 and BW0 after writing to the MODR. Otherwise,
operation errors may occur.
RST (reset)
MODR write
↓
The contents of the AMD0 to AMD5
registers are valid.
109
CHAPTER 4 BUS INTERFACE
4.3.3
Area Mode Register 1 (AMD1)
This register specifies the operating mode of the chip select area 1 (specified by ASR1
and AMR1).
■ AMD1
The configuration of this register is as follows:
AMD
bit
Address: 000620H
7
6
5
4
3
MPX
−
−
BW1
BW0
2
1
0
WTC2 WTC1 WTC0
Initial value Access
0--00000B
R/W
[bit7] MultiPleX bit (MPX)
The MPX controls the time-sharing I/O interface of address or data input and output.
0
Normal bus interface (Normal bus interface)
1
Setting is prohibited.
[bit4, bit3] Bus Width bits (BW1 and BW0)
The BW1 and BW0 specify the bus width of area 1.
BW1
BW0
Bus width
0
0
8 bits
0
1
16 bits
1
0
Reserved
1
1
Reserved
[bit2 to bit0] Wait Cycle bits (WTC2 to WTC0)
WTC2 to WTC0 specify the number of wait cycles to be automatically inserted during normal
bus interface operation. This operation is the same as that of WTC2 to WTC0 of AMD0
except that WTC2 to WTC0 are initialized to 000B and the number of wait cycles to be
inserted becomes 0 when the system is reset.
110
CHAPTER 4 BUS INTERFACE
4.3.4
Area Mode Register 32 (AMD32)
This register specifies the operating mode of chip select area 2 (specified by ASR2 and
AMR2) and chip select area 3 (specified by ASR3 and AMR3).
BW1 and BW0 control the common bus width for areas 2 and 3. The number of wait
cycles to be inserted can be set separately for areas 2 and 3.
■ AMD32
The configuration of this register is as follows:
AMD32
bit
Address: 000622H
7
6
BW1
BW0
5
4
3
2
1
0
WT32 WT31 WT30 WT22 WT21 WT20
Initial value Access
00000000B
R/W
[bit7, bit6] Bus Width bits (BW1 and BW0)
These bits specify the bus width of areas 2 and 3.
BW1
BW0
Bus width
0
0
8 bits
0
1
16 bits
1
0
Reserved
1
1
Reserved
[bit5 to bit3] Wait Cycle bits (WT32 to WT30)
These bits specify the number of wait cycles to be automatically inserted during memory
access of area 3.
The operation is the same as that of WTC2 to WTC0 of AMD0 except that these bits are
initialized to 000B and the number of wait cycles to be inserted becomes 0 when the system
is reset.
[bit2 to bit0] Wait Cycle bits (WT22 to WT20)
These bits specify the number of wait cycles to be automatically inserted during memory
access of area 2.
The operation is the same as that of WTC2 to WTC0 of AMD0 except these bits are
initialized to 000B and the number of wait cycles to be inserted becomes 0 when the system
is reset.
111
CHAPTER 4 BUS INTERFACE
4.3.5
Area Mode Register 4 (AMD4)
This register specifies the operating mode of chip select area 4 (specified by ASR4 and
AMR4).
■ AMD4
The configuration of this register is as follows:
AMD4
bit
Address: 000623H
7
6
5
4
3
DRME
−
−
BW1
BW0
2
1
0
WTC2 WTC1 WTC0
Initial value Access
0--00000B
R/W
[bit7] DRaM Enable bit (DRME)
This bit selects whether to use the normal bus interface or DRAM interface for area 4.
0
Normal bus interface (Normal bus interface)
1
Setting is prohibited.
[bit4, bit3] Bus Width bits (BW1, BW0)
These bits specify the bus width of area 4.
BW1
BW0
Bus width
0
0
8 bits
0
1
16 bits
1
0
Reserved
1
1
Reserved
[bit2 to bit0] Wait Cycle bits (WTC2 to WTC0)
These bits specify the number of wait cycles to be automatically inserted during normal bus
interface operation. The operation is the same as that of WTC2 to WTC0 of AMD0, except
that these bits are initialized to 000B and the number of wait cycles to be inserted becomes 0
when the system is reset.
112
CHAPTER 4 BUS INTERFACE
4.3.6
Area Mode Register 5 (AMD5)
This register specifies the operating mode of chip select area 5 (specified by ASR5 and
AMR5).
■ AMD5
The configuration of this register is as follows:
AMD5
bit
Address: 000624H
7
6
5
4
3
DRME
−
−
BW1
BW0
2
1
0
WTC2 WTC1 WTC0
Initial value Access
0--00000B
R/W
Each bit has the same meaning as the corresponding bit of AMD4.
See Section "4.3.5 Area Mode Register 4 (AMD4)".
113
CHAPTER 4 BUS INTERFACE
4.3.7
External Pin Control Register 0 (EPCR0)
This register controls output of each signal.
If output is allowed, a signal is outputted with the required timing in each bus mode. If
input is enabled, inputs signal from an external circuit are accepted.
If output is inhibited and input is disabled, the corresponding pin can be used as an
I/O port.
■ EPCR0
The configuration of this register is as follows:
EPCR0
bit
Address: 000628H
15
14
13
12
−
−
−
−
7
6
5
4
−
CKE
−
−
11
10
9
WRE RDXE RDYE
3
2
8
Initial value
Access
BRE
----1100B
W
0
Initial value
Access
-1111111B
W
1
COE3 COE2 COE1 COE0
[bit11] WRite pulse output Enable bit (WRE)
This bit specifies whether write pulses WR0 and WR1 is to be outputted.
The output becomes enabled when the system is reset.
•
0: Output prohibited
•
1: Output allowed (initial value)
Even if the WRE bit is set to 1, a write pulse pin can be used as an I/O port, depending on
the bus width set by the AMD. (For example, in the 8-bit mode, the WR1 is not outputted and
the corresponding pin can be used as an I/O port.)
[bit10] ReaDX pulse output Enable bit (RDXE)
This bit specifies whether read pulse RD is to be outputted.
The output becomes enabled when the system is reset.
•
0: Output inhibited (setting prohibited)
•
1: Output allowed (initial value)
[bit9] ReaDY input Enable bit (RDYE)
This bit controls RDY input as follows.
The input becomes disabled when the system is reset.
•
0: RDY input disabled (initial value)
•
1: RDY input enabled
[bit8] Bus Request Enable bit (BRE)
This bit controls BRQ and BGRNT as follows.
BRQ input is disabled and BGRNT output is inhibited when the system is reset.
•
114
0: BRQ input disabled, BGRNT output inhibited
CHAPTER 4 BUS INTERFACE
(The pins function as I/O ports.) (Initial value)
•
1: BRQ input enabled, BGRNT output allowed
[bit6] ClocK output Enable bit (CKE)
This bit enables output of the CLK (external bus operating clock waveform)
•
0: Output inhibited
•
1: Output allowed (initial value)
This bit is initialized to 1 when the system is reset and output of the CLK is allowed.
[bit5, bit4]
These bits are not used. Writing to these bits has no effect.
The default value is 1.
[bit3] Chip select Output Enable (COE3)
COE3 controls CS3 output.
Output is enabled after resetting.
•
0: Output prohibited
•
1: Output allowed (initial value)
[bit2] Chip select Output Enable (COE2)
COE2 controls CS2 output.
Output is enabled after resetting.
•
0: Output prohibited
•
1: Output allowed (initial value)
[bit1] Chip select Output Enable (COE1)
COE1 controls CS1 output.
Output is enabled after resetting.
•
0: Output prohibited
•
1: Output allowed (initial value)
[bit0] Chip select Output Enable (COE0)
COE0 controls CS0 output.
Output is enabled after resetting.
•
0: Output prohibited (setting inhibited)
•
1: Output allowed (initial value)
In this model, keep this bit set to 1.
115
CHAPTER 4 BUS INTERFACE
4.3.8
External Pin Control Register 1 (EPCR1)
This register controls output of address signals.
■ EPCR1
The configuration of this register is as follows:
EPCR1
bit
Address: 00062AH
15
14
13
12
11
10
9
8
−
−
−
−
−
−
−
−
7
6
5
4
3
2
1
0
AE23
AE22
AE21
AE20
AE19
AE18
AE17
AE16
Initial value Access
--------B
Initial value Access
11111111B
[bit7 to bit0] Address output Enable 23 to 16 (AE23 to AE16)
These bits specify whether the corresponding addresses are to be outputted.
If output is inhibited, the pins can be used as I/O ports.
•
0: Output inhibited
•
1: Output allowed (initial value)
AE23 to AE16 are initialized to FFH when the system is reset.
116
W
W
CHAPTER 4 BUS INTERFACE
4.3.9
Little-endian Register (LER)
The MB91151A ordinarily accesses the bus while treating all areas as big- endian
areas. However, making the required settings in this register enables one of the areas
1 to 5 to be treated as a little-endian area.
Note that area 0 cannot be treated as a little-endian area.
This register can be written only once after the system is reset.
■ LER
The configuration of this register is as follows:
LER
bit
Address: 0007FEH
7
6
5
4
3
2
1
0
−
−
−
−
−
LE2
LE1
LE0
Initial value Access
-----000B
W
[bit2 to bit0] LE2 to LE0
As listed in Table 4.3-1, a little-endian area is specified by the combination of the LE2, LE1,
and LE0 bits.
Table 4.3-1 Mode Setting by the Combination of the LE2, LE1, and LE0 Bits
LE2
LE1
LE0
Mode
0
0
0
Initial value after reset. No little-endian area is set.
0
0
1
Area 1 is set as a little-endian area and areas 0 and
2 to 5 are set as big-endian areas.
0
1
0
Area 2 is set as a little-endian area and areas 0, 1,
and 3 to 5 are set as big-endian areas.
0
1
1
Area 3 is set as a little-endian area and areas 0 to 2,
4, and 5 are set as big-endian areas.
1
0
0
Area 4 is set as a little-endian area and areas 0 to 3,
and 5 are set as big-endian areas.
1
0
1
Area 5 is set as a little-endian area and areas 0 to 4
are set as big-endian areas.
MODR (MODe Register)
For the mode register (MODR), see Section "3.11 Operation Mode".
117
CHAPTER 4 BUS INTERFACE
4.4
Bus Operation
This section describes the bus operation based on the following topics:
• Relationship between data bus width and control signals
• Big-endian bus access
• Little-endian bus access
• Comparison of external access
■ Relationship Between Data Bus Width and Control Signals
The relationship between the data bus width and control signals is described for the normal bus
interface:
■ Big-endian Bus Access
External access is described based on the following topics:
•
Data format
•
Data bus width
•
External bus access
•
Example of a connection with external devices
■ Little-endian Bus Access
External access is described based on the following topics:
•
Differences between little-endian and big-endian mode
•
Data format
•
Data bus width
•
Examples of connection with external devices
■ Comparison of External Access in Big-endian and Little-endian Mode
Word access, halfword access, and byte access are described for the various bus widths to
compare external access in big-endian and little-endian mode.
118
CHAPTER 4 BUS INTERFACE
4.4.1
Relationship Between Data Bus Width and Control
Signals
Control signals WR0 and WR1 always correspond to byte positions of the data bus in a
one to one relationship regardless of whether the mode is big-endian or little-endian,
and regardless of the data bus width.
■ Relationship Between Data Bus Width and Control Signals
The following figure shows the byte positions on the data bus of the MB91151A to be used with
the set data bus width for each bus mode and control signals.
Figure 4.4-1 Data Bus Width and Control Signals for a Normal Bus Interface
(a) 16-bit bus
data bus
D31
(b) 8-bit bus
Control signals
data bus
D31
WR0
Control signals
WR0
D24
WR1
D16
(D23 to D16 are not used.)
119
CHAPTER 4 BUS INTERFACE
4.4.2
Bus Access in Big-endian Mode
Areas not specified in the LER are accessed through an external bus as a big-endian
area.
The FR family ordinarily uses big-endian access.
■ Data Format
The following figures show the relationship between internal registers and the external data bus
for each data format.
❍ Word access (when an LD or ST instruction is executed)
Figure 4.4-2 Relationship Between Internal Register and External Data Bus for Word Access
Internal register External bus
D31
D31
AA
AA
CC
BB
BB
DD
D23
D23
D15
CC
D07
DD
❍ Half-word access (when an LDUH or STH instruction is executed)
Figure 4.4-3 Relationship Between Internal Register and External Data Bus for Half-Word Access
Internal register External bus
D31
D31
AA
D23
D23
BB
D15
AA
D07
BB
120
CHAPTER 4 BUS INTERFACE
❍ Byte access (when an LDUB or STB instruction is executed)
Figure 4.4-4 Relationship Between Internal Register and External Data Bus for Byte Access
(a) The lower byte of the
output address is 0.
(b) The lower byte of the output
address is 1.
Internal register External bus
D31
Internal register External bus
D31
D31
D23
D23
D31
AA
D23
D23
AA
D15
D15
D07
D07
AA
AA
■ Data Bus Width
The following figures show the relationship between internal registers and external data bus for
each data bus width.
❍ Relationship Between Internal Register and External Data Bus for 16-bit Bus
Figure 4.4-5 Relationship Between Internal Register and External Data Bus for 16-bit Bus
Internal register
External bus
The lower bytes of the output address
"00""10"
D31
D31
AA
Read/Write
AA CC
D23
D23
BB
BB DD
D15
CC
D07
DD
❍ Relationship Between Internal Register and External Data Bus for 8-bit Bus
Figure 4.4-6 Relationship Between Internal Register and External Data Bus for 8-bit Bus
Internal register
External bus
The lower bytes of the output address
"00" "01""10" "11"
D31
Read/Write
AA
D31
AA BB CC DD
D23
BB
D15
CC
D07
DD
121
CHAPTER 4 BUS INTERFACE
■ External Bus Access
Figure 4.4-7 and Figure 4.4-8 show external bus accesses under the following conditions:
•
Data bus width: 16 bits and 8 bits
•
Data format: Word, halfword, and byte
These figures also show the access byte location, program address and output address, and
bus access count under each condition.
The MB91151A cannot detect misalignment errors.
Therefore, for word access, even if the lower two bits of the address specified by a program are
"00", "01", "10", or "11", the lower two bits of the output address are always "00". For half-word
access, "00" is output if the two bits are "00" or "01", and "10" is output if the bits are "10" or
"11".
122
CHAPTER 4 BUS INTERFACE
❍ 16-bit bus
Figure 4.4-7 External Bus Access in Big-Endian Mode (16-bit Bus)
(A) Word access
(a) PA1/PA0="00"
(b) PA1/PA0="01"
(c) PA1/PA0="10"
(d) PA1/PA0="11"
(1) Output A1/A0 = "00"
(1) Output A1/A0 = "00"
(1) Output A1/A0 = "00"
(1) Output A1/A0 = "00"
(2) Output A1/A0 = "10"
(2) Output A1/A0 = "10"
(2) Output A1/A0 = "10"
(2) Output A1/A0 = "10"
MSB
LSB
(1)
00
01
(1)
00
01
(1)
00
01
(1)
00
01
(2)
10
11
(2)
10
11
(2)
10
11
(2)
10
11
16-bit
(B) Half-word access
(a) PA1/PA0="00"
(b) PA1/PA0="01"
(c) PA1/PA0="10"
(d) PA1/PA0="11"
(1) Output A1/A0 = "10"
(1) Output A1/A0 = "10"
(1) Output A1/A0 = "00"
(1) Output A1/A0 = "00"
(1)
00
01
10
11
(1)
00
01
10
11
(1)
00
01
10
11
(1)
00
01
10
11
(C) Byte access
(a) PA1/PA0="00"
(b) PA1/PA0="01"
(c) PA1/PA0="10"
(d) PA1/PA0="11"
(1) Output A1/A0 = "01"
(1) Output A1/A0 = "11"
(1) Output A1/A0 = "00"
(1) Output A1/A0 = "10"
(1)
00
01
10
11
(1)
00
01
10
11
(1)
00
01
10
11
(1)
00
01
10
11
PA1/PA0
: The lower two bits of the address specified by a program
Output A1/A0: The lower two bits of the address to be outputted
: Leading byte position of an address to be outputted
+
(1) to (4)
: Data byte position to be accessed
: Bus access count
123
CHAPTER 4 BUS INTERFACE
❍ 8-bit bus
Figure 4.4-8 External Bus Access in Big-Endian Mode (8-bit Bus)
(A) Word access
(a)PA1/PA0="00"
(b)PA1/PA0="01"
(c)PA1/PA0="10"
(d)PA1/PA0="11"
(1) Output A1/A0 = "00"
(1) Output A1/A0 = "00"
(1) Output A1/A0 = "00"
(1) Output A1/A0 = "00"
(2) Output A1/A0 = "01"
(2) Output A1/A0 = "01"
(2) Output A1/A0 = "01"
(2) Output A1/A0 = "01"
(3) Output A1/A0 = "10"
(3) Output A1/A0 = "10"
(3) Output A1/A0 = "10"
(3) Output A1/A0 = "10"
(4) Output A1/A0 = "11"
(4) Output A1/A0 = "11"
(4) Output A1/A0 = "11"
(4) Output A1/A0 = "11"
MSB LSB
(1)
00
(1)
00
(1)
00
(1)
00
(2)
01
(2)
01
(2)
01
(2)
01
(3)
10
(3)
10
(3)
10
(3)
10
(4)
11
(4)
11
(4)
11
(4)
11
8-bit
(B) Half-word access
(a)PA1/PA0="00"
(b)PA1/PA0="01"
(c)PA1/PA0="10"
(d)PA1/PA0="11"
(1) Output A1/A0 = "00"
(1) Output A1/A0 = "10"
(1) Output A1/A0 = "10"
(1) Output A1/A0 = "00"
(2) Output A1/A0 = "01"
(2) Output A1/A0 = "11"
(2) Output A1/A0 = "11"
(2) Output A1/A0 = "01"
(1)
00
(1)
00
00
00
(2)
01
(2)
01
01
01
10
10
(1)
10
(1)
10
11
11
(2)
11
(2)
11
(C) Byte access
(a)PA1/PA0="00"
(b)PA1/PA0="01"
(c)PA1/PA0="10"
(d)PA1/PA0="11"
(1) Output A1/A0 = "11"
(1) Output A1/A0 = "00"
(1) Output A1/A0 = "01"
(1) Output A1/A0 = "10"
(1)
00
01
(1)
00
00
00
01
01
01
10
10
10
10
11
11
(1)
PA1/PA0
: The lower two bits of the address specified by a program
Output A1/A0: The lower two bits of the address to be outputted
: Leading byte position of an address to be outputted
+
(1) to (4)
124
: Data byte position to be accessed
: Bus access count
11
(1)
11
CHAPTER 4 BUS INTERFACE
■ Example of Connection with External Devices
Figure 4.4-9 shows an example of connecting the MB91151A with external devices.
Figure 4.4-9 Example of a Connection Between the MB91151A and External Devices
MB91151A
D31
to
D24
D23
WR0
to
D16
0
D15
D08 D07
WR1
1
X
D00
* 16-bit device
D07
D00
* 8-bit device
(0/1 = the lowest bit of the address. X indicates that it does not matter
whether the lowest bit of the address is 0 or 1.)
* For 16- and 8-bit devices, the data bus on the side of the MSB is used.
125
CHAPTER 4 BUS INTERFACE
4.4.3
Bus Access in Little-endian Mode
An area specified in the LER is accessed as a little-endian area through the external
bus.
The MB91151A accesses a little-endian area in the same bus access operation as for a
big-endian area. The order of output addresses and control signals are the same as
those for a big-endian area, but the byte positions of the data bus are swapped in
accordance with the bus width.
Note that big-endian areas and little-endian areas should kept physically separated
during connection.
■ Differences and Similarities of Access in Little-endian and in Big-endian Mode
The order of output addresses are the same for access in big-endian and in little-endian mode.
The data bus control signals used for a bus width of 16 or 8 bits are also the same for access in
big-endian and in little-endian mode.
Differences between the data formats are shown below:
❍ Word access
Byte data on the side of the MSB, which corresponds to address 00B in big-endian mode, is
treated as byte data on the side of the LSB in little-endian mode.
In word access, all byte positions of the four bytes in a word are reversed as follows.
00 --> 11, 01 -- > 10, 10 --> 01, 11 --> 00
❍ Halfword access
Byte data on side of the MSB corresponding to address 0 in big-endian mode becomes byte
data on side of the LSB in little-endian mode.
For half-word access, the byte positions of the two bytes in a halfword are reversed.
0 -->1, 1 --> 0
❍ Byte access
There is no difference in byte access between big-endian and little-endian mode.
126
CHAPTER 4 BUS INTERFACE
■ Data Format
Figure 4.4-10 to Figure 4.4-12 show the relationship between the internal register and external
data bus for each data format.
❍ Word access (when an LD or ST instruction is executed)
Figure 4.4-10 Relationship Between Internal Register and External Data Bus (in Word Access)
Internal register
External bus
D31
D31
AA
DD BB
BB
CC AA
D23
D23
D15
CC
D07
DD
❍ Halfword access (when an LDUH or STH instruction is executed)
Figure 4.4-11 Relationship Between Internal Register and External Data Bus (in Halfword Access)
Internal register
External bus
D31
D31
BB
D23
D23
AA
D15
AA
D07
BB
❍ Byte access (when an LDUB or STB instruction is executed)
Figure 4.4-12 Relationship Between Internal Register and External Data Bus (in Byte Access)
(a) The lower byte of the
output address is 0.
Internal register
(b) The lower byte of the
output address is 1.
External bus
D31
Internal register
D31
D31
D23
D23
External bus
D31
AA
D23
D23
AA
D15
D15
D07
D07
AA
AA
127
CHAPTER 4 BUS INTERFACE
■ Data Bus Width
Figure 4.4-13 to Figure 4.4-14 show the relationships between the internal register and external
data bus for each data bus width.
❍ 16-bit bus width
Figure 4.4-13 Relationship Between Internal Register and External Data Bus (for 16-bit Bus)
Internal register
External bus
Lower bytes of an output address
"00" "10"
D31
AA
Read/Write
DD BB
D23
D31
D23
CC AA
BB
D15
CC
D07
DD
❍ 8-bit bus width
Figure 4.4-14 Relationship Between Internal Register and External Data Bus for a 8-bit Bus
Internal register
External bus
Lower bytes of an output address
"00" "01" "10" "11"
D31
D31
AA
D23
BB
D15
CC
D07
DD
128
Read/Write
DD CC BB
AA
CHAPTER 4 BUS INTERFACE
■ Examples of Connection with External Devices
Figure 4.4-15 and Figure 4.4-16 show examples of connecting the MB91151A with external
devices.
❍ 16-bit bus
Figure 4.4-15 Example of Connecting the MB91151A with External Devices (16-bit Bus)
MB91151A
D23
D31
to
D24
WR0
to
D16 WR1
Little-endian area
Bigendian
area
WR0
D31-24
MSB
D15
WR1
D23-16
LSB
D08 D07
D00
WR1
D23-16
MSB
D15
WR0
D31-24
LSB
D08 D07
D00
❍ 8-bit bus
Figure 4.4-16 Example of Connecting the MB91151A with External Devices (8-bit Bus)
MB91151A
D31
D23
to
to
D24 WR0 D16 WR1
Bigendian
area
D07 D00
Little-endian area
D07 D00
Note:
Because the MB91151A has no chip select output, addresses must be decoded externally.
129
CHAPTER 4 BUS INTERFACE
4.4.4
Comparison of External Access in Big-endian and Littleendian Mode
Table 4.4-1 to Table 4.4-3 compare external accesses between big-endian and littleendian modes in terms of each data bus width and data format.
■ Word Access
Table 4.4-1 Comparison of External Accesses Between Big-endian and Little-endian Modes (in Word
access)
Bus width
Big-endian mode
Little-endian mode
16-bit bus
Internal register
External pins
Control pins
Internal register
address: "0" "2"
D31
D31
BB
Control pins
address: "0" "2"
D31
AA
External pins
D31
AA CC
WR0
AA
BB DD
WR1
BB
D16
DD BB
WR0
CC AA
WR1
D16
CC
CC
DD
DD
D00
D00
(1) (2)
(1) (2)
8-bit bus
Internal register
D31
External pins
address: "0" "1" "2" "3"
D31
AA
AA BB CC DD
Control pins
Internal register
D31
WR0
D31
AA
DD CC BB AA
D24
BB
BB
CC
CC
DD
DD
D00
D00
(1) (2) (3) (4)
Control pins
address: "0" "1" "2" "3"
D24
130
External pins
(1) (2) (3) (4)
WR0
CHAPTER 4 BUS INTERFACE
■ Halfword Access
Table 4.4-2 Comparison of External Accesses Between Big-endian and Little-endian Modes (in Halfword
access) (1 / 2)
Bus width
Big-endian mode
Little-endian mode
16-bit bus
Internal register External pins Control pins
address: "0"
D31
D31
AA
WR0
BB
Internal register External pins
address: "0"
D31
D31
WR1
D16
BB
WR0
AA
WR1
D16
AA
AA
BB
BB
D00
D00
(1)
Internal register
D31
Control pins
(1)
External pins Control pins
address: "2"
D31
CC
WR0
DD
WR1
Internal register External pins Control pins
address: "2"
D31
D31
DD
WR0
CC
WR1
CC
−
−
DD
−
−
D16
D16
CC
DD
D00
D00
(1)
(1)
131
CHAPTER 4 BUS INTERFACE
Table 4.4-2 Comparison of External Accesses Between Big-endian and Little-endian Modes (in Halfword
access) (2 / 2)
Bus width
Big-endian mode
Little-endian mode
Internal register External pins Control pins
address: "0" "1"
D31
D31
AA BB
WR0
Internal register External pins Control pins
address: "0" "1"
D31
D31
BB AA
WR0
8-bit bus
D24
D24
AA
AA
BB
D00
BB
D00
D00
D00
(1) (2)
(1) (2)
Internal register
D31
External pins
address: "2" "3"
D31
CC DD
Control pins
WR0
Internal register
D31
External pins Control pins
address: "2" "3"
D31
DD CC
D24
WR0
D24
−
CC
DD
D00
D00
(1) (2)
132
D00
CC
−
DD
−
D00
(1) (2)
CHAPTER 4 BUS INTERFACE
■ Byte Access
Table 4.4-3 Comparison of External Accesses Between Big-endian and Little-endian Modes (in Byte
access) (1 / 2)
Bus width
Big-endian mode
Little-endian mode
16-bit bus
Internal register
External pins
Control pins
Internal register
D31
External pins
D31
D31
D31
WR0
AA
WR0
AA
D16
D16
AA
AA
D00
D00
(1)
(1)
Internal register
External pins Control pins
Internal register
address: "1"
D31
D31
D31
BB
External pins Control pins
address: "1"
D31
WR1
BB
D16
BB
BB
D00
(1)
Internal register
(1)
External pins Control pins
address: "2"
D31
CC
Internal register
D31
WR0
External pins Control pins
address: "2"
D31
CC
D16
WR0
D16
CC
CC
D00
D00
(1)
Internal register
D31
WR1
D16
D00
D31
Control pins
address: "0"
address: "0"
External pins
(1)
Control pins
address: "3"
D31
DD
Internal register
D31
External pins
Control pins
address: "3"
D31
DD
WR1
WR1
D16
D16
DD
DD
D00
D00
(1)
(1)
133
CHAPTER 4 BUS INTERFACE
Table 4.4-3 Comparison of External Accesses Between Big-endian and Little-endian Modes (in Byte
access) (2 / 2)
Bus width
Big-endian mode
Little-endian mode
8-bit bus
Internal register
External pins Control pins
Internal register
address: "0"
D31
D31
D31
AA
External pins Control pins
address: "0"
D31
WR0
AA
D24
AA
AA
D00
D00
(1)
Internal register
(1)
External pins Control pins
address: "1"
D31
D31
BB
WR0
Internal register
External pins Control pins
address: "1"
D31
D31
BB
D24
WR0
D24
BB
BB
D00
D00
(1)
(1)
Internal register External pins Control pins
address: "2"
D31
D31
CC
WR0
Internal register External pins Control pins
address: "2"
D31
D31
CC
WR0
D24
D24
CC
CC
D00
D00
(1)
Internal register External pins
address: "3"
D31
D31
DD
D24
(1)
Control pins
WR0
Internal register External pins
address: "3"
D31
D31
DD
D24
DD
DD
D00
D00
(1)
134
WR0
D24
(1)
Control pins
WR0
CHAPTER 4 BUS INTERFACE
4.5
Bus Timing
This section provides detailed information on bus access operations in each of the
following modes:
• Normal bus access
• Wait cycle
• External bus request
■ Normal Bus Access
With a normal bus interface, a basic bus cycle contains two clock cycles for both the read and
write cycles. This manual refers to the two cycles as BA1 and BA2.
Normal bus access includes the following cycles:
•
Basic read cycle
•
Basic write cycle
•
Read cycle in each mode
•
Write cycle in each mode
•
Mixed read/write cycles
■ Wait Cycle
In the wait cycle mode, the preceding cycle is continued. The BA1 cycle is repeated until wait is
canceled.
This device has two types of wait cycles:
•
An automatic wait cycle that is set by the WTC2 to WTC0 bits in the AMD register
•
An external wait cycle that is set by the RDY pin
■ External Bus Request
The following two types of external bus requests are used:
•
Release of bus right
•
Acquisition of bus right
135
CHAPTER 4 BUS INTERFACE
4.5.1
Basic Read Cycle
This section describes the operations of the basic read cycle.
■ Basic Read Cycle Timing Chart
Figure 4.5-1 shows an example of basic read cycle timing under the following conditions:
•
Bus width: 16 bits
•
Access type: in words
•
Access to CS0 area
Note:
This model does not use CS4 and CS5 outputs.
Figure 4.5-1 Timing Chart of the Basic Read Cycle
BA1
BA2
BA1
BA2
CLK
A23-00
D31-24
D23-16
#0
#2
#0
#1
#2
#3
RD
WR0
WR1
(CS0)
(CS1)
(CS2)
(CS3)
(DACK0)
(DEOP0)
Access to the
Access to the
higher halfword lower halfword
of an address
of an address
Notes:
The sharp-symbol (#) of A23 to A00 indicates the lower two bits
of an address.
The sharp-symbol (#) of D31 to D16 indicates the byte address
for read data.
(DACK0) and (DEOP0) indicate DMAC bus cycles.
The arrow-symbol ( ) indicates the timing of fetching read data.
136
CHAPTER 4 BUS INTERFACE
[Operation]
•
The CLK outputs the pulses for the operating clock of the external bus. If the clock doubler
is off, the operating clocks of the CPU and that of the external bus are in 1:1 relationship and
the clock pulses output from the CLK have the same frequency as the clock pulses of the
CPU. If the clock doubler is on, the operating clocks of the CPU and that of the external bus
are in 1:1/2 relationship and the clock pulses output from the CLK have a frequency that is
half that of the CPU clock pulses. If the gear is set, the CLK frequency is decreased
according to the gear ratio.
•
A23 to A00 (address 23 to address 00) output the address of a leading byte location during
word, halfword or byte access in a read cycle starting with the start of a bus cycle (BA1). In
the above example, a word is accessed in 16-bit bus access, and the address of the higher
16 bits of the word to be accessed (the lower two bits, indicating 0) is therefore outputted in
the first bus cycle, while the address of the lower 16 bits is outputted in the second bus cycle
(the lower two bits, indicating 2).
•
D31 to D16 (data 31 to data 16) indicate read data from external memory and I/O. In a read
cycle, D31 to D16 are read when the RD rises. Moreover, in a read cycle, all of D31 to D16
are read when the RD rises regardless of bus width and whether the access in units of
words, halfwords, or bytes. Whether the read data is valid is checked in the chip.
•
The RD is the read strobe signal of the external data bus. This signal is asserted when the
BA1 falls and negated when the BA2 falls.
•
In a read cycle, WR0 and WR1 are negated.
•
The CS0 to CS3 (area chip select) signals are asserted from the beginning of the bus cycle
(BA1) with the same timing as for A23 to A00. CS0 to CS3 are generated by decoding
address output. These signals are changed only if the address output changes and the chip
select area set by the ASR register and AMR register is changed.
•
The DACK0 to DACK2 and DEOP0 to DEOP2 are outputted during external bus cycles of
the DMA. Whether they are outputted is determined by DMA controller register settings.
Their output timing is the same as that of the RD.
137
CHAPTER 4 BUS INTERFACE
4.5.2
Basic Write Cycle
This section describes the operations of the basic write cycle.
■ Basic Write Cycle Timing Chart
Figure 4.5-2 shows an example of basic write cycle timing under the following conditions:
•
Bus width: 8 bits
•
Access type: in words
•
Access to CS0 area
Note:
This model does not use CS4 and CS5 outputs.
Figure 4.5-2 Example of a Timing Chart for Basic Write Cycle
BA1
BA2
BA1
BA2
BA1
BA2
BA1
BA2
CLK
A23-A00
D31-D24
D23-D16
RD
WR0
WR1
(CS0)
(CS1)
(CS2)
(CS3)
(DACK0)
(DEOP0)
#0
#0
Byte access when
the lower two bits
of the address
indicate 0
138
#1
#1
Byte access when
the lower two bits
of the address
indicate 1
#2
#2
Byte access when
the lower two bits
of the address
indicate 2
#3
#3
Byte access when
the lower two bits
of the address
indicate 3
CHAPTER 4 BUS INTERFACE
[Operation]
•
A23 to A00 (address 23 to address 00) output the address of the leading byte location for
word, halfword, or byte access during a write cycle starting from the beginning of a bus cycle
(BA1). In the above example, because a word is accessed in a width of eight bits, the
address of the leading byte of the word (the lower bits of the address indicate 0) is outputted.
Then, the address for the leading byte address plus 1 (1), the address of the leading byte
address plus 2 (2), and the address for the leading byte address plus 3 (3) are outputted in
sequence.
•
D31 to D16 (data 31 to data 16) indicate write data for the external memory and I/O. In a
write cycle, write data is outputted starting from the beginning of a bus cycle (BA1) and set to
High-Z at the end of the bus cycle (end of the BA2). In the above example, write data is
outputted to D31 to D24 because the data bus has a width of 8 bits.
•
The RD is negated during a write cycle.
•
WR0 and WR1 are write strobe signals for the external data bus. They are asserted when
BA1 falls and negated when BA2 falls. D31 to D24 and D23 to D16 are asserted in
accordance with WR0 and WR1 and the width of their data buses. In the above example,
only WR0 is asserted because the data bus has a width of eight bits.
•
If the maximum bus width of chip select areas 0 to 5 is eight bits, that is, all of the set areas
are set to 8-bit mode, D23 to D16 and WR1 automatically become I/O ports and turn to high
impedance (Hi-Z).
In the above example, D23 to D16 and WR1 are used as I/O ports.
Note that D23 to D16 and WR1 cannot be used as I/O ports if the bus width for even one of
chip select areas 0 to 5 is 16 bits.
Pin
•
Maximum bus width
D31 to D24
WR0
D23 to D16
WR1
16 bits
D31 to D24
WR0
D23 to D16
WR1
8 bits
D31 to D24
WR0
I/O port
DACK0 to DACK2 and DEOP0 to DEOP2 are outputted during an external bus cycle of the
DMA. Whether they are outputted is determined by DMA controller register settings. The
output timing is the same as that of WR0 and WR1.
139
CHAPTER 4 BUS INTERFACE
4.5.3
Read Cycle in Each Mode
Figure 4.5-3 to Figure 4.5-7 show examples of the read cycle timing in each mode.
■ Timing Chart of Read Cycles in Each Mode
❍ Bus width: 16 bits Access: In units of halfwords
Figure 4.5-3 Sample Read Cycle Timing Chart 1
BA1
BA2
BA1
BA2
CLK
#0
A23 to A00
D31 to D24
D23 to D16
RD
#2
#0
#1
#2
#3
❍ Bus width: 16 bits Access: In units of bytes
Figure 4.5-4 Sample Read Cycle Timing Chart 2
BA1
BA2
BA1
BA2
BA1
BA2
BA1
BA2
CLK
A23 to A00
D31 to D24
D23 to D16
RD
#0
#1
#0
X
#2
X
#1
#3
#2
X
X
#3
X: Input of invalid data
❍ Bus width: 8 bits Access: In units of words
Figure 4.5-5 Sample Read Cycle Timing Chart 3
BA1
BA2
BA1
BA2
BA1
BA2
BA1
BA2
CLK
A23 to A00
D31 to D24
D23 to D16
RD
140
#0
#1
#0
#2
#1
#3
#2
#3
CHAPTER 4 BUS INTERFACE
❍ Bus width: 8 bits Access: In units of halfwords
Figure 4.5-6 Sample Read Cycle Timing Chart 4
BA1
BA2
BA1
BA2
BA1
BA2
BA1
BA2
CLK
A23 to A00
D31 to D24
D23 to D16
RD
#0
#1
#0
#2
#1
#3
#2
#3
❍ Bus width: 8 bits Access: In units of bytes
Figure 4.5-7 Sample Read Cycle Timing Chart 5
BA1
BA2
BA1
BA2
BA1
BA2
BA1
BA2
CLK
A23 to A00
D31 to D24
D23 to D16
RD
#0
#1
#0
#2
#1
#3
#2
#3
141
CHAPTER 4 BUS INTERFACE
4.5.4
Write Cycle in Each Mode
Figure 4.5-8 to Figure 4.5-12 show examples of the write cycle timing in each mode.
■ Write Cycle Timing in Each Mode
❍ Bus width: 16 bits Access: In units of words
Figure 4.5-8 Sample Write Cycle Timing Chart 1
BA1
BA2
BA1
BA2
CLK
#0
#0
#1
A23 to A00
D31 to D24
D23 to D16
WR0
WR1
#2
#2
#3
❍ Bus width: 16 bits Access: In units of halfwords
Figure 4.5-9 Sample Write Cycle Timing Chart 2
BA1
BA2
BA1
BA2
CLK
A23 to A00
D31 to D24
D23 to D16
WR0
WR1
#0
#0
#1
#2
#2
#3
❍ Bus width: 16 bits Access: In units of bytes
Figure 4.5-10 Sample Write Cycle Timing Chart 3
BA1
BA2
BA1
BA2
BA1
BA2
BA1
CLK
A23 to A00
D31 to D24
D23 to D16
WR0
WR1
#0
#0
X
#1
X
#1
#2
#2
X
X: Output of invalid data
142
#3
X
#3
BA2
CHAPTER 4 BUS INTERFACE
❍ Bus width: 8 bits Access: In units of halfwords
Figure 4.5-11 Sample Write Cycle Timing Chart 4
BA1
BA2
BA1
BA2
BA1
BA2
BA1
BA2
CLK
A23 to A00
D31 to D24
D23 to D16
WR0
WR1
#0
#0
#1
#1
#2
#2
#3
#3
❍ Bus width: 8 bits Access: In units of bytes
Figure 4.5-12 Sample Write Cycle Timing Chart 5
BA1
BA2
BA1
BA2
BA1
BA2
BA1
BA
CLK
A23 to A00
D31 to D24
D23 to D16
WR0
WR1
#0
#0
#1
#1
#2
#2
#3
#3
143
CHAPTER 4 BUS INTERFACE
4.5.5
Mixed Read/Write Cycles
This section describes the operations of the mixed read/write cycles.
■ Timing Chart for Mixed Read/Write Cycles
Figure 4.5-13 shows examples of mixed read/write cycles timing under the following conditions:
•
•
CS0 area
•
Bus width: 16 bits
•
Access type: reading in units of words
CS1 area
•
Bus width: 8 bits
•
Access type: Writing in units of halfwords
Note:
This model does not use CS4 and CS5 outputs.
Figure 4.5-13 Sample Timing Chart for Mixed Read/Write Cycles
BA1
BA2
BA1
BA2
Idle
BA2
BA1
BA1
BA
Idle
CLK
A23 to A00
D31 to D24
D23 to D16
#0
#2
#0
#1
#0
#0
X
#2
#3
#1
#1
X
RD
WR0
WR1
(CS0)
(CS1)
Halfword write cycle
Word read cycle
CS0 area
CS1 area
[Operation]
144
•
In the above example, an idle cycle (in which no bus cycle is provided) is inserted when a
chip select area is switched. If an idle cycle is inserted between bus cycles, the address of
the preceding bus cycle is kept as output until the next bus cycle starts. Accordingly, the
CS0 to CS3 corresponding to the output address are kept asserted.
•
In the above example, the 16-bit bus and 8-bit bus are mixed. Because the maximum bus
width is 16 bits, D23 to D16 and WR1 cannot be used as I/O ports even for an 8-bit access
area (CS1 area). The output of D23 to D16 is undefined and WR1 is negated.
CHAPTER 4 BUS INTERFACE
4.5.6
Automatic Wait Cycle
This section describes the operations of the automatic wait cycle.
■ Automatic Wait Cycle Timing Chart
Figure 4.5-14 shows an example of automatic wait cycle timing under the following conditions:
•
Bus width: 16 bits
•
Access type: Reading/writing in halfwords
Figure 4.5-14 Sample Timing Chart for an Automatic Wait Cycle
BA1
BA1
BA2
BA1
BA1
BA2
CLK
A23 to A00
D31 to D16
RD
WR0,WR1
(DACK0)
(DEOP0)
#0
#0:1
wait
Read
#2
#2,3
wait
Write
[Operation]
•
Automatic wait cycles can be implemented by setting the WTC2 to WTC0 bits of the AMD
register in each chip select area.
•
In the above example, the WTC bits are set to 001B to insert one wait bus cycle between
normal bus cycles. The bus cycle includes three clock cycles (two clock cycles for normal
bus cycle plus one clock cycle for wait cycle).
Up to seven clock cycles can be set for one automatic wait cycle (accordingly, one normal
bus cycle contains nine clock cycles).
145
CHAPTER 4 BUS INTERFACE
4.5.7
External Wait Cycle
This section describes the operation of the external wait cycle.
■ Timing Chart of External Wait Cycle
Figure 4.5-15 shows an example of external wait cycle timing under the following conditions:
•
Bus width: 16 bits
•
Access type: In halfwords
Figure 4.5-15 Sample Timing Chart for an External Wait Cycle
BA1
BA1
BA1
BA1
BA1
BA2
CLK
A23 to A00
Read
D31 to D16
RD
Write
D31 to D16
WR0,WR1
#0
#0:1
#0,1
wait
wait
wait
RDY
RDY
Automatic
wait
Wait set by the RDY
Bus cycle
[Operation]
146
•
An external wait cycle can be implemented by setting the RDYE bit of the EPCR0 to 1 and
enabling input of the external RDY pin.
•
To use the external RDY, set an automatic wait cycle containing one clock cycle or more (set
001B or a larger value via the WTC2 to WTC0 bits of the AMD). The RDY is detected in the
last cycle of an automatic wait.
•
Input the external RDY, synchronizing it with a falling edge of the CLK pin output. A wait
cycle follows if the external RDY is of low level when the CLK goes low and the same BA1
cycle is repeated. If the external RDY is of high level, the wait cycle is assumed to have
ended and a BA2 cycle follows.
CHAPTER 4 BUS INTERFACE
4.5.8
External Bus Request
This section describes the operations of external bus requests.
■ Releasing Bus Right
Figure 4.5-16 shows an example of releasing bus right timing.
Figure 4.5-16 Sample Timing Chart for Releasing Bus Right
CLK
A23 to A00
D31 to D16
RD
#0:1
#0:1
Hi-Z
Hi-Z
Hi-Z
BRQ
BGRNT
One cycle
[Operation]
•
Bus arbitration by the BRQ and BGRNT can be implemented by setting the BRE bit of the
EPCR0 to 1.
•
Assert the BGRNT one cycle after the pin is set to high impedance (Hi-Z).
■ Bus Right Acquisition
Figure 4.5-17 shows an example of bus right acquisition timing.
Figure 4.5-17 Sample Timing Chart for Bus Right Acquisition
CLK
A23 to A00
D31 to D16
RD
Hi-Z
Hi-Z
Hi-Z
BRQ
BGRNT
One cycle
[Operation]
•
Bus arbitration by the BRQ and BGRNT can be implemented by setting the BRE bit of the
EPCR0 to 1.
•
Activate each pin one clock after negating the BGRNT.
147
CHAPTER 4 BUS INTERFACE
4.6
Internal Clock Multiply Operation (Clock Doubler)
The MB91151A has a clock multiply circuit. The CPU internally operates at a frequency
obtained by multiplying the bus interface frequency by one or two. The bus interface
operates in synch with the CLK output pin regardless of the selected frequency.
If an external access request is made from the CPU, external access starts after the
CLK output goes high.
■ Clock Selection Method
For the method of selecting multiply-by-one or multiply-by-two clock frequencies, see Section
"3.12.4 Gear Control Register (GCR)".
A selected clock can be changed even during chip operation. Bus operation is suspended while
clock selection is changed. When the system is reset, the clock obtained by multiplying the bus
interface frequency by 1 is assumed.
❍ Multiply-by-two clock
Figure 4.6-1 shows an example of multiply-by-two clock timing under the following conditions:
•
Bus width: 16 bits
•
Access type: In words
Figure 4.6-1 Example of Multiply-by-two Clock Timing
Internal clock
Internal instruction address
N+2
N
Internal instruction data
D
D+2
CLK output
External address bus
N+2
N
External data bus
D
N+4
D+2
External RD
External access (instruction fetch)
Prefetch
❍ Multiply-by-one clock
Figure 4.6-2 shows an example of multiply-by-one clock timing under the following conditions:
148
•
Bus width: 16 bits
•
Access type: In words
CHAPTER 4 BUS INTERFACE
Figure 4.6-2 Example of Multiply-by-one Clock Timing
Internal clock
Internal instruction address
N
N+2
Internal instruction data
D
D+2
CLK output
External address bus
External data bus
N+2
N
D
N+4
D+2
External RD
External access (instruction fetch)
Prefetch
149
CHAPTER 4 BUS INTERFACE
4.7
Program Examples for the External Bus
This section shows simple sample programs for operating the external bus.
■ Specification Example of a Program for External Bus Operation
❍ Registers are set as follows:
•
•
Areas
•
Area 0 (AMD0):
16 bits, normal bus, automatic wait - 0
•
Area 1 (AMD1):
16 bits, normal bus, automatic wait - 2
•
Area 2 (AMD32): 16 bits, normal bus, automatic wait - 1
•
Area 3 (AMD32): 16 bits, normal bus, automatic wait - 1
•
Area 4 (AMD4):
16 bits, DRAM, page size 256, 1CAS/2WE, with wait, CBR refresh
•
Area 5 (AMD5):
16 bits, DRAM, page size 512, 2CAS/1WE, without wait, CBR refresh
Other buses
•
Refresh (RFCR):
Without wait, 1/8 setting
•
External pin (EPCR0):
External RDY acceptance, BRQ, BGRNT arbitration
•
External pin (DSCR):
DRAM pin setting
•
Little-endian (LER):
Area 2
❍ Note the following points:
•
MD2 to MD0: 001. External vector: 16-bit mode
•
Set the same bus width for area 0, then set the mode register (MODR).
•
Set areas 1 to 5 so that they do not overlap each other.
Note:
This model does not support the DRAM control function and chip select output.
150
CHAPTER 4 BUS INTERFACE
■ Program Example for External Bus Operation
The explanation of this example assumes that writing to a byte register is performed in units of
bytes while writing to halfword registers is performed in units of halfwords.
*****
Program example
*****
//Setting of each register
init_epcr ldi:20 #0xffff,r0
ldi:20
sth
ldi:8
#0x628,r1
r0,@r1
#0xff,r0
ldi:20
stb
init_amd0 ldi:8
ldi:20
stb
init_amd1 ldi:8
ldi:20
stb
init_amd32 ldi:8
#0x625,r1
r0,@r1
#0x08,r0
#0x620,r1
r0,@r1
#0x0a,r0
#0x621,r1
r0,@r1
#0x49,r0
ldi:20
stb
init_amd4 ldi:8
ldi:20
stb
init_amd5 ldi:8
ldi:20
stb
init_dmcr4 ldi:20
#0x622,r1
r0,@r1
#0x88,r0
#0x623,r1
r0,@r1
#0x88,r0
#0x624,r1
r0,@r1
#0x0c90,r0
ldi:20
sth
init_dmcr5 ldi:20
#0x62c,r1
r0,@r1
#0x10c0,r0
init_dscr
ldi:20
sth
init_rfcr ldi:20
ldi:20
sth
init_asr ldi:32
ldi:32
ldi:32
ldi:32
ldi:32
ldi:20
ldi:20
ldi:20
ldi:20
ldi:20
st
st
st
st
st
#0x62e,r1
r0,@r1
#0x0205,r0
#0x626,r1
r0,@r1
#0x0013001,r0
#0x0015001,r1
#0x0017001,r2
#0x0019001,r3
#0x001b001,r4
#0x60c,r5
#0x610,r6
#0x614,r7
#0x618,r8
#0x61C,r9
r0,@r5
r1,@r6
r2,@r7
r3,@r8
r4,@r9
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
External pin setting
External RDY wait, BRQ, BGRNT bus arbitration
epcr0 register address setting
epcr0 register write
DRAM pin setting
RAS,CAS,WE
dscr register address setting
dscr register write
16-bit bus, 0 wait cycle
amd0 register address setting
amd0 register write
16-bit bus, two wait cycles
amd1 register address setting
amd1 register write
Normal, 16-bit bus, one wait
cycle
amd32 register address setting
amd32 register write
DRAM, 16-bit bus
amd4 register address setting
amd4 register write
DRAM, 16-bit bus
amd5 register address setting
amd5 register write
page size=256,Q1/Q4-wait,Page
1CAS-2WE,CBR,without parity
dmcr4 register address setting
dmcr4 register write
page size=512,Q1/Q4 - without wait, Page
2CAS-1WE,CBR, without parity
dmcr5 register address setting
dmcr5 register write
REL=2,R1W/R3W - without wait,refresh, 1/8
rfcr register address setting
rfcr register write
asr1, amr1 register set value
asr2, amr2 register set value
asr3, amr3 register set value
asr4, amr4 register set value
asr5, amr5 register set value
asr1, amr1 register address setting
asr2, amr2 register address setting
asr3, amr3 register address setting
asr4, amr4 register address setting
asr5, amr5 register address setting
asr1, amr1 register write
asr2, amr2 register write
asr3, amr3 register write
asr4, amr4 register write
asr5, amr5 register write
151
CHAPTER 4 BUS INTERFACE
init_ler
ldi:8
ldi:20
stb
init_modr ldi:8
ldi:20
stb
//External bus access
adr_set
ldi:32
ldi:32
ldi:32
ldi:32
ldi:32
ldi:32
ldi:32
ldi:32
bus_acc
ld
lduh
ld
ldub
st
sth
st
stb
152
#0x02,r0
#0x7fe,r1
r0,@r1
#0x80,r0
#0x7ff,r1
r0,@r1
#0x00136da0,
#0x00151300,
#0x00196434,
#0x0019657c,
#0x00196600,
#0x001a6818,
#0x001a6b8c,
#0x001a6c00,
@r0,r8
@r1,r9
@r2,r10
@r3,r11
r8,@r4
r9,@r5
r10,@r6
r11,@r7
//
//
//
//
//
//
r0
r1
r2
r3
r4
r5
r6
r7
CS2 little-endian
ler register address setting
ler register write
External ROM external bus
modr register address setting
modr register write
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
CS1
CS2
CS4
CS4
CS4
CS5
CS5
CS5
CS1
CS2
CS4
CS4
CS4
CS5
CS5
CS5
address
address
address (in page)
address (in page)
address (not in page)
address (in page)
address (in page)
address (not in page)
data word load
data half word load
data word load
data byte load
data word store
data half word store
data word store
data byte store
CHAPTER 5 I/O PORTS
CHAPTER 5
I/O PORTS
This chapter describes the overview of the I/O ports and provides the block diagrams
of individual ports. It also describes the register configurations.
5.1 Overview of I/O Ports
5.2 Block Diagram of Basic I/O Port
5.3 Block Diagram of I/O Ports (Including the Pull-up Resistor)
5.4 Block Diagram of I/O Ports (Including the Open-Drain Output Function and
the Pull-up Resistor)
5.5 Block Diagram of I/O Port (With Open-Drain Output Function)
5.6 Port Data Register (PDR2 to PDRL)
5.7 Data Direction Register (DDR2 to DDRL)
5.8 Pull-up Resistor Control Register (PCR6 to PCRI)
5.9 Open-Drain Control Register (OCRH and OCRI)
5.10 Analog Input Control Register (AICR)
153
CHAPTER 5 I/O PORTS
5.1
Overview of I/O Ports
This section provides I/O port block diagrams for the device and an outline of
registers.
■ I/O Port Block Diagrams
The MB91151A supports using a pin as an I/O port when the pin is not set to be used for input
or output of the resource corresponding to the pin.
When a pin is set to be used as input port, the level of the pin is read as the read value of the
port data register (PDR). When a pin is set to be used as output port, the value of a data
register is used as read value. This applies also to the read value for read modify write
operations.
Before the pin setting is changed from input to output, the output data must be specified in
advance in the respective data register. Note that if an instruction of the read modify write
system (such as a bit set) is used in this situation, the data to be read is input data from a pin
instead of the latch value in the data register.
The MB91151A has the following types of I/O ports:
•
Basic I/O port
•
I/O port with pull-up resistor
•
I/O port with open-drain output function and pull-up resistor
•
I/O port with open-drain output function
■ I/O Port Registers
The I/O ports are configured with the following registers:
154
•
Port data register (PDR)
•
Data direction register (DDR)
•
Pull-up resistor control register (PCR)
•
Open-Drain control register (OCR)
•
Analog input control register (AICR)
CHAPTER 5 I/O PORTS
5.2
Block Diagram of Basic I/O Port
This section provides a block diagram of a basic I/O port.
■ Block Diagram of Basic I/O Port
Figure 5.2-1 shows the basic configuration of the I/O ports.
Figure 5.2-1 Block Diagram of Basic I/O Ports
Data Bus
Resource input
PDR read
pin
PDR
Resource output
DDR
Resource output
enabled
PDR : Port Data Register
DDR : Data Direction Register
I/O ports contain a port data register (PDR) and a data direction register (DDR).
•
Input mode (DDR = 0):
PDR read: The level of the corresponding external pin is read.
PDR write: The setting value is written to the PDR.
•
Output mode (DDR = 1):
PDR read: The value of the PDR is read.
PDR write: The value of the PDR is outputted to the corresponding pin.
The ports that have these functions are P20 to P27, P30 to P37, P40 to P47, P50 to P57, P80 to
P86, PE0 to PE7, PF0 to PF4, PG0 to PG5, PK0 to PK7, and PL0 to PL7.
Note:
The analog input control register (AICR) is used for control of switching between using the analog
pins (A/D) as resources or ports. AICR controls whether port K is used for analog input or as
general-purpose port.
0: General-purpose port
1: Analog input (A/D)
155
CHAPTER 5 I/O PORTS
5.3
Block Diagram of I/O Ports (Including the Pull-up Resistor)
This section provides a block diagram of an I/O port with a pull-up resistor.
■ Block Diagram of I/O Port with a Pull-Up Resistor
Figure 5.3-1 shows a block diagram of an I/O port with a pull-up resistor.
Figure 5.3-1 Block Diagram of a I/O Port Including the Pull-up Resistor
Data Bus
Resource input
0
Pull-up resistor (approximately 50 kΩ)
1
PDR read
pin
0
PDR
Resource output
DDR
1
Resource output
enabled
PCR
PDR : Port Data Register
DDR : Data Direction Register
PCR : Pull-up Control Register
The ports that have these functions are P60 to P67, PD0 to PD7, and PC0 to PC7.
Notes:
• Pull-up resistor control register (PCR): Specifies whether to turn the pull-up resistor on or off.
0: Pull-up resistor is OFF
1: Pull-up resistor is ON
• In stop mode, the setting of the pull-up resistor control register is prioritized.
• When the pin is used as an external bus pin, the pull-up resistor control function cannot be used.
Do not write 1 to this register.
156
CHAPTER 5 I/O PORTS
5.4
Block Diagram of I/O Ports (Including the Open-Drain
Output Function and the Pull-up Resistor)
This section provides a block diagram of an I/O port with open-drain output function
and a pull-up resistor.
■ Block Diagram of I/O Port with Open-Drain Output Function and Pull-Up Resistor
Figure 5.4-1 shows a block diagram of an I/O port with open-drain output function and a pull-up
resistor.
Figure 5.4-1 Block Diagram of a I/O Port Including the Open-drain Output and the Pull-up Resistor
Data Bus
Resource input
0
1
PDR read
pin
0
PDR
Resource output
DDR
1
Resource output
enabled
OCR
PCR
PDR : Port Data Register
DDR : Data Direction Register
OCR : Open-drain Control Register
PCR : Pull-up Control Register
The ports that have the above function are PH0 to PH5 and PI0 to PI5.
157
CHAPTER 5 I/O PORTS
Notes:
• Pull-up resistor control register (PCR): Specifies whether to turn the pull-up resistor on or off.
0: Pull-up resistor is OFF
1: Pull-up resistor is ON
• Open-drain control register (OCR): Specifies whether the port is used for standard output or
open-drain output.
0: Standard output port (in output mode)
1: Open-drain output port (in output mode)
In input mode, these settings have no effect (output Hi-Z). Whether input or output mode is
applied is determined based on the value in the data direction register (DDR).
• In stop mode, the setting of the pull-up resistor control register is prioritized.
• When this pin is used as an external bus pin, neither the pull-up resistor control function nor
open-drain control function can be used. Do not write 1 to these registers.
158
CHAPTER 5 I/O PORTS
5.5
Block Diagram of I/O Port (With Open-Drain Output
Function)
This section provides a block diagram of an I/O port with open-drain output function.
■ Block Diagram of I/O Port With Open-Drain Output Function
Figure 5.5-1 shows a block diagram of an I/O port with open-drain output function.
Figure 5.5-1 Block Diagram of I/O Port With Open-Drain Output Function
Data Bus
RMW
Resource output
Resource input
RMW = 0
RMW = 1
pin
PDR read
PDR
PDR : Port Data Register
The ports that have the above function are PJ0 and PJ1.
Notes:
• When the pin is used as input port or for resource input, set the PDR and resource output to 1.
• In RMW read mode, the PDR value, not the pin value, is read.
159
CHAPTER 5 I/O PORTS
5.6
Port Data Register (PDR2 to PDRL)
The port data registers (PDR2 to PDRL) are I/O data registers of the I/O ports. The
corresponding data direction registers (DDR2 to DDRL) control input and output.
■ Port Data Register (PDR2 to PDRL)
The register configuration of the port data register (PDR2 to PDRL) is shown below.
160
PDR2
Address: 000001H
7
P27
6
P26
5
P25
4
P24
3
P23
2
P22
1
P21
0
P20
Initial value
XXXXXXXXB
Access
R/W
PDR3
Address: 000000H
7
P37
6
P36
5
P35
4
P34
3
P33
2
P32
1
P31
0
P30
Initial value
XXXXXXXXB
Access
R/W
PDR4
Address: 000007H
7
P47
6
P46
5
P45
4
P44
3
P43
2
P42
1
P41
0
P40
Initial value
XXXXXXXXB
Access
R/W
PDR5
Address: 000006H
7
P57
6
P56
5
P55
4
P54
3
P53
2
P52
1
P51
0
P50
Initial value
XXXXXXXXB
Access
R/W
PDR6
Address: 000005H
7
P67
6
P66
5
P65
4
P64
3
P63
2
P62
1
P61
0
P60
Initial value
XXXXXXXXB
Access
R/W
PDR8
Address: 00000BH
7
−
6
P86
5
P85
4
P84
3
P83
2
P82
1
P81
0
P80
Initial value
-XXXXXXXB
Access
R/W
PDRC
Address: 000013H
7
PC7
6
PC6
5
PC5
4
PC4
3
PC3
2
PC2
1
PC1
0
PC0
Initial value
XXXXXXXXB
Access
R/W
PDRD
Address: 000012H
7
PD7
6
PD6
5
PD5
4
PD4
3
PD3
2
PD2
1
PD1
0
PD0
Initial value
XXXXXXXXB
Access
R/W
PDRE
Address: 000011H
7
PE7
6
PE6
5
PE5
4
PE4
3
PE3
2
PE2
1
PE1
0
PE0
Initial value
XXXXXXXXB
Access
R/W
PDRF
Address: 000010H
7
−
6
−
5
−
4
PF4
3
PF3
2
PF2
1
PF1
0
PF0
Initial value
---XXXXXB
Access
R/W
PDRG
Address: 000017H
7
−
6
−
5
PG5
4
PG4
3
PG3
2
PG2
1
PG1
0
PG0
Initial value
--XXXXXXB
Access
R/W
PDRH
Address: 000016H
7
−
6
−
5
PH5
4
PH4
3
PH3
2
PH2
1
PH1
0
PH0
Initial value
--XXXXXXB
Access
R/W
PDRI
Address: 000015H
7
−
6
−
5
PI5
4
PI4
3
PI3
2
PI2
1
PI1
0
PI0
Initial value
--XXXXXXB
Access
R/W
PDRJ
Address: 000014H
7
−
6
−
5
−
4
−
3
−
2
−
1
PJ1
0
PJ0
Initial value
------11B
Access
R/W
PDRK
Address: 00001BH
7
PK7
6
PK6
5
PK5
4
PK4
3
PK3
2
PK2
1
PK1
0
PK0
Initial value
XXXXXXXXB
Access
R/W
PDRL
Address: 00001AH
7
PL7
6
PL6
5
PL5
4
PL4
3
PL3
2
PL2
1
PL1
0
PL0
Initial value
XXXXXXXXB
Access
R/W
CHAPTER 5 I/O PORTS
5.7
Data Direction Register (DDR2 to DDRL)
The data direction registers (DDR2 to DDRL) control in units of bits whether the
corresponding I/O ports perform input or output. When 0 is set, input is performed,
when 1 is set, output is performed.
■ Data Direction Register (DDR2 to DDRL)
The register configuration of the data direction register (DDR2 to DDRL) is shown below.
DDR2
Address: 00000601H
7
P27
6
P26
5
P25
4
P24
3
P23
2
P22
1
P21
0
P20
Initial value
00000000B
Access
W
DDR3
Address: 00000600H
7
P37
6
P36
5
P35
4
P34
3
P33
2
P32
1
P31
0
P30
Initial value
00000000B
Access
W
DDR4
Address: 00000607H
7
P47
6
P46
5
P45
4
P44
3
P43
2
P42
1
P41
0
P40
Initial value
00000000B
Access
W
DDR5
Address: 00000606H
7
P57
6
P56
5
P55
4
P54
3
P53
2
P52
1
P51
0
P50
Initial value
00000000B
Access
W
DDR6
Address: 00000605H
7
P67
6
P66
5
P65
4
P64
3
P63
2
P62
1
P61
0
P60
Initial value
00000000B
Access
W
DDR8
Address: 0000060BH
7
−
6
P86
5
P85
4
P84
3
P83
2
P82
1
P81
0
P80
Initial value
-0000000B
Access
W
DDRC
Address: 0000FFH
7
PC7
6
PC6
5
PC5
4
PC4
3
PC3
2
PC2
1
PC1
0
PC0
Initial value
00000000B
Access
R/W
DDRD
Address: 0000FEH
7
PD7
6
PD6
5
PD5
4
PD4
3
PD3
2
PD2
1
PD1
0
PD0
Initial value
00000000B
Access
R/W
DDRE
Address: 0000FDH
7
PE7
6
PE6
5
PE5
4
PE4
3
PE3
2
PE2
1
PE1
0
PE0
Initial value
00000000B
Access
R/W
DDRF
Address: 0000FCH
7
−
6
−
5
−
4
PF4
3
PF3
2
PF2
1
PF1
0
PF0
Initial value
---00000B
Access
R/W
DDRG
Address: 000103H
7
−
6
−
5
PG5
4
PG4
3
PG3
2
PG2
1
PG1
0
PG0
Initial value
--000000B
Access
R/W
DDRH
Address: 000102H
7
−
6
−
5
PH5
4
PH4
3
PH3
2
PH2
1
PH1
0
PH0
Initial value
--000000B
Access
R/W
DDRI
Address: 000101H
7
−
6
TEST
5
PI5
4
PI4
3
PI3
2
PI2
1
PI1
0
PI0
Initial value
-0000000B
Access
R/W
DDRK
Address: 000107H
7
PK7
6
PK6
5
PK5
4
PK4
3
PK3
2
PK2
1
PK1
0
PK0
Initial value
00000000B
Access
R/W
DDRL
Address: 000106H
7
PL7
6
PL6
5
PL5
4
PL4
3
PL3
2
PL2
1
PL1
0
PL0
Initial value
00000000B
Access
R/W
Note:
DDRI bit6 is a test bit. Always set the bit to 0. The value read from this bit is always 0.
161
CHAPTER 5 I/O PORTS
5.8
Pull-up Resistor Control Register (PCR6 to PCRI)
Each of the pull-up resistor control registers (PCR6 to PCRI) specifies controls the
pull-up resistor for the corresponding I/O port in input mode.
• PCR = 0: Disables the pull-up resistor in input mode.
• PCR = 1: Enables the pull-up resistor in input mode.
The PCR has no meaning in output mode (no pull-up resistor disabled).
■ Pull-up Resistor Control Register (PCR6 to PCRI)
The bit configuration of the pull-up resistor control register (PCR6 to PCRI) is shown below:
162
PCR6
Address: 000631H
7
P67
6
P66
5
P65
4
P64
3
P63
2
P62
1
P61
0
P60
Initial value
00000000B
Access
R/W
PCRC
Address: 0000F7H
7
PC7
6
PC6
5
PC5
4
PC4
3
PC3
2
PC2
1
PC1
0
PC0
Initial value
00000000B
Access
R/W
PCRD
Address: 0000F6H
7
PD7
6
PD6
5
PD5
4
PD4
3
PD3
2
PD2
1
PD1
0
PD0
Initial value
00000000B
Access
R/W
PCRH
Address: 0000F5H
7
−
6
−
5
PH5
4
PH4
3
PH3
2
PH2
1
PH1
0
PH0
Initial value
--000000B
Access
R/W
PCRI
Address: 0000F4H
7
−
6
−
5
PI5
4
PI4
3
PI3
2
PI2
1
PI1
0
PI0
Initial value
--000000B
Access
R/W
CHAPTER 5 I/O PORTS
5.9
Open-Drain Control Register (OCRH and OCRI)
Each of the open-drain control registers (OCRH and OCRI) specifies whether the
corresponding I/O port is used for standard output or open-drain output while the port
is used in output mode.
• OCR = 0: Standard output port in output mode
• OCR = 1: Open-drain output port in output mode
The OCR has no meaning in input mode (Hi-Z output).
■ Open-Drain Control Register (OCRH and OCRI)
The structure of the open-drain control register (OCRH and OCRI) is shown below:
OCRH
Address: 0000F9H
7
−
6
−
5
PH5
4
PH4
3
PH3
2
PH2
1
PH1
0
PH0
Initial value
--000000B
Access
R/W
OCRI
Address: 0000F8H
7
−
6
−
5
PI5
4
PI4
3
PI3
2
PI2
1
PI1
0
PI0
Initial value
--000000B
Access
R/W
163
CHAPTER 5 I/O PORTS
5.10 Analog Input Control Register (AICR)
The analog input control register (AICR) controls the pins of the corresponding I/O
port as follows:
• AICR = 0: Port input mode
• AICR = 1: Analog input mode
The AICR is cleared to 0 by resetting.
■ Analog Input Control Register (AICR)
The structure of the analog input control register (AICR) is shown below:
AICR
Address: 0000EBH
164
7
PK7
6
PK6
5
PK5
4
PK4
3
PK3
2
PK2
1
PK1
0
PK0
Initial value
00000000B
Access
R/W
CHAPTER 6 8/16-BIT UP/DOWN COUNTERS/TIMERS
CHAPTER 6
8/16-BIT UP/DOWN COUNTERS/TIMERS
This chapter describes the overview of the 8/16-bit up/down counters/timers, their
block diagrams, their configurations and functions of the registers, as well as the
operation of the 8/16-bit up/down counters/timers.
6.1 Overview of 8/16-bit Up/Down Counters/Timers
6.2 Block diagram of the 8/16-bit Up/Down Counters/Timers
6.3 List of Registers of the 8/16-bit Up/Down Counters/Timers
6.4 Selection of Counting Mode
6.5 Reload and Compare Functions
6.6 Writing data to the up/down count register (UDCR0, UDCR1)
165
CHAPTER 6 8/16-BIT UP/DOWN COUNTERS/TIMERS
6.1
Overview of 8/16-bit Up/Down Counters/Timers
The 8/16-bit up/down counters/timers consist of six event input pins, two 8-bit up/
down counters, two 8-bit reload/compare registers, and their control circuits.
■ Characteristics of the 8/16-bit Up/Down Counters/Timers
•
With the 8-bit count register, counting can be performed in a range between 0 and 255 (00H
to FFH) (decimal numbers). In 16-bit × 1 operation mode, counting can be performed in a
range between 0 and 65535 (0000H to FFFFH) (decimal numbers).
•
The following four count modes can be selected for the count clock:
•
•
Timer mode
•
Up/down counter mode
•
Phase difference count mode (multiply-by-2)
•
Phase difference count mode (multiply-by-4)
In timer mode, one of the following internal clocks can be selected for the count clock during
33.3 MHz operation:
•
60 ns (16.67 MHz:1/2 division)
•
240 ns (4.17 MHz:1/8 division)
The detection edge of the external pin input signal can be selected in up and in down
counting mode.
•
Detection of trailing edges
•
Detection of leading edges
•
Detection of both trailing and leading edges
•
Edge detection disabled
•
The phase difference counting mode is suitable for counting for an encoder, such as for a
motor. Using one of A phase output, B phase output, and Z phase output as input allows to
count rotation angle and number of rotations easily and with high precision.
•
Two different functions can be selected for the ZIN pin (this applies for all modes).
•
166
•
•
Counter clear function
•
Gate function
The compare function and reload function are available. These functions can be used
separately or combined. By combining these functions, counting up or down can be
performed with an arbitrary width.
•
Compare function (compare interrupt request output)
•
Compare function (compare interrupt request output and counter clearing)
•
Reload function (underflow interrupt request output and reloading)
•
Compare and reload function (compare interrupt request output, counter clearing,
underflow interrupt request output, and reloading)
•
Compare and reload disabled
CHAPTER 6 8/16-BIT UP/DOWN COUNTERS/TIMERS
•
With the count direction flag, the counting direction immediately before the current count can
be identified.
•
The generation of interrupts when a compare match occurs, at reload (underflow), at
overflow, or when the counting direction changes, can be controlled individually.
167
CHAPTER 6 8/16-BIT UP/DOWN COUNTERS/TIMERS
6.2
Block diagram of the 8/16-bit Up/Down Counters/Timers
This section provides block diagrams of the 8/16-bit up/down counters/timers.
■ Block Diagram of the 8/16-bit Up/Down Counters/Timers
❍ Channel 0
Figure 6.2-1 shows a block diagram of the 8/16-bit up/down counters/timers (for Channel 0).
Figure 6.2-1 Block Diagram of the 8/16-bit Up/Down Counters/Timers (Channel 0)
Data bus
8 bits
CGE1
ZIN0
CGE0
RCR0 (Reload/compare register 0)
CGSC
CTUT
Control reload
UCRE
RLDE
Detects edge or level
Clear counter
UDCC
8 bits
UDCR0 (Up/down count register 0)
Carry
CES1
CES0
CMS1
CMS0
UDFF
CITE
Count clock
AIN0
BIN0
Select up or down
count clock
Prescaler
UDF1
UDF0
CDCF
CFIE
CSTR
Output interrupt
CLKS
168
UDIE
OVFF
CMPF
CHAPTER 6 8/16-BIT UP/DOWN COUNTERS/TIMERS
❍ Channel 1
Figure 6.2-2 shows a block diagram of the 8/16-bit up/down counters/timers (for Channel 1).
Figure 6.2-2 Block Diagram of the 8/16-bit Up/Down Counters/Timers (Channel 1)
Data bus
8 bits
CGE1
ZIN1
CGE0
RCR1 (Reload/compare register 1)
CGSC
CTUT
Control reload
UCRE
RLDE
Detects edge or level
Clear counter
UDCC
8 bits
UDCR1 (Up/down count register 1)
CMPF
UDFF
CMS1
CMS0
CES1
CES0
OVFF
M16E
CITE
UDIE
Carry
Count clock
AIN1
BIN1
Select up or down
count clock
Prescaler
UDF1
UDF0
CDCF
CFIE
CSTR
Output interrupt
CLKS
169
CHAPTER 6 8/16-BIT UP/DOWN COUNTERS/TIMERS
6.3
List of Registers of the 8/16-bit Up/Down Counters/Timers
This section provides a listing of 8/16-bit up/down counter/timer registers.
■ List of Registers of the 8/16-bit Up/Down Counters/Timers
Figure 6.3-1 lists the registers of the 8/16-bit up/down counters/timers.
Figure 6.3-1 List of Registers of the 8/16-bit Up/Down Counters/Timers
31
24 23
16 15
8 7
0
RCR1
RCR0
UDCR1
UDCR0
CCRH0
CCRL0
−
CSR0
CCRH1
CCRL1
−
CSR1
bit
Address: 00005FH
7
6
5
4
3
2
1
0
D07
D06
D05
D04
D03
D02
D01
D00
Up/down count
register ch0
(UDCR0)
bit
15
14
13
12
11
10
9
8
Address: 00005EH
D15
D14
D13
D12
D11
D10
D09
D08
Up/down count
register ch1
(UDCR1)
bit
Address: 00005DH
7
6
5
4
3
2
1
0
D07
D06
D05
D04
D03
D02
D01
D00
Reload compare
register ch0
(RCR0)
bit
Address: 00005CH
15
14
13
12
11
10
9
8
D15
D14
D13
D12
D11
D10
D09
D08
Reload compare
register ch1
(RCR1)
bit
7
Address: 000063H CSTR
000067H
bit
Address: 000061H
000065H
bit
7
−
15
6
CITE
6
bit
170
15
−
4
3
2
1
0
Counter status
5
4
3
2
1
0
Counter control
CTUT UCRE RLDE UDCC CGSC CGE1 CGE0 register ch0,1
(CCRL0,1)
14
Address: 000060H M16E CDCF
Address: 000064H
5
UDIE CMPF OVFF UDFF UDF1 UDF0 register ch0,1
(CSR0,1)
13
CFIE
14
13
CDCF
CFIE
12
11
10
9
8
Counter control
CLKS CMS1 CMS0 CES1 CES0 register ch0
(CCRH0)
12
11
10
9
8
Counter control
CLKS CMS1 CMS0 CES1 CES0 register ch1
(CCRH1)
CHAPTER 6 8/16-BIT UP/DOWN COUNTERS/TIMERS
6.3.1
Counter Control Register H/L ch0 (CCRH/CCRL)
This section describes the counter control register H/L ch0 (CCRH/CCRL).
■ Counter Control Register High/Low ch0 (CCRH/CCRL)
The structure of the counter control register H/L ch0 (CCRH/CCRL) is shown below:
bit
15
Address: 000060H M16E
R/W
7
000061H
−
14
13
12
CDCF
R/W
CFIE
R/W
CLKS
R/W
11
6
5
4
10
CMS1 CMS0
R/W
R/W
3
2
9
8
Initial value
CES1
R/W
CES0
R/W
00000000B
0
Initial value
CGE0
R/W
-000X000B
1
CTUT UCRE RLDE UDCC CGSC CGE1
R/W
R/W
R/W
W
R/W
R/W
[bit15] M16E: 16-bit mode permission setting bit
8 bits × 2 channels/16 bits × 1 channel operation mode selection (switching) bit
M16E
16-bit mode permission setting
0
8 bits × 2 channels operation mode (initial value)
1
16 bits × 1 channel operation mode
171
CHAPTER 6 8/16-BIT UP/DOWN COUNTERS/TIMERS
[bit14] CDCF: Count direction change flag
This flag is set when the count direction is changed. When the count direction is changed
from up to down or down to up during counting, this flag is set to 1.
0: Writing 0 clears the setting.
1: Writing 1 is ignored. The value of this bit is not changed.
CDCF
Direction change detection
0
Direction has not been changed (initial value).
1
Direction has been changed once or more.
[bit13] CFIE: Count direction change interrupt enable bit
This bit controls the interrupt output for the CPU when CDCF is set. An interrupt occurs if
the count direction is changed at least once during counting.
CFIE
Direction change interrupt output
0
Disables direction change interrupt output (initial value).
1
Enables direction change interrupt output.
[bit12] CLKS: Internal prescaler selection bit
When timer mode is selected, this bit selects the frequency of the internal prescaler.
This bit is effective only in timer mode and only for down counting.
CLKS
Selected internal clock
0
Two machine cycles (initial value)
1
Eight machine cycles
[bit11, bit10] CMS1 and CMS0: Counting mode selection bit
This bit selects counting mode.
172
CMS1
CMS0
Counting mode
0
0
Timer mode [down count] (initial value)
0
1
Up or down counting mode
1
0
Phase difference counting mode, 2 multiplication
1
1
Phase difference counting mode, 4 multiplication
CHAPTER 6 8/16-BIT UP/DOWN COUNTERS/TIMERS
[bit9, bit8] CES1 and CES0: Count clock edge selection bit
In up/down counting mode, this bit selects the detection edge of external pins AIN and BIN.
This setting is invalid in modes other than up or down counting mode.
CES1
CES0
Selection edge
0
0
Disables edge detection (initial value).
0
1
Detects falling edge.
1
0
Detects rising edge.
1
1
Detects rising and falling edges.
[bit6] CTUT: Counter write bit
This bit transfers data from RCR to UDCR.
When this bit is set to1, data is transferred from RCR to UDCR.
Writing 0 to this bit has no effect. The read value is always 0.
Do not set this bit to 1 during counting (when the CSTR bit of the CSR is 1).
[bit5] UCRE: UDCR clear enable bit
This bit controls the compare operation that clears UDCR.
UDCR clear functions other than clearing due to comparing (such as due to the ZIN pin), are
not affected.
UCRE
Counter clear by compare
0
Disables counter clear (initial value).
1
Enables counter clear.
[bit4] RLDE: Reload enable bit
This bit controls the start of the reload function. When the reload function is started, if UDCR
leads the underflow, this bit transfers the value of RCR to UDCR.
RLDE
Reload function
0
Disables the reload function (initial value).
1
Enables the reload function.
[bit3] UDCC: UDCR clear bit
This bit clears the UDCR. When this bit is set to 0, the UDCR is cleared to 0000H. Writing 1
to this bit has no effect. The read value is undefined.
173
CHAPTER 6 8/16-BIT UP/DOWN COUNTERS/TIMERS
[bit2] CGSC: Counter clear/gate selection bit
This bit selects the function of the external pin ZIN.
CGSC
ZIN function
0
Counter clear function (initial value)
1
Gate function
[bit1, bit0] CGE1 and CGE0: Counter clear/gate edge selection bit
This bit selects the detection edge/level of the external pin ZIN.
174
CGE1
CGE0
When counter clear function
is selected
When gate function is
selected
0
0
Disables edge detection (initial
value).
Disables level detection
(count disable)
0
1
Falling edge
"L" level
1
0
Rising edge
"H" level
1
1
Setting not allowed
Setting not allowed
CHAPTER 6 8/16-BIT UP/DOWN COUNTERS/TIMERS
6.3.2
Counter Control Register H/L ch1 (CCRH/CCRL)
This section describes the counter control register H/L ch1 (CCRH/CCRL).
■ Counter Control Register High/Low ch1 (CCRH/CCRL)
The structure of the counter control register H/L ch1 (CCRH/CCRL) is shown below:
bit
Address: 000064H
15
14
13
12
−
R/W
CDCF
R/W
CFIE
R/W
CLKS
R/W
6
5
4
7
000065H
−
11
10
CMS1 CMS0
R/W
R/W
3
2
9
8
Initial value
CES1
R/W
CES0
R/W
-0000000B
1
0
Initial value
CTUT UCRE RLDE UDCC CGSC CGE1 CGE0
R/W
R/W
R/W
W
R/W
R/W
R/W
-000X000B
For details of the individual bits, see Section "6.3.1 Counter Control Register H/L ch0 (CCRH/
CCRL)".
175
CHAPTER 6 8/16-BIT UP/DOWN COUNTERS/TIMERS
6.3.3
Counter status register 0/1 (CSR0, CSR1)
The register configuration of counter status register 0/1 (CSR0, CSR1) is shown below.
■ Counter Status Register 0/1 (CSR0, CSR1)
The structure of counter status register 0/1 is shown below:
bit
7
Address:000063H CSTR
000067H R/W
6
5
CITE
R/W
UDIE
R/W
4
3
CMPF OVFF
R/W
R/W
2
1
0
Initial value
UDFF
R/W
UDF1
R
UDF0
R
00000000B
[bit7] CSTR: Count start bit
This bit controls the start and stop of UDCR counting.
CSTR
Operation
0
Stops the counting operation (initial value)
1
Starts the counting operation
[bit6] CITE: Compare interrupt output control bit
This bit controls whether to enable or disable interrupt output to the CPU when a compare
detection flag (CMPF) is set (during a compare operation).
CITE
Compare interrupt output
0
Disables compare interrupt output (initial value).
1
Enables compare interrupt output.
[bit5] UDIE: Overflow/underflow interrupt output control bit
This bit controls whether to enable or disable interrupt output to the CPU when OVFF/UDFF
is set (when overflow or underflow occurs).
UDIE
176
Overflow/underflow interrupt output
0
Disables overflow/underflow interrupt output (initial value).
1
Enables overflow/underflow interrupt output.
CHAPTER 6 8/16-BIT UP/DOWN COUNTERS/TIMERS
[bit4] CMPF: Compare detection flag
This flag indicates that the comparison result of the UDCR value and RCR value is that the
values are equal. In write operations, the flag can only be set to 0, not to 1.
CMPF
Meaning of flag
0
Comparison result does not match (initial value).
1
Comparison result matches.
[bit3] OVFF: Overflow detection flag
This flag indicates the occurrence of an overflow. During write operations, this flag can only
be set to 0, not to 1.
OVFF
Meaning of flag
0
No overflow (initial value)
1
Overflow
[bit2] UDFF: Underflow detection flag
This flag indicates that an underflow occurs. During write operations, this flag can only be
set to 0, not to 1.
UDFF
Meaning of flag
0
No underflow (initial value)
1
Underflow
[bit1, bit0] UDF1 and UDF0: Up/down flag
These bits indicate the type of a counting operation (up or down) immediately preceding the
current operation. Only reading is allowed. No writing is allowed.
UDF1
UDF0
Detection edge
0
0
No input (initial value)
0
1
Down count
1
0
Up count
1
1
Both up and down counting were performed simultaneously.
177
CHAPTER 6 8/16-BIT UP/DOWN COUNTERS/TIMERS
6.3.4
Up/down count register 0/1 (UDCR0, UDCR1)
The register configuration of the up/down count register 0/1 (UDCR0, UDCR1) is shown
below.
■ Up/Down Count Register 0/1 (UDCR0, UDCR1)
The structure of the up/down count register 0/1 is shown below:
bit
15
14
13
12
11
10
9
8
Initial value
Address: 00005EH
UDCR1
D15
R
D14
R
D13
R
D12
R
D11
R
D10
R
D09
R
D08
R
00000000B
7
6
5
4
3
2
1
0
Initial value
00005FH
UDCR0
D07
R
D06
R
D05
R
D04
R
D03
R
D02
R
D01
R
D00
R
00000000B
This register is an 8-bit count register. Up/down counting is performed with an internal prescaler
or an input through the AIN pin or BIN pin. In 16-bit counting mode, this bit operates as a 16-bit
count register. In this case, the setting value in the control register for the higher 8 bits is invalid
for the operation.
Values cannot be written to this register directly. To write a value to this register, the RCR must
be used. First write the value to write to this register to the RCR, then set the CTUT bit of the
CCRL register to 1. The value will then be transferred from the RCR to this register (in a reloadoperation by software).
In 16-bit mode, perform a 16-bit read operation for this register once.
178
CHAPTER 6 8/16-BIT UP/DOWN COUNTERS/TIMERS
6.3.5
Reload/compare register 0/1 (RCR0, RCR1)
The register configuration of the reload/compare register 0/1 (RCR0, RCR1) is shown
below.
■ Reload/Compare Register 0/1 (RCR0, RCR1)
The structure of the reload/compare register 0/1 is shown below:
15
14
13
12
11
10
9
8
Initial value
Address: 00005CH
RCR1
bit
D15
W
D14
W
D13
W
D12
W
D11
W
D10
W
D09
W
D08
W
00000000B
7
6
5
4
3
2
1
0
Initial value
00005DH
RCR0
D07
W
D06
W
D05
W
D04
W
D03
W
D02
W
D01
W
D00
W
00000000B
This register is an 8-bit reload/compare register. This register sets the reload value and
compare value. The reload value and compare value are the same. Starting the reload function
and compare function enables counting up or down between 00H and the value of this register
(In 16-bit operation mode: counting up and down between 0000H and the value of this register).
Only writing is allowed for this register. This register cannot be read. By setting the CTUT bit of
the CCR0, CCR1 register to 1 while counting is stopped, the value of this register can be
transferred to the UDCR (reloaded by software).
Write a 16-bit value to this register once.
179
CHAPTER 6 8/16-BIT UP/DOWN COUNTERS/TIMERS
6.4
Selection of Counting Mode
This timer/counter has four counting modes. The CMS1 and CMS0 bits of the CCR
register can be used to select these counting modes.
■ Selecting Counting Mode
Table 6.4-1 lists the count modes that can be selected by the CMS1 and CMS0 bits.
Table 6.4-1 Selecting Timer Counting Mode
CMS1, CMS0
Counting mode
00B
Timer mode [down count]
01B
Up/down counting mode
10B
Phase difference counting mode, 2 multiplication
11B
Phase difference counting mode, 4 multiplication
■ Timer Mode [Down Count]
In timer mode, the output of the internal prescaler is used for counting down. For the internal
prescaler, either two machine cycles or eight machine cycles can be selected with the CLKS bit
of the CCRH register.
■ Up/Down Counting Mode
In up/down counting mode, counting up/down is performed by counting the input through
external pins AIN and BIN. The input through the AIN pin controls counting up and the input
through the BIN pin controls counting down.
The inputs through the AIN pin and BIN pin are subject to edge-detected. The edge detection
can be selected by the CES1 and CES0 bits of the CCRH register.
Table 6.4-2 Selecting the Detection Edge
CES1, CES0
Detection edge
00B
Disables the edge detection.
01B
Detects rising edge.
10B
Detects falling edge.
11B
Detects both falling and rising edges.
■ Phase Difference Counting Mode (Two Multiplication/Four Multiplication)
In phase difference counting mode, to count the phase difference between phase A and phase
B of the output signal for encoder, detect the input level of the BIN pin at input edge detection of
the AIN pin and detect the input level of the AIN pin at input edge detection of the BIN pin.
For the phase difference between AIN pin input and BIN pin input in two multiplication or four
multiplication mode, count up if the AIN pin is faster, and count down if the BIN pin is faster.
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CHAPTER 6 8/16-BIT UP/DOWN COUNTERS/TIMERS
❍ Multiply-by-2 mode
In two multiplication mode, counting is performed by detecting the value of the AIN pin in the
period between the rising and falling edges of the BIN pin. In this case, counting is performed
as follows:
•
When the value of the AIN pin detected at the rising edge of the BIN pin is "H", count up.
•
When the value of the AIN pin detected at the rising edge of the BIN pin is "L", count down.
•
When the value of the AIN pin detected at the falling edge of the BIN pin is "H", count down.
•
When the value of the AIN pin detected at the falling edge of the BIN pin is "L", count up.
Figure 6.4-1 shows the overview of the phase difference counting mode (two multiplication)
operation.
Figure 6.4-1 Overview of the Phase Difference Counting Mode (Two Multiplication) Operation
AIN pin
BIN pin
Count
value
0
+1
+1
+1
+1
+1
-1
+1
-1
-1
-1
-1
-1
1
2
3
4
5
4
5
4
3
2
1
0
❍ Multiply-by-4 mode
In four-multiplication mode, counting is performed by detecting the value of the AIN pin at the
rising and falling edges of the BIN pin, and detecting the value of the BIN pin at the rising and
falling edges of the AIN pin. In this case, counting is performed as follows:
•
When the value of the AIN pin detected at the rising edge of the BIN pin is "H", count up.
•
When the value of the AIN pin detected at the rising edge of the BIN pin is "L", count down.
•
When the value of the AIN pin detected at the falling edge of the BIN pin is "H", count down.
•
When the value of the AIN pin detected at the falling edge of the BIN pin is "L", count up.
•
When the value of the BIN pin detected at the rising edge of the AIN pin is "H", count down.
•
When the value of the BIN pin detected at the rising edge of the AIN pin is "L", count up.
•
When the value of the BIN pin detected at the falling edge of the AIN pin is "H", count up.
•
When the value of the BIN pin detected at the falling edge of the AIN pin is "L", count down.
Figure 6.4-2 shows an overview of operation in phase difference counting (multiply-by-4) mode.
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CHAPTER 6 8/16-BIT UP/DOWN COUNTERS/TIMERS
Figure 6.4-2 Overview of the Phase Difference Counting Mode (Four Multiplication) Operation
AIN pin
BIN pin
Count
value
0
+1
+1 +1
+1
+1
1
2 3
4
5
+1 +1
6
7
+1
+1
+1
-1
+1
-1
-1
-1
-1 -1
-1
-1
-1 -1
8
9
10
9
10
9
8
7
6 5
4
3
2 1
For counting the encoder output, by inputting the A phase to the AIN pin, the B phase to the BIN
pin, and the Z phase to the ZIN pin, a highly precise count of the rotation angle and number of
rotations can be obtained and the rotation direction can be detected as well.
When this counting mode is selected, the selection of the detection edge with CES1 and CES0
of CCRM is invalid.
182
CHAPTER 6 8/16-BIT UP/DOWN COUNTERS/TIMERS
6.5
Reload and Compare Functions
The 8/16-bit up/down counters/timers have the reload and compare functions. These
two functions can be combined for processing.
■ Example for Selection of Reload and Compare Function
Table 6.5-1 shows an example for the selection of the reload/compare function.
Table 6.5-1 Example for Selection of Reload and Compare Function
RLDE, UCRE
Reload/compare function
00B
Disables reload/compare (initial value).
01B
Enables compare.
10B
Enables reload.
11B
Enables reload/compare.
■ When the Reload Function is Enabled
When the reload function is started, the value of the RCR is transferred to the UDCR with the
timing of the down count clock after an underflow. In this case, when UDFF is set, an interrupt
request is generated.
In a mode in which down counting is not performed, starting this function is invalid.
Figure 6.5-1 shows an overview of reload function operation.
Figure 6.5-1 Overview of the Operation for the Reload Function
(0FFFFH)
0FFH
Reload, interrupt occur.
Reload, interrupt occur.
RCR
00H
Underflow
Underflow
183
CHAPTER 6 8/16-BIT UP/DOWN COUNTERS/TIMERS
■ When the Compare Function is Enabled
The compare function can be used in all modes other than timer mode. When the compare
function is started, if the value of RCR and the value of UDCR match, CMPF is set and an
interrupt request is generated. When the compare clear function is started, the UDCR is
cleared with the timing of the up count clock.
In a mode in which up counting is not performed, starting this function is invalid.
Figure 6.5-2 shows an overview of compare function operation.
Figure 6.5-2 Overview of the Compare Function Operation
(0FFFFH)
0FFH
Compare match
Compare match
RCR
00H
Counter is cleared,
interrupt is generated.
Counter is cleared,
interrupt is generated.
■ When the Reload and Compare Functions are Enabled Simultaneously
When the reload/compare function is started, counting up or down can be performed with an
arbitrary width.
The reload function is started at an underflow and transfers the value of the RCR to the UDCR.
When the values of RCR and UDCR match, the compare function clears the UDCR. By using
these functions, counting up or down is performed for values between 0000H and the value of
the RCR.
Figure 6.5-3 shows an overview of operation when the reload and compare functions are
enabled simultaneously.
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CHAPTER 6 8/16-BIT UP/DOWN COUNTERS/TIMERS
Figure 6.5-3 Overview of the Operation when the Reload and Compare Functions are Started at the
Same Time
0FFH
Compare match Compare match
Reload
Reload
Reload
Compare match
Underflow
Underflow
Counter clear
RCR
00H
Counter clear Counter clear Underflow
An interrupt to the CPU can be generated at a compare match or at reload (underflow). These
interrupt outputs can be enabled separately.
The timing for reloading and clearing the UDCR is different during counting and when counting
is stopped.
•
During counting, if an event for reloading or clearing occurs, all the events are synchronized
with the counter clock (the figure shows the status when 0080H is reloaded).
UDCR
065H
066H
080H
081H
Synchronizes with this clock.
Reload/clear event
Counter clock
•
When an event for reloading and clearing occurs during counting, if counting is stopped in
counter clock synchronization wait state (state of waiting for the count input for
synchronization), the reload and clear operations are performed when counting is stopped
(the figure shows the state when 0080H is reloaded).
065H
UDCR
066H
080H
Reload/clear event
Counter clock
Count enable
Enable (counting permitted)
•
Disable (counting prohibited)
If an event for reloading or clearing occurs while the counter is stopped, reload and clear are
performed when the event occurs (the figure shows the state when 0080H is reloaded).
185
CHAPTER 6 8/16-BIT UP/DOWN COUNTERS/TIMERS
UDCR
065H
080H
Reload/clear event
Clear by compare is performed when the values of the UDCR and the RCR match and while
counting up. If down counting is performed or counting is stopped, the clear operation is not
performed even when the values of the UDCR and the RCR match.
As for the timing of clearing and reloading, the clear operation follows the above timing for all
events other than reset input, and reloading also uses the above timing for all events.
When the events for clearing and reloading occur at the same time, the clear event takes
priority.
186
CHAPTER 6 8/16-BIT UP/DOWN COUNTERS/TIMERS
6.6
Writing data to the up/down count register (UDCR0, UDCR1)
Data cannot be written to the up/down count register (UDCR0, UDCR1) directly from
the data bus. This section describes the procedure for writing, counter clearing, and
flags of the device.
■ Writing Data to the Up/Down Count Register (UDCR0, UDCR1)
To write data to the UDCR, follow the procedure below:
1. Write the data that is to be written to the UDCR first to the RCR (Note that this means that
the original data in the RCR will be lost).
2. By setting the CTUT of the CCR to 1, data is transferred from the RCR to the UDCR.
Perform the above operation while counting is stopped (when the CSTR bit of the CSR is 0).
Besides the above procedure, the following procedure can also be applied to clear the counter.
•
Clearing by reset input (initialization).
•
Clearing by edge input through the ZIN pin.
•
Clearing by writing 0 to UDCC of the CCR.
•
Clearing by compare.
The above can be performed regardless of the status of the counter (regardless of whether
counting is performed or stopped).
■ Count Clear/Gate Function
The ZIN pin can be used after selecting the count clear function or gate function based on the
CGSC bit of the CCR register.
When the count clear function is started, the ZIN pin clears the counter. The CGE1 and CGE0
bits of the CCRL register can control which edge input of the ZIN pin to use for clearing the
counter.
When the gate function is started, the ZIN pin enables or disables counting. The CGE1 and
CGE0 bits of the CCR register can control which level input of the ZIN pin enables counting.
This function is effective for all modes.
Table 6.6-1 summarizes how the ZIN pin functions are selected.
Table 6.6-1 Selecting the ZIN Pin Function
CGSC
ZIN pin function
CGE1,
CGE0
When counter clear
function is used
When gate function is
used
0
Counter clear function
00B
Disables detection.
Disables detection.
1
Gate function
01B
Rising edge
"L" level
10B
Falling edge
"H" level
187
CHAPTER 6 8/16-BIT UP/DOWN COUNTERS/TIMERS
■ Count Direction Flag
The count direction flag (UDF1 and UDF0) indicates at the time of up/down counting whether
the counting operation preceding the current operation was counting up or down. Based on the
counter clock signal from the input of the AIN and BIN pins, this value of this flag changes for
each count. By checking this flag, the current rotation angle can be determined.
Table 6.6-2 summarizes how the count direction flag works.
Table 6.6-2 Count Direction Flag
UDF1, UDF0
Count direction
01B
Down count
10B
Up count
11B
Up/down occurs simultaneously (no counting operation is performed).
■ Count Direction Change Flag
The CDCF is set when the counting direction changes between up and down. Simultaneously
to setting this flag, an interrupt request to the CPU can be generated. By referring the interrupt
and count direction flag, the direction to which counting is changed can be determined.
However, note that when the period of direction change is short and multiple direction changes
are performed in succession, the direction that the flag indicates after the direction change may
return to the original direction so that it appears as if the counting direction has not changed at
all in between.
Table 6.6-3 summarizes how the count direction change flag works.
Table 6.6-3 Count Direction Change Flag
CDCF
Count direction detection
0
No direction change
1
Counting direction has changed (at least once).
■ Compare Detection Flag
The CMPF is set when the values of UDCR and RCR match during counting. This flag is set for
a match during counting up, match by occurrence of a reloading event, as well as when the
values already match when counting started.
However, a match during counting down (other than a match by compare during reload due to
an underflow) is not regarded as a match, and this flag is not set.
■ Operations for 8 Bits × 2 Channels and 16 Bits × 1 Channel
This module can be used as an 8-bit up/down counter for two channels or a 16-bit up/down
counter for one channel. Setting the M16E bit of the CCRH0 register to 0 sets 8-bit mode for
two channels. Setting the bit to 1 sets 16-bit mode for one channel.
For operation in 16-bit mode for one channel, the registers CSR0, CCRL0, CCRH0 are valid
and the CSR1, CCRL1, and CCRH1 registers are invalid. In addition, the AIN0, BIN0, ZIN0 pins
are enabled as input pins, while the AIN1, BIN1, and ZIN1 pins are disabled.
188
CHAPTER 7 16-BIT RELOAD TIMERS
CHAPTER 7
16-BIT RELOAD TIMERS
This chapter describes the overview of the 16-bit reload timer, the configuration and
functions of the timer registers, and the operations of the 16-bit reload timer. The
chapter also provides a block diagram of the 16-bit reload timer.
7.1 Overview of 16-bit Reload Timer
7.2 Block diagram of a 16-bit Reload Timer
7.3 Registers of 16-bit Reload Timer
7.4 Internal Clock Operation
7.5 Underflow Operation
7.6 Counter Operation States
189
CHAPTER 7 16-BIT RELOAD TIMERS
7.1
Overview of 16-bit Reload Timer
The 16-bit reload timer consists of the following elements:
• 16-bit down counter
• 16-bit reload register
• Internal count clock generation prescaler
• Control register
■ Features of 16-bit Reload Timer
190
•
The input clock can be selected from three internal clocks (1/2, 1/8, and 1/32 of the machine
clock).
•
Interrupt-driven DMA transfer is supported.
•
This model contains four reload timer channels.
•
Output T0 of reload timer channel 2 is connected to the A/D converter in the LSI circuit.
Therefore, A/D conversion can be started at the intervals specified in the reload register.
CHAPTER 7 16-BIT RELOAD TIMERS
7.2
Block diagram of a 16-bit Reload Timer
Figure 7.2-1 shows a block diagram of the 16-bit reload timer.
■ Block Diagram of the 16-bit Reload Timer
Figure 7.2-1 Block Diagram of the 16-bit Reload Timer
16-bit reload register
16
8
Reload
RELD
16
16-bit down counter
OUTE
UF
R-bus
2
OUTL
OUT
CTL.
GATE
2
INTE
CSL1
UF
CSL0
CNTE
IRQ
Clock selector
2
TRG
IN CTL.
Retrigger
φ
φ
φ
21
23
25
3
Prescaler
clear
MOD2
PWM (ch0,ch1)
A/D (ch2)
MOD1
φ Internal clocks
MOD0
3
191
CHAPTER 7 16-BIT RELOAD TIMERS
7.3
Registers of 16-bit Reload Timer
Figure 7.3-1 lists the registers of the 16-bit reload timer.
■ Register List of the 16-bit Reload Timer
Figure 7.3-1 Register List of 16-bit Reload Timer
15
14
13
12
11
10
-
-
-
-
CSL1
CSL0
7
6
5
MOD0 OUTE OUTL
15
9
8
Control status register
MOD2 MOD1 (TMCSR0 to TMCSR3)
4
3
2
1
0
RELD
INTE
UF
CNTE
TRG
0 16-bit timer register
(TMR0 to TMR3)
15
0 16-bit reload register
(TMRLR0 to TMRLR3)
192
CHAPTER 7 16-BIT RELOAD TIMERS
7.3.1
Control status register (TMCSR0 to TMCSR3)
This register controls the operation mode and interrupts of the 16-bit timer.
Bits other than UF, CNTE, and TRG can be rewritten only when CNTE = 0.
Concurrent writing can be performed.
■ Control Status Register (TMCSR0 to TMCSR3)
The register configuration of the control status register (TMCSR) is shown below.
TMCSR
Address:
11
10
9
8
7
6
5
4
3
000032H CSL1 CSL0 MOD2 MOD1 MOD0 OUTE OUTL RELD INTE
00003AH R/W R/W R/W R/W R/W R/W R/W R/W R/W
000042H
00004AH
2
1
0
Initial value
UF CNTE TRG
R/W R/W R/W
-000H
[bit11, bit10] CSL1, CSL0 (Count clock SeLect)
These are count clock select bits.
Table 7.3-1 lists the clock sources that can be selected.
Table 7.3-1 Clock Sources and CSL Bits
CSL1
CSL0
Clock source (φ: machine clock)
0
0
φ/21
0
1
φ/23
1
0
φ/25
1
1
Setting prohibited
[bit9, bit8, bit7] MOD2, MOD1, MOD0 (MODe)
These bits set the operation mode.
All bits must be set to 0.
[bit6] OUTE (OUTput Enable)
This is an output enable bit. When this bit is set to 0, the TO pin becomes a general-purpose
port and when it is set to 1, the TO pin becomes a timer output pin.
The output waveform becomes toggled output at the reload mode and rectangular wave
output that indicates the counting operation at the one-shot mode.
[bit5] OUTL
This bit sets the output level of the TO pin. The output level reverses in case of setting the bit
to 0 or 1.
193
CHAPTER 7 16-BIT RELOAD TIMERS
[bit4] RELD
This is a reload enable bit. When this bit is set to 1, the reload mode is entered, and if the
counter value underflows from 0000H to FFFFH, the counter loads the reload register value
and continues operating.
When this bit is set to 0, if the counter value underflows from 0000H to FFFFH, the timer
stops counting.
Table 7.3-2 How to Setting OUTE, OUTL and RELD
OUTE
OUTL
RELD
OUTPUT WAVEFORM
0
X
X
General-purpose port
1
0
0
Rectangular wave with "H" level in counting
1
1
0
Rectangular wave with "L" level in counting
1
0
1
Toggled output with "L" level at count start
1
1
1
Toggled output with "H" level at count start
Note: "X" in the table means any value.
[bit3] INTE
This is an interrupt request enable bit. When this bit is set to 1, if the UF bit is set to 1, an
interrupt request is generated. If the UF bit is 0, an interrupt request is not generated.
[bit2] UF
This is a timer interrupt request flag. When the counter value underflows (0000H --> FFFFH),
this bit is set to 1. When this bit is set to 0, the interrupt request flag is cleared.
Setting this bit to 1 has no effect.
When this bit is read by read-modify-write instructions, 1 is returned.
[bit1] CNTE
This is a timer-count-enable bit. When this bit is set to 1, the activation trigger waiting state is
entered. When this bit is set to 0, the timer stops counting.
[bit0] TRG
This is a software trigger bit. When this bit is set to 1, a software trigger is activated, the
value in the reload register is loaded into the counter, and the timer starts counting.
Setting this bit to 0 has no effect. When this bit is read, 0 is always returned.
A trigger input to this register is valid only when CNTE = 1.
When CNTE = 0, no operation is performed.
194
CHAPTER 7 16-BIT RELOAD TIMERS
7.3.2
16-bit Timer Register (TMR0 to TMR3) and 16-bit Reload
Register (TMRLR0 to TMRLR3)
The 16-bit timer register (TMR0 to TMR3) reads the count value from the 16-bit timer.
The initial value of this register is undefined.
The 16-bit reload register (TMRLR0 to TMRLR3) retains the initial count value. The
initial value of this register is undefined.
■ 16-bit Timer Register (TMR0 to TMR3)
The register configuration of the 16-bit timer register (TMR) is shown below.
00002EH
000036H
00003EH
000046H
Initial value
0
~ ~
~ ~
TMR
Address: 15
R
X
R
X
R
X
R
X
...
...
R
X
R
X
R
X
R
X
R
X
Note:
Always use a 16-bit data transfer instruction to read data from this register.
■ 16-bit Reload Register (TMRLR0 to TMRLR3)
The register configuration of the 16-bit reload register (TMRLR) is shown below.
00002CH
000034H
00003CH
000044H
Initial value
0
~ ~
~ ~
TMRLR
Address: 15
W
X
W
X
W
X
W
X
...
...
W
X
W
X
W
X
W
X
W
X
Note:
Always use a 16-bit data transfer instruction to write data to this register.
195
CHAPTER 7 16-BIT RELOAD TIMERS
7.4
Internal Clock Operation
When the timer is driven by a divided-by internal clock, the clock source can be
selected from 1/2, 1/8, and 1/32 of the machine clock.
■ Internal Clock Operation
To start counting immediately after counting is enabled, set the CNTE and TRG bits of the
control status register to 1. A trigger input to the TRG bit is always valid when the timer is in
active state (CNTE = 1) regardless of the operation mode.
Figure 7.4-1 shows the activation and operation of the counter.
A time T (T: Peripheral clock machine cycle) elapses from when a trigger for starting the counter
is inputted to when the data of the reload register is loaded into the counter
Figure 7.4-1 Activation and Operations of a Counter
Counter clock
Counter
Reloaded data
Data load
CNTE (register)
TRG (register)
T
196
-1
-1
-1
CHAPTER 7 16-BIT RELOAD TIMERS
7.5
Underflow Operation
A transition of a counter value from 0000H to FFFFH is called "underflow." An
underflow occurs when the [set value in the reload register + 1] count is reached.
■ Underflow Operation
When an underflow occurs, and the RELD bit in the control register is 1, the counter loads the
value in the reload register and continues counting. If the RELD bit is 0, the counter stops at
FFFFH.
The UF bit of the control register is set by an underflow, and if the INTE bit is 1, an interrupt
request is generated.
Figure 7.5-1 shows underflow operation.
Figure 7.5-1 Underflow Operation
Counter clock
Counter
0000H
Reloaded data
-1
-1
-1
Data load
Underflow set
[RELD=1]
Counter clock
Counter
0000H
FFFFH
Underflow set
[RELD=0]
197
CHAPTER 7 16-BIT RELOAD TIMERS
■ Function of Output Pin
The TO0 to TO3 output pin operates as toggled output reversed by underflowing at the reload
mode, and as pulse output meaning the counting operation at the one-shot mode. The output
polarity can be set by the OUTL bit of the register. When the OUTL bit is set to "0", the TO0 to
TO3 output pin outputs initial value 0 as toggled output and value 1 as the one-shot pulse output
during counting operation. When the OUTL bit is set to "1", the output waveform is reversed.
Figure 7.5-2 and Figure 7.5-3 show the function of output pin.
Figure 7.5-2 Function(1) of Output Pin in 16-bit Reload Timer
Count start
Underflow
TO0 to TO3
Inverse at OUTL=1
General-purpose port
CNTE
Start up
trigger
[RELD=1, OUTL=0]
Figure 7.5-3 Function(2) of Output Pin in 16-bit Reload Timer
Count start
Underflow
TO0 to TO3
Inverse at OUTL=1
General-purpose port
CNTE
Start up
trigger
[RELD=0, OUTL=0]
198
Waiting state for
start up trigger
CHAPTER 7 16-BIT RELOAD TIMERS
7.6
Counter Operation States
The state of the counter depends on the CNTE bit of the control register and the WAIT
signal generated internally. The states that can be set are the stop state (STOP state)
for CNTE = 0 and WAIT = 1, the start trigger waiting state (WAIT state) for CNTE = 1
and WAIT = 1, and the operational state (RUN state) for CNTE = 1 and WAIT = 0.
■ Counter Operation States
Figure 7.6-1 shows the transitions between these states.
Figure 7.6-1 Counter State Transition
State transition through hardware
Reset
State transition through register access
STOP
CNTE=0, WAIT=1
Counter retains value stored
when it stops.
Counter value after reset is
undefined.
CNTE="1"
TRG="1"
CNTE="1"
TRG="0"
WAIT
CNTE=1,WAIT=1
Counter retains value stored
when it stops.
Counter value is undefined until
loaded after reset.
RUN
CNTE=1,WAIT=0
Counter is operating.
RELD UF
TRG="1"
TRG="1"
RELD UF
LOAD
CNTE=1,WAIT=0
Value in reload register is loaded
into counter
Load completed
199
CHAPTER 7 16-BIT RELOAD TIMERS
200
CHAPTER 8 PPG TIMERS
CHAPTER 8
PPG TIMERS
This chapter describes the overview of the PPG timer, register configurations and
functions, and PPG timer operation. The chapter also provides a block diagram of the
PPG timer.
8.1 Overview of PPG Timers
8.2 Block Diagram of PPG Timers
8.3 Registers of PPG Timers
8.4 PWM Operation
8.5 One-shot Operation
8.6 PWM Timer Interrupt Source and Timing Chart
8.7 Activating Multiple Channels by Using the General Control Register (GCN)
201
CHAPTER 8 PPG TIMERS
8.1
Overview of PPG Timers
The PPG timer can generate PWM waveforms with great precision and efficiency.
The MB91151A has six built-in channels for the PPG timers.
Each channel consists of the following elements:
• 16-bit down counter
• 16-bit data register with cycle setting buffer
• 16-bit compare register with duty setting buffer
• Pin controller
■ Features of PPG Timers
•
•
Internal clock: φ
•
Internal clock: φ/4
•
Internal clock: φ/16
•
Internal clock: φ/64
•
The counter value can be initialized to FFFFH by using reset and counter borrows.
•
Each channel has a PWM output.
•
Register
•
•
•
202
One of the following can be selected for the 16-bit down counter clock:
•
Cycle set register: reload data register with buffer
•
Duty set register: compare register with buffer
•
Transfer from buffers is performed by using counter borrows.
Pin control overview
•
When a duty ratio match occurs, the counter value is set to 1. (Preferred)
•
When a counter borrow occurs, the counter value is reset to 0.
•
By using output value fix mode, all-low (or all-high) can be outputted easily.
•
In addition, the polarity can be specified.
An interrupt request can be generated by the following sources. Interrupt requests can be
used to start DMA transfer.
•
Start of PPG timer
•
Counter borrow (cycle match)
•
Duty cycle match
•
Counter borrow (cycle match) or duty ratio match
Software or other interval timers can be used to specify that multiple channels are activated
at the same time. In addition, restart during operation can be specified.
CHAPTER 8 PPG TIMERS
8.2
Block Diagram of PPG Timers
Figure 8.2-1 shows the block diagram of an entire PPG timer. Figure 8.2-2 shows the
block diagram of one channel of the PPG timer.
■ Block Diagram of the Entire PPG Timer
Figure 8.2-1 Block Diagram of the Entire PPG Timer
TRG input
PWM timer ch0
PWM0
TRG input
PWM timer ch1
PWM1
TRG input
PWM timer ch2
PWM2
TRG input
PWM timer ch3
PWM3
External TRG4
TRG input
PWM timer ch4
PWM4
External TRG5
TRG input
PWM timer ch5
PWM5
16-bit reload timer ch0
16-bit reload timer ch1
General control
register 2
External TRG0 to
TRG3
4
General control
register 1
(Source selection)
4
203
CHAPTER 8 PPG TIMERS
■ Block Diagram of One Channel of the PPG Timer
Figure 8.2-2 Block Diagram of One Channel of the PPG Timer
PCSR
PDUT
Prescaler
1/1
1/4
Clock
Load
CMP
1/16
1/64
16-bit down counter
Start
Borrow
PPG mask
Peripheral clock
S
Q
PWM output
R
Reverse bit
Enable
TRG input
Edge detection
Software trigger
204
Interrupt
selection
IRQ
CHAPTER 8 PPG TIMERS
8.3
Registers of PPG Timers
Figure 8.3-1 lists the registers of the PPG timers.
■ Register List of PPG Timers
Figure 8.3-1 Register List of PPG Timers
Address
15
0
00000094H
GCN1
00000097H
GCN2
R/W
General control register 1
R/W
General control register 2
00000098H
PTMR0
R
PWM timer register (ch0)
0000009AH
PCSR0
W
PWM cycle set register (ch0)
0000009CH
PDUT0
W
PWM duty set register (ch0)
R/W
Control status register (ch0)
0000009EH
PCNH0
PCNL0
000000A0H
PTMR1
R
PWM timer register (ch1)
000000A2H
PCSR1
W
PWM cycle set register (ch1)
000000A4H
PDUT1
W
PWM duty set register (ch1)
R/W
Control status register (ch1)
000000A6H
PCNH1
PCNL1
000000A8H
PTMR2
R
PWM timer register (ch2)
000000AAH
PCSR2
W
PWM cycle set register (ch2)
000000ACH
PDUT2
W
PWM duty set register (ch2)
R/W
Control status register (ch2)
000000AEH
PCNH2
PCNL2
(Continued)
205
CHAPTER 8 PPG TIMERS
(Continued)
Address
0
PTMR3
R
PWM timer register (ch3)
000000B2H
PCSR3
W
PWM cycle set register (ch3)
000000B4H
PDUT3
W
PWM duty set register (ch3)
R/W
Control status register (ch3)
000000B6H
PCNH3
PCNL3
000000B8H
PTMR4
R
PWM timer register (ch4)
000000BAH
PCSR4
W
PWM cycle set register (ch4)
000000BCH
PDUT4
W
PWM duty set register (ch4)
R/W
Control status register (ch4)
000000BEH
PCNH4
PCNL4
000000C0H
PTMR5
R
PWM timer register (ch5)
000000C2H
PCSR5
W
PWM cycle set register (ch5)
000000C4H
PDUT5
W
PWM duty set register (ch5)
R/W
Control status register (ch5)
000000C6H
206
15
000000B0H
PCNH5
PCNL5
CHAPTER 8 PPG TIMERS
8.3.1
Control status registers (PCNH0 to PCNH5, PCNL0 to
PCNH5)
The control status register (PCNH0 to PCNH5, PCNL0 to PCNH5) controls the PWM
timer and indicates the status of the timer. Note that some bits cannot be rewritten
while the PWM timer is operating.
■ Control Status Registers (PCNH0 to PCNH5, PCNL0 to PCNH5)
The register configuration of the control status registers (PCNH0 to PCNH5, PCNL0 to PCNH5)
is shown below.
PCNH
bit
15
14
13
12
11
Address: ch0 00009EH CNTE STGR MDSE RTRG CKS1
ch1 0000A6H R/W
R/W
R/W
R/W
R/W
ch2 0000AEH
0
0
0
0
0
ch3 0000B6H
ch4 0000BEH
ch5 0000C6H
10
9
CKS0 PGMS
R/W
R/W
0
0
8
-
←Attribute
←Initial value
←Rewriting during
operation
PCNL
bit
7
Address: ch0 00009FH EGS1
ch1 0000A7H R/W
ch2 0000AFH
0
ch3 0000B7H
ch4 0000BFH
ch5 0000C7H
6
5
4
3
2
EGS0
R/W
0
IREN
R/W
0
IRQF
R/W
0
IRS1
R/W
0
IRS0
R/W
0
1
0
POEN OSEL
R/W
R/W ←Attribute
0
0
←Initial value
←Rewriting during
operation
[bit15] CNTE: Timer enable bit
This bit enables operation of the 16-bit down counter.
0
Stopped (initial value)
1
Enabled
[bit14] STGR: Software trigger bit
When this bit is set to 1, a software trigger is activated. Whenever this bit is read, a value of
0 is returned.
[bit13] MDSE: Mode selection bit
This bit determines whether the PWM operation in which pulses are generated continuously
or the one-shot operation in which only single pulses are generated is used.
0
PWM operation (initial value)
1
One-shot operation
207
CHAPTER 8 PPG TIMERS
[bit12] RTRG: Restart enable bit
This bit determines whether restart through a software trigger or trigger input is allowed.
0
Restart disabled (initial value)
1
Restart enabled
[bit11, bit10] CKS1, CKS0: Counter clock selection bit
These bits select the counter clock of the 16-bit down counter.
CKS1
CKS0
Cycle
0
0
φ (initial value)
0
1
φ/4
1
0
φ/16
1
1
φ/64
φ: Peripheral machine clock
[bit9] PGMS: PWM output mask selection bit
When this bit is set to 1, the PWM output can be masked to 0 or 1 regardless of the mode
setting, cycle setting, or duty ratio setting.
PWM output when PGMS is set to 1
Polarity
PWM output
Normal polarity
"L" output
Reverse polarity
"H" output
For output of all-high for normal polarity (or all-low for reverse polarity), write the same value to
the cycle set register and the duty set register to obtain the reverse output of these mask
values.
[bit8] Unused bit
[bit7, bit6] EGS1, EGS0: Trigger input edge selection bit
These bits select the valid edge for the activation source selected by the general control
register 1.
When the software trigger bit is set to 1, a software trigger is enabled regardless of the mode
selected.
208
EGS1
EGS0
Edge selection
0
0
Disabled (initial value)
0
1
Rising edge
1
0
Falling edge
1
1
Both edges
CHAPTER 8 PPG TIMERS
[bit5] IREN: Interrupt request enable bit
This bit specifies whether to enable interrupt requests.
0
Disabled (initial value)
1
Enabled
[bit4] IRQF: Interrupt request flag
When bit5 (IREN) is set to "Enabled," and the interrupt source specified by bit3 and bit2
(IRS1 and IRS0) occurs, this bit is set and an interrupt request is issued to the CPU. In
addition, when activation of DMA transfer is specified, DMA transfer is started.
This bit is cleared when a value of 0 is written or the clear signal is received from the DMAC.
The value of this bit does not change even if there is an attempt to set it to 1 via a write
operation.
When this bit is read by read-modify-write instructions, 1 is returned regardless of the bit
value.
[bit3, bit2] IRS1, IRS0: Interrupt source selection bit
These bits select the interrupt source that sets bit4 (IRQF).
IRS1
IRS0
Interrupt source
0
0
Software trigger or trigger input (initial value)
0
1
Counter borrow (cycle match)
1
0
Duty match
1
1
Counter borrow (cycle match) or duty match
[bit1] POEN: PWM output enable bit
When this bit is set to 1, the PWM output is generated from the pin.
0
General-purpose port (initial value)
1
PWM output pin
209
CHAPTER 8 PPG TIMERS
[bit0] OSEL: PWM output polarity specification bit
This bit specifies the polarity of the PWM output
This bit and bit9 are combined to select the type of PWM output
210
PMGS
OSEL
PWM output
0
0
Normal polarity (initial value)
0
1
Reverse polarity
1
0
Fixed to "L" level
1
1
Fixed to "H" level
Polarity
After reset
Normal polarity
"L" output
Reverse polarity
"H" output
Duty match
Counter borrow
CHAPTER 8 PPG TIMERS
8.3.2
PWM cycle set register (PCSR0 to PCSR5)
The PCSR is a register for setting cycles. It has a buffer. Transfers from the buffer are
performed through counter borrows.
■ PWM Cycle Set Register (PCSR0 to PCSR5)
The register configuration of the PCSR0 to PCSR5 is shown below.
PCSR
bit
Address: ch0 00009AH
ch1 0000A2H
ch2 0000AAH
ch3 0000B2H
ch4 0000BAH
ch5 0000C2H
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
This register is write-only.
Initial value is undefined.
Notes:
• After initializing or rewriting the PCSR, write to the duty set register after writing to the cycle set
register.
• This register must be accessed in 16-bit mode.
211
CHAPTER 8 PPG TIMERS
8.3.3
PWM duty set register (PDUT0 to PDUT5)
The PDUT is a register for setting duties. It has a buffer. Transfers from the buffer are
performed through counter borrows.
■ PWM Duty Set Register (PDUT0 to PDUT5)
The register configuration of the PDUT0 to PDUT5 is shown below.
PDUT
bit
Address: ch0 00009CH
ch1 0000A4H
ch2 0000ACH
ch3 0000B4H
ch4 0000BCH
ch5 0000C4H
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
This register is write-only.
Initial value is undefined.
If the same value is written to the PCSR and PDUT, all-high is outputted for normal polarity and
all-low is outputted for reverse polarity.
Notes:
• Do not set values so that the condition PCSR < PDUT would be met. Otherwise, the PWM
output becomes undefined.
• This register must be accessed in 16-bit mode.
212
CHAPTER 8 PPG TIMERS
8.3.4
PWM timer register (PTMR0 to PTMR5)
The PTMR0 to PTMR5 can be used to read the 16-bit down counter.
■ PWM Timer Register (PTMR0 to PTMR5)
The register configuration of the PTMR (PTMR0 to PTMR5) is shown below.
PTMR
bit
Address: ch0 000098H
ch1 0000A0H
ch2 0000A8H
ch3 0000B0H
ch4 0000B8H
ch5 0000C0H
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
This register is read-only.
Initial value is 11111111 11111111B.
Note:
This register must be accessed in 16-bit mode.
213
CHAPTER 8 PPG TIMERS
8.3.5
General control register 1 (GCN1)
The GCN1 selects the source of the PWM timer trigger input. Only channels 0-3 can be
selected by this register. Channels 4-5 are dedicated to external trigger pins.
■ General Control Register 1 (GCN1)
The register configuration of the GCN1 is shown below.
GCN1
bit
Address: 000094H
bit
15
14
13
12
TSEL 33 to TSEL 30
R/W
R/W
R/W
R/W
0
0
1
1
7
6
5
4
TSEL 13 to TSEL 10
R/W
R/W
R/W
R/W
0
0
0
1
11
10
9
8
TSEL 23 to TSEL 20
R/W
R/W
R/W
R/W
0
0
1
0
3
2
1
←Attribute
←Initial value
0
TSEL 03 to TSEL 00
R/W
R/W
R/W
R/W
0
0
0
0
←Attribute
←Initial value
[bit15 to bit12] TSEL33 to TSEL30: ch3 trigger input selection bit
TSEL33 to TSEL30
214
ch3 trigger input
0
0
0
0
EN0 bit of GCN2
0
0
0
1
EN1 bit of GCN2
0
0
1
0
EN2 bit of GCN2
0
0
1
1
EN3 bit of GCN2 (initial value)
0
1
0
0
16-bit reload timer ch0
0
1
0
1
16-bit reload timer ch1
0
1
1
X
Setting prohibited
1
0
0
0
External TRG0
1
0
0
1
External TRG1
1
0
1
0
External TRG2
1
0
1
1
External TRG3
1
1
X
X
Setting prohibited
CHAPTER 8 PPG TIMERS
[bit11 to bit8] TSEL23 to TSEL20: ch2 trigger input selection bit
TSEL23 to TSEL20
ch2 trigger input
0
0
0
0
EN0 bit of GCN2
0
0
0
1
EN1 bit of GCN2
0
0
1
0
EN2 bit of GCN2 (initial value)
0
0
1
1
EN3 bit of GCN2
0
1
0
0
16-bit reload timer ch0
0
1
0
1
16-bit reload timer ch1
0
1
1
X
Setting prohibited
1
0
0
0
External TRG0
1
0
0
1
External TRG1
1
0
1
0
External TRG2
1
0
1
1
External TRG3
1
1
X
X
Setting prohibited
[bit7 to bit4] TSEL13 to TSEL10: ch1 trigger input selection bit
TSEL13 to TSEL10
ch1 trigger input
0
0
0
0
EN0 bit of GCN2
0
0
0
1
EN1 bit of GCN2 (initial value)
0
0
1
0
EN2 bit of GCN2
0
0
1
1
EN3 bit of GCN2
0
1
0
0
16-bit reload timer ch0
0
1
0
1
16-bit reload timer ch1
0
1
1
X
Setting prohibited
1
0
0
0
External TRG0
1
0
0
1
External TRG1
1
0
1
0
External TRG2
1
0
1
1
External TRG3
1
1
X
X
Setting prohibited
215
CHAPTER 8 PPG TIMERS
[bit3 to bit0] TSEL03 to TSEL00: ch0 trigger input selection bit
TSEL03 to TSEL00
216
ch0 trigger input
0
0
0
0
EN0 bit of GCN2 (initial value)
0
0
0
1
EN1 bit of GCN2
0
0
1
0
EN2 bit of GCN2
0
0
1
1
EN3 bit of GCN2
0
1
0
0
16-bit reload timer ch0
0
1
0
1
16-bit reload timer ch1
0
1
1
X
Setting prohibited
1
0
0
0
External TRG0
1
0
0
1
External TRG1
1
0
1
0
External TRG2
1
0
1
1
External TRG3
1
1
X
X
Setting prohibited
CHAPTER 8 PPG TIMERS
8.3.6
General control register 2 (GCN2)
The GCN2 activates a start trigger through software.
■ General Control Register 2 (GCN2)
The register configuration of the GCN2 is shown below.
GCN2
bit
Address: 000097H
7
6
5
4
3
2
1
−
R/W
0
−
R/W
0
−
R/W
0
−
R/W
0
EN3
R/W
0
EN2
R/W
0
EN1
R/W
0
0
EN0
R/W ←Attribute
0
←Initial value
When one of the EN-bits of this register is selected by the GCN1, the register value is passed to
the trigger input of the PWM timer.
The PWM timers of multiple channels can be activated at the same time by generating the edge
selected by the EGS1 and EGS0 bits of the control status register via software.
Note:
Bit7 to bit4 of this register must be set to 0.
217
CHAPTER 8 PPG TIMERS
8.4
PWM Operation
The PWM operation allows continuous pulses to be outputted after a start trigger is
detected. The cycle and duty ratio of the output pulses can be controlled by changing
the values of the PCSR and PDUT, respectively.
■ PWM Operation
❍ When restart is inhibited
Figure 8.4-1 shows a timing chart of the PWM operation when trigger restart is inhibited.
Figure 8.4-1 Timing Chart of PWM Operation (Trigger Restart Prohibited)
Rising edge detected
Trigger ignored
Start
trigger
m
n
o
PWM
A
B
A=T (n+1) µs
B=T (m+1) µs
218
T: Count clock cycle
m: PCSR value
n: PDUT value
CHAPTER 8 PPG TIMERS
❍ When restart is enabled
Figure 8.4-2 shows the timing chart of the PWM operation when trigger restart is enabled.
Figure 8.4-2 Timing Chart of PWM Operation (Trigger Restart Enabled)
Rising edge detected
Restarted by trigger
Start
trigger
m
n
o
PWM
A
B
A=T (n+1) µs
B=T (m+1) µs
T: Count clock cycle
m: PCSR value
n: PDUT value
Note:
After data is written to PCSR, be sure to write to PDUT.
219
CHAPTER 8 PPG TIMERS
8.5
One-shot Operation
The one-shot operation allows output of a single pulse of any width through a trigger.
If restart is enabled, the counter value is reloaded when the edge is detected during
operation.
■ One-shot Operation
❍ When restart is inhibited
Figure 8.5-1 shows the timing chart of a one-shot operation when a trigger restart is inhibited.
Figure 8.5-1 Timing Chart of a One-shot Operation (Trigger Restart Prohibited)
Rising edge detected
Trigger ignored
Start
trigger
m
n
o
PWM
A
B
A=T (n+1) µs
B=T (m+1) µs
220
T: Count clock cycle
m: PCSR value
n: PDUT value
CHAPTER 8 PPG TIMERS
❍ When restart is enabled
Figure 8.5-2 shows the timing chart of a one-shot operation when a trigger restart is enabled.
Figure 8.5-2 Timing Chart of One-shot Operation (Trigger Restart Enabled)
Rising edge detected
Restarted by trigger
Start
trigger
m
n
o
PWM
A
B
A=T (n+1) µs
B=T (m+1) µs
T: Count clock cycle
m: PCSR value
n: PDUT value
221
CHAPTER 8 PPG TIMERS
8.6
PWM Timer Interrupt Source and Timing Chart
This section describes interrupt sources and provides the related timing charts.
■ PWM Timer Interrupt Sources and Timing Chart (PWM Output: Normal Polarity)
Figure 8.6-1 shows the PWM timer interrupt sources and a timing chart.
Note:
A maximum time of 2.5 T (T: counter clock cycle) is required from when a start trigger is activated
to when the counter value is loaded.
Figure 8.6-1 PWM Timer Interrupt Sources and Timing Chart (PWM Output: Normal Polarity)
Start trigger
Maximum of 2.5 T
Load
Clock
Count value
X
0003
0002
0001
0000
0003
PWM
Clock
Valid edge
Duty match
Counter borrow
■ Examples for Setting PWM Output to All-low or All-high
❍ Example of setting PWM output to all-low level
Figure 8.6-2 shows how to set the PWM output to all-low.
Figure 8.6-2 Example of Setting PWM Output to all-low
PWM
Decrease the
duty ratio in
stages.
222
Set the PGMS (mask bit) to 1 by issuing a borrow interrupt.
Setting the PGMS (mask bit) to 0 with borrow interrupt allows
to output a PWM waveform without whisker.
CHAPTER 8 PPG TIMERS
❍ Example of setting PWM output to all-high level
Figure 8.6-3 shows an example of setting PWM output to all-high level.
Figure 8.6-3 Example of Setting PWM Output to All-high
PWM
Increase duty
ratio in stages.
Write the same value as that set in cycle set register to
the duty set register by compare match interrupt.
223
CHAPTER 8 PPG TIMERS
8.7
Activating Multiple Channels by Using the General Control
Register (GCN)
You can activate multiple channels at the same time by selecting the start trigger with
the GCN1 register.
This section shows an example of how GCN2 register is set to activate channels via
software.
■ Activating Multiple Channels with the GCN
[Setting procedure]
1) Set the cycle in the PCSR.
2) Set the duty ratio in the PDUT.
Note that the setting must follow the order of PCSR followed by PDUT.
3) Specify the trigger input source for the channel to be activated by GCN1.
In this case, the initial setting is kept because GCN2 is used.
(ch0 --> EN0, ch1 --> EN1, ch2 --> EN2, ch3 --> EN3)
4) Set the control status register for the channel to be activated.
- CNTE: 1 --> Enables timer operation.
- STGR: 0 --> Since the channel is activated by GCN2, this bit is not set.
- MDSE: 0 --> Selects PWM operation.
- RTRG: 0 --> Inhibits restart.
- CSK1, CSK0:00 --> Sets the counter clock to Φ.
- PGMS: 0 --> Does not mask PWM output. - (bit 8:0 --> Any value can be set because
these bits are unused.)
- EGS1, EGS0:01 --> Activates channel at a rising edge
- IREN: 1 --> Enables interrupt request.
- IRQF: 0 --> Clears interrupt source.
- IRS1, IRS0:01 --> Issues interrupt request when counter borrow occurs.
- POEN: 1 --> Enables PWM output.
- OSEL: 0 --> Sets normal polarity.
5) Activate a start trigger by writing data to GCN2.
To activate ch0 and ch1 at the same time with the above settings, set the EN0 and EN1 bits of
GCN2 to 1. A rising edge is generated and pulses are outputted from PWM0 and PWM1.
224
CHAPTER 8 PPG TIMERS
■ When the 16-bit Reload Timer is Used for activation
Specify the 16-bit reload timer as a source in GCN1 register (see 3) above). Start the 16-bit
reload timer instead of writing data to GCN2 as in 5) above.
In addition, set the control status register as follows:
•
RTRG: 1 --> Enables restart.
•
EGS1, EGS0:11 --> Enables activation by both edges
By setting 16-bit reload timer output to toggle mode, the PPG timer can be restarted at fixed
intervals.
225
CHAPTER 8 PPG TIMERS
226
CHAPTER 9 MULTIFUNCTIONAL TIMERS
CHAPTER 9
MULTIFUNCTIONAL TIMERS
This chapter gives an overview of the multifunctional timer, its block diagram, the
configuration and functions of its registers, and its operation.
9.1 Overview of Multifunctional Timers
9.2 Block Diagram of the Multifunctional Timer
9.3 Registers of Multifunctional Timers
9.4 Operations of Multifunctional Timer
227
CHAPTER 9 MULTIFUNCTIONAL TIMERS
9.1
Overview of Multifunctional Timers
The multifunctional timer consists of the following elements:
• 16-bit free-run timer,
• Eight 16-bit output compares,
• Four 16-bit input captures,
• 16-bit PPG timer with 6 channels.
This function enables output of waveforms based on the 16-bit free-run timer, as well
as measuring the width of input pulses and the external clock cycle.
■ Configuration of the Multifunctional Timers
❍ 16-bit free-run timer (x1)
The 16-bit free-run timer consists of a 16-bit up counter, control register, 16-bit compare clear
register, and prescaler. The output values of this counter are used as a base timer for output
compare and input capture operations.
•
The user can select a counter operating clock of eight clocks.
Eight internal clocks (φ,φ/2, φ/4, φ/8, φ/16, φ/32, φ/64, and φ/128)
φ: Machine clock
•
An interrupt can be generated as result of an overflow or compare match with the compare
clear register. (For the compare match, a mode must be set.)
•
The counter value can be initialized to 0000H by reset, software clear, and a compare match
with the compare clear register.
❍ Output compare (x8)
An output compare consists of eight 16-bit compare registers, a latch for compare output, and a
control register. When a 16-bit free-run timer value matches a compare register value and the
output level is reversed, interrupts can be generated at the same time.
•
Eight compare registers can be operated independently. The output compare has an output
pin and interrupt flag for each of the compare registers.
•
Two compare registers can be paired to control output pins in the sense that two compare
registers are used to reverse the output levels.
•
The user can set initial values for the output pins.
•
An interrupt can be generated by a compare match.
❍ Input capture (x4)
An input capture consists of four independent external input pins, the corresponding capture
register, and a control register. When any edge of a signal input from an external input pin is
detected, a 16-bit free-run timer value can be stored in the capture register and an interrupt can
be generated at the same time.
•
228
The user can select the significant edges (rising edge, falling edge, and both edges) of
external input signals.
CHAPTER 9 MULTIFUNCTIONAL TIMERS
•
Four input captures can operate independently.
•
Interrupts can be generated by the significant edge of an external input signal.
❍ 16-bit PPG timer (x6)
See "CHAPTER 8 PPG TIMERS".
229
CHAPTER 9 MULTIFUNCTIONAL TIMERS
9.2
Block Diagram of the Multifunctional Timer
Figure 9.2-1 shows a block diagram of the multifunctional timer unit.
■ Block Diagram of Multifunctional Timer
Figure 9.2-1 Block Diagram of Multifunctional Timer
Interrupt
IVF
IVFE
STOP MODE SCLR
CLK2
CLK1
CLK0
Divider
Clock
R-bus
16-bit free-run timer
16-bit compare clear register
(Ch. 6 compare register)
Compare circuit
Interrupt
Compare register 0/2/4/6
CST0
Compare circuit
Compare register 1/3/5/7
T
Q
OC0/2/4/6
T
Q
OC1/3/5/7
CMOD
Select
Compare circuit
IOP1
IOP0
IOE1
IOE0
Interrupt
Interrupt
Detection
of an edge
Capture data register 0/2
EG11
EG10
EG01
Detection
of an edge
Capture data register 1/3
ICP0
ICP1
ICE0
IN 0/2
EG00
IN 1/3
ICE1
Interrupt
Interrupt
230
CHAPTER 9 MULTIFUNCTIONAL TIMERS
9.3
Registers of Multifunctional Timers
This section lists the registers of the multifunctional timer unit.
■ Registers of Multifunctional Timers
See "APPENDIX A I/O Map", for a list of registers for the multifunctional timer unit.
231
CHAPTER 9 MULTIFUNCTIONAL TIMERS
9.3.1
Registers of 16-bit Free-run Timer
The 16-bit free-run timer has the following three registers.
• Data register (TCDT)
• Compare clear register
• Timer control status register (TCCS)
■ Data Register (TCDT)
The register configuration of the data register (TCDT) is as follows:
Upper 8 bits of timer data register
bit15
00008CH
T15
read/write→ R/W
Initial value→
(0)
Lower 8 bits of timer data register
read/write→
Initial value→
bit14
bit13
bit12
bit11
bit10
bit9
bit8
T14
R/W
(0)
T13
R/W
(0)
T12
R/W
(0)
T11
R/W
(0)
T10
R/W
(0)
T09
R/W
(0)
T08
R/W
(0)
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
T07
R/W
(0)
T06
R/W
(0)
T05
R/W
(0)
T04
R/W
(0)
T03
R/W
(0)
T02
R/W
(0)
T01
R/W
(0)
T00
R/W
(0)
This register allows reading the counter value of the 16-bit free-run timer. The counter value is
cleared to 0000H at reset. To set a timer value, write it to this register in the stop status (STOP =
1). Access this register in units of words. The 16-bit free-run timer is initialized by following one
of the methods below.
•
Initialization by reset
•
Initialization by clearing the control status register (SCLR)
•
Initialization by matching a compare clear register (ch6 compare register) value with a timer
counter value (A mode must be set.)
■ Compare Clear Register
This register is a 16-bit compare register for comparison with the 16-bit free-run timer. The ch6
compare register of an output compare is used. When this register value matches the value of
the 16-bit free-run timer, the 16-bit free-run timer value is initialized to 0000H and a compare
clear interrupt flag is set. When interrupt operation is allowed, an interrupt request is issued to
the CPU.
232
CHAPTER 9 MULTIFUNCTIONAL TIMERS
■ Timer Control Status Register (TCCS)
The register configuration of the timer control status register (TCCS) is as follows:
Upper 8 bits of timer control register
00008EH
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
ECLK
−
−
−
−
−
−
−
R/W
(0)
−
(−)
−
(−)
−
(−)
−
(−)
−
(−)
−
(−)
−
(−)
bit5
bit4
bit3
read/write→
Initial value→
Lower 8 bits of timer control
read/write→
Initial value→
bit7
bit6
IVF
IVFE
R/W
(0)
R/W
(0)
STOP MODE SCLR
R/W
(0)
R/W
(0)
R/W
(0)
bit2
bit1
bit0
CLK2
CLK1
CLK0
R/W
(0)
R/W
(0)
R/W
(0)
[bit15] ECLK
This bit is always set to 0 by the write processing.
0
Internal clock source is selected (initial value).
1
Setting is prohibited.
[bit14 to bit8] Unused bits
[bit7] IVF
This bit is an interrupt request flag of the 16-bit free-run timer. When an overflow occurs in
the 16-bit free-run timer, this bit is set to 1. If an interrupt request permission bit (bit6: IVFE)
is set, an interrupt occurs. This bit is cleared by setting it to 0. Writing 1 has no effect. The
reading result of read modify write instructions is always 1.
0
No interrupt request (initial value)
1
Interrupt request
[bit6] IVFE
This bit is an interrupt permission bit for the 16-bit free-run timer. When this bit is 1 and the
interrupt flag (bit7: IVF) is set to 1, an interrupt occurs.
0
Prohibits an interrupt (initial value)
1
Allows an interrupt.
[bit5] STOP
This bit is used to stop the counter of the 16-bit free-run timer. When the bit is set to 1, the
counter of the timer is stopped. When the bit is set to 0, the counter of the timer is started.
0
Allows counting (operation) (initial value)
1
Prohibits counting (stop)
Note:
When the 16-bit free-run timer is stopped, output compare operation is stopped as well.
233
CHAPTER 9 MULTIFUNCTIONAL TIMERS
[bit4] MODE
This bit is used to set the initialization condition of the 16-bit free-run timer. When this bit is
set to 0, the counter value can be initialized by reset or with the clear bit (bit3: SCLR). When
the bit is set to 1, the counter value can be initialized by reset, with the clear bit (bit3: SCLR),
or by a match with the value of compare register 6 during an output compare operation.
0
Initialization by reset or the clear bit (initial value)
1
Initialization by reset, clear bit, or output comparison with compare register 6
Note:
The counter value is initialized when the counter value is changed.
[bit3] SCLR
This bit is used to initialize the value of the operating 16-bit free-run timer to 0000H. When
this bit is set to 1, the counter is initialized to 0000H. Setting this bit to 0 has no effect. The
returned value during the read operation is always 0. The counter value is initialized when
the counter value is changed.
SCLR
Meaning of flag
0
This value has no effect. (initial value)
1
The counter value is initialized to 0000H.
Note:
When initializing the counter value while the timer is stopped, set the data register to 0000H.
[bit2, bit1, bit0] CLK2, CLK1, and CLK0
These bits are used to select a counter clock for the 16-bit free-run timer. Immediately after
these bits are set to a new value, the clock is switched. Therefore, change these bits while
the output compare and input capture are stopped.
Counter
clock
φ=16MHz
φ=8MHz
φ=4MHz
φ=1MHz
CLK2
CLK1
CLK0
0
0
0
φ
62.5 ns
125 ns
0.25 µs
1 µs
0
0
1
φ/2
125 ns
0.25 µs
0.5 µs
2 µs
0
1
0
φ/4
0.25 µs
0.5 µs
1 µs
4 µs
0
1
1
φ/8
0.5 µs
1 µs
2 µs
8 µs
1
0
0
φ/16
1 µs
2 µs
4 µs
16 µs
1
0
1
φ/32
2 µs
4 µs
8 µs
32 µs
1
1
0
φ/64
4 µs
8 µs
16 µs
64 µs
1
1
1
φ/128
8 µs
16 µs
32 µs
128 µs
φ: Machine clock
234
CHAPTER 9 MULTIFUNCTIONAL TIMERS
9.3.2
Registers of the Output Compare
The output compare has the following two registers.
• Compare register (OCCP0 to OCCP7)
• Output control register (OCS0 to OCS7)
■ Compare Register (OCCP0 to OCCP7)
The register configuration of the compare registers (OCCP0 to OCCP7) is as follows:
bit15
000076H
000074H
00007AH
000078H
00007EH
00007CH
000082H
000080H
Upper 8 bits of
compare register
bit14
bit12
bit11
bit10
bit9
bit8
OP15
OP14
OP13
OP12
OP11
OP10
OP09
OP08
R/W
(X)
R/W
(X)
R/W
(X)
R/W
(X)
R/W
(X)
R/W
(X)
R/W
(X)
R/W
(X)
bit7
Lower 8 bits of
compare register
bit13
bit6
bit5
bit4
bit3
bit2
bit1
bit0
OP07
OP06
OP05
OP04
OP03
OP02
OP01
OP00
R/W
(X)
R/W
(X)
R/W
(X)
R/W
(X)
R/W
(X)
R/W
(X)
R/W
(X)
R/W
(X)
This register is a 16-bit compare register for comparison with the 16-bit free-run timer. Since
the initial value of this register is not fixed, allow activation only after a value has been set.
Access this register in word units. When this register value matches a value of the 16-bit freerun timer, a compare signal is issued and an output-compare interrupt flag is set. When output
permission is set, the output level corresponding to the compare register is reversed.
Note:
To rewriting the compare register, within the compare interrupt routine or compare operation is
disabled. Be sure not to occur simultaneously a compare match and writing the compare register.
■ Output Control Register (OCS0 to OCS7)
The register configuration of the output control registers (OCS0 to OCS7) is as follows:
bit15
000086H
000084H
00008AH
000088H
bit14
Upper 8 bits of
output control register
R/W
(X)
R/W
(X)
bit7
Lower 8 bits of
output control register
R/W
(X)
bit6
bit13
bit12
bit11
bit10
bit9
CMOD
OTE1
OTE0
OTD1
OTD0
R/W
(0)
R/W
(0)
R/W
(0)
R/W
(0)
R/W
(0)
bit5
IOP1
IOP0
IOE1
IOE0
R/W
(0)
R/W
(0)
R/W
(0)
R/W
(0)
bit4
R/W
(X)
bit3
R/W
(X)
bit2
bit1
CST1
CST0
R/W
(0)
R/W
(0)
bit8
bit0
This section explains ch0 and ch1. The explanation of ch0 also applies to ch2, ch4, and ch6,
while the explanation of ch1 applies also to ch3, ch5, and ch7.
235
CHAPTER 9 MULTIFUNCTIONAL TIMERS
[bit12] CMOD
If pin output is allowed (OTE1 = 0 or OTE0 = 1), the pin output level reverse operation mode
is switched when a compare match is detected.
•
When CMOD = 0 (initial value), the output level of the pin corresponding to a compare
register is reversed.
OC0: The level is reversed due to a match with compare register 0.
OC1: The level is reversed due to a match with compare register 1.
•
When CMOD = 1, the output level of compare register 0 is reversed in the same way as
when CMOD = 0. However, the output level of the pin (OC1) corresponding to compare
register 1 is reversed in case of a match with compare register 0 and a match of compare
register 1. When the value of compare register 0 is the same as that of compare register 1,
the operation is the same as when a single compare register was used.
OC0: The level is reversed due to a match with compare register 0.
OC1: The level is reversed due to matches with compare registers 0 and 1.
[bit11, bit10] OTE1 and OTE0
These bits are used to enable pin output of the output compare.
0
Operate as general-purpose ports (PF0 to PF7). (initial value)
1
Output compare pin output is allowed.
OTE1: Corresponds to output compare 1.
OTE0: Corresponds to output compare 0.
[bit9, bit8] OTD1 and OTD0
These bits are used to change the pin output level, if pin output of the compare register is
allowed. The initial value of the compare pin output is 0. To write a value, stop the compare
operation. During a read operation, the output compare pin output value can be read.
0
Set the compare pin output to 0. (initial value)
1
Set the compare pin output to 1.
OTD1: Corresponds to output compare 1.
OTD0: Corresponds to output compare 0.
[bit7, bit6] IOP1 and IOP0
These bits are used as interrupt flags of the output compare. When the value of the
compare register matches the value of the 16-bit free-run timer, the bits are set to 1. If these
bits are set to 1 when the interrupt request bits (IOE1 and IOE0) are enabled, an outputcompare interrupt occurs. These bits are cleared by setting them to 0. Writing 1 has no
effect. Reading these bits with read modify write instructions always returns 1.
0
No output compare match exists. (initial value)
1
An output compare match exists.
IOP1: Corresponds to output compare 1.
IOP0: Corresponds to output compare 0.
236
CHAPTER 9 MULTIFUNCTIONAL TIMERS
[bit5, bit4] IOE1 and IOE0
These bits are used to allow an interrupt of the output compare. An output-compare interrupt
occurs when these bits are set to 1 and the interrupt flags (IOP1 and IOP0) are also set to 1.
0
Prohibits output-compare interrupts. (initial value)
1
Allows an output-compare interrupt.
IOE1: Corresponds to output compare 1.
IOE0: Corresponds to output compare 0.
[bit3, bit2] Unused bits
[bit1, bit0] CST1 and CST0
These bits are used to allow a match operation with the 16-bit free-run timer. Before
allowing a compare operation, be sure to set a compare register value and an output data
register value.
0
Prohibits the compare operation. (initial value)
1
Allows compare operation.
CST1: Corresponds to output compare 1.
CST0: Corresponds to output compare 0.
Notes:
• The write processing of the compare register should be performed in the interrupt routine for the
comparison, or under the prohibition state of the compare operation so that both of the
comparison agreement and the write processing do not occur at the same time.
• The output compare is synchronized with the 16-bit free-run timer. Therefore, when the 16-bit
free-run timer is stopped, the output compare operation is stopped as well.
237
CHAPTER 9 MULTIFUNCTIONAL TIMERS
9.3.3
Registers of Input Capture
The input capture has the following two data registers:
• Input capture data register (IPCP0 to IPCP3)
• Input capture control register (ICS01, ICS23)
■ Input Capture Data Register (IPCP0 to IPCP3)
The register configuration of the input capture data registers (IPCP0 to IPCP3) is as follows:
bit15
00006AH
000068H
00006EH
00006CH
Upper 8 bits of input
capture data register
bit13
bit12
bit11
bit10
bit9
bit8
CP15
CP14
CP13
CP12
CP11
CP10
CP09
CP08
R
(X)
R
(X)
R
(X)
R
(X)
R
(X)
R
(X)
R
(X)
R
(X)
bit7
Lower 8 bits of input
capture data register
bit14
bit6
bit5
bit4
bit3
bit2
bit1
bit0
CP07
CP06
CP05
CP04
CP03
CP02
CP01
CP00
R
(X)
R
(X)
R
(X)
R
(X)
R
(X)
R
(X)
R
(X)
R
(X)
The input capture data registers (IPCP0 to IPCP3) are used to store the value of the 16-bit freerun timer when a significant edge of the corresponding external pin input waveform is detected.
(Access this register in word units. The user cannot write any value to this register.)
■ Input Capture Control Register (ICS01, ICS23)
The register configuration of the input capture control register (ICS01, ICS23) is as follows:
Upper 8 bits of capture control register
(ICS23)
read/write→
Initial value→
000073H
000071H
Upper 8 bits of capture control register
(ICS01)
read/write→
Initial value→
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
ICP3
ICP2
ICE3
ICE2
EG31
EG30
EG21
EG20
R/W
(0)
R/W
(0)
R/W
(0)
R/W
(0)
R/W
(0)
R/W
(0)
R/W
(0)
R/W
(0)
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
ICP1
ICP0
ICE1
ICE0
EG11
EG10
EG01
EG00
R/W
(0)
R/W
(0)
R/W
(0)
R/W
(0)
R/W
(0)
R/W
(0)
R/W
(0)
R/W
(0)
[bit7, bit6] ICP3, ICP2, ICP1, and ICP0
These bits are used as input-capture interrupt flags. When a significant edge of an external
input pin is detected, these bits are set to 1. When the interrupt permission bits (ICE3, ICE2,
ICE1, and ICE0) are also set, an interrupt is generated as soon as the significant edge is
detected. To clear these bits, set them to 0. Setting these bits to 1 has no effect. Read
operations with read modify write instructions always return 1 for these bits.
0
No significant edge is detected. (initial value)
1
A significant edge is detected.
ICPn: n corresponds to the channel number of the input capture.
238
CHAPTER 9 MULTIFUNCTIONAL TIMERS
[bit5, bit4] ICE3, ICE2, ICE1, and ICE0
These bits are used as input-capture interrupt permission bits. When these bits are set to 1
and the interrupt flags (ICP3, ICP2, ICP1, and ICP0) are also 1, an input-capture interrupt
occurs.
0
Prohibits interrupts. (initial value)
1
Allows an interrupt.
ICEn: n corresponds to the channel number of the input capture.
[bit3 to bit0] EG31, EG30, EG21, EG20, EG11, EG10, EG01, and EG00
These bits are used to select the significant edge polarity of the external input. They are
also used to enable input capture operations.
EG31. EG21,
EG01
EG30. EG20,
EG00
0
0
No edge is detected. (stop status) (initial value)
0
1
A rising edge is detected. ↑
1
0
A falling edge is detected. ↓
1
1
Both edges are detected. ↑ & ↓
Edge detection polarity
EGn1 and EGn0: n corresponds to the channel number of the input capture.
239
CHAPTER 9 MULTIFUNCTIONAL TIMERS
9.4
Operations of Multifunctional Timer
This section describes the operations of the multifunctional timer.
■ Explanation of Multifunctional Timer Operation
❍ 16-bit free-run timer
The 16-bit free-run timer starts counting from the counter value 0000H after releasing reset.
This counter value is the reference time for the 16-bit output compare and 16-bit input capture.
❍ 16-bit output compare
The 16-bit output compare compares the set compare register value with the 16-bit free-run
timer value. If these values match, an interrupt flag can be set and the output level can be
reversed.
❍ 16-bit input capture
The 16-bit input capture captures the 16-bit free-run timer value to the capture register to
generate an interrupt when the set significant edge is detected.
240
CHAPTER 9 MULTIFUNCTIONAL TIMERS
9.4.1
Operation of 16-bit Free-run Timer
The 16-bit free-run timer starts counting from the counter value 0000H after releasing
reset. The counter value becomes the reference time of the 16-bit output compare and
the 16-bit input capture.
■ Explanation of 16-bit Free-run Timer Operation
The counter value is cleared under the following conditions.
•
When an overflow occurs
•
When the value matches that of the compare clear register (compare register of output
compare ch6) (A mode must be set.)
•
When the SCLR bit in the TCCS register is set to 1 during operation
•
When 0000H is written to TCDT register while the timer is stopped
An interrupt occurs when an overflow occurs and the counter is cleared because the counter
value matches that of the compare clear register. (For a compare match interrupt, a mode must
be set.)
Figure 9.4-1 shows an example of the output waveform when an overflow occurs and the
counter is cleared. Figure 9.4-2 is an example of the output waveform when the counter value
matches that of the compare clear register, and the counter is cleared.
Figure 9.4-1 Clearing the Counter when an Overflow Occurs
Counter value
FFFFH
BFFFH
7FFFH
3FFFH
0000H
Time
Reset
Interrupt
241
CHAPTER 9 MULTIFUNCTIONAL TIMERS
Figure 9.4-2 Clearing the Counter when the Counter Value Matches That of the Compare Clear Register
Counter value
FFFFH
Match
BFFFH
Match
7FFFH
3FFFH
Time
0000H
Reset
Compare register
BFFFH
Interrupt
■ Timing to Clear the 16-bit Free-run Timer
The counter is cleared by reset, software, or when the counter value matches that of the
compare clear register. When clearing the counter by way of reset or software, it is cleared
immediately when a clear command is issued. However, when the counter is cleared because
of a match with the value in the compare clear register, clearing is performed in synchronization
with the count timing.
Figure 9.4-3 shows the clear timing of the free-run timer.
Figure 9.4-3 Clear Timing of the Free-run Timer
N
Compare clear register value
Compare match
N
Counter value
0000
■ Count Timing of the 16-bit Free-run Timer
The counter of the 16-bit free-run timer is incremented by the input clock (internal or external
clock). When an external clock is selected, the counter is incremented by a rising edge.
Figure 9.4-4 shows the count timing of the 16-bit free-run timer.
Figure 9.4-4 Count Timing of the 16-bit Free-run Timer
External clock input
Count clock
Counter value
242
N
N+1
CHAPTER 9 MULTIFUNCTIONAL TIMERS
9.4.2
Operation of 16-bit Output Compare
The 16-bit output compare compares the set compare register value with the value of
the 16-bit free-run timer. If the values match, the compare can set an interrupt flag and
reverse the output level.
■ Explanation of 16-bit Output Compare Operation
❍ CMOD = 0
A compare operation can be performed independently with a single channel. (When CMOD =
0)
Figure 9.4-5 shows an example of the output waveform when compare registers 0 and 1 are
used (at the beginning of output, a value of "0" is assumed).
Figure 9.4-5 Example of the Output Waveform when Compare Registers 0 and 1 are Used
(At the Beginning of Output, 0 is Assumed.)
Counter value
FFFFH
BFFFH
7FFFH
3FFFH
0000 H
Time
Reset
Compare register 0
BFFFH
Compare register 1
7FFFH
Output compare 0
Output compare 1
Compare 0 interrupt
Compare 1 interrupt
❍ 1 when CMOD=1
The output level can be changed by using two pairs of compare registers. (1 when CMOD = 1)
Figure 9.4-6 is an example of the output waveform when compare registers 0 and 1 are used (at
the beginning of output, a value of "0" is assumed).
243
CHAPTER 9 MULTIFUNCTIONAL TIMERS
Figure 9.4-6 Example of the Output Waveform when Compare Registers 0 and 1 are Used
(At the Beginning of Output, 0 is Assumed.)
Counter value
FFFFH
BFFFH
7FFFH
3FFFH
0000H
Time
Reset
Compare register 0
BFFFH
Compare register 1
7FFFH
Output compare 0
Output compare 1
Compare 0 interrupt
Compare 1 interrupt
244
CHAPTER 9 MULTIFUNCTIONAL TIMERS
■ Timing of 16-bit Output Compare
The output level can be changed by using two pairs of compare registers. (One when CMOD =
1)
The output compare can generate a compare match signal to reverse output and also generate
an interrupt when the value of the free-run timer matches that of the set compare register. The
timing of output reverse at a compare match is synchronized with the count timing of the
counter.
Figure 9.4-7 is a timing chart of the 16-bit output compare.
Figure 9.4-7 Timing Chart of 16-bit Output Compare
N
Counter value
Value of compare clear register
N+1
N
Compare match
Interrupt
Counter value
Value of compare clear register
N
N
N+1
N+1
N
Compare match
Pin output
Note:
The write processing of the compare register should be performed in the interrupt routine for the
comparison, or under the prohibition state of the compare operation so that both of the comparison
agreement and the write processing do not occur at the same time.
245
CHAPTER 9 MULTIFUNCTIONAL TIMERS
9.4.3
Operation of 16-bit Input Capture
When the set significant edge is detected, the 16-bit input capture can capture the 16bit free-run timer value to the capture register to generate an interrupt.
■ Operation of 16-bit Input Capture
Figure 9.4-8 shows an example of capture timing for the 16-bit input capture.
Figure 9.4-8 Example of Capture Timing for the 16-bit Input Capture
Counter value
FFFFh
BFFFh
7FFFh
3FFFh
Time
0000h
Reset
IN0
IN1
IN example
Data register 0
Not fixed
3FFFh
Data register 1
Data register example
BFFFh
Not fixed
Not fixed
BFFFh
7FFFh
Capture 0 interrupt
Capture 1 interrupt
Capture example interrupt
Capture 0 = rising edge
Capture 1 = falling edge
Capture example = both edges (example)
246
An interrupt occurs again
because of a significant edge.
Clearing an interrupt by use of software
CHAPTER 9 MULTIFUNCTIONAL TIMERS
■ Input Timing of 16-bit Input Capture
Figure 9.4-9 shows the input timing of the 16-bit input capture.
Figure 9.4-9 Input Timing of 16-bit Input Capture
Counter value
N
N+1
Input capture input
Significant edge
Capture signal
Capture register value
N+1
Interrupt
247
CHAPTER 9 MULTIFUNCTIONAL TIMERS
248
CHAPTER 10 EXTERNAL-INTERRUPT CONTROL BLOCK
CHAPTER 10
EXTERNAL-INTERRUPT CONTROL
BLOCK
This chapter gives an overview of the external-interrupt control block, the structure
and functions of the registers, and the operation of the external-interrupt control
block.
10.1 Overview of External Interrupt
10.2 External-Interrupt Registers
10.3 External-Interrupt Operation
10.4 External-Interrupt Request Level
249
CHAPTER 10 EXTERNAL-INTERRUPT CONTROL BLOCK
10.1 Overview of External Interrupt
The external-interrupt control block is a block that controls external-interrupt requests
received through INT0 to INT15.
You can select one of the following request levels to be detected: high, low, rising
edge, or falling edge.
■ Block Diagram of the External-Interrupt Control Block
Figure 10.1-1 shows a block diagram of the external-interrupt control block.
Figure 10.1-1 Block Diagram of the External-Interrupt Control Block
R -b u s
16
Interrupt
request
16
16
32
250
Enable interrupt register
Gate
Source F/F
Interrupt source register
Request level set register
Edge detection circuit
16
INT 0 t o
INT 15
CHAPTER 10 EXTERNAL-INTERRUPT CONTROL BLOCK
10.2 External-Interrupt Registers
Figure 10.2-1 lists the registers in the external-interrupt control block.
■ List of External-Interrupt Registers
Figure 10.2-1 List of External-Interrupt Registers
bit
bit
bit
bit
bit
bit
bit
bit
7
6
5
4
3
2
1
0
EN7
EN6
EN5
EN4
EN3
EN2
EN1
EN0
7
6
5
4
3
2
1
0
EN15
EN14
EN13
EN12
EN11
EN10
EN9
EN8
15
14
13
12
11
10
9
8
ER7
ER6
ER5
ER4
ER3
ER2
ER1
ER0
15
14
13
12
11
10
9
8
ER15
ER14
ER13
ER12
ER11
ER10
ER9
ER8
15
14
13
12
11
10
9
8
LB7
LA7
LB6
LA6
LB5
LA5
LB4
LA4
7
6
5
4
3
2
1
0
LB3
LA3
LB2
LA2
LB1
LA1
LB0
LA0
15
14
13
12
11
10
9
8
LB15
LA15
LB14
LA14
LB13
LA13
LB12
LA12
7
6
5
4
3
2
1
0
LB11
LA11
LB10
LA10
LB9
LA9
LB8
LA8
Enable interrupt register
(ENIR0)
Enable interrupt register
(ENIR1)
External-interrupt request
register (EIRR0)
External-interrupt request
register (EIRR1)
External interrupt request level
setting register (ELVR0)
External interrupt request level
setting register (ELVR1)
251
CHAPTER 10 EXTERNAL-INTERRUPT CONTROL BLOCK
10.2.1 Enable Interrupt Register (ENIR0, ENIR1)
The enable interrupt register (ENIR0, ENIR1) masks external-interrupt request output.
■ Enable Interrupt Register (ENIR0, ENIR1: ENable Interrupt Register)
The register configuration of the enable interrupt register (ENIR0, ENIR1) is shown below.
ENIR0
7
6
5
4
3
2
1
0
Address: 0000C9H
EN7
EN6
EN5
EN4
EN3
EN2
EN1
EN0
7
6
5
4
3
2
ENIR1
Address: 0000CBH
EN15 EN14 EN13 EN12 EN11 EN10
1
0
EN9
EN8
Initial value Access
00000000B
R/W
00000000B
R/W
The output of interrupt requests, corresponding to this register bit being set to 1, is enabled
(INT0 is enabled by EN0), and the request is outputted to the interrupt controller. The pins for
which the corresponding bit is set to 0 retain an interrupt source but do not issue an interrupt
request to the interrupt controller.
252
CHAPTER 10 EXTERNAL-INTERRUPT CONTROL BLOCK
10.2.2 External-Interrupt Request Register (EIRR0, EIRR1)
During a read operation, the external-interrupt request register (EIRR0, EIRR1)
indicates whether a corresponding external-interrupt request exists. A write operation
clears the value in the flip-flop indicating the request.
■ External-Interrupt Request Register (EIRR0, EIRR1: External-Interrupt Request Register n)
The register configuration of the external-interrupt request register (EIRR0, EIRR1) is shown
below.
EIRR0
15
14
13
12
11
10
9
8
Address: 0000C8H
ER7
ER6
ER5
ER4
ER3
ER2
ER1
ER0
15
14
13
12
11
10
9
EIRR1
Address: 0000CAH
ER15 ER14 ER13 ER12 ER11 ER10 ER9
Initial value Access
00000000B
R/W
00000000B
R/W
8
ER8
When a bit of this register is 1, the pin corresponding to the bit has received an externalinterrupt request. When a bit of this register is set to 0, the value in the flip-flop corresponding
to the bit, which indicates a request, is cleared. Writing 1 to this register is prohibited.
When this register is read by read-modify-write instructions, 1 is returned.
253
CHAPTER 10 EXTERNAL-INTERRUPT CONTROL BLOCK
10.2.3 External-Interrupt Level Setting Register
(ELVR0, ELVR1: External Level Register)
The external level register (ELVR0, ELVR1) selects the level at which an interrupt
request is detected.
■ External Level Register (ELVR0, ELVR1: External Level Register)
The register configuration of the external level register is shown below.
ELVR0
15
14
13
12
11
10
9
8
Address: 0000CCH
LB7
LA7
LB6
LA6
LB5
LA5
LB4
LA4
7
6
5
4
3
2
1
0
LB3
LA3
LB2
LA2
LB1
LA1
LB0
LA0
15
14
13
12
11
10
9
8
ELVR1
Address: 0000CEH
LB15 LA15 LB14 LA14 LB13 LA13 LB12 LA12
7
6
5
4
3
LB11 LA11 LB10 LA10 LB9
2
1
0
LA9
LB8
LA8
Initial value Access
00000000B
R/W
Initial value Access
00000000B
R/W
Initial value Access
00000000B
R/W
Initial value Access
00000000B
R/W
INT0 to INT15 has two bits that specify the operations shown below. If you specify that the
request be detected at a low or high level, even when each bit of the EIRR is cleared, the
corresponding bits are set again when active-level input occurs.
Table 10.2-1 is the external-interrupt level setting table.
Table 10.2-1 External-Interrupt Level Setting Table
254
LB15 to LB0
LA15 to LA0
Operation
0
0
"L" level request
0
1
"H" level request
1
0
Rising edge request
1
1
Falling edge request
CHAPTER 10 EXTERNAL-INTERRUPT CONTROL BLOCK
10.3 External-Interrupt Operation
When the request specified by the ELVR register is inputted to the corresponding pin
after the request level and enable register are set, this module issues an interrupt
request signal to the interrupt controller.
■ External-Interrupt Operation
When the interrupt issued from this resource has the highest priority of all the interrupts issued
concurrently in the interrupt controller, the appropriate interrupt is generated.
Figure 10.3-1 shows the operation for an external interrupt.
Figure 10.3-1 External-Interrupt Operation
External interrupt
Interrupt controller
CPU
Resource request
ELVR
EIRR
ENIR
Interrupt
level
ICR YY
CMP
ICR XX
CMP
ILM
Interrupt source
■ Return from Stop State
When the rising or falling edge request is selected, the return from the stop state of the clock
stop mode is not performed.
■ Setting Procedure for an External Interrupt
To set the registers in the external-interrupt block, follow the steps below.
1. The general-purpose I/O port that is shared with the terminal used as external interrupt input
is set to the input port.
2. Disable the appropriate bits of the enable interrupt register.
3. Set the appropriate bits of the external level register.
4. Clear the appropriate bits of the external-interrupt request register.
5. Enable the appropriate bits of the enable interrupt register.
Steps 4 and 5 can be performed concurrently by writing 16-bit data.
Before setting registers included in this module, be sure to disable the enable-interrupt register.
In addition, before enabling the enable-interrupt register, be sure to clear the external-interrupt
request register. This prevents interrupt sources from being accidentally generated when the
registers are set or interrupts are enabled.
255
CHAPTER 10 EXTERNAL-INTERRUPT CONTROL BLOCK
10.4 External-Interrupt Request Level
When the request level is the edge request, a minimum of three machine cycles
(peripheral clock machine cycles) for the pulse width are required for edge detection.
When the request input level is in accordance with the level setting, even if the request
input previously issued externally is canceled, the request to the interrupt controller
remains active because the internal source-holding circuit retains it.
To cancel the request to the interrupt controller, clear the external-interrupt request
register.
■ External-Interrupt Request Level
Figure 10.4-1 shows how the source holding circuit is cleared when the level is set. Figure 10.42 shows how interrupt sources are inputted when interrupt sources are enabled and how an
interrupt request is issued to the interrupt controller.
Figure 10.4-1 Clearing the Source-holding Circuit During Level Setting
Interrupt input
Level detection
Enable gate
Source F/F
(Source-holding circuit)
To interrupt controller
Sources are retained until holding circuit is cleared.
Figure 10.4-2 Interrupt-source Input with Interrupts Enabled and Interrupt Request to the Interrupt
Controller
Interrupt input
"H" level
Interrupt request to
interrupt controller
Inactivated by clearing source F/F
256
CHAPTER 11 DELAYED-INTERRUPT MODULE
CHAPTER 11
DELAYED-INTERRUPT MODULE
This chapter gives an overview of the delayed-interrupt module, the structure and
functions of the registers, and the operation of the delayed-interrupt module.
11.1 Overview of Delayed-Interrupt Module
11.2 Delayed-Interrupt Control Register (DICR)
11.3 Operation of Delayed-Interrupt Module
257
CHAPTER 11 DELAYED-INTERRUPT MODULE
11.1 Overview of Delayed-Interrupt Module
The delayed-interrupt module issues an interrupt for switching tasks.
This module can be used to issue or cancel an interrupt request to the CPU via
software.
■ Block Diagram of the Delayed Interrupt Module
A block diagram of the delayed interrupt module is shown in Section "12.2 Block Diagram of the
Interrupt Controller".
■ List of Delayed Interrupt Module Registers
Figure 11.1-1 lists the delayed interrupt module registers.
Figure 11.1-1 List of Delayed Interrupt Module Registers
258
Address:
7
6
5
4
3
2
1
0
000430H
−
−
−
−
−
−
−
DLYI
R/W
←bit No.
DICR
CHAPTER 11 DELAYED-INTERRUPT MODULE
11.2 Delayed-Interrupt Control Register (DICR)
The delayed-interrupt control register (DICR) controls delayed interrupts.
■ Delayed-Interrupt Control Register (DICR)
The register configuration of the delayed-interrupt control register (DICR) is shown below.
Address:
7
6
5
4
3
2
1
0
−
−
−
−
−
−
−
←bit No.
000430H
DLYI
R/W
-------0B
(Initial value)
[bit0] DLYI
This bit controls issuing and canceling of the appropriate interrupt sources.
DLY1
Description
0
Delayed-interrupt source not canceled or requested (initial value)
1
Delayed-interrupt source issued
259
CHAPTER 11 DELAYED-INTERRUPT MODULE
11.3 Operation of Delayed-Interrupt Module
The delayed-interrupt function issues interrupts for switching tasks. This function can
be used to issue or cancel an interrupt request to the CPU via software.
■ Interrupt Number
The delayed interrupt is assigned to the interrupt source corresponding to the maximum
interrupt number.
For the MB91130, the delayed interrupt is assigned to interrupt number 63 (3FH).
■ DLYI Bit of DICR
To issue a delayed-interrupt source, set this bit to 1. To cancel the delayed-interrupt source, set
this bit to 0.
This bit is the same as that used as interrupt-source flag of general interrupts. Use the interrupt
routine to clear this bit and switch tasks.
260
CHAPTER 12 INTERRUPT CONTROLLER
CHAPTER 12
INTERRUPT CONTROLLER
This chapter provides an overview of the interrupt controller, its block diagram, the
structure and functions of the registers, the operation of the interrupt controller.
12.1 Overview of Interrupt Controller
12.2 Block Diagram of the Interrupt Controller
12.3 List of Interrupt Controller Registers
12.4 Priority Evaluation
12.5 Return from Standby (Stop or Sleep) Mode
12.6 Hold-Request Cancellation Request
12.7 Example of Using Hold-Request Cancellation-Request Function (HRCR)
261
CHAPTER 12 INTERRUPT CONTROLLER
12.1 Overview of Interrupt Controller
The interrupt controller accepts and arbitrates interrupts.
■ Hardware Configuration of Interrupt Controller
This module consists of the following components.
•
Interrupt control register (ICR register: ICR00 to ICR47)
•
Interrupt priority evaluation circuit
•
Interrupt level and interrupt number (vector) generator
•
HOLD request cancellation request generator
■ Main Functions of the Interrupt Controller
This module performs the following functions:
262
•
Detecting an interrupt request.
•
Evaluating the interrupt priority (based on levels and numbers)
•
Forwarding the result of source-interrupt level evaluation (to the CPU)
•
Forwarding the result of source-interrupt number evaluation (to the CPU)
•
Indicating a recovery from the stop mode through interrupt generation
•
Issuing HOLD request cancellation requests to the bus master
CHAPTER 12 INTERRUPT CONTROLLER
12.2 Block Diagram of the Interrupt Controller
Figure 12.2-1 shows a block diagram of the interrupt controller.
■ Block Diagram of the Interrupt Controller
Figure 12.2-1 Block Diagram of the Interrupt Controller
INTO
*2
IM
Priority evaluation
OR
5
NMI handling
NMI
4
Level evaluation
ICR00
Resource
interrupt 00
Vector
evaluation
6
Level
and
vector
generation
Hold
request
Cancellation
request
LEVEL4 to
LEVEL0
HLDCAN
*3
VCT5 to
VCT0
ICR47
Resource
interrupt 47
*1
(DLYIRQ)
DLYI
R-bus
*1
DLYI in the figure represents the delayed interrupt block.
(See CHAPTER11 DEL AYED-INTERRUPT MODULE for the details.)
*2
INT0 is the wake-up signal for a clock control block in sleep or stop state.
*3
HLDCAN is the bus-release request signal for a bus master other than the CPU.
Note: This device type does not have the NMI function.
263
CHAPTER 12 INTERRUPT CONTROLLER
12.3 List of Interrupt Controller Registers
Figure 12.3-1 lists the registers of the interrupt controller.
■ List of Interrupt Controller Registers
Figure 12.3-1 List of Interrupt Controller Registers
Address:
7
6
5
4
3
2
1
0
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
←bit No.
00000400H
00000401H
00000402H
00000403H
00000404H
00000405H
00000406H
00000407H
00000408H
00000409H
0000040AH
0000040BH
0000040CH
0000040DH
0000040EH
0000040FH
00000410H
00000411H
00000412H
00000413H
00000414H
00000415H
00000416H
00000417H
00000418H
00000419H
0000041AH
0000041BH
0000041CH
0000041DH
0000041EH
0000041FH
ICR3
ICR3
ICR3
ICR3
ICR3
ICR3
ICR3
ICR3
ICR3
ICR3
ICR3
ICR3
ICR3
ICR3
ICR3
ICR3
ICR3
ICR3
ICR3
ICR3
ICR3
ICR3
ICR3
ICR3
ICR3
ICR3
ICR3
ICR3
ICR3
ICR3
ICR3
ICR3
R/W
ICR2
ICR2
ICR2
ICR2
ICR2
ICR2
ICR2
ICR2
ICR2
ICR2
ICR2
ICR2
ICR2
ICR2
ICR2
ICR2
ICR2
ICR2
ICR2
ICR2
ICR2
ICR2
ICR2
ICR2
ICR2
ICR2
ICR2
ICR2
ICR2
ICR2
ICR2
ICR2
R/W
ICR1
ICR1
ICR1
ICR1
ICR1
ICR1
ICR1
ICR1
ICR1
ICR1
ICR1
ICR1
ICR1
ICR1
ICR1
ICR1
ICR1
ICR1
ICR1
ICR1
ICR1
ICR1
ICR1
ICR1
ICR1
ICR1
ICR1
ICR1
ICR1
ICR1
ICR1
ICR1
R/W
ICR0
ICR0
ICR0
ICR0
ICR0
ICR0
ICR0
ICR0
ICR0
ICR0
ICR0
ICR0
ICR0
ICR0
ICR0
ICR0
ICR0
ICR0
ICR0
ICR0
ICR0
ICR0
ICR0
ICR0
ICR0
ICR0
ICR0
ICR0
ICR0
ICR0
ICR0
ICR0
R/W
ICR00
ICR01
ICR02
ICR03
ICR04
ICR05
ICR06
ICR07
ICR08
ICR09
ICR10
ICR11
ICR12
ICR13
ICR14
ICR15
ICR16
ICR17
ICR18
ICR19
ICR20
ICR21
ICR22
ICR23
ICR24
ICR25
ICR26
ICR27
ICR28
ICR29
ICR30
ICR31
(Continued)
264
CHAPTER 12 INTERRUPT CONTROLLER
(Continued)
Address:
7
6
5
4
3
2
1
0
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
←bit No.
00000420H
00000421H
00000422H
00000423H
00000424H
00000425H
00000426H
00000427H
00000428H
00000429H
0000042AH
0000042BH
0000042CH
0000042DH
0000042EH
0000042FH
−
−
−
−
ICR2
ICR2
ICR2
ICR2
ICR2
ICR2
ICR2
ICR2
ICR2
ICR2
ICR2
ICR2
ICR2
ICR2
ICR2
ICR2
R/W
LVL2
R/W
ICR1
ICR1
ICR1
ICR1
ICR1
ICR1
ICR1
ICR1
ICR1
ICR1
ICR1
ICR1
ICR1
ICR1
ICR1
ICR1
R/W
LVL1
R/W
ICR0
ICR0
ICR0
ICR0
ICR0
ICR0
ICR0
ICR0
ICR0
ICR0
ICR0
ICR0
ICR0
ICR0
ICR0
ICR0
R/W
LVL0
R/W
ICR32
ICR33
ICR34
ICR35
ICR36
ICR37
ICR38
ICR39
ICR40
ICR41
ICR42
ICR43
ICR44
ICR45
ICR46
ICR47
00000431H
ICR3
ICR3
ICR3
ICR3
ICR3
ICR3
ICR3
ICR3
ICR3
ICR3
ICR3
ICR3
ICR3
ICR3
ICR3
ICR3
R/W
LVL3
R/W
HRCL
265
CHAPTER 12 INTERRUPT CONTROLLER
12.3.1 Interrupt Control Register (ICR00 to ICR47)
This register controls interrupts. One of these registers exists for each interrupt input
and is used to set the interrupt level of the corresponding interrupt request.
■ Interrupt Control Register (ICR)
The register configuration of the interrupt control register (ICR) is shown below.
Address:
7
6
5
4
3
2
1
0
←bit No.
000400H to
00042FH
−
−
−
−
ICR3
R/W
ICR2
R/W
ICR1
R/W
ICR0
R/W
----1111B
(Initial value)
[bit3 to bit0] ICR3 to ICR0
These are interrupt-level setting bits and specify the interrupt level of the corresponding
interrupt request.
If the interrupt level specified in this register is equal to or greater than to the level mask
value specified in the ILM register of the CPU, the interrupt request is masked by the CPU.
These bits are initialized to 1111B at reset. The interrupt-level setting bits that can be set and
the corresponding interrupt levels are shown in Table 12.3-1.
266
CHAPTER 12 INTERRUPT CONTROLLER
Table 12.3-1 Interrupt-level Setting Bits and Corresponding Interrupt Levels
ICR4
ICR3
ICR2
ICR1
ICR0
Interrupt level
0
0
0
0
0
0
0
1
1
1
0
14
0
1
1
1
1
15
(NMI)
1
0
0
0
0
16
1
0
0
0
1
17
Highest level that can be set
(High)
1
0
0
1
0
18
1
0
0
1
1
19
1
0
1
0
0
20
1
0
1
0
1
21
1
0
1
1
0
22
1
0
1
1
1
23
1
1
0
0
0
24
1
1
0
0
1
25
1
1
0
1
0
26
1
1
0
1
1
27
1
1
1
0
0
28
1
1
1
0
1
29
1
1
1
1
0
30
1
1
1
1
1
31
Reserved by the system
(Low)
Interrupt disabled
Since ICR4 is fixed by the system, this register does not have an ICR4 bit.
267
CHAPTER 12 INTERRUPT CONTROLLER
12.3.2 Hold-Request Cancellation-Request Level-Set Register
(HRCL)
This register sets the level for issuing hold-request cancellation requests.
■ Hold-request Cancellation Request Level Set Register (HRCL)
The register configuration of the hold-request cancellation-request level-set register (HRCL) is
shown below.
Address
7
6
5
4
3
2
1
0
←bit No.
000431H
−
−
−
−
LVL3
R/W
LVL2
R/W
LVL1
R/W
LVL0
R/W
----1111B
(Initial value)
[bit3 to bit0] LVL3 to LVL0
These bits set the interrupt level for issuing hold-request cancellation requests to the bus
master.
If an interrupt request with an interrupt level higher than that specified in this register is
issued, a hold-request cancellation request is issued to the bus master.
268
CHAPTER 12 INTERRUPT CONTROLLER
12.4 Priority Evaluation
This module selects the interrupt source with the highest priority, out of all interrupt
sources that occur at the same time, and outputs the interrupt level and interrupt
number of the source to the CPU.
■ Priority Evaluation
The criteria for evaluating the priority are shown below.
1. NMI
2. The interrupt source meets the following conditions:
•
The interrupt source has an interrupt level other than "31" (A value of "31" represents
interrupt disable.)
•
The interrupt source has the lowest interrupt level
•
The interrupt source has the smallest interrupt number
Table 12.4-1 shows the relationship among interrupt sources, interrupt numbers, and interrupt
levels.
Table 12.4-1 Relationship Among Interrupt Sources, Interrupt Numbers, and Interrupt Levels (1 / 3)
Interrupt number
Interrupt
level
Offset
TBR default
address
0F
15(FH)
3C0H
000FFFC0H
16
10
ICR00
3BCH
000FFFBCH
External interrupt 1
17
11
ICR01
3B8H
000FFFB8H
External interrupt 2
18
12
ICR02
3B4H
000FFFB4H
External interrupt 3
19
13
ICR03
3B0H
000FFFB0H
External interrupt 4
20
14
ICR04
3ACH
000FFFACH
External interrupt 5
21
15
ICR05
3A8H
000FFFA8H
External interrupt 6
22
16
ICR06
3A4H
000FFFA4H
External interrupt 7
23
17
ICR07
3A0H
000FFFA0H
External interrupt 8 to 15
24
18
ICR08
39CH
000FFF9CH
System-reserved
25
19
ICR09
398H
000FFF98H
UART0 (Receiving
completed)
26
1A
ICR10
394H
000FFF94H
UART1 (Receiving
completed)
27
1B
ICR11
390H
000FFF90H
UART2 (Receiving
completed)
28
1C
ICR12
38CH
000FFF8CH
Interrupt source
Decimal
Hexadecimal
(NMI request)
15
External interrupt 0
269
CHAPTER 12 INTERRUPT CONTROLLER
Table 12.4-1 Relationship Among Interrupt Sources, Interrupt Numbers, and Interrupt Levels (2 / 3)
Interrupt number
Interrupt source
Interrupt
level
Offset
TBR default
address
Decimal
Hexadecimal
UART3 (Receiving
completed)
29
1D
ICR13
388H
000FFF88H
System-reserved
30
1E
ICR14
384H
000FFF84H
UART0 (Sending completed)
31
1F
ICR15
380H
000FFF80H
UART1 (Sending completed)
32
20
ICR16
37CH
000FFF7CH
UART2 (Sending completed)
33
21
ICR17
378H
000FFF78H
UART3 (Sending completed)
34
22
ICR18
374H
000FFF74H
System-reserved
35
23
ICR19
370H
000FFF70H
DMAC (Exit and error)
36
24
ICR20
36CH
000FFF6CH
Reload timer 0
37
25
ICR21
368H
000FFF68H
Reload timer 1
38
26
ICR22
364H
000FFF64H
Reload timer 2
39
27
ICR23
360H
000FFF60H
Reload timer 3
40
28
ICR24
35CH
000FFF5CH
System-reserved
41
29
ICR25
358H
000FFF58H
A/D
42
2A
ICR26
354H
000FFF54H
PPG0
43
2B
ICR27
350H
000FFF50H
PPG1
44
2C
ICR28
34CH
000FFF4CH
PPG2
45
2D
ICR29
348H
000FFF48H
PPG3
46
2E
ICR30
344H
000FFF44H
PPG4
47
2F
ICR31
340H
000FFF40H
PPG5
48
30
ICR32
33CH
000FFF3CH
U/D counter 0
49
31
ICR33
338H
000FFF38H
U/D counter 1
50
32
ICR34
334H
000FFF34H
ICU0 (Fetch)
51
33
ICR35
330H
000FFF30H
ICU1 (Fetch)
52
34
ICR36
32CH
000FFF2CH
ICU2 (Fetch)
53
35
ICR37
328H
000FFF28H
ICU3 (Fetch)
54
36
ICR38
324H
000FFF24H
OCU0 (Coincidence)
55
37
ICR39
320H
000FFF20H
OCU1 (Coincidence)
56
38
ICR40
31CH
000FFF1CH
OCU2 (Coincidence)
57
39
ICR41
318H
000FFF18H
OCU3 (Coincidence)
58
3A
ICR42
314H
000FFF14H
OCU4/5 (Coincidence)
59
3B
ICR43
310H
000FFF10H
270
CHAPTER 12 INTERRUPT CONTROLLER
Table 12.4-1 Relationship Among Interrupt Sources, Interrupt Numbers, and Interrupt Levels (3 / 3)
Interrupt number
Interrupt source
Interrupt
level
Offset
TBR default
address
Decimal
Hexadecimal
OCU6/7 (Coincidence)
60
3C
ICR44
30CH
000FFF0CH
System-reserved
61
3D
ICR45
308H
000FFF08H
16-bit free running timer
62
3E
ICR46
304H
000FFF04H
Delayed interrupt source bit
63
3F
ICR47
300H
000FFF00H
■ Releasing Interrupt Factors
The interrupt routine has restrictions on the relationship between an instruction for releasing
interrupt factors and the RETI instruction.
For details, see "CHAPTER 3 MEMORY SPACE, CPU, AND CONTROL UNIT".
271
CHAPTER 12 INTERRUPT CONTROLLER
12.5 Return from Standby (Stop or Sleep) Mode
This module implements the function that enables a return from the stop mode
through interrupts.
■ Return from Standby (Stop or Sleep) Mode
If at least one interrupt request is issued from a peripheral, the request for returning from the
stop mode is sent to the clock control block.
Since the priority evaluation block restarts operation after the clock signal is supplied upon
return from stop mode, the CPU continues executing instructions until the result is outputted
from the priority evaluation block.
The same operation is performed when returning from the sleep state.
The registers in this module are accessible in the sleep state.
Note:
For interrupt sources you do not want to use to return from the stop and sleep states, set the
control register for the corresponding peripheral to prohibit the interrupt request output. Since the
return request signal in the standby state is generated by simply ORing of all interrupt sources, the
contents of the interrupt level specified in ICR register are not applied.
272
CHAPTER 12 INTERRUPT CONTROLLER
12.6 Hold-Request Cancellation Request
To handle an interrupt with a higher priority while the CPU is in hold status, the
requester of the hold request must cancel that request. The interrupt level used to
determine whether a hold-request cancellation request is issued needs to be set in the
HRCL register.
■ Criteria for Determining whether a Hold-request Cancellation-request Must be Issued
If an interrupt source with an interrupt level higher than that specified in the HRCL register is
issued, a hold-request cancellation request must be generated.
•
Interrupt level of HRCL register is greater than interrupt level after evaluating priority
--> Cancellation request issued
•
Interrupt level of HRCL register is equal to or less than interrupt level after evaluating priority
--> Cancellation request not issued
Since this cancellation request is valid unless the interrupt source that is a cause for generation
of cancellation request is cleared, DMA transfer does never start. Be sure to clear the
corresponding interrupt source.
■ Levels That Can Be Set for Hold Request Cancellation Requests
A number from 0000B to 1111B can ICR register be set in the HRCL register.
When 1111B is set, the cancellation request is issued for all interrupt levels. When 0000B is set,
the cancellation request is issued only for NMI.
Table 12.6-1 lists the interrupt levels for which the hold-request cancellation request is issued.
Table 12.6-1 Interrupt Levels for which the Hold-request Cancellation Request is Issued
HRCL register
Interrupt levels for which the hold-request cancellation
request is issued
16
(Only NMI)
17
Interrupt level 16
18
Interrupt levels 16, 17
:
31
:
Interrupt levels 16 to 30 (Initial value)
Note:
After a reset, DMA transfer is disabled for all interrupt levels. This means that DMA transfer is not
performed when an interrupt has been issued. Therefore, set the HRCL register to the appropriate
value.
273
CHAPTER 12 INTERRUPT CONTROLLER
12.7 Example of Using Hold-Request Cancellation-Request
Function (HRCR)
To let the CPU perform an operation with a higher priority during DMA transfer, the
DMA must release the hold state by canceling the hold request. In this case, use an
interrupt to cause the DMA to cancel the hold request. This allows the CPU to operate
with a higher priority.
■ Control Register
❍ HRCL (Hold-request cancellation-level set register): this module
When an interrupt with the priority level higher than that specified in this register occurs, the
hold request cancellation request is issued to the DMA. This register is used to set the base
level.
❍ ICR: this module
For the ICR corresponding to the interrupt source used, set an interrupt level higher than that
specified in the HRCL register.
❍ PDRR (DMA request disable register): clock control block
This register temporarily disables a hold request from the DMA. It prevents the system from
entering the hold state again by clearing the interrupt source. A hold request from the DMA is
passed to the CPU only when this register is set to 0000B. The contents of this register must be
incremented at the beginning of the interrupt routine and decremented at the end of the interrupt
routine.
■ Hardware Configuration
The signal flow of each signal is shown below.
Figure 12.7-1 Sample Hardware Configuration for Using a Hold-request Cancellation-request Signal
This module
IRQ
274
(ICR)
(HRCL)
Clock control block
HRQ
DMA
HRCR
DHRQ (PDRR)
HACK
CPU
DHRQ :
HRQ :
HACK :
IRQ :
HRCR :
DMA hold request
Hold request
Hold acknowledge
Interrupt request
Hold request cancellation request
CHAPTER 12 INTERRUPT CONTROLLER
■ Hold-request Cancellation-request Sequence
❍ Example for the interrupt routine
Figure 12.7-2 is a sample timing chart of the hold request cancellation-request sequence
(interrupt level HRCL > a).
Figure 12.7-2 Sample Timing Chart of the Hold Request Cancellation-request Sequence
(Interrupt Level is HRCL > a)
RUN
Bus hold
CPU
Interrupt handling
(1)(2)
(3) (4)
Bus hold (DMA transfer)
DHRQ
HRQ
HACK
IRQ
LEVEL
a
HRCR
PDRR
0000
0001
0000
Sample interrupt routine
(1) PDRR incremented
(2) Interrupt source cleared
(3) PDRR decremented
(4) RETI
When an interrupt request is issued, the interrupt level is changed. If this level is higher than
the level specified in the HRCL register, the HRCR is activated for the DMA. This causes the
DMA to cancel the hold request. The CPU returns from the hold state and performs interrupt
handling. The interrupt routine increments PDRR and clears the interrupt source. This causes
the interrupt level to vary, inactivates the HRCR, and allows the DMA to issue a hold request
again. However, because the PDRR is not 0, this hold request is blocked. To enable DMA
transfer again, decrement the PDRR to pass the hold request to the CPU.
275
CHAPTER 12 INTERRUPT CONTROLLER
❍ Example for multiple interrupt routine
Figure 12.7-3 is a sample timing chart for multiple interrupts.
Figure 12.7-3 Sample Timing of the Hold-request Cancellation-request Sequence (HRCL > a > b)
RUN
Bus hold
Interrupt I
(1)
CPU
Interrupt handling II
(5)(6)
(7)(8)
b
a
Interrupt handling I
(2)
Bus hold
(3) (4)
DHRQ
HRQ
HACK
IRQ1
IRQ2
LEVEL
a
HRCR
PDRR
0000
0001
0002
0001
0000
Sample interrupt routine
(1), (5) Increment PDRR.
(2), (6) Clear the interrupt source.
(3), (7) Decrement PDRR.
(4), (8) RETI
In this example, an interrupt with a higher priority occurs while interrupt routine I is running. This
example also prevents a hold request from being issued accidentally by incrementing the PDRR
at the beginning of each interrupt routine and decrementing the PDRR at the end of interrupt
routine.
Notes:
• Increment the PDRR at the beginning of the interrupt routine that is processed while DMA
transfer is performed (the CPU is held), and decrement it at the end of the interrupt routine.
Otherwise, DMA transfer is performed again while the interrupt routine is being executed.
• In addition, do not increment and decrement the PDRR in a normal interrupt routine. This
degrades performance because DMA transfer cannot be performed while the interrupt routine is
being executed.
• Exercise caution when setting interrupt levels in the HRCL register and in the ICR register.
276
CHAPTER 13 8/10-BIT A/D CONVERTER
CHAPTER 13
8/10-BIT A/D CONVERTER
This chapter provides an overview of the 8/10-bit A/D converter, its block diagram, its
pin, configuration and functions of its registers, and operation of the 8/10-bit A/D
converter.
13.1 Overview of the 8/10-bit A/D Converter
13.2 8/10-bit A/D Converter Block Diagram
13.3 8/10-bit A/D Converter Pins
13.4 8/10-bit A/D Converter Registers
13.5 8/10-bit A/D Converter Interrupt
13.6 Operation of the 8/10-bit A/D Converter
13.7 A/D Converted Data Preservation Function
13.8 Notes on Using the 8/10-bit A/D Converter
277
CHAPTER 13 8/10-BIT A/D CONVERTER
13.1 Overview of the 8/10-bit A/D Converter
The 8/10-bit A/D converter converts an analog voltage (input voltage) that is inputted
to an analog input pin into a digital value.
■ Features of the 8/10-bit A/D Converter
The 8/10-bit A/D converter changes an analog input voltage into a 10-bit or 8-bit digital value
based on the RC successive approximation conversion method. Signals are inputted through
eight analog input channel pins, and software, internal clock, or external pin trigger can be
selected as a cause of startup of conversion.
The 8/10-bit A/D converter has the following features:
•
The minimum conversion time is 5.0 µs (including the sampling time, when the machine
clock frequency is 33 MHz).
•
The RC successive approximation conversion method is applied using a sampling/holding
circuit.
•
For the resolution, 10 bits or 8 bits can be selected.
•
Any of the eight channels can be selected for the analog input pins by a program.
•
An interrupt request can be generated at the end of A/D conversion.
•
When interrupts are enabled, no data is lost during continuous conversion due to the
converted data-preservation function.
•
Software, 16-bit reload timer 2 (rising edge), or external pin trigger (falling edge) can be
selected as a cause for starting conversion.
■ Conversion Modes of 8/10-bit A/D Converter
The following three conversion modes are supported.
Table 13.1-1 8/10-bit A/D Converter Conversion Modes
Conversion
mode
Single conversion operation
Singleconversion mode
The converter converts a signal input from
a specified channel (only one channel)
and terminates.
The converter simultaneously converts
signal inputs from contiguous multiple
channels (up to eight channels can be
specified) and terminates.
Continuousconversion mode
The converter continuously converts signal
inputs from a specified channel (only one
channel).
The converter continuously converts signal
inputs from contiguous multiple channels
(up to eight channels can be specified).
Intermittentconversion mode
The converter converts a signal input from
the specified channel (only one channel),
then stops temporarily until it is started
again.
The converter continuously converts signal
inputs from continuous multiple channels
(up to eight channels can be specified).
However, the converter temporarily stops
after converting a signal input until it is
started again.
278
Scan conversion operation
CHAPTER 13 8/10-BIT A/D CONVERTER
13.2 8/10-bit A/D Converter Block Diagram
Figure 13.2-1 is a block diagram of the 8/10-bit A/D converter.
■ 8/10-bit A/D Converter Block Diagram
Figure 13.2-1 8/10-bit A/D Converter Block Diagram
AVRH
AVSS AVRL AVSS
MPX
D/A converter
Input circuit
AN0
AN1
AN2
AN3
AN4
AN5
AN6
AN7
Successive appro
-ximation register
Comparator
R-bus
Sampling and holding circuit
Decoder
Data register
ADCR
A/D control register 1
A/D control register 2
16-bit reload timer 2
External pin trigger
φ
ADCS1, 2
Operation clock
Prescaler
The function of each block is as follows.
❍ A/D control status registers (ADCS1, ADCS2)
The A/D control status registers can be used for starting conversion via software, selecting a
start trigger, selecting a conversion mode, selecting an A/D conversion channel, and enabling/
disabling interrupt requests. Moreover, they can be used for checking the state of interrupt
requests, and indicating that the converter is temporarily stopped or converting signals.
❍ A/D data register (ADCR)
Stores the result of A/D conversion. This register also selects the resolution of A/D conversion.
❍ Clock selector
Selects an A/D conversion start clock. 16-bit reload timer channel 2 output or external pin
trigger can be selected for the start clock.
279
CHAPTER 13 8/10-BIT A/D CONVERTER
❍ Decoder
Selects the analog input pin to be used in accordance with the setting of the ANE0 to ANE2 bits
and ANS0 to ANS2 bits for the A/D control status register (ADCS1).
❍ Analog channel selector
Selects one of the eight analog input pins to be used.
❍ Sampling/holding circuit
Maintains the voltage input from the pin selected by the analog channel selector. This circuit
samples and holds the voltage input immediately after A/D conversion is started to allow
conversion to be performed without being affected by fluctuations in the input voltage during A/D
conversion (comparison).
❍ D/A converter
Generates a reference voltage used for comparison with the input voltage that is sampled and
held.
❍ Comparator
Compares the input voltage that is sampled and held with the D/A converter output voltage to
determine which is higher respectively lower.
❍ Control circuit
Determines the A/D conversion value based on whether a high or low signal is sent from the
comparator. After A/D conversion, the result of conversion is stored in the A/D data register
(ADCR), after which an interrupt request is generated.
280
CHAPTER 13 8/10-BIT A/D CONVERTER
13.3 8/10-bit A/D Converter Pins
This section provides the 8/10-bit A/D converter pins and the block diagram of the
pins.
■ 8/10-bit A/D Converter Pins
The 8/10-bit A/D converter pins are also used as general-purpose ports. Table 13.3-1 lists the
functions, I/O formats of the pins, and settings when the 8/10-bit A/D converter is used.
Table 13.3-1 8/10-bit A/D Converter Pins
Function
Pin name
Channel 0
PK0/AN0
Channel 1
PK1/AN1
Channel 2
PK2/AN2
Channel 3
PK3/AN3
Channel 4
PK4/AN4
Channel 5
PK5/AN5
Channel 6
PK6/AN6
Channel 7
PK7/AN7
Pin
function
I/O
format
Port K I/O,
analog
input
CMOS
output,
CMOS
hysteresis
input or
analog
input
Pull-up
setting
None
Standby
control
I/O port settings
required for use of the
pins
None
Port K is set for input.
(DDRK: bit0 to bit7 = 0)
Pins are set for analog
input.
(AICR bit0 to bit7 = 1)
281
CHAPTER 13 8/10-BIT A/D CONVERTER
■ 8/10-bit A/D Converter Pin Block Diagram
Figure 13.3-1 is a block diagram of the 8/10-bit A/D converter pins.
Figure 13.3-1 Block Diagram of the Pins PK0/AN0 to PK7/AN7
AICR
Analog input
Internal data bus
PDR (port data register)
PDR read
Output
latch
PDR write
Pin
DDR (port direction register)
Direction
latch
DDR write
DDR read
Standby control
Notes:
• For the pins to be used as input ports, set the DDRK register bits corresponding to these pins to
0 and apply pull-up resistance to the external pin. Also, set the AICR register bits corresponding
to the pins to 0 as well.
• For pins to be used as analog input pins, set the AICR register bits corresponding to these pins
to 1 as well. The value that is read from the PDRK register at this time is 0.
282
CHAPTER 13 8/10-BIT A/D CONVERTER
13.4 8/10-bit A/D Converter Registers
Figure 13.4-1 provides a schema of the 8/10-bit A/D converter registers.
■ Schema of the 8/10-bit A/D Converter Registers
Figure 13.4-1 Schema of the 8/10-bit A/D Converter Registers
15
14
13
12
11
10
9
8
7
0000EBH
0000E6H
0000E4H
6
5
4
3
2
1
0
AICR
ADCS1
ADCS0
ADCR
283
CHAPTER 13 8/10-BIT A/D CONVERTER
13.4.1 A/D Control Status Register 1 (ADCS1)
A/D control status register 1 (ADCS1) is used for starting conversion via software,
selecting a start trigger, enabling/disabling interrupt requests, checking the state of
interrupt requests, and indicating when the converter is temporarily stopped or
converting signals.
■ Higher Bits of the A/D Control Status Register 1 (ADCS1)
Figure 13.4-2 shows the configuration and provides a functional outline of the A/D control status
register 1 (ADCS1).
Figure 13.4-2 Configuration and Functional Outline of A/D Control Status Register 1 (ADCS1)
0000E6H
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
BUSY
INT
INTE
PAUS
STS1
STS0
STRT
RESV
R/W
(0)
R/W
(0)
R/W
(0)
R/W
(0)
R/W
(0)
R/W
(0)
W
(0)
R/W
(0)
RESV
bit0
bit7
(ADCS0)
Reserved bit
Be sure to set this bit to 0.
STRT
A/D conversion start bit (effective only when
start via software is specified)
0
Do not start the A/D conversion function.
1
Starts the A/D conversion function.
STS1
STS0
0
0
A/D start cause selection bits
0
1
Start via software
Start via zero detection or start
via software
1
0
Start via 16-bit reload timer or start via software
1
1
Start via zero detection, start via 16-bit
reloadtimer, or start via software
PAUS Temporary stop flag bit
A/D conversion operation is not temporarily
0
stopped.
1
A/D conversion operation is temporarily stopped.
INTE Interrupt request permission bit
0
Disables output of interrupt requests.
1
Enables output of interrupt requests.
Interrupt request flag bits
INT
0
1
BUSY
R/W: Read/Write enabled
W: Write only
0, 1: Initial value
0
1
284
During read
During write
A/D conversion has not
This bit is cleared.
ended.
No
changes and no external
A/D conversion has ended. effect
Converting bits
During read
A/D conversion is being
stopped.
A/D conversion is being
performed.
During write
A/D conversion is forcibly
stopped.
No changes and no external
effect
CHAPTER 13 8/10-BIT A/D CONVERTER
[bit15] BUSY (Converting bit)
•
This is the bit for indicating that the A/D converter is currently performing a conversion.
•
When a read access shows that this bit is 0, the converter is not executing an A/D
conversion. When the bit is 1, an A/D conversion is in progress.
•
Setting this bit to 0 in a write operation forcibly stops the A/D conversion. Setting this bit to 1
has no effect.
Note: Do not specify forcible stop and start via software (BUSY = 0 and STRT = 1) at the
same time.
[bit14] INT (Interrupt request flag bit)
•
When data is stored in the A/D data register via A/D conversion, this bit is set to 1.
•
When both this bit and the interrupt request permission bit (ADCS: INTE) are set to 1, an
interrupt request is generated.
•
This bit is cleared by setting it to 0 via a write operation. Setting this bit to 1 has no effect.
Note: Clear this bit by setting it to 0 in a write operation while the A/D converter is stopped.
[bit13] INTE (Interrupt request permission bit)
•
This bit enables/disables output of an interrupt to the CPU.
•
When both this bit and the interrupt request flag bit (ADCS: INT) are 1, an interrupt request is
generated.
[bit12] PAUS (Temporary stop flag bit)
•
This bit becomes 1 when the A/D conversion operation is temporarily stopped.
•
This A/D converter has only one A/D data register. Thus, when continuous-conversion mode
is used, and if the CPU has not read the result of a previous conversion, the result of the
previous conversion is lost when the data in the register is overwritten with the result of the
next conversion. Therefore, in continuous-conversion mode, it is normally required to ensure
that the result of a conversion is transferred to memory whenever a conversion ends.
However, there may be cases where a transfer of converted data is not completed by the
time the next conversion starts due to multiple interrupts. This bit is used for addressing this
problem. If this bit is set to 1, A/D conversion is stopped in the period from when a
conversion ends to when the content in the data register is fully transferred so that the data
register is not overwritten with the data from the next conversion.
[bit11, bit10] STS1, STS0 (A/D start cause selection bits)
•
These bits select the cause for starting A/D conversion.
•
When multiple causes are specified as the start source, the start source that occurred first is
used for start.
Note: The change in the start procedure becomes effective as soon as a new cause has
been written. Therefore, if start causes are to be changed during A/D conversion,
change the start causes in a period in which no new start causes need to be applied.
[bit9] STRT (A/D conversion start bit)
•
This bit is used for starting A/D conversion from software.
•
Setting this bit to 1 in a writing operation starts A/D conversion.
•
In intermittent-conversion mode, this bit cannot restart A/D conversion.
Note: Do not specify forcible stop and start via software (BUSY = 0 and STRT = 1) at the
same time.
285
CHAPTER 13 8/10-BIT A/D CONVERTER
[bit8] RESV (Reserved bit)
Note: Be sure to set this bit to 0.
286
CHAPTER 13 8/10-BIT A/D CONVERTER
13.4.2 A/D Control Status Register 0 (ADCS0)
A/D control status register 0 (ADCS0) is used for selecting a conversion mode and A/D
conversion channel.
■ A/D Control Status Register 0 (ADCS0)
Figure 13.4-3 shows the configuration and function outline of A/D Control Status Register 0
(ADCS0).
Figure 13.4-3 Configuration and Functional Outline of A/D Control Status Register 0 (ADCS0)
bit15
0000E7H
bit8
(ADCS1)
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
MD1
MD0
ANS2
ANS1
ANS0
ANE2
ANE1
ANE0
R/W
(0)
R/W
(0)
R/W
(0)
R/W
(0)
R/W
(0)
R/W
(0)
R/W
(0)
R/W
(0)
ANE2
ANE1
ANE0 A/D conversion end channel selection bits
0
0
0
AN0 pin
0
0
1
AN1 pin
0
1
0
AN2 pin
0
1
1
AN3 pin
1
0
0
AN4 pin
1
0
1
AN5 pin
1
1
0
AN6 pin
1
1
1
AN7 pin
A/D conversion start channel selection bits
ANS2
ANS1
ANS0
At a stop
0
0
0
AN0 pin
0
0
1
AN1 pin
0
1
0
AN2 pin
0
1
1
AN3 pin
1
0
0
AN4 pin
1
0
1
AN5 pin
1
1
0
AN6 pin
1
1
AN7 pin
1
MD1
R/W: Read/Write enabled
0, 1: Initial value
MD0
0
0
0
1
1
0
1
1
Read
operation
during
conversion
Read operation at
a temporary stop in
intermittentconversion mode
Number of
the channel
for which a
signal is
being
converted
Number of the
channel for which
conversion has
been performed
immediately
before
A/D conversion mode selection bits
Single-conversion mode 1 (A converter operating in
this mode can be restarted.)
Single-conversion mode 2 (A converter operating in
this mode cannot be restarted.)
Continuous-conversion mode (A converter operating
in this mode cannot be restarted.)
Intermittent-conversion mode (A converter operating
in this mode cannot be restarted.)
287
CHAPTER 13 8/10-BIT A/D CONVERTER
[bit7, bit6] MD1, MD0 (A/D conversion mode selection bits)
•
These bits are used for selecting the A/D conversion mode.
•
Single-conversion mode 1, single-conversion mode 2, continuous-conversion mode, or
intermittent-conversion mode is selected in accordance with the values in the MD1 and MD0
bits.
•
The operation in each mode is as follows:
•
Single-conversion mode 1:
Consecutively performs A/D conversion between the
channel specified by ANS2 to ANS0 and the channel
specified by ANE2 to ANE0 only once. The converter can
be restarted.
•
Single-conversion mode 2:
Consecutively performs A/D conversion between the
channel specified by ANS2 to ANS0 and the channel
specified by ANE2 to ANE0 only once. The converter
cannot be restarted.
•
Continuous-conversion mode: Repeatedly performs A/D conversion between the
channel specified by ANS2 to ANS0 and the channel
specified by ANE2 to ANE0 until operation is forcibly
stopped with the BUSY bit. The converter cannot be
restarted.
•
Intermittent-conversion mode: Repeatedly performs A/D conversion between the
channel specified by ANS2 to ANS0 and the channel
specified by ANE2 to ANE0, temporarily stopping A/D
conversion on a per-channel basis, until it is forcibly
stopped by the BUSY bit. The converter cannot be
restarted. A temporarily stopped A/D conversion is
restarted in accordance with the start source selected with
the STS1 and STS0 bits.
Note: When the converter cannot be restarted in single-, continuous-, or intermittentconversion modes, the converter cannot be restarted by the timer, external trigger or
software.
[bit5, bit4, bit3] ANS2, ANS1, ANS0 (A/D conversion start channel selection bits)
•
These bits are used to specify the channel on which A/D conversion starts, and for checking
the number of the channel on which conversion is being performed.
•
The converter starts A/D conversion from the channel specified by these bits.
•
The number of the channel on which conversion is being performed can be read during A/D
conversion. While A/D conversion is being temporarily stopped in intermittent-conversion
mode, the number of the channel for which conversion was previously performed can be
read.
[bit2, bit1, bit0] ANE2, ANE1, ANE0(A/D conversion end channel selection bits)
•
These bits specify the channel at which A/D conversion ends.
•
A/D conversion is performed up to the channel specified by these bits at the start of A/D
conversion.
•
When the channel specified by ANS2 through ANS0 is specified by these bits, A/D
conversion is performed only for this channel.
When continuous-conversion mode or intermittent-conversion mode is specified, A/D
conversion control returns to the start channel specified by ANS2 to ANS0 after A/D
conversion is performed for the channel specified by these bits. When the specified start
channel number is larger than the specified end channel number, conversion is performed
from the start channel to AN7, then from AN0 to the end channel in a cycle.
288
CHAPTER 13 8/10-BIT A/D CONVERTER
Notes:
• Please do not set the A/D conversion mode setting bit (MD1, MD0) and the A/D conversion end
channel selection bit (ANE3, ANE2, ANE1, and ANE0) by the instruction of read-modify-write
after setting the start channel to the A/D conversion start channel selection bit (ANS3, ANS2,
ANS1, ANS0).
• The last conversion channel is read from the ANS3, ANS2, ANS1, and ANS0 bits until the A/D
conversion operating starts. Therefore, when MD1, MD0 bits and ANE3, ANE2, ANE1, and
ANE0 bits are set by the read-modify-write system instruction after setting the starting channel to
ANS3, ANS2, ANS1, and ANS0 bits, the value of the ANE3, ANE2, ANE1, and ANE0 bits may
be over-write.
289
CHAPTER 13 8/10-BIT A/D CONVERTER
13.4.3 A/D Data Register (ADCR)
The A/D data register (ADCR) stores the result of A/D conversion. This register is also
used for selecting the resolution of A/D conversion.
■ A/D Data Register (ADCR)
The figure below shows the configuration and functional outline of the A/D data register (ADCR).
Figure 13.4-4 Configuration and Functional Outline of the A/D Data Register (ADCR0, 1)
0000E4H
bit15
bit14
bit13
bit12
bit11
bit9
bit8
S10
ST1
ST0
CT1
W
(0)
W
(0)
W
(1)
W
(0)
CT0
D9
D8
W
(1)
(X)
R
(X)
R
(X)
bit7
D7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
D6
D5
D4
D3
D2
D1
D0
R
(X)
R
(X)
R
(X)
R
(X)
R
(X)
R
(X)
R
(X)
R
(X)
bit10
A/D data bits
D0 to D9
Converted data
CT1
CT0
0
0
34 machine cycles (4.3
s @ 8MHz)
0
1
67 machine cycles (4.2
s @ 16MHz)
1
0
100 machine cycles (4.0
s @ 25MHz)
1
1
122 machine cycles (3.7
s @ 33MHz)
ST1
ST0
Sampling time setting bits
0
0
11 machine cycles (1.4
0
1
23 machine cycles (1.4
s @ 16MHz)
1
0
33 machine cycles (1.3
s @ 25MHz)
1
1
45 machine cycles (1.4
s @ 33MHz)
S10
R: Read only
W: Write only
0, 1: Initial value
Comparison time setting bits
s @ 8MHz)
A/D conversion resolution selection bit
0
10-bit resolution mode (D9 to D0)
1
8-bit resolution mode (D7 to D0)
[bit15] S10 (A/D conversion resolution selection bit)
290
•
This bit is used for selecting the resolution of A/D conversion.
•
Setting this bit to 0 in a writing operation selects a resolution of 10 bits. Setting this bit to 1
selects a resolution of 8 bits.
CHAPTER 13 8/10-BIT A/D CONVERTER
Note: Which data bits are used depends on the resolution.
[bit14, bit13] ST1, ST0 (Sampling time setting bits)
•
These bits are used for selecting the A/D conversion sampling time.
•
After A/D conversion is started, analog input is acquired for the time specified by these bits.
Note: When 00 for 8 MHz is specified when 16-MHz operation is used, analog voltages may
not be correctly acquired.
[bit12, bit11] CT1, CT0 (Comparison time setting bit)
•
These bits are used to select the comparison time for A/D conversion.
•
After analog input is acquired (the sampling time elapses) and the time specified by these
bits elapses, the converted data is fixed and stored in bit9 to bit0 of this register.
Note: When 00 for 8 MHz is specified in cases where 16-MHz operation is used, the analog
converted value may not be correctly obtained.
[bit10]
Unused bit
[bit9 to bit0] D9 to D0
•
The result of A/D conversion is stored. The content of this register is rewritten every time
conversion is completed.
•
Normally, the final value of conversion is stored.
•
The initial value of this register is undetermined.
Note: The device has a function for saving converted data.
Do not write these bits during A/D conversion.
Notes:
• Be sure to rewrite the S10 bit during a stop of the A/D conversion operation and before the
conversion operation is restarted. When the S10 bit is rewritten after conversion, the content of
the ADCR becomes unknown.
• When the 10-bit mode is specified, be sure to use the word transfer command to read data from
the ADCR register.
291
CHAPTER 13 8/10-BIT A/D CONVERTER
13.5 8/10-bit A/D Converter Interrupt
The 8/10-bit A/D converter can generate an interrupt request when data is set in the A/
D data register during A/D conversion.
■ 8/10-bit A/D Converter Interrupt
Table 13.5-1 shows the 8/10-bit A/D converter interrupt control bits and the cause for an
interrupt.
Table 13.5-1 8/10-bit A/D Converter Interrupt Control Bits and Cause for an Interrupt
8/10-bit A/D converter
Interrupt request flag bit
ADCS1:INT
Interrupt request permission
bit
ADCS1:INTE
Cause of interrupt
Writing the A/D conversion result to the A/D data register
When the A/D conversion operation is started and the A/D conversion result is set to the A/D
data register (ADCR), the INT bit of the A/D control status register (ADCS1) is set to 1. If the
interrupt request is enabled (ADCS1: INTE = 1), an interrupt request is then outputted to the
interrupt controller.
292
CHAPTER 13 8/10-BIT A/D CONVERTER
13.6 Operation of the 8/10-bit A/D Converter
The 8/10-bit A/D converter supports three modes: single-conversion mode,
continuous-conversion mode, or intermittent-conversion mode. This section
describes the operation of the converter in each mode.
■ Operation in Single-conversion Mode
In single-conversion mode, analog inputs from channels specified by the ANS bits and ANE bits
are converted in sequence. After conversion is done for the end channel specified by the ANE
bits, A/D conversion ends. When the start channel is the same as the end channel (ANS =
ANE), conversion is performed only for the channel specified by the ANS bits. To operate the
converter in single-conversion mode, the setting shown in Figure 13.6-1 is required.
Figure 13.6-1 Single-conversion Mode Setting
bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
ADCS0,
ReBUSY INT INTE PAUS STS1 STS0 STRT served MD1 MD0 ANS2 ANS1 ANS0 ANE2 ANE1 ANE0
ADCS1
0
ADCR S10 ST1 ST0 CT1 CT0
Stores converted data.
: Used bit
: Set the bit corresponding to the used pin to 1.
0 : Set 0.
AICK
Note:
The following shows examples for the conversion sequences in single-conversion mode.
ANS = 000B, ANE = 011B: AN0 --> AN1 --> AN2 --> AN3 --> End
ANS = 110B, ANE = 010B: AN6 --> AN7 --> AN0 --> AN1 --> AN2 --> End
ANS = 011B, ANE = 011B: AN3 --> End
■ Operation in Continuous-conversion Mode
In the continuous-conversion mode, analog inputs from channels specified by the ANS bits and
ANE bits are converted in sequence. After conversion is done for the end channel specified by
the ANE bits, A/D conversion control returns to the analog input channel specified by the ANS
bits, before A/D conversion for the channel continues. When the start channel is same as the
end channel (ANS = ANE), conversion is repeatedly performed only for the channel specified by
the ANS bits. To operate the converter in continuous-conversion mode, the setting shown in
Figure 13.6-2 is required.
293
CHAPTER 13 8/10-BIT A/D CONVERTER
Figure 13.6-2 Continuous-conversion Mode Setting
bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
ADCS0,
ReBUSY INT INTE PAUS STS1 STS0 STRT served MD1 MD0 ANS2 ANS1 ANS0 ANE2 ANE1 ANE0
ADCS1
0
1
0
Stores converted data.
ADCR S10 ST1 ST0 CT1 CT0
:
:
0 :
1 :
AICK
Used bit
Set the bit corresponding to the used pin to 1.
Set 1.
Set 0.
Note:
The following shows examples for the conversion sequences in continuous-conversion mode.
ANS = 000B, ANE = 011B: AN0 --> AN1 --> AN2 --> AN3 --> AN0 --> Repeat
ANS = 110B, ANE = 010B: AN6 --> AN7 --> AN0 --> AN1 -->AN2 --> AN6 --> Repeat
ANS = 011B, ANE = 011B: AN3 --> AN3 --> Repeat
■ Operation in Intermittent-conversion Mode
In intermittent-conversion mode, analog inputs from channels specified by the ANS bits and
ANE bits are converted with a temporary stop of each of the channels. After conversion is
performed for the end channel specified by the ANE bits, A/D conversion control returns to the
analog input channel specified by the ANS bits, and A/D conversion continues from the channel
that was temporarily stopped. When the start channel is the same as the end channel (ANS =
ANE), conversion is repeatedly performed only for the channel specified by the ANS bits. To
restart a conversion that was temporarily stopped, generate the start source specified by the
STS1 and STS0 bits. To operate the converter in intermittent-conversion mode, the setting
shown in Figure 13.6-3 is required.
Figure 13.6-3 Intermittent-conversion Mode Setting
bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
ADCS0,
ReADCS1 BUSY INT INTE PAUS STS1 STS0 STRT served MD1 MD0 ANS2 ANS1 ANS0 ANE2 ANE1 ANE0
0
1
ADCR S10 ST1 ST0 CT1 CT0
AICK
0
Stores converted data
:
:
0:
1:
Used bit
Set the bit corresponding to the used pin to 1.
Set 1.
Set 0.
Note:
The following shows examples for the conversion sequences in intermittent-conversion mode.
ANS = 000B, ANE = 011B: AN0 --> Temporary stop --> AN1 --> Temporary stop --> AN2 -->
Temporary stop --> AN0 --> Repeat
ANS = 110B, ANE = 001B: AN6 --> Temporary stop --> AN7 --> Temporary stop --> AN0 -->
Temporary stop --> AN1 --> Temporary stop --> AN6 --> Repeat
ANS = 011B, ANE = 011B: AN3 --> Temporary stop --> AN3 --> Temporary stop --> Repeat
294
CHAPTER 13 8/10-BIT A/D CONVERTER
13.7 A/D Converted Data Preservation Function
The converted data preservation function is executed when A/D conversion is
performed while interrupts are enabled.
■ A/D Converted Data Preservation Function
The A/D converter has only one data register for storing converted data. When A/D conversion
is performed, data stored in the data register is stored externally and rewritten at the end of
conversion. Therefore, if the converted data is not fully transferred to memory before the
converted data in the data register is rewritten, some of the data is lost. To cope with this
problem, the data preservation function is executed when interrupts are enabled (INTE = 1) as
described below.
When converted data is stored in the A/D data register (ADCR), the INT bit of A/D control status
register 1 (ADCS1) is set to 1. While this bit is 1, A/D conversion temporarily stops. When the
INT bit is cleared after the data in the A/D data register (ADCR) is transferred to memory within
the interrupt routine, the temporary stop is released.
Notes:
• The converted data preservation function operates only when interrupts are enabled (ADCS1:
INTE = 1).
• Restarting the converter while it is temporarily stopped might lead to corruption of the data on
standby.
295
CHAPTER 13 8/10-BIT A/D CONVERTER
13.8 Notes on Using the 8/10-bit A/D Converter
This section provides notes on using the 8/10-bit A/D converter.
■ Notes on Using the 8/10-bit A/D Converter
❍ Analog input pin
The A/D input pins are also used as I/O pins for port K. The pins are switched using the port K
direction register (DDRK) and analog input permission register (AICR). For a pin to be used for
analog input, set the DDRK bit corresponding to the pin to 0 to set the pin as the input port, then
specify the analog input mode using the AICR register to fix the input gate for the port. While
port input mode is set, the input leak current flows to the gate if an intermediate level signal is
inputted.
❍ Note on using the A/D converter with the internal timer
To start the A/D converter with the internal timer, specify the STS1 and STS0 bits of A/D control
status register 1 (ADCS1) and also set the value for internal timer inputs to inactive (L for the
internal timer). When it is set to active, the internal timer may start operating as soon as a write
operation to the ADCS register is performed.
❍ Priorities of A/D converter power and analog input
Be sure to apply the power to the A/D converter (AVCC, AVRH, AVRL) and analog input (AN0 to
AN7) after or as soon as the digital power supply (VCC) is turned on. Also, be sure to turn off
the digital power (VCC) after or as soon as the power to the A/D converter and analog input are
cut.
❍ Voltage of the A/D converter
To prevent a latch-up, set an A/D converter voltage (AVCC) that does not exceed the voltage of
the digital circuit (VCC).
296
CHAPTER 14 8-BIT D/A CONVERTER
CHAPTER 14
8-BIT D/A CONVERTER
This chapter provides an overview of the 8-bit D/A converter, the block diagram, the
configuration and functions of the registers, and the operation of the 8-bit D/A
converter.
14.1 Overview of the 8-bit D/A Converter
14.2 8-bit D/A Converter Block Diagram
14.3 8-bit D/A Converter Registers
14.4 8-bit D/A Converter Operation
297
CHAPTER 14 8-BIT D/A CONVERTER
14.1 Overview of the 8-bit D/A Converter
This 8-bit D/A converter supports a resolution of 8 bits and is an R-2R type D/A
converter.
■ Features of the 8-bit D/A Converter
The MB91151A contains a 3-channel D/A converter. The D/A control registers can control the
output of the three channels separately.
298
CHAPTER 14 8-BIT D/A CONVERTER
14.2 8-bit D/A Converter Block Diagram
The 8-bit D/A converter consists of the following three blocks:
• 8-bit resistance ladder
• Data registers
• Control registers
■ 8-bit D/A Converter Block Diagram
Figure 14.2-1 shows the 8-bit D/A converter block diagram.
Figure 14.2-1 8-bit D/A Converter Block Diagram
R-bus
DA27 to DA20
DA17 to DA10
DAVC
DA27
DA20
DA07 to DA00
DAVC
DA17
DA10
DAVC
DA07
DA00
DAE2
DAE1
DAE0
Standby control
Standby control
Standby control
D/A output
ch2
D/A output
ch1
D/A output
ch0
■ 8-bit D/A Converter Pins
The 8-bit D/A converter pins are exclusively used for the D/A converter.
299
CHAPTER 14 8-BIT D/A CONVERTER
14.3 8-bit D/A Converter Registers
Figure 14.3-1 lists the 8-bit D/A converter registers.
■ List of the 8-bit D/A Converter Registers
Figure 14.3-1 List of the 8-bit D/A Converter Registers
bit
DADR0 0000E3H
bit
DADR1 0000E2H
bit
6
5
4
3
2
1
DA06
DA05
DA04
DA03
DA02
DA01
15
14
13
12
11
10
9
DA17
DA16
DA15
DA14
DA13
DA12
DA11
23
22
21
20
19
18
17
DA27
DA26
DA25
DA24
DA23
DA22
DA21
bit
7
6
5
4
3
2
1
DACR0 0000DFH
−
−
−
−
−
−
−
15
14
13
12
11
10
9
−
−
−
−
−
−
−
23
22
21
20
19
18
17
−
−
−
−
−
−
−
DADR2 0000E1H
bit
DACR1 0000DEH
bit
DACR2 0000DDH
300
7
DA07
0
DA00 D/A data register 0
8
DA10 D/A data register 1
16
DA20 D/A data register 2
0
DAE0 D/A control register 0
8
DAE1 D/A control register 1
16
DAE2 D/A control register 2
CHAPTER 14 8-BIT D/A CONVERTER
14.3.1 D/A Control Registers (DACR0, DACR1, DACR2)
The D/A control registers (DACR0, DACR1, and DACR2) enable or disable D/A
converter output.
■ D/A Control Registers (DACR0, DACR1, DACR2)
The figure below shows the configuration of the D/A control registers (DACR0, DACR1,
DACR2).
bit
DACR0 0000DFH
bit
DACR1 0000DEH
bit
DACR2 0000DDH
7
6
5
4
3
2
1
0
−
−
−
−
−
−
−
DAE0
R/W
15
14
13
12
11
10
9
8
−
−
−
−
−
−
−
DAE1
R/W
23
22
21
20
19
18
17
16
−
−
−
−
−
−
−
DAE2
R/W
Initial value
-------0B
Initial value
-------0B
Initial value
-------0B
[bit0] DAE2, DAE1, DAE0
•
DAE2, DAE1, and DAE0 are used to control the output of ch2, ch1 and ch0, respectively.
•
When bit0 is set to 1, D/A output is enabled. When bit0 is set to 0, D/A output is disabled.
•
A reset initializes these bits to 0. These bits can be both read and written.
•
When output is disabled, the D/A converter output pins are set to the output level of 0.
301
CHAPTER 14 8-BIT D/A CONVERTER
14.3.2 D/A Data Registers (DADR2, DADR1, DADR0)
The D/A data registers (DADR2, DADR1, and DADR0) specify the D/A converter output
voltage.
■ D/A Data Registers (DADR2, DADR1, DADR0)
The figure below shows the configuration of the D/A data registers (DADR2, DADR1, DADR0).
bit
DADR0 0000E3H
bit
DADR1 0000E2H
bit
DADR2 0000E1H
7
6
5
4
3
2
1
0
DA07
R/W
DA06
R/W
DA05
R/W
DA04
R/W
DA03
R/W
DA02
R/W
DA01
R/W
DA00
R/W
15
14
13
12
11
10
9
8
DA17
R/W
DA16
R/W
DA15
R/W
DA14
R/W
DA13
R/W
DA12
R/W
DA11
R/W
DA10
R/W
23
22
21
20
19
18
17
16
DA27
R/W
DA26
R/W
DA25
R/W
DA24
R/W
DA23
R/W
DA22
R/W
DA21
R/W
DA20
R/W
Initial value
XXXXXXXXB
Initial value
XXXXXXXXB
Initial value
XXXXXXXXB
[bit23 to bit16] DA27 to DA20
•
These bits are used to set the output voltage of D/A converter ch2.
•
A reset does not initialize these bits. These bits can be both read and written.
[bit15 to bit8] DA17 to DA10
•
These bits are used to set the output voltage of D/A converter ch1.
•
A reset does not initialize these bits. These bits can be both read and written.
[bit7 to bit0] DA07 to DA00
302
•
These bits are used to set the output voltage of D/A converter ch0.
•
A reset does not initialize these bits. These bits can be both read and written.
CHAPTER 14 8-BIT D/A CONVERTER
14.4 8-bit D/A Converter Operation
D/A output starts by setting the D/A output value in the D/A data register (DADR) and
setting the permission bit for the D/A output channel in the D/A control register
(DACR) to 1.
■ Operation of the 8-bit D/A Converter
When D/A output is disabled, the analog switches in the output blocks of the D/A converter
channels are turned off. The D/A converter is also internally cleared to an output state of 0, and
the direct current routes are cut off. This operation is also performed in the stop mode.
This D/A converter does not have a built-in buffer amplifier for its output. In addition, an analog
switch (nearly equal to 100 Ω) is connected to its output in series. For external output load,
always take the required settling time into consideration.
The D/A converter output voltage ranges from 0 V to 255/256 × DAVC. External adjustments to
the DAVC voltage change the output voltage range.
Table 14.4-1 shows the logical values of the D/A converter output voltages.
Table 14.4-1 Logical Values of the 8-bit D/A Converter Output Voltages
Values specified in
DA07 to DA00
DA17 to DA10
DA27 to DA20
8-bit D/A converter
00H
0/256 × DAVC (=0V)
01H
1/256 × DAVC
02H
2/256 × DAVC
:
:
FDH
253/256 × DAVC
FEH
254/256 × DAVC
FFH
255/256 × DAVC
303
CHAPTER 14 8-BIT D/A CONVERTER
304
CHAPTER 15 UART
CHAPTER 15
UART
This chapter describes the overview of the UART, its block diagram, its pin, the
configuration and functions of UART registers, and UART operations.
15.1 Overview of the UART
15.2 UART Block Diagram
15.3 UART Pins
15.4 UART Registers
15.5 Interrupts
15.6 Receive-Interrupt Generation and Flag Set Timing
15.7 Send-Interrupt Generation and Flag Set Timing
15.8 Baud Rate
15.9 UART Operations
15.10 Notes on Using UART
305
CHAPTER 15 UART
15.1 Overview of the UART
The UART is a general-purpose serial data communication interface for synchronous
or asynchronous communication (start-stop synchronization) with external devices.
The UART has an ordinary bidirectional communication function (normal mode) and a
master/slave-type communication function (multiprocessor mode: Only the master is
supported).
■ UART Functions
❍ UART functions
The UART is a general-purpose serial data communication interface that sends serial data to
and receives serial data from other CPUs and peripheral devices. The UART has the functions
listed in Table 15.1-1.
Table 15.1-1 UART Functions
Function
Data buffer
Full-duplex double buffer
Transfer mode
•
•
Synchronous with the clock (without start/stop bits)
Asynchronous with the clock (start-stop synchronization cycle)
Baud rate
•
•
•
A dedicated baud-rate generator is provided. One of eight
types can be selected.
External clock input enabled
Internal clock (An internal clock whose pulses are supplied
from the 16-bit reload timer that corresponds to each channel
can be used.)
Data length
•
•
7 bits (only in asynchronous normal mode)
8 bits
Signal method
Non Return to Zero (NRZ) method
Receive-error detection
•
•
•
Framing error
Overrun error
Parity error (disabled in multiprocessor mode)
Interrupt request
•
Receive interrupt (receiving completed, receive-error
detection)
Send interrupt (sending completed)
•
Master/slave-type
communication function
(multiprocessor mode)
Enables 1-to-n (master-to-slaves) communication.
(Only the master is supported.)
Note:
The UART appends neither a start bit nor stop bit and transfers only the data itself during clock
synchronous transfer.
306
CHAPTER 15 UART
Table 15.1-2 lists the UART operation modes.
Table 15.1-2 UART Operation Modes
Data length
Operation mode
Without
parity
With
parity
7 bits or 8 bits
Synchronization
method
Asynchronous
Stop-bit length
0
Normal mode
1
Multiprocessor mode
2
Normal mode
-:
*1:
*2:
Setting is not allowed.
+1 is the address/data selection bit (A/D) used for communication control.
Only a single bit can be detected as stop bit during reception.
8 + 1 *1
-
Asynchronous
8
-
Synchronous
1 bit or 2 bits *2
None
307
CHAPTER 15 UART
15.2 UART Block Diagram
Figure 15.2-1 shows a block diagram of UART.
■ UART Block Diagram
Figure 15.2-1 UART Block Diagram
Control bus
Receive-interrupt
signal
#26 to #29*
Dedicated
baud rate
generator
16-bit reload
timer
Send-interrupt
signal
#31 to #34*
Send clock
Clock
selector
Receive clock
Pins
<SCK0 to SCK3>
Receivecontrol circuit
Send-control
circuit
Start bit detection
circuit
Send-start
circuit
Receive-bit
counter
Send-bit
counter
Receive-parity
counter
Send-parity
counter
<SOT0 to SOT3>
Pins
<SIN0 to SIN3>
Receive-shift
register
Pins
Receive-status
identification circuit
SIDR0 to SIDR3
Send-shift
register
Receive
end
SODR0 to SODR3
Send
start
Receive error
Generation signal
(to CPU)
Internal data bus
SMR0 to
SMR3
register
MD1
MD0
CS2
CS1
CS0
SCKE
SOE
*: Interrupt number
308
SCR0 to
SCR3
register
PEN
P
SBL
CL
A/D
REC
RXE
TXE
SSR0 to
SSR3
register
PE
ORE
FRE
RDRF
TDRE
BDS
RIE
TIE
CHAPTER 15 UART
The following describes the function of each block.
❍ Clock selector
The clock selector selects the send and receive clocks from the dedicated baud-rate generator,
external input clock, and internal clock (clock supplied from the 16-bit reload timer).
❍ Receive control circuit
The receive control circuit consists of the receive-bit counter, start-bit detection circuit, and
receive-parity counter. The receive-bit counter counts receive data and, after reception of one
data unit is completed, generates a receive-interrupt request in accordance with the set-data
length. The start-bit detection circuit detects a start bit in the serial-input signal and, if a start bit
is detected, writes data to the SIDR0 to SIDR3 register while shifting in accordance with the
specified transfer speed. The receive-parity counter calculates the parity of receive data.
❍ Send-control circuit
The send-control circuit consists of the send-bit counter, send-start circuit, and send-parity
counter. The send-bit counter counts send data and, when sending of one data unit is
completed, generates a send-interrupt request in accordance with the set data length. The
send-start circuit starts a send operation when SODR0 to SODR3 is written. The send-parity
counter generates the parity bit of send data when parity is enabled.
❍ Receive-shift register
The receive-shift register fetches the receive data, which is inputted from the SIN pins, while
shifting the data in steps of one bit. When reception terminates, the receive data is transferred
from the receive-shift register to the SIDR0 to SIDR3 register.
❍ Send-shift register
The send-shift register transfers the data written in SODR0 to SODR3 to the send-shift register
and outputs the data to the SOT pins while shifting the data in steps of one bit.
❍ Mode register 1 (SMR0 to SMR3)
This register selects the operation mode, selects the clock-input source, sets the dedicated
baud-rate generator, and selects the clock rate (clock divide-by value) for using the dedicated
baud-rate generator. It also sets serial data output to pin enabled or disabled and sets clock
output to pin enabled or disabled.
❍ Control register 1 (SCR0 to SCR3)
This register sets parity to enabled or disabled, selects the parity, sets the stop-bit length, sets
the data length, selects the frame data format in mode 1, and clears the flag. It also sets
sending to enabled or disabled and sets receiving to enabled or disabled.
❍ Status register 1 (SSR0 to SSR3)
This register checks the send, receive, and error statuses and sets send- and receive-interrupt
request enabled/disabled.
❍ Input-data register 1 (SIDR0 to SIDR3)
This register retains the receive data. Serial input is converted and stored in this register.
❍ Output-data register 1 (SODR0 to SODR3)
This register sets the send data. The data written in this register undergoes parallel-to-serial
conversion and is outputted.
309
CHAPTER 15 UART
15.3 UART Pins
This section describes the UART pins and provides pin block diagrams.
■ UART Pins
UART pins can also be used as general-purpose ports. Table 15.3-1 shows the pin functions,
input-output format, and settings for using the UART.
Table 15.3-1 UART Pins (1 / 2)
Pin name
Pin
function
PH0/SIN0
Port H inputoutput/serial
data input
PH1/SOT0
Port H inputoutput/serial
data output
PH2/SCK0/
T00
Port H inputoutput/serial
clock inputoutput
PH3/SIN1
Port H inputoutput/serial
data input
PH4/SOT1
Port H inputoutput/serial
data output
PH5/SCK1/
T01
310
Port H inputoutput/serial
clock inputoutput
Inputoutput
format
Pull-up
selection
Standby
control
Opendrain
control
Settings necessary for
using the pins
Set to input port
(DDRH: bit0 = 0)
CMOS
output/
CMOS
hysteresis
input
Set to output enabled
(SMR0: SOE = 1)
Available
Available
Available
Set to input port at clock
input (DDRH: bit2 = 0)
Set to output enabled at
clock output (SMR0:
SCKE = 1)
Set to input port
(DDRH: bit3 = 0)
CMOS
output/
CMOS
hysteresis
input
Set to output enabled
(SMR1: SOE = 1)
Available
Available
Available
Set to input port at clock
input (DDRH: bit5 = 0)
Set to output enabled at
clock output (SMR1:
SCKE = 1)
CHAPTER 15 UART
Table 15.3-1 UART Pins (2 / 2)
Pin name
Pin
function
PI0/SIN2
Port I inputoutput/serial
data input
PI1/SOT2
Port I inputoutput/serial
data output
PI2/SCK2/
T02
Port I inputoutput/serial
clock inputoutput
PI3/SIN3
Port I inputoutput/serial
data input
PI4/SOT3
Port I inputoutput/serial
data output
PI5/SCK3/
T03
Port I inputoutput/serial
clock inputoutput
Inputoutput
format
Pull-up
selection
Standby
control
Opendrain
control
Settings necessary for
using the pins
Set to input port
(DDRI: bit0 = 0)
CMOS
output/
CMOS
hysteresis
input
Set to output enabled
(SMR2: SOE = 1)
Available
Available
Available
Set to input port at clock
input (DDRI: bit2 = 0)
Set to output enabled at
clock output (SMR2:
SCKE = 1)
Set to input port
(DDRI: bit3 = 0)
CMOS
output/
CMOS
hysteresis
input
Set to output enabled
(SMR3: SOE = 1)
Available
Available
Available
Set to input port at clock
input (DDRI: bit5 = 0)
Set to output enabled at
clock output (SMR3:
SCKE = 1)
311
CHAPTER 15 UART
■ UART Pin Block Diagram
Figure 15.3-1 shows a block diagram of UART pins.
Figure 15.3-1 UART Pin Block Diagram
Data Bus
Resource input
0
1
PDR read
pin
0
PDR
DDR
Resource
1
output
Resource
output enabled
OCR
PCR
PDR : Port Data Register
DDR : Data Direction Register
OCR: OpenDrain Control Register
PCR : Pull-up Control Register
312
CHAPTER 15 UART
15.4 UART Registers
Figure 15.4-1 shows the configuration of the UART registers.
■ UART Registers
Figure 15.4-1 UART Registers
Address
bit 15 ...................................... bit 8
bit 7 ........................................bit 0
ch0:00001EH,00001FH
ch1:000022H,000023H
ch2:000026H,000027H
ch3:00002AH,00002BH
SCR (control register)
SMR (mode register)
ch0:00001CH,00001DH
ch1:000020H,000021H
ch2:000024H,000025H
ch3:000028H,000029H
SSR (status register)
SIDR/SODR
(input-output data register)
ch0:00004EH
ch1:00004CH
ch2:000052H
ch3:000050H
CDCR
(communication prescaler
control register)
Unoccupied
313
CHAPTER 15 UART
15.4.1 Control register (SCR0 to SCR3)
The control register (SCR0 to SCR3) sets the parity, selects the stop-bit length and
data length, selects the frame data format in mode 1, clears the receive-error flag, and
sets send- and receive-operations to enabled or disabled.
■ Control Register (SCR0 to SCR3)
The configuration of the control register (SCR0 to SCR3) is shown below.
Figure 15.4-2 Control Register (SCR0 to SCR3)
Address
bit15
ch0: 0000_001EH
PEN
ch1: 0000_0022H
R/W
ch2: 0000_0026H
ch3: 0000_002AH
R/W: Read/write enabled
W: Write only
bit14
bit13
bit12
bit11
bit10
bit9
bit8
bit7.............bit0
P
SBL
CL
A/D
REC
RXE
TXE
(SMR)
R/W
R/W
R/W
R/W
W
R/W
R/W
TXE
Send-operation enable bit
CL
0
Send operation is disabled
0
7 bits
1
Send operation is enabled
1
8 bits
Data-length selection bit
RXE
Receive-operation enable bit
SBL
0
Receive operation is disabled
0
1-bit length
1
Receive operation is enabled
1
2-bit length
REC
Clears the FRE, ORE, and PE flags
1
Does not change, does not affect
other operations
Address/data selection bit
0
Data frame
1
Address frame
0 , 1 : The underline indicates an initial value.
Stop-bit length selection bit
Parity selection bit
Receive-error flag-clear bit
0
A/D
314
Initial value 00000100B
P
Only (PEN = 1) is valid when parity
is enabled
0
Even-number parity
1
Odd-number parity
PEN
Send-enable bit
0
Without parity
1
With parity
CHAPTER 15 UART
[bit15] PEN (Parity enable bit)
This bit selects whether to add a parity bit to serial data (for sending). This bit selects
whether to detect a parity bit (for receiving) within the serial data.
Note: When operation mode 1 or 2 is selected, parity cannot be used. Always set this bit to
0.
[bit14] P (Parity selection bit)
This bit selects odd parity or even parity when parity is enabled (PEN = 1).
[bit13] SBL (Stop-bit-length selection bit)
This bit selects the bit length of the stop bit, which is a frame-end mark for the send data in
asynchronous transfer mode.
Note: Only one bit is detected as stop bit at reception.
[bit12] CL (Data-length selection bit)
This bit specifies the data length of the send and receive data.
Note: Bit7 can be selected only in operation mode 0 (asynchronous). Bit8 (CL = 1) must be
selected in operation mode 1 (multiprocessor mode) and operation mode 2
(synchronous).
[bit11] A/D (Address/data selection bit)
•
This bit specifies the data format of frames to be sent and received in multiprocessor mode
(mode 1).
•
When this bit is 0, ordinary data is selected. When this bit is 1, address data is selected.
[bit10] REC (Receive-error flag-clear bit)
•
This bit clears the FRE, ORE, and PE flags of the status register (SSR).
•
When this bit is set to 0, the FRE, ORE, and PE flags are cleared. When this bit is set to 1,
the flags do not change and other operations are not affected.
Note: Clear the REC bit only when the FRE, ORE, or PE flag is 1 in receive interrupt
enabled status during UART operation.
[bit9] RXE (Receive-operation enable bit)
•
This bit controls the UART receive operation.
•
When this bit is 0, the receive operation is disabled. When this bit is 1, the receive operation
is enabled.
Note: If the receive operation is disabled during reception, the receive operation stops when
reception of the frame is completed and receive data is stored in the receive data
buffer (SIDR0 to SIDR3).
[bit8] TXE (Send-operation enable bit)
•
This bit controls the UART send operation.
•
When this bit is 0, the send operation is disabled. When this bit is 1, the send operation is
enabled.
Note: If the send operation is disabled during sending, the send operation stops after the
send-data buffer (SODR0 to SODR3) runs out of data. When data is written to SODR0
to SODR3, wait a specified period of time before setting this bit to "0". In clock
asynchronous transfer mode, this specified period of time is 1/16 of the baud rate; in
clock synchronous transfer mode, it is the baud rate.
315
CHAPTER 15 UART
15.4.2 Mode register (SMR0 to SMR3)
The mode register (SMR0 to SMR3) selects the operation mode, selects the baud-rate
clock, and sets serial data and clock output to pin enabled or disabled.
■ Mode Register (SMR0 to SMR3)
The configuration of the mode register (SMR0 to SMR3) is shown below.
Figure 15.4-3 Mode Register (SMR0 to SMR3)
Address
bit15...........bit8
ch0: 0000_001FH
(SCR)
ch1: 0000_0023H
ch2: 0000_0027H
ch3: 0000_002BH
R/W: Read/write enabled
SOE
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
MD1
MD0
CS2
CS1
CS0
−
SCKE
SOE
R/W
R/W
R/W
R/W
R/W
−
R/W
R/W
Initial value
Serial data output-enable bit
0
Sets to general-purpose input-output port
1
Sets to UART serial data output pins
SCKE
Serial clock output-enable bit
0
Sets to general-purpose input-output port or UART clock-input pin
1
Sets to UART clock output pins
CS2 to CS0
"000B" to "101B"
Clock selection bit
Baud rate based on the dedicated baud-rate generator
"110B"
Baud rate based on the internal timer (16-bit reload timer)
"111B"
Sets to UART clock output pins
Operation mode selection bit
MD1
MD0
Clock selection bit
0
0
0
Asynchronous (normal mode)
0
1
1
Asynchronous (multiprocessor mode)
1
0
2
Synchronous (normal mode)
1
1
Setting is prohibited
0 , 1 : The underline indicates an initial value.
316
00000-00B
CHAPTER 15 UART
[bit7, bit6] MD1, MD0 (Operation mode selection bit)
•
These bits select the operation mode.
Note: In operation mode 1 (multiprocessor mode), these bits can only be used at the side of
the master in master-slave-type communication. These bits cannot be used in the
slave unit because the UART does not have a function for distinguishing between the
address and the data at reception.
[bit5, bit4, bit3] CS2 to CS0 (Clock selection bit)
•
These bits select the baud-rate clock source. When the dedicated baud-rate generator is
selected, the baud rate is determined simultaneously.
•
When the dedicated baud-rate generator is selected, one of a total of eight baud rates can
be selected, five of them for asynchronous transfer mode and three types for synchronous
transfer mode.
•
The clock input can be selected from the external clock (SCK0 to SCK3 pin), 16-bit reload
timer, and dedicated baud-rate generator.
[bit2] Unused bit
Unused
[bit1] SCKE (Serial clock output-enable bit)
•
This bit controls serial clock input and output.
•
When this bit is set to 0, the SCK0 to SCK3 pins become general-purpose input-output ports
or serial clock input pins. When this bit is set to 1, the SCKn pins become serial clock output
pins.
Notes:
1. When using the SCK0 to SCK3 pins as serial clock input pins (SCKE=0), set the
corresponding port to be an input port. Also, select the external clock by the
clock selection bits (SMR0 to SMR3: CS2 to CS0 = 111B).
2. When using the SCK0 to SCK3 pins as serial clock output pins (SCKE=1), select
a clock other than the external clock (SMR0 to SMR3: CS2 to CS0 = other than
111B).
3. The condition that serial clock output is enabled (SCKE=1) is permitted only by
the synchronous transfer.
Note: When serial clock output is enabled (SCKE=1), the SCK0 to SCK3 pins function as
serial clock output pins regardless of the general-purpose input-output port status.
[bit0] SOE (Serial data output-enable bit)
•
This bit enables or disables serial data output.
•
When this bit is set to 0, the SOTn pins become general-purpose input-output ports. When
this bit is set to 1, the SOTn pins become serial data output pins (SOT0 to SOT3).
Note: When serial data output is enabled (SOE=1), the SOTn pins function as SOT0 to
SOT3 pins regardless of the general-purpose input-output port status.
317
CHAPTER 15 UART
15.4.3 Status register (SSR0 to SSR3)
The status register (SSR0 to SSR3) is used to check the send, receive, and error
statuses and sets interrupt enabled or disabled.
■ Status Register (SSR0 to SSR3)
The configuration of the status register (SSR0 to SSR3) is shown below.
Figure 15.4-4 Status Register (SSR0 to SSR3)
Address
bit15
ch0: 0000_001CH
PE
ch1: 0000_0020H
R
ch2: 0000_0024H
ch3: 0000_0028H
R/W: Read/write enabled
R: Read only
TIE
bit14
bit13
bit12
bit11
bit10
bit9
bit8
bit7.............bit0
ORE
FRE
RDRF TDRE
BDS
RIE
TIE
(SIDR/SODR)
R
R
R/W
R/W
R/W
R
R
Send-interrupt request enable bit
Initial value
RDRF
00001000B
Receive data full flag bit
0
Disables send-interrupt request output
0
Without receive data
1
Enables send-interrupt request output
1
With receive data
RIE
Receive-interrupt request enable bit
FRE
Framing error flag bit
0
Disables receive-interrupt request output
0
Without framing error
1
Enables receive-interrupt request output
1
With framing error
BDS
Transfer direction selection bit
ORE
Overrun error flag bit
0
LSB first (transfer begins from the least significant bit)
0
Without overrun error
1
MSB first (transfer begins from the most significant bit)
1
With overrun error
PE
Parity error flag bit
TDRE Send data empty flag bit
0
With send data (disables send data to be written)
0
Without parity error
1
Without send data (enables send data to be written)
1
With parity error
0 , 1 : The underline indicates an initial value.
[bit15] PE (Parity error flag bit)
318
•
If a parity error occurs at reception, this bit is set to 1. When the REC bit of the control
register (SCR0 to SCR3) is set to 0, this bit is cleared.
•
When this bit and the RIE bit are 1, a receive-interrupt request is outputted.
•
When this flag is set, data in the input-data register (SIDR0 to SIDR3) is invalid.
CHAPTER 15 UART
[bit14] ORE (Overrun error flag bit)
•
If an overrun occurs at reception, this bit is set to 1. When the REC bit of the control register
(SCR0 to SCR3) is set to 0, this bit is cleared to 0.
•
When this bit and the RIE bit are 1, a receive-interrupt request is outputted.
•
When this flag is set, data in the input-data register (SIDR0 to SIDR3) is invalid.
[bit13] FRE (Framing error flag bit)
•
If a framing error occurs at reception, this bit is set to 1. When the REC bit of the control
register (SCR0 to SCR3) is set to 0, this bit is cleared to 0.
•
When this bit and the RIE bit are 1, a receive-interrupt request is outputted.
•
When this flag is set, data in the input-data register (SIDR0 to SIDR3) is invalid.
[bit12] RDRF (Receive data full flag bit)
•
This bit indicates the status of the input-data register (SIDR0 to SIDR3).
•
When receive data is loaded into SIDR0 to SIDR3, this bit is set to 1. When the SIDR0 to
SIDR3 is read, this bit is cleared to 0.
•
When this bit and the RIE bit are 1, a receive-interrupt request is outputted.
[bit11] TDRE (Send data empty flag bit)
•
This bit indicates the status of the output-data register (SODR0 to SODR3).
•
When send data is written into SODR0 to SODR3, this bit is cleared to 0. When data is
loaded into the send-shift register and sending starts, this bit is set to 1.
•
When this bit and the TIE bit are 1, a send-interrupt request is outputted.
Note: In the initial status, this bit is set to 1 (SODR0 to SODR3 unoccupied).
[bit10] BDS (Transfer direction selection bit)
•
This bit selects whether to begin transferring serial data from the least significant bit (LSB
first, BDS = 0) or from the most significant bit (MSB first, BDS = 1).
Note: If this bit is rewritten after data is written into the SIDR0 to SIDR3 register, the data
becomes invalid. This is because the high-order bits and low-order bits of the data are
swapped during read and write accesses to the serial data register.
[bit9] RIE (Receive-interrupt request enable bit)
•
This bit enables or disables output of receive-interrupt requests to the CPU.
•
When this bit and the receive data flag bit (RDRF) bit are 1 or when this bit and one or more
of the error flag bits (PE, ORE, and FRE) are 1, a receive-interrupt request is outputted.
[bit8] TIE (Send-interrupt request enable bit)
•
This bit enables/disables send-interrupt requests to be outputted to the CPU.
•
When this bit and the TDRE bit are 1, a send-interrupt request is outputted.
319
CHAPTER 15 UART
15.4.4 Input-data register (SIDR0 to SIDR3), Output-data register
(SODR0 to SODR3)
The input-data register (SIDR0 to SIDR3) is for receiving serial data. The output-data
register (SODR0 to SODR3) is for sending serial data. The SIDR0 to SIDR3 and SODR0
to SODR3 registers are located at the same address.
■ Input-data Register (SIDR0 to SIDR3)
The configuration of the input-data register (SIDR0 to SIDR3) is shown below.
Address
ch0: 0000_001DH
ch1: 0000_0021H
ch2: 0000_0025H
ch3: 0000_0029H
R: Read only
X: Undetermined
bit15..........bit8
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
D7
D6
D5
D4
D3
D2
D1
D0
R
R
R
R
R
R
R
R
Initial value
XXXXXXXXB
Received data is stored in this register. The shift register converts the serial data signal sent to
the SIN0 to SIN3 pins. The converted data is stored in this register. When the data length is 7
bits, the high-order bit (D7) contains invalid data. When the receive data is stored in this
register, the receive data full flag bit (SSR0 to SSR3: RDRF) is set to 1. If receive-interrupt
request is enabled, a receive interrupt occurs.
Read the SIDR0 to SIDR3 when the RDRF bit of the status register (SSR0 to SSR3) is 1. The
RDRF bit is automatically cleared to 0 when the SIDR0 to SIDR3 is read. If a receive error
occurs (SSR0 to SSR3: If PE, ORE, or FRE is 1), the SIDR0 to SIDR3 data becomes invalid.
■ Output-data Register (SODR0 to SODR3)
The configuration of the output-data register (SODR0 to SODR3) is shown below.
Address
ch0: 0000_001DH
ch1: 0000_0021H
ch2: 0000_0025H
ch3: 0000_0029H
W: Write only
X: Undetermined
bit15..........bit8
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
D7
D6
D5
D4
D3
D2
D1
D0
W
W
W
W
W
W
W
W
Initial value XXXXXXXXB
When send data is written to this register in send-enabled status, the send data is transferred to
the send-shift register, is converted into serial data, and is sent out from the serial data output
pins (SOT0 to SOT3 pins). When the data length is 7 bits, the high-order bit (D7) contains
invalid data.
When the send data is written to this register, the send data empty flag (SSR0 to SSR3: TDRE)
320
CHAPTER 15 UART
is cleared to 0. When the transfer to the send-shift register terminates, the flag is set to 1.
When the TDRE bit is 1, the next send data can be written. If send-interrupt request output is
enabled, a send interrupt occurs. The next send data should be written when a send interrupt
occurs or when the TDRE bit is 1.
Note:
The SODR0 to SODR3 is a write-only register and the SIDR0 to SIDR3 is a read-only register. The
write value and read value are different because these registers are located at the same address.
Therefore, instructions that perform the read-modify-write (RMW) operation cannot be used.
321
CHAPTER 15 UART
15.4.5 Communication prescaler control register (CDCR)
The communication prescaler control register (CDCR) controls division of the machine
clock.
■ Communication Prescaler Control Register (CDCR)
The UART operation clock is obtained by dividing the machine clock. This communication
prescaler is designed to obtain a fixed baud rate for machine cycles. The configuration of the
communication prescaler control register (CDCR) is shown below.
Address
bit15
ch0: 0000_004EH
MD
ch1: 0000_004CH
R/W
ch2: 0000_0052H
ch3: 0000_0050H
R/W: Read/write enabled
bit14
bit13
bit12
bit11
bit10
bit9
bit8
−
−
−
DIV3
DIV2
DIV1
DIV0
−
−
−
R/W
R/W
R/W
R/W
[bit15] MD (Machine clock device mode select)
This is the communication prescaler operation enable bit.
0: The communication prescaler stops.
1: The communication prescaler operates.
322
Initial value 0---0000B
CHAPTER 15 UART
[bit11 to bit8] DIV3 to DIV0 (DIVide 3 to 0)
The machine clock division ratio is determined in accordance with Table 15.4-1.
Table 15.4-1 Communication Prescaler
MD
DIV3
DIV2
DIV1
DIV0
div
0
-
-
-
-
Stop
1
0
0
0
0
1
1
0
0
0
1
2
1
0
0
1
0
3
1
0
0
1
1
4
1
0
1
0
0
5
1
0
1
0
1
6
1
0
1
1
0
7
1
0
1
1
1
8
1
1
0
0
0
9
1
1
0
0
1
10
1
1
0
1
0
11
1
1
0
1
1
12
1
1
1
0
0
13
1
1
1
0
1
14
1
1
1
1
0
15
1
1
1
1
1
16
Notes:
• After the division ratio has been changed, wait two cycles for the clock to stabilize before
performing communication.
• When the dedicated baud rate generator is used at synchronous transmitting, the following
settings are prohibited;
- CS2 to CS0=000B
- CS2 to CS0=001B and DIV3 to DIV0=0000B
323
CHAPTER 15 UART
15.5 Interrupts
The UART has receive interrupts and send interrupts. Interrupt requests are generated
in the following cases:
• When receive data is set in the input-data register (SIDR0 to SIDR3) or when a
receive error occurs
• When send data is transferred from the output-data register (SODR0 to SODR3) to
the send-shift register
■ UART Interrupts
Table 15.5-1 shows the UART interrupt control bit and interrupt sources.
Table 15.5-1 UART Interrupt Control Bit and Interrupt Sources
Interrupt
request
flag bit
Send or
receive
Receive
Send
Operation mode
Interrupt source
0
1
2
RDRF
o
o
o
Receive data is loaded
into the buffer (SIDR0
to SIDR3)
ORE
o
o
o
An overrun error
occurs
FRE
o
o
x
A framing error occurs
PE
o
x
x
A parity error occurs
TDRE
o
o
o
Send buffer (SODR0
to SODR3) is empty
Interrupt
source
enable bit
Interrupt
request flag
clear
Receive data is
read
SSR0 to
SSR3: RIE
The receiveerror flag-clear
bit (SCR0 to
SCR3: REC) is
set to 0
SSR0 to
SSR3: TIE
Send data is
written
o: Used bit
x: Unused bit
❍ Receive interrupt
In receive mode, if data reception is completed (SSR0 to SSR3: RDRF), if an overrun error
occurs (SSR0 to SSR3: ORE), if a framing error occurs (SSR0 to SSR3: FRE), or if a parity
error occurs (SSR0 to SSR3: PE), the corresponding flag bit is set to 1. If the receive interrupt
is enabled (SSR0 to SSR3: RIE = 1) when any of these flag bits is 1, a receive-interrupt request
is outputted to the interrupt controller.
The receive data full flag (SSR0 to SSR3: RDRF) is automatically cleared to 0 when the inputdata register (SIDR0 to SIDR3) is read. When the REC bit of the control register (SCR0 to
SCR3) is set to 0, the receive-error flags (SSR0 to SSR3: PE, ORE, FRE) are cleared to 0.
❍ Send interrupt
When send data is transferred from the output-data register (SODR0 to SODR3) to the transfer
shift register, the TDRE bit of the status register (SSR0 to SSR3) is set to 1. If the send
interrupt is enabled (SSR0 to SSR3: TIE = 1), a send-interrupt request is outputted to the
interrupt controller.
324
CHAPTER 15 UART
■ UART-related Interrupts
Table 15.5-2 lists the UART-related interrupts.
Table 15.5-2 UART-related Interrupts
Interrupt source
Interrupt
number
Interrupt control
register
Vector table address
Register
name
Address
Offset
TBR default
address
UART0 receive
interrupt
#26 (1AH)
ICR10
00040AH
394H
000FFF94H
UART1 receive
interrupt
#27 (1BH)
ICR11
00040BH
390H
000FFF90H
UART2 receive
interrupt
#28 (1CH)
ICR12
00040CH
38CH
000FFF8CH
UART3 receive
interrupt
#29 (1DH)
ICR13
00040DH
388H
000FFF88H
UART0 send interrupt
#31 (1FH)
ICR15
00040FH
380H
000FFF80H
UART1 send interrupt
#32 (20H)
ICR16
000410H
37CH
000FFF7CH
UART2 send interrupt
#33 (21H)
ICR17
000411H
378H
000FFF78H
UART3 send interrupt
#34 (22H)
ICR18
000412H
374H
000FFF74H
325
CHAPTER 15 UART
15.6 Receive-Interrupt Generation and Flag Set Timing
The receive interrupts are interrupts indicating receive completion (SSR0 to SSR3:
RDRF) and receive-error generation (SSR0 to SSR3: PE, ORE, FRE).
■ Receive-interrupt Generation and Flag Set Timing
When the stop bit is detected (in operation modes 0 to 4) or when the final bit (D7) of the data is
detected (in operation mode 2) during reception, the receive data is stored in input-data register
1 (SIDR0 to SIDR3). In case of a receive error, the error flag (SSR0 to SSR3: PE, ORE, FRE)
is set. After this, the receive data full flag (SSR0 to SSR3: RDRF) is set to 1. In each mode, the
SIDR0 to SIDR3 value is invalid when the error flag is 1.
❍ Operation mode 0 (asynchronous, normal mode)
When the stop bit is detected, the RDRF is set to 1. When a receive error occurs, the error flag
(PE, ORE, FRE) is set.
❍ Operation mode 1 (asynchronous, multiprocessor mode)
When the stop bit is detected, the RDRF is set to 1. When a receive error occurs, the error flag
(ORE, FRE) is set. Parity errors cannot be detected.
❍ Operation mode 2 (synchronous, normal mode)
When the final bit (D7) of receive data is detected, the RDRF is set to 1. If a receive error
occurs, the error flag (ORE) is set. Parity errors and framing errors cannot be detected. Figure
15.6-1 shows the receive operation and flag set timing.
Figure 15.6-1 Receive Operation and Flag Set Timing
Receive data
(Operation mode 0)
ST
D0
D1
D5
D6
D7/P
SP
Receive data
(Operation mode 1)
ST
D0
D1
D6
D7
A/D
SP
D0
D1
D4
D5
D6
D7
Receive data
(Operation mode 2)
PE, ORE, FRE*
RDRF
*: The PE flag cannot be used in mode 1.
The PE and FRE flags cannot be used in mode 2.
ST: Start bit
SP: Stop bit
A/D: Mode 2 (multiprocessor mode) address/data selection bit
Receive-interrupt generation
❍ Timing of receive-interrupt generation
A receive-interrupt request is issued immediately after the RDRF, PE, ORE, or FRE flag is set to
1 while receive interrupts are enabled (SSR0 to SSR3: RIE = 1).
326
CHAPTER 15 UART
15.7 Send-Interrupt Generation and Flag Set Timing
A send interrupt is generated when the output-data register (SODR0 to SODR3)
enables the next unit of data to be written.
■ Send-interrupt Generation and Flag Set Timing
When data from the output-data register (SODR0 to SODR3) is transferred to the send-shift
register and writing of the next unit of data is enabled, the send data empty flag bit (SSR0 to
SSR3: TDRE) is set to 1. When the send data is written to the SODR0 to SODR3, the TDRE is
cleared to 0. Figure 15.7-1 shows the send operation and flag set timing.
Figure 15.7-1 Send Operation and Flag Set Timing
[Operation modes 0, 1]
Send-interrupt generation
Send-interrupt generation
SODR write
TDRE
ST
SOUT output
[Operation mode 2]
D0
D1
D2
D3
D4
Send-interrupt generation
D5
D6
D7
SP SP
A/D
ST
D0
D1
D2
D3
D3
D4
D5
D6
D7
Send-interrupt generation
SODR write
TDRE
SOUT output
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
ST: Start bit
D0-D7: Data bits
SP: Stop bit
A/D: Address/data selection bit
❍ Timing of send-interrupt request generation
A send-interrupt request is issued immediately after the TDRE flag is set to 1 while send
interrupts are enabled (SSR0 to SSR3: TIE = 1).
Note:
A send completion interrupt is generated immediately when the send interrupt is enabled (TIE = 1)
because the initial status of the TDRE bit is 1. The TDRE bit is read-only and can only be cleared
when new data is written to the output-data register (SODR0 to SODR3). So, be careful with the
timing for enabling send interrupts.
327
CHAPTER 15 UART
15.8 Baud Rate
The UART send and receive clocks can be selected from any of the following.
• Dedicated baud-rate generator
• Internal clock (16-bit reload timer)
• External clock (SCK pin input clock)
■ UART Baud-rate Selection
The baud-rate selection circuit consists of blocks as shown Figure 15.8-1. The baud rate to be
selected can be one of three kinds.
❍ Baud-rate selection based on the dedicated baud-rate generator
The UART internally contains a dedicated baud-rate generator. One of eight baud rates can be
selected through the mode register (SMR0 to SMR3). Select an asynchronous or clocksynchronous baud rate through the machine clock frequency and CS2 to CS0 bits of the mode
register (SMR0 to SMR3).
❍ Baud rate based on the internal clock
The frequency of the internal clock supplied from 16-bit reload timer 0 to 3 is used as the baud
rate as it is (in synchronous mode) or first divided by 16 and then used as the baud rate (in
asynchronous mode). Any baud rate can be set through the reload value setting.
❍ Baud rate based on the external clock
The clock frequency input from the UART clock-input pins is used as the baud rate as it is (in
synchronous mode) or first divided by 16 and then used as the baud rate (in asynchronous
mode). Any baud rate can be set externally.
328
CHAPTER 15 UART
■ UART Baud-Rate Selection Circuit
Figure 15.8-1 shows a UART baud rate selection circuit.
Figure 15.8-1 UART Baud-rate Selection Circuit
SMR0 to SMR3:CS2/CS1/CS0
(Clock selection bit)
Clock selector
[Dedicated baud rate generator]
φ
For 000B to 101B
Divide-by circuit
(Synchronous)
Select 1/2, 1/4, or 1/8
division
(Asynchronous)
Select the internal fixed
division ratio
Prescaler
[Internal timer]
TMCSR0 to TMCSR3:CSL1,CSL0
2
Clock selector
φ
φ /2
Down
counter
For 110B
UF
1/1 (synchronous)
1/16 (asynchronous)
Baud rate
φ /8 φ /32
Prescaler
16-bit reload timer 0-3
[External clock]
SCK0 to SCK3
Pins
For 111B
1/1 (synchronous)
1/16 (asynchronous)
SMR0 to SMR3:MD1
(Clock synchronous/asynchronous selection)
φ : Machine clock frequency
329
CHAPTER 15 UART
15.8.1 Baud Rate Based on the Dedicated Baud-Rate Generator
This section shows the baud rates that can be set when the output clock of the
dedicated baud-rate generator is selected as the UART transfer clock.
■ Baud Rate Based on the Dedicated Baud-rate Generator
When the dedicated baud-rate generator is used to generate the transfer clock, the machine
clock prescaler is used to divide the machine clock rate by the transfer clock division ratio
selected with the clock selector. The machine clock division ratio is common in asynchronous
and synchronous modes, but the transfer clock division ratio differs in asynchronous and
synchronous modes. The values internally set separately for asynchronous and synchronous
modes are selected.
Therefore, the actual baud rate can be expressed in the following equations.
•
Asynchronous baud rate = φ × (prescaler division ratio) × (asynchronous transfer clock
division ratio)
•
Synchronous baud rate = φ × (prescaler division ratio) × (synchronous transfer clock division
ratio)
φ: Machine clock frequency
❍ Division ratio based on the prescaler (common for asynchronous and synchronous
modes)
The machine clock division ratio is determined in accordance with the DIV3 to DIV0 bits of the
CDCR register as shown in Table 15.8-1.
Table 15.8-1 Selection of Division Ratio Based on the Machine Clock Prescaler
330
MD
DIV3
DIV2
DIV1
DIV0
div
0
-
-
-
-
Stop
1
0
0
0
0
1
1
0
0
0
1
2
1
0
0
1
0
3
1
0
0
1
1
4
1
0
1
0
0
5
1
0
1
0
1
6
1
0
1
1
0
7
1
0
1
1
1
8
1
1
0
0
0
9
1
1
0
0
1
10
1
1
0
1
0
11
1
1
0
1
1
12
1
1
1
0
0
13
1
1
1
0
1
14
1
1
1
1
0
15
1
1
1
1
1
16
CHAPTER 15 UART
❍ Synchronous transfer clock division ratio
The synchronous baud-rate division ratio is specified in the CS2 to CS0 bits of the mode
register (SMR0 to SMR3) as shown in Table 15.8-2.
Table 15.8-2 Selection of Synchronous Baud-rate Division Ratio
CS2
CS1
CS0
Synchronous with CLK
Equation for calculation
0
0
0
Disabled
Disabled
0
0
1
16MHz
(φ/div)/2
0
1
0
8MHz
(φ/div)/4
0
1
1
4MHz
(φ/div)/8
1
0
0
2MHz
(φ/div)/16
1
0
1
1MHz
(φ/div)/32
Note that the calculation is based on a machine cycle, φ, of 32.0 MHz, and div = 1.
Note:
When the dedicated baud rate generator is used at synchronous transmitting, the following settings
are prohibited;
- CS2 to CS0=000B
- CS2 to CS0=001B and DIV3 to DIV0=0000B
❍ Asynchronous transfer clock division ratio
The asynchronous baud-rate division ratio is specified in the CS2 to CS0 bits of the mode
register (SMR0 to SMR3) as shown in Table 15.8-3.
Table 15.8-3 Selection of Asynchronous Baud-rate Division Ratio
CS2
CS1
CS0
Asynchronous (start-stop
synchronization)
Equation for calculation
0
0
0
76800Hz
(φ/div)/(8x13x2)
0
0
1
38400Hz
(φ/div)/(8x13x4)
0
1
0
19200Hz
(φ/div)/(8x13x8)
0
1
1
9600Hz
(φ/div)/(8x13x16)
1
0
0
500kHz
(φ/div)/(8x2x2)
1
0
1
250kHz
(φ/div)/(8x2x4)
Note that the calculation is based on a machine cycle, φ, of 31.9488 MHz, and div = 2.
331
CHAPTER 15 UART
❍ Internal timer
The equations for calculating the baud rate with CS2 to CS0 set to 110B and the internal timer
selected (example of using the reload timer) are shown below.
•
Asynchronous (start-stop synchronization) (φ/N)/(16x2x(n+1))
•
Synchronous with CLK (φ/N)/(2x(n+1))
N: Timer count clock source
n: Timer reload value
❍ External clock
The baud rate for cases where CS2 to CS0 are set to 111B and the external clock has a
frequency of f is shown below.
•
Asynchronous (start-stop synchronization)
f/16
•
Synchronous with CLK
f’
The maximum of f is one-half (1/2) the machine clock frequency and the maximum of f’ is oneeighth (1/8) the machine clock frequency.
332
CHAPTER 15 UART
15.8.2 Baud Rate Based on the Internal Timer (16-bit Reload
Timer 0)
This section shows the settings and equations for calculating the baud rate when the
internal clock from 16-bit reload timer 0 is selected as the UART transfer clock.
■ Baud Rate Based on the Internal Timer (16-bit Reload Timer 0)
When the bits CS2 to CS0 of the mode register (SMR0 to SMR3) are set to 110B, the baud rate
is selected based on the internal timer. Any baud rate can be set through selection of the
prescaler division ratio and reload value of the 16-bit reload timer 0. Figure 15.8-2 shows the
baud-rate selection circuit based on the internal timer.
Figure 15.8-2 Baud-rate Selection Circuit Based on the Internal Timer (16-bit Reload Timer 0)
SMR0 to SMR3: CS2/CS1/CS0=110B
(Internal timer selection)
Clock selector
1/1 (synchronous)
1/16 (asynchronous)
16-bit reload timer 0 output
(frequency specified in
accordance with the
prescaler divide-by value
and reload value)
Baud rate
SMR0 to SMR3: MD1
(Clock synchronous/asynchronous selection)
❍ Baud-rate calculation equation
φ
Asynchronous baud rate =
X (n+1)
Synchronous baud rate =
bps
2
φ
X (n+1)
16
bps
2
φ : Machine clock frequency
X : Division ratio based on the prescaler of the 16-bit reload timer 0 (21, 23, 25)
n : Reload value of the 16-bit reload timer 0 (0 to 65,535)
333
CHAPTER 15 UART
❍ Example of reload-value setting (when the machine clock is 31.9488 MHz)
Table 15.8-4 Baud Rate and Reload Value
Reload value
Baud rate
(bps)
Asynchronous with the clock (start-stop
synchronization)
X = 21
(Divide-by-two
machine cycle)
X = 23
(Divide-by-eight
machine cycle)
X = 21
(Divide-by-two
machine cycle)
X = 23
(Divide-by-eight
machine cycle)
38400
12
-
207
51
19200
25
-
415
103
9600
51
12
831
207
4800
103
25
1663
415
2400
207
51
3327
831
1200
415
103
6655
1663
600
831
207
13311
3327
300
1663
415
26623
6655
X: Division ratio based on the prescaler of the 16-bit reload timer 0
-: Setting is not allowed.
334
Synchronous with the clock
CHAPTER 15 UART
15.8.3 Baud Rate Based on the External clock
This section shows the settings and equations for calculating the baud rate when the
external clock is selected as the UART transfer clock.
■ Baud Rate Based on the External Clock
The following three settings are necessary for selecting the baud rate based on the external
clock.
•
Set the SCKE bit of the mode register (SMR0 to SMR3) to 0.
•
Set the bits CS2 to CS0 of the mode register (SMR0 to SMR3) to 111B and select the baud
rate based on the external clock.
•
The port for inputting the external clock is set to input.
The baud rate is selected based on the external clock input from the SCK0 to SCK3 pins as
shown in Figure 15.8-3. To change the baud rate, the cycle of the external input clock must be
changed because the internal division ratio is fixed.
Figure 15.8-3 Circuit for Baud Rate Selection Based on the External Clock
SMR0 to SMR3: CS2/CS1/CS0=111B
(External clock selection)
Clock selector
SCK0 to SCK3
1/1 (synchronous)
1/16 (asynchronous)
Pins
Baud rate
SMR0 to SMR3: MD1
(Clock synchronous/asynchronous selection)
❍ Equation for baud-rate calculation
• Asynchronous baud rate = f/16
• Synchronous baud rate = f
f: External clock frequency
(The maximum of f is [frequency of peripheral operation clock]/8. With a frequency of the
peripheral operation clock of 31.9488 MHz, the maximum of f is 3.9936 MHz.)
335
CHAPTER 15 UART
15.9 UART Operations
The UART has an ordinary bidirectional serial communication function (operation
modes 0 and 2) and master/slave-type connection communication function (operation
mode 1).
■ UART Operations
❍ Operation mode
The UART has three operation modes, mode 0 to mode 2. The inter-CPU connection method
and data transfer method can be used to select the operation mode as shown in Table 15.9-1.
Table 15.9-1 UART Operation Modes
Data length
Operation mode
Without parity
0
Normal mode
1
Multiprocessor mode
2
Normal mode
With parity
7 bits or 8 bits
Synchronization
method
Stop-bit length
Asynchronous
1 bit or 2 bits (*2)
-:
*1:
*2:
8 + 1 (*1)
-
Asynchronous
8
-
Synchronous
None
Setting is disabled.
+1 is the address/data selection bit (A/D) used for communication control.
Only one bit can be detected as stop bit at reception.
Note:
UART operation mode 1 is only used for the master unit in master/slave-type connection.
❍ Inter-CPU connection method
One-to-one connection (normal mode) or master/slave-type connection (multiprocessor mode)
can be selected. With either method, the data length, whether to use parity, and the
synchronization method must be the same for all CPUs. The operation mode is selected as
shown below.
•
In a one-to-one connection, the two CPUs must use the same operation mode (operation
mode 0 or 2). For the asynchronous method, select operation mode 0. For the synchronous
method, select operation mode 2.
•
In the master/slave-type connection, use operation mode 1. Select operation mode 1 and
use the unit as the master. In this connection, select no parity.
❍ Synchronization method
For the operation mode, the asynchronous method (start-stop synchronization) or clock
synchronization method can be selected.
❍ Signal method
The UART can handle data in the Non Return to Zero (NRZ) format only.
336
CHAPTER 15 UART
❍ Operation enable
The UART has the TXE (sending) and RXE (receiving) operation enable bits separately for
sending and receiving, which are used to control send and receive operations. If operation
becomes disabled while the operation is in progress, the following occurs.
•
If the receive operation is disabled during reception (while data is being inputted into the
receive-shift register), the receive operation stops when reception of the frame is completed
and receive data is stored in the input-data register (SIDR0 to SIDR3).
•
If the send operation is disabled during sending (while data is being outputted from the sendshift register), the send operation stops after the output-data register (SODR0 to SODR3)
runs out of data.
337
CHAPTER 15 UART
15.9.1 Operation in asynchronous mode (operation modes 0, 1)
When the UART is used in operation mode 0 (normal mode) or operation mode 1
(multiprocessor mode), the transfer becomes asynchronous.
■ Operation in Asynchronous Mode (Operation Modes 0, 1)
❍ Transfer-data format
Transfer data always starts from the start bit (L level), is transferred LSB first with the specified
data bit length, and ends with the stop bit (H level).
•
In normal mode of operation mode 0, data length can be set to 7 bits or 8 bits.
•
In operation mode 1, data has a fixed length of eight bits without parity, but an address/data
selection bit (A/D) is added instead of the parity bit.
Figure 15.9-1 shows the data format in asynchronous mode.
Figure 15.9-1 Transfer-data Format (Operation Modes 0-1)
[Operation mode 0]
[Operation mode 1]
ST
D0
D1
D2
D3
D4
D5
D6
*
D7/P
SP
ST
D0
D1
D2
D3
D4
D5
D6
D7
A/D
SP
*: D7 (bit 7): Without parity
P (parity): With parity
ST: Start bit
SP: Stop bit
A/D: Operation mode 1 (multiprocessor mode) address/data selection bit
❍ Send operation
When the send data empty flag bit (SSR0 to SSR3: TDRE) is 1, send data is written to the
output-data register (SODR0 to SODR3). If sending is enabled (SCR0 to SCR3: TXE = 1), the
data is sent.
The send data is transferred to the send-shift register. When sending begins, the TDRE flag is
set to 1 again and setting of the next unit of send data is enabled. If send-interrupt requests are
enabled (SSR0 to SSR3: TIE = 1), a send-interrupt request that requests the send data to be
set in SODR0 to SODR3 is outputted. As soon as the send data is written to SODR0 to
SODR3, the TDRE flag is cleared to 0.
❍ Receive operation
If receiving is enabled (SCR0 to SCR3: RXE = 1), receive operations are consistently
performed. When the start bit is detected, data of one frame is received in accordance with the
data format determined by the control register (SCR0 to SCR3). After reception of the data of
one frame, if an error has occurred, the error flag is set and the receive data full flag bit (SSR0
to SSR3: RDRF) is set to 1. If receive-interrupt requests are enabled (SSR0 to SSR3: RIE = 1),
a receive-interrupt request is outputted. Check each flag of the status register (SSR0 to SSR3).
If reception is normal, read the input-data register (SIDR0 to SIDR3). If an error has occurred,
338
CHAPTER 15 UART
perform the required processing to handle the error. As soon as the receive data is read from
SIDR0 to SIDR3, the RDRF flag is cleared to 0.
❍ Detecting the start bit
Implement the following settings to detect the start bit:
•
Set the communication line level to "H" (attach the mark level) before the communication
period.
•
Specify reception permission (RXE = H) while the communication line level is "H" (mark
level).
•
Do not specify reception permission (RXE = H) for periods other than the communication
period (without mark level). Otherwise, data is not received correctly.
•
After the stop bit is detected (the RDRF flag is set to 1), specify reception inhibition (RXE =
L) while the communication line level is "H" (mark level).
Figure 15.9-2 Normal Operation
Communication period
Non-communication period
Mark level
Start bit
SIN
ST
Non-communication period
Stop bit
Data
D0
D1
D0
D1
D2
D3
D4
D5
D6
D7
SP
(Sending 01010101B)
RXE
Receive clock
Sampling clock
Receive clock (8 pulses)
Recognition by the microcontroller
ST
Generating sampling clocks by dividing the receive clock by 16
D2
D3
D4
D5
D6
D7
SP
(Receiving 01010101B)
Note that specifying reception permission at the timing shown below obstructs the correct
recognition of the input data (SIN) by the microcontroller.
•
Example of operation if reception permission (RXE = H) is specified while the communication
line level is L.
Figure 15.9-3 Abnormal Operation
Communication period
Non-communication period
Mark level
Start bit
SIN
(Sending 01010101B)
RXE
Non-communication period
Stop bit
Data
ST
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
SP
SP
Receive clock
Sampling clock
Recognition by the microcontroller
ST recognition
(Receiving 10101010B)
PE,ORE,FRE
Occurrence of a reception error
❍ Stop bit
For sending, 1 bit or 2 bits can be selected. However, the receiving side always detects only
the first 1 bit.
339
CHAPTER 15 UART
❍ Error detection
•
In mode 0, parity errors, overrun errors, and frame errors can be detected.
•
In mode 1, overrun errors and frame errors can be detected, but parity errors cannot be
detected.
❍ Parity 0
Parity can only be used in operation mode 0 (asynchronous, normal mode). Whether to use
parity is specified in the PEN bit of the control register (SCR0 to SCR3). Whether to use evennumber parity or odd-number parity is specified in the P bit. In operation mode 1 (asynchronous,
multiprocessor mode) and operation mode 2 (synchronous, normal mode), parity cannot be
used. Figure 15.9-4 shows the send and receive data operations with parity set to valid.
Figure 15.9-4 Send Data Operation with Parity Set to Valid
SIN0 to SIN3
ST
1
SOT0 to SOT3
1
1
0
0
0
1
1
0
0
0
1
1
0
0
0
Data
Parity
ST: Start bit
SP: Stop bit
Note: In operation modes 1 and 2, parity cannot be used.
340
SP
Sending of even-number parity
(SCR0 to SCR3: P=0)
SP
Sending of odd-number parity
(SCR0 to SCR3: P=1)
1
ST
1
Parity error occurred during
reception with even-number parity
(SCR0 to SCR3: P=0)
0
ST
1
SOT0 to SOT3
0
SP
CHAPTER 15 UART
15.9.2 Operation in synchronous mode (operation mode 2)
When the UART is used in operation mode 2 (normal mode), the transfer mode
becomes clock synchronization.
■ Operation in Synchronous Mode (Operation Mode 2)
❍ Transfer-data format
In synchronous mode, data is transferred in units of eight bits LSB first without the start bit and
stop bit appended. Figure 15.9-5 shows the data format in clock synchronization mode.
Figure 15.9-5 Transfer-data Format (Operation Mode 2)
Send-data write
Send and receive clock
Mark level
RXE, TXE
Send and receive data
1
0
LSB
1
1
0
0
1
Data
0
MSB
❍ Clock supply
In clock synchronization mode, a number of clock pulses equal to the number of send and
receive bits must be supplied.
•
With the internal clock (dedicated baud-rate generator or internal timer) is selected, the
synchronization clock for data reception is automatically generated when data is sent.
•
When the external clock is selected, ensure that the output-data register (SODR0 to SODR3)
on the sending-side UART has data (SSR0 to SSR3: TDRE = 0). Then, clock pulses
matching a length of exactly one byte must be supplied externally. Before sending begins
and after sending, the mark level ("H") must always be set.
❍ Error detection
Overrun errors can be detected, but parity errors and frame errors cannot be detected.
❍ Initialization
The setting values of each control register in synchronous mode are shown below.
[Mode register (SMR0 to SMR3)]
- MD1, MD0: 10B
- CS2, CS1, CS0: Specify the clock selector clock input.
- SCKE: 1 for the dedicated baud-rate generator or internal timer, and 0 for the clock output
and external clock (clock input)
341
CHAPTER 15 UART
- SOE: 1 for sending and 0 for receive-only
[Control register (SCR0 to SCR3)]
- PEN: 0
- P, SBL, and A/D: These bits have no effect.
- CL: 1 (8-bit data)
- REC: 0 (To initialize, the error flag is cleared.)
- RXE, TXE: At least one of these must be 1.
[Status register (SSR0 to SSR3)]
- RIE: 1 for using interrupts and 0 for not using interrupts
- TIE: 0
❍ Start of communication
Communication starts by writing to the output-data register (SODR0 to SODR3). Note that this
applies even to communication for receiving: In this case, dummy data must be written to
SODR0 to SODR3.
❍ End of communication
When sending or receiving of the data for one frame terminates, the RDRF flag of the status
register (SSR0 to SSR3) is set to 1. For receiving, check the overrun error flag bit (SSR0 to
SSR3: ORE) and determine whether communication was performed normally.
342
CHAPTER 15 UART
15.9.3 Bidirectional communication function (normal mode)
In operation modes 0 and 2, ordinary serial bidirectional communication can be
performed in a one-to-one connection. The synchronization method is asynchronous
in operation mode 0 and synchronous in operation mode 2.
■ Bidirectional Communication Function
To operate the UART in normal mode (operation modes 0 and 2), the settings shown in Figure
15.9-6 are necessary.
Figure 15.9-6 Settings for UART Operation Mode 0
bit15 bit14 bit13 bit12 bit11 bit10
SCR1, SMR1
Mode 0→
Mode 2→
SSR1,
SIDR1/SODR1
PEN
P
SBL
0
PE
CL
AD
1
bit9
bit8
bit6
bit5
bit4
bit3
REC RXE TXE MD1 MD0 CS2 CS1 CS0
0
ORE FRE RDRF TDRE
bit7
−
1
RIE
TIE
bit2
−
bit1
bit0
SCKE SOE
0
Send data is set (for writing)/
receive data is retained (for reading)
Mode 0→
Mode 2→
: Used bit
: Unused bit
1 : Set to 1
0 : Set to 0
❍ Inter-CPU connection
Connect the two CPUs to each other as shown in Figure 15.9-7.
Figure 15.9-7 Example of Connection for UART Bidirectional Communication
SOT1
SOT1
SIN1
SIN1
Output
SCK1
CPU-1
Input
SCK1
CPU-2
❍ Communication procedure
Communication can start at any time from the sending side when send data is ready. The
receiving side receives send data and periodically returns ANS (in this example for each byte).
Figure 15.9-8 shows an example of the bidirectional communication flow.
343
CHAPTER 15 UART
Figure 15.9-8 Example of Bidirectional Communication Flow
(Sending side)
(Receiving side)
Start
Start
Set operation mode
("0" or "2")
Set operation mode (that
matches the sending side)
Set one-byte data in SODR
and perform
communication
Send data
Does receive
data exist?
NO
YES
NO
Read and process
receive data
Does receive
data exist?
YES
Read and process
receive data
344
Send data
(ANS)
Send one-byte data
CHAPTER 15 UART
15.9.4 Master/slave-type communication function
(multiprocessor mode)
The UART can communicate with multiple CPUs in a master/slave-type connection in
operation mode 1. However, the UART can only be used as the master CPU.
■ Master/slave-type Communication Function
To operate the UART in multiprocessor mode (operation mode 1), the settings shown in Figure
15.9-9 are necessary.
Figure 15.9-9 Settings for UART Operation Mode 1
bit15 bit14 bit13 bit12 bit11 bit10
SCR1, SMR1
PEN
P
SBL
0
SSR1,
SIDR1/SODR1
PE
CL
AD
1
bit9
bit8
bit6
bit5
bit4
bit3
REC RXE TXE MD1 MD0 CS2 CS1 CS0
0
ORE FRE RDRF TDRE
bit7
−
0
RIE
1
bit2
−
bit1
bit0
SCKE SOE
0
Send data is set (for writing)/
receive data is retained (for reading)
TIE
: Used bit
: Unused bit
1 : Set to 1
0 : Set to 0
❍ Inter-CPU connection
Connect one master CPU and multiple slave CPUs to two common communication lines and
configure the communication system as shown in Figure 15.9-10. UART can only be used as
the master CPU.
Figure 15.9-10 Example of Connection for UART Master/Slave-type Communication
SOT1
SIN1
Master CPU
SOT
SIN
Slave CPU #0
SOT
SIN
Slave CPU #1
❍ Function selection
For master/slave-type communication, select the operation mode and data transfer method as
shown in Table 15.9-2.
345
CHAPTER 15 UART
Table 15.9-2 Selection of Master/Slave-type Communication Functions
Operation mode
Data
Master CPU
Parity
Synchronization
method
Stop bit
None
Asynchronous
1 bit or 2 bits
Slave CPU
A/D=1
+
8-bit address
Address send
and receive
Mode 1
A/D=0
+
8-bit data
Data send
and receive
❍ Communication procedure
Communication starts when the master CPU sends address data. Address data is indicated by
the fact that the A/D bit set to 1. It selects the slave CPU to communicate with. Each slave
CPU determines the address data via the program. If the address data matches the allocated
address, the slave CPU communicates (ordinary data) with the master CPU.
Figure 15.9-11 shows a flowchart of the master-slave-type communication (in multiprocessor
mode).
Figure 15.9-11 Flowchart of Master/Slave-type Communication
(Master CPU)
START
Set to operation mode "1"
Set the SIN pins to
serial-data input
Set 1-byte data (address
data) that selects the slave
CPU in D0 to D7 and send
(A/D = 1)
Set A/D to 0
Enable receive operation
Communicate with slave CPU
Communication
terminated?
NO
YES
Communicate
with another slave
CPU
YES
Enable receive operation
346
NO
END
CHAPTER 15 UART
15.10 Notes on Using UART
This section provides notes on using the UART.
■ Notes on Using the UART
❍ Operation enabled
The UART has the TXE (sending) and RXE (receiving) operation enable bits in the control
register (SCR0 to SCR3) separately for sending and receiving. Since both sending and
receiving are disabled in the default state (initial value), these operations must be enabled
before performing the transfer. The operations can be disabled to stop transfer as necessary.
❍ Communication mode setting
Set the communication mode while the UART is stopped. If the mode is set during a sending or
receiving operation, the integrity of the sent or received data cannot be guaranteed.
❍ Synchronization mode
The UART clock synchronization mode (operation mode 2) employs the clock control (I/O
extend serial) method and does not append the start bit and stop bit to data.
❍ Timing of enabling send interrupts
A send-interrupt request occurs immediately after the send-interrupt request is enabled (SSR0
to SSR3: TIE = 1) because the default (initial value) of the send data empty flag bit (SSR0 to
SSR3: TDRE) is 1 (no send data, send-data write enabled). The send data must be ready
before the TIE flag is set to 1.
347
CHAPTER 15 UART
348
CHAPTER 16 DMA CONTROLLER
CHAPTER 16
DMA CONTROLLER
This chapter describes the overview of the DMA controller, its block diagram,
configuration and functions of its registers, and its operations.
16.1 Overview of the DMA Controller
16.2 Block Diagram of the DMA Controller
16.3 Registers of the DMA Controller
16.4 Transfer Modes Supported by the DMA Controller
16.5 Transfer-Acceptance Signal Output and Transfer-End Signal Output
16.6 Notes on the DMA Controller
16.7 Timing Charts for the DMA Controller
349
CHAPTER 16 DMA CONTROLLER
16.1 Overview of the DMA Controller
The DMA controller is a module built in the MB91151A that performs DMA (Direct
Memory Access) transfers.
■ Features of the DMA Controller
350
•
8 channels
•
The 3 transfer modes below are available
•
Single/block transfer
•
Burst transfer
•
Continuous transfer
•
Transfers within the entire address area
•
Up to 65,536 transfers
•
Interrupt at end of transfer
•
Software selection available for increasing or decreasing the number of transfer addresses
•
The following pins are available (3 of each kind):
•
Input pin for external transfer request
•
Output pin for reception of external transfer request
•
Output pin for "end of external transfer"
CHAPTER 16 DMA CONTROLLER
16.2 Block Diagram of the DMA Controller
Figure 16.2-1 shows a block diagram of the DMA controller.
■ Block Diagram of the DMA Controller
Figure 16.2-1 Block Diagram of the DMA Controller
DREQ0 to DREQ2
Internal resource
transfer request
3
Edge/level
detector circuit
3
3
3
Sequencer
5
Data buffer
8
DACK0 to DACK2
DEOP0 to DEOP2
Interrupt request
Switcher
DPDP
Data bus
DACSR
DATCR
Mode
BLK DEC
BLK
DMACT
INC/DEC
SADR
DADR
351
CHAPTER 16 DMA CONTROLLER
16.3 Registers of the DMA Controller
Figure 16.3-1 lists the registers of the DMA controller.
■ Registers of the DMA Controller
Figure 16.3-1 Registers for the DMA Controller
[Internal registers in the DMAC]
31
0
000200H
DPDP
000204H
DACSR
000208H
DATCR
[DMA descriptors in RAM]
31
0
DPDP + 0H
DMA
ch0
Descriptor
DMA
ch1
Descriptor
DPDP + 0CH
:
:
DPDP + 54H
352
DMA
ch7
Descriptor
CHAPTER 16 DMA CONTROLLER
16.3.1 DMAC parameter descriptor pointer (DPDP)
This pointer is an internal register in the DMAC that stores the start address in the
descriptor table for the DMAC in RAM.
Bit0 to bit6 are always set to "0". The start address of the descriptor can be set in units
of 128 bytes.
■ DMAC Parameter Descriptor Pointer (DPDP)
The register configuration of the DMAC parameter descriptor pointer (DPDP) is given below.
31
7
000200H
6
0
0000000
Initial value: 0000000B
Initial value: Undefined
•
Upon reset, the pointer is not initialized.
•
The pointer value can be read and written.
•
Use a 32-bit transfer instruction to access this register.
The descriptor used to specify the operating mode for each channel is placed at an address set
by the DPDP, as covered in Table 16.3-1.
Table 16.3-1 Descriptor Address for Each Channel
DMA channel
Descriptor address
DMA channel
Descriptor address
0
DPDP + 0 (00H)
4
DPDP + 48 (30H)
1
DPDP + 12 (0CH)
5
DPDP + 60 (3CH)
2
DPDP + 24 (18H)
6
DPDP + 72 (48H)
3
DPDP + 36 (24H)
7
DPDP + 84 (54H)
353
CHAPTER 16 DMA CONTROLLER
16.3.2 MAC control status register (DACSR)
The DMAC control status register (DACSR) is an internal register in the DMAC that
controls the entire DMAC and indicates its status.
■ DMAC Control Status Register (DACSR)
The register configuration of the DMAC control status register (DACSR) is given below.
000204H
31
30
29
28
DER7
DED7
DIE7
R/W
R/W
R/W
R/W
23
22
21
20
DER5
DED5
DIE5
R/W
R/W
R/W
R/W
15
14
13
12
DER3
DED3
DIE3
R/W
R/W
R/W
R/W
7
6
5
4
DER1
DED1
DIE1
R/W
R/W
R/W
27
26
25
24
Initial value
DED6
DIE6
DOE6
00000000B
R/W
R/W
R/W
R/W
19
18
17
16
DED4
DIE4
DOE4
R/W
R/W
R/W
R/W
11
10
9
8
DED2
DIE2
DOE2
R/W
R/W
R/W
R/W
3
2
1
0
DED0
DIE0
DOE0
R/W
R/W
R/W
DOE7 DER6
DOE5 DER4
DOE3 DER2
DOE1 DER0
R/W
R/W
00000000B
00000000B
00000000B
[bit31, bit27, bit23, bit19, bit15, bit11, bit7, bit3] DER7 to DER0 (DMA error)
Indicates that an error has occurred at the DMA request source of channel 7 to 0 and that
DMA transfer processing has been terminated.
0: No error has occurred.
1: An error has occurred.
Whether an error is detected depends on the DMA request source. Some DMA request
sources have no error detection.
- Upon a reset, the bits in the register are initialized to 0.
- Although these bits can be read and written, they can be set only to 0.
- Read/modify/write instructions always return a reading value of 1.
354
CHAPTER 16 DMA CONTROLLER
[bit30, bit26, bit22, bit18, bit14, bit10, bit6, bit2] DED7 to DED0 (DMA end)
Indicates that DMA transfer over channel 7 to 0 has ended.
0: DMA transfer operation has not ended.
1: The counter has been reset to "0", or an error occurred at the transfer request source.
- Upon a reset, the bits in the register are initialized to 0.
- Although these bits can be read and written, these bits can only be set to 0 for writing.
- Read/modify/write instructions always return a reading value of 1.
[bit29, bit25, bit21, bit17, bit13, bit9, bit5, bit1] DIE7 to DIE0 (DMA interrupt enable)
Specify whether to generate an interrupt request at the end of DMA transfer over channel 7
to 0 (when DED7 to DED0 is set to 1).
0: Disables interrupts.
1: Enables interrupts.
- Upon reset, the bits in the register are initialized to 0.
- These bits can be read and written.
[bit28, bit24, bit20, bit16, bit12, bit8, bit4, bit0] DOE7 to DOE0 (DMA operation enable)
Enables DMA transfer operation over channel 7 to 0.
0: Disables operation.
1: Enables operation.
- Upon completion of DMA transfer over the appropriate channel (when DED7 to DED0 is set
to 1), DOE7 to DOE0 is reset to 0.
- If a clearing operation following completion of transfer, and a setting operation by loading
from a bus are performed concurrently, the setting operation has priority.
- Upon reset, the bits in the register are initialized to 0.
- These bits can be read and written.
355
CHAPTER 16 DMA CONTROLLER
16.3.3 DMAC pin control register (DATCR)
The DMAC pin control register (DATCR) is an internal register in the DMAC that
controls an external transfer request input pin, an external transfer-requestacceptance output pin, and an external transfer-end output pin.
■ DMAC Pin Control Register (DATCR)
The register configuration of the DMAC pin control register (DATCR) is given below.
31
24
−
000208H
XXXXXXXXB
23
22
21
−
−
LS21
LS20 AKSE2 AKDE2 EPSE2 EPDE2 XXXX0000B
R/W
R/W
R/W
R/W
R/W
R/W
12
11
10
9
8
15
14
13
−
−
LS11
R/W
7
6
5
−
−
LS01
R/W
20
Initial value
19
18
17
16
LS10 AKSE1 AKDE1 EPSE1 EPDE1 XXXX0000B
R/W
R/W
R/W
R/W
R/W
4
3
2
1
0
LS00 AKSE0 AKDE0 EPSE0 EPDE0 XXXX0000B
R/W
R/W
R/W
R/W
R/W
[bit21, bit20, bit13, bit12, bit5, bit4] LS21, LS10, LS11, LS10, LS01 and LS00 for transfer
request input detection level selection
These bits select a detection level for an external transfer request input pin DREQn as
shown below.
LS21,
LS11, LS01
LS20,
LS10, LS00
0
0
Detects a rising edge.
0
1
Detects a falling edge.
1
0
Detects the "H" level.
1
1
Detects the "L" level.
•
•
•
356
Description
Upon reset, register operation is undefined.
These bits can be read and written.
To use continuous transfer mode, set "H" level detection or "L" level detection.
CHAPTER 16 DMA CONTROLLER
[bit19, bit11, bit3] AKSE2 to AKSE0
[bit18, bit10, bit2] AKDE2 to AKDE0
Specify the time at which to generate a transfer-request-acceptance output signal. Also,
specify whether to enable or disable the function for output of transfer-request-acceptance
output signals from a pin.
•
•
AKSE2 to
AKSE0
AKDE2 to
AKDE0
0
0
Disables transfer-acceptance output.
0
1
Enables transfer-acceptance output during access to transfer
destination data.
1
0
Enables transfer-acceptance output during access to transfer
source data.
1
1
Enables transfer-acceptance output during access to transfer
destination data.
Description
Upon a reset, the bits in the register are initialized to 00B.
These bits can be read and written.
[bit17, bit9, bit1] EPSE2 to EPSE0
[bit16, bit8, bit0] EPDE2 to EPDE0
Specify the time at which to generate a transfer-end output signal. Also, specify whether to
enable or disable the function for outputting a transfer-end output signal from a pin.
•
•
EPSE2 to
EPSE0
EPDE2 to
EPDE0
0
0
Disables transfer-end output.
0
1
Enables transfer-end output during access to transfer
destination data.
1
0
Enables transfer-end output during access to transfer source
data.
1
1
Enables transfer-end output during access to transfer source
and transfer destination data.
Description
Upon reset, the bits in the register are initialized to 00B.
These bits can be read and written.
357
CHAPTER 16 DMA CONTROLLER
16.3.4 Register of the descriptor in RAM
This register stores information for each channel for DMA transfer.
This register has a size of 12 bytes per channel and uses the memory space at the
address allocated by the DPDP.
For details on the start address of the descriptor for each channel, see Table 16.3-1.
■ Descriptor Start Word
The register configuration of the descriptor start word is given below.
31
16
DMACT
R/W
15
14
13
12
11
10
−
9
8
1
0
BLK
R/W
7
6
5
4
3
2
SCS1
SCS0
DCS1
DCS0
WS1
WS0
R/W
R/W
R/W
R/W
R/W
R/W
MOD1 MOD0
R/W
R/W
Initial value: Undefined
[bit31 to bit16] DMACT transfer count
Specify the number of times the DMA is to be transferred. With 0000H set, the DMA is
transferred 65536 times.
The value is decremented by one for each transfer.
[bit15 to bit12] Empty
[bit11 to bit8] BLK block size
Specify the size of a block to be transferred in single/block transfer mode.
If you specify 0, a block size of 16 is set. For single transfer, specify 1.
[bit7 and bit6] SCS1 and SCS0 transfer source address update mode
358
CHAPTER 16 DMA CONTROLLER
[bit5, bit4] DCS1 and DCS0 transfer destination address update mode
Specify the mode for updating the transfer source and destination addresses for each
transfer.
You can specify the combinations listed below.
Table 16.3-2 Transfer Source/Destination Address Update Mode
SCS1
SCS0
DCS1
DCS0
Transfer source
address
Transfer destination
address
0
0
0
0
Address incremented
Address incremented
0
0
0
1
Address incremented
Address decremented
0
0
1
0
Address incremented
Address fixed
0
1
0
0
Address decremented
Address incremented
0
1
0
1
Address decremented
Address decremented
0
1
1
0
Address decremented
Address fixed
1
0
0
0
Address fixed
Address incremented
1
0
0
1
Address fixed
Address decremented
1
0
1
0
Address fixed
Address fixed
Others
Disabled
In address update mode, the units of increment or decrement are as follows, depending on the
length of data to be transferred.
Length of data transferred
Unit of address increment or decrement
Byte (8 bits)
Plus or minus 1 byte
Halfword (16 bits)
Plus or minus 2 bytes
Word (32 bits)
Plus or minus 4 bytes
[bit3, bit2] WS1 and WS0
Specify the length of data to be transferred.
WS1
WS0
Length of data to be transferred
0
0
Byte
0
1
Halfword
1
0
Word
1
1
Disabled
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CHAPTER 16 DMA CONTROLLER
[bit1, bit0] MOD1 and MOD0 transfer mode
Specify transfer mode.
MOD1
MOD2
Operating mode
0
0
Single/block mode
0
1
Burst mode
1
0
Continuous transfer mode
1
1
Disabled
Note: Only ch0 to ch2 can use continuous transfer mode.
■ Second Word in the Descriptor
31
0
SADR
R/W
Stores a transfer source address.
The value is updated in accordance with a transfer operation based on the specified address
update mode (SCS1 and SCS0 bits).
Specify a multiple of "2" as the address if the length of data to be transferred is of halfword
length, and a multiple of "4" as the address if the data is of word length.
■ Third Word in the Descriptor
31
0
DADR
R/W
Stores a transfer destination address.
The value is updated in accordance with transfer operation based on the specified address
update mode (DCS1 and DCS0 bits).
Specify a multiple of "2" as the address if the length of data to be transferred is of halfword
length, and a multiple of "4" as the address if the data is of word length.
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CHAPTER 16 DMA CONTROLLER
16.4 Transfer Modes Supported by the DMA Controller
The DMA controller supports the following three transfer modes.
• Single/block transfer mode
• Continuous transfer mode
• Burst transfer mode
■ Single/block Transfer Mode
1. Use an initialization routine to set the descriptor.
2. Use the appropriate program to initialize the DMA transfer request source. If this source is an
internal peripheral circuit, enable interrupt requests. Disable interrupt requests for interrupt
controller ICR register.
3. Use a program to set the DOE7 to DOE0 bit in the desired DACSR to 1. This completes the
DMA setup.
4. When the DMAC detects DMA transfer request input, it requests the CPU to acquire the bus
right.
5. When the CPU assigns the bus right, the DMAC accesses three-word information stored in
the descriptor via the bus.
6. DMACT subtraction is performed, and data is transferred in accordance with information in
the descriptor by the number of times set in BLK or until the DMACT becomes "0". During
data transfer, the transfer-request-acceptance output signal is outputted (if external transfer
request input is used). If the DMACT subject to subtraction becomes "0", the transfer-end
output signal is outputted during data transfer.
7. The transfer request input is cleared.
8. SADR or DADR addition or subtraction is performed, and a new value is written back to the
descriptor together with the DMACT value.
9. The bus right is returned to the CPU.
10.If the DMACT value is "0", DACSR DED7 to DED0 is set to "1", and a CPU interrupt is
generated if interrupts are enabled.
If the descriptor is stored in the internal RAM, and data of byte length is transferred between
external buses, the required minimum cycle count per transfer is as described below, under the
conditions indicated:
•
When both the transfer source and destination addresses are fixed: (6 + 5 × BLK) cycles
•
When only one of the transfer source and destination addresses is fixed:(7 + 5 × BLK) cycles
•
When both the transfer source and destination addresses are incremented or decremented:
(8 + 5 × BLK) cycles
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CHAPTER 16 DMA CONTROLLER
■ Continuous Transfer Mode
1. Use an initialization routine to set the descriptor.
2. Use the appropriate program to initialize the DMA transfer request source. Set the external
transfer request input pin to H or L level detection.
3. Use the program to set the DOE7 to DOE0 bit in the desired DACSR to 1. This completes
the DMA setup.
4. When the DMAC detects DMA transfer request input, its requests the CPU to acquire the
bus right.
5. When the CPU assigns the bus right, the DMAC accesses three-word information in the
descriptor via the bus.
6. DMACT subtraction is performed, and data is transferred once in accordance with the
information in the descriptor. During data transfer, the transfer-request-acceptance output
signal is outputted. When the DMACT subject to the subtraction becomes "0", the transferend output signal is outputted during data transfer.
7. If the DMACT value is not "0" and a peripheral DMA request still exists, step 6) is repeated.
(Step 8) is used depending on the bus status.)
8. If the DMACT value is "0" or if a peripheral DMA request is cleared, SADR or DADR addition
or subtraction is performed, and a new value is written back to the descriptor together with
the DMACT value.
9. The bus right is returned to the CPU.
10.If the counter value is 0, DACSR DED7 to DED0 is set to "1", and a CPU interrupt is
generated if interrupts are enabled.
If the descriptor is stored in the internal RAM, and data of byte length is transferred between
external buses, the required minimum cycle count per transfer is as described below, under the
conditions indicated:
•
When both the transfer source and destination addresses are fixed: (6 + 5 × n) cycles
•
When only one of the transfer source and destination addresses is fixed: (7 + 5 × n) cycles
•
When both the transfer source and destination addresses are incremented or decremented:
(8 + 5 × n) cycles
■ Burst Transfer Mode
1. Use an initialization routine to set the descriptor.
2. Use the appropriate program to initialize the DMA transfer request source. If the internal
peripheral circuit is the transfer request source, enable interrupt requests. At the same time,
disable interrupt for interrupt controller ICR.
3. Use the program to set the DOE7 to DOE0 bit in the desired DACSR to "1". This completes
the DMA setup.
4. When the DMAC detects DMA transfer request input, it requests the CPU to acquire the bus
right.
5. When the CPU assigns the bus right, the DMAC accesses three-word information in the
descriptor via the bus.
6. Data is transferred in accordance with the descriptor information by the number of times set
in the DMACT during DMACT subtraction. The transfer-request-acceptance output signal is
outputted during data transfer. (If external transfer request input is used,) the transfer-end
output signal is outputted during data transfer when the DMACT becomes "0".
7. SADR or DADR addition or subtraction is performed, and a new value is written back to the
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CHAPTER 16 DMA CONTROLLER
descriptor together with the DMACT value.
8. The bus right is returned to the CPU.
9. DACSR DED7 to DED0 is set to 1, and a CPU interrupt is generated if interrupts are
enabled.
If the descriptor is stored in the internal RAM, and data of byte length is transferred between
external buses, the required minimum cycle count per transfer is as described below, under the
conditions indicated:
•
When both the transfer source and destination addresses are fixed: (6 + 5 × n) cycles
•
When only one of the transfer source and destination addresses is fixed: (7 + 5 × n) cycles
•
When both the transfer source and destination addresses are incremented or decremented:
(8 + 5 × n) cycles
■ Combinations of Request Sense Modes and Transfer Modes
Figure 16.4-1 shows the available combinations of request sense modes and transfer modes.
Figure 16.4-1 Combinations of Request Sense Modes and Transfer Modes
Request sense
Transfer mode
Transfer unit
Edge sense
Step operation
mode
Single transfer
Level sense
Burst transfer
mode
Block transfer
Continuous
transfer mode
■ DREC Signal Sense Modes
❍ Edge sense
This mode can be used in step transfer (single/block) and burst transfer modes.
DMA requests are detected at an active edge.
Because the input of an external DREQ is masked during DMAC transfer, note that the active
edge for the next transfer must be after that of the transfer destination DACK in the previous
DMA transfer. Note that the step transfer is used.
❍ Level sense
This mode can be used in step transfer (single/block) and continuous and burst transfer modes.
DMA requests are detected at an "active" level.
Note:
Minimum 2tCYC [ns] applies as the electrical characteristic of DACK signals for both level and edge
detection.
In the case of edge detection, minimum 2tCYC [ns] is also required as DACK negation interval.
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CHAPTER 16 DMA CONTROLLER
16.4.1 Step Transfer (Single/Block Transfer)
The step transfer (single/block transfer) performs one DMA transfer per transfer
request. Edge or level can be selected for the DREQ input.
■ Step Transfer (Single/Block Transfer)
In step transfer mode, the bus access right is transferred to the CPU for each DMA transfer.
The unit of transfer is determined based on the block size. As the block size increases, the
DMAC transfer rate increases, but the CPU throughput decreases.
Figure 16.4-2 shows a sample timing of step transfer the case a CLK doubler, internal
descriptors, and a block size of 1 is used.
Figure 16.4-2 Sample Timing of Step Transfer
Step transfer [use of CLK doubler, internal descriptors, and block size = 1]
CLK
DREQ
DACK
Descriptor access
Internal
D-Abus
Interval during
which the CPU
can use the DATA
bus
External
Abus
Transfer
Transfer
destination destination
364
Transfer
Transfer
destination destination
CHAPTER 16 DMA CONTROLLER
16.4.2 Continuous Transfer
In continuous transfer, DMA transfer is performed while a transfer request [DREQ]
retains the active level. For the DREQ input, only level sense mode is possible.
■ Continuous Transfer
In continuous transfer mode, the bus access right is transferred to the CPU when the transfer
count register is reset to 0 or the DREQ input is negated.
Figure 16.4-3 shows an example for continuous transfer timing when a CLK doubler and internal
descriptors are used.
Figure 16.4-3 Sample Timing of Continuous Transfer
Continuous transfer [use of CLK doubler and internal descriptors]
CLK
Descriptor access
DREQ
DACK
Internal
D-Abus
External
Abus
Interval during
which the CPU
can use the
DATA bus
Transfer
destination
Transfer Transfer
destination destination
Transfer
destination
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CHAPTER 16 DMA CONTROLLER
16.4.3 Burst Transfer
In burst transfer, DMA transfer is performed as many times as specified in a transfer
request [DREQ].
Level or edge sense mode can be selected for the DREQ input.
■ Burst Transfer
In burst transfer mode, DMA transfer is finished when the transfer count register becomes 0,
and bus access right is transferred to the CPU.
Figure 16.4-4 shows an example of burst transfer timing when a CLK doubler and internal
descriptors are used.
Figure 16.4-4 Sample Timing of Burst Transfer
Burst transfer [use of CLK doubler and internal descriptors]
CLK
DREQ
Descriptor access
DACK
Internal
D-Abus
External
Abus
Interval during which
the CPU can use the
DATA bus
Transfer
destination
Transfer
Transfer
Transfer
destination destination destination
DEOP2 to DEOP0
DMACT=1
366
DMACT=0
CHAPTER 16 DMA CONTROLLER
16.4.4 Differences Because of DREQ Sense Mode
The DREQ sense modes include level and edge modes. This section provides notes
on each mode.
■ Notes on Level Mode
In level sense mode, be careful that no overrun occurs during DMAC transfer.
Negate DREQ until the rising DACK edge during transfer destination access.
Figure 16.4-5 shows the level-mode timing.
Figure 16.4-5 Level-Mode Timing
Up to 1 cycle
CLK
DREQ
DREQ
DACK
DREQ(NG)
Transfer is performed twice
per transfer request.
Source reading
Writing to destination
Internal
D-A
Descriptor writing
Descriptor reading
External
A bus
Transfer
destination
Transfer
destination
A
B
A:
Request flag clearance point
Sensing start point for the next DREQ in edge sense mode
Sensing start point for the next DREQ in continuous transfer mode
B:
Sensing start point for the next DREQ during single and block transfer in level sense mode
Note: The timing from DREQ to DMA start reflects the case where this is performed close to top speed.
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CHAPTER 16 DMA CONTROLLER
■ Notes on Edge Mode
In edge sense mode, the next DREQ edge must be inputted after the clearance point of the
DMAC request flag. Any edge input before that point is ignored.
To ensure the edge is recognized, a negation interval of minimum 2tCYC [ns] is required.
Input the DREQ, as shown in Figure 16.4-6, after the falling DACK edge during transfer
destination access.
Figure 16.4-6 shows the timing in edge-mode.
Figure 16.4-6 Edge-Mode Timing
CLK
DREQ
DACK
DREQ(NG)
Active edge is too early.
DREQ(NG)
DREQ(NG)
Writing to destination
The time is greater than
"Minimum 2tCYC [ns]"
Internal
D-A bus
Descriptor writing
External
A bus
Transfer
destination
Transfer
destination
A
A:
B
Request flag clearance point
Sensing start point for the next DREQ in edge sense mode
Sensing start point for the next DREQ in continuous transfer mode
B:
Sensing start point for the next DREQ during single and block transfer in level sense mode
Note: The timing from DREQ to DMA start reflects the case where this is performed close to top speed.
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CHAPTER 16 DMA CONTROLLER
16.5 Transfer-Acceptance Signal Output and Transfer-End
Signal Output
Channels 0, 1 and 2 support a function for outputting the transfer-request-acceptance
signal and transfer-end signal output from a pin.
When accepting transfer request input from a pin for DMA transfer, the DMAC outputs
the transfer-request-acceptance signal.
When accepting transfer request input from a pin for DMA transfer and ending the
transfer with the DMACT counter set to "0", the DMAC outputs the transfer-end signal.
■ Transfer-Acceptance Signal Output
The transfer-request-acceptance signal is outputted as active-low pulses when transfer data is
accessed. Using the AKSE2 to AKSE0 and AKDE2 to AKDE0 bits in DATCR, you can set
whether to output that signal synchronously with transfer source access, transfer destination
access, or both of transfer source access and transfer destination access.
■ Transfer-End Signal Output
The transfer-end signal is outputted as active-low pulses when the final transfer data is
accessed. Using the EPSE2 to EPSE0 and EPDE2 to EPSE0 bits in DATCR, you can set
whether to output that signal synchronously with transfer source access, transfer destination
access, or both of transfer source access and transfer destination access.
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CHAPTER 16 DMA CONTROLLER
16.6 Notes on the DMA Controller
This section provides notes on using the DMA controller.
■ Interchannel Priority
Once the DMAC is activated by a DMA transfer request over a channel, a DMA transfer request
over another channel is not accepted and is held until the end of the current transfer.
If requests over multiple channels are active at detection of a DMA transfer request by the
DMAC, which channel is to be accepted depends on the priority given below.
(High) ch0 --> ch1 --> ch2 --> ch3 --> ch4 --> ch5 --> ch6 --> ch7 (Low)
If requests over multiple channels are generated concurrently, the DMA transfer over one
channel is executed, then bus control is returned to the CPU before performing DMA transfer
over the next channel.
■ Notes on Using a Resource Interrupt Request as a DMA Transfer Request
For DMA controller transfer, you must disable the interrupt levels via the appropriate interrupt
controller.
In contrast, for interrupt generation, you must disable the DMA controller operation enable bit in
the DMA controller and set the interrupt level to a proper value.
■ Suppression of DMA Transfer upon Generation of a Higher-priority Interrupt
The FR family supports a function for terminating DMA transfer originating in a DMA transfer
request when a higher-priority interrupt occurs.
❍ HRCL register
You can terminate DMA transfer operation upon occurrence of an interrupt request by operating
the HRCL register (Hold Request Cancel Level register) in the interrupt controller.
If the interrupt level set in an interrupt request generated from a peripheral circuit is higher than
that set in the HRCL register, DMAC DMA transfer operation is suppressed. With DMA transfer
operation executed, the transfer operation is suspended at a breakpoint, and the bus right is
given to the CPU. If the system is currently waiting for the generation of a DMA transfer request,
a DMA transfer request is held when it is generated.
After reset, the HRCL register is set to the lowest level (31). The DMA transfer operation is,
therefore, suppressed against all interrupt requests. To operate DMA transfer even with an
interrupt request generated, set the HRCL register to the required value.
❍ PDRR register
The function for suppressing DMA transfer operation by setting the HRCL register is enabled
only when an interrupt request of a higher priority is active. For example, when an interrupt
request is cleared in the interrupt handler program, the suppression of DMA transfer by the
HRCL register may be released, with the CPU losing the bus right.
The clock control section supports a PDRR register to clear an interrupt request so that other
interrupt requests may be accepted, and to suppress DMA transfer operation.
If you use the interrupt handler to load the PDRR with a value other than "0", DMA transfer operation
is suppressed. To release the suppression of DMA transfer operation, load the PDRR with "0".
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CHAPTER 16 DMA CONTROLLER
■ DMA Transfer Operation in Sleep Mode
DMA transfer operation cannot use during sleep state. Before the CPU changes to sleep state,
the state of DMA transfer operation must be set to prohibition state.
■ Transfer Operation to DMAC Internal Register
Do not specify a DMAC internal register as a transfer destination address. Table 16.6-1 lists the
DMA transfer request sources.
Table 16.6-1 Source for DMA Transfer Requests
Channel number
Description
0
External transfer request input pin DREQ0
1
External transfer request input pin DREQ1
2
External transfer request input pin DREQ2
3
PPG ch0
4
Received over UART ch0
5
Sent over UART ch0
6
16-bit reload timer ch0
7
A/D converter
❍ Error status in the DMAC transfer request source
Only ch4 can report the occurrence of an error in the DMA request source, by using the DER7
to DER0 bit in the DACSR.
When a UART ch0 reception interrupt is used as the DMA transfer request, the DER4 bit is set
to 1 if any of the errors given below occurs.
•
Parity error
•
Overrun error
•
Framing error
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CHAPTER 16 DMA CONTROLLER
16.7 Timing Charts for the DMA Controller
This section covers timing charts for DMA controller operation.
• Timing chart for the descriptor access section
• Timing chart for the data transfer section
• Timing chart for transfer termination in continuous transfer mode
• Timing chart for transfer-end operation
■ Symbols Used in the Timing Charts
Table 16.7-1 shows the symbol meaning used in the following timing charts.
Table 16.7-1 Symbols Used in the Timing Charts
Symbol
#0
Descriptor No. 0
#0H
Bit31 to bit16 in descriptor No. 0
#0L
Bit15 to bit0 in descriptor No. 0
#1
Descriptor No. 1
#1H
Bit31 to bit16 in descriptor No. 1
#1L
Bit15 to bit0 in descriptor No. 1
#2
Descriptor No. 2
#2H
Bit31 to bit16 in descriptor No. 2
#2L
Bit15 to bit0 in descriptor No. 2
#1/2
Descriptor No. 1 or No. 2 (Depending on SCS1 and SCS0, and DCS1 and
DCS0)
#1/2H
Bit31 to bit16 in descriptor No. 1 or No. 2
#1/2L
Bit15 to bit0 in descriptor No. 1 or No. 2
S
372
Description
Transfer source
SH
Bit31 to bit16 of the transfer source
SL
Bit15 to bit0 of the transfer source
D
Transfer destination
DH
Bit31 to bit16 of the transfer destination
DL
Bit15 to bit0 of the transfer destination
CHAPTER 16 DMA CONTROLLER
16.7.1 Timing charts for the descriptor access section
This section covers the timing charts for the descriptor access section.
■ Descriptor access Section
❍ Request pin input mode: Level, Descriptor address: External
(A)
CLK
DREQ0 to DREQ2
Addr pin
#0H
Data pin
#0L
#1H
#0L
#0H
#1L
#1H
#2H
#1L
S
#2L
#2H
#2L
S
RD
WR0, WR1
DACK0 to DACK2
DEOP0 to DEOP2
❍ Request pin input mode: Level, Descriptor address: Internal
(A)
Internal KB
CLK
DREQ0 to DREQ2
Addr pin
Data pin
S
S
RD
WR0, WR1
DACK0 to DACK2
DEOP0 to DEOP2
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CHAPTER 16 DMA CONTROLLER
❍ Request pin input mode: Edge, Descriptor address: External
(A)
CLK
DREQ0 to DREQ2
Addr pin
#0H
Data pin
#0L
#0H
#1H
#0L
#1L
#1H
#2L
#2H
#1L
#2H
S
#2L
S
RD
WR0, WR1
DACK0 to DACK2
DEOP0 to DEOP2
❍ Request pin input mode: Edge, Descriptor address: Internal
(A)
CLK
DREQ0 to DREQ2
Addr pin
S
Data pin
S
RD
WR0, WR1
DACK0 to DACK2
DEOP0 to DEOP2
Note:
For the part from DREQn generation to the start of DMAC operation, only the conditions for the
fastest case are covered. The actual start of the DMAC operation may be delayed owing to bus
contention originating in CPU instruction fetching and data access.
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CHAPTER 16 DMA CONTROLLER
16.7.2 Timing charts for the data transfer section
This section covers timing charts for the data transfer section.
■ Data Transfer Section, 16/8-bit Data
❍ Transfer source area: External, Transfer destination area: External
(A)
CLK
DREQ0 to DREQ2
Addr pin
#2
Data pin
S
S
D
#2
S
D
S
D
S
D
D
S
D
S
D
S
D
RD
WR0, WR1
W
W
W
DACK0 to DACK2
DEOP0 to DEOP2
❍ Transfer source area: External, Transfer destination area: Internal RAM
(A)
CLK
DREQ0 to DREQ2
Addr pin
#2
Data pin
S
#2
S
S
S
S
S
S
S
RD
WR0, WR1
DACK0 to DACK2
DEOP0 to DEOP2
❍ Transfer source area: Internal RAM, Transfer destination area: External
(A)
CLK
DREQ0 to DREQ2
Addr pin
Data pin
#2
#2
D
D
D
D
D
D
D
D
RD
WR0, WR1
W
W
W
W
DACK0 to DACK2
DEOP0 to DEOP2
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CHAPTER 16 DMA CONTROLLER
16.7.3 Timing charts for transfer termination in continuous
transfer mode
This section covers timing charts for transfer termination in continuous transfer mode.
■ Transfer Termination in Continuous Transfer Mode (When Either Address is Fixed), 16/8-bit Data
❍ Transfer source area: External, Transfer destination area: External
CLK
DREQ0 to DREQ2
Addr pin
D
Data pin
D
S
S
D
#0H
#1/2H
#1/2L
D
#0H
#1/2H
#1/2L
W
W
RD
W
WR0, WR1
W
W
DACK0 to DACK2
DEOP0 to DEOP2
❍ Transfer source area: External, Transfer destination area: Internal RAM
CLK
DREQ0 to DREQ2
Addr pin
S
Data pin
S
S
S
#0H
#1/2H
#1/2L
#0H
#1/2H
#1/2L
W
W
RD
W
WR0, WR1
DACK0 to DACK2
DEOP0 to DEOP2
❍ Transfer source area: Internal RAM, Transfer destination area: External
CLK
DREQ0 to DREQ2
Addr pin
D
D
D
#0H
#1/2H
#1/2L
Data pin
D
D
D
#0H
#1/2H
#1/2L
RD
WR0, WR1
DACK0 to DACK2
DEOP0 to DEOP2
376
W
W
W
W
W
W
CHAPTER 16 DMA CONTROLLER
■ Transfer Termination in Continuous Transfer Mode (When both Addresses are Changed), 16/8-bit Data
❍ Transfer source area: External, Transfer destination area: External
CLK
DREQ0 to DREQ2
Addr pin
D
Data pin
D
S
S
D
#0H
#1H
#1L
#2H
#2L
D
#0H
#1H
#1L
#2H
#2L
RD
WR0, WR1
W
W
W
W
W
W
W
DACK0 to DACK2
DEOP0 to DEOP2
❍ Transfer source area: External, Transfer destination area: Internal RAM
CLK
DREQ0 to DREQ2
Addr pin
S
Data pin
S
S
S
#0H
#1H
#1L
#2H
#2L
#0H
#1H
#1L
#2H
#2L
RD
W
WR0, WR1
W
W
W
W
DACK0 to DACK2
DEOP0 to DEOP2
❍ Transfer source area: Internal RAM, Transfer destination area: External
CLK
DREQ0 to DREQ2
Addr pin
D
D
D
#0H
#1H
#1L
#2H
#2L
Data pin
D
D
D
#0H
#1H
#1L
#2H
#2L
RD
WR0, WR1
W
W
W
W
W
W
W
W
DACK0 to DACK2
DEOP0 to DEOP2
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CHAPTER 16 DMA CONTROLLER
16.7.4 Timing charts for the transfer termination operation
This section covers timing charts for the transfer termination operation.
■ Transfer Termination Operation (When Either Address is Fixed)
❍ Bus width: 16 bits, Data length: 8/16 bits
CLK
Addr pin
D
Data pin
D
S
S
D
S
D
S
D
#0H
#1/2H
#1/2L
D
#0H
#1/2H
#1/2L
W
W
RD
W
WR0, WR1
W
W
W
AKSE = 1
DACK0 to
DACK2
AKDE = 1
Both = 1
EPSE = 1
DEOP0 to
DEOP2
EPDE = 1
Both = 1
❍ Bus width: 16 bits, Data length: 32 bits
CLK
Addr pin
SH
Data pin
SL
SH
SL
DH
DL
DH
DL
SH
SL
SH
SL
DH
DL
#0H
#1/2H
#1/2L
DH
DL
#0H
#1/2H
#1/2L
W
W
RD
WR0, WR1
AKSE = 1
DACK0 to
DACK2
AKDE = 1
Both = 1
EPSE = 1
DEOP0 to
DEOP2
EPDE = 1
Both = 1
378
W
W
W
W
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CHAPTER 16 DMA CONTROLLER
■ Transfer Termination Operation (When both Addresses are Changed)
❍ Bus width: 16 bits, Data length: 8/16 bits
CLK
Addr pin
D
Data pin
D
D
S
S
D
S
S
D
#0H
#1H
#1L
#2H
#2L
D
#0H
#1H
#1L
#2H
#2L
RD
WR0, WR1
W
W
W
W
W
W
W
W
AKSE = 1
DACK0 to
AKDE = 1
DACK2
Both = 1
EPSE = 1
DEOP0 to
EPDE = 1
DEOP2
Both = 1
❍ Bus width: 16 bits, Data length: 32 bits
CLK
Addr pin
SH
Data pin
SL
SH
SL
DH
DL
DH
DL
SH
SL
SH
SL
DH
DL
#0H
#1H
#1L
DH
DL
#0H
#1H
#1L
RD
W
WR0, WR1
W
W
W
W
W
W
AKSE = 1
DACK0 to
AKDE = 1
DACK2
Both = 1
EPSE = 1
DEOP0 to
EPDE = 1
DEOP2
Both = 1
CLK
Addr pin
#2H
#2L
Data pin
#2H
#2L
RD
WR0, WR1
W
W
379
CHAPTER 16 DMA CONTROLLER
380
CHAPTER 17 BIT-SEARCH MODULE
CHAPTER 17
BIT-SEARCH MODULE
This chapter describes the overview of the bit-search module, the register
configuration and functions, and the operation of the bit-search module.
17.1 Overview of the Bit-Search Module
17.2 Registers of the Bit-Search Module
17.3 Operation of the Bit-Search Module
381
CHAPTER 17 BIT-SEARCH MODULE
17.1 Overview of the Bit-Search Module
This module searches for "0" or "1", or for changes in bit values in response to data
loaded into the input register and returns the bit position at which the respective
behavior was detected.
■ Block Diagram of the Bit-search Module
Figure 17.1-1 shows a block diagram of the bit-search module.
Figure 17.1-1 Block Diagram of the Bit-search Module
D-bus
Input latch
Address
decoder
Detection
mode
1 detection register
Bit-search circuit
Result of search
■ Registers of the Bit-search Module
Figure 17.1-2 shows the bit-search module registers.
Figure 17.1-2 Registers of the Bit-search Module
31
382
0
Address: 0003F0H
BSD0
0 detection data register
Address: 0003F4H
BSD1
1 detection data register
Address: 0003F8H
BSDC
Change point detection data register
Address: 0003FCH
BSRR
Detection result register
CHAPTER 17 BIT-SEARCH MODULE
17.2 Registers of the Bit-Search Module
The bit-search module registers include the following four:
• 0-detection data register (BSD0)
• 1-detection data register (BSD1)
• Value-change detection data register (BSDC)
• Detection result register (BSRR)
■ 0 Detection Data Register (BSD0)
The register configuration of the 0 detection data register (BSD0) is given below.
Address
000003F0H
31
0
R/W→ Write only
Initial value→ XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0 detection is performed for a written value.
The initial value of this register upon reset is undefined.
The read value is undefined.
Use the 32-bit data transfer instruction to transfer data. (Do not use the 8-bit and 16-bit data
transfer instructions.)
■ 1 Detection Data Register (BSD1)
The register configuration of the 1 detection data register (BSD1) is given below.
Address
000003F4H
31
0
R/W→ Readable/Writable
Initial value→ XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
Use the 32-bit data transfer instruction to transfer data. (Do not use the 8-bit or 16-bit data
transfer instructions.)
❍ Writing
1 detection is performed for a written value.
383
CHAPTER 17 BIT-SEARCH MODULE
❍ Reading
Data storing the internal status of the bit-search module is read. This function is used to save
and return the original status when e.g. the interrupt handler uses the bit-search module.
The original status can be saved and returned based on the 1 detection data register even if
data has been loaded into the 0 detection or change point detection data register.
The initial value of this register upon reset is undefined.
■ Change Point Detection Data Register (BSDC)
The register configuration of the change point detection data register (BSDC) is given below.
Address
000003F8H
31
0
R/W→ Write only
Initial value→ XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
Change point detection is performed for a written value.
The initial value of this register upon reset is undefined.
The read value is undefined.
Use the 32-bit data transfer instruction to transfer data. (Do not use the 8-bit and 16-bit data
transfer instructions.)
■ Detection Result Register (BSRR)
The register configuration of the detection result register (BSRR) is given below.
Address
31
000003FCH
R/W→ Read only
Initial value→ XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
This register indicates the result of 0, 1 or change point detection.
What detection result is read depends on the data register last loaded.
384
0
CHAPTER 17 BIT-SEARCH MODULE
17.3 Operation of the Bit-Search Module
The bit-search module perform the following operations:
• 0 detection
• 1 detection
• Change point detection
• This section shows the save and return processing.
■ 0 Detection
Data loaded in the 0 detection data register is scanned from the MSB to the LSB, and the
position at which the first 0 is detected is returned. The result of detection is obtained by
unloading the detection result register. Table 17.3-1 shows the relationship between detected
positions and return values.
If the data contains no 0 (i.e., the value is FFFFFFFFH), a value of 32 is returned as the search
result.
[Example of execution]
Written data
11111111111111111111000000000000B
11111000010010011110000010101010B
10000000000000101010101010101010B
11111111111111111111111111111111B
Read value (In decimal notation)
(FFFFF000H)
(F849E0AAH)
(8002AAAAH)
(FFFFFFFFH)
20
5
1
32
■ 1 Detection
Data written in the 1 detection data register is scanned from the MSB to the LSB, and the
position at which first 1 is detected is returned. The result of detection is obtained by unloading
the detection result register. Table 17.3-1 shows the relationship between detected positions
and return values.
If the data contains no 1 (i.e., the value is 00000000H), a value of 32 is returned as the search
result.
[Example of execution]
Written data
00100000000000000000000000000000B
00000001001000110100010101100111B
00000000000000111111111111111111B
00000000000000000000000000000001B
00000000000000000000000000000000B
Read value (In decimal notation)
(20000000H)
(01234567H)
(0003FFFFH)
(00000001H)
(00000000H)
2
7
14
31
32
■ Change Point Detection
Data loaded into the change point detection data register is scanned from bit30 to the LSB for
comparison against the MSB value. The position at which a value different from the MSB is
385
CHAPTER 17 BIT-SEARCH MODULE
detected first is returned. The result of detection is obtained by unloading the detection result
register.
Table 17.3-1 shows the positions of detection and their corresponding return values. If no
change point occurred, a value of "32" is returned. During change point detection, the value "0"
is not returned as result.
[Example of execution]
Read value (In decimal notation)
Written data
00100000000000000000000000000000B
00000001001000110100010101100111B
00000000000000111111111111111111B
00000000000000000000000000000001B
00000000000000000000000000000000B
11111111111111111111000000000000B
11111000010010011110000010101010B
10000000000000101010101010101010B
11111111111111111111111111111111B
(20000000H)
(01234567H)
(0003FFFFH)
(00000001H)
(00000000H)
(FFFFF000H)
(F849E0AAH)
(8002AAAAH)
(FFFFFFFFH)
2
7
14
31
32
20
5
1
32
Table 17.3-1 Bit Positions and Return Values (Decimal)
Detected
bit
position
Return
value
Detected
bit
position
Return
value
Detected
bit
position
Return
value
Detected
bit
position
Return
value
31
0
23
8
15
16
7
24
30
1
22
9
14
17
6
25
29
2
21
10
13
18
5
26
28
3
20
11
12
19
4
27
27
4
19
12
11
20
3
28
26
5
18
13
10
21
2
29
25
6
17
14
9
22
1
30
24
7
16
15
8
23
0
31
Non
existent
32
■ Processing for Saving and Restoring
If you must save and restore the internal status of the bit-search module owing to use of the bitsearch module in the interrupt handler, follow the procedure below.
1. Unload the 1 detection data register, and save the read contents. (Save)
2. Use the bit-search module.
3. Load the 1 detection data register with the data saved in step 1. (Restore)
The value obtained by the above operations when the detection result register is unloaded next
depends on the contents written to the bit-search module before step 1).
Even if the data register for which the last load operation is performed was the one for which
zero or a change point was detected, the above procedure provides the correct return.
386
CHAPTER 18 PERIPHERAL STOP CONTROL
CHAPTER 18
PERIPHERAL STOP CONTROL
This chapter provides an overview of peripheral stop control and explains the
configuration and the function of registers.
18.1 Overview of Peripheral Stop Control
18.2 Peripheral Stop Control Registers
387
CHAPTER 18 PERIPHERAL STOP CONTROL
18.1 Overview of Peripheral Stop Control
The peripheral stop control stops the clocks for unused resources, which reduces
power consumption.
■ Peripheral Stop Control Registers
Figure 18.1-1 lists the peripheral stop control registers.
Figure 18.1-1 Peripheral Stop Control Registers
Address
000090H
bit7....................................bit0
STPR0
000091H
STPR1
000092H
STPR2
■ Operation of Peripheral Stop Control Registers and Applicable Notes
The clock for the resource corresponding to each bit can be stopped.
Operation of a resource whose clock is stopped cannot be started. Do not access the register
for a resource whose operation has been stopped.
Do not use this function to stop the operation of a resource that is currently in use.
388
CHAPTER 18 PERIPHERAL STOP CONTROL
18.2 Peripheral Stop Control Registers
The peripheral stop control registers include the following three:
• Stop control register 0 (STPR0)
• Stop control register 1 (STPR1)
• Stop control register 2 (STPR2)
■ Stop Control Register 0 (STPR0)
Stop control register 0 (STPR0) has the following bit configuration:
Address
000090H
bit7
bit6
bit5
bit4
ST07 ST06 ST05 ST04
bit3
bit2
bit1
bit0
Initial value
−
−
−
−
0000----B (R/W)
[bit7] ST07
0: Enables UART0 operation.
1: Disables UART0 operation.
[bit6] ST06
0: Enables UART1 operation.
1: Disables UART1 operation.
[bit5] ST05
0: Enables UART2 operation.
1: Disables UART2 operation.
[bit4] ST04
0: Enables UART3 operation.
1: Disables UART3 operation.
389
CHAPTER 18 PERIPHERAL STOP CONTROL
■ Stop Control Register 1 (STPR1)
Stop control register 1 (STPR1) has the following bit configuration:
Address
000091H
bit7
bit6
bit5
bit4
bit3
ST17 ST16 ST15 ST14 ST13
[bit7] ST17
0: Enables reload timer 0 operation.
1: Disables reload timer 0 operation.
[bit6] ST16
0: Enables reload timer 1 operation.
1: Disables reload timer 1 operation.
[bit5] ST15
0: Enables reload timer 2 operation.
1: Disables reload timer 2 operation.
[bit4] ST14
0: Enables reload timer 3 operation.
1: Disables reload timer 3 operation.
[bit3] ST13
0: Enables the free-run timer.
1: Disables the free-run timer.
[bit1] ST11
0: Enables up-down counter operation.
1: Disables up-down counter operation.
[bit0] ST10
0: Enables A/D converter operation.
1: Disables A/D converter operation.
390
bit2
−
bit1
bit0
ST11 ST10
Initial value
00000-00B (R/W)
CHAPTER 18 PERIPHERAL STOP CONTROL
■ Stop Control Register 2 (STPR2)
Stop control register 2 (STPR2) has the following bit configuration:
Address
000092H
bit7
bit6
bit5
bit4
bit3
bit2
ST27 ST26 ST25 ST24 ST23 ST22
bit1
bit0
Initial value
−
−
000000--B (R/W)
[bit7] ST27
0: Enables PPG0 operation.
1: Disables PPG0 operation.
[bit6] ST26
0: Enables PPG1 operation.
1: Disables PPG1 operation.
[bit5] ST25
0: Enables PPG2 operation.
1: Disables PPG2 operation.
[bit4] ST24
0: Enables PPG3 operation.
1: Disables PPG3 operation.
[bit3] ST23
0: Enables PPG4 operation.
1: Disables PPG4 operation.
[bit2] ST22
0: Enables PPG5 operation.
1: Disables PPG5 operation.
391
CHAPTER 18 PERIPHERAL STOP CONTROL
392
CHAPTER 19 SERIAL - START
CHAPTER 19
SERIAL - START
This chapter provides an outline of the serial-start and describes the communication
mode.
19.1 Outline of Serial-Start and How to Set
19.2 Communication Mode of Serial-Start
393
CHAPTER 19 SERIAL - START
19.1 Outline of Serial-Start and How to Set
This mode is suitable for writing to the internal RAM (2K bytes) with a internal
dedicated RAM and starting the RAM program. This model can perform the
communication with the internal UARTch1 and be used for the data transfer to the
external flash memory and so on. Either synchronous or asynchronous
communication can be selected by setting the external pin in this model. Either baud
rate of 9600bps for machine clock of 25MHz (the oscillation frequency: 12.5MHz) or
baud rate of 9600bps for machine clock of 33MHz (the oscillation frequency: 16.5MHz)
can be selected in asynchronous communication.
NOTE:
In case of machine clock of 36MHz (the oscillation frequency: 18MHz), the serial-start
in asynchronous communication is disabled.
■ How to Set
Table 19.1-1 How to Set
The external pin name
Specification
394
MD2
MD1
MD0
PG5
PG4
PG3
Asynchronous communication mode
(machine clock: 33MHz)
1
1
0
1
0
0
Asynchronous communication mode
(machine clock 25MHz)
1
1
0
1
0
1
Synchronous communication mode
1
1
0
1
1
0
CHAPTER 19 SERIAL - START
19.2 Communication Mode of Serial-Start
The following three modes can be selected for the communication mode of the serialstart:
• Asynchronous communication mode (machine clock: 33MHz)
• Asynchronous communication mode (machine clock: 25MHz)
• Synchronous communication mode
■ Communication Mode of Serial-Start
❍ Asynchronous communication mode (machine clock: 33MHz)
The serial communication can be performed by using the asynchronous mode (normal mode) of
UART ch1. The value of baud rate is 9600bps in case of the machine clock of 33MHz (the
external crystal oscillator: 16.5MHz). The data length of 8 bits, the stop-bit length of 1 bit, no
parity error checking and LSB first must be set for the serial-start.
❍ Asynchronous communication mode (machine clock: 25MHz)
The serial communication can be performed by using the asynchronous mode (normal mode) of
UART ch1. The value of baud rate is 9600bps in case of the machine clock of 25MHz (the
external crystal oscillator: 12.5MHz). The data length of 8 bits, the stop-bit length of 1 bit, no
parity error checking and LSB first must be set for the serial-start.
❍ Synchronous communication mode
The serial communication can be performed by using the synchronous mode (normal mode) of
UART ch1. Any value of baud rate can be selected by inputting the external clock. (The external
clock frequency becomes the value of baud rate as it is.) The maximum inputting value of the
external clock is one-eighth (1/8) the operating clock frequency of the peripheral system. (The
fastest speed of PLL system must be setting for the operating clock frequency of the peripheral
system.) The data length of 8 bits, the stop-bit length of 1 bit, no parity error checking and LSBfirst must be set for the serial-start.
In each mode, the following three informations of the download are transferred one byte by one
byte in order of high-order byte to the FR side and the SUM-checking data (low-order eight bits
of data summing up all bytes) are transferred. Afterwards, the download routine toward the RAM
is executed.
•
The command data (00H)
•
The destination RAM address of 4 bytes (00080400H to 000807FFH) for the download
•
The number of the download bytes of 4 bytes (Maximum value: 000003FFH)
Then the download data toward the RAM are transferred one byte by one byte in order of highorder byte to the FR side and the SUM-checking data are transferred. After the transfer, the
download program in the RAM is executed.
For example, Table 19.2-1 shows the transfer of 5BH bytes size data to the address 80400H of
the RAM in asynchronous communication mode.
395
CHAPTER 19 SERIAL - START
Table 19.2-1 Transfer of 5BH Bytes Size Data to the Address 80400H of the RAM in
Asynchronous Communication Mode
PC etc.
FR side
(1)
00H
-->
-
(2)
00H
-->
-
(3)
08H
-->
-
(4)
04H
-->
-
(5)
00H
-->
-
(6)
00H
-->
-
(7)
00H
-->
-
(8)
00H
-->
-
(9)
5BH
-->
-
SUM-checking data
(10)
67H
-->
-
Acknowledge response from the FR side
(11)
-
<--
01H
Send data
(12)
DATA
-->
-
SUM-checking data
(13)
*
-->
-
Command data
Destination address for download
The number of download byte
(91 bytes)
* : low-order 8 bits of data summed up all sent data
Refer to the flowchart for the program in the dedicated ROM as shown following pages about
detail operations. And refer to the chapter 15 "UART" and the term "Pin status in serial-start
mode" of the appendix C "Pin Status in Each CPU State" about detail operations of the UART
and all pins status.
396
CHAPTER 19 SERIAL - START
Figure 19.2-1 Main Program Flowchart
START
PG5 to PG3=3'b100?
PG5 to PG3=3'b101?
PG5 to PG3=3'b110?
Yes
Asynchronous
Communication Mode(33MHz)
Yes
Asynchronous
Communication Mode(25MHz)
Yes
Synchronous
Communication Mode
Prohibition
Asynchronous
Communication Mode(25MHz)
Note: Setting of UART1
In Asynchronous Communication Mode(33MHz)
Asynchronous
Communication Mode(33MHz)
Synchronous
Communication Mode
Setting of Gear (PLL System:fastest speed)
Setting of UART1 (* Note)
MAIN
Receipt of Command
Received Command(1)=00H?
(Download)
No
• Asynchronous Mode (Using Internal Timer)
• Baud Rate: 9600bps
(External Oscillator: 16.5MHz)
• Data Length: 8 bits
• Stop-bit Length: 1 bit
• No Parity Error Checking
In Asynchronous Communication Mode(25MHz)
• Asynchronous Mode (Using Internal Timer)
• Baud Rate: 9600bps
(External Oscillator: 12.5MHz)
• Data Length: 8 bits
• Stop-bit Length: 1 bit
• No Parity Error Checking
In Synchronous Communication Mode
• Synchronous Mode (Using Internal Timer)
• Data Length: 8 bits
• No Parity Error Checking
Download
JUMP to RAM
Command Error
397
CHAPTER 19 SERIAL - START
■ Command List
Table 19.2-2 shows the list of the commands issued toward the FR side and the responses
signal from the FR side.
Table 19.2-2 Command List
FR side
PC etc.
Download
-
<--
00H
Reset
-
<--
18H
Command
Responses of
received
command
398
Command error
(Received command & F0H) | 04H
-->
-
SUM-checking error
(Received command(00H) & F0H) | 02H
-->
-
Receipt of RESET command
11H
-->
-
Receipt of Download
command
01H
-->
-
CHAPTER 19 SERIAL - START
Figure 19.2-2 Subroutine "Receipt of Command" Flowchart
[in Asynchronous Communication Mode (Common for 25MHz or 33MHz)]
Receipt of Command
Receipt of 1 byte data (command data)
Received the data ?
No
Receipt of one byte data [1] (command data)
Receipt of 8 bytes data (download information data)
Destination address of the download: 4 bytes
+
The number of the download bites: 4 bytes
The received
data [1] = 18H ?
Yes
RESET
No
Received the data ?
Receipt of one byte data (2) to (9) (download information data)
increase the address point of stored data
Count receipt times
No
Receipt times = 8 ?
Receipt of 1 byte data (SUM check data)
Received the data ?
No
Receipt of one byte data (10) (SUM check data)
Sum data (1) to (9) and generate lower 8-bit data (α)
[10] = α ? (SUM checking)
No
SUM check error
EXIT
399
CHAPTER 19 SERIAL - START
Figure 19.2-3 Subroutine "DOWN LOAD" Flowchart
[in Asynchronous Communication Mode (Common for 25MHz or 33MHz)]
DOWN LOAD
Send of 1 byte data
(Normal response for receipt of command data)
Send of 1 byte data (01H)
Download to RAM
Received the data ?
No
Receipt of one byte data
Increase the address point of stored data
Count receipt times
Receipt times =
Number of download bytes ?
No
Receipt of 1 byte data (SUM check data)
Received the data ?
No
Receipt of one byte data (13) (SUM check data)
Sum all receipt data and generate lower-order 8-bit data (β)
[13] = β ? (SUM checking)
EXIT
400
No
SUM check error
CHAPTER 19 SERIAL - START
Figure 19.2-4 Subroutine "Command Error" Flowchart
[in Asynchronous Communication Mode (Common for 25MHz or 33MHz)]
Send of 1 byte data
(abnormal response for receipt of command data)
Command Error
Generate send data
Extract receipt data of command
[(receipt data of command) & (F0H)] | (04H)
Send of 1 byte data
MAIN
Figure 19.2-5 Subroutine "SUM-checking Error" Flowchart
[in Asynchronous Communication Mode (Common for 25MHz or 33MHz)]
Send of 1 byte data
(abnormal response for SUM checking)
SUM check Error
Generate send data
Extract receipt data of command
[(receipt data of command) & (F0H)] | (02H)
Send of 1 byte data
MAIN
Figure 19.2-6 Subroutine "RESET" Flowchart
[in Asynchronous Communication Mode (Common for 25MHz or 33MHz)]
Send of 1 byte data
(Normal response for receipt of RESET command data)
RESET
Send of 1 byte data (11H)
MAIN
401
CHAPTER 19 SERIAL - START
Figure 19.2-7 Subroutine "Receipt of Command" Flowchart
[in Synchronous Communication Mode]
Receipt of
Command
"L" output of PH4/SOT1
Send of 1 byte data (dummy data): 00H
Receipt of 1 byte data (command data)
Received the data ?
No
Receipt of one byte data [1] (command data)
The received
data [1] = 18H ?
Yes
RESET
Send of 1 byte data (dummy data) : 00H
Inverted output of PH4/SOT1
Receipt of 8 bytes data (download information data)
Destination address of the download: 4 bytes
+
The number of the download bytes: 4 bytes
No
Received the data ?
Send of 1 byte data (dummy data) : 00H
Inverted output of PH4/SOT1
Receipt of one byte data (2) to (9) (download information data)
Increase the address point of stored data
Count receipt times
Receipt times = 8 ?
No
Receipt of 1 byte data (SUM check data)
Received the data ?
No
"H" output of PH4/SOT1
Receipt of one byte data (10) (SUM check data)
Sum data (1) to (9) and generate lower-order 8-bit data (α)
(10)= α ? (SUM checking)
EXIT
402
No
SUM check error
CHAPTER 19 SERIAL - START
Figure 19.2-8 Subroutine "DOWN LOAD" Flowchart [in Synchronous Communication Mode]
DOWN LOAD
Send of 1 byte data
(Normal response for receipt of command data)
"L" output of PH4/SOT1
Enable serial output
"H" output of PH4/SOT1
Send of 1 byte data (01H)
No
Received the data ?
Receipt of dummy data
Switch general-purpose input/output (disable serial output)
Download
Receipt of dummy data
Inverted output of PH4/SOT1
B
No
Received the data ?
Receipt of dummy data
Inverted output of PH4/SOT1
A
(Continued)
403
CHAPTER 19 SERIAL - START
(Continued)
A
Download to RAM
No
Received the data ?
Receipt of one byte data
Increase the address point of stored data
Count receipt times
No
Receipt times =
The number of the download bytes ?
B
Receipt of 1 byte data (SUM check data)
No
Received the data ?
"H" output of PH4/SOT1
Receipt of one byte data (13)
Sum all receipt data and extract lower-order 8-bit data (β)
(13) = β ? (SUM checking)
EXIT
404
No
SUM check error
CHAPTER 19 SERIAL - START
Figure 19.2-9 Subroutine "Command Error" Flowchart [in Synchronous Communication Mode]
Send of 1 byte data
(abnormal response for receipt of command data)
Command Error
Generate send data
Extract receipt data of command
[(receipt data of command) & (F0H)] | (04H)
"L" output of PH4/SOT1
Enable serial output
"H" output of PH4/SOT1
Send of 1 byte data
Received the data ?
No
Receipt of dummy data
Switch general-purpose input/output (disable serial output)
MAIN
405
CHAPTER 19 SERIAL - START
Figure 19.2-10 Subroutine "SUM-checking Error" Flowchart
[in Synchronous Communication Mode]
Send of 1 byte data
(abnormal response for SUM checking)
SUM check Error
Generate send data
Extract receipt data of command
[(receipt data of command) & (F0H)] | (02H)
"L" output of PH4/SOT1
Enable serial output
"L" output of PH4/SOT1
Send of 1 byte data
No
Received the data ?
Receipt of dummy data
Switch general-purpose input/output (disable serial output)
MAIN
406
CHAPTER 19 SERIAL - START
Figure 19.2-11 Subroutine "RESET" Flowchart
[in Synchronous Communication Mode]
Send of 1 byte data
(normal response for receipt of RESET command data)
RESET
"L" output of PH4/SOT1
Enable serial output
"H" output of PH4/SOT1
Send of 1 byte data (11H)
Received the data ?
No
Receipt of dummy data
Switch general-purpose input/output (disable serial output)
MAIN
407
CHAPTER 19 SERIAL - START
408
APPENDIX
These appendixes provide the I/O map, notes on using the little-endian area, and
instruction lists. They also explain interrupt vectors and the pin status in each CPU
state.
APPENDIX A I/O Map
APPENDIX B Interrupt Vectors
APPENDIX C Pin Status in Each CPU State
APPENDIX D Notes on Using the Little-Endian Area
APPENDIX E Instruction Lists
409
APPENDIX A I/O Map
APPENDIX A I/O Map
Figure A-1 shows how to use the I/O map, and Table A-1 shows the I/O map itself
(which indicates the correspondence between the memory area and peripheral
resources for each register).
■ How to Use the I/O Map
Figure A-1
How to Use the I/O
register
address
+0
000000 H
+1
PDR3 [R/W]
PDR2 [R/W]
+2
________
+3
________
block
Port Data Register
XXXXXXXX XXXXXXXX
Read/write attribute
Initial register value after reset
Register name
(the register in column 1 has a number of the type 4n address, the register
in column 2 has a number of the type 4n+2 address, etc.)
Leftmost register address.
(The register in column 1 becomes the MSB side of data in word access.)
Note:
The bit values of a register have the following initial values:
1: Initial value 1
0: Initial value 0
X: Initial value X
-: No register exists physically at this position.
410
APPENDIX A I/O Map
■ I/O Map
Table A-1 I/O Map (1 / 6)
Register
Address
Block
+0
+1
+2
+3
000000H
PDR3 [R/W]
XXXXXXXX
PDR2 [R/W]
XXXXXXXX
-
-
000004H
-
PDR6 [R/W]
XXXXXXXX
PDR5 [R/W]
XXXXXXXX
PDR4 [R/W]
XXXXXXXX
PDR8 [R/W]
-XXXXXXX
-
000008H
Port data
register
-
00000CH
000010H
PDRF [R/W]
---XXXXX
PDRE [R/W]
XXXXXXXX
PDRD [R/W]
XXXXXXXX
PDRC [R/W]
XXXXXXXX
000014H
PDRJ [R/W]
------11
PDRI [R/W]
--XXXXXX
PDRH [R/W]
--XXXXXX
PDRG [R/W]
--XXXXXX
PDRL [R/W]
XXXXXXXX
PDRK [R/W]
XXXXXXXX
000018H
-
00001CH
SSR0 [R/W, R]
00001000
SIDR0/SODR0[R/W]
XXXXXXXX
SCR0 [R/W, W]
00000100
SMR0 [R/W]
00000-00
UART0
000020H
SSR1 [R/W, R]
00001000
SIDR1/SODR1[R/W]
XXXXXXXX
SCR1 [R/W, W]
00000100
SMR1 [R/W]
00000-00
UART1
000024H
SSR2 [R/W, R]
00001000
SIDR2/SODR2[R/W]
XXXXXXXX
SCR2 [R/W, W]
00000100
SMR2 [R/W]
00000-00
UART2
000028H
SSR3 [R/W, R]
00001000
SIDR3/SODR3[R/W]
XXXXXXXX
SCR3 [R/W, W]
00000100
SMR3 [R/W]
00000-00
UART3
00002CH
TMRLR0
[W]
XXXXXXXX XXXXXXXX
TMR0
[R]
XXXXXXXX XXXXXXXX
000030H
-
TMCSR0
[R/W]
----0000 00000000
000034H
TMRLR1
[W]
XXXXXXXX XXXXXXXX
TMR1
[R]
XXXXXXXX XXXXXXXX
000038H
-
TMCSR1
[R/W]
----0000 00000000
00003CH
TMRLR2
[W]
XXXXXXXX XXXXXXXX
TMR2
[R]
XXXXXXXX XXXXXXXX
000040H
-
TMCSR2
[R/W]
----0000 00000000
Reload timer
0
Reload timer
1
Reload timer
2
411
APPENDIX A I/O Map
Table A-1 I/O Map (2 / 6)
Register
Address
Block
+0
+1
+2
+3
000044H
TMRLR3
[W]
XXXXXXXX XXXXXXXX
TMR3
[R]
XXXXXXXX XXXXXXXX
000048H
-
TMCSR3
[R/W]
----0000 00000000
00004CH
CDCR1 [R/W]
0---0000
-
CDCR0 [R/W]
0---0000
-
000050H
CDCR3 [R/W]
0---0000
-
CDCR2 [R/W]
0---0000
-
000054H
to
000058H
-
Reload timer
3
Communication prescaler
1
Reserved
00005CH
RCR1 [W]
00000000
RCR0 [W]
00000000
UDCR1 [R]
00000000
UDCR0 [R]
00000000
000060H
CCRH0 [R/W]
00000000
CCRL0 [R/W, W]
-000X000
-
CSR0 [R/W, R] 8/16-bit up/
down counter
00000000
000064H
CCRH1 [R/W]
-0000000
CCRL1 [R/W, W]
-000X000
-
CSR1 [R/W, R]
00000000
000068H
IPCP1
[R]
XXXXXXXX XXXXXXXX
IPCP0
[R]
XXXXXXXX XXXXXXXX
00006CH
IPCP3
[R]
XXXXXXXX XXXXXXXX
IPCP2
[R]
XXXXXXXX XXXXXXXX
000070H
-
000074H
OCCP1
[R/W]
XXXXXXXX XXXXXXXX
OCCP0
[R/W]
XXXXXXXX XXXXXXXX
000078H
OCCP3
[R/W]
XXXXXXXX XXXXXXXX
OCCP2
[R/W]
XXXXXXXX XXXXXXXX
00007CH
OCCP5
[R/W]
XXXXXXXX XXXXXXXX
OCCP4
[R/W]
XXXXXXXX XXXXXXXX
000080H
OCCP7
[R/W]
XXXXXXXX XXXXXXXX
OCCP6
[R/W]
XXXXXXXX XXXXXXXX
000084H
OCS2,3 [R/W]
XXX00000 0000XX00
OCS0, 1 [R/W]
XXX00000 0000XX00
000088H
OCS6, 7 [R/W]
XXX00000 0000XX00
OCS4, 5 [R/W]
XXX00000 0000XX00
00008CH
TCDT [R/W]
00000000 00000000
TCCS [R/W]
0------- 00000000
ICS23 [R/W]
00000000
16-bit ICU
ICS01 [R/W]
00000000
-
16-bit OCU
000090H
412
STPR0 [R/W]
0000----
STPR1 [R/W]
00000-00
STPR2 [R/W]
000000--
16-bit freerun timer
-
Stop registers
0, 1 and 2
APPENDIX A I/O Map
Table A-1 I/O Map (3 / 6)
Register
Address
Block
+0
+1
000094H
GCN1 [R/W]
00110010 00010000
000098H
PTMR0
[R]
11111111 11111111
00009CH
PDUT0
[W]
XXXXXXXX XXXXXXXX
0000A0H
PTMR1 [R]
11111111 11111111
0000A4H
PDUT1
[W]
XXXXXXXX XXXXXXXX
0000A8H
PTMR2
[R]
11111111 11111111
0000ACH
PDUT2
[W]
XXXXXXXX XXXXXXXX
0000B0H
PTMR3
[R]
11111111 11111111
0000B4H
PDUT3
[W]
XXXXXXXX XXXXXXXX
0000B8H
PTMR4
[R]
11111111 11111111
0000BCH
PDUT4
[W]
XXXXXXXX XXXXXXXX
0000C0H
PTMR5
[R]
11111111 11111111
0000C4H
PDUT5
[W]
XXXXXXXX XXXXXXXX
+2
+3
-
GCN2 [R/W]
00000000
PPG ctl
PCSR0
[W]
XXXXXXXX XXXXXXXX
PPG0
PCNH0 [R/W]
0000000-
PCNL0 [R/W]
00000000
PCSR1
[W]
XXXXXXXX XXXXXXXX
PPG1
PCNH1 [R/W]
0000000-
PCNL1 [R/W]
00000000
PCSR2
[W]
XXXXXXXX XXXXXXXX
PPG2
PCNH2 [R/W]
0000000-
PCNL2 [R/W]
00000000
PCSR3
[W]
XXXXXXXX XXXXXXXX
PPG3
PCNH3 [R/W]
0000000-
PCNL3 [R/W]
00000000
PCSR4
[W]
XXXXXXXX XXXXXXXX
PPG4
PCNH4 [R/W]
0000000-
PCNL4 [R/W]
00000000
PCSR5
[W]
XXXXXXXX XXXXXXXX
PPG5
0000C8H
EIRR0 [R/W]
00000000
ENIR0 [R/W]
00000000
PCNH5 [R/W]
0000000-
PCNL5 [R/W]
00000000
EIRR1 [R/W]
00000000
ENIR1 [R/W]
00000000
Exit int
ELVR0 [R/W]
00000000 00000000
0000CCH
0000D0H
to
0000D8H
ELVR1 [R/W]
00000000 00000000
-
Reserved
-
DACR2 [R/W]
-------0
DACR1 [R/W]
-------0
DACR0 [R/W]
-------0
0000E0H
-
DADR2 [R/W]
XXXXXXXX
DADR1 [R/W]
XXXXXXXX
DADR0 [R/W]
XXXXXXXX
0000E4H
ADCR [R, W]
00101-XX XXXXXXXX
ADCS1 [R/W, W]
00000000
ADCS0 [R/W]
00000000
0000DCH
D/A converter
A/D converter
413
APPENDIX A I/O Map
Table A-1 I/O Map (4 / 6)
Register
Address
0000E8H
Block
+0
+1
+2
+3
-
-
-
AICR [R/W]
00000000
0000ECH
to
000 F0H
-
Reserved
0000F4H
PCRI [R/W]
--000000
PCRH [R/W]
--000000
0000F8H
OCRI [R/W]
--000000
OCRH [R/W]
--000000
0000FCH
DDRF [R/W]
---00000
DDRE [R/W]
00000000
DDRD [R/W]
00000000
DDRC [R/W]
00000000
000100H
-
DDRI [R/W]
-0000000
DDRH [R/W]
--000000
DDRG [R/W]
--000000
DDRL [R/W]
00000000
DDRK [R/W]
00000000
000104H
PCRD [R/W]
00000000
PCRC [R/W]
00000000
Pull-up
control
Open-drain
control
-
-
Analog input
control
Data direction
register
000108H
to
0001FCH
-
000200H
DPDP [R/W]
-------- -------- --------- -0000000
000204H
DACSR [R/W]
00000000 00000000 00000000 00000000
000208H
DATCR [R/W]
XXXXXXXX XXXX0000 XXXX0000 XXXX0000
00020CH
to
0003E0H
-
Reserved
0003E4H
ICHCR [R/W]
-------- -------- -------- --000000
Instruction
Cache
0003E8H
to
0003ECH
-
Reserved
0003F0H
BSD0 [W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0003F4H
BSD1 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0003F8H
BSDC [W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0003FCH
BSRR [R]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
414
Reserved
DMAC
Bit search
module
APPENDIX A I/O Map
Table A-1 I/O Map (5 / 6)
Register
Address
Block
+0
+1
+2
+3
000400H
ICR00 [R/W]
----1111
ICR01 [R/W]
----1111
ICR02 [R/W]
----1111
ICR03 [R/W]
----1111
000404H
ICR04 [R/W]
----1111
ICR05 [R/W]
----1111
ICR06 [R/W]
----1111
ICR07 [R/W]
----1111
000408H
ICR08 [R/W]
----1111
ICR09[R/W]
----1111
ICR10 [R/W]
----1111
ICR11 [R/W]
----1111
00040CH
ICR12 [R/W]
----1111
ICR13 [R/W]
----1111
ICR14 [R/W]
----1111
ICR15 [R/W]
----1111
000410H
ICR16 [R/W]
----1111
ICR17 [R/W]
----1111
ICR18 [R/W]
----1111
ICR19 [R/W]
----1111
000414H
ICR20 [R/W]
----1111
ICR21 [R/W]
----1111
ICR22 [R/W]
----1111
ICR23 [R/W]
----1111
000418H
ICR24 [R/W]
----1111
ICR25 [R/W]
----1111
ICR26 [R/W]
----1111
ICR27 [R/W]
----1111
00041CH
ICR28 [R/W]
----1111
ICR29 [R/W]
----1111
ICR30 [R/W]
----1111
ICR31 [R/W]
----1111
000420H
ICR32 [R/W]
----1111
ICR33 [R/W]
----1111
ICR34 [R/W]
----1111
ICR35 [R/W]
----1111
000424H
ICR36 [R/W]
----1111
ICR37 [R/W]
----1111
ICR38 [R/W]
----1111
ICR39 [R/W]
----1111
000428H
ICR40 [R/W]
----1111
ICR41 [R/W]
----1111
ICR42 [R/W]
----1111
ICR43 [R/W]
----1111
00042CH
ICR44 [R/W]
----1111
ICR45 [R/W]
----1111
ICR46 [R/W]
----1111
ICR47 [R/W]
----1111
000430H
DICR [R/W]
-------0
HRCL [R/W]
----1111
000434H
to
00047CH
-
RSRR/WTCR [R, W]
1-XXX-00
STCR [R/W, W]
000111--
000484H
GCR [R/W, R]
110011-1
WPR [W]
XXXXXXXX
000488H
PCTR [R/W]
00XX0XXX
00048CH
to
0005FCH
Delay
-
000480H
Interrupt
control unit
Reserved
PDRR [R/W]
----0000
CTBR [W]
XXXXXXXX
Clock control
unit
-
-
PLL control
Reserved
415
APPENDIX A I/O Map
Table A-1 I/O Map (6 / 6)
Register
Address
Block
+0
+1
+2
+3
000600H
DDR3 [W]
00000000
DDR2 [W]
00000000
-
-
000604H
-
DDR6 [W]
00000000
DDR5 [W]
00000000
DDR4 [W]
00000000
000608H
-
-
-
DDR8 [W]
-0000000
00060CH
ASR1 [W]
00000000 00000001
AMR1 [W]
00000000 00000000
000610H
ASR2 [W]
00000000 00000010
AMR2 [W]
00000000 00000000
000614H
ASR3 [W]
00000000 00000011
AMR3
[W]
00000000 00000000
000618H
ASR4 [W]
00000000 00000100
AMR4
[W]
00000000 00000000
00061CH
ASR5 [W]
00000000 00000101
AMR5
[W]
00000000 00000000
Data direction
register
T-unit
000620H
AMD0 [R/W]
---00111
000624H
AMD5 [R/W]
0--00000
AMD1 [R/W]
0--00000
EPCR1 [W]
-------- 11111111
-
00062CH
Reserved
PCR6 [R/W]
00000000
-
000634H
to
0007F8H
0007FCH
AMD4 [R/W]
0--00000
-
EPCR0 [W]
----1100 -1111111
000628H
000630H
AMD32 [R/W]
00000000
Pull-up
control
-
-
Reserved
LER [W]
-----000
-
MODR [W]
XXXXXXXX
Little-endian
register
mode register
Notes:
1. Do not execute a read-modify-write (RMW) instruction for a register with a write-only bit.
2. Read-modify-write (RMW) instructions:
AND Rj, @Ri
ANDH Rj, @Ri
ANDB Rj, @Ri
BANDL #u4, @Ri
BANDH #u4, @Ri
OR Rj, @Ri
ORH Rj, @Ri
ORB Rj, @Ri
BORL #u4, @Ri
3. Reserved, or data in (-) areas is undefined.
416
BORH #u4, @Ri
EOR Rj, @Ri
EORH Rj, @Ri
EORB Rj, @Ri
BEORL #u4, @Ri
BEORH #u4, @Ri
APPENDIX B Interrupt Vectors
APPENDIX B Interrupt Vectors
Table B-1 is the interrupt vector table. This table lists the MB91151A interrupt sources
and assignment of interrupt vectors to interrupt control registers.
■ Interrupt Vectors
•
ICR0 to ICR47: Register located in the interrupt controller. This register sets an interrupt
level for each interrupt request. An ICR is prepared for each interrupt
request.
•
TBR: Register that indicates the first address of the EIT vector table. The address obtained
by adding the contents of the TBR and the offset value determined for each EIT
interrupt source is a vector address.
The 1K byte area starting from the address indicated by the TBR is the EIT vector area.
Each vector has a size of four bytes, and the relationship between vector numbers and vector
addresses is as follows:
vctadr = TBR + vctofs = TBR + (3FCH - 4 × vct)
vctadr: Vector address
vctofs: Vector offset
vct: Vector number
Table B-1 Interrupt Vectors (1 / 4)
Interrupt number
Interrupt
level
Offset
TBR default
address
00
-
3FCH
000FFFFCH
1
01
-
3F8H
000FFFF8H
System-reserved
2
02
-
3F4H
000FFFF4H
System-reserved
3
03
-
3F0H
000FFFF0H
System-reserved
4
04
-
3ECH
000FFFECH
System-reserved
5
05
-
3E8H
000FFFE8H
System-reserved
6
06
-
3E4H
000FFFE4H
System-reserved
7
07
-
3E0H
000FFFE0H
System-reserved
8
08
-
3DCH
000FFFDCH
System-reserved
9
09
-
3D8H
000FFFD8H
System-reserved
10
0A
-
3D4H
000FFFD4H
System-reserved
11
0B
-
3D0H
000FFFD0H
System-reserved
12
0C
-
3CCH
000FFFCCH
Interrupt source
Decimal
notation
Hexadecimal
notation
Reset
0
System-reserved
417
APPENDIX B Interrupt Vectors
Table B-1 Interrupt Vectors (2 / 4)
Interrupt number
Interrupt
level
Offset
TBR default
address
0D
-
3C8H
000FFFC8H
14
0E
-
3C4H
000FFFC4H
System-reserved
15
0F
-
3C0H
000FFFC0H
External interrupt 0
16
10
ICR00
3BCH
000FFFBCH
External interrupt 1
17
11
ICR01
3B8H
000FFFB8H
External interrupt 2
18
12
ICR02
3B4H
000FFFB4H
External interrupt 3
19
13
ICR03
3B0H
000FFFB0H
External interrupt 4
20
14
ICR04
3ACH
000FFFACH
External interrupt 5
21
15
ICR05
3A8H
000FFFA8H
External interrupt 6
22
16
ICR06
3A4H
000FFFA4H
External interrupt 7
23
17
ICR07
3A0H
000FFFA0H
External interrupts 8 to 15
24
18
ICR08
39CH
000FFF9CH
System-reserved
25
19
ICR09
398H
000FFF98H
UART0 (reception completed)
26
1A
ICR10
394H
000FFF94H
UART1 (reception completed)
27
1B
ICR11
390H
000FFF90H
UART2 (reception completed)
28
1C
ICR12
38CH
000FFF8CH
UART3 (reception completed)
29
1D
ICR13
388H
000FFF88H
System-reserved
30
1E
ICR14
384H
000FFF84H
UART0 (transmission
completed)
31
1F
ICR15
380H
000FFF80H
UART1 (transmission
completed)
32
20
ICR16
37CH
000FFF7CH
UART2 (transmission
completed)
33
21
ICR17
378H
000FFF78H
UART3 (transmission
completed)
34
22
ICR18
374H
000FFF74H
System-reserved
35
23
ICR19
370H
000FFF70H
DMAC (ended with error)
36
24
ICR20
36CH
000FFF6CH
Reload timer 0
37
25
ICR21
368H
000FFF68H
Reload timer 1
38
26
ICR22
364H
000FFF64H
Reload timer 2
39
27
ICR23
360H
000FFF60H
Interrupt source
Decimal
notation
Hexadecimal
notation
System-reserved
13
Undefined instruction
exception
418
APPENDIX B Interrupt Vectors
Table B-1 Interrupt Vectors (3 / 4)
Interrupt number
Interrupt
level
Offset
TBR default
address
28
ICR24
35CH
000FFF5CH
41
29
ICR25
358H
000FFF58H
A/D
42
2A
ICR26
354H
000FFF54H
PPG0
43
2B
ICR27
350H
000FFF50H
PPG1
44
2C
ICR28
34CH
000FFF4CH
PPG2
45
2D
ICR29
348H
000FFF48H
PPG3
46
2E
ICR30
344H
000FFF44H
PPG4
47
2F
ICR31
340H
000FFF40H
PPG5
48
30
ICR32
33CH
000FFF3CH
U/D counter 0 (compare/
underflow, overflow, up-down
inversion)
49
31
ICR33
338H
000FFF38H
U/D counter 1 (compare/
underflow, overflow, up-down
inversion)
50
32
ICR34
334H
000FFF34H
ICU0 (fetch)
51
33
ICR35
330H
000FFF30H
ICU1 (fetch)
52
34
ICR36
32CH
000FFF2CH
ICU2 (fetch)
53
35
ICR37
328H
000FFF28H
ICU3 (fetch)
54
36
ICR38
324H
000FFF24H
OCU0 (match)
55
37
ICR39
320H
000FFF20H
OCU1 (match)
56
38
ICR40
31CH
000FFF1CH
OCU2 (match)
57
39
ICR41
318H
000FFF18H
OCU3 (match)
58
3A
ICR42
314H
000FFF14H
OCU4/5 (match)
59
3B
ICR43
310H
000FFF10H
OCU6/7 (match)
60
3C
ICR44
30CH
000FFF0CH
System-reserved
61
3D
ICR45
308H
000FFF08H
16-bit free-run timer
62
3E
ICR46
304H
000FFF04H
Delayed-interrupt source bit
63
3F
ICR47
300H
000FFF00H
System-reserved
(used by REALOS*)
64
40
-
2FCH
000FFEFCH
System-reserved
(used by REALOS*)
65
41
-
2F8H
000FFEF8H
System-reserved
66
42
-
2F4H
000FFEF4H
Interrupt source
Decimal
notation
Hexadecimal
notation
Reload timer 3
40
System-reserved
419
APPENDIX B Interrupt Vectors
Table B-1 Interrupt Vectors (4 / 4)
Interrupt number
Interrupt
level
Offset
TBR default
address
43
-
2F0H
000FFEF0H
68
44
-
2ECH
000FFEECH
System-reserved
69
45
-
2E8H
000FFEE8H
System-reserved
70
46
-
2E4H
000FFEE4H
System-reserved
71
47
-
2E0H
000FFEE0H
System-reserved
72
48
-
2DCH
000FFEDCH
System-reserved
73
49
-
2D8H
000FFED8H
System-reserved
74
4A
-
2D4H
000FFED4H
System-reserved
75
4B
-
2D0H
000FFED0H
System-reserved
76
4C
-
2CCH
000FFECCH
System-reserved
77
4D
-
2C8H
000FFEC8H
System-reserved
78
4E
-
2C4H
000FFEC4H
System-reserved
79
4F
-
2C0H
000FFEC0H
Used by INT instruction
80
|
255
50
|
FF
-
2BCH
|
000H
00FFEBCH
|
00FFC00H
Interrupt source
Decimal
notation
Hexadecimal
notation
System-reserved
67
System-reserved
* : REALOS/FR uses 0x40 and 0x41 interrupts for system codes.
420
APPENDIX C Pin Status in Each CPU State
APPENDIX C Pin Status in Each CPU State
Table C-1 explains the terms related to pin status, and Table C-2 to Table C-4 list the
pin status in each CPU state.
■ Terms Related to Pin Status
Table C-1 lists the meanings of the terms related to pin status.
Table C-1 Terms Related to Pin Status
Term
Meaning
Input enabled
This means that the input function can be used.
Keep the input at 0
An external input is shut off at the input gate that is nearest to the pin and 0 is
internally transferred.
Output Hi-Z
This means that the pin drive transistor enters the drive-disabled state and that the pin
is set to high impedance.
Output retained
This means that the output immediately before this mode continues to be outputted.
In other words, if a built-in peripheral circuit with an output is in operation, output is
performed in accordance with that built-in peripheral circuit and retained for port
output.
Retaining the last
status
This means that the output status immediately before this mode was entered
continues. If input was performed immediately before this mode was entered, this term
indicates that input will continue to be enabled.
421
APPENDIX C Pin Status in Each CPU State
■ Pin Status in Each CPU State
Table C-2 Pin Status in 16-bit Mode of the External Bus (1 / 2)
Pin
name
In stop mode
Function
P20 to
D16 to D23
P27
P30 to
D24 to D31
P37
P40 to
A00 to A07
P47
P50 to
A08 to A15
P57
Bus release
In sleep mode
Output retained
or Hi-Z
At reset
(STCR:HIZX=0)
(STCR:HIZX=1)
(BGRNT="L")
Output retained
or Hi-Z
Output Hi-Z or
Output Hi-Z
keep the input at
0
Output Hi-Z or
enable all-pin
input
FFH output
Output retained Output retained
(Address output) (Address output)
P60 to
A16 to A23
P67
P: Last status
retained
F: Address
output
P: Last status
retained
F: Address
output
P80
RDY
P: Last status
retained
F: RDY input
Last status
retained or keep
the input at 0
BGRNT
P: Last status
retained
F: H output
L output
P81
BRQ
P: Last status
retained
F: BRQ input
BRQ input
P82
P83
RD
Output Hi-Z
H output
P84
WR0
Last status
retained
CLK output
CLK output
Input enabled
Last status
retained
Output Hi-Z or
enable all-pin
input
P85
P86
WRI
P: Last status
retained
F: H output
CLK
P: Last status
retained
F: CLK output
Output Hi-Z or
enable all-pin
input
PC0 to INT0 to INT3
PC3
Last status
retained
PC4
P: Last status
retained
F: CS output
Output Hi-Z or
Input enabled
Last status
CS output
retained/Hi-Z for
CS output
Last status
retained
Input enabled
Last status
retained
INT4/CS0
PC5 to INT5 to INT7/
PC7
CS1 to CS3
PD0
AIN0/INT8
PD1
BIN0/INT9
PD2
AIN1/INT10
PD3
BIN1/INT11
PD4
ZIN0/INT12
PD5
ZIN1/INT13
PD6
DEOP2/INT14
PD7
ATG/INT15
422
Input enabled
P: Last status
retained
F: RDY input
Remarks
Output Hi-Z or
enable all-pin
input
APPENDIX C Pin Status in Each CPU State
Table C-2 Pin Status in 16-bit Mode of the External Bus (2 / 2)
Pin
name
In stop mode
Function
Last status
retained
PF0 to IN0 to IN3
PF3
PF4
At reset
(STCR:HIZX=0)
PE0 to OC0 to OC7
PE7
Bus release
In sleep mode
(STCR:HIZX=1)
(BGRNT="L")
Last status
Output Hi-Z or
Last status
retained or keep keep the input at retained
the input at 0
0
Output Hi-Z or
enable all-pin
input
Remarks
-
Port
PG0 to PPG0 to
PG5
PPG5
PJ0
Port
PJ1
Port
PI0
SIN2
PI1
SOT2
PI2
SCK/TO2
PI3
SIN3
PI4
SOT3
PI5
SCK3/TO3
PH0
SIN0
PH1
SOT0
PH2
SCK0/TO0
PH3
SIN1
PH4
SOT1
PH5
SCK1/TO1
PK0 to AN0 to AN7
PK7
PL0
DREQ0
PL1
DACK0
PL2
DEOP0
PL3
DREQ1
PL4
DACK1
PL5
DEOP1
PL6
DREQ2
PL7
DACK2
P: At selection of general-purpose port
F: At selection of specified function
423
APPENDIX C Pin Status in Each CPU State
Table C-3 Pin Status in External Bus 8-bit Mode (1 / 2)
Pin
name
In stop mode
Function
At reset
(STCR:HIZX=0)
(STCR:HIZX=1)
Output Hi-Z or
Last status
keep the input at retained
0
Output Hi-Z
P20 to
Port
P27
Last status
retained
Last status
retained
P30 to
D24 to D31
P37
Output retained
or Hi-Z
Output retained
or Hi-Z
P40 to
A00 to A07
P47
P50 to
A08 to A15
P57
Bus release
In sleep mode
(BGRNT="L")
Output Hi-Z or
enable all-pin
input
FFH output
Output retained Output retained
(Address output) (Address output)
P60 to
A16 to A23
P67
P: Last status
retained
F: Address
output
P: Last status
retained
F: Address
output
P80
RDY
P: Last status
retained
F: RDY input
Last status
retained or keep
the input at 0
BGRNT
P: Last status
retained
F: H output
L output
P81
BRQ
P: Last status
retained
F: BRQ input
BRQ input
P82
P83
RD
P84
WR0
P85
Port
P86
CLK
P: Last status
retained
F: RDY input
Output Hi-Z or
enable all-pin
input
Output Hi-Z
H output
Last status
retained
Output Hi-Z or
enable all-pin
input
CLK output
CLK output
Input enabled
Last status
retained
Output Hi-Z or
enable all-pin
input
P: Last status
retained
Output Hi-Z
CS output
PC5 to INT5/CS1 to
PC7
CS3
F: CS output
Input enabled
Last status
retained/
Hi-Z for CS
output
PD0
AIN0/INT8
Input enabled
PD1
BIN0/INT9
Last status
retained
Last status
retained
Output Hi-Z or
enable all-pin
input
PD2
AIN1/INT10
PD3
BIN1/INT11
PD4
ZIN0/INT12
PD5
ZIN1/INT13
PD6
DEOP2/INT14
PD7
ATG/INT15
PC0 to
INT0 to INT3
PC3
PC4
424
INT4/CS0
Last status
retained
P: Last status
retained
F: CLK output
Last status
retained
Input enabled
Remarks
-
APPENDIX C Pin Status in Each CPU State
Table C-3 Pin Status in External Bus 8-bit Mode (2 / 2)
Pin
name
In stop mode
Function
Last status
retained
PF0 to IN0 to IN3
PF3
PF4
At reset
(STCR:HIZX=0)
PE0 to OC0 to OC7
PE7
Bus release
In sleep mode
(STCR:HIZX=1)
(BGRNT="L")
Last status
Output Hi-Z or
Last status
retained or keep keep the input at retained
the input at 0
0
Output Hi-Z or
enable all-pin
input
Remarks
-
Port
PG0 to PPG0 to
PG5
PPG5
PJ0
Port
PJ1
Port
PI0
SIN2
PI1
SOT2
PI2
SCK2/TO2
PI3
SIN3
PI4
SOT3
PI5
SCK3/TO3
PH0
SIN0
PH1
SOT0
PH2
SCK0/TO0
PH3
SIN1
PH4
SOT1
PH5
SCK1/TO1
PK0 to AN0 to AN7
PK7
PL0
DREQ0
PL1
DACK0
PL2
DEOP0
PL3
DREQ1
PL4
DACK1
PL5
DEOP1
PL6
DREQ2
PL7
DACK2
P: At selection of general-purpose port
F: At selection of specified function
425
APPENDIX C Pin Status in Each CPU State
Table C-4 Pin Status in Serial-start Mode (1 / 2)
Pin
name
In stop mode
Function
In sleep mode
(STCR:HIZX=0)
P20 to Port
P27
P30 to
P37
Last status
retained
Last status
Output Hi-Z or
retained or keep keep the input at
the input at 0
0
P40 to
P47
P50 to
P57
P60 to
P67
P80
P81
P82
P83
P84
P85
P86
CLK
PC0 to INT0 to INT7
PC7
PD0
IAIN0/INT8
PD1
BIN0/INT9
PD2
AIN1/INT10
PD3
BIN1/INT11
PD4
ZIN0/INT12
PD5
ZIN1/INT13
PD6
DEOP2/INT14
PD7
ATG/INT15
PE0 to OC0 to OC7
PE7
PF0 to IN0 to IN3
PF3
PF4
Port
PG0 to PPG0 to PPG5
PG5
PJ0
Port
PJ1
Port
PI0
SIN2
426
Input enabled
-
At reset
-
Output Hi-Z or
enable all-pin
input
(STCR:HIZX=1)
Input enabled
Last status
Output Hi-Z or
retained or keep keep the input at
the input at 0
0
Remarks
-
APPENDIX C Pin Status in Each CPU State
Table C-4 Pin Status in Serial-start Mode (2 / 2)
Pin
name
In stop mode
Function
In sleep mode
(STCR:HIZX=0)
PI1
SOT2
PI2
SCK2/TO2
PI3
SIN3
PI4
SOT3
PI5
SCK3/TO0
PH0
SIN0
PH1
SOT0
PH2
SCK0/TO0
PH3
SIN1
PH4
SOT1
PH5
SCK1/TO1
Last status
retained
-
At reset
-
Output Hi-Z or
enable all-pin
input
(STCR:HIZX=1)
Last status
Output Hi-Z or
retained or keep keep the input at
the input at 0
0
Remarks
-
PK0 to
AN0 to AN7
PK7
PL0
DREQ0
PL1
DACK0
PL2
DEOP0
PL3
DREQ1
PL4
DACK1
PL5
DEOP1
PL6
DREQ2
PL7
DACK2
P: At selection of general-purpose port
F: At selection of specified function
427
APPENDIX D Notes on Using the Little-Endian Area
APPENDIX D Notes on Using the Little-Endian Area
This appendix provides notes on using the little-endian area for each of the following
items:
D.1 C Compiler (fcc911)
D.2 Assembler (fasm911)
D.3 Linker (flnk911)
D.4 Debuggers (sim911, eml911, and mon911)
428
APPENDIX D Notes on Using the Little-Endian Area
D.1
C Compiler (fcc911)
When programming in C, note that the operation result is unpredictable if the following
operations are performed for the little-endian area:
• Allocation of variables having initial values
• Structure insertion
• Manipulation of a non-character type array by using a character-string handling
function
• Specification of the -K lib option during use of a character-string handling function
• Using the double type and long-double type
• Allocating stacks in the little-endian area
■ Allocation of Variables Having Initial Values
A variable having an initial value cannot be allocated in the little-endian area.
The compiler has no function for generating initial values in the little-endian area. The compiler
can allocate variables in the little-endian area; however, it cannot set initial values in this area.
Perform the processing for setting the initial value at the beginning of the program.
[Example] Setting of an initial value for the variable little_data in the little-endian area
extern int little_data;
void little_init(void) {
little_data = initial-value;
}
void main(void) {
little_init();
...
}
■ Structure Insertion
For insertion between structures, the compiler selects the optimum transfer method to perform
transfer byte-by-byte, halfword-by-halfword, or word-by-word. If structure insertion is performed
between structure variables allocated in an ordinary area and those allocated in the little-endian
area, the obtained results will not be correct.
[Example] Structure insertion in the structure variable little_st of the little-endian area
struct tag { char c; int i;} normal_st;
extern struct tag little_st;
#define STRMOVE(DEST,SRC) DEST.c=SRC.c;DEST.i=SRC.i;
void main(void) {
STRMOVE(little_st,normal_st);
}
The location of the structure member differs for each compiler. So, the member location may
differ from that of a structure generated by another compiler. If this occurs, the method
previously explained will not produce correct results.
If structure member locations do not match, do not allocate structure variables in the littleendian area.
429
APPENDIX D Notes on Using the Little-Endian Area
■ Manipulation of a Non-character Type Array by Using a Character-string Handling Function
The character-string handling functions provided in the standard library perform processing in
units of bytes. They will therefore not produce correct results if processing is performed by
using a character-string handling function for an area with a type other than char, unsigned
char, and signed char allocated in the little-endian area.
Do not attempt to perform such processing.
[Erroneous example] Transfer of word data with memcpy
int big = 0x01020304;
/*
extern int little;
/*
memcpy(&little,&big,4); /*
Big-endian area
Little-endian area
Transfer with memcpy
*/
*/
*/}
The execution result of the above example is shown below. It is wrong as result of a word-data
transfer.
(Big-endian area)
01
02
03
(Little-endian area)
04
memcpy
01
02
03
04
(Correct result)
04
03
02
01
■ Specification of the -K lib Option During Use of a Character-string Handling Function
When the -K lib option is specified, the compiler performs inline expansion for some characterstring handling functions. To optimize processing, the compiler may change the processing to
halfword-level or word-level processing.
This type of processing does therefore not lead to the correct results for a little-endian area.
When processing is performed for the little-endian area by using character-string-handling
functions, do not specify the -K lib option.
Do not specify the -04 option, which contains the -K lib option, or the -K speed option.
■ Using Double Type and Long-double Type
During access to data of double or long-double type, a word in either the higher bits or the lower
bits of the data is accessed. Access to double type and long-double type variables allocated in
the little-endian area does therefore not produce correct results.
Variables of the same type allocated in the little-endian area can be replaced by each other.
However, as a result of optimization, these insertions may be performed as constant insertions.
Do not allocate variables of double type and long-double type in the little-endian area.
[Erroneous example] Transfer of double-type data
double big = 1.0; /*
extern int little; /*
little = big;
/*
Big-endian area
Little-endian area
Transfer of double-type data
*/
*/
*/
The execution result of the above example is shown below. It is not correct as result of a
double-type data transfer.
430
APPENDIX D Notes on Using the Little-Endian Area
(Big-endian area)
3f
f0
00
00
00
00
(Little-endian area)
00
00
(Correct result)
00
00
f0
3f
00
00
00
00
00
00
00
00
00
00
f0
3f
■ Allocation of Stacks in the Little-endian area
Integrity of operation results cannot be assured if all or some stacks are allocated in the littleendian area.
431
APPENDIX D Notes on Using the Little-Endian Area
D.2
Assembler (fasm911)
When programming in the assembler language for the FR Family, note the following
for the little-endian area with respect to the items below:
• Sections
• Data access
■ Sections
The little-endian area is used mainly for data exchange with CPUs employing the little-endian
system. Define this area as a data section without initial values.
If a code, stack, or data section with initial values is specified in the little-endian area, the
integrity of access operations of the MB91151A cannot be assured.
[Example]
/* Correct section definition for the little-endian area */
.SECTION Little_Area, DATA, ALIGN=4
Little_Word:
.RES.W 1
Little_Half:’
.RES.H 1
Little_Byte:
.RES.B 1
■ Data access
To execute a data access to the little-endian area, the data value can be coded without
considering that the value is allocated in the endian area. However, be sure to use a data
access matching the data length in the little-endian area.
[Example]
LDI
#0x01020304, r0
LDI
#Little_Word, r1
LDI
#0x0102, r2
LDI
#Little_Half, r3
LDI
#0x01, r4
LDI
#Little_Byte, r5
*/ 32-bit data is accessed with the ST (or LD) instruction. */
ST
r0, @r1
*/ 16-bit data is accessed with the STH (or LDH) instruction. */
STH
r2, @r3
*/ 8-bit data is accessed with the STB (or LDB) instruction.*/
STB
r4, @r5
In the MB91151A, if a data access operation that does not match the data length in the littleendian area, the integrity of the results cannot be assured. For example, if two consecutive 16bit data items are accessed at the same time with a 32-bit access instruction, the integrity of the
data values cannot be assured.
432
APPENDIX D Notes on Using the Little-Endian Area
D.3
Linker (flnk911)
This section provides notes related to the following topics for the section placement at
linkage when a program that uses the little-endian area is to be created:
• Restrictions on section types
• Failure to detect errors
■ Restriction on Section Types
Only data sections without initial values can be allocated in the little-endian area.
Assume that a data section, stack section, or code section having initial values is placed in the
little-endian area. Because the linker internally performs such arithmetic operations as resolving
addresses in big-endian mode, the correctness of program operation cannot be assured.
■ Failure to Detect Errors
The linker is not aware of the little-endian area. Because of this, no error message is posted if
an allocation in violation of the above restriction is made. Use the linker after thoroughly
confirming the contents of the section allocated in the little-endian area.
433
APPENDIX D Notes on Using the Little-Endian Area
D.4
Debuggers (sim911, eml911, and mon911)
This section provides notes on using the simulator debugger, emulator debugger, and
monitor debugger.
■ Simulator Debugger
There is no memory space specification command that explicitly indicates the little-endian area.
Therefore, memory operation commands and memory operation instructions are handled in bigendian mode.
■ Emulator Debugger and Monitor Debugger
Note that, if the following commands are used to access the little-endian area, data values are
handled as incorrect:
❍ Set memory, show memory, enter, examine, and set watch commands
If floating-point (single or double) data is handled, the specified value cannot be set or
displayed.
❍ Search memory command
Halfword or word data is not searched with the specified value.
❍ Line or reverse assembling (this includes reverse assembling of the contents of the
source-code window)
Normal instruction code cannot be set or displayed. (Do not set any instruction code in the littleendian area.)
❍ Call and show call commands
If the stack area is allocated in the little-endian area, operation is not performed normally. (Do
not allocate the stack area in the little-endian area.)
434
APPENDIX E Instruction Lists
APPENDIX E
Instruction Lists
This appendix lists the FR Family instructions. For facilitating understanding the
instruction list, notes on the following items are provided:
• How to read the instruction lists
• Addressing mode symbols
• Instruction format
■ How to Read the Instruction Lists
Mnemonic
Type
OP
CYCLE
NZVC
Operation
Remarks
ADD Rj, Rj
*ADD #s5, Rj
,
,
A
C
,
,
AG
A4
,
,
1
1
,
,
CCCC
CCCC
,
,
Ri + Rj --> Rj
Ri + s5 --> Ri
,
,
-
3)
4)
5)
6)
7)
1)
2)
1) Indicates an instruction name.
•
An asterisk (*) indicates an extended instruction which is not listed in the CPU specifications
and which was obtained by extending or adding an instruction with the assembler.
2) Indicates the addressing mode specifiable in an operand, with its symbol.
•
For the meaning of the symbols, see the sub-section on "■Addressing Mode Symbols".
3) Indicates the instruction format.
4) Indicates an instruction code in hexadecimal notation.
5) Indicates the number of machine cycles for the instruction.
•
a: Memory access cycle. It may be extended by the Ready function.
•
b: Memory access cycle. It may be extended by the Ready function. However, when the
succeeding instruction references the register subject to LD operation, an interlock occurs
and the number of execution cycles is incremented by one.
•
c: When the succeeding instruction performs reading or writing for R15, SSP, or USP, or it
has instruction format A, an interlock occurs, and the number of execution cycles is
incremented by one and becomes 2.
•
d: When the succeeding instruction references MDH or MDL, an interlock occurs and the
number of execution cycles increments and becomes 2.
•
The minimum number of cycles is 1 for a, b, c, and d.
6) Indicates flag changes.
Flag change
C: Change
-: No change
0: Clear
1: Set
Flag meaning
N:
Z:
V:
C:
Negative flag
Zero flag
Overflow flag
Carry flag
435
APPENDIX E Instruction Lists
7) Indicates the operation of the instruction.
■ Addressing Mode Symbols
Table E-1 Explanations of the addressing Mode Symbols (1 / 2)
Symbol
436
Meaning
Ri
Register direct (R0 to R15, AC, FP, and SP)
Rj
Register direct (R0 to R15, AC, FP, and SP)
R13
Register direct (R13 and AC)
Ps
Register direct (program status register)
Rs
Register direct (TBR, RP, SSP, USP, MDH, and MDL)
CRi
Register direct (CR0 to CR15)
CRj
Register direct (CR0 to CR15)
#i8
Unsigned 8-bit immediate value (-128 to 255)
Note: -128 to -1 are handled as 128 to 255.
#i20
Unsigned 20-bit immediate value (-0x80000 to 0xFFFFF)
Note: -0x7FFFF to -1 are handled as 0x7FFFF to 0xFFFFF.
#i32
Unsigned 32-bit immediate value (-0x80000000 to 0xFFFFFFFF)
Note: -0x80000000 to -1 are handled as 0x80000000 to 0xFFFFFFFF.
#s5
Signed 5-bit immediate value (-16 to 15)
#s10
Signed 10-bit immediate value (-512 to 508, only multiples of 4)
#u4
Unsigned 4-bit immediate value (0 to 15)
#u5
Unsigned 5-bit immediate value (0 to 31)
#u8
Unsigned 8-bit immediate value (0 to 255)
#u10
Unsigned 10-bit immediate value (0 to 1020, only multiples of 4)
@dir8
Unsigned 8-bit direct address (0 to 0xFF)
@dir9
Unsigned 9-bit direct address (0 to 0x1FE, only multiples of 2)
@dir10
Unsigned 10-bit direct address (0 to 0x3FC, only multiples of 4)
label9
Signed 9-bit branch address (-0x100 to 0xFC, only multiples of 2)
label12
Signed 12-bit branch address (-0x800 to 0x7FC, only multiples of 2)
label20
Signed 20-bit branch address (-0x80000 to 0x7FFFF)
label32
Signed 20-bit branch address (-0x80000 to 0x7FFFF)
@Ri
Signed 32-bit branch address (-0x80000000 to 0x7FFFFFFF)
@Rj
Register indirect (R0 to R15, AC, FP, and SP)
@(R13,Rj)
Register relative indirect (Rj: R0 to R15, AC, FP, and SP)
@(R14,disp10)
Register relative indirect (disp10: -0x200 to 0x1FC, only multiples of 4)
APPENDIX E Instruction Lists
Table E-1 Explanations of the addressing Mode Symbols (2 / 2)
Symbol
Meaning
@(R14,disp9)
Register relative indirect (disp9: -0x100 to 0xFE, only multiples of 2)
@(R14,disp8)
Register relative indirect (disp8: -0x80 to 0x7F)
@(R15,udisp6)
Register relative indirect (udisp6: 0 to 60, only multiples of 4)
@Ri+
Register indirect with post-increment (R0 to R15, AC, FP, and SP)
@R13+
Register indirect with post-increment (R13 and AC)
@SP+
Stack pop
@-SP
Stack push
(reglist)
Register list
437
APPENDIX E Instruction Lists
■ Instruction Format
Table E-2 Instruction Format
Type
Instruction format
A
MSB
LSB
16 bit
OP
Rj
Ri
8
4
4
B
OP
i8/o8
Ri
8
4
4
C
OP
u4/m4
Ri
8
4
4
C’
Only for ADD, ADDN, CMP, LSL,
LSR, and ASR instructions
OP
s5/u5
Ri
7
5
4
OP
u8/re18/dir/
reglist
8
8
D
E
OP
SUB-OP
Ri
8
4
4
F
438
OP
re111
5
11
APPENDIX E Instruction Lists
■ FR Family Instruction Lists
This section provides lists of the FR family instructions in the following order:
•
Table E-3 Addition and Subtraction Instructions
•
Table E-4 Comparison Operation Instruction
•
Table E-5 Logical Operation Instructions
•
Table E-6 Bit Manipulation Instructions
•
Table E-7 Multiplication and Division Instructions
•
Table E-8 Shift Instructions
•
Table E-9 Immediate Value Set, 16-bit Immediate Value, and 32-bit Immediate Value
Transfer Instructions
•
Table E-10 Memory Load Instructions
•
Table E-11 Memory Store Instructions
•
Table E-12 Register-to-register Transfer Instructions
•
Table E-13 Ordinary Branch (No Delay) Instructions
•
Table E-14 Delayed Branch Instructions
•
Table E-15 Other Instructions
•
Table E-16 20-bit Ordinary Branch Macroinstructions
•
Table E-17 20-bit Delayed Branch Macroinstructions
•
Table E-18 32-bit Ordinary Branch Macroinstructions
•
Table E-19 32-bit Delayed Branch Macroinstructions
•
Table E-20 Direct addressing Instructions
•
Table E-21 Resource Instructions
•
Table E-22 Coprocessor Control Instructions
439
APPENDIX E Instruction Lists
■ Addition and Subtraction Instructions
Table E-3 Addition and Subtraction Instructions
Mnemonic
Type
OP
CYCLE
NZVC
Operation
Remarks
ADD Rj, Ri
*ADD #s5, Ri
A
C’
A6
A4
1
1
CCCC
CCCC
Ri+Rj --> Ri
Ri+s5 --> Ri
ADD #u4, Ri
ADD2 #u4, Ri
C
C
A4
A5
1
1
CCCC
CCCC
Ri+extu(i4) --> Ri
Ri+extu(i4) --> Ri
The assembler assumes the
higher one bit to be a symbol.
Zero extension
Minus extension
ADDC Rj, Ri
A
A7
1
CCCC
Ri+Rj + c --> Ri
Addition with carries
ADDN Rj, Ri
*ADDN #s5, Ri
A
C’
A2
A0
1
1
-------
Ri+Rj --> Ri
Ri+s5 --> Ri
ADDN #u4, Ri
ADDN2 #u4, Ri
C
C
A0
A1
1
1
-------
Ri+extu(i4) --> Ri
Ri+extu(i4) --> Ri
SUB Rj, Ri
A
AC
1
CCCC
Ri - Rj --> Ri
SUBC Rj, Ri
A
AD
1
CCCC
Ri - Rj - c --> Ri
SUBN Rj, Ri
A
AE
1
----
The assembler assumes the
higher one bit to be a symbol.
Zero extension
Minus extension
Subtraction with carries
Ri - Rj --> Ri
-
■ Comparison Operation Instruction
Table E-4 Comparison Operation Instruction
Mnemonic
Type
OP
CYCLE
NZVC
Operation
CMP Rj, Ri
*CMP #s5, Ri
A
C’
AA
A8
1
1
CCCC
CCCC
Ri - Rj
Ri - s5
CMP #u4, Ri
CMP2 #u4, Ri
C
C
A8
A9
1
1
CCCC
CCCC
Ri - extu(i4)
Ri - extu(i4)
Remarks
The assembler assumes the
higher one bit to be a symbol.
Zero extension
Minus extension
■ Logical Operation Instructions
Table E-5 Logical Operation Instructions
Mnemonic
Type
OP
CYCLE
NZVC
AND Rj, Ri
AND Rj, @Ri
ANDH Rj, @Ri
ANDB Rj, @Ri
A
A
A
A
82
84
85
86
1
1+2a
1+2a
1+2a
CC-CC-CC-CC--
Ri &= Rj
(Ri) &= Rj
(Ri) &= Rj
(Ri) &= Rj
Word
Word
Halfword
Byte
OR
OR
ORH
ORB
A
A
A
A
92
94
95
96
1
1+2a
1+2a
1+2a
CC-CC-CC-CC--
Ri |= Rj
(Ri) |= Rj
(Ri) |= Rj
(Ri) |= Rj
Word
Word
Halfword
Byte
A
A
A
A
9A
9C
9D
9E
1
1+2a
1+2a
1+2a
CC-CC-CC-CC--
Ri ^= Rj
(Ri) ^= Rj
(Ri) ^= Rj
(Ri) ^= Rj
Word
Word
Halfword
Byte
Rj, Ri
Rj, @Ri
Rj, @Ri
Rj, @Ri
EOR
EOR
EORH
EORB
440
Rj, Ri
Rj, @Ri
Rj, @Ri
Rj, @Ri
Operation
Remarks
APPENDIX E Instruction Lists
■ Bit Manipulation Instructions
Table E-6 Bit Manipulation Instructions
Mnemonic
Type
OP
CYCLE
NZVC
BANDL #u4, @Ri
C
80
1+2a
----
(Ri) &=(0xF0+u4)
BANDH #u4, @Ri
C
81
1+2a
----
(Ri) &=((u4<<4)+0x0F)
----
(Ri) &=u8
*BAND #u8, @Ri*1
Operation
BORL #u4, @Ri
C
90
1+2a
----
(Ri) |= u4
BORH #u4, @Ri
C
91
1+2a
----
(Ri) |= (u4<<4)
----
(Ri) |= u8
*BOR #u8, @Ri*2
BEORL #u4, @Ri
C
98
1+2a
----
(Ri) ^= u4
BEORH #u4, @Ri
C
99
1+2a
----
(Ri) ^= (u4<<4)
----
(Ri) ^= u8
*BEOR #u8, @Ri*3
BTSTL #u4, @Ri
C
88
2+a
0C--
(Ri) & u4
BTSTH #u4, @Ri
C
89
2+a
CC--
(Ri) & (u4<<4)
*1:
*2:
*3:
Remarks
Manipulation of the
lower four bits
Manipulation of the
higher four bits
Manipulation of the
lower four bits
Manipulation of the
higher four bits
Manipulation of the
lower four bits
Manipulation of the
higher four bits
Manipulation of the
lower four bits
Manipulation of the
higher four bits
If the bit is set for u8&0x0F, the assembler generates BANDL. If the bit is set for u8&0xF0, the
assembler generates BANDH. The assembler may generate both BANDL and BANDH.
If the bit is set for u8&0x0F, the assembler generates BORL. If the bit is set for u8&0xF0, the
assembler generates BORH. The assembler may generate both BORL and BORH.
If the bit is set for u8&0x0F, the assembler generates BEORL. If the bit is set for u8&0xF0, the
assembler generates BEORH. The assembler may generate both BEORL and BEORH.
441
APPENDIX E Instruction Lists
■ Multiplication and Division Instructions
Table E-7 Multiplication and Division Instructions
Mnemonic
Type
OP
CYCLE
NZVC
MUL Rj,Ri
MULU Rj,Ri
MULH Rj,Ri
MULUH Rj,Ri
A
A
A
A
AF
AB
BF
BB
5
5
3
3
CCCCCCCC-CC--
DIV0S Ri
DIV0U Ri
DIV1 Ri
DIV2 Ri*3
DIV3
DIV4S
*DIV Ri*1
E
E
E
E
E
E
97-4
97-5
97-6
97-7
9F-6
9F-7
1
1
d
1
1
1
36
-------C-C
-C-C
-------C-C
33
-C-C
*DIVU Ri*2
*1:
*2:
*3:
Operation
Ri * Rj --> MDH,MDL
Ri * Rj --> MDH,MDL
Ri * Rj --> MDL
Ri * Rj --> MDL
Remarks
32bit*32bit=64bit
Unsigned
16bit*16bit=32bit
Unsigned
Step operation
32bit/32bit=32bit
MDL / Ri --> MDL ,
MDL % Ri--> MDH
MDL / Ri --> MDL ,
MDL % Ri--> MDH
Generates DIVOS, DIV1 x 32, DIV2, DIV3, and DIV4S. The instruction code length is 72 bytes.
Generates DIVOU and DIV1 x 32. The instruction code length is 66 bytes.
Be sure to place the DIV3 instruction after the DIV2 instruction.
■ Shift Instructions
Table E-8 Shift Instructions
Mnemonic
Type
OP
CYCLE
NZVC
Operation
LSL Rj, Ri
*LSL # u5, Ri (u5:0 to 31)
LSL #u4, Ri
LSL2 #u4, Ri
A
C’
C
C
B6
B4
B4
B5
1
1
1
1
CC-C
CC-C
CC-C
CC-C
Ri << Rj --> Ri
Ri << u5 --> Ri
Ri << u4 --> Ri
Ri <<(u4+16) --> Ri
Logical shift
LSR Rj, Ri
*LSR # u5, Ri (u5:0 to 31)
LSR #u4, Ri
LSR2 #u4, Ri
A
C’
C
C
B2
B0
B0
B1
1
1
1
1
CC-C
CC-C
CC-C
CC-C
Ri << Rj --> Ri
Ri << u5 --> Ri
Ri << u4 --> Ri
Ri <<(u4+16) --> Ri
Logical shift
ASR Rj, Ri
*ASR # u5, Ri (u5:0 to 31)
ASR #u4, Ri
ASR2 #u4, Ri
A
C’
C
C
BA
B8
B8
B9
1
1
1
1
CC-C
CC-C
CC-C
CC-C
Ri << Rj --> Ri
Ri << u5 --> Ri
Ri << u4 --> Ri
Ri <<(u4+16) --> Ri
Arithmetic shift
442
Remarks
APPENDIX E Instruction Lists
■ Immediate Value Set, 16-bit Immediate Value, and 32-bit Immediate Value Transfer Instructions
Table E-9 Immediate Value Set, 16-bit Immediate Value, and 32-bit Immediate Value Transfer Instructions
Mnemonic
Type
OP
CYCLE
NZVC
LDI:32 #i32, Ri
LDI:20 #i20, Ri
E
C
9F-8
9B
3
2
-------
i32 --> Ri
i20 --> Ri
LDI:8 #i8, Ri
B
C0
1
----
i8 --> Ri
*LDI # {i8|i20|i32}, Ri*1
*1:
Operation
Remarks
The higher 12 bits are
zero-extended.
The higher 24 bits are
zero-extended.
{i8|i20|i32} --> Ri
If an immediate value is an absolute value, the assembler automatically selects i8, i20, or i32.
If the immediate value contains a relative value or external reference symbol, i32 is selected.
■ Memory Load Instructions
Table E-10 Memory Load Instructions
Mnemonic
Type
OP
CYCLE
NZVC
Operation
@Rj, Ri
@(R13,Rj), Ri
@(R14,disp10), Ri
@(R15,udisp6), Ri
@R15+, Ri
@R15+, Rs
A
A
B
C
E
E
04
00
20
03
07-0
07-8
b
b
b
b
b
b
-------------------
(Rj) --> Ri
(R13+Rj) --> Ri
(R14+disp10) --> Ri
(R15+udisp6) --> Ri
(R15) --> Ri,R15+=4
(R15) --> Rs, R15+=4
LD @R15+, PS
E
07-9
1+a+b
CCCC
(R15) --> PS, R15+=4
LDUH @Rj, Ri
LDUH @(R13,Rj), Ri
LDUH @(R14,disp9), Ri
A
A
B
05
01
40
b
b
b
----------
(Rj) --> Ri
(R13+Rj) --> Ri
(R14+disp9) --> Ri
Zero extension
Zero extension
Zero extension
LDUB @Rj, Ri
LDUB @(R13,Rj), Ri
LDUB @(R14,disp8), Ri
A
A
B
06
02
60
b
b
b
----------
(Rj) --> Ri
(R13+Rj) --> Ri
(R14+disp8) --> Ri
Zero extension
Zero extension
Zero extension
LD
LD
LD
LD
LD
LD
*:
Note:
Remarks
Rs: Special
registers*
Special registers Rs: TBR, RP, USP, SSP, MDH, and MDL
The assembler performs calculations as shown below and sets values in the o8 and o4 fields of the
hardware specifications:
disp10/4 --> o8, disp9/2 --> o8, and disp8 --> o8. disp10, disp9, and disp8 are signed operands.
udisp6/4 --> o4. udisp6 is an unsigned operand.
443
APPENDIX E Instruction Lists
■ Memory Store Instructions
Table E-11 Memory Store Instructions
Mnemonic
Type
OP
CYCLE
NZVC
Operation
A
A
B
C
E
E
14
10
30
13
17-0
17-8
a
a
a
a
a
a
-------------------
Ri --> (Rj)
Ri --> (R13+Rj)
Ri --> (R14+disp10)
Ri --> (R15+udisp6)
R15-=4,Ri --> (R15)
R15-=4, Rs --> (R15)
ST PS, @ -R15
E
17-9
a
----
R15-=4, PS --> (R15)
STH Ri, @ Rj
STH Ri, @ (R13,Rj)
STH Ri, @ (R14,disp9)
A
A
B
15
11
50
a
a
a
----------
Ri --> (Rj)
Ri --> (R13+Rj)
Ri --> (R14+disp9)
Halfword
Halfword
Halfword
STB Ri, @ Rj
STB Ri, @ (R13,Rj)
STB Ri, @ (R14,disp8)
A
A
B
16
12
70
a
a
a
----------
Ri --> (Rj)
Ri --> (R13+Rj)
Ri --> (R14+disp8)
Byte
Byte
Byte
ST
ST
ST
ST
ST
ST
Ri, @ Rj
Ri, @ (R13,Rj)
Ri, @ (R14,disp10)
Ri, @ (R15,udisp6)
Ri, @ -R15
Rs, @ -R15
*:
Note:
Remarks
Word
Word
Word
Rs: Special
registers*
Special registers Rs: TBR, RP, USP, SSP, MDH, and MDL
The assembler performs calculations as shown below and sets values in the o8 and o4 fields within
the hardware specifications:
disp10/4 --> o8, disp9/2 --> o8, and disp8 --> o8. disp10 disp9, and disp8 are signed operands.
udisp6/4 --> o4. udisp6 is an unsigned operand.
■ Register-to-register Transfer Instructions
Table E-12 Register-to-register Transfer Instructions
Mnemonic
Type
OP
CYCLE
NZVC
MOV Rj, Ri
A
8B
1
----
Rj --> Ri
MOV
MOV
MOV
MOV
A
A
E
E
B7
B3
17-1
07-1
1
1
1
c
---------CCCC
Rs --> Ri
Ri --> Rs
PS --> Ri
Ri --> PS
*:
444
Rs, Ri
Ri, Rs
PS, Ri
Ri, PS
Operation
Special registers Rs: TBR, RP, USP, SSP, MDH, and MDL
Remarks
Transfer between generalpurpose registers
Rs: Special registers*
Rs: Special registers*
APPENDIX E Instruction Lists
■ Ordinary Branch (No Delay) Instructions
Table E-13 Ordinary Branch (No Delay) Instructions
Mnemonic
Type
OP
CYCLE
NZVC
JMP @Ri
E
97-0
2
----
Rj --> PC
-
CALL label12
F
D0
2
----
-
CALL @Ri
E
97-1
2
----
PC+2 --> RP ,
PC+2+(label12-PC-2) --> PC
PC+2 --> RP ,Ri --> PC
RET
E
97-2
2
----
RP --> PC
D
1F
3+3a
----
INTE
E
9F-3
3+3a
----
SSP-=4,PS --> (SSP),
SSP-=4,PC+2 --> (SSP),
0 --> I flag, 0 --> S flag
(TBR+0x3FC-u8 x 4) --> PC
SSP-=4,PS --> (SSP),
SSP-=4,PC+2 --> (SSP),
0 --> S flag
(TBR+0x3D8) --> PC
RET1
E
97-3
2+2a
CCCC
INT
#u8
BRA
BNO
BEQ
label9
label9
label9
D
D
D
E0
E1
E2
2
1
2/1
----------
BNE
BC
BNC
BN
BP
BV
BNV
BLT
BGE
BLE
BGT
BLS
BHI
label9
label9
label9
label9
label9
label9
label9
label9
label9
label9
label9
label9
label9
D
D
D
D
D
D
D
D
D
D
D
D
D
E3
E4
E5
E6
E7
E8
E9
EA
EB
EC
ED
EE
EF
2/1
2/1
2/1
2/1
2/1
2/1
2/1
2/1
2/1
2/1
2/1
2/1
2/1
----------------------------------------
Notes:
•
•
•
Operation
Remarks
Return
For the emulator
(R15) --> PC,R15-=4,
(R15) --> PS,R15-=4
-
PC+2+(label9-PC-2) --> PC
No branch
if(Z==1) then
PC+2+(label9-PC-2) --> PC
! s/Z==0
! s/C==1
! s/C==0
! s/N==1
! s/N==0
! s/V==1
! s/V==0
! s/V xor N==1
! s/V xor N==0
! s/(V xor N) or Z==1
! s/(V xor N) or Z==0
! s/C or Z==1
! s/C or Z==0
-
2/1 in the number of CYCLEs indicates 2 for a branch and "1" for no branch.
The assembler performs calculations as shown below and sets values in the rel11 and rel8
fields of the hardware specifications: (label12-PC-2)/2 --> rel11 and (label9-PC-2)/2 --> rel8.
label12 and label9 are signed operands.
To execute the RETI instruction, the S flag must be 0.
445
APPENDIX E Instruction Lists
■ Delayed Branch Instructions
Table E-14 Delayed Branch Instructions
Mnemonic
Type
OP
CYCLE
NZVC
JMP:D @Ri
E
9F-0
1
----
Ri --> PC
-
CALL:D label12
F
D8
1
----
-
CALL:D @Ri
E
9F-1
1
----
PC+4 --> RP ,
PC+2+(label12-PC-2) --> PC
PC+4 --> RP ,Ri --> PC
RET:D
E
9F-2
1
----
RP --> PC
PC+2+(label9-PC-2) --> PC
No branch
if(Z==1) then
PC+2+(label9-PC-2) --> PC
! s/Z==0
! s/C==1
! s/C==0
! s/N==1
! s/N==0
! s/V==1
! s/V==0
! s/V xor N==1
! s/V xor N==0
! s/(V xor N) or Z==1
! s/(V xor N) or Z==0
! s/C or Z==1
! s/C or Z==0
BRA:D
BNO:D
BEQ:D
label9
label9
label9
D
D
D
F0
F1
F2
1
1
1
----------
BNE:D
BC:D
BNC:D
BN:D
BP:D
BV:D
BNV:D
BLT:D
BGE:D
BLE:D
BGT:D
BLS:D
BHI:D
label9
label9
label9
label9
label9
label9
label9
label9
label9
label9
label9
label9
label9
D
D
D
D
D
D
D
D
D
D
D
D
D
F3
F4
F5
F6
F7
F8
F9
FA
FB
FC
FD
FE
FF
1
1
1
1
1
1
1
1
1
1
1
1
1
----------------------------------------
Notes:
•
•
•
446
Operation
Remarks
Return
-
The assembler performs calculations as shown below and sets values in the rel11 and rel8
fields of the hardware specifications: (label12-PC-2)/2 --> rel11 and (label9-PC-2)/2 --> rel8.
label12 and label9 are signed labels.
In a delayed branch, a branch will occur after the next instruction (delayed slot) is executed.
The instructions that can be placed in delayed slots are all one-cycle, a-cycle, b-cycle, c-cycle,
and d-cycle instructions. Multiple-cycle instructions cannot be placed in delayed slots.
APPENDIX E Instruction Lists
■ Other Instructions
Table E-15 Other Instructions
Mnemonic
Type
OP
CYCLE
NZVC
NOP
E
9F-A
1
----
ANDCCR #u8
ORCCR #u8
D
D
93
83
c
c
CCCC
CCCC
STILM #u8
D
87
1
----
i8 --> ILM
ILM immediate
value set
ADDSP #s10*1
D
A3
1
----
R15 += s10
ADD SP instruction
EXTSB
EXTUB
EXTSH
EXTUH
E
E
E
E
97-8
97-9
97-A
97-B
1
1
1
1
-------------
Sign extension 8 --> 32bit
Zero extension 8 --> 32bit
Sign extension 16 --> 32bit
Zero extension 16 --> 32bit
LDM0 (reglist)
D
8C
-
----
LDM1 (reglist)
D
8D
(R15) --> reglist,
R15 increment
(R15) --> reglist,
R15 increment
(R15) --> reglist,
R15 increment
Load multiple R0 to
R7
Load multiple R8 to
R15
Load multiple R0 to
R15
STM0 (reglist)
D
8E
STM1 (reglist)
D
8F
R15 decrement
reglist --> (R15)
R15 decrement
reglist --> (R15)
R15 decrement
reglist --> (R15)
Store multiple R0
to R7
Store multiple R8
to R15
Store multiple R0
to R15
ENTER #u10*4
D
0F
1+a
----
R14 --> (R15 - 4),
R15 - 4 --> R14,
R15 - u10 --> R15
Entry processing of
a function
LEAVE
E
9F-9
b
----
R14 + 4 --> R15,
(R15 - 4) --> R14
Exit processing of
a function
A
8A
2a
----
Ri --> TEMP
(Rj) --> Ri
TEMP --> (Rj)
For semaphore
control
Byte data
Ri
Ri
Ri
Ri
----
*LDM (reglist)*2
-
-------
*STM (reglist)*3
XCHB
*1:
*2:
*3:
*4:
Notes:
@Rj, Ri
Operation
Remarks
No change
-
CCR and u8 --> CCR
CCR or u8 --> CCR
-
-
The assembler changes s10 to s8 by calculating s10/4 and sets a value. s10 is a signed value.
If reglist specifies any of R0 to R7, the assembler generates LDM0. If reglist specifies any of R8
to R15, the assembler generates LDM1. The assembler may generate both LDM0 and LDM1.
If reglist specifies any of R0 to R7, the assembler generates STM0. If reglist specifies any of R8
to R15, the assembler generates STM1. The assembler may generate both STM1 and STM0.
The assembler changes u10 to u8 by calculating u10/4 and sets a value. u10 is an unsigned
value.
•
•
The number of execution cycles of LDM0 (reglist) and LDM1 (reglist) is a×(n-1)+b+1 cycles
when the specified number of registers is n.
The number of execution cycles of STM0 (reglist) and STM1 (reglist) is a×n+1 cycles when the
specified number of registers is n.
447
APPENDIX E Instruction Lists
■ 20-bit Ordinary Branch Macroinstructions
Table E-16 20-bit Ordinary Branch Macroinstructions
Mnemonic
Operation
Remarks
*CALL20 label20,Ri
Address of the next instruction --> RP
label20 --> PC
Ri: Temporary register (See Reference 1.)
*BRA20
*BEQ20
*BNE20
*BC20
*BNC20
*BN20
*BP20
*BV20
*BNV20
*BLT20
*BGE20
*BLE20
*BGT20
*BLS20
*BHI20
label20 --> PC
if(Z==1) then label20 -->PC
! s/Z==0
! s/C==1
! s/C==0
! s/N==1
! s/N==0
! s/V==1
! s/V==0
! s/V xor N==1
! s/V xor N==0
! s/(V xor N) or Z==1
! s/(V xor N) or Z==0
! s/C or Z==1
! s/C or Z==0
Ri: Temporary register (See Reference 2.)
Ri: Temporary register (See Reference 3.)
!
!
!
!
!
!
!
!
!
!
!
!
!
label20,Ri
label20,Ri
label20,Ri
label20,Ri
label20,Ri
label20,Ri
label20,Ri
label20,Ri
label20,Ri
label20,Ri
label20,Ri
label20,Ri
label20,Ri
label20,Ri
label20,Ri
[Reference 1] CALL20
1)
2)
When label20-PC-2 is -0x800 to +0x7fe, the instruction is generated as follows:
CALL label12
When label20-PC-2 exceeds the range in condition 1) or contains an external reference symbol, the
instruction is generated as follows:
LDI:20 #label20,Ri
CALL @Ri
[Reference 2] BRA20
1)
2)
When label20-PC-2 is -0x100 to +0xfe, the instruction is generated as follows:
BRA label9
When label20-PC-2 exceeds the range in condition 1) or contains an external reference symbol, the
instruction is generated as follows:
LDI:20 #label20,Ri
JMP @Ri
[Reference 3] Bcc20
1)
2)
448
When label20-PC-2 is -0x100 to +0xfe, the instruction is generated as follows:
Bcc label9
When label20-PC-2 exceeds the range in condition 1) or contains an external reference symbol, the
instruction is generated as follows:
Bxcc false
xcc is a condition against cc.
LDI:20 #label20,Ri
JMP @Ri
false:
APPENDIX E Instruction Lists
■ 20-bit Delayed Branch Macroinstructions
Table E-17 20-bit Delayed Branch Macroinstructions
Mnemonic
Operation
Remarks
*CALL20:D label20,Ri
Address of the next instruction + 2
--> RP
label20 --> PC
Ri: Temporary register (See Reference 1.)
*BRA20:D
*BEQ20:D
*BNE20:D
*BC20:D
*BNC20:D
*BN20:D
*BP20:D
*BV20:D
*BNV20:D
*BLT20:D
*BGE20:D
*BLE20:D
*BGT20:D
*BLS20:D
*BHI20:D
label20 --> PC
if(Z==1) then label20 -->PC
! s/Z==0
! s/C==1
! s/C==0
! s/N==1
! s/N==0
! s/V==1
! s/V==0
! s/V xor N==1
! s/V xor N==0
! s/(V xor N) or Z==1
! s/(V xor N) or Z==0
! s/C or Z==1
! s/C or Z==0
Ri: Temporary register (See Reference 2.)
Ri: Temporary register (See Reference 3.)
!
!
!
!
!
!
!
!
!
!
!
!
!
label20,Ri
label20,Ri
label20,Ri
label20,Ri
label20,Ri
label20,Ri
label20,Ri
label20,Ri
label20,Ri
label20,Ri
label20,Ri
label20,Ri
label20,Ri
label20,Ri
label20,Ri
[Reference 1] CALL20:D
1)
2)
When label20-PC-2 is -0x800 to +0x7fe, the instruction is generated as follows:
CALL:D label12
When label20-PC-2 exceeds the range in condition 1) or contains an external reference symbol, the
instruction is generated as follows:
LDI:20 #label20,Ri
CALL:D @Ri
[Reference 2] BRA20:D
1)
2)
When label20-PC-2 is -0x100 to +0xfe, the instruction is generated as follows:
BRA:D label9
When label20-PC-2 exceeds the range in condition 1) or contains an external reference symbol, the
instruction is generated as follows:
LDI:20 #label20,Ri
JMP:D @Ri
[Reference 3] Bcc20:D
1)
2)
When label20-PC-2 is -0x100 to +0xfe, the instruction is generated as follows:
Bcc:D label9
When label20-PC-2 exceeds the range in condition 1) or contains an external reference symbol, the
instruction is generated as follows:
Bxcc false
xcc is a condition against cc.
LDI:20 #label20,Ri
JMP:D @Ri
false:
449
APPENDIX E Instruction Lists
■ 32-bit Ordinary Branch Macroinstructions
Table E-18 32-bit Ordinary Branch Macroinstructions
Mnemonic
Operation
Remarks
*CALL32 label32,Ri
Address of the next instruction --> RP
label32 --> PC
Ri: Temporary register (See Reference 1.)
*BRA32
*BEQ32
*BNE32
*BC32
*BNC32
*BN32
*BP32
*BV32
*BNV32
*BLT32
*BGE32
*BLE32
*BGT32
*BLS32
*BHI32
label32 --> PC
if(Z==1) then label32 -->PC
! s/Z==0
! s/C==1
! s/C==0
! s/N==1
! s/N==0
! s/V==1
! s/V==0
! s/V xor N==1
! s/V xor N==0
! s/(V xor N) or Z==1
! s/(V xor N) or Z==0
! s/C or Z==1
! s/C or Z==0
Ri: Temporary register (See Reference 2.)
Ri: Temporary register (See Reference 3.)
!
!
!
!
!
!
!
!
!
!
!
!
!
label32,Ri
label32,Ri
label32,Ri
label32,Ri
label32,Ri
label32,Ri
label32,Ri
label32,Ri
label32,Ri
label32,Ri
label32,Ri
label32,Ri
label32,Ri
label32,Ri
label32,Ri
[Reference 1] CALL32
1)
2)
When label32-PC-2 is -0x800 to +0x7fe, the instruction is generated as follows:
CALL label12
When label32-PC-2 exceeds the range in condition 1) or contains an external reference symbol, the
instruction is generated as follows:
LDI:32 #label32,Ri
CALL @Ri
[Reference 2] BRA32
1)
2)
When label32-PC-2 is -0x100 to +0xfe, the instruction is generated as follows:
BRA label9
When label32-PC-2 exceeds the range in condition 1) or contains an external reference symbol, the
instruction is generated as follows:
LDI:32 #label32,Ri
JMP @Ri
[Reference 3] Bcc32
1)
2)
450
When label32-PC-2 is -0x100 to +0xfe, the instruction is generated as follows:
Bcc label9
When label32-PC-2 exceeds the range in condition 1) or contains an external reference symbol, the
instruction is generated as follows:
Bxcc false
xcc is a condition against cc.
LDI:32 #label32,Ri
JMP @Ri
false:
APPENDIX E Instruction Lists
■ 32-bit Delayed Branch Macroinstructions
Table E-19 32-bit Delayed Branch Macroinstructions
Mnemonic
Operation
Remarks
*CALL32:D label32,Ri
Address of the next instruction + 2
--> RP
label32 --> PC
Ri: Temporary register (See Reference 1.)
*BRA32:D
*BEQ32:D
*BNE32:D
*BC32:D
*BNC32:D
*BN32:D
*BP32:D
*BV32:D
*BNV32:D
*BLT32:D
*BGE32:D
*BLE32:D
*BGT32:D
*BLS32:D
*BHI32:D
label32 --> PC
if(Z==1) then label32 -->PC
! s/Z==0
! s/C==1
! s/C==0
! s/N==1
! s/N==0
! s/V==1
! s/V==0
! s/V xor N==1
! s/V xor N==0
! s/(V xor N) or Z==1
! s/(V xor N) or Z==0
! s/C or Z==1
| s/C or Z==0
Ri: Temporary register (See Reference 2.)
Ri: Temporary register (See Reference 3.)
!
!
!
!
!
!
!
!
!
!
!
!
!
label32,Ri
label32,Ri
label32,Ri
label32,Ri
label32,Ri
label32,Ri
label32,Ri
label32,Ri
label32,Ri
label32,Ri
label32,Ri
label32,Ri
label32,Ri
label32,Ri
label32,Ri
[Reference 1] CALL32:D
1)
2)
When label32-PC-2 is -0x800 to +0x7fe, the instruction is generated as follows:
CALL:D label12
When label32-PC-2 exceeds the range in condition 1) or contains an external reference symbol, the
instruction is generated as follows:
LDI:32 #label32,Ri
CALL:D @Ri
[Reference 2] BRA32:D
1)
2)
When label32-PC-2 is -0x100 to +0xfe, the instruction is generated as follows:
BRA:D label9
When label32-PC-2 exceeds the range in condition 1) or contains an external reference symbol, the
instruction is generated as follows:
LDI:32 #label32,Ri
JMP:D @Ri
[Reference 3] Bcc32:D
1)
2)
When label32-PC-2 is -0x100 to +0xfe, the instruction is generated as follows:
Bcc:D label9
When label32-PC-2 exceeds the range in condition 1) or contains an external reference symbol, the
instruction is generated as follows:
Bxcc false
xcc is a condition against cc.
LDI:32 #label32,Ri
JMP:D @Ri
false:
451
APPENDIX E Instruction Lists
■ Direct Addressing Instructions
Table E-20 Direct addressing Instructions
Mnemonic
Type
OP
CYCLE
NZVC
@dir10, R13
R13, @dir10
@dir10, @R13+
@R13+, @dir10*1
@dir10, @-R15
@R15+, @dir10
D
D
D
D
D
D
08
18
0C
1C
0B
1B
b
a
2a
2a
2a
2a
-------------------
(dir10) --> R13
R13 --> (dir10)
(dir10) --> (R13),R13+=4
(R13) --> (dir10),R13+=4
R15-=4,(R15) --> (dir10)
(R15) --> (dir10),R15+=4
Word
Word
Word
Word
Word
Word
DMOVH
DMOVH
DMOVH
DMOVH
@dir9, R13
R13, @dir9
@dir9, @R13+
@R13+, @dir9*1
D
D
D
D
09
19
0D
1D
b
a
2a
2a
-------------
(dir9) --> R13
R13 --> (dir9)
(dir9) --> (R13),R13+=2
(R13) --> (dir9),R13+=2
Halfword
Halfword
Halfword
Halfword
DMOVB
DMOVB
DMOVB
DMOVB
@dir8, R13
R13, @dir8
@dir8, @R13+
@R13+, @dir8*1
D
D
D
D
0A
1A
0E
1E
b
a
2a
2a
-------------
(dir8) --> R13
R13 --> (dir8)
(dir8) --> (R13),R13++
(R13) --> (dir8),R13++
Byte
Byte
Byte
Byte
DMOV
DMOV
DMOV
DMOV
DMOV
DMOV
*1:
Note:
Operation
Remarks
Be sure to put one NOP after the DMOV instruction that uses R13+ as the transfer source.
The assembler performs calculations as shown below and sets values in the dir8, dir9, and dir10
fields:
dir8 --> dir, dir9/2 --> dir, and dir10/4 --> dir. dir8, dir9, and dir10 are unsigned values.
■ Resource Instructions
Table E-21 Resource Instructions
Mnemonic
Type
OP
CYCLE
NZVC
LDRES @Ri+, #u4
C
BC
a
----
STRES #u4, @Ri+
C
BD
a
----
Operation
(Ri) --> u4 resource
Ri+=4
u4 resource --> (Ri)
Ri+=4
Remarks
u4: Channel number
u4: Channel number
■ Coprocessor Control Instructions
Table E-22 Coprocessor Control Instructions
Mnemonic
Type
OP
CYCLE
NZVC
Operation
COPOP #u4, #u8, CRj, CRi
E
9F-C
2+a
----
COPLD #u4, #u8, Rj, CRi
COPST #u4, #u8, CRj, Ri
COPSV #u4, #u8, CRj, Ri
E
E
E
9F-D
9F-E
9F-F
1+2a
1+2a
1+2a
----------
Arithmetic operation
indication
Rj --> CRi
CRj --> Ri
CRj --> Ri
Notes:
•
•
452
Remarks
No error trap
{CRi|CRj}:=
CR0|CR1|CR2|CR3|CR4|CR5|CR6|CR7|CR8|CR9|CR10|CR11|CR12|CR13|CR14|CR15
• u4: Channel specification
• u8: Command specification
This model cannot use these instructions because it has no coprocessor.
INDEX
INDEX
The index follows on the next page.
This is listed in alphabetic order.
453
INDEX
Index
Numerics
0 Detection
0 Detection ...................................................... 385
0 Detection Data Register
0 Detection Data Register (BSD0) ..................... 383
1 Detection
1 Detection ...................................................... 385
1 Detection Data Register
1 Detection Data Register (BSD1) ..................... 383
16-bit Free-run Timer
Count Timing of the 16-bit Free-run Timer ......... 242
Explanation of 16-bit Free-run Timer Operation
.......................................................... 241
Timing to Clear the 16-bit Free-run Timer .......... 242
16-bit Immediate Value
Immediate Value Set,16-bit Immediate Value,and
32-bit Immediate Value Transfer Instructions
.......................................................... 443
16-bit Input Capture
Input Timing of 16-bit Input Capture.................. 247
Operation of 16-bit Input Capture ...................... 246
16-bit Output Compare
Explanation of 16-bit Output Compare Operation
.......................................................... 243
Timing of 16-bit Output Compare ...................... 245
16-bit Reload Register
16-bit Reload Register (TMRLR0 to TMRLR3)
.......................................................... 195
16-bit Reload Timer
Baud Rate Based on the Internal Timer (16-bit Reload
Timer 0) ............................................. 333
Block Diagram of the 16-bit Reload Timer ......... 191
Features of 16-bit Reload Timer ........................ 190
Register List of the 16-bit Reload Timer ............. 192
When the 16-bit Reload Timer is Used for Activation
.......................................................... 225
16-bit Timer Register
16-bit Timer Register (TMR0 to TMR3)............. 195
20-bit Delayed Branch Macroinstructions
20-bit Delayed Branch Macroinstructions ........... 449
20-bit Ordinary Branch Macroinstructions
20-bit Ordinary Branch Macroinstructions .......... 448
32-bit Delayed Branch Macroinstructions
32-bit Delayed Branch Macroinstructions ........... 451
32-bit Immediate Value
Immediate Value Set,16-bit Immediate Value,and
32-bit Immediate Value Transfer Instructions
.......................................................... 443
454
32-bit Ordinary Branch Macroinstructions
32-bit Ordinary Branch Macroinstructions.......... 450
8/10-bit A/D Converter
8/10-bit A/D Converter Block Diagram.............. 279
8/10-bit A/D Converter Interrupt ....................... 292
8/10-bit A/D Converter Pin Block Diagram ........ 282
8/10-bit A/D Converter Pins.............................. 281
Conversion Modes of 8/10-bit A/D Converter
......................................................... 278
Features of the 8/10-bit A/D Converter .............. 278
Notes on Using the 8/10-bit A/D Converter ........ 296
Schema of the 8/10-bit A/D Converter Registers
......................................................... 283
8/16-bit Up/Down Counters/Timers
Block Diagram of the 8/16-bit Up/Down
Counters/Timers ................................. 168
Characteristics of the 8/16-bit Up/Down
Counters/Timers ................................. 166
List of Registers of the 8/16-bit Up/Down
Counters/Timers ................................. 170
8-bit D/A Converter
8-bit D/A Converter Block Diagram .................. 299
8-bit D/A Converter Pins .................................. 299
Features of the 8-bit D/A Converter ................... 298
List of the 8-bit D/A Converter Registers ........... 300
Operation of the 8-bit D/A Converter................. 303
INDEX
A
A/D Control Status Register
A/D Control Status Register 0 (ADCS0) ............ 287
Higher Bits of the A/D Control Status Register 1
(ADCS1)............................................ 284
A/D Converted Data Preservation
A/D Converted Data Preservation Function ........ 295
A/D Converter
8/10-bit A/D Converter Block Diagram.............. 279
8/10-bit A/D Converter Interrupt ....................... 292
8/10-bit A/D Converter Pin Block Diagram ........ 282
8/10-bit A/D Converter Pins.............................. 281
Conversion Modes of 8/10-bit A/D Converter
.......................................................... 278
Features of the 8/10-bit A/D Converter .............. 278
Notes on Using the 8/10-bit A/D Converter ........ 296
Schema of the 8/10-bit A/D Converter Registers
.......................................................... 283
A/D Data Register
A/D Data Register (ADCR) .............................. 290
Acceptance Priority
EIT Source Acceptance Priority .......................... 61
Acceptance Signal
Transfer-Acceptance Signal Output ................... 369
Access
Byte Access..................................................... 133
Data Access....................................................... 48
Halfword Access.............................................. 131
Normal Bus Access .......................................... 135
Program Access ................................................. 48
Word Access ................................................... 130
ADCR
A/D Data Register (ADCR) .............................. 290
ADCS
A/D Control Status Register 0 (ADCS0) ............ 287
Higher Bits of the A/D Control Status Register 1
(ADCS1)............................................ 284
Addition
Addition and Subtraction Instructions ................ 440
Addressing
Direct Addressing Area ...................................... 28
Direct Addressing Instructions .......................... 452
Addressing Mode
Addressing Mode Symbols ............................... 436
AICR
Analog Input Control Register (AICR)............... 164
AMD
AMD0 ............................................................ 108
AMD1 ............................................................ 110
AMD32........................................................... 111
AMD4 ............................................................ 112
AMD5 ............................................................ 113
AMR
Area Select Registers (ASR) and Area Mask Registers
(AMR)................................................106
Analog Input Control Register
Analog Input Control Register (AICR) ...............164
Architecture
Internal Architecture ...........................................31
Area Mask Registers
Area Select Registers (ASR) and Area Mask Registers
(AMR)................................................106
Area Select Registers
Area Select Registers (ASR) and Area Mask Registers
(AMR)................................................106
ASR
Area Select Registers (ASR) and Area Mask Registers
(AMR)................................................106
Assembler Source Code
Example of the Related Assembler Source Code
(Example of Switching to the PLL System)
............................................................90
Asynchronous Mode
Operation in Asynchronous Mode (Operation Modes
0,1) ....................................................338
Automatic Wait Cycle
Automatic Wait Cycle Timing Chart ..................145
B
Basic I/O Port
Block Diagram of Basic I/O Port........................155
Basic Programming Model
Basic Programming Model ..................................40
Basic Read Cycle
Basic Read Cycle Timing Chart .........................136
Basic Write Cycle
Basic Write Cycle Timing Chart ........................138
Baud Rate
Baud Rate Based on the Dedicated Baud-rate
Generator............................................330
Baud Rate Based on the External Clock ..............335
Baud Rate Based on the Internal Timer
(16-bit Reload Timer 0)........................333
UART Baud-rate Selection ................................328
UART Baud-Rate Selection Circuit ....................329
Bidirectional Communication
Bidirectional Communication Function...............343
Big-endian
Big-endian Bus Access......................................118
Comparison of External Access in Big-endian and
Little-endian Mode ..............................118
Differences and Similarities of Access in Little-endian
and in Big-endian Mode .......................126
Bit Manipulation Instructions
Bit Manipulation Instructions.............................441
455
INDEX
Bit Ordering
Bit Ordering....................................................... 47
Bit-search Module
Block Diagram of the Bit-search Module............ 382
Registers of the Bit-search Module .................... 382
Block Diagram
8/10-bit A/D Converter Block Diagram .............. 279
8/10-bit A/D Converter Pin Block Diagram ........ 282
8-bit D/A Converter Block Diagram................... 299
Block Diagram for MB91V151A and MB91151A
.............................................................. 5
Block Diagram of Basic I/O Port ....................... 155
Block Diagram of I/O Port with a Pull-Up Resistor
.......................................................... 156
Block Diagram of I/O Port With Open-Drain Output
Function ............................................. 159
Block Diagram of I/O Port with Open-Drain Output
Function and Pull-Up Resistor .............. 157
Block Diagram of Multifunctional Timer............ 230
Block Diagram of One Channel of the PPG Timer
.......................................................... 204
Block Diagram of the 16-bit Reload Timer ......... 191
Block Diagram of the 8/16-bit Up/Down
Counters/Timers.................................. 168
Block Diagram of the Bit-search Module............ 382
Block Diagram of the Clock Generator................. 72
Block Diagram of the Delayed Interrupt Module
.......................................................... 258
Block Diagram of the DMA Controller............... 351
Block Diagram of the Entire PPG Timer............. 203
Block Diagram of the External-Interrupt Control
Block ................................................. 250
Block Diagram of the Gear Control Block ............ 84
Block Diagram of the Interrupt Controller .......... 263
Block Diagram of the Reset Source Retention Circuit
............................................................ 86
Block Diagram of the Sleep Control Block ........... 96
Block Diagram of the Stop Control Block............. 93
Block Diagram of the Watchdog Control Block
............................................................ 82
Bus Interface Block Diagram............................. 104
I/O Port Block Diagrams................................... 154
UART Block Diagram ...................................... 308
UART Pin Block Diagram ................................ 312
Branch Instructions
Branch Instructions with Delay Slots.................... 52
Branch Instructions without a Delay Slot .............. 55
Explanation of Operation for Branch Instructions
without a Delay Slot .............................. 55
Explanation of the Operation for Branch Instructions
with Delay Slots.................................... 52
Restrictions on Branch Instructions with Delay Slots
............................................................ 54
BSD0
0 Detection Data Register (BSD0) ..................... 383
456
BSD1
1 Detection Data Register (BSD1) ..................... 383
BSDC
Change Point Detection Data Register (BSDC)
......................................................... 384
BSRR
Detection Result Register (BSRR) ..................... 384
Burst Transfer
Burst Transfer.................................................. 366
Burst Transfer Mode ........................................ 362
Bus Access
Big-endian Bus Access ..................................... 118
External Bus Access......................................... 122
Little-endian Bus Access .................................. 118
Normal Bus Access.......................................... 135
Bus Interface
Bus Interface ................................................... 103
Bus Interface Block Diagram ............................ 104
Bus Interface Features ...................................... 102
Registers of the Bus Interface............................ 105
Bus Request
External Bus Request ....................................... 135
Bus Right
Bus Right Acquisition ...................................... 147
Releasing Bus Right......................................... 147
Bus Width
Data Bus Width ....................................... 121, 128
Relationship Between Data Bus Width and Control
Signals ....................................... 118, 119
Byte Access
Byte Access..................................................... 133
Byte Ordering
Byte Ordering.................................................... 47
C
CCRH/CCRL
Counter Control Register High/Low ch0
(CCRH/CCRL) ................................... 171
Counter Control Register High/Low ch1
(CCRH/CCRL) ................................... 175
CDCR
Communication Prescaler Control Register (CDCR)
......................................................... 322
Change Point Detection
Change Point Detection .................................... 385
Change Point Detection Data Register
Change Point Detection Data Register (BSDC)
......................................................... 384
Character-string Handling Function
Manipulation of a Non-character Type Array by Using
a Character-string Handling Function
......................................................... 430
Specification of the -K lib Option During Use of a
Character-string Handling Function ...... 430
INDEX
Chip Select
Chip Select Area .............................................. 102
Circuit
Block Diagram of the Reset Source Retention Circuit
............................................................ 86
UART Baud-Rate Selection Circuit ................... 329
Circuit Handling
Circuit Handling ................................................ 23
Clock
Internal Clock Operation................................... 196
Baud Rate Based on the External Clock ............. 335
Clock Generator
Block Diagram of the Clock Generator ................ 72
Register Configuration of Clock Generator........... 71
Clock Selection
Clock Selection Method.................................... 148
Clock System
Reference Chart for the Clock System.................. 89
Command
Command List ................................................. 398
Communication
Bidirectional Communication Function .............. 343
Master/Slave-type Communication Function ...... 345
Communication Mode
Communication Mode of Serial-Start ................. 395
Communication Prescaler Control Register
Communication Prescaler Control Register (CDCR)
.......................................................... 322
Compare Clear Register
Compare Clear Register.................................... 232
Compare Detection Flag
Compare Detection Flag ................................... 188
Compare Function
Example for Selection of Reload and Compare
Function............................................. 183
When the Compare Function is Enabled ............. 184
When the Reload and Compare Functions are Enabled
Simultaneously ................................... 184
Compare Register
Compare Register (OCCP0 to OCCP7) .............. 235
Comparison Operation Instruction
Comparison Operation Instruction ..................... 440
Continuous Transfer
Continuous Transfer......................................... 365
Continuous Transfer Mode
Continuous Transfer Mode................................ 362
Transfer Termination in Continuous Transfer Mode
(When both Addresses are Changed),
16/8-bit Data ...................................... 377
Transfer Termination in Continuous Transfer Mode
(When Either Address is Fixed),
16/8-bit Data ...................................... 376
Continuous-conversion Mode
Operation in Continuous-conversion Mode......... 293
Control Register
Control Register (SCR0 to SCR3) ......................314
Control Register Configuration ............................35
Control Signals
Relationship Between Data Bus Width and Control
Signals........................................118, 119
Control Status Register
Control Status Register (TMCSR0 to TMCSR3)
..........................................................193
Control Status Registers (PCNH0 to PCNH5,
PCNL0 to PCNH5) ..............................207
Conversion Mode
Operation in Continuous-conversion Mode .........293
Operation in Intermittent-conversion Mode .........294
Operation in Single-conversion Mode.................293
Coprocessor Absence Trap
Coprocessor Absence Trap ..................................66
Coprocessor Control Instructions
Coprocessor Control Instructions .......................452
Coprocessor Error Trap
Coprocessor Error Trap .......................................66
Count Clear/Gate Function
Count Clear/Gate Function ................................187
Count Direction Change Flag
Count Direction Change Flag.............................188
Count Direction Flag
Count Direction Flag.........................................188
Counter
Counter Operation States...................................199
Counter Control Register
Counter Control Register High/Low ch0
(CCRH/CCRL)....................................171
Counter Status Register
Counter Status Register 0/1 (CSR0,CSR1) ..........176
Counting Mode
Phase Difference Counting Mode
(Two Multiplication/Four Multiplication)
..........................................................180
Selecting Counting Mode ..................................180
Up/Down Counting Mode .................................180
CPU
Pin Status in Each CPU State .............................422
CPU State
Pin Status in Each CPU State .............................422
CSR
Counter Status Register 0/1 (CSR0,CSR1) ..........176
CTBR
Timebase Timer Clear Register (CTBR) ...............76
Cycles
Timing Chart for Mixed Read/Write Cycles ........144
457
INDEX
D
D/A Control Registers
D/A Control Registers (DACR0,DACR1,DACR2)
.......................................................... 301
D/A Converter
8-bit D/A Converter Block Diagram................... 299
8-bit D/A Converter Pins................................... 299
Features of the 8-bit D/A Converter ................... 298
List of the 8-bit D/A Converter Registers............ 300
Operation of the 8-bit D/A Converter ................. 303
D/A Data Registers
D/A Data Registers (DADR2,DADR1,DADR0)
.......................................................... 302
DACR
D/A Control Registers (DACR0,DACR1,DACR2)
.......................................................... 301
DACSR
DMAC Control Status Register (DACSR) .......... 354
DADR
D/A Data Registers (DADR2,DADR1,DADR0)
.......................................................... 302
Data Access
Data Access ....................................................... 48
Data Bus Width
Data Bus Width........................................ 121, 128
Relationship Between Data Bus Width and
Control Signals ........................... 118, 119
Data Direction Register
Data Direction Register (DDR2 to DDRL).......... 161
Data Format
Data Format............................................. 120, 127
Data Register
Data Register (TCDT) ...................................... 232
Data Transfer Section
Data Transfer Section,16/8-bit Data ................... 375
DATCR
DMAC Pin Control Register (DATCR) .............. 356
DDR
Data Direction Register (DDR2 to DDRL).......... 161
DDRL
Data Direction Register (DDR2 to DDRL).......... 161
Debugger
Emulator Debugger and Monitor Debugger ........ 434
Simulator Debugger.......................................... 434
Dedicated Baud-rate Generator
Baud Rate Based on the Dedicated
Baud-rate Generator ............................ 330
Delay
Causes of Reset Delays Other than Programs ........ 83
Ordinary Branch (No Delay) Instructions ........... 445
Delay Slot
Branch Instructions with Delay Slots.................... 52
Branch Instructions without a Delay Slot .............. 55
458
Delay Slot ......................................................... 56
Explanation of Operation for Branch Instructions
without a Delay Slot.............................. 55
Explanation of the Operation for Branch Instructions
with Delay Slots ................................... 52
Restrictions on Branch Instructions with Delay Slots
........................................................... 54
Delayed Branch Instructions
Delayed Branch Instructions ............................. 446
Delayed Branch Macroinstructions
20-bit Delayed Branch Macroinstructions........... 449
32-bit Delayed Branch Macroinstructions........... 451
Delayed Interrupt Module
Block Diagram of the Delayed Interrupt Module
......................................................... 258
List of Delayed Interrupt Module Registers ........ 258
Delayed-Interrupt Control Register
Delayed-Interrupt Control Register (DICR) ........ 259
Descriptor
Descriptor Access Section ................................ 373
Descriptor Start Word ...................................... 358
Second Word in the Descriptor.......................... 360
Third Word in the Descriptor ............................ 360
Detection
0 Detection...................................................... 385
1 Detection...................................................... 385
Change Point Detection .................................... 385
Detection Result Register
Detection Result Register (BSRR) ..................... 384
DICR
Delayed-Interrupt Control Register (DICR) ........ 259
DLYI Bit of DICR ........................................... 260
Direct Addressing
Direct Addressing Area ...................................... 28
Direct Addressing Instructions
Direct Addressing Instructions .......................... 452
Division Instructions
Multiplication and Division Instructions............. 442
DLYI Bit
DLYI Bit of DICR ........................................... 260
DMA Controller
Block Diagram of the DMA Controller .............. 351
Features of the DMA Controller ........................ 350
Registers of the DMA Controller ....................... 352
DMA Request Suppression Register
DMA Request Suppression Register (PDRR) ....... 80
DMA Transfer
DMA Transfer Operation in Sleep Mode............ 371
Notes on Using a Resource Interrupt Request
as a DMA Transfer Request ................. 370
Suppression of DMA Transfer upon Generation of
a Higher-priority Interrupt.................... 370
DMAC Control Status Register
DMAC Control Status Register (DACSR) .......... 354
INDEX
DMAC Internal Register
Transfer Operation to DMAC Internal Register
.......................................................... 371
DMAC Parameter Descriptor Pointer
DMAC Parameter Descriptor Pointer (DPDP)
.......................................................... 353
DMAC Pin Control Register
DMAC Pin Control Register (DATCR).............. 356
Double Type
Using Double Type and Long-double Type ........ 430
Down Count
Timer Mode [Down Count]............................... 180
DPDP
DMAC Parameter Descriptor Pointer (DPDP)
.......................................................... 353
DREC Signal Sense Modes
DREC Signal Sense Modes............................... 363
E
Edge Mode
Notes on Edge Mode ........................................ 368
EIRR
External-Interrupt Request Register (EIRR0,EIRR1:
External-Interrupt Request Register n)
.......................................................... 253
EIT
EIT Source Acceptance Priority .......................... 61
EIT Sources....................................................... 56
EIT Vector Table ............................................... 59
Notes on EIT ..................................................... 56
Return from EIT ................................................ 56
ELVR
External Level Register (ELVR0,ELVR1: External
Level Register) ................................... 254
Emulator Debugger
Emulator Debugger and Monitor Debugger ........ 434
Enable Interrupt Register
Enable Interrupt Register (ENIR0,ENIR1: ENable
Interrupt Register) ............................... 252
End Signal
Transfer-End Signal Output .............................. 369
ENIR
Enable Interrupt Register (ENIR0,ENIR1: ENable
Interrupt Register) ............................... 252
Entire PPG Timer
Block Diagram of the Entire PPG Timer ............ 203
EPCR
EPCR0............................................................ 114
EPCR1............................................................ 116
Errors
Failure to Detect Errors .................................... 433
Example
Examples for Setting PWM Output to All-low or
All-high ..............................................222
Exception
Operation for an Undefined Instruction Exception
............................................................65
External Access
Comparison of External Access in Big-endian and
Little-endian Mode ..............................118
External Bus Access
External Bus Access .........................................122
External Bus Operation
Program Example for External Bus Operation
..........................................................151
Specification Example of a Program for External Bus
Operation............................................150
External Bus Request
External Bus Request ........................................135
External Clock
Baud Rate Based on the External Clock ..............335
External Clock ...................................................24
External Devices
Example of Connection with External Devices
..........................................................125
Examples of Connection with External Devices
..........................................................129
External Interrupt
External-Interrupt Operation ..............................255
External-Interrupt Request Level........................256
List of External-Interrupt Registers ....................251
Setting Procedure for an External Interrupt..........255
External Level Register
External Level Register (ELVR0,ELVR1:
External Level Register).......................254
External-Interrupt Control
Block Diagram of the External-Interrupt
Control Block......................................250
External-Interrupt Request Register
External-Interrupt Request Register (EIRR0,EIRR1:
External-Interrupt Request Register n)
..........................................................253
External Reset
External Reset Input............................................24
External Wait Cycle
Timing Chart of External Wait Cycle .................146
F
Flag
Compare Detection Flag....................................188
Count Direction Change Flag.............................188
Count Direction Flag.........................................188
Receive-Interrupt Generation and Flag Set Timing
..........................................................326
459
INDEX
Send-Interrupt Generation and Flag Set Timing
.......................................................... 327
FPT-144P-M08
Package Dimensions of FPT-144P-M08 ................. 7
Pin Assignments of MB91151A (FPT-144P-M08)
............................................................ 10
FR Family
FR Family Instruction Lists ............................... 439
Free-run Timer
Count Timing of the 16-bit Free-run Timer ......... 242
Explanation of 16-bit Free-run Timer Operation
.......................................................... 241
Timing to Clear the 16-bit Free-run Timer .......... 242
Function
Example for Selection of Reload and Compare
Function ............................................. 183
When the Reload and Compare Functions are Enabled
Simultaneously ................................... 184
G
GCN
Activating Multiple Channels with the GCN ....... 224
General Control Register 1 (GCN1) ................... 214
General Control Register 2 (GCN2) ................... 217
GCR
Gear Control Register (GCR) .............................. 77
Gear
Settings of the Gear Function .............................. 85
Gear Control Block
Block Diagram of the Gear Control Block ............ 84
Gear Control Register
Gear Control Register (GCR) .............................. 77
General Control Register
General Control Register 1 (GCN1) ................... 214
General Control Register 2 (GCN2) ................... 217
General-purpose Registers
General-purpose Registers................................... 41
Generator
Baud Rate Based on the Dedicated
Baud-rate Generator ............................ 330
H
Halfword Access
Halfword Access .............................................. 131
Hardware Configuration
Hardware Configuration.................................... 274
Hardware Configuration of Interrupt Controller
.......................................................... 262
Hold Request Cancellation Requests
Levels That Can Be Set for Hold Request Cancellation
Requests............................................. 273
460
Hold-request Cancellation Request Level Set
Register
Hold-request Cancellation Request Level Set Register
(HRCL) ............................................. 268
Hold-request Cancellation-request
Criteria for Determining whether a Hold-request
Cancellation-request Must be Issued ..... 273
Hold-request Cancellation-request Sequence ...... 275
HRCL
Hold-request Cancellation Request Level Set Register
(HRCL) ............................................. 268
I
I/O Circuit
I/O Circuit Types ............................................... 18
I/O Map
How to Use the I/O Map................................... 410
I/O Map .......................................................... 411
I/O Port
Block Diagram of Basic I/O Port ....................... 155
Block Diagram of I/O Port with a Pull-Up Resistor
......................................................... 156
Block Diagram of I/O Port With Open-Drain Output
Function............................................. 159
Block Diagram of I/O Port with Open-Drain Output
Function and Pull-Up Resistor.............. 157
I/O Port Block Diagrams .................................. 154
I/O Port Registers ............................................ 154
I-Cache
Setting Method when Using I-Cache of This Type
........................................................... 37
ICR
Interrupt Control Register (ICR)........................ 266
ICS
Input Capture Control Register (ICS01,ICS23)
......................................................... 238
Immediate Value
Immediate Value Set,16-bit Immediate Value,and
32-bit Immediate Value Transfer Instructions
......................................................... 443
Initial Values
Allocation of Variables Having Initial Values..... 429
Initialization
Initialization by Reset......................................... 67
Input Capture
Input Timing of 16-bit Input Capture ................. 247
Operation of 16-bit Input Capture ...................... 246
Input Capture Control Register
Input Capture Control Register (ICS01,ICS23)
......................................................... 238
Input Capture Data Register
Input Capture Data Register (IPCP0 to IPCP3)
......................................................... 238
INDEX
Input-data Register
Input-data Register (SIDR0 to SIDR3) ............... 320
Instruction
Addition and Subtraction Instructions ................ 440
Bit Manipulation Instructions ............................ 441
Branch Instructions with Delay Slots ................... 52
Branch Instructions without a Delay Slot.............. 55
Comparison Operation Instruction ..................... 440
Coprocessor Control Instructions....................... 452
Delayed Branch Instructions ............................. 446
Direct Addressing Instructions .......................... 452
Explanation of Operation for Branch Instructions
without a Delay Slot .............................. 55
Explanation of the Operation for Branch Instructions
with Delay Slots.................................... 52
FR Family Instruction Lists............................... 439
How to Read the Instruction Lists...................... 435
Immediate Value Set,16-bit Immediate Value,and
32-bit Immediate Value Transfer Instructions
.......................................................... 443
Instruction Format............................................ 438
Logical Operation Instructions .......................... 440
Memory Load Instructions ................................ 443
Memory Store Instructions................................ 444
Multiplication and Division Instructions............. 442
Operation for an Undefined Instruction Exception
............................................................ 65
Operation for INT Instruction.............................. 64
Operation for INTE Instruction ........................... 64
Operation for RETI Instruction............................ 66
Ordinary Branch (No Delay) Instructions ........... 445
Other Instructions ............................................ 447
Overview of Instructions..................................... 50
Register-to-Register Transfer Instructions .......... 444
Resource Instructions ....................................... 452
Restrictions on Branch Instructions with Delay Slots
............................................................ 54
Shift Instructions.............................................. 442
Instruction Cache
Area That can be Used for the Instruction Cache
............................................................ 37
Configuration of the Instruction Cache................. 33
INT Instruction
Operation for INT Instruction.............................. 64
INTE Instruction
Operation for INTE Instruction ........................... 64
Interchannel Priority
Interchannel Priority......................................... 370
Interface
Bus Interface ................................................... 103
Bus Interface Block Diagram ............................ 104
Bus Interface Features ...................................... 102
Registers of the Bus Interface............................ 105
Intermittent-conversion Mode
Operation in Intermittent-conversion Mode ........ 294
Internal Architecture
Internal Architecture ...........................................31
Internal Clock
Internal Clock Operation ...................................196
Internal Timer
Baud Rate Based on the Internal Timer
(16-bit Reload Timer 0)........................333
Interrupt
8/10-bit A/D Converter Interrupt ........................292
Interrupt Level ...................................................57
Interrupt Number ..............................................260
Interrupt Stack....................................................58
Level Mask for Interrupts ....................................57
Notes on Using a Resource Interrupt Request as a
DMA Transfer Request ........................370
PWM Timer Interrupt Sources and Timing Chart
(PWM Output: Normal Polarity) ...........222
Receive-Interrupt Generation and Flag Set Timing
..........................................................326
Releasing Interrupt Factors ................................271
Send-Interrupt Generation and Flag Set Timing
..........................................................327
Suppression of DMA Transfer upon Generation of
a Higher-priority Interrupt ....................370
UART Interrupts ..............................................324
UART-related Interrupts ...................................325
User Interrupt Operation......................................63
Interrupt Control Register
Interrupt Control Register (ICR) ........................266
Interrupt Controller
Block Diagram of the Interrupt Controller...........263
Hardware Configuration of Interrupt Controller
..........................................................262
List of Interrupt Controller Registers ..................264
Main Functions of the Interrupt Controller ..........262
Interrupt Vectors
Interrupt Vectors ..............................................417
IPCP
Input Capture Data Register (IPCP0 to IPCP3)
..........................................................238
K
-K lib Option
Specification of the -K lib Option During Use of
a Character-string Handling Function
..........................................................430
L
Latch-up
Latch-up Prevention............................................22
LER
LER ................................................................117
Level Mode
Notes on Level Mode ........................................367
461
INDEX
Little-endian
Allocation of Stacks in the Little-endian Area
.......................................................... 431
Comparison of External Access in Big-endian and
Little-endian Mode .............................. 118
Differences and Similarities of Access in Little-endian
and in Big-endian Mode....................... 126
Little-endian Bus Access................................... 118
Logical Operation Instructions
Logical Operation Instructions........................... 440
Long-double Type
Using Double Type and Long-double Type......... 430
Low-power Consumption Mode
Low-power Consumption Mode Operations.......... 92
Status Transition of the Low-power Consumption
Mode ................................................... 99
M
Macroinstructions
20-bit Delayed Branch Macroinstructions ........... 449
20-bit Ordinary Branch Macroinstructions .......... 448
32-bit Delayed Branch Macroinstructions ........... 451
32-bit Ordinary Branch Macroinstructions .......... 450
Mask
Level Mask for Interrupts.................................... 57
Master/slave-type Communication
Master/Slave-type Communication Function....... 345
MB91151A
Block Diagram for MB91V151A and MB91151A
.............................................................. 5
Functions of the MB91151A Pins ........................ 11
MB91151A Features............................................. 2
Memory Map for MB91V151A and MB91151A
............................................................ 29
Memory Map of MB91151A ............................... 49
Pin Assignments of MB91151A (FPT-144P-M08)
............................................................ 10
Pin Assignments of MB91151A (PGA-299C-A01)
.............................................................. 8
MB91V151A
Block Diagram for MB91V151A and MB91151A
.............................................................. 5
Memory Map for MB91V151A and MB91151A
............................................................ 29
MDH
Multiplication and Division Result Registers
(MDH and MDL) .................................. 46
MDL
Multiplication and Division Result Registers
(MDH and MDL) .................................. 46
Memory Load Instructions
Memory Load Instructions ................................ 443
462
Memory Map
Memory Map for MB91V151A and MB91151A
........................................................... 29
Memory Map of MB91151A............................... 49
Memory Store Instructions
Memory Store Instructions................................ 444
Mixed Read/Write Cycles
Timing Chart for Mixed Read/Write Cycles ....... 144
Mode
Addressing Mode Symbols ............................... 436
Burst Transfer Mode ........................................ 362
Communication Mode of Serial-Start................. 395
Comparison of External Access in Big-endian and
Little-endian Mode.............................. 118
Continuous Transfer Mode ............................... 362
Differences and Similarities of Access in Little-endian
and in Big-endian Mode ...................... 126
Mode Data ........................................................ 69
Mode Pins ......................................................... 68
Note on During Operation of PLL Clock Mode
........................................................... 24
Notes on Edge Mode ........................................ 368
Notes on Level Mode ....................................... 367
Operation in Asynchronous Mode
(Operation Modes 0,1)......................... 338
Operation in Continuous-conversion Mode......... 293
Operation in Intermittent-conversion Mode ........ 294
Operation in Single-conversion Mode ................ 293
Operation in Synchronous Mode (operation Mode 2)
......................................................... 341
Operation Mode................................................. 68
Return from Standby (Stop or Sleep) Mode ........ 272
Selecting Counting Mode ................................. 180
Single/Block Transfer Mode ............................. 361
Status in Each Operation Mode ........................... 36
Timing Chart of Read Cycles in Each Mode ....... 140
Transfer Termination in Continuous Transfer Mode
(When both Addresses are Changed),
16/8-bit Data ...................................... 377
Transfer Termination in Continuous Transfer Mode
(When Either Address is Fixed),16/8-bit Data
......................................................... 376
Up/Down Counting Mode................................. 180
Write Cycle Timing in Each Mode .................... 142
Mode Register
Mode Register (SMR0 to SMR3) ...................... 316
Modes
Combinations of Request Sense Modes and Transfer
Modes................................................ 363
DREC Signal Sense Modes............................... 363
Monitor Debugger
Emulator Debugger and Monitor Debugger ........ 434
Multifunctional Timer
Block Diagram of Multifunctional Timer ........... 230
Configuration of the Multifunctional Timers
......................................................... 228
INDEX
Explanation of Multifunctional Timer Operation
.......................................................... 240
Registers of Multifunctional Timers................... 231
Multiple Channels
Activating Multiple Channels with the GCN....... 224
Multiplication
Multiplication and Division Instructions............. 442
Phase Difference Counting Mode
(Two Multiplication/Four Multiplication)
.......................................................... 180
Multiplication and Division Result Registers
Multiplication and Division Result Registers
(MDH and MDL).................................. 46
N
No Delay
Ordinary Branch (No Delay) Instructions ........... 445
Non-character Type Array
Manipulation of a Non-character Type Array by Using
a Character-string Handling Function
.......................................................... 430
Normal Bus Access
Normal Bus Access .......................................... 135
Normal Polarity
PWM Timer Interrupt Sources and Timing Chart
(PWM Output: Normal Polarity) .......... 222
O
OCCP
Compare Register (OCCP0 to OCCP7) .............. 235
OCRH
Open-Drain Control Register (OCRH and OCRI)
.......................................................... 163
OCRI
Open-Drain Control Register (OCRH and OCRI)
.......................................................... 163
OCS
Output Control Register (OCS0toOCS7) ............ 235
One-shot Operation
One-shot Operation .......................................... 220
Open-Drain Control Register
Open-Drain Control Register (OCRH and OCRI)
.......................................................... 163
Open-Drain Output
Block Diagram of I/O Port With Open-Drain Output
Function............................................. 159
Block Diagram of I/O Port with Open-Drain Output
Function and Pull-Up Resistor.............. 157
Operation
Operations for 8 Bits X 2 Channels and 16 Bits X 1
Channel.............................................. 188
Operation Mode
Operation in Asynchronous Mode (Operation Modes
0,1) ....................................................338
Operation in Synchronous Mode (operation Mode 2)
..........................................................341
Operation Mode .................................................68
Status in Each Operation Mode ............................36
Operation States
Counter Operation States...................................199
Option
Specification of the -K lib Option During Use of a
Character-string Handling Function .......430
Ordering
Bit Ordering .......................................................47
Byte Ordering ....................................................47
Ordinary Branch
Ordinary Branch (No Delay) Instructions............445
Ordinary Branch Macroinstructions
20-bit Ordinary Branch Macroinstructions ..........448
32-bit Ordinary Branch Macroinstructions ..........450
Output Compare
Explanation of 16-bit Output Compare Operation
..........................................................243
Timing of 16-bit Output Compare ......................245
Output Control Register
Output Control Register (OCS0toOCS7).............235
Output Pin
Function of Output Pin ......................................198
Output-data Register
Output-data Register (SODR0 to SODR3) ..........320
P
Package Dimensions
Package Dimensions of FPT-144P-M08 .................7
Package Dimensions of PGA-299C-A01.................6
PC
Program Counter (PC).........................................45
PCNH
Control Status Registers (PCNH0 to PCNH5,
PCNL0 to PCNH5) ..............................207
PCNL
Control Status Registers (PCNH0 to PCNH5,
PCNL0 to PCNH5) ..............................207
PCR
Pull-up Resistor Control Register (PCR6 to PCRI)
..........................................................162
PCRI
Pull-up Resistor Control Register (PCR6 to PCRI)
..........................................................162
PCSR
PWM Cycle Set Register (PCSR0 to PCSR5)
..........................................................211
463
INDEX
PCTR
PLL Control Register (PCTR) ............................. 81
PDR
Port Data Register (PDR2 to PDRL) .................. 160
PDRL
Port Data Register (PDR2 to PDRL) .................. 160
PDRR
DMA Request Suppression Register (PDRR) ........ 80
PDUT
PWM Duty Set Register (PDUT0 to PDUT5)
.......................................................... 212
Peripheral Stop Control Registers
Operation of Peripheral Stop Control Registers and
Applicable Notes................................. 388
Peripheral Stop Control Registers ...................... 388
PGA-299C-A01
Package Dimensions of PGA-299C-A01 ................ 6
Pin Assignments of MB91151A (PGA-299C-A01)
.............................................................. 8
Phase Difference Counting Mode
Phase Difference Counting Mode
(Two Multiplication/Four Multiplication)
.......................................................... 180
Pin Assignments
Pin Assignments of MB91151A (FPT-144P-M08)
............................................................ 10
Pin Assignments of MB91151A (PGA-299C-A01)
.............................................................. 8
Pin Processing
Pin Processing.................................................... 22
Pin Status
Pin Status in Each CPU State............................. 422
Terms Related to Pin Status............................... 421
PLL Clock
Example of Setting the PLL Clock ....................... 88
PLL Clock Mode
Note on During Operation of PLL Clock Mode
............................................................ 24
PLL Control Register
PLL Control Register (PCTR) ............................. 81
PLL System
Example of the Related Assembler Source Code
(Example of Switching to the PLL System)
............................................................ 90
Polarity
PWM Timer Interrupt Sources and Timing Chart
(PWM Output: Normal Polarity)........... 222
Port Data Register
Port Data Register (PDR2 to PDRL) .................. 160
Power-On
Notes on Power-On ............................................ 25
464
PPG Timer
Block Diagram of One Channel of the PPG Timer
......................................................... 204
Block Diagram of the Entire PPG Timer ............ 203
Features of PPG Timers.................................... 202
Register List of PPG Timers ............................. 205
Preservation
A/D Converted Data Preservation Function ........ 295
Priority
EIT Source Acceptance Priority .......................... 61
Interchannel Priority......................................... 370
Priority Evaluation ........................................... 269
Suppression of DMA Transfer upon Generation of
a Higher-priority Interrupt.................... 370
Program
Program Example for External Bus Operation
......................................................... 151
Specification Example of a Program for External Bus
Operation ........................................... 150
Program Access
Program Access ................................................. 48
Program Counter
Program Counter (PC) ........................................ 45
Program Status
Program Status (PS) ........................................... 42
Programming Model
Basic Programming Model ................................. 40
PS
Program Status (PS) ........................................... 42
PTMR
PWM Timer Register (PTMR0 to PTMR5) ........ 213
Pull-Up Resistor
Block Diagram of I/O Port with a Pull-Up Resistor
......................................................... 156
Block Diagram of I/O Port with Open-Drain Output
Function and Pull-Up Resistor.............. 157
Pull-up Resistor Control Register
Pull-up Resistor Control Register (PCR6 to PCRI)
......................................................... 162
PWM
Examples for Setting PWM Output to All-low or
All-high ............................................. 222
PWM Operation............................................... 218
PWM Cycle Set Register
PWM Cycle Set Register (PCSR0 to PCSR5)
......................................................... 211
PWM Duty Set Register
PWM Duty Set Register (PDUT0 to PDUT5)
......................................................... 212
PWM Timer
PWM Timer Interrupt Sources and Timing Chart
(PWM Output: Normal Polarity) .......... 222
PWM Timer Register
PWM Timer Register (PTMR0 to PTMR5) ........ 213
INDEX
R
RCR
Reload/compare Register 0/1 (RCR0,RCR1) ...... 179
Read
Timing Chart for Mixed Read/Write Cycles ....... 144
Read Cycle
Basic Read Cycle Timing Chart......................... 136
Timing Chart of Read Cycles in Each Mode ....... 140
Receive-interrupt
Receive-interrupt Generation and Flag Set Timing
.......................................................... 326
Reference Chart
Reference Chart for the Clock System.................. 89
Register-to-register Transfer Instructions
Register-to-Register Transfer Instructions .......... 444
Reload
Example for Selection of Reload and Compare
Function............................................. 183
When the Reload and Compare Functions are Enabled
Simultaneously ................................... 184
Reload Function
When the Reload Function is Enabled ................ 183
Reload Timer
Block Diagram of the 16-bit Reload Timer ......... 191
Features of 16-bit Reload Timer ........................ 190
Register List of the 16-bit Reload Timer............. 192
When the 16-bit Reload Timer is Used for Activation
.......................................................... 225
Baud Rate Based on the Internal Timer (16-bit Reload
Timer 0) ............................................. 333
Reload/compare Register
Reload/Compare Register 0/1 (RCR0,RCR1)
.......................................................... 179
Request Sense Modes
Combinations of Request Sense Modes and Transfer
Modes................................................ 363
Reset
Causes of Reset Delays Other than Programs........ 83
Delaying Reset Generation.................................. 83
External Reset Input ........................................... 24
Initialization by Reset......................................... 67
Reset Sequence.................................................. 67
Reset Sources .................................................... 67
Reset Source Register
Reset Source Register (RSRR) and Watchdog Cycle
Control Register (WTCR) ...................... 73
Reset Source Retention Circuit
Block Diagram of the Reset Source Retention Circuit
............................................................ 86
Resource Instructions
Resource Instructions ....................................... 452
Resource Interrupt Request
Notes on Using a Resource Interrupt Request as
a DMA Transfer Request ..................... 370
Restoring
Processing for Saving and Restoring...................386
RETI Instruction
Operation for RETI Instruction ............................66
Return Pointer
Return Pointer (RP) ............................................45
RP
Return Pointer (RP) ............................................45
RSRR
Reset Source Register (RSRR) and Watchdog Cycle
Control Register (WTCR).......................73
S
Saving
Processing for Saving and Restoring...................386
SCR
Control Register (SCR0 to SCR3) ......................314
Second Word
Second Word in the Descriptor ..........................360
Section
Data Transfer Section,16/8-bit Data....................375
Descriptor Access Section .................................373
Section Types
Restriction on Section Types .............................433
Send-interrupt
Send-interrupt Generation and Flag Set Timing
..........................................................327
Sense Modes
Combinations of Request Sense Modes and Transfer
Modes ................................................363
DREC Signal Sense Modes ...............................363
Serial-Start
Communication Mode of Serial-Start .................395
Shift Instructions
Shift Instructions ..............................................442
SIDR
Input-data Register (SIDR0 to SIDR3)................320
Signals
Relationship Between Data Bus Width and Control
Signals........................................118, 119
Simulator Debugger
Simulator Debugger ..........................................434
Single/Block Transfer
Step Transfer (Single/Block Transfer).................364
Single/block Transfer Mode
Single/Block Transfer Mode ..............................361
Single-conversion Mode
Operation in Single-conversion Mode.................293
Sleep
Return from Standby (Stop or Sleep) Mode.........272
Sleep Control Block
Block Diagram of the Sleep Control Block............96
465
INDEX
Sleep Mode
DMA Transfer Operation in Sleep Mode ............ 371
Sleep Status
Overview of the Sleep Status ............................... 91
Return from the Sleep Status ............................... 97
Transition to the Sleep Status .............................. 96
SMR
Mode Register (SMR0 to SMR3)....................... 316
SODR
Output-data Register (SODR0 to SODR3) .......... 320
Source Code
Example of the Related Assembler Source Code
(Example of Switching to the PLL System)
............................................................ 90
SSP
System Stack Pointer (SSP)................................. 45
SSR
Status Register (SSR0 to SSR3)......................... 318
Stack
Allocation of Stacks in the Little-endian Area ..... 431
Interrupt Stack ................................................... 58
Standby
Return from Standby (Stop or Sleep) Mode ........ 272
Standby Control Register
Standby Control Register (STCR) ........................ 75
Start Word
Descriptor Start Word....................................... 358
Status Register
Status Register (SSR0 to SSR3)......................... 318
Status Transition
Status Transition of the Low-power Consumption
Mode ................................................... 99
STCR
Standby Control Register (STCR) ........................ 75
Step Trace
Operation for Step Trace Trap ............................. 65
Step Transfer
Step Transfer (Single/Block Transfer) ................ 364
Stop
Return from Standby (Stop or Sleep) Mode ........ 272
Stop Control Block
Block Diagram of the Stop Control Block............. 93
Stop Control Register
Stop Control Register 0 (STPR0) ....................... 389
Stop Control Register 1 (STPR1) ....................... 390
Stop Control Register 2 (STPR2) ....................... 391
Stop State
Return from Stop State...................................... 255
Stop Status
Overview of the Stop Status ................................ 91
Return from the Stop Status................................. 95
Transition to Stop Status ..................................... 93
466
STPR
Stop Control Register 0 (STPR0)....................... 389
Stop Control Register 1 (STPR1)....................... 390
Stop Control Register 2 (STPR2)....................... 391
Structure Insertion
Structure Insertion............................................ 429
Subtraction Instructions
Addition and Subtraction Instructions ................ 440
Synchronous Mode
Operation in Synchronous Mode (operation Mode 2)
......................................................... 341
System Stack Pointer
System Stack Pointer (SSP) ................................ 45
T
Table Base Register
Table Base Register (TBR) ................................. 45
TBR
Table Base Register (TBR) ................................. 45
TCCS
Timer Control Status Register (TCCS) ............... 233
TCDT
Data Register (TCDT) ...................................... 232
Third Word
Third Word in the Descriptor ............................ 360
Timebase Timer
Timebase Timer................................................. 83
Timebase Timer Clear Register
Timebase Timer Clear Register (CTBR) .............. 76
Timer Control Status Register
Timer Control Status Register (TCCS) ............... 233
Timer Mode
Timer Mode [Down Count]............................... 180
Timing Chart
Automatic Wait Cycle Timing Chart.................. 145
Basic Read Cycle Timing Chart ........................ 136
Basic Write Cycle Timing Chart........................ 138
PWM Timer Interrupt Sources and Timing Chart
(PWM Output: Normal Polarity) .......... 222
Symbols Used in the Timing Charts................... 372
Timing Chart for Mixed Read/Write Cycles ....... 144
Timing Chart of External Wait Cycle................. 146
Timing Chart of Read Cycles in Each Mode ....... 140
TMCSR
Control Status Register (TMCSR0 to TMCSR3)
......................................................... 193
TMR
16-bit Timer Register (TMR0 to TMR3) ............ 195
TMRLR
16-bit Reload Register (TMRLR0 to TMRLR3)
......................................................... 195
INDEX
Transfer Instructions
Immediate Value Set,16-bit Immediate Value,and
32-bit Immediate Value Transfer Instructions
.......................................................... 443
Register-to-Register Transfer Instructions .......... 444
Transfer Mode
Burst Transfer Mode ........................................ 362
Combinations of Request Sense Modes and Transfer
Modes................................................ 363
Continuous Transfer Mode................................ 362
Single/Block Transfer Mode ............................. 361
Transfer Termination in Continuous Transfer Mode
(When both Addresses are Changed),16/8-bit
data.................................................... 377
Transfer Termination in Continuous Transfer Mode
(When Either Address is Fixed),16/8-bit data
.......................................................... 376
Transfer Operation
Transfer Operation to DMAC Internal Register
.......................................................... 371
Transfer Termination
Transfer Termination in Continuous Transfer Mode
(When both Addresses are Changed),
16/8-bit Data ...................................... 377
Transfer Termination in Continuous Transfer Mode
(When Either Address is Fixed),16/8-bit Data
.......................................................... 376
Transfer Termination Operation (When both
Addresses are Changed)....................... 379
Transfer Termination Operation (When Either
Address is Fixed) ................................ 378
Transfer-Acceptance Signal
Transfer-Acceptance Signal Output ................... 369
Transfer-End Signal
Transfer-End Signal Output .............................. 369
Trap
Coprocessor Absence Trap.................................. 66
Coprocessor Error Trap ...................................... 66
Operation for Step Trace Trap ............................. 65
UDCR
Up/Down Count Register 0/1 (UDCR0,UDCR1)
..........................................................178
Writing Data to the Up/Down Count Register
(UDCR0,UDCR1) ...............................187
Undefined Instruction
Operation for an Undefined Instruction Exception
............................................................65
Underflow
Underflow Operation ........................................197
Up/Down Count Register
Up/Down Count Register 0/1 (UDCR0,UDCR1)
..........................................................178
Writing Data to the Up/Down Count Register
(UDCR0,UDCR1) ...............................187
Up/Down Counters/Timers
Block Diagram of the 8/16-bit Up/Down Counters/
Timers ................................................168
Characteristics of the 8/16-bit Up/Down Counters/
Timers ................................................166
List of Registers of the 8/16-bit Up/Down Counters/
Timers ................................................170
Up/Down Counting Mode
Up/Down Counting Mode .................................180
User Interrupt
User Interrupt Operation......................................63
User Stack Pointer
User Stack Pointer (USP) ....................................46
USP
User Stack Pointer (USP) ....................................46
U
Wait Cycle
Automatic Wait Cycle Timing Chart ..................145
Timing Chart of External Wait Cycle .................146
Wait Cycle .......................................................135
Watchdog Control Block
Block Diagram of the Watchdog Control Block
............................................................82
Watchdog Cycle Control Register
Reset Source Register (RSRR) and Watchdog Cycle
Control Register (WTCR).......................73
Watchdog Reset Generation Delay Register
Watchdog Reset Generation Delay Register (WPR)
............................................................79
Watchdog Timer
Activating the Watchdog Timer ...........................82
UART
Notes on Using the UART ................................ 347
UART Baud-rate Selection ............................... 328
UART Block Diagram...................................... 308
UART Functions.............................................. 306
UART Interrupts.............................................. 324
UART Operations ............................................ 336
UART Pin Block Diagram ................................ 312
UART Pins...................................................... 310
UART Registers .............................................. 313
UART-related Interrupts ................................... 325
UART Baud-Rate Selection Circuit
UART Baud-Rate Selection Circuit ................... 329
V
Variables
Allocation of Variables Having Initial Values......429
Vector Table
EIT Vector Table................................................59
W
467
INDEX
Watchdog Timer Function................................... 24
Word Access
Word Access.................................................... 130
WPR
Watchdog Reset Generation Delay Register (WPR)
............................................................ 79
Write Cycle
Basic Write Cycle Timing Chart ........................ 138
Timing Chart for Mixed Read/Write Cycles........ 144
Write Cycle Timing in Each Mode..................... 142
Writing
Writing Data to the Up/Down Count Register
(UDCR0,UDCR1) ............................... 187
WTCR
Reset Source Register (RSRR) and Watchdog Cycle
Control Register (WTCR) ...................... 73
468
CM71-10116-2E
FUJITSU SEMICONDUCTOR
FR30
32-BIT MICROCONTROLLER
MB91151A Series
HARDWARE MANUAL
August 2006 the second edition
Published
FUJITSU LIMITED
Edited
Business Promotion Dept.
Electronic Devices
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