A8591 Datasheet

A8591
Wide Input Voltage, 2 A Buck
Regulator Family with Low-IQ Mode
FEATURES AND BENEFITS
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Automotive AEC-Q100 qualified
Withstands surge input to 40 VIN for load dump
Operates down to 3.4 VIN (typ), 3.6 VIN (max) for idle stop
Utilizes pulse-frequency modulation (PFM) for low-IQ mode
10 μA Sleep mode (automatic PWM / Low-IQ PFM
mode selection)
Fixed output voltage options: 3.3 or 5 V with ±1%
accuracy
Delivers up to 2 A of output current
Integrated 110 mΩ high-side MOSFET
Adjustable switching frequency from 300 kHz to 2.4 MHz
EMI reduction features:
□□ Frequency dithering
□□ Controlled switching node
External synchronization capability
Maximum duty cycle for low dropout
Active low NPOR output with 7.5 ms delay
Pre-bias startup capable: VOUT increases monotonically,
will not cause a reset
Continued on the next page…
DESCRIPTION
The A8591 is designed to provide the power supply requirements
of next generation car audio and infotainment systems.
The A8591 provides all the control and protection circuitry
to produce a high-current regulator with ±1% output voltage
accuracy.
The A8591 employs current-mode control to provide simple
compensation, excellent stability, and fast transient response.
The A8591 employs pulse-frequency modulation (PFM) to
draw less than 33 µA from 12 VIN while supplying 5 V/40 µA
(A8591, 5 VOUT), or less than 24 μA from 12 VIN while
supplying 3.3 V/40 μA (A8591-1, 3.3 VOUT). When operational,
the A8591 operates down to at least 3.6 VIN (VIN falling). The
Sleep feature allows for very low standby current.
Features of the A8591 include a programmable PWM
switching frequency. The regulator switching frequency can
be synchronized to an external clock. The A8591 has external
compensation to optimize stability and transient response for
a wide range of external components and applications. The
A8591 has a fixed soft-start time of 5 ms.
Continued on the next page…
PACKAGE:
10-Pin, 3 × 3 mm Wettable Flank DFN
with Exposed Thermal Pad (suffix EJ)
APPLICATIONS:
• Automotive:
□□ Instrument clusters
□□ Audio systems
□□ Navigation
□□ HVAC
• Home audio
• Network and telecom
• Industrial
Not to scale
VIN
LO
1
CIN
2
8
VOUT
9
VIN
SW
C BOOT
47 nF
A8591
VIN
D1
2 A/40 V
CO
10
BOOT
GND
5
VOUT
3
EN/SLEEP
SYNC
4
7
RFSET
R PU
FSET /SYNC PWM
6
NPOR
NPOR
COMP
CP
RZ
See Table 2 for recommended component values
CZ
Typical Application Diagram
A8591-DS
Wide Input Voltage, 2 A Buck
Regulator Family with Low-IQ Mode
A8591
FEATURES AND BENEFITS (CONTINUED)
DESCRIPTION (CONTINUED)
•
•
•
•
Extensive protection features of the A8591 include pulse-by-pulse
current limit, hiccup mode short-circuit protection, open/short
asynchronous diode protection, BOOT open/short voltage protection,
VIN undervoltage lockout, and thermal shutdown.
External compensation for maximum flexibility
Stable with ceramic or electrolytic output capacitors
Internally fixed soft-start time of 5 ms
Pulse-by-pulse current limit, hiccup mode short-circuit, and
thermal protections
• Pin open/short and component fault tolerant
• –40°C to 150°C operating junction temperature range
• Thermally enhanced DFN-10 surface-mount package
Selection Guide
Part Number
A8591KEJTR-J
A8591KEJTR-J-1
The A8591 is supplied in a 10-pin wettable flank DFN package
(suffix EJ) with exposed power pad. It is lead (Pb) free, with 100%
matte-tin leadframe plating.
Packing*
Output Voltage Option
1500 pieces per 7-in. reel
5 V compatible
1500 pieces per 7-in. reel
3.3 V compatible
*Contact Allegro™ for additional packing options
Table of Contents
Specifications
Absolute Maximum Ratings
Thermal Characteristics
Functional Block Diagram
Pinout Diagram and Terminal List Table
Electrical Characteristics
Characteristic Performance
Dropout Operation – Typical and
Worst-Cast Operation
Functional Description
3
3
3
4
5
6
10
12
13
Overview
13
Reference Voltage
13
PWM Switching Frequency
13
EN/SLEEP Input
13
PWM Synchronization
14
Transconductance Error Amplifier
14
Slope Compensation
14
Current-Sense Amplifier
14
Power MOSFETs
14
BOOT Regulator
14
Pulse-Width Modulation (PWM) Mode
15
Low-IQ Pulse-Frequency Modulation (PFM) Mode 15
Soft-Start (Startup) and Inrush Current Control
16
Pre-Biased Startup
17
Active-Low Power-On Reset (NPOR) Output
17
Protection Features
17
Undervoltage Lockout (UVLO)
17
Pulse-by-Pulse Overcurrent Protection (OCP) 17
Overcurrent Protection (OCP) and Hiccup
18
Mode
BOOT Capacitor Protection
18
Asynchronous Diode Protection
18
Overvoltage Protection (OVP)
19
Pin-to-Ground and Pin-to-Pin Short Protections 19
Thermal Shutdown (TSD)
19
Design and Component Selection
21
21
21
22
23
24
25
25
25
A Generalized Tuning Procedure
27
Power Dissipation and Thermal Calculations 29
PCB Component Placement and Routing
30
Package Outline Drawing
31
PWM Switching Frequency (RFSET)
Output Inductor (LO )
Output Capacitors
Low-IQ PFM Output Voltage Ripple Calculation
Input Capacitors
Asynchronous Diode (D1)
Bootstrap Capacitor
Compensation Components (RZ, CZ , and CP)
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
2
Wide Input Voltage, 2 A Buck
Regulator Family with Low-IQ Mode
A8591
SPECIFICATIONS
Absolute Maximum Ratings*
Characteristic
Input Voltage (VIN pins)
Switching Node Voltage (SW pin)
BOOT Pin Voltage
VOUT Pin Voltage
EN/SLEEP Pin Voltage
Symbol
Notes
VIN
VSW
VBOOT
VOUT
Maximum Junction Temperature
Unit
V
–0.3 to VIN + 0.3
V
–1.0 to VIN + 3
V
Continuous
VSW – 0.3 to
VSW + 5.5
V
BOOT pin overvoltage fault condition
VSW – 0.3 to
VSW + 7
V
–0.3 to 5.5
V
Continuous; rating is a function of temperature
t < 50 ns
Continuous
VOUT pin overvoltage fault condition
–0.3 to 7
V
–0.3 to VIN + 0.3
V
–0.3 to 5.5
V
TJ(max)
150
ºC
Tstg
–55 to 150
ºC
VEN/SLEEP
All other pins
Storage Temperature
Rating
–0.3 to 40
*Operation at levels beyond the ratings listed in this table may cause permanent damage to the device. The Absolute Maximum Ratings are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the Electrical Characteristics table is not implied. Exposure to Absolute Maximumrated conditions for extended periods may affect device reliability.
Thermal Characteristics: May require derating at maximum conditions; see Power Dissipation and Thermal Calculations section
Characteristic
Package Thermal Resistance
Symbol
RθJA
Test Conditions*
On 4-layer PCB based on JEDEC standard
Value
Unit
45
ºC/W
*Additional thermal information available on the Allegro website.
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
3
Wide Input Voltage, 2 A Buck
Regulator Family with Low-IQ Mode
A8591
VIN
VOUT
VREG
LDO
EN/
SLEEP
DELAY
–
2.9 V
224 ms↓
Digital
REGOK
+
IRAM P
BOOT
FAULT
BOOT
+
–
ISENSE
GCSA
blankOn
minOff
FB < 0.4 V
timer hold off
FB < 0.2 V
F
F/2
F/4
+
BOOT
OFF
400 mV
FSET/
SYNC PWM
1.22 V
1.16 V
2 V, 4.1 V
1.2 V
OC
250 mA
EN
B OOT
RE G
Q
F > 200 kHz
–
B OOT
OFF
UVLO
+
BG
LDO OFF
VOUT ↑>3.1 V
REGOK
openBIAS
3.8 V
3.4 V
BOOT REG .
5V
–
+
VIN
S
Q
R
Q
TG
Q
Current
Comp
SW
VREG
PFM
Controller
BOOT
> 4.1 V
PFMready
BG
DIODEOK
COMPLO
FBHI
Calibration
3.5A
CLAMP
ERROR
AMP
5 ms
OCL
800 mV
VOUT
VOUT Z
Check
COMP
PULL DOWN
P FMready
FB
FB > 880 mV
OCL
DIODEOK
BOOT FAULT
UVLO
REGOK
voutOpen
BOOT OFF
FAULT
LOGIC
800 mA
CLAMP
COMPLO
openBIAS
PULL DOWN
(See Fault
Table )
TSD
FB > 880 mV
1 kΩ
NPOR
120 ↑
DELAY
7.5 ms↓
FB < 740 mV
Functional Block Diagram
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
4
Wide Input Voltage, 2 A Buck
Regulator Family with Low-IQ Mode
A8591
PINOUT DIAGRAM AND TERMINAL LIST TABLE
VIN
1
10
VIN
2
9
SW
PAD
BOOT
EN/SLEEP
3
8
GND
FSET/SYNCPWM
4
7
COMP
VOUT
5
6
NPOR
EJ Package, 10-Pin 3 × 3 mm DFN Pinouts
Terminal List Table
Number
Name
Function
Power input for the control circuits and the drain of the internal high-side N-channel MOSFET. Connect this pin to
a power supply of 4 to 35 V. A high-quality, high-frequency ceramic capacitor should be placed and grounded very
close to this pin.
1, 2
VIN
3
EN/SLEEP
4
FSET/SYNCPWM
5
VOUT
Connect this pin to the output of the regulator. This pin supplies internal circuitry when its voltage level is high
enough. Also, through an on-chip voltage divider, this pin connects to the negative feedback input of the error
amplifier. Keep the VOUT pin quiet and Kelvin connect.
6
NPOR
Active-low, power-on reset output signal. This pin is an open-drain output that transitions from low to high
impedance after the output has maintained regulation for tdPOR .
7
COMP
Output of the error amplifier, and compensation node for the current-mode control loop. Connect a series RC
network from this pin to GND for loop compensation. See the Design and Component Selection section of this
datasheet for further details.
8
GND
9
SW
The source for the internal high-side N-channel MOSFET. The external freewheeling diode (D1) and output inductor
(LO) should be connected to this pin. Both D1 and LO should be placed close to this pin and connected with
relatively wide traces.
10
BOOT
High-side gate drive boost input. This pin supplies the drive for the high-side N-channel MOSFET. Connect a 47 nF
ceramic capacitor from BOOT to SW.
–
PAD
This pin must be set high to enable the device. If this pin is set low, the device will enter a very low current
shutdown or sleep state (VOUT = 0 V). If the application does not require a sleep mode, then this pin can be tied
directly to VIN. Do not float this pin.
Frequency setting and PWM synchronization pin. A resistor, RFSET , from this pin to GND sets the PWM switching
frequency. See Figure 11 and/or Equation 1 to determine the value of RFSET. Applying a clock signal to this pin
forces PWM mode and synchronizes the PWM switching frequency.
Ground pin.
Exposed pad of the package providing enhanced thermal dissipation. This pad must be connected to the ground
plane(s) of the PCB with at least 6 vias, directly in the pad.
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
5
Wide Input Voltage, 2 A Buck
Regulator Family with Low-IQ Mode
A8591
ELECTRICAL CHARACTERISTICS1: Valid at 4 V ≤ VIN ≤ 35 V, −40°C ≤ TA = TJ ≤ 150ºC, unless otherwise specified
Characteristic
Symbol
Test Conditions
Min.
Typ.
Max.
Unit
4
−
35
V
Input Voltage
Input Voltage Range2
VIN
VIN Undervoltage Lockout Start
Threshold
VUVLO(ON)
VIN rising
3.6
3.8
4
V
VIN Undervoltage Lockout Stop
Threshold
VUVLO(OFF) VIN falling
3.2
3.4
3.6
V
VIN Undervoltage Hysteresis
VUVLO(HYS)
−
400
−
mV
Input Supply Current
Input Supply Current (Not in PFM)
IIN
IOUT = 0 mA
A8591,
VIN = 12 V,
VOUT = 5 V
Input Supply Current (Low-IQ PFM)3,4
ILO_IQ
A8591-1,
VIN = 12 V,
VOUT = 3.3 V
Input Supply Current (Sleep Mode)
IIN(SLEEP)
−
2.5
3.5
mA
IOUT = No Load, TA = 25ºC
−
10
14
µA
IOUT = No Load, TA = 65ºC
−
15
−
µA
IOUT = 40 µA, TA = 25ºC
−
28
33
µA
IOUT = 40 µA, TA = 65ºC
−
33
−
µA
IOUT = No Load, TA = 25ºC
−
7
10
µA
µA
IOUT = No Load, TA = 65ºC
−
12
−
IOUT = 40 µA, TA = 25ºC
−
20
24
µA
IOUT = 40 µA, TA = 65ºC
−
25
−
µA
VEN/SLEEP = 0 V, TJ ≤ 85°C, VIN = 16 V
−
5
15
µA
VEN/SLEEP = 0 V, TJ ≤ 85°C, VIN = 35 V
−
7
25
µA
0ºC < TJ < 85ºC, VOUT =
4 × VCOMP
4.95
5
5.05
V
–40ºC < TJ < 150ºC, VOUT =
4 × VCOMP
4.925
5
5.075
V
0ºC < TJ < 85ºC, VOUT =
2 × VCOMP
3.267
3.3
3.333
V
–40ºC < TJ < 150ºC, VOUT =
2 × VCOMP
3.25
3.3
3.35
V
Voltage Regulation
EVOUT
(5.0V)
A8591
Output Voltage Accuracy4
EVOUT
(3.3V)
Low IQ Ripple3,4
Low IQ Peak Current Threshold
Output Dropout Voltage4
VPP(LO_IQ)
A8591-1
8 V < VIN < 12 V
−
25
65
mVPP
640
800
930
mAPEAK
TA = 85ºC, DCRLO ≤ 75 mΩ, VIN = 4 V,
IOUT = 1 A, fSW = 425 kHz
3.27
3.295
–
V
TA = 85ºC, DCRLO ≤ 75 mΩ, VIN = 5.75 V,
IOUT = 1 A, fSW = 425 kHz
4.94
5
–
V
TA = 85ºC, DCRLO ≤ 50 mΩ, VIN = 4.25 V,
IOUT = 1 A, fSW = 2 MHz
3.25
3.3
–
V
TA = 85ºC, DCRLO ≤ 50 mΩ, VIN = 6 V,
IOUT = 1 A, fSW = 2 MHz
4.89
5
–
V
IPEAK(LO_IQ)
VOUT(SAT)
Continued on the next page…
1 Negative
current is defined as coming out of the node or pin, positive current is defined as going into the node or pin.
limited depending on input voltage, output voltage, duty cycle, regulator load currents, PCB layout, and airflow.
3 Configured as shown in Typical Application Diagram.
4 Ensured by design and characterization, not production tested.
2 Thermally
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
6
Wide Input Voltage, 2 A Buck
Regulator Family with Low-IQ Mode
A8591
ELECTRICAL CHARACTERISTICS1 (continued): Valid at 4 V ≤ VIN ≤ 35 V, −40°C ≤ TA = TJ ≤ 150ºC, unless otherwise specified
Characteristic
Symbol
Test Conditions
Min.
Typ.
Max.
Unit
Error Amplifier
Open-Loop Voltage Gain
Transconductance with On-Chip
Resistor Divider Included
AVOL
gm(5V)
gm(3.3V)
Output Current
IEA
VCOMP = 1.2 V
A8591
A8591-1
2.5 V < VOUT
−
65
−
dB
88
120
152
μA/V
0 V < VOUT < 2.5 V
46.4
64
81.6
μA/V
1.65 V < VOUT
133.3
181.8
230.3
μA/V
0 V < VOUT < 1.65 V
70.3
97
123.6
μA/V
VCOMP = 1.2 V
−
±75
−
μA
TJ = 25ºC, VBOOT – VSW = 4.5 V, IDS = 1 A
−
110
–
mΩ
TJ < 85ºC, VEN/SLEEP ≤ 0.8 V, VSW = 0 V,
VIN = 16 V
−
−
10
µA
VIN = 12 V, IOUT = 1 A
−
0.72
−
V/ns
−
−
10
Ω
1.8
2
2.2
V
−
400
−
mV
RFSET = 86.6 kΩ
270
300
330
kHz
RFSET = 61.9 kΩ
373
415
457
kHz
RFSET = 9.31 kΩ
Internal MOSFET Parameters2
High-Side MOSFET On-Resistance
High-Side MOSFET Leakage Current4
RDS(on)HS
ILKGHS
SW Node Rising/Falling Slew Rate4
SR
Low-Side MOSFET On-Resistance
RDS(on)LS
TJ = 25ºC, VIN ≥ 6 V, IDS = 0.1 A
BOOT Voltage Enable Threshold
VBOOT(TH)
VBOOT rising
BOOT Voltage Enable Hysteresis
VBOOT(HYS)
BOOT Regulator
Oscillator and PWM Timing
PWM Switching Frequency
fOSC
1.8
2
2.2
MHz
PWM Frequency Dithering
fDITHER
No dithering with synchronization
−
±7.5
−
%
Minimum Controllable On-Time
tON(MIN)
VIN = 12 V, IOUT = 1 A
−
85
125
ns
Minimum Switch Off-Time
tOFF(MIN)
VIN = 12 V, IOUT = 1 A
−
85
125
ns
0.375
−
2.4
MHz
FSET/SYNCPWM Synchronization Timing
Synchronization Frequency Range
fSW_MULT
Synchronization Input Duty Cycle
DSYNC
−
−
80
%
Synchronization Input Pulse Width
twSYNC
200
−
−
ns
Synchronization Input Rise Time4
trSYNC
−
10
15
ns
Synchronization Input Fall Time4
tfSYNC
−
10
15
ns
Synchronization Rising Threshold4
VSYNC(LO)
VFSET/SYNCPWM rising
−
−
1.5
V
Threshold4
VSYNC(HI)
VFSET/SYNCPWM falling
0.9
−
−
V
Synchronization Falling
Continued on the next page…
1 Negative
current is defined as coming out of the node or pin, positive current is defined as going into the node or pin.
limited depending on input voltage, output voltage, duty cycle, regulator load currents, PCB layout, and airflow.
3 Configured as shown in Typical Application Diagram.
4 Ensured by design and characterization, not production tested.
2 Thermally
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
7
Wide Input Voltage, 2 A Buck
Regulator Family with Low-IQ Mode
A8591
ELECTRICAL CHARACTERISTICS1 (continued): Valid at 4 V ≤ VIN ≤ 35 V, −40°C ≤ TA = TJ ≤ 150ºC, unless otherwise specified
Characteristic
Symbol
Test Conditions
Min.
Typ.
Max.
Unit
3
3.5
4
A
2
2.6
3
A
−
3
−
A/V
−
0.35
−
A/μs
Current Control Loop
PWM Pulse-by-Pulse Limit
COMP to SW Current Gain
ILIM(TONMIN) tON = tON(MIN)PWM, 4 V ≤ VIN ≤ 16 V
ILIM(TONMAX)
tON = (1 / fSW) – tOFF(MIN)PWM , no PWM
synchronization
gmPOWER
During synchronization
Slope Compensation
SE
RFSET = 86.6 kΩ
0.18
0.25
0.34
A/μs
RFSET = 61.9 kΩ
0.25
0.34
0.45
A/μs
RFSET = 9.31 kΩ
1.6
2
2.4
A/μs
Soft-Start
Soft-Start Ramp Time
tSS
fSS(5.0V)
A8591
Soft-Start Switching Frequency
fSS(3.3V)
A8591-1
2.5
5
7.5
ms
0 V < VOUT < 1.25 V
−
fOSC / 4
−
−
1.25 V < VOUT < 2.5 V
−
fOSC / 2
−
−
2.5 V < VOUT
−
fOSC
−
−
0 V < VOUT < 0.825 V
−
fOSC / 4
−
−
0.825 V < VOUT < 1.65 V
−
fOSC / 2
−
−
1.65 V < VOUT
−
fOSC
−
−
Hiccup Mode
Hiccup Off-Time
HICOFF
All hiccup faults such as VOUT shorted to GND
−
20
−
ms
Hiccup Overcurrent Protection (OCP)
Count
OCPLIM
t > tSS , OCP pulses
−
120
−
counts
Hiccup BOOT Shorted Count
BOOTUV
−
64
−
counts
Hiccup BOOT Open Count
BOOTOV
−
7
−
counts
155
170
−
ºC
−
20
−
ºC
Thermal Protection
Thermal Shutdown Threshold (Rising)
Thermal Shutdown Hysteresis
TSDth
PWM stops immediately, COMP is pulled low,
and soft-start is reset
TSDHYS
Continued on the next page…
1 Negative
current is defined as coming out of the node or pin, positive current is defined as going into the node or pin.
limited depending on input voltage, output voltage, duty cycle, regulator load currents, PCB layout, and airflow.
as shown in Typical Application Diagram.
4 Ensured by design and characterization, not production tested.
2 Thermally
3 Configured
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
8
Wide Input Voltage, 2 A Buck
Regulator Family with Low-IQ Mode
A8591
ELECTRICAL CHARACTERISTICS1 (continued): Valid at 4 V ≤ VIN ≤ 35 V, −40°C ≤ TA = TJ ≤ 150ºC, unless otherwise specified
Characteristic
Symbol
Test Conditions
Min.
Typ.
Max.
Unit
5.37
5.5
5.75
V
−
–60
−
mV
4.45
4.62
4.75
V
−
60
−
mV
3.54
3.63
3.75
V
−
–40
−
mV
2.93
3.05
3.14
V
VOUT rising, relative to VNPORUV
−
40
−
mV
VOUT falling beyond VNPOROV
−
120
−
counts
Power-On Reset (NPOR) Output
NPOR Overvoltage Threshold, 5 V
NPOR Overvoltage Hysteresis, 5 V
NPOR Undervoltage Threshold, 5 V
NPOR Undervoltage Hysteresis, 5 V
NPOR Overvoltage Threshold, 3.3 V
NPOR Overvoltage Hysteresis, 3.3 V
VNPOROV
(5V)
VNPOROV
(HYS)(5V)
VNPORUV(5V)
VNPORUV
(HYS)(5V)
VOUT rising
VOUT falling, relative to VNPOROV
VOUT falling
VOUT rising, relative to VNPORUV
VNPOROV(3.3V) VOUT rising
VNPOROV
(HYS)(3.3V)
VOUT falling, relative to VNPOROV
NPOR Undervoltage Threshold, 3.3 V VNPORUV(3.3V) VOUT falling
NPOR Undervoltage Hysteresis, 3.3 V
NPOR Overvoltage Delay
NPOR Delay to Rising Edge
VNPORUV
(HYS)(3.3V)
tdPOV_POR
VOUT rising only
5
7.5
10
ms
NPOR Low Output Voltage
VPOROL
INPOR = 4 mA
−
200
400
mV
NPOR Leakage
ILKGPOR
VNPOR = 5.5 V
−
−
1.2
µA
tdPOR
EN/SLEEP Pin Input Thresholds
EN/SLEEP Threshold (High)
VSLEEPVIH
VEN/SLEEP rising
−
1.3
2.1
V
EN/SLEEP Threshold (Low)
VSLEEPVIL
VEN/SLEEP falling
0.5
1.2
−
V
VEN/SLEEP transitioning low
115
224
400
µs
−
500
−
nA
EN/SLEEP Delay
EN/SLEEP Input Bias Current
tdSLEEP
IBIASSLEEP VEN/SLEEP = 5 V
1 Negative
current is defined as coming out of the node or pin, positive current is defined as going into the node or pin.
limited depending on input voltage, output voltage, duty cycle, regulator load currents, PCB layout, and airflow.
as shown in Typical Application Diagram.
4 Ensured by design and characterization, not production tested.
2 Thermally
3 Configured
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
9
Wide Input Voltage, 2 A Buck
Regulator Family with Low-IQ Mode
A8591
CHARACTERISTIC PERFORMANCE
Output Voltage versus Temperature
Switching Frequency versus Temperature
2200
Oscillator Frequency, fOSC (kHz)
Output Voltage, VOUT (V)
5.5
5.0
VOUT = 5 V
4.5
4.0
3.5
VOUT = 3.3 V
3.0
2.5
2.0
-50
-25
0
25
50
75
100
125
150
175
2000
1800
fOSC = 300 kHz
1600
fOSC = 415 kHz
1400
fOSC = 2000 kHz
1200
1000
800
600
400
200
-50
-25
0
Temperature (°C)
VIN UVLO Start and Stop Thresholds
versus Temperature
75
100
125
150
175
3.55
3.50
3.8
VIN Undervoltage Lockout Start Threshold, VUVLO(ON)
3.45
3.7
ILIM(TONMIN) (A)
Input Voltage, VIN (V)
50
Pulse-by-Pulse Current Limit at tON(MIN)
versus Temperature
3.9
3.6
3.5
VIN Undervoltage Lockout Stop Threshold, VUVLO(OFF)
3.4
3.3
-50
-25
0
25
50
75
100
125
3.40
3.35
3.30
150
3.25
175
-50
-25
0
Error Amplifier Transconductance
versus Temperature
50
75
100
125
150
175
Error Amplifier Transconductance
versus Temperature
140
Transconductance, gm (µA/V)
200
120
VIN > 2.5 V
100
80
VIN < 2.5 V
60
40
VOUT = 5.0 V
20
0
25
Temperature (°C)
Temperature (°C)
Transconductance, gm (µA/V)
25
Temperature (°C)
-50
-25
0
25
50
75
100
Temperature (°C)
125
150
175
180
160
VIN > 1.65 V
140
120
VIN < 1.65 V
100
80
60
VOUT = 3.3 V
40
20
0
-50
-25
0
25
50
75
100
125
150
175
Temperature (°C)
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
10
PWM/PFM Pin Input Volt
PWM/PFM Pin Input Volt
VIH
1.80
1.75
A8591
1.60
-50
-25
VIL
0
25
50
1.24
1.22
Wide Input Voltage, 2 A Buck
Regulator Family with Low-IQ Mode
1.70
1.65
VIH
1.26
75
100
125
150
1.20
1.18
VIL
1.16
1.14
175
-50
-25
0
25
Temperature (°C)
NPOR Overvoltage and Undervoltage Thresholds
versus Temperature
3.6
NPOR Pin Voltage (V)
NPOR Pin Voltage (V)
100
125
150
175
3.8
5.6
VNPOROV(5.0V)
5.4
5.2
5.0
4.8
VNPORUV(5.0V)
4.6
4.4
VOUT = 5 V
4.2
-50
-25
VNPOROV(3.3V)
3.4
3.2
3.0
VNPORUV(3.3V)
2.8
2.6
2.4
VOUT = 3.3 V
2.2
0
25
50
75
100
125
150
2.0
175
-50
-25
0
25
Temperature (°C)
IOUT = 2 mA
200
150
100
50
0
-50
-25
0
25
50
75
Temperature (°C)
100
125
150
175
NPOR Delay to Rising Edge tdPOR (ms)
300
250
50
75
100
125
150
175
Temperature (°C)
NPOR Low Output Voltage versus Temperature
NPOR Pin Output Voltage (mV)
75
NPOR Overvoltage and Undervoltage Thresholds
versus Temperature
5.8
4.0
50
Temperature (°C)
NPOR Time Delay versus Temperature
8.20
8.15
8.10
8.05
8.00
7.95
7.90
7.85
7.80
7.75
-50
-25
0
25
50
75
100
125
150
175
Temperature (°C)
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
11
Wide Input Voltage, 2 A Buck
Regulator Family with Low-IQ Mode
A8591
DROPOUT OPERATION – TYPICAL AND WORST-CASE OPERATION
Typical Output Voltage versus Input Voltage at High Ambient
at 100%, 66%, and 33% Load
8
Output Voltage, VOUT (V)
7
6
5
IOUT = 0.67 A
4
IOUT = 2 A
3
IOUT = 1.33 A
2
1
4
5
6
7
Input Voltage, VIN (V)
8
9
10
Worst-Case Output Voltage versus Input Voltage at High Ambient
at 100%, 66%, and 33% Load
8
Output Voltage, VOUT (V)
7
6
5
IOUT = 0.67 A
4
IOUT = 2 A
IOUT = 1.33 A
3
2
1
4
5
6
7
8
9
10
Input Voltage, VIN (V)
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
12
Wide Input Voltage, 2 A Buck
Regulator Family with Low-IQ Mode
A8591
FUNCTIONAL DESCRIPTION
The A8591 family are current-mode buck regulators that incorporate all the control and protection circuitry necessary to provide
the power supply requirements of car audio and infotainment
systems.
The A8591 family consists of two parts:
• A8591 (5 V output voltage)
• A8591-1 (3.3 V output voltage)
The A8591 family has three modes of operation:
• Pulse-width modulation (PWM) mode, delivering up to 2 A.
• Low-IQ pulse-frequency modulation (PFM) mode, drawing
only approximately 10 µA from VIN while maintaining VOUT
(at no load). Under most conditions, Low-IQ PFM mode is
typically capable of supporting up to approximately 100 mA,
depending on applications.
Current Rating (A)
Overview
2.1
2.0
1.9
1.8
1.7
1.6
1.5
1.4
1.3
1.2
1.1
1.0
0.9
0.8
0.7
12 VIN, 5.0 VOUT, 300 kHz
12 VIN, 3.3 VOUT, 300 kHz
12 VIN, 5.0 VOUT, 2 MHz
12 VIN, 3.3 VOUT, 2 MHz
75
85
95
105
Ambient Temperature (ºC)
115
125
Figure 3: Typical Current Derating
PWM Switching Frequency
• The third mode of operation is entered when the EN/SLEEP
pin is set to 0. The device enters an ultralow-current shutdown
mode. VOUT = 0 V and the total current drawn from VIN is less
than 10 µA (typ).
The PWM switching frequency of the A8591 family is adjustable
from 300 kHz to 2.4 MHz and has an accuracy of ±10% over the
operating temperature range. The switching frequency is dithered
to help reduce EMI between –7.5% and 7.5% according to a
random sequence.
In PFM mode, the device operates with lower switching frequency to achieve higher efficiency at light load. When the load
is heavy, the device automatically transitions into PWM mode to
support a relatively higher current.
During startup, the PWM switching frequency changes from
25%, to 50%, and finally to 100% of fSW as VOUT rises from
0 V to the regulation voltage. The startup switching frequency is
described in detail in the Soft-Start section of this datasheet.
The A8591 family is designed to support up to 2 A output.
However, the exact amount of current it will supply, before possible thermal shutdown, depends heavily on duty cycle, ambient
temperature, airflow, PCB layout, and PCB construction. Figure 3
shows calculated current ratings versus ambient temperature for
VIN = 12 V and VOUT = 3.3 V, and for VIN = 12 V and VOUT =
5 V, each at 300 kHz and 2 MHz. This analysis assumes a 4-layer
PCB according to the JEDEC standard (45°C/W), no nearby heat
sources, and no airflow.
If the regulator output is shorted to ground, VFB ≈ 0 V and the
PWM frequency is 25% of fSW . In this case, the low switching
frequency allows extra off-time between SW pulses. The extra
off-time allows the inductor current to remain under control
(remaining well above 0 A) before the next SW pulse occurs.
This prevents the inductor current from ratcheting up, or rising, to
a value that could damage the device or the output inductor.
Reference Voltage
The output voltage from the device regulator is directly connected to the VOUT pin and is divided down internally to
800 mV by an internal resistor divider inside the regulator, as
shown in the Functional Block Diagram. The A8591 has a fixed
5 V output voltage; the A8591-1 has a fixed 3.3 V output voltage.
The FSET pin includes protection features that disable the
regulator when the FSET pin is shorted to GND, shorted High (to
NPOR), or when RFSET is mis-selected.
EN/SLEEP Input
The A8591 family has the EN/SLEEP logic level input pin.
To enable the device, the EN/SLEEP pin must be a logic high
(>2.1 V). The EN/SLEEP pin is rated to 40 V so this EN/SLEEP
pin may be connected directly to VIN if there is no suitable logic
signal available to wake up the regulator.
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
13
A8591
Wide Input Voltage, 2 A Buck
Regulator Family with Low-IQ Mode
When EN/SLEEP transitions low, the device waits approximately
224 µs before shutting down. This delay provides plenty of
filtering to prevent the device from prematurely entering Sleep
mode because of any small glitches that might couple onto the
PCB trace or EN/SLEEP pin.
PWM Synchronization
If an external clock is applied to the FSET/SYNCPWM pin, the
device is forced into PWM mode and synchronizes its PWM
frequency to the external clock. Synchronization is independent
of RFSET; it only needs to satisfy the range requirement in the
Electrical Characteristics table. When synchronizing, the external
clock pulses must satisfy the pulse-width, duty cycle, and rise/fall
time requirements shown in the Electrical Characteristics table
in this datasheet. During synchronization, frequency dithering is
disabled.
The A8591 synchronizes to the SYNC input when the FSET/
SYNCPWM pin is driven above the 1.2 V threshold. Synchronization must occur within 16 µs or else a fault may be declared
causing SW to halt operation. The A8591 will transition back to
using the RFSET resistor after a rising has not crossed the 1.2 V
threshold for ~8 µs, resulting in the high-side switch remaining
off for ~8 µs and causing some VOUT droop.
Transconductance Error Amplifier
The transconductance error amplifier's primary function is to
control the regulator output voltage. The error amplifier is shown
in the Functional Block diagram. It is shown as a three-terminal
input device with two positive inputs and one negative input. An
on-chip resistor divider is included. The negative input is simply
connected to the internal resistor divider and is used to sense
the feedback voltage for regulation. The two positive inputs are
used for soft-start and steady-state regulation. The error amplifier
performs an analog OR selection between the two positive inputs.
The error amplifier regulates to either the internal soft-start voltage or the device internal reference, whichever is lower.
To stabilize the regulator, a series RC compensation network
(RZ and CZ) must be connected from the error amplifier output
(the COMP pin) to GND, as shown in the Typical Application
Diagram. In most instances, an additional relatively low-value
capacitor (CP) should be connected in parallel with the RZ-CZ
components to reduce the loop gain at very high frequencies.
However, if the CP capacitor is too large, the phase margin of the
converter can be reduced. Calculating RZ, CZ, and CP is covered
in detail in the Component Selection section of this datasheet.
If a fault occurs or the regulator is disabled, the COMP pin
is pulled to GND via approximately 1 kΩ and SW switching
is inhibited.
Slope Compensation
The A8591 family incorporates internal slope compensation (SE )
to allow PWM duty cycles above 50% for a wide range of input/
output voltages and inductor values. The slope compensation signal is added to the sum of the current-sense amplifier output and
the PWM ramp offset. As shown in the Electrical Characteristics
table, the amount of slope compensation scales with the nominal
switching frequency (fSW) set by RFSET . The amount of slope
compensation scales with the SYNC input frequency centered
around 0.35 A/µs at 425 kHz in a similar way with RFSET.
The value of the output inductor should be chosen such that SE
is between 0.5× and 1× the falling slope of the inductor current (SF).
Current-Sense Amplifier
The A8591 family incorporates a high-bandwidth current-sense
amplifier to monitor the current in the high-side MOSFET.
This current signal is used by both the PWM and PFM control
circuitry to regulate the MOSFET peak current. The current
signal is also used by the protection circuitry to prevent damage
to the device.
Power MOSFETs
The A8591 family includes a 40 V, 110 mΩ high-side N-channel
MOSFET capable of delivering at least 2 A. The device also
includes a 10 Ω, low-side MOSFET to help ensure the boot
capacitor is always charged. The typical RDS(on) increase versus
temperature is shown in Figure 4.
BOOT Regulator
The A8591 family contains a regulator to charge the boot capacitor. The voltage across the BOOT capacitor typically is 5 V. If the
boot capacitor is missing, the device detects a boot overvoltage.
Similarly, if the BOOT capacitor is shorted, the device detects a
boot undervoltage. Also, the boot regulator has a current limit to
protect itself during a short-circuit condition. The details of how
each type of boot fault is handled by the A8591 are shown in
Table 1.
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
14
Wide Input Voltage, 2 A Buck
Regulator Family with Low-IQ Mode
A8591
showing how faults are handled during PWM mode. Also, the
Protection Features section of this datasheet provides a detailed
description of each fault and Table 1 presents a summary.
1.8
1.6
Normalized RDS(on)
1.4
Low-IQ Pulse-Frequency Modulation (PFM)
Mode
1.2
1.0
0.8
0.6
0.4
0.2
0
-40
-20
0
20
40
60
80
100 120 140 160
Temperature (°C)
Figure 4: Typical MOSFET RDS(on) versus Temperature
Pulse-Width Modulation (PWM) Mode
The A8591 family utilizes fixed-frequency, peak current-mode
control to provide excellent load and line regulation, fast transient
response, and ease of compensation.
A high-speed comparator and control logic, capable of typical
pulse widths down to tON(MIN), are included in the device. The
inverting input of the PWM comparator is connected to the
output of the error amplifier. The non-inverting input is connected
to the sum of the current-sense signal, the slope compensation,
and a DC offset voltage (VPWMOFFS , nominally 400 mV).
At the beginning of each PWM cycle, the CLK signal sets the
PWM flip-flop and the high-side MOSFET is turned on. When
the summation of the DC offset, slope compensation, and currentsense signal, rises above the error amplifier voltage, the PWM
flip-flop is reset and the high-side MOSFET is turned off.
The PWM flip-flop is reset-dominant, so the error amplifier
may override the CLK signal in certain situations. For example,
at very light loads or extremely high input voltages, the error
amplifier (temporarily) reduces its output voltage below the
400 mV DC offset and the PWM flip-flop ignores one or more of
the incoming CLK pulses. The high-side MOSFET does not
turn on and the regulator skips pulses to maintain output
voltage regulation.
In PWM mode, and when SW is switching in PFM mode, all
of the device fault detection circuits are active. See Figure 1
The A8591 and A8591-1 enter Low-IQ PFM, provided that no
faults are present, the load is light, NPOR = 1, and no external
clock is applied to the FSET/SYNCPWM pin, and the EN/SLEEP
pin is high. At light loads, the PFM comparator, which is connected to the VOUT pin through the internal feedback resistor
divider (which is the internal FB point), modulates the frequency
of the SW node to regulate the output voltage with very high
efficiency.
The reference for the PFM comparator is calibrated approximately 1% above the PWM regulation point. When the voltage at
the internal FB point rises above the PFM comparator threshold
and peak inductor current falls below IPEAK(LO_IQ) minus slope
compensation, the device will enter PFM coast mode, tri-stating
the SW node and drawing extremely low current from VIN.
When voltage at the FB point falls below the PFM comparator
threshold, the device will fully power-up after approximately a
2.5 µs delay and the high-side MOSFET is repeatedly turned on,
operating at the PWM switching frequency until the voltage at
the FB pin rises above the PFM comparator threshold. VOUT will
rise at a rate determined by, and have a voltage ripple dependent
on, the input voltage, output voltage, inductor value, output
capacitance, and load.
When the COMP pin falls to a voltage corresponding to the
Low-IQ Peak Current Threshold ( IPEAK(LO_IQ) ) value, an internal
clamp prevents the COMP voltage from falling further. This
results in the output voltage rising slightly which causes the
PFM comparator to trip and the device to enter the PFM Coast
mode. Thus, when the load demands a peak inductor current that
corresponds to less than the Low-IQ Peak Current Threshold
(IPEAK(LO_IQ)) minus the impact of slope compensation at the
given duty cycle, the device operates in PFM mode. This transition point from PWM to PFM mode is defined by the input
voltage, output voltage, slope compensation, and inductor value.
Figure 5 demonstrates PFM mode operation for a light load
(5 mA). Figure 6 shows PWM and Low-IQ PFM transitions. In
PFM mode, the load steps from 0.05 A (PFM operation) to 1.05 A
(PWM operation) and then transitions back to 0.05 A PFM mode.
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
15
A8591
Wide Input Voltage, 2 A Buck
Regulator Family with Low-IQ Mode
Soft-Start (Startup) and Inrush Current Control
Inrush current is controlled by the internal embedded soft-start
function. The soft-start time of the A8591 family is fixed at 5 ms.
When the device is enabled and all faults are cleared, the internal
soft-start voltage ramps upward from 0 V. When the soft-start
voltage exceeds the equivalent VOUT voltage, the error amplifier output slews above the 400 mV pedestal, initiating PWM
switching.
When the device begins switching, the error amplifier regulates
the internal FB voltage to be the soft-start voltage. During the
active portion of soft-start, the regulator output voltage rises from
0 V to the nominal value.
Figure 5: PFM Mode at Light Load (5 mA)
VIN = 12 V, VOUT = 5 V
In Figure 7, the startup sequence shows the soft-start operation.
During startup, while VOUT voltage is below 25% (interval A
in Figure 7), the PWM switching frequency is reduced to ¼ of
fSW. This corresponds to VOUT < 1.25 V (for nominal 5 V output:
A8591) or < 0.825 V (for nominal 3.3 V output: A8591-1). While
VOUT is above 25% but below 50% (interval B), the switching
frequency is reduced to ½ of fSW, and when VOUT is above 50%
(at C), the switching frequency is fSW.
The error amplifier gain (gm) also changes. While VOUT is below
50% (at A through B), gm is reduced to gm / 2. While VOUT is
above 50% (at C), the error amplifier gain is gm .
The reduced switching frequencies and error amplifier gain are
necessary to help improve output regulation and stability when
VOUT is very low. When VOUT is very low, the PWM control
loop requires on-times near the minimum controllable on-time
and extra-low duty cycles that are not possible at the nominal
switching frequency. When the soft-start voltage reaches approximately 800 mV, the error amplifier switches over to referencing
the device-internal 800 mV reference for regulating the internal
(resistor divider) FB voltage.
If the device is disabled or a fault occurs, the internal fault latch
is set, and the soft-start voltage is discharged to ground very
quickly. When the soft-start voltage decays to approximately
200 mV, the device clears the internal fault latch.
The soft-start voltage is discharged slowly when the device is
in hiccup mode. Therefore, the soft-start not only determines
the startup time but also the time between soft-start attempts in
hiccup mode. Hiccup mode operation is discussed in more detail
in the Protections section of this datasheet.
Figure 6: Load Steps Between 0.05 A and 1.05 A
in PFM Mode
(A)
(B)
fSW/4
fSW/2
gm/2
gm/2
(C)
fSW
gm
Figure 7: Soft-Start Operation –
VOUT Ramps from Startup (VIN powered) to Nominal (5 V at 2 A, for
A8591, shown)
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
16
A8591
Wide Input Voltage, 2 A Buck
Regulator Family with Low-IQ Mode
Pre-Biased Startup
If the output of the regulator is pre-biased to some voltage, the
A8591 family modifies the normal startup routine to prevent
discharging the output capacitors. As described previously, the
error amplifier usually becomes active when the soft-start voltage
starts to ramp. If the output is pre-biased, the internal FB voltage
is at some non-zero voltage. The COMP pin remains low and SW
is tri-stated until the soft-start voltage rises above the VFB. Figure
8 shows startup when the output voltage is pre-biased to 2 V.
fSW/2
fSW
Active-Low Power-On Reset (NPOR) Output
The A8591 family has an inverted Power-On Reset output
(NPOR) with a fixed delay ( tdPOR ) before the rising edge. The
NPOR output is an open-drain output, so an external pull-up
resistor must be used, as shown in the Typical Application
Diagram. NPOR transitions high when the output voltage is
within regulation. In PWM mode, NPOR is high when the output
voltage is typically within 92.5% to 110% of the target value. The
NPOR overvoltage and undervoltage comparators incorporate a
small amount of hysteresis (VNPORUV(HYS)(xV) ), 40 mV(typ) for
3.3 V output (A8591-1) and 60 mV (typ) for 5 V output (A8591),
and filtering (5 µs, typical) to help reduce chattering.
The NPOR output is immediately pulled low if either an overvoltage or an undervoltage condition occurs, or if the device
junction temperature exceeds the Thermal Shutdown Threshold
(TSDth ). For other faults, NPOR depends on the output voltage.
Table 1 summarizes all of the A8591 family fault modes and the
effects on NPOR. When powering down, if VIN goes low before
VOUT, NPOR will pulled low when the undervoltage condition
occurs, but will only remain low while VOUT remains above ~3 V.
When the EN/SLEEP pin goes low, switching stops after 224 µs
(typ) (tdSLEEP ), and NPOR goes low (even if VOUT > VNPORUV)
and stays low until VOUT drops to about 25% of nominal value.
When VOUT falls to about 25% of its nominal value, the device
goes into Sleep mode, consuming IIN(SLEEP) on VIN, and shortly
after that, NPOR will be released (no longer pulled low). Given
this operation, the time that NPOR remains low is dependent on
the current consumption on VOUT and the output capacitance. It
is important to note that the high-side switch leakage can overwhelm the load current on VOUT, especially since the IC current
on VOUT is very low in this mode. Therefore for reliable operation in this situation, the user should select an NPOR resistor (if
connected to VOUT) with a low enough value to overwhelm any
high-side switch leakage.
Figure 8: Soft-Start Prebiased Startup –
VOUT Prebiased at 2 V, Ramps to Nominal (5 V at 2 A, for A8591,
shown)
Protection Features
The A8591 was designed to satisfy the most demanding automotive and non-automotive applications. In this section, a description of each protection feature is provided, and Table 1 summarizes the protection operation. All faults are available in both
PWM and PFM mode. In PFM mode, all faults are monitored just
before and while switching is active, but are ignored while VOUT
remains above the PFM comparator threshold and below the
NPOR OV threshold.
UNDERVOLTAGE LOCKOUT (UVLO)
An undervoltage lockout (UVLO) comparator monitors the voltage at the VIN pin and keeps the regulator disabled if the voltage
is below the stop threshold (VUVLO(OFF) ). The UVLO comparator
incorporates some hysteresis (VUVLO(HYS) ) to help reduce on-off
cycling of the regulator due to resistive or inductive drops in the
VIN path during heavy loading or during startup.
PULSE-BY-PULSE OVERCURRENT PROTECTION
(OCP)
The A8591 family monitors the current of the high-side MOSFET, and if the current exceeds the pulse-by-pulse overcurrent
threshold (ILIM), then the high-side MOSFET is turned off.
Normal PWM operation resumes on the next clock pulse from the
oscillator. The device includes leading-edge blanking (as defined
by tON(MIN) spec) to prevent false triggering of the pulse-by-pulse
current limit when the high-side MOSFET is turned on initially.
Because the slope compensation ramp is added to the inductor
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
17
Wide Input Voltage, 2 A Buck
Regulator Family with Low-IQ Mode
A8591
current, the A8591 family delivers more current at lower duty
cycles and less current at higher duty cycles. Figure 9 illustrates
the relationship between the current limit and duty cycle. As
shown, the current limit at min. and max. duty cycle remains
fixed, but the relationship vs. duty cycle is skewed with frequency due to the fixed min. off-time. Given the relationship, it is
best to use the ILIM(tonmin) and ILIM(toffmin) to calculate the current
limit at a given duty cycle.
During synchronization, the slope compensation scales in a
similar fashion as RFSET, with slightly less accuracy.
The exact current the buck regulator can support is heavily
dependent on duty cycle (VIN , VOUT , diode forward voltage Vf ),
ambient temperature, thermal resistance of the PCB, airflow,
component selection, and nearby heat sources.
4.2
4.0
3.8
3.6
ILIM (A)
3.2
3.0
2.8
2.6
Min. 415 kHz
Typ. 415 kHz
Max. 415 kHz
2.2
Min. 2 MHz
Typ. 2 MHz
2.0
1.8
Max. 2 MHz
0
If the OCP counter reaches OCPLIM counts (120), a hiccup latch
is set and the COMP pin is quickly pulled down by a relatively
low resistance (1 kΩ), and switching is halted for 20 ms to
provide time for the IC to cool down. After the hiccup off-time
expires (20 ms), the soft-start ramp starts, marking the beginning
of a new, normal soft-start cycle as described earlier.
When the soft-start voltage crosses the effective output voltage,
the error amplifier forces the voltage at the COMP pin to quickly
slew upward and PWM switching resumes. If the short-circuit
at the regulator output remains, another hiccup cycle occurs.
Hiccups repeat until the short-circuit is removed or the converter
is disabled. If the short-circuit has been removed, the device
soft-starts normally and the output voltage automatically recovers
to the target level, as shown in Figure 10.
BOOT CAPACITOR PROTECTION
The A8591 family monitors the voltage across the BOOT
capacitor to detect if the capacitor is missing or short-circuited.
If the BOOT capacitor is missing, the regulator enters hiccup
mode after 7 PWM cycles. If the BOOT capacitor is shorted, the
regulator enters hiccup mode after 120 to 64 PWM cycles.
3.4
2.4
As long as these two conditions are met, the OCP counter
remains enabled and counts pulses from the overcurrent comparator. If the COMP voltage decreases (OCL = 0), the OCP counter
is cleared.
5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90 95 100
Duty Cycle, D (%)
Figure 9: Pulse-by-Pulse Current Limit vs. Duty Cycle at
415 kHz (solid lines) and 2 MHz (dashed lines)
OVERCURRENT PROTECTION (OCP) AND HICCUP
MODE
An OCP counter and hiccup mode circuit protect the buck regulator when the output of the regulator is shorted to ground or when
the load is too high. When the soft-start ramp is active (t < tSS),
the OCP hiccup counter is disabled. Two conditions must be met
for the OCP counter to be enabled and begin counting:
• t > tSS, and
• VCOMP clamped at its maximum voltage (OCL = 1)
For a BOOT fault, hiccup mode operates virtually the same as
described previously for an output short-circuit fault (OCP), having a hiccup off-time of 20 ms, followed by a soft-start retry with
repeated attempts until the fault clears. However, OCP is the only
fault that is ignored during the soft-start ramp time ( tSS ). BOOT
faults are a non-latched condition, so the device automatically
recovers when the fault is corrected.
ASYNCHRONOUS DIODE PROTECTION
If the asynchronous diode is missing or damaged (open), the SW
pin is subject to unusually high negative voltages. This negative
voltage may cause the device to malfunction and could lead to
damage. The A8591 family includes protection circuitry to detect
when the asynchronous diode is missing. If the SW pin is below
−1.25 V typically, for more than 50 ns typically, the device enters
hiccup mode after detecting 1 missing diode fault.
Also, if the asynchronous diode is shorted, the device experiences
extremely high currents through the high-side MOSFET. If this
occurs, the device enters hiccup mode after detecting 1 shorted
diode fault.
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
18
A8591
Wide Input Voltage, 2 A Buck
Regulator Family with Low-IQ Mode
OVERVOLTAGE PROTECTION (OVP)
The A8591 family provides an always-on overvoltage protection
that monitors VOUT, to protect against VOUT rising up at light
loads due to high-side switch leakage. In this case, the high-side
switch is forced off and the low-side switch continues to operate
and can correct the OVP condition, provided only a few milliamperes of pull-down current are required. When the condition
causing the overvoltage is corrected, the regulator automatically
recovers.
During an output overvoltage condition, the device tries for up
to 120 counts ( tdPOV_POR ) to clear the overvoltage condition. If
the overvoltage condition is successfully cleared within this time
period, NPOR does not go low and the device continues to operate in PFM mode. If the overvoltage fault is not cleared during
this time, then an NPOR = 0 is declared and the device works
indefinitely to reduce the output overvoltage fault. If it is successful in clearing this fault, then there will be an approximately
7.5 ms delay ( tdPOR ) before NPOR pin returns high. Note that
the size of the regulator output capacitor may have an effect on
whether the overvoltage condition is cleared within the tdPOV_POR
time period.
PIN-TO-GROUND AND PIN-TO-PIN SHORT PROTECTIONS
The A8591 family is designed to satisfy the most demanding
automotive applications. For example, the device is carefully
designed fundamentally to withstand a short-circuit to ground at
each pin without suffering damage.
In addition, care was taken when defining the device pin-out to
optimize protection against adjacent pin-to-pin short-circuits.
For example, logic pins and high-voltage pins are separated as
much as possible. Inevitably, some low-voltage pins had to be
located adjacent to high-voltage pins, but in these instances the
low-voltage pins are designed to withstand increased voltages,
with clamps and/or series input resistance, to prevent damage to
the device.
THERMAL SHUTDOWN (TSD)
The A8591 family monitors internal junction temperature and
stops switching and pulls NPOR low if it becomes too hot. Also,
to prepare for a restart, the internal soft-start voltage (VSS) and
the voltage at the COMP pin are pulled low until VSS < VSSRST .
TSD is a non-latched fault, so the device automatically recovers
if the junction temperature decreases by approximately 20°C.
Figure 10: Hiccup Mode and Recovery
(to 5 V at 0.5 A, for A8591, shown)
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
19
Wide Input Voltage, 2 A Buck
Regulator Family with Low-IQ Mode
A8591
Table 1: Summary of A8591 Family Fault Modes and Operation
During Fault Counting, Before Hiccup Mode
Fault Mode
Internal
Soft-Start
VCOMP
High-Side
Switch
Low-Side
Switch
Boot
Charging
Latched
Fault
Reset
Condition
Output
shorted to
ground
Hiccup, after
120 OCL
faults
Clamped for
ILIM , then
pulled low for
Hiccup
fOSC / 4 due to
VOUT < 25%,
responds to
VCOMP
Can be
activated if
BOOT voltage
is too low
Not affected
Depends on
VOUT
No
Automatic,
remove the
short
Output
overcurrent,
VOUT > 50%
Hiccup, after
120 OCL
faults
Clamped for
ILIM , then
pulled low for
Hiccup
fOSC,
responds to
VCOMP
Can be
activated if
BOOT voltage
is too low
Not affected
Depends on
VOUT
No
Automatic,
decrease load
current
VOUT pin
open
Pulled low
after 32 cycles
Pulled low
after 32 cycles
Forced off by
COMP low
Can be
activated if
BOOT voltage
is to low
Not affected
Stays low
No
Automatic,
VOUT pin
reconnected
Boot capacitor
missing
Hiccup, after 7
Boot OV faults
Not affected
but pulled low
for Hiccup
Forced off
when Boot OV
fault occurs
Forced off
when Boot OV
fault occurs
Off after Boot
fault occurs
Depends on
VOUT
No
Automatic,
replace
capacitor
Boot capacitor
shorted
Hiccup, after
64 Boot UV
faults
Not affected
but pulled low
for Hiccup
Forced off
when Boot UV
fault occurs
Forced off
only during
Hiccup
Off only during
Hiccup
Depends on
VOUT
No
Automatic,
unshort
capacitor
Asynchronous
diode missing
Hiccup after 1
fault
Not affected
but pulled low
for Hiccup
Forced off
after 1 fault
Can be
activated if
BOOT voltage
is too low
Not affected
Depends on
VOUT
No
Automatic,
install diode
Asynchronous
diode (or SW)
hard short-toground
Hiccup after 1
fault
Clamped for
ILIM , then
pulled low for
Hiccup
Forced off
after 1 fault
Can be
activated if
BOOT voltage
is too low
Not affected
Depends on
VOUT
No
Automatic,
remove short
Asynchronous
diode (or SW)
soft short-toground
Hiccup, after
120 OCL
faults
Clamped for
ILIM , then
pulled low for
Hiccup
Active,
responds to
VCOMP
Can be
activated if
BOOT voltage
is too low
Not affected
Depends on
VOUT
No
Automatic,
remove short
Not affected
Transitions
low via loop
response
Forced off
Active during
tOFF(MIN)
Off when VOUT
is too high
Pulled low
when VOUT is
too high for
120 counts
No
Automatic,
VOUT returns
to normal
range
Output
undervoltage
Not affected
Transitions
high via loop
response
Active,
responds to
VCOMP
Can be
activated if
BOOT voltage
is too low
Not affected
Pulled low
when VOUT is
too low
No
Automatic,
VOUT returns
to normal
range
FSET shorted
to GND or
above 1 V
Pulled Low
Pulled Low
Forced Off
Forced Off
Forced Off
Depends on
VOUT
No
Auto
Thermal
shutdown
(TSD)
Pulled low
until
VSS < VSSRST
and TSD = 0
Pulled low
until
VSS < VSSRST
and TSD = 0
Forced Off
Disabled
Off
Pulled Low
No
Auto, part
cools down
Output
overvoltage,
(VOUT >
3.6 V/5.5 V)
NPOR
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
20
Wide Input Voltage, 2 A Buck
Regulator Family with Low-IQ Mode
A8591
DESIGN AND COMPONENT SELECTION
PWM Switching Frequency (RFSET)
The PWM switching frequency is set by connecting a resistor
from the FSET/SYNCPWM pin to ground. Figure 11 is a graph
showing the relationship between the typical switching frequency
(y-axis) and the FSET resistor (x-axis). For a required switching
frequency ( fSW ), the FSET resistor value can be calculated as
follows:
RFSET =
27770
fSW
– 4.78
(1)
where fSW is in kHz and RFSET is in kΩ.
When the PWM switching frequency is chosen, the user should
be aware of the minimum controllable on-time ( tON( MIN) ) and
minimum off-time of the A8591 family. If the system required
on-time is less than tON(MIN), then switch node jitter occurs and
the output voltage has increased ripple or oscillations.
If the device synchronization function is employed, then the
base switching frequency should be chosen such that jitter does
not result at the maximum synchronized switching frequency
according to Equation 2.
Output Inductor (LO )
For a peak current mode regulator, it is common knowledge
that, without adequate slope compensation, the system becomes
unstable when the duty cycle is near or above 50%. However, the
slope compensation in the A8591 family is a fixed value (SE ).
Therefore, it is important to calculate an inductor value such that
the falling slope of the inductor current ( SF ) works well with
the device slope compensation. Equations 3a and 3b can be used
to calculate a range of values for the output inductor, based on
the well-known approach of providing slope compensation that
matches 50% to 100% of the down slope of the inductor current.
VOUT +Vf
2 × SE
The PWM switching frequency should be calculated as follows:
fSW =
VOUT
tON(MIN) ×VIN(MAX)
(2)
where VOUT is the output voltage, tON(MIN) is the minimum
controllable on-time of the A8591 family, and VIN(MAX) is the
maximum required operational input voltage (not the peak
surge voltage).
2000
Swtiching Frequency, fSW (kHz)
1800
1600
1400
1200
VOUT +Vf
SE
(3a)
where LO is in µH, Vf is the forward voltage of the asynchronous diode, and the slope compensation (SE ) is a function of
switching frequency, as follows:
SE = 0.13 × f 2SW + 0.69 × f SW+ 0.031
(3b)
where SE is in A/µs and fSW is in MHz.
More recently, Dr. Raymond Ridley presented a formula to
calculate the amount of slope compensation required to critically
damp the double poles at half the PWM switching frequency (this
approach includes the duty cycle (D), which should be calculated
at the minimum input voltage to ensure optimal stability):
LO ≥
1000
≤ LO ≤
VOUT + Vf
VIN(MIN) + Vf
1 – 0.18 ×
SE
VOUT + Vf
(4)
800
To avoid dropout (saturation of the buck regulator), VIN(MIN)
must be approximately 1 to 1.5 V above VOUT when calculating
the inductor value with Equation 4.
600
400
200
0
0
10
20
30
40 50
60 70
80
90 100 110 120 130 140 150
FSET Resistor, RFSET (kΩ)
If Equations 3a or 4 yield an inductor value that is not a standard
value, then the next closest available value should be used. The
final inductor value should allow for 10% to 20% of initial tolerance and 20% to 30% of inductor saturation.
Figure 11: PWM Switching Frequency versus RFSET
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
21
Wide Input Voltage, 2 A Buck
Regulator Family with Low-IQ Mode
A8591
The saturation current of the inductor should be higher than
the peak current capability of the device. Ideally, for output
short-circuit conditions, the inductor should not saturate given
the highest pulse-by-pulse current limit at minimum duty cycle
(ILIM(0)), 4 A (max). This may be too costly. At the very least,
the inductor should not saturate given the peak operating current
according to the following equation:
IPEAK = 4.1 –
SE × (VOUT + Vf )
1.15 × fSW × (VIN(MAX) + Vf )
(5)
where VIN(MAX) is the maximum continuous input voltage,
such as 18 V (not a surge voltage, like 40 V).
Starting with Equation 5 and subtracting half of the inductor
ripple current provides us with an interesting equation to predict
the typical DC load capability of the regulator at a given duty
cycle (D):
IOUT(DC) ≤ 4.1 –
SE × D VOUT × (1 – D )
–
fSW
2 × fSW × LO
(6)
After an inductor is chosen, it should be tested during output
short-circuit conditions. The inductor current should be monitored using a current probe. A good design should ensure the
inductor or the regulator are not damaged when the output is
shorted to ground at maximum input voltage and the highest
expected ambient temperature.
Output Capacitors
The output capacitors filter the output voltage to provide an
acceptable level of ripple voltage, and they also store energy to
help maintain voltage regulation during a load transient. The
voltage rating of the output capacitors must support the output
voltage with sufficient design margin.
The output voltage ripple (ΔVOUT ) is a function of the output
capacitor parameters: CO , ESRCO , and ESLCO:
∆VOUT =
∆IL × ESRCO
+
VIN – VOUT
LO
∆IL
+
8 fSWC O
× ESLCO
(7)
The type of output capacitors determines which terms of Equation 7 are dominant. For ceramic output capacitors, the ESRCO
and ESLCO are virtually zero, so the output voltage ripple will be
dominated by the third term of Equation 7:
∆VOUT ≤
∆IL
8 fSWC O
(8)
To reduce the voltage ripple of a design using ceramic output
capacitors, simply increase the total capacitance, reduce the
inductor current ripple (that is, increase the inductor value), or
increase the switching frequency.
For electrolytic output capacitors, the value of capacitance will be
relatively high, so the third term in Equation 7 will be very small
and the output voltage ripple will be determined primarily by the
first two terms of Equation 7:
∆VOUT = ∆IL × ESRCO +
VIN – VOUT
LO
× ESLCO
(9)
To reduce the voltage ripple of a design using electrolytic output
capacitors, simply decrease the equivalent ESRCO and ESLCO
by using a high(er) quality capacitor, or add more capacitors in
parallel, or reduce the inductor current ripple (that is, increase the
inductor value).
The ESR of some electrolytic capacitors can be quite high so
Allegro recommends choosing a quality capacitor for which the
ESR or the total impedance is clearly documented in the capacitor datasheet. Also, the ESR of electrolytic capacitors usually
increases significantly at cold ambients, as much as 10×, which
increases the output voltage ripple and, in most cases, reduces the
stability of the system.
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
22
Wide Input Voltage, 2 A Buck
Regulator Family with Low-IQ Mode
A8591
The transient response of the regulator depends on the quantity
and type of output capacitors. In general, minimizing the ESR of
the output capacitance will result in a better transient response.
The ESR can be minimized by simply adding more capacitors
in parallel or by using higher quality capacitors. At the instant
of a fast load transient (di/dt), the output voltage changes by the
amount:
∆VOUT = ∆IL × ESRCO +
di
dt
× ESLCO
(10)
After the load transient occurs, the output voltage will deviate
from its nominal value for a short time. The length of this time
depends on the system bandwidth, the output inductor value, and
output capacitance. Eventually, the error amplifier brings the
output voltage back to its nominal value.
The speed at which the error amplifier brings the output voltage back to the setpoint depends mainly on the closed-loop
bandwidth of the system. A higher bandwidth usually results in a
shorter time to return to the nominal voltage. However, a higher
bandwidth system may be more difficult to obtain acceptable gain
and phase margins. Selection of the compensation components
(RZ , CZ , and CP ) are discussed in more detail in the Compensation Components section of this datasheet.
Low-IQ PFM Output Voltage Ripple Calculation
After choosing an output inductor and output capacitor(s), it is
important to calculate the output voltage ripple ( ∆VOUT(PFM) )
during Low-IQ PFM mode. With ceramic output capacitors, the
output voltage ripple in PWM mode is usually negligible, but that
is not the case during Low-IQ PFM mode.
The PFM mode comparator requires about 20 mV or greater of
voltage ripple on the VOUT pin, and generates groups of pulses
to meet this requirement. However, if a single pulse results in a
voltage ripple greater than 20 mV, then the voltage ripple would
be dictated by that single pulse. To calculate the voltage ripple
from that single pulse, first the peak inductor current must be calculated with slope compensation accounted for. The IPEAK(LO_IQ)
specification does not include slope compensation, therefore the
peak inductor current operating point is calculated as follows:
IPEAK_L =
IPEAK(LO_IQ)
SE × LO
1+
VIN – VOUT
(11)
Then, calculate the MOSFET on-time and off-time (Figure 12).
The on-time is defined as the time it takes for the inductor current
to reach IPEAK_L :
tON =
IPEAK_L × LO
(12)
VIN – VOUT – IPEAK_L × (RDS(on)HS + LO(DCR) )
where RDS(on) is the on-resistance of the internal high-side
MOSFET (110 mΩ (typ)) and LO(DCR) is the DC resistance of
the output inductor, LO .
During this rising time interval, the length of time for the inductor current to rise from 0 A to IOUT is:
t1 =
IOUT × LO
(13)
VIN – VOUT – IPEAK_L × (RDS(on)HS + LO(DCR) )
The off-time is defined as the time it takes for the inductor current to decay from IPEAK_L to 0 A:
tOFF =
IPEAK_L × LO
(14)
VOUT + Vf
During this falling time interval, the length of time for the inductor current to fall from IOUT to 0 A is:
t2 =
VOUT
IOUT × LO
(15)
VOUT + Vf
Vpp(LO_IQ)
IL
I PEAK(LO_IQ)
I OUT
t
t1
t ON
t2
t OFF
Figure 12: Calculating the Output Ripple Voltage
in PFM Mode
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
23
Wide Input Voltage, 2 A Buck
Regulator Family with Low-IQ Mode
Given the peak inductor current (IPEAK_L ) and the rise and fall
times (tON and tOFF) for the inductor current, the output voltage
ripple can be calculated for a signal pulse as follows:
VPP(LO_IQ) =
IPEAK_L – IOUT
2 × COUT
× (tON + tOFF – t1 – t2 )
(16)
If VPP(LO_IQ) is greater than the ~20 mV ripple that the PFM
comparator requires, then the output capacitance or inductor
can be adjusted to reduce the PFM mode voltage ripple. In PFM
mode, decreasing the inductor value reduces the PFM ripple, but
may negatively impact the PWM voltage ripple, maximum load
current in PWM mode, or change the mode of operation from
CCM to DCM.
If VPP(LO_IQ) is less than the ~20 mV requirement, the A8591
operates with multiple pulses at the PWM frequency to meet the
ripple requirement. The fixed-frequency operation may result in
DCM or CCM operation during the multiple pulses.
Input Capacitors
Three factors should be considered when choosing the input
capacitors. First, the capacitors must be chosen to support the
maximum expected input surge voltage with adequate design
margin. Second, the capacitor rms current rating must be higher
than the expected rms input current to the regulator. Third, the
capacitors must have enough capacitance and a sufficiently
low ESR to limit the input voltage dV/dt to much less than the
hysteresis of the UVLO circuitry (nominally 400 mV for the
A8591 family) at maximum loading and minimum input voltage.
The input capacitors must deliver an rms current (IRMS) according to the following formula:
IRMS = IOUT D × ( 1 – D)
(17)
where the duty cycle (D) is defined as:
D ≈ (VOUT + Vf ) / (VIN + Vf )
cycle, the input/output current multiplier is 0.40. Therefore, if the
regulator is delivering 2 A of steady-state load current, the input
capacitor(s) must support 0.40 × 2 A or 0.8 A(rms).
IRMS / IOUT
A8591
0.55
0.50
0.45
0.40
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0.00
0
10
and Vf is the forward voltage of the asynchronous diode, D1.
Figure 13 shows the normalized input capacitor rms current
versus duty cycle. To use this graph, simply find the operational
duty cycle (D) on the x-axis and determine the input/output
current multiplier on the y-axis. For example, at a 20% duty
30
40
50
60
Duty Cycle, D (%)
70
80
90
100
Figure 13: Normalized Input Capacitor Ripple
versus Duty Cycle
The input capacitor(s) must limit the voltage deviations at the
VIN pin to significantly less than the device UVLO hysteresis
during maximum load and minimum input voltage. The following
equation allows us to calculate the minimum input capacitance:
CIN ≥
IOUT × D × (1– D)
0.85 × fSW × ∆VIN(MIN)
(19)
where ΔVIN(MIN) is chosen to be much less than the hysteresis
of the VIN UVLO comparator (ΔVIN(MIN) ≤ 150 mV is recommended), and fSW is the nominal PWM frequency.
The D × (1 – D) term in Equation 17 has an absolute maximum
value of 0.25 at 50% duty cycle. So, for example, a very conservative design based on IOUT = 2 A, fSW = 85% of 425 kHz,
D × (1 – D) = 0.25, and ΔVIN = 150 mV yields:
CIN ≥
(18)
20
2.0 (A) × 0.25
= 9.2 µF 361 (kHz) × 150 (mV)
(20)
A good design should consider the DC-bias effect on a ceramic
capacitor: as the applied voltage approaches the rated value, the
capacitance value decreases. This effect is very pronounced with
the Y5V and Z5U temperature characteristic devices (as much as
90% reduction), so these types should be avoided. The X5R and
X7R type capacitors should be the primary choices due to their
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
24
Wide Input Voltage, 2 A Buck
Regulator Family with Low-IQ Mode
A8591
stability versus both DC bias and temperature.
Compensation Components (RZ, CZ , and CP)
For all ceramic capacitors, the DC-bias effect is even more
pronounced on smaller sizes of device case, so a good design
uses the largest affordable case size (such as 1206 or 1210). Also,
it is advisable to select input capacitors with plenty of design
margin in the voltage rating to accommodate the worst-case
transient input voltage (such as a load dump as high as 40 V for
automotive applications).
To properly compensate the system, it is important to understand
where the buck power stage, load resistance, and output capacitance form their poles and zeros in frequency. Also, it is important to understand that the (Type II) compensated error amplifier
introduces a zero and two more poles, and where these should be
placed to maximize system stability, provide a high bandwidth,
and optimize the transient response.
Asynchronous Diode (D1)
There are three requirements for the asynchronous diode. First,
the asynchronous diode must be able to withstand the regulator
input voltage when the high-side MOSFET is on. Therefore,
choose a diode with a reverse voltage rating (VR) higher than
the maximum expected input voltage (that is, the surge voltage). Second, the forward voltage of the diode ( Vf ) should be
minimized or the regulator efficiency suffers. Also, if Vf is too
high, the missing-diode protection in the A8591 family could be
inappropriately activated. A Schottky type diode that can maintain a very low Vf when the regulator output is shorted to ground
at the coldest ambient temperature is highly recommended. Third,
the asynchronous diode must conduct the output current when
the high-side MOSFET is off. Therefore, the average forward
current rating of this diode ( If(av) ) must be high enough to deliver
the load current according to the following equation:
If(av) ≥ IOUT(MAX) (1 – DMIN )(21)
where DMIN is the minimum duty cycle, as defined in Equation 19, and IOUT(MAX) is the maximum continuous output current
of the regulator.
Bootstrap Capacitor
A bootstrap capacitor must be connected between the BOOT and
SW pins to provide floating gate drive to the high-side MOSFET.
Usually, 47 nF is an adequate value. This capacitor should be a
high-quality ceramic capacitor, such as an X5R or X7R, with a
voltage rating of at least 16 V.
The A8591 family incoporates a 10 Ω low-side MOSFET to
ensure that the bootstrap capacitor is always charged, even when
the converter is lightly loaded or pre-biased.
First, consider the power stage of the A8591 family, the output
capacitors, and the load resistance. This circuitry is commonly
referred as the control-to-output transfer function. The low
frequency gain of this circuitry depends on the COMP to SW
current gain ( gmPOWER ), and the value of the load resistor (RL ).
The DC gain (GCO(0HZ) ) of the control-to-output is:
GCO(0Hz) = gmPOWER × RL(22)
The control-to-output transfer function has a pole (fP1), formed
by the output capacitance (COUT) and load resistance (RL),
located at:
fP1 =
1
2� × RL × COUT
(23)
The control-to-output transfer function also has a zero (fZ1)
formed by the output capacitance (COUT) and its associated ESR:
fZ1 =
1
2� × ESR × COUT
(24)
For a design with very low ESR type output capacitors (such
as ceramic or OSCON output capacitors), the ESR zero, fZ1, is
usually at a very high frequency, so it can be ignored. On the
other hand, if the ESR zero falls below or near the 0 dB crossover
frequency of the system (as happens with electrolytic output
capacitors), then it should be cancelled by the pole formed by the
CP capacitor and the RZ resistor (discussed and identified later
as fP3 ).
A Bode plot of the control-to-output transfer function for the
configuration shown in the Typical Application Diagram, with
VOUT = 5 V, IOUT = 2 A, and RL = 2.5 Ω, is shown in Figure 14.
The pole at fP1 can easily be seen at 1.2 kHz, while the ESR zero,
fZ1 , occurs at a very high frequency, 600 kHz (this is typical for
a design using ceramic output capacitors). Note, there is more
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
25
Wide Input Voltage, 2 A Buck
Regulator Family with Low-IQ Mode
A8591
than 90° of total phase shift because of the double-pole at half the
switching frequency.
80
Gain (dB)
20
GCO(0Hz) = 17 dB
f P1 = 1.2 kHz
0
-20
fZ2 =
-40
-60
Phase (°)
180
0
-180
10
30
100
300
3×103
10×103
30×103
100×103
300×103
fP3 =
106
Frequency (Hz)
Figure 14: Control-to-Output Bode Plot
Next, consider the error amplifier ( gm ), and the compensation
network RZ-CZ-CP . It greatly simplifies the transfer function
derivation if RO >> RZ , and CZ >> CP . In most cases, RO >
2 MΩ, 1 kΩ < RZ < 100 kΩ, 220 pF < CZ < 47 nF, and CP <
50 pF, so the following equations are very accurate.
The low frequency gain of the control section (GC(0Hz) ) is
calculated as:
(26)
1
2� × RZ × CZ
(27)
Lastly, the transfer function of the Type-II compensated error
amplifier has a (very) high frequency pole (fP3) dominated by the
RZ resistor and the CP capacitor:
Double Pole at
275 kHz
103
1
2� × RO × CZ
The transfer function of the Type-II compensated error amplifier
also has frequency zero (fZ2) dominated by the RZ resistor and
the CZ capacitor:
60
40
fP2 =
GC(0 Hz) = gm × R0 = AVOL(25)
where
VOUT is the output voltage,
VFB is the reference voltage (0.8 V),
gm is the error amplifier transconductance (750 µA/V ), and
RO is the error amplifier output impedance (AVOL/gm ).
1
2� × RZ × CP
(28)
A Bode plot of the error amplifier and its compensation network
is shown in Figure 15, where fP2, fP3, and fZ2 are indicated on the
Gain plot. Notice that the zero (fZ2 at 2.6 kHz) has been placed
so that it is just above the pole at fP1 previously shown at 1.2 kHz
in the control-to-output Bode plot (Figure 14). Placing fZ2 just
above fP1 results in excellent phase margin, but relatively slow
transient recovery time, as shown later.
Finally, consider the combined Bode plot of both the control-tooutput and the compensated error amplifier (Figure 16). Careful
examination of this plot shows that the magnitude and phase
of the entire system (red curve) are simply the sum of the error
amplifier response (blue curve) and the control to output response
(green curve). As shown in Figure 16, the bandwidth of this
system (fc ) is 60 kHz, the phase margin is 69 degrees, and the
gain margin is 14 dB.
Complete designs for several common output voltages at 2 MHz,
425 kHz, and 300 kHz are provided in Table 2.
The transfer function of the Type-II compensated error amplifier
has a (very) low frequency pole (fP2 ) dominated by the output
error amplifier output impedance (RO) and the CZ compensation
capacitor:
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
26
Wide Input Voltage, 2 A Buck
Regulator Family with Low-IQ Mode
A8591
80
80
60
40
f Z2 = 2.6 kHz
f P2 = 99 Hz
20
Gain (dB)
GC0Hz = 49 dB
f P3 ≈ 100 kHz
0
40
0
-20
-40
-40
-60
-60
180
180
0
-180
10
30
100
300
103
3×103
10×103
30×103
100×103 300×103
106
f c = 50 kHz
20
-20
Phase (°)
Phase (°)
Gain (dB)
60
GM ≈ 14 dB
PM ≈ 45 deg
0
-180
10
30
100
300
103
3×103
10×103
30×103
100×103 300×103
106
Frequency (Hz)
Frequency (Hz)
Figure 15: Type-II Compensated Error Amplifier
Bode Plot
A Generalized Tuning Procedure
This section presents a methodology to systematically apply
design considerations provided above.
1. Choose the system bandwidth (fC ). This is the frequency at
which the magnitude of the gain crosses 0 dB. Recommended
values for fC, based on the PWM switching frequency, are
in the range fSW / 20 < fC < fSW / 7.5. A higher value of fC
generally provides a better transient response, while a lower
value of fC generally makes it easier to obtain higher gain and
phase margins.
Figure 16: Bode Plot of the Complete System
(red curve)
2. Calculate the RZ resistor value. This sets the system bandwidth (fC):
2 × COUT
RZ = fC ×
(29)
gmPOWER × gm
3. Determine the frequency of the pole (fP1). This pole is formed
by COUT and RL. Use Equation 23 (repeated here):
fP1 =
1
2� × RL × COUT
Table 2: Recommended Component Values
VOUT
(V)
3.3
(A8591-1)
5
(A8591)
3.3
(A8591-1)
5
(A8591)
3.3
(A8591-1)
5
(A8591)
fSW
(kHz)
300
425
2000
RFSET
(kΩ)
86.6
59
9.31
LO
(µH)
CO*
(µF)
10
(DR-1050-100-R)
RZ + CZ // CP
RZ
(kΩ)
CZ
(pF)
CP
(pF)
38
24.9
1500
22
22
(744770122)
53
35.7
1500
15
10
(DR-1050-100-R)
38
34
560
15
10
(DR-1050-100-R)
53
47.5
680
8
3.3
(74437346033)
32
39.2
1000
3.3
4.7
(74437346047)
32
54.9
1000
3.3
*The user must consider negative tolerance and DC-bias effect when choosing components to obtain CO .
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
27
A8591
Wide Input Voltage, 2 A Buck
Regulator Family with Low-IQ Mode
4. Calculate a range of values for the CZ capacitor. Use the following:
4
1
< CZ <
f
2� × RZ × C
2� × RZ × 1.5 × fP1
(30)
To maximize system stability (that is, to have the greatest
gain margin), use a higher value of CZ . To optimize transient
recovery time, although at the expense of some phase margin,
use a lower value of CZ .
5. Calculate the frequency of the ESR zero (fZ1 ) formed by the
output capacitor(s) by using Equation 24 (repeated here):
fZ1 =
1
2� × ESR × COUT
If fZ1 is at least 1 decade higher than the target crossover frequency (fC ), then fZ1 can be ignored. This is usually the case
for a design using ceramic output capacitors. Use Equation
28 to calculate the value of CP by setting fP3 to either 5 × fC or
fSW / 2, whichever is higher.
Alternatively, if fZ1 is near or below the target crossover
frequency (fC ), then use Equation 28 to calculate the value
of CP by setting fP3 equal to fZ1. This is usually the case for a
design using high ESR electrolytic output capacitors.
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
28
Wide Input Voltage, 2 A Buck
Regulator Family with Low-IQ Mode
A8591
POWER DISSIPATION AND THERMAL CALCULATIONS
The power dissipated in the A8591 family is the sum of the
power dissipated from the VIN supply current (PIN ), the power
dissipated due to the switching of the high-side power MOSFET (PSW ), the power dissipated due to the rms current being
conducted by the high-side MOSFET (PCOND ), and the power
dissipated by the gate drivers (PDRIVER).
The power dissipated from the VIN supply current can be
calculated using the following Equation:
PIN = VIN × IQ + (VIN - VGS ) × QG × fSW (31)
where
VIN is the input voltage,
IQ is the input quiescent current drawn by the device (nominally 2.5 mA),
VGS is the MOSFET gate drive voltage (typically 5 V),
QG is the MOSFET gate charge (approximately 2.5 nC), and
fSW is the PWM switching frequency.
The power dissipated by the internal high-side MOSFET during
PWM switching can be calculated using the following equation:
PSW =
VIN × IOUT × (tr + tf ) × fSW
2
(32)
where
VIN is the input voltage,
IOUT is the output current,
fSW is the PWM switching frequency, and
tr and tf are the rise and fall times measured at the SW node.
The exact rise and fall times at the SW node depend on the
external components and PCB layout so each design should be
measured at full load. Approximate values for both tr and tf range
from 10 to 15 ns.
2
PCOND = Irms(FET)
× RDS(on)HS
VOUT +Vf
VIN +Vf
∆IL2
2
× IOUT + 12 × RDS(on)HS
The power dissipated by the internal gate drivers can be calculated using the following equation:
PDRIVER = QG × VGS × fSW (34)
where
QG is the gate charge to drive the MOSFET to VGS = 5 V
(about 2.5 nC),
VGS is the gate drive voltage (typically 5 V), and
fSW is the PWM switching frequency.
Bias power dissipation at VOUT pin:
Pbias = VOUT × IIN = 5 V (or 3.3 V) × 2.5 mA
Finally, the total power dissipated by the device (PTOTAL) is the
sum of the previous equations:
PTOTAL = PIN + PSW + PCOND + PDRIVER + Pbias(35)
The average junction temperature can be calculated with the
following equation:
TJ = PTOTAL + RθJA + TA (36)
where
PTOTAL is the total power dissipated as described in Equation 35,
RθJA is the junction-to-ambient thermal resistance (34°C/W on
a 4-layer PCB), and
TA is the ambient temperature.
The maximum junction temperature is dependent on how
efficiently heat can be transferred from the PCB to ambient air. It
is critical that the thermal pad on the bottom of the IC should be
connected to at least one ground plane using multiple vias.
The power dissipated by the high-side MOSFET while it is
conducting can be calculated using the following equation:
=
The RDS(on) of the MOSFET has some initial tolerance plus an
increase from self-heating and elevated ambient temperatures.
A conservative design should accommodate an RDS(on) with
at least a 15% initial tolerance plus 0.39%/°C increase due to
temperature.
(33)
where
IOUT is the regulator output current,
ΔIL is the peak-to-peak inductor ripple current, and
RDS(on)HS is the on-resistance of the high-side MOSFET.
As with any regulator, there are limits to the amount of heat that
can be dissipated before risking thermal shutdown. There are
trade-offs among ambient operating temperature, input voltage,
output voltage, output current, switching frequency, PCB thermal
resistance, airflow, and other nearby heat sources. Even a small
amount of airflow will reduce the junction temperature considerably.
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
29
A8591
Wide Input Voltage, 2 A Buck
Regulator Family with Low-IQ Mode
PCB COMPONENT PLACEMENT AND ROUTING
A good PCB layout is critical if the A8591 family is to provide
clean, stable output voltages. Follow these guidelines to ensure a
good PCB layout.
Figure 17 shows a typical buck converter schematic with the
critical power paths/loops. Figure 18 shows an example PCB
component placement and routing with the same critical power
paths/loops from the schematic.
1. By far, the highest di/dt in the asynchronous buck regulator occurs at the instant the high-side MOSFET turns on
and the capacitance of the asynchronous Schottky diode
(200 to 1000 pF ) is quickly charged to VIN. The ceramic
input capacitors must deliver this fast, short pulse of current.
Therefore the loop, from the ceramic input capacitors through
the high-side MOSFET and into the asynchronous diode to
ground, must be minimized. Ideally, these components are all
connected using only the top metal (that is, do not use vias to
other power/signal layers).
2. When the high-side MOSFET is on, current flows from the
input supply and capacitors, through the high-side MOSFET,
into the load via the output inductor, and back to ground. This
loop should be minimized and have relatively wide traces.
3. When the high-side MOSFET is off, freewheeling current
flows from ground, through the asynchronous diode, into the
load via the output inductor, and back to ground. This loop
should be minimized and have relatively wide traces.
4. The voltage on the SW node transitions from 0 V to VIN very
quickly and is the root cause of many noise issues. It is best
to place the asynchronous diode and output inductor close
to the device to minimize the size of the SW polygon. Also,
keep low-level analog signals (like FB and COMP) away
from the SW polygon.
5. To have the highest output voltage accuracy, the output voltage sense trace should be connected as close as possible to
the load.
6. Place the compensation components (RZ, CZ, and CP) as
close as possible to the COMP pin. Place vias to the GND
plane as close as possible to these components.
7. Place the bootstrap capacitor (CBOOT) near the BOOT pin and
keep the routing from this capacitor to the SW polygon as
short as possible.
8. When connecting the input and output ceramic capacitors,
use multiple vias to GND and place the vias as close as possible to the pads of the components.
9. To minimize PCB losses and improve system efficiency, the
input and output traces should be as wide as possible and be
duplicated on multiple layers, if possible.
10.To improve thermal performance, place multiple vias to the
GND plane around the anode of the asynchronous diode.
11. The thermal pad under the device must connect to the GND
plane using multiple vias. More vias will ensure the lowest
junction temperature and highest efficiency.
12.EMI/EMC issues are always a concern. Allegro recommends
having component locations for an RC snubber from SW to
ground. The resistor should be 1206 size.
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
30
Wide Input Voltage, 2 A Buck
Regulator Family with Low-IQ Mode
A8591
3
VIN
CIN3
CIN2
SW
CIN1
Q1
1
VOUT
LO
Rsnub
D1
CO1
CO2
CO3
CO4
LOAD
Csnub
2
Figure 17: Typical Buck Converter with Critical Paths/Loops Shown
Loop 1 (red): At the instant Q1 turns on, Schottky diode D1, which is
very capacitive, must be very quickly shut off (only 5 to 15 ns of charging
time). This spike of charging current must come from the local input
ceramic capacitor, CIN1. This spike of current is quite large and can be an
EMI/EMC issue if the loop is not minimized. Therefore, the input capacitor
CIN1 and Schottky diode D1 must be placed be on the same (top) layer,
be located near each other, and be grounded at virtually the same point on
the PCB.
Loop 2 (magenta): When Q1 is off, freewheeling inductor current must flow
3
from ground through diode D1 (SW will be at –Vf ), into the output inductor,
out to the load and return via ground. While Q1 is off, the voltage on the
output capacitors will decrease. The output capacitors and Schottky diode
D1 should be placed on the same (top) layer, be located near each other,
and be sharing a good, low-inductance ground connection.
Loop 3 (blue): When Q1 is on, current flows from the input supply and
input capacitors through the output inductor and into the load and the
output capacitors. At this time, the voltage on the output capacitors
increases.
2
1
Figure 18: Example PCB Component Placement and Routing
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
31
Wide Input Voltage, 2 A Buck
Regulator Family with Low-IQ Mode
A8591
PACKAGE OUTLINE DRAWING
For Reference Only – Not for Tooling Use
(Reference JEDEC MO-229)
Dimensions in millimeters – NOT TO SCALE
Exact case and lead configuration at supplier discretion within limits shown
0.30
3.00 ±0.05
0.50
10
10
0.85
3.00 ±0.05
1.64 3.10
A
1
2
DETAIL A
10X
D
0.05
1
0.75 ±0.05
C
0.25 ±0.05
SEATING
PLANE
C
PCB Layout Reference View
0.05
0.00
0.5 BSC
1
2.38
C
0.40 ±0.10
0.08 REF
2
0.203 REF
0.40 ±0.10
0.05 REF
Detail A
1.65 ±0.10
B
0.05 REF
A Terminal #1 mark area
B Exposed thermal pad (reference only, terminal #1 identifier appearance at supplier discretion)
10
2.38 ±0.10
C Reference land pattern layout (reference IPC7351 SON50P300X300X80-11WEED3M);
all pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary to meet
application process requirements and PCB layout tolerances; when mounting on a
multilayer PCB, thermal vias at the exposed thermal pad land can improve thermal
dissipation (reference EIA/JEDEC Standard JESD51-5)
D Coplanarity includes exposed thermal pad and terminals
Figure 19: Package EJ, Wettable Flank DFN-10 with Exposed Thermal Pad
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
32
Wide Input Voltage, 2 A Buck
Regulator Family with Low-IQ Mode
A8591
Revision History
Revision No.
Revision Date
–
December 17, 2015
Description of Revision
Initial Release
Copyright ©2016, Allegro MicroSystems, LLC
Allegro MicroSystems, LLC reserves the right to make, from time to time, such departures from the detail specifications as may be required to
permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that
the information being relied upon is current.
Allegro’s products are not to be used in any devices or systems, including but not limited to life support devices or systems, in which a failure of
Allegro’s product can reasonably be expected to cause bodily harm.
The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, LLC assumes no responsibility for its
use; nor for any infringement of patents or other rights of third parties which may result from its use.
For the latest version of this document, visit our website:
www.allegromicro.com
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
33
Similar pages