XMC 400 0 Applic atio n Ki t For XMC4000 Family CP U_ 45 A - V3 CPU Board XMC4500 General Purpose Boa rd Us er‘s Ma nu al Revision 1.0, 2014-01-10 Mic rocon t rolle r Edition 2014-01-10 Published by Infineon Technologies AG 81726 Munich, Germany © 2014 Infineon Technologies AG All Rights Reserved. Legal Disclaimer The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights of any third party. Information For further information on technology, delivery terms and conditions and prices, please contact the nearest Infineon Technologies Office (www.infineon.com). Warnings Due to technical requirements, components may contain dangerous substances. For information on the types in question, please contact the nearest Infineon Technologies Office. Infineon Technologies components may be used in life-support devices or systems only with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered. CPU_45A-V3 CPU Board XMC4500 General Purpose Revision History Page or Item Subjects (major changes since previous revision) Revision V1.0, 2014-01-10 Initial release Trademarks of Infineon Technologies AG AURIX™, C166™, CanPAK™, CIPOS™, CIPURSE™, EconoPACK™, CoolMOS™, CoolSET™, CORECONTROL™, CROSSAVE™, DAVE™, EasyPIM™, EconoBRIDGE™, EconoDUAL™, EconoPIM™, EiceDRIVER™, eupec™, FCOS™, HITFET™, HybridPACK™, I²RF™, ISOFACE™, IsoPACK™, MIPAQ™, ModSTACK™, my-d™, NovalithIC™, OptiMOS™, ORIGA™, PRIMARION™, PrimePACK™, PrimeSTACK™, PRO-SIL™, PROFET™, RASIC™, ReverSave™, SatRIC™, SIEGET™, SINDRION™, SIPMOS™, SmartLEWIS™, SOLID FLASH™, TEMPFET™, thinQ!™, TRENCHSTOP™, TriCore™. Other Trademarks Advance Design System™ (ADS) of Agilent Technologies, AMBA™, ARM™, MULTI-ICE™, KEIL™, PRIMECELL™, REALVIEW™, THUMB™, µVision™ of ARM Limited, UK. AUTOSAR™ is licensed by AUTOSAR development partnership. Bluetooth™ of Bluetooth SIG Inc. CAT-iq™ of DECT Forum. COLOSSUS™, FirstGPS™ of Trimble Navigation Ltd. EMV™ of EMVCo, LLC (Visa Holdings Inc.). EPCOS™ of Epcos AG. FLEXGO™ of Microsoft Corporation. FlexRay™ is licensed by FlexRay Consortium. HYPERTERMINAL™ of Hilgraeve Incorporated. IEC™ of Commission Electrotechnique Internationale. IrDA™ of Infrared Data Association Corporation. ISO™ of INTERNATIONAL ORGANIZATION FOR STANDARDIZATION. MATLAB™ of MathWorks, Inc. MAXIM™ of Maxim Integrated Products, Inc. MICROTEC™, NUCLEUS™ of Mentor Graphics Corporation. Mifare™ of NXP. MIPI™ of MIPI Alliance, Inc. MIPS™ of MIPS Technologies, Inc., USA. muRata™ of MURATA MANUFACTURING CO., MICROWAVE OFFICE™ (MWO) of Applied Wave Research Inc., OmniVision™ of OmniVision Technologies, Inc. Openwave™ Openwave Systems Inc. RED HAT™ Red Hat, Inc. RFMD™ RF Micro Devices, Inc. SIRIUS™ of Sirius Satellite Radio Inc. SOLARIS™ of Sun Microsystems, Inc. SPANSION™ of Spansion LLC Ltd. Symbian™ of Symbian Software Limited. TAIYO YUDEN™ of Taiyo Yuden Co. TEAKLITE™ of CEVA, Inc. TEKTRONIX™ of Tektronix Inc. TOKO™ of TOKO KABUSHIKI KAISHA TA. UNIX™ of X/Open Company Limited. VERILOG™, PALLADIUM™ of Cadence Design Systems, Inc. VLYNQ™ of Texas Instruments Incorporated. VXWORKS™, WIND RIVER™ of WIND RIVER SYSTEMS, INC. ZETEX™ of Diodes Zetex Limited. Last Trademarks Update 2011-02-24 Template: IFX_Template_2011-02-24.dot CPU_45A-V3 CPU Board XMC4500 General Purpose Table of Contents Table of Contents Introduction ............................................................................................................................................................ 7 1 1.1 1.2 Overview ............................................................................................................................................. 7 Key Features ........................................................................................................................................ 7 Block Diagram ...................................................................................................................................... 8 2 2.1 2.2 2.3 2.4 2.5 2.5.1 2.5.2 2.5.3 2.6 2.7 2.8 2.9 2.10 2.11 2.11.1 2.11.2 2.11.3 Hardware Description ........................................................................................................................ 9 Power Supply ..................................................................................................................................... 10 Reset .................................................................................................................................................. 12 Clock Generation................................................................................................................................ 12 Boot Option ........................................................................................................................................ 13 Debug Interface .................................................................................................................................. 14 On-board USB Debugger ................................................................................................................... 14 Cortex Debug Connector (10-pin) ...................................................................................................... 15 Cortex Debug+ETM Connector (20-pin) ............................................................................................ 16 Serial Flash Memory .......................................................................................................................... 18 USB .................................................................................................................................................... 19 RTC .................................................................................................................................................... 21 User LEDs and User Buttons ............................................................................................................. 22 Potentiometer ..................................................................................................................................... 22 Satellite Connectors ........................................................................................................................... 23 COM Connector ................................................................................................................................. 24 HMI Connector ................................................................................................................................... 25 ACT Satellite Connector ..................................................................................................................... 26 3 Differences to Board Version V2 .................................................................................................... 27 4 4.1 4.2 4.3 Production Data................................................................................................................................ 27 Schematics ......................................................................................................................................... 27 Component Placement and Geometry ............................................................................................... 32 Bill of Material (BOM) ......................................................................................................................... 33 Board User's Manual 4 Revision 1.0, 2014-01-10 CPU_45A-V3 CPU Board XMC4500 General Purpose List of Figures List of Figures Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9 Figure 10 Figure 11 Figure 12 Figure 13 Figure 14 Figure 15 Figure 16 Figure 17 Figure 18 Figure 19 Figure 20 Figure 21 Figure 22 Figure 23 Figure 24 Figure 25 Figure 26 Figure 27 Figure 28 Figure 29 Figure 30 CPU_45A-V3 Board Block Diagram..................................................................................................... 8 CPU Board XMC4500 General Purpose (CPU_45A-V3)..................................................................... 9 Powering option through USB interface (5 V) .................................................................................... 10 CPU_45A-V3 Board Power ................................................................................................................ 11 Battery (VBAT Supply) ....................................................................................................................... 11 Reset .................................................................................................................................................. 12 Reset LED and Reset Switch ............................................................................................................. 12 Clock Generation................................................................................................................................ 13 Boot Options Switch ........................................................................................................................... 13 On-Board USB Debugger .................................................................................................................. 14 Cortex Debug Connector (10-pin) ...................................................................................................... 15 Cortex Debug Connector (10-pin) Layout .......................................................................................... 15 Cortex Debug+ETM Connector (20-pin) ............................................................................................ 16 Cortex Debug+ETM Connector (20-pin) Layout ................................................................................ 17 Quad SPI Flash Interface Circuit ........................................................................................................ 18 Quad SPI Flash .................................................................................................................................. 18 USB Connector Schematic ................................................................................................................ 19 USB power generation - Host/OTG mode ......................................................................................... 19 Battery Holder for Coin Cell ............................................................................................................... 21 RTC .................................................................................................................................................... 21 GPIO LED .......................................................................................................................................... 22 Satellite Connectors ........................................................................................................................... 23 Satellite Connector Type COM .......................................................................................................... 24 Satellite Connector Type HMI ............................................................................................................ 25 Satellite Connector Type ACT ............................................................................................................ 26 Schematic of Satellite Connectors, USB-OTG ................................................................................... 28 Schematic of XMC4500 ..................................................................................................................... 29 Schematic of Power Supply, Debug Connectors, Reset Circuit ........................................................ 30 Schematic of On-board Debugger ..................................................................................................... 31 Component Placement and Geometry ............................................................................................... 32 Board User's Manual 5 Revision 1.0, 2014-01-10 CPU_45A-V3 CPU Board XMC4500 General Purpose List of Figures List of Tables Table 1 Table 2 Table 3 Table 4 Table 5 Table 6 Table 7 Table 8 Table 9 Table 10 Table 11 Table 12 Power status LED’s ............................................................................................................................ 10 Power Measurement .......................................................................................................................... 11 Boot Options Settings ........................................................................................................................ 13 Cortex Debug Connector (10 Pin) ...................................................................................................... 15 Cortex Debug+ETM Connector (20 Pin) ............................................................................................ 16 Quad SPI Signals ............................................................................................................................... 18 USB micro AB connector Pinout ........................................................................................................ 19 GPIO LED .......................................................................................................................................... 22 User Button ........................................................................................................................................ 22 Potentiometer ..................................................................................................................................... 22 Differences to older board versions ................................................................................................... 27 BOM of CPU_45A-V3 Board .............................................................................................................. 33 Board User's Manual 6 Revision 1.0, 2014-01-10 CPU_45A-V3 CPU Board XMC4500 General Purpose Overview Introduction This document describes the features and hardware details of the CPU Board XMC4500 General Purpose (CPU_45A-V3) designed to work with Infineon’s XMC4500 Microcontroller. This board is part of Infineon’s XMC4000 Application Kits. 1 Overview The CPU board CPU_45A-V3 houses the XMC4500 Microcontroller and three satellite connectors (HMI, COM, ACT) for application expansion. The board along with satellite cards (e.g. HMI_OLED-V1, COM_ETH-V1, AUT_ISO-V1, MOT_GPDLV-V boards) demonstrates the capabilities of XMC4500. The main use case for this board is to demonstrate the generic features of XMC4500 device including tool chain. The focus is safe operation under evaluation conditions. The board is neither cost nor size optimized and does not serve as a reference design. 1.1 Key Features The CPU_45A-V3 board is equipped with the following features ® XMC4500 (ARM Cortex™-M4-based) Microcontroller, 120 MHz CPU clock, 1 MByte on-chip Flash, 160 kByte RAM, LQFP-144, Connection to XMC4500 satellite cards via satellite connectors COM, HMI and ACT USB OTG Host/Device support via micro USB connector Debug options − On-board Debugger via Debug USB connector − Cortex Debug connector 10-pin (0.05”) − Cortex Debug+ETM connector 20-pin (0.05”) Reset push button 32 MBit quad SPI flash memory Boot option switch PowerScale Connector: Ready for MCU power consumption analysis 5 LED’s 3 Power indicating LED’s 1 User LEDs (P3.9) 1 RESET LED 1 Debug LED User Button connected to P2.15 Potentiometer, connected to analog input P14.1 Power supply − Via Micro-USB connector in USB device mode − Via satellite connector pins (COM/ACT satellites cards can supply power to CPU board) − Via Debug USB connector − RTC backup battery Board User's Manual 7 Revision 1.0, 2014-01-10 CPU_45A-V3 CPU Board XMC4500 General Purpose Overview 1.2 Block Diagram Figure 1 shows the functional block diagram of the CPU_45A-V3 board. For more information about the power supply please refer to chapter 2.1. The CPU board has got the following building blocks: - 3 Satellite Connectors (COM, HMI ACT) - On-board Debugger via Debug USB connector (Micro-USB) - User LED connected to P3.9 - User Button connected to P2.15 - Quad SPI flash memory (EE) connected to USIC1 Channel1 with Chip-Select1 - 2 Cortex Debug Connectors - Variable resistor (POTI) connected to GPIO P14.1 - USB On-The-Go Connector (Micro-USB) On-board Debugger XMC4200 SWV SWD RS485 Debug+ETM 20pin CAN1 JTAG 2xGPIO ETH CAN CAN2 EE LED TS U1C1 2xCS QSPI U2C1 U0C1 4xCS SDMMC U1C0 EE CCU 4/8 CAPCOM POSIF ENCODER DSD DSMOD DAC OPAMP ADC SENSOR ACT RMII POTI GPIO I2S I2C SPI GPIO SD SPI SPI GPIO GPIO GPIO 2x TS SPI GPIO GPIO GPIO GPIO GPIO GPIO I2C_IOEX COM SPI USB XMC4500 LQFP144 ETH QSPI CPU Board XMC4500 General Purpose Button CPU_45A-V3 U0C0 EXTBUS CAN USB OTG LED BSL UART CAN Debug 10pin SWV SWD UART CAN Debug USB I2C I2C 2xISOFACE I2C_IOEX HMI I2C_IOEX reset OLED HEADSET cmd SDCARD TOUCH Figure 1 Block_Diag.emf CPU_45A-V3 Board Block Diagram Board User's Manual 8 Revision 1.0, 2014-01-10 CPU_45A-V3 CPU Board XMC4500 General Purpose Hardware Description 2 Hardware Description The following sections give a detailed description of the hardware and how it can be used. Debug USB Connector COM Satellite Connector ACT Satellite Connector User LEDs and User Buttons On-board Debugger 5V to 3.3V Voltage Regulator Serial Quad-SPI Flash Power indicating LEDs Boot Option Switch XMC4500 CPU Reset Circuit Debug Connectors Battery Holder Potentiometer HMI Satellite Connector Figure 2 Board_Interfaces.emf CPU Board XMC4500 General Purpose (CPU_45A-V3) Board User's Manual 9 Revision 1.0, 2014-01-10 CPU_45A-V3 CPU Board XMC4500 General Purpose Hardware Description 2.1 Power Supply The CPU_45A-V3 board can be powered via the USB plug (5 V); however, there is a current limit that can be drawn from the host PC through USB. If the CPU_45A-V3 board is used to drive other satellite cards (e.g. AUT_ISO-V1 or MOT_GPDLV-V2) and the total current required exceeds 500 mA, then the board needs to be powered by either an external power supply connected to USB or by a satellite card, which supports external power supply like e.g. AUT_ISO-V1, MOT_GPDLV-V2, COM_ETH-V1. For powering the board through USB interface, connect the USB cable provided with the kit to the Micro-USB connector on board. USB OTG Debug USB IFX1763 3.3V Linear LDO Voltage Regulator PowerScale Probe Power indicating LEDs Power.emf Figure 3 Powering option through USB interface (5 V) To indicate the power status of CPU_45A-V3 board three LED’s are provided on board (See Figure 3). The LED will be “ON” when the corresponding rail is powered. Table 1 Power status LED’s LED Reference Power Rail Voltage Note V401 VDD5 5V Must always be “ON” V402 VDD5USB 5V “ON” if powered by USB plug V403 VDD3.3 3.3 V Must always be “ON” Board User's Manual 10 Revision 1.0, 2014-01-10 CPU_45A-V3 CPU Board XMC4500 General Purpose Hardware Description USB OTG Power LED Debug USB Power LED VDD5USB +5V Power LED VDD5 +5V CPU Board XMC4400 General Purpose CPU_45A-V3 VDD3.3 +3.3V VDD3.3 On Board Devices U401 U403 U300 JP300 Lin. Voltage Regulator IFX1763 VDD5USB VDD3.3 VDDP HIB_IO_1 EN P3.2 VDD5 VDD5 XMC4500 LQFP144 VBAT BATTERY HMI Sat. Connector Figure 4 COM Sat. Connector ACT Sat. Connector Power_Block.emf CPU_45A-V3 Board Power Battery Holder Battery.emf Figure 5 Battery (VBAT Supply) Hitex PowerScale probe is provided on the CPU_45A-V3 board to measure the power consumption. Table 2 Power Measurement Jumper Function Description JP300 PowerScale A Hitex PowerScale probe can be connected for current sensing the VDD3.3 (CPU power source). Default: pos. 1-2 (closed) Note: On the PCB there is a shorting trace between pin 1-2. This trace has to be cut first, before using PowerScale. Pin 3 is GND. The maximum current drawn by the CPU board without any satellite cards connected is about 150 mA. Board User's Manual 11 Revision 1.0, 2014-01-10 CPU_45A-V3 CPU Board XMC4500 General Purpose Hardware Description 2.2 Reset The reset pin (PORST#) of the XMC45000 is a bi-directional pin. An internal pull-up resistor will keep the PORST# pin high during normal operation. A low level at this pin will force a hardware reset. In case of an internal reset the PORST# pin will drive a low signal. An internal circuit of the XMC4500 ensures a save Poweron-Reset. XMC4500 does not require any additional external components to generate a reset signal during power-up. An on-board reset button (SW400, RESET) supports a hardware reset of the CPU during operation. The reset signal is also routed to all satellite connectors. The reset state is indicated by a red LED (V407). The LED will be “ON” during reset state and will be “OFF” during normal operation conditions. Figure 6 Reset Reset LED Reset Button RST.emf Figure 7 2.3 Reset LED and Reset Switch Clock Generation An external 12 MHz crystal provides the clock signal to the XMC4500 microcontroller. The drive strength of the oscillator is set to maximum by software, in order to ensure a safe start-up of the oscillator even under worst case conditions. A serial 510 Ohm resistor will attenuate the oscillations during operations. For the RTC clock a separate external 32.768 kHz crystal is used on board. Board User's Manual 12 Revision 1.0, 2014-01-10 CPU_45A-V3 CPU Board XMC4500 General Purpose Hardware Description Figure 8 2.4 Clock Generation Boot Option During power-on-reset the XMC4500 latches the dip switch SW300 settings via the TCK and the TMS pin. Based on the values latched different boot options are possible. Table 3 Boot Options Settings BSL (TMS) CAN/UART (TCK) Boot Option OFF (1) UART (0) Normal Mode (Boot from flash) ON (0) UART (0) ASC BSL Enabled (Boot from UART) OFF (1) CAN (1) BMI Customized Boot Enabled ON (0) CAN (1) CAN BSL Enabled (Boot from CAN) Boot Option Switch Boot_Switch.emf Figure 9 Boot Options Switch Board User's Manual 13 Revision 1.0, 2014-01-10 CPU_45A-V3 CPU Board XMC4500 General Purpose Hardware Description 2.5 Debug Interface The CPU_45A-V3 board supports JTAG debug via 3 different connectors. On-board Debugger Cortex Debug Connector (10-pin) Cortex Debug+ETM Connector (20-pin) The Hexagon Application Boards are designed to use “Serial Wire Debug” as debug interface. JTAG is not supported by default because the GPIO P0.7 (TDI), where the required TDI function is mapped to, is used by various Actuator boards connected to the ACT satellite connector. Note: It is strongly recommended not to use JTAG debug mode, especially if satellites boards are connected, which uses the GPIO 0.7. For the same reason also do not use the on-board debugger in JTAG mode. If you want to use the JTAG debug mode through the cortex debug connectors (X400, X401) anyway, enable the JTAG interface of the XMC device by assembling the pull-up resistor R427 (4k7 Ohm) and the resistor R410 (0 - 33 Ohm). 2.5.1 On-board USB Debugger The on-board debugger supports Serial Wire Debug Serial Wire Viewer Full Duplex UART communication via a USB Virtual COM The on-board debugger can be accessed through the Debug USB connector shown in Figure 10. The Debug LED V502 shows the status during debugging. Debug USB Debug LED On-board Debugger Debugger.emf Figure 10 On-Board USB Debugger When using an external debugger connected to the 10-pin/20-pin Cortex Debug Connector, the on-board debugger is switched off. When using the USB virtual COM port function of the on-board debugger the UART interface to the COM satellite is disabled through the switches U301 and U303. Board User's Manual 14 Revision 1.0, 2014-01-10 CPU_45A-V3 CPU Board XMC4500 General Purpose Hardware Description 2.5.2 Cortex Debug Connector (10-pin) The CPU_45A-V3 board supports Serial Wire debug operation and Serial Wire viewer operation (via the SWO signal when Serial Wire debug mode is used) through the 10-pin Cortex Debug Connector. When using an external debugger connected to the 10-pin Cortex Debug Connector, the on-board debugger is switched off. Cortex Debug Connector (10-pin) VCC 1 2 SWDIO / TMS GND 3 4 SWDCLK / TCK GND 5 6 SWO / TDO KEY 7 8 NC / TDI GNDDetect 9 10 nRESET cortex-10pin.emf Figure 11 Cortex Debug Connector (10-pin) Table 4 Cortex Debug Connector (10 Pin) Pin No. Signal Name Serial Wire Debug JTAG Debug 1 VCC +3.3 V +3.3 V 2 SWDIO / TMS Serial Wire Data I/O Test Mode Select 3 GND Ground Ground 4 SWDCLK / TCK Serial Wire Clock Test Clock 5 GND Ground Ground 6 SWO / TDO Trace Data OUT Test Data OUT 7 KEY KEY KEY 8 NC / TDI Not connected Test Data IN 9 GNDDetect Ground Detect Ground Detect 10 nRESET Reset (Active Low) Reset (Active Low) Cortex Debug Connector (10 Pin) 10Pin_Conn.emf Figure 12 Cortex Debug Connector (10-pin) Layout Board User's Manual 15 Revision 1.0, 2014-01-10 CPU_45A-V3 CPU Board XMC4500 General Purpose Hardware Description 2.5.3 Cortex Debug+ETM Connector (20-pin) The CPU_45A-V3 board supports Serial Wire debug operation, Serial Wire viewer operation (via SWO connection when Serial Wire debug mode is used) and Instruction Trace operation through the 20-pin Cortex Debug+ETM Connector. JTAG operation additionally would require the TDI (P0.7) signal. By default the TDI signal is disconnected from the Cortex Debug Connectors by a not assembled resistor R410, because the pin P0.7 is used by the Actuator boards connected to the ACT satellite connector. Cortex Debug+ETM Connector (20-pin) VCC 1 2 SWDIO / TMS GND 3 4 SWDCLK / TCK GND 5 6 SWO / TDO / EXTa / TRACECTL KEY 7 8 NC/EXTb/TDI GNDDetect 9 10 nRESET GND/TgtPwr+Cap 11 12 TRACECLK GND/TgtPwr+Cap 13 14 TRACEDATA[0] GND 15 16 TRACEDATA[1] GND 17 18 TRACEDATA[2] GND 19 20 TRACEDATA[3] cortex-20pin.emf Figure 13 Cortex Debug+ETM Connector (20-pin) Table 5 Cortex Debug+ETM Connector (20 Pin) Pin No. Signal Name Serial Wire Debug JTAG Debug 1 VCC +3.3 V +3.3 V 2 SWDIO / TMS Serial Wire Data I/O Test Mode Select 3 GND Ground Ground 4 SWDCLK / TCK Serial Wire Clock Test Clock 5 GND Ground Ground 6 SWO / TDO Trace Data OUT Test Data OUT 7 KEY KEY KEY 8 NC / TDI Not connected Test Data IN 9 GNDDetect Ground Detect Ground Detect 10 nRESET Reset (Active Low) Reset (Active Low) 11 GND/TgtPwr+Cap Ground Ground 12 TRACECLK Trace Clock Trace Clock 13 GND/TgtPwr+Cap Ground Ground 14 TRACEDATA[0] Trace Data 0 Trace Data 0 15 GND Ground Ground Board User's Manual 16 Revision 1.0, 2014-01-10 CPU_45A-V3 CPU Board XMC4500 General Purpose Hardware Description Table 5 Cortex Debug+ETM Connector (20 Pin) Pin No. Signal Name Serial Wire Debug JTAG Debug 16 TRACEDATA[1] Trace Data 1 Trace Data 1 17 GND Ground Ground 18 TRACEDATA[2] Trace Data 2 Trace Data 2 19 GND Ground Ground 20 TRACEDATA[3] Trace Data 3 Trace Data 3 Cortex Debug+ETM Connector (20 Pin) 20Pin_Conn.emf Figure 14 Cortex Debug+ETM Connector (20-pin) Layout Board User's Manual 17 Revision 1.0, 2014-01-10 CPU_45A-V3 CPU Board XMC4500 General Purpose Hardware Description 2.6 Serial Flash Memory The CPU_45A-V3 board provides a 32 Mbit serial flash memory from Micron (type: N25Q03) interfaced to XMC4500 through a SPI interface. The SPI interface can be configured as single, dual or quad SPI. Table 6 Quad SPI Signals Pin No. Pin Description Signal Name Signal Description P0.13 U1C1_SCLKOUT CLK Clock P3.3 U1C1_SELO1 CS# Active Low Chip Select P3.15 U1C1_DOUT0 DI (IO0) Data Input/Output of Flash (MTSR/MOSI) P3.14 U1C1_DX0B DO (IO1) Data Input/Output of Flash (MRST/MISO ) P0.14 U1C1_HOUT3/DWIN3 HOLD# (IO3) Data Input/Output P0.15 U1C1_HOUT2/DWIN2 WP# (IO2) Data Input/Output Figure 15 Quad SPI Flash Interface Circuit 32 Mbit serial Quad-SPI Flash (Micron, N25Q032A13) SPI-Flash.emf Figure 16 Quad SPI Flash Board User's Manual 18 Revision 1.0, 2014-01-10 CPU_45A-V3 CPU Board XMC4500 General Purpose Hardware Description 2.7 USB The XMC4500 supports USB interface in host only mode, device only mode or as an OTG Dual Role Device (DRD). In USB device mode, power is expected through VBUS (pin 1) from an external host (e.g. PC). When the current is more than 500 mA power from an external source through satellite cards shall be used. Note: Some PCs, notebooks or hubs have a weak USB supply which is not sufficient for proper supply. In this case use an external 5 Volt power supply or a powered USB hub. Figure 17 USB Connector Schematic Port P0.9 of XMC4500 is connected to the USB ID pin (pin 4). An OTG device will detect whether a USB 3.0 Micro-A or Micro-B plug is inserted by checking the ID pin. When the ID = FALSE, Micro-A connector is plugged and when ID = TRUE a Micro-B connector is plugged in. When ID is true the XMC4500 acts as USB host else as USB device. Table 7 USB micro AB connector Pinout Pin No. Pin Name Pin Description 1 VBUS 5V 2 D- Data Minus 3 D+ Data Plus 4 ID Identification 5 GND Ground Figure 18 USB power generation - Host/OTG mode Board User's Manual 19 Revision 1.0, 2014-01-10 CPU_45A-V3 CPU Board XMC4500 General Purpose Hardware Description In the host only mode and OTG mode the CPU_45A-V3 board is capable of supplying power to the connected device (e.g. USB mouse). The board has a power-switch which is controlled by the XMC4500. Port P3.2 (active high) is used for this purpose. In the Host/OTG mode a low active FAULT signal indicates to XMC4500 via HIB_IO_0 signal, if more than 500 mA current is drawn by the external device. HIB_IO_0 signal is used as general purpose input pin for this implementation. Diode V400 will allow powering the board through USB in all USB modes via e.g. a PC. Board User's Manual 20 Revision 1.0, 2014-01-10 CPU_45A-V3 CPU Board XMC4500 General Purpose Hardware Description 2.8 RTC The XMC4400 CPU has two power domains, the Core Domain and Hibernate Domain. The Core Domain (VDDP pins) is connected to the VDD3.3 rail. An on-board LDO voltage regulator generates VDD3.3 (3.3 V) from VDD5 (5 V). The Hibernate Domain is powered via the auxiliary supply pin VBAT, which is supplied by either a 3 V coin cell (size 1216, 1220, 1225) plugged into the battery holder (see Figure 19) or 3.3 V (VDD3.3) generated by the onboard voltage regulator. Battery Holder Battery.emf Figure 19 Battery Holder for Coin Cell The Real Time Clock (RTC) is located in the hibernate domain. The XMC4500 uses the HIB_IO_1 signal (active low) to shut down the external LDO voltage regulator which generates the VDD3.3 (Core Domain). Even if the Core Domain is not powered the Hibernate Domain will operate if VBAT is available. The RTC keeps running as long as the Hibernate Domain is powered via the auxiliary supply VBAT. The RTC is capable to wake-up the whole system from Hibernate mode by setting HIB_IO_1 to high. With VDD3.3 power supply switched off and no coin cell supply the power in the capacitor connected to VBAT will provide power to the hibernate domain for about 10 seconds (depending on which features in the hibernate domain are enabled). XMC4500 VDD3.3 CPU VDDP Core Domain EN HIBIO_1 Hibernate Domain Hibernate Control SPI IFX1763 LDO Voltage Reg. 12 MHz RTC VBAT 32.768 kHz Internal OSC Battery External OSC + RTC.emf Figure 20 RTC Board User's Manual 21 Revision 1.0, 2014-01-10 CPU_45A-V3 CPU Board XMC4500 General Purpose Hardware Description 2.9 User LEDs and User Buttons The port pin P3.9 of XMC4500 is connected to a LED V300. More user LED’s are available through I2C GPIO expander on most of the satellite cards. Table 8 GPIO LED LED Connected to Port Pin V300 GPIO P3.9 The User Button is connected to port pin P2.15 of the XMC4500. Table 9 User Button Button Connected to Port Pin BUTTON1 P2.15 User Button User LED1 Button_LED.emf Figure 21 GPIO LED 2.10 Potentiometer The CPU_45A-V3 board provides a potentiometer POT1 for ease of use and testing of the on-chip analog to digital converter. The potentiometer is connected to the analog input G0_CH1 (P14.1). The analog output of the potentiometer ranges from 0 V to 3.3 V. Table 10 Potentiometer R300 Board User's Manual P14.1 / G0_CH1 (Group 0, Channel 1) 22 Revision 1.0, 2014-01-10 CPU_45A-V3 CPU Board XMC4500 General Purpose Hardware Description 2.11 Satellite Connectors The CPU_45A-V3 board provies three satellite connectors for application extension by satellite cards: COM satellite connector (Communication) HMI satellite connector (Human Machine Interface) ACT satellite connector (Actuator) Note: Satellite cards shall be connected to their matching satellite connectors only. (For e.g. COM satellite cards shall be connected to COM satellite connector only) ACT Satellite Connector COM Satellite Connector HMI Satellite Connector Sat_Conn.emf Figure 22 Satellite Connectors Board User's Manual 23 Revision 1.0, 2014-01-10 Board User's Manual 24 nc nc nc nc nc GND nc nc nc nc nc VSS nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc GND EBU_A EBU_A EBU_A EBU_A EBU_A EBU_A EBU_A EBU_A GND EBU_CS EBU_CS EBU_BC EBU_BC EBU_RD EBU_WR EBU_ADV VDD5 VDD5 COM_GPIO0 COM 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 GND P3.7 P3.7 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 COM nc P15.8 VSS P1.9 P1.8 ETH0_RXERD ETH0_CLK_RMIIC GND nc CAN_N2_TXD CAN_N2_RXDA U0C1_DOUT0 GND RSVD CAN_TXD CAN_RXD SPI_MTSR RESET VDD5 GND EBU_AD EBU_AD EBU_AD EBU_AD EBU_AD EBU_AD EBU_AD EBU_AD EBU_AD EBU_AD EBU_AD EBU_AD EBU_AD EBU_AD EBU_AD EBU_AD GND nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc RESET# GPIO VDD5 P5.8 P0.6 I2C_SCL VSS nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc PORST P0.6 P3.0 U1C0_SCLKOUT SPI_SCLK P2.5 U0C1_DX0B U0C1_SCLKOUT SPI_MRST P3.13 nc P5.3 P15.9 P2.8 P2.9 ETH_RMII ETH0_TXD1 ETH_RMII P0.14 ETH_RMII nc RSVD P0.15 ETH0_TXD0 U1C1_DOUT3 qSPI_D3 P3.14 P3.15 VSS XMC Pin ETH0_CRS_DVC U1C1_DOUT2 qSPI_D2 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 ETH_RMII U1C1_DOUT1 qSPI_D1 6 ETH_RMII GND U1C1_DOUT0 GND qSPI_D0 4 VSS P14.13 P14.13 COM_GPIO1 I2C_SDA U1C0_DOUT0/DX0D P2.14 SPI_CSC1 SPI_CSC2 U0C1_SELO0 P3.1 ASC_TXD SPI_CSC0 nc P5.5 ASC_RXD ASC_DIR ETH_RMII ETH_RMII ETH_RMII ETH_RMII RSVD nc U0C0_DOUT0 P5.9 P5.5 ETH0_MDC ETH0_TX_EN P2.7 P1.5 (3) ETH0_MDO P2.0 U0C0_DX0B ETH0_RXD0A P2.2 P1.4 (3) RSVD ETH0_RXD1A P2.3 nc nc nc 7 RSVD 5 P3.10 nc nc qSPI_CS qSPI_CS 3 nc U1C1_SELO1 P3.3 XMC Function Function 2 COM 1 P3.10 ETH_RMII U1C1_SELO0 P0.12 qSPI_SCLK GND U1C1_SCLKOUT VSS GND CPU_45A-V3 Pin Satellite Connector Function CPU_45A-V3 XMC Function 2.11.1 P0.13 XMC Pin CPU_45A-V3 CPU Board XMC4500 General Purpose Hardware Description COM Connector The COM satellite connector on the CPU_45A-V3 board allows interface expansion through COM satellite cards (e.g. COM_ETH-V1) Figure 23 Satellite Connector Type COM (3) This pin is connected with the satellite connector via an analog switch Revision 1.0, 2014-01-10 Board User's Manual 25 nc nc nc nc P2.10 U0C1_SELO0 nc nc U0C1_SELO1 U0C1_SELO0 U0C1_SELO3 U1C0_DX0D/DOUT0 P15.5 Input P5.6 AGND VADC_G1CH1 VADC_G0CH6 VADC_G1CH4 VADC_G3CH5 VADC_G3CH4 nc nc nc nc nc nc nc nc nc nc nc nc P2.10 P3.1 nc nc P3.12 P3.1 P3.8 P2.14 P15.5 P5.6 VAGND P14.9 P14.6 P14.12 P15.13 P15.12 nc nc nc nc nc nc nc nc GND GND VSS VSS nc nc LEDTS0_COL1 nc nc GND COLA COL0 COL1 COL2 COL3 TPx0 TPx1 RSVD RSVD RSVD ADC19 ADC17 ADC15 ADC3/ORC0 DAC1/ADC1 AGND VDD5 VDD5 SPI_CSH2 SPI_CSH1 SPI_CSH0 I2S_SYNCLK I2S_MCLK I2S_WA AudioRST RSVD RSVD RSVD MMC_nSDCD MMC_BUSPOW MMC_DATA7 MMC_DATA5 MMC_DATA3 MMC_DATA1 VSS MMC_DATA2_OUT nc nc MMC_CMD_OUT GND nc nc nc P5.11 U0C1_DOUT0 U0C1_DX0B U0C1_SCLKOUT U0C1_DOUT0 MMC_DATA2 MMC_DATA4 MMC_DATA6 MMC_CMD MMC_LED MMC_SDWC RSVD RSVD OLED_CMD I2S_MTSR I2S_MRST I2S_SCLK SPI_MTSR HMI P3.5 MMC_DATA0_OUT MMC_DATA0 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 LEDTS0_COLA HMI_GPIO0 MMC_DATA3_OUT P4.1 6 5 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 HMI RESET GND TP0 TP1 TP2 TP3 TP4 TP5 TP6 TP7 RSVD RSVD ADC18 ADC16 ADC14 ADC2/DACREF DAC0/ADC0 AREF VDD5 GND nc nc LEDTS0_TSIN2A nc nc nc nc LEDTS0_TSIN7A nc nc VADC_G2CH2 VADC_G2CH3 VADC_G0CH3 VADC_G0CH4 VADC_G1CH0 VAREF P0.6 RESET# GPIO VDD5 P5.8 P0.6 I2C_SCL VSS nc nc P2.4 nc nc nc nc P5.10 nc nc P15.2 P15.3 P14.3 P14.4 P14.8 VAREF PORST P3.0 U1C0_SCLKOUT SPI_SCLK P2.5 U0C1_DX0B U0C1_SCLKOUT SPI_MRST P3.13 P3.0 P2.5 P3.13 P5.11 nc nc nc nc nc P1.7 P4.0 P0.11 GND MMC_nRST GND MMC_nRST VSS XMC Pin 4 3 P5.7 HMI_GPIO1 MMC_DATA1_OUT P1.6 MMC_CLK HMI XMC Function Function 2 1 P0.10 I2C_SDA MMC_CLK_OUT P3.6 GND GND CPU_45A-V3 Pin Satellite Connector VSS Function CPU_45A-V3 XMC Function 2.11.2 XMC Pin CPU_45A-V3 CPU Board XMC4500 General Purpose Hardware Description HMI Connector The HMI satellite connector on the CPU_45A-V3 board allows interface expansion through HMI satellite cards. Figure 24 Satellite Connector Type HMI Revision 1.0, 2014-01-10 Board User's Manual DSDCLK1 RSVD DSD_MCLK3B SPI_CSA2 I2C_SDA ACT_GPIO1 CCU81_IN1B CCU81_IN3B CCU80_IN0A CCU81_IN0A/1A/2A/3A CCU43_IN0C U0C1_SELO2 U0C1_SELO3 nc U1C0_DX0D/DOUT0 P15.4 Input P4.2 AGND VADC_G1CH1 VADC_G0CH6 VADC_G0CH7 VADC_G0CH0 VADC_G2CH1 VADC_G3CH6 VADC_G3CH7 CCU81_OUT00 CCU81_OUT01 CCU81_OUT10 CCU81_OUT11 CCU81_OUT20 CCU81_OUT21 CCU81_OUT31 CCU81_OUT30 GND P5.2 P5.4 P0.7 (1) P5.0 P4.7 P3.11 P3.8 nc P2.14 P15.4 P4.2 26 VAGND P14.9 P14.6 P14.7 P14.0 P14.5 P15.14 P15.15 P1.15 P1.12 P1.14 P1.11 P1.13 P1.10 P6.0 (3) P6.1 (3) VSS GND PWMX3 PWMX2 PWMB2_L PWMB2_H PWMB1_L PWMB1_H PWMB0_L PWMB0_H ADC13 ADC11 ADC9 ADC7 ADC5/ORC2 ADC3/ORC0 DAC1/ADC1 AGND 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 ACT 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 ACT P1.1 P6.4 GND PWMX1 PWMX0 PWMA2_L PWMA2_H PWMA1_L PWMA1_H PWMA0_L PWMA0_H ADC12 ADC10 ADC8 ADC6/ORC3 ADC4/ORC1 ADC2/DACREF DAC0/ADC0 AREF VDD5 GND CCU43OUT3 CCU43OUT2 CCU80_OUT21 CCU80_OUT20 CCU80_OUT11 CCU80_OUT10 CCU80_OUT01 CCU80_OUT00 VADC_G2CH7 VADC_G2CH6 VADC_G0CH2 VADC_G1CH7 VADC_G1CH6 VADC_G0CH4 VADC_G1CH0 VAREF RESET# RESET VDD5 P5.8 P0.6 GPIO VSS P6.2 P6.3 P0.0 P0.3 P0.1 P0.4 P0.2 P0.5 P15.7 P15.6 P14.2 P14.15 P14.14 P14.4 P14.8 VAREF PORST P0.6 P3.0 P2.5 P3.13 U1C0_SCLKOUT U0C1_DOUT0 SPI_MTSR P2.12 I2C_SCL CCU43OUT1 ENA_X U0C1_DX0B CCU43_IN3C ENA_B P4.4 P2.13 U0C1_SCLKOUT CCU43_IN2C ENA_A P4.5 SPI_SCLK CCU43_IN2A CC_IN2 P4.6 SPI_MRST CCU43_IN1A CC_IN1 nc nc CCU43_IN0A RSVD CC_IN0 P1.6 P6.5 (3) DSD_DIN3A DSDIN3 P2.6 P0.8 (2) DSD_DIN1B DSD_DIN0A DSDIN0 P1.2 P1.3 VSS XMC Pin DSD_DIN2A PIF0_IN2A PIF0IN3 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 DSDIN2 PIF0_IN1A PIF0IN2 6 DSDIN1 GND PIF0_IN0A GND PIF0IN1 4 VDD5 VDD5 ACT_GPIO0 SPI_CSA1 SPI_CSA0 TRAP_X TRAP_B TRAP_A CC_IN5 CC_IN4 CC_IN3 nc CCU43_IN3A nc P4.3 DSDCLK0 PWMP PWMN P3.4 DSD_PWMN P1.0 PIF1IN2 PIF1IN1 7 DSD_PWMP nc nc 5 DSD_MCLK2A nc nc PIF1IN0 XMC Function Function 2 ACT 3 P1.7 nc nc GND 1 P5.1 GND CPU_45A-V3 Pin Satellite Connector VSS Function CPU_45A-V3 XMC Function 2.11.3 XMC Pin CPU_45A-V3 CPU Board XMC4500 General Purpose Hardware Description ACT Satellite Connector The ACT satellite connector on the CPU_45A-V3 board allows interface expansion through ACT satellite cards. Figure 25 Satellite Connector Type ACT (1) P0.7 can also be used for JTAG Debugging (TDI) (2) P0.8 is used as TRST in order to enable JTAG Debug (3) This pin is connected with the satellite connector via an analog switch Revision 1.0, 2014-01-10 CPU_45A-V3 CPU Board XMC4500 General Purpose Differences to Board Version V2 3 Differences to Board Version V2 Table 11 Differences to older board versions Topic of Change Description Debugger An on-board debugger has been added. The debugger has an USB interface (X500). An external debugger can still be used via X400 / X401. A user button as been added. The user button is connected to P2.15. In V2 versions P2.15 was connected to P2.14. User Push Button I2C Connection The SDA signal of the I2C is connected to P2.14 only. In V2 versions the SDA signal was connected to P2.14 and P2.15. USB Shielding The USB shield has been connected to ground through a 1 MOhm resistor and a 100 nF capacitor 4 Production Data 4.1 Schematics This chapter contains the schematics for the CPU board: Schematic of Satellite Connectors, USB-OTG Schematic of XMC4500 Schematic of Power Supply, Debug Connectors, Reset Circuit Schematic of On-board Debugger The board has been designed with Eagle. The PCB design data of this board can be downloaded from www.infineon.com/xmc-dev. Board User's Manual 27 Revision 1.0, 2014-01-10 A B L201 BLM18PG600 1 GND GND GND 100nF/0402 C200 1 2 3 4 5 X203C USB-OTG Connector X203S GND 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 COM 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 GND HSEC8_MATING-CARD 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 X200 P1.9 P1.8 P3.13 P2.5 P3.0 P5.8 P0.6 RESET# P2.9 P2.8 P15.9 P5.3 P15.8 P3.15 P3.14 P0.15 P0.14 3 GND GND 2 V201 ESD8V0L2B-03L OTG_FS_DM OTG_FS_DP P0.9 R202 33R/0402 R203 33R/0402 GND 3 SJ5 2 P14.9 P14.6 P14.7 P14.0 P14.5 P15.14 P15.15 P1.15 P1.12 P1.14 P1.11 P1.13 P1.10 CCU81_OUT31 CCU81_OUT30 P2.14 P15.4 P4.2 P4.3 P5.2 P5.4 P0.7 P5.0 P4.7 P3.11 P3.8 1 P1.0 P5.1 P1.7 P3.4 VDD5 AGND 4 4 GND 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 VDD5 ACT GND GND GND VAREF P14.8 P14.4 P14.14 P14.15 P14.2 P15.6 P15.7 P0.5 P0.2 P0.4 P0.1 P0.3 P0.0 P6.3 P6.2 P4.6 P4.5 P4.4 P2.13 P2.12 P6.4 P3.13 P2.5 P3.0 P5.8 P0.6 RESET# P1.3 P1.2 P1.1 P0.8 P2.6 P1.6 DSD_DIN3A P0.10 P5.7 P14.9 P14.6 P14.12 P15.13 P15.12 P3.12 P3.1 1 P3.8 P2.14 P15.5 P5.6 2 SJ6 1 2 SJ7 P2.10 P3.1 I2S_WA MMC_BUSPOW P3.6 P1.6 P4.1 6 GND 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 5 6 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 7 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 VDD5 HMI GND 7 GND HSEC8_MATING-CARD 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 X202 The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights of any third party. Legal Disclaimer HSEC8_MATING-CARD 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 X201 5 VDD5 AGND 2 VDD5 VDD5 P0.[0..15],P1.[0..15],P2.[0..15],P3.[0..15],P4.[0..7],P5.[0..11],P6.[0..6],P14.[0..15],P15.[2..15] ZX62-AB-5PA 100nF/0402 C 1M/0402 100nF/0402 D SJ3 2 P3.10 COM_RXD COM_TXD P5.5 1 2 P3.1 SJ4 P2.14 P14.13 P3.7 P2.3 P2.2 P2.0 P2.7 P5.9 1 2 100nF/0402 P0.13 P0.12 P3.3 R200 VDD5USB 1 D1 VDD5 C201 VDD3.3 R204 100nF/0402 E 3 D2 10k/0402 VDD5 C202 VDD5 C205 VDD5 C206 VDD5 C209 VDD5 GND C210 28 100nF/0402 Board User's Manual 100nF/0402 1 I2S_MTSR I2S_MRST I2S_SCLK Sheet: 2/5 8 05.11.2013 09:55:58 CPU_45A-V3-2 Satellite Conn., USB-OTG V3 / 01.02.2012 / Ma P2.4 P5.10 VAREF P14.8 P14.4 P14.3 P15.3 P15.2 P5.11 P3.13 P2.5 P3.0 P3.13 P2.5 P3.0 P5.8 P0.6 RESET# P3.5 MMC_LED P0.11 P4.0 P1.7 8 A B C D E CPU_45A-V3 CPU Board XMC4500 General Purpose Production Data Figure 26 Schematic of Satellite Connectors, USB-OTG Revision 1.0, 2014-01-10 A B C VDD3.3 R310 VDD3.3 P0.15 Jumper closed with a cutable trace on bottom layer VDD3.3 GND PS + - 1 VDD3.3 U302 VCC CS# CLK DI DO HOLD# (IO3) (IO0) (IO1) WP# (IO2) GND GND GND GND 2k2/0603 N25Q032A13ESE40 3 4 2k2/0603 R307 qSPI FLASH R306 10k/0402 GND GND GND 100nF/0402 P3.3 P0.13 P3.15 P3.14 1 6 5 2 C321 P0.14 7 8 P5.8 P2.14 P3.9 GND 2 117 118 119 120 121 122 123 124 126 86 62 18 15 16 17 125 90 61 VDDC 19 OTG_FS_DM OTG_FS_DP 20 21 24 P14.1531 P14.1432 P14.1333 P14.1234 P14.9 51 P14.8 52 P14.7 35 P14.6 36 P14.5 37 P14.4 38 P14.3 39 P14.2 40 P14.1 41 P14.0 42 P6.6 95 P6.5 96 P6.4 97 P6.3 98 P6.2 99 P6.1 100 P6.0 101 P4.7 P4.6 P4.5 P4.4 P4.3 P4.2 P4.1 P4.0 P1.15 94 P1.14102 P1.13103 P1.12104 P1.11105 P1.10106 P1.9 113 P1.8 114 P1.7 115 P1.6 116 P1.5 107 P1.4 108 P1.3 109 P1.2 110 P1.1 111 P1.0 112 HIB_IO_1 HIB_IO_0 100nF/0402 C300 3 10uF/10V/0805 P14.1 100nF/0402 C301 VDDP 1 JP300 2 C323 S 100nF/0402 C302 D 10uF/10V/0805 E A 10uF/10V/0805 CPU 100nF/0402 C303 680R/0603 10uF/10V/0805 AGND VDD3.3 VDD3.3 R309 100nF/0402 C304 LED1 LED-GE/D/0603 V300 R301 C325 10k/0402 R303 R300 POTI/10K/VERT C326 10k/0402 100nF/0402 C305 E VBAT 100nF/0402 C306 Hitex PowerScale C324 P0.[0..15],P1.[0..15],P2.[0..15],P3.[0..15],P4.[0..7],P5.[0..11],P6.[0..6],P14.[0..15],P15.[2..15] 100nF/0402 C307 GND 3 VDDC3 VDDC2 VDDC1 VDDC VDDP3 VDDP2 VDDP1 VDDP Analog Digital VSSO VSS EPAD PORST# TCK TMS XTAL1 XTAL2 RTC_XTAL_1 RTC_XTAL_2 VAREF VAGND VDDA VSSA P15.15 P15.14 P15.13 P15.12 P15.9 P15.8 P15.7 P15.6 P15.5 P15.4 P15.3 P15.2 P5.11 P5.10 P5.9 P5.8 P5.7 P5.6 P5.5 P5.4 P5.3 P5.2 P5.1 P5.0 P2.15 P2.14 P2.13 P2.12 P2.11 P2.10 P2.9 P2.8 P2.7 P2.6 P2.5 P2.4 P2.3 P2.2 P2.1 P2.0 P3.15 P3.14 P3.13 P3.12 P3.11 P3.10 P3.9 P3.8 P3.7 P3.6 P3.5 P3.4 P3.3 P3.2 P3.1 P3.0 XMC4500_LQFP144 Supply Hibernate/RTC USB_DUSB USB_D+ VBUS HIB_IO_1 HIB_IO_0 VBAT P14.15 P14.14 P14.13 P14.12 P14.9 P14.8 P14.7 P14.6 P14.5 P14.4 P14.3 P14.2 P14.1 P14.0 P6.6 P6.5 P6.4 P6.3 P6.2 P6.1 P6.0 P4.7 P4.6 P4.5 P4.4 P4.3 P4.2 P4.1 P4.0 P1.15 P1.14 P1.13 P1.12 P1.11 P1.10 P1.9 P1.8 P1.7 P1.6 P1.5 P1.4 P1.3 P1.2 P1.1 P1.0 P0.15 P0.14 P0.13 P0.12 P0.11 P0.10 P0.9 P0.8 P0.7 P0.6 P0.5 P0.4 P0.3 P0.2 P0.1 P0.0 U300 4 89 85 EXP 91 93 92 87 88 22 23 46 45 48 47 43 44 49 50 53 54 25 26 27 28 29 30 55 56 57 58 77 78 79 80 81 82 83 84 59 60 63 64 65 66 67 68 75 76 69 70 71 72 73 74 133 134 8 9 10 11 12 13 14 129 130 131 132 5 6 7 4 GND 5 Boot Options GND C311 2 4 2 P6.5 P6.1 2 P6.0 2 4 2 4 4 DBGPRES# A VCC GND A VCC GND A A VCC GND A VCC GND 7 74LVC1G66DCK B EN U305 74LVC1G66DCK B EN U304 74LVC1G66DCK B EN U303 VCC GND 74LVC1G66DCK B EN U306 74LVC1G66DCK B Trace Signal / ACT Board Switch P1.5 P1.4 EN U301 1 5 3 1 5 3 1 5 3 1 5 3 1 5 3 GND GND GND COM_TXD COM_RXD GND GND GND 5 6 100nF/0402 V3 / 01.02.2012 / Ma DSD_DIN3A CCU81_OUT30 CCU81_OUT31 GND 8 Sheet: 3/5 8 05.11.2013 09:55:58 CPU_45A-V3-2 GND 4 CAN_TxD COMDIS# CAN_RxD P1.5 USIC_TxD CAN Node1 P1.4 USIC_RxD UART USIC0CH0 COM Board Switch 7 The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights of any third party. AGND CPU GND GND GND Q301 32.768kHz 100nF/0402 100nF/0402 TMS TCK 6 C320 Legal Disclaimer GND 219-02 4 3 BSL OFF ON SW300 C309 1 2 Q302 510R/0603 12MHZ/S/3.2X2.5 VAREF RESET# TCK TMS P0.[0..15],P1.[0..15],P2.[0..15],P3.[0..15],P4.[0..7],P5.[0..11],P6.[0..6],P14.[0..15],P15.[2..15] R313 P15.15 P15.14 P15.13 P15.12 P15.9 P15.8 P15.7 P15.6 P15.5 P15.4 P15.3 P15.2 P5.11 P5.10 P5.9 P5.8 P5.7 P5.6 P5.5 P5.4 P5.3 P5.2 P5.1 P5.0 P2.15 P2.14 P2.13 P2.12 P2.11 P2.10 P2.9 P2.8 P2.7 P2.6 P2.5 P2.4 P2.3 P2.2 P2.1 P2.0 P3.15 P3.14 P3.13 P3.12 P3.11 P3.10 P3.9 P3.8 P3.7 P3.6 P3.5 P3.4 P3.3 P3.2 P3.1 P3.0 100nF/0402 3 L300 Potentiometer, GPIO LED, I2C Pullups 10uF/10V/0805 VDD5USB P0.15135 P0.14136 P0.13137 P0.12138 P0.11139 P0.10 3 4 P0.9 P0.8 127 P0.7 128 P0.6 140 P0.5 141 P0.4 142 P0.3 143 P0.2 144 1 P0.1 2 P0.0 C308 2 AGND 4k7/0402 R302 BLM18PG600 VDD3.3 R304 VDDP BLM18PG600 L301 4k7/0402 C312 15pF/0402 1 2 UART C315 15pF/0402 100nF/0402 100nF/0402 ON CAN C316 15pF/0402 29 C317 15pF/0402 VDD3.3 VDD3.3 C310 C318 C322 C319 Board User's Manual 100nF/0402 1 A B C D E CPU_45A-V3 CPU Board XMC4500 General Purpose Production Data Figure 27 Schematic of XMC4500 Revision 1.0, 2014-01-10 A B C D 1 P3.2 USB-OTG Supply GND C411 2 C1 C3 C5 C7 C9 X401 S2*10/1.27SO 2 4 6 8 10 12 14 16 18 20 C2 C4 C6 C8 C10 D2 D4 D6 A V400 5 4 VIN EN VOUT FAULT# U403 TPS2051BDBV BAS3010A-03W C XE3K_DM2+CTX FLE-103-01-G-DV D1 D3 D5 FTSH-105-01-L-DV-K GND GND 100uF/T/10V/C Ext. device pulls signal to GND and disconnects UART/CAN signals from COM connector COMDIS# DBG2PRES# Debugger pulls signal to GND and keeps the On-board Debugger in reset state GND 100nF/0402 C401 1 3 5 7 9 11 13 15 17 19 GND 1 3 VDD5USB GND 3 4u7F/0805 C412 P1.4 P1.5 HIB_IO_0 4 Push Button P2.15 CAN_TxD CAN Node1 TRACECLK TRACED[0] TRACED[1] TRACED[2] TRACED[3] CAN_RxD UART USIC0CH0 RESET# P6.0 P6.6 P6.5 P2.11 P6.1 TDO/SWO TDI TRST P1.5 USIC_TxD 33R/0402 33R/0402 33R/0402 33R/0402 33R/0402 R421 R423 R424 R425 R426 P0.8 TMS TCK P2.1 P0.7 P1.4 USIC_RxD no ass./4k7/0402 33R/0402 33R/0402 33R/0402 no ass./33R/0402 R427 R402 R403 R404 R410 P P1 S S1 3 RESET# Power LED and Testpoints Reset GND GND OUT BYP EXP SENSE/ADJ IFX1763_PADNOP GND GND GND EN IN 7 GND 10k/0402 S S1 GND GND GND Q404 BC858C GND GND V3 / 01.02.2012 / Ma GND 5 6 Sheet: 4/5 8 05.11.2013 09:55:58 Power, Debug, Reset GND GND GND R422 0R/0603 R416 SW400 TMPS2-SMD 10nF/0402 C415 P P1 GND 4 9 2 1 8 CPU_45A-V3-2 X402 BK-885 Battery Holder GND 3 6 7 5 8 U401 7 The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights of any third party. GND 1 GND 10k/0402 R414 R415 R413 Legal Disclaimer GND 100nF/0402 C416 BUTTON1 SW401 TMPS2-SMD GND 100uF/T/10V/C C414 RTC Battery HIB_IO_1 BAV70 VDD5 270k/0402 no ass./10k/0402 X400 VDD5 C405 10uF/10V/0805 VDD3.3 R400 VDD3.3 R408 GNDGND 10k/0402 VDD3.3 10k/0402 R401 1 2 VDD3.3 Supply VDD3.3 DBGPRES# VDD3.3 10k/0402 VDD5 C A VDD5 V408 V404 V405 VDD3.3 BAT54-02V BAT54-02V 10k/0402 Debugger pulls signal to GND, disconnects trace signals C400 from ACT connector and keeps the On-board 100nF/0402 Debugger in reset state VDD3.3 R411 R428 V406 VDD3.3 + + 6 1 E no ass./10k/0402 10k/0402 10k/0402 2 1 VDD3.3 R412 VDD3.3 R429 VBAT 2 2+ 1+ - VDD3.3 C406 Debug Connectors GND 2 1 5 TP404 4 TP405 3 no ass. 10k/0402 680R/0603 V403 LED-GN/D/0603 TP406 10nF/0402 C407 10uF/10V/0805 1k5/0603 V401 LED-GN/D/0603 TP407 2 1 R419 VDD3.3 no ass. R407 R417 VDD5 VDD3.3 R420 1 no ass./0R/0603 no ass. R405 VDD3.3 C413 100nF/0402 2k2/0603 V407 LED-RT/D/0603 VDD5USB 30 no ass. R406 Board User's Manual 1k5/0603 V402 LED-GN/D/0603 1 A B C D E CPU_45A-V3 CPU Board XMC4500 General Purpose Production Data Figure 28 Schematic of Power Supply, Debug Connectors, Reset Circuit Revision 1.0, 2014-01-10 BAS3010A-03W A B C D 1 3 DBG2PRES# GND 2Y 1Y NC7WZ07P6X 2A 1A VCC 100nF/0402 C511 1 DBGPRES# GND RESET# GPIO-P0.3 DEBUG_LED# GPIO-P0.2 RESET# DEBUG_LED# U501 U1C0 DX0A-P0.4 DOUT0-P0.5 GPIO-P0.6 RXD TXD EN# 5 U1C1 DX0D-P0.0 UART2 (DM2) RXD TXD TXACTIVE# SWV 4 6 2 GND U0C1 DX2A-P2.3 DX1A-P2.4 DOUT0-P2.5 DX0A-P2.2 SPI Slave CS_IN CLK_IN MISO MOSI UART RXD TDI TDO 2 GND GND GND no ass./10nF/0402 C503 C502 VDD3.3 3 WPORST# WTCK WTMS 32 34 33 29 30 8 9 18 17 21 22 23 24 25 26 GND VSS EPAD PORST# TCK TMS XTAL1 XTAL2 RTC_XTAL_1 RTC_XTAL_2 VAREF VAGND P2.5 P2.4 P2.3 P2.2 P2.1 P2.0 Analog Digital 4 Supply HIB_IO_0 VBAT P14.9 P14.8 P14.7 P14.6 P14.5 P14.4 P14.3 P14.0 P1.5 P1.4 P1.3 P1.2 P1.1 P1.0 P0.8 P0.7 P0.6 P0.5 P0.4 P0.3 P0.2 P0.1 P0.0 VDDC1 VDDC VDDP2 VDDP1 VDDP USB_DUSB USB_D+ Hibernate/RTC XMC4200_QFN48 no ass. 1 2 3 4 X501 27 EPAD GND 510R/0603 100nF/0402 P0.7 TCK CS P2.1 Q500 R500 12MHZ/S/3.2X2.5 TDO TDI U500 31 6 41 28 5 3 4 7 10 19 20 11 12 13 14 15 16 35 36 37 38 39 40 42 43 44 45 46 47 48 1 2 R501 R502 VDD3.3 R504 L500 BLM18PG600 GND GND GND 100nF/0402 C512 X500S 7 V3-2 / 05.11.2013 / Ma 5 6 Sheet: 5/5 8 05.11.2013 09:55:58 CPU_45A-V3-2 GND 1 2 3 4 5 X500C The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights of any third party. GND 8 Configure COMDIS# as open-drain output Configure Debugger-P0.5 as USIC_Tx but only active while X-spy function is selected Configure Debugger-P0.4 as USIC_Rx but only active while X-spy function is selected Configure Debugger-P0.3 as RESET# detect input but with additional open-drain output capabilities 7 On-board Debugger GND TCK TMS SWV EN# TXD RXD 1 Legal Disclaimer GND 33R/0402 33R/0402 TCK CS TMS P2.1 COMDIS# P1.4 P1.5 RESET# DEBUG_LED# C505 100nF/0402 R508 no ass./33R/0402 C507 100nF/0402 U0C0 DX0B-P1.4 DOUT0-P1.5 SCLKOUT-P1.1 SELO0-P1.0 C508 100nF/0402 SPI Master MISO MOSI CLK_OUT CS_OUT C506 4u7F/0805 VDD3.3 C510 10uF/10V/0805 TMS TCK C509 100nF/0402 C A VDD5 V501 R506 R507 BAS3010A-03W 4k7/0402 10k/0402 E VDD3.3 V502 680R/0603 LED-GN/D/0603 V500 On-board Debugger C500 15pF/0402 6 2 D2 5 3 D1 4 ESD8V0L2B-03L 3 R505 On-board Debugger Concept 2 C501 15pF/0402 VDD3.3 R503 31 10k/0402 1M/0402 Board User's Manual ZX62-AB-5PA 1 A B C D E CPU_45A-V3 CPU Board XMC4500 General Purpose Production Data Figure 29 Schematic of On-board Debugger Revision 1.0, 2014-01-10 C504 100nF/0402 CPU_45A-V3 CPU Board XMC4500 General Purpose Production Data 4.2 Component Placement and Geometry R506 U305 R501 R502 1 2 C505 3 Q 500 C 509 X 501 Q 302 C500 4 C 502 C501 S J5 C 305 93.57 C 205 C 206 C 312 C 324 R 313 C 301 R 404 R 410 V 405 U 301U 306 R402 R403 E FL C 303 C 307 C 316 R 401 37.50 C 310 Q 301 C 323 C 317 C 322 C 401 C 400 20.99 R 426 R 425 R 424 R 423 R 421 V 404 C318 U303 R 419 R 400 Q 404 TP 404 TP 405 TP 406 R422 X 401 SH FT C 415 C 302 C 326 C 306 C 308 C 309 L300 L301 C 311 V4 03 R4 V4 07 01 R4 V4 05 02 R4 06 TP 407 S W 400 R 420 V 407 A D J _3 V 406 C 414 X4 02 2 R 309 R 302 R 304 U304 R 310 C319 U 300 R307 R306 C416 R429 R505 C512 V300 R301 C412 C406 R416 C 320 R 500 R 508 C 315 R 42 7 PS C 30 C 0 30 4 44 2 X2 00 U 500 C 506 S J3 U 302 R 507 ON 75.00 S W 401 C 508 80 R 303 1 81.03 R 411 R 204 U 501 C 507 C 504 - J P 300 C 321 0 30 SW U403 46 + C 510 46 A C 413 S J4 R 504 C 503 R 503 C 325 C 511 R 408 C 407 C 405 C 202 V 500 L500 V 501 V 502 44 R 417 U 401 01 X2 V 408 R 412 R 414 C 201 R 413 R 415 A D J _2 X 500 X 203 V 201 R 203 R 202 C 411 L201 R 200 R 428 C 200 V 400 2 80 All dimensions in mm R 300 X 400 14.70 17.82 2.4 21.03 A D J _1 C 209 C 210 S J 7 S J6 X 202 25.08 80 46 44 2 86.60 Figure 30 Component Placement and Geometry Board User's Manual 32 Revision 1.0, 2014-01-10 CPU_45A-V3 CPU Board XMC4500 General Purpose Production Data 4.3 Bill of Material (BOM) Table 12 BOM of CPU_45A-V3 Board Pos. Qty Value No. Device Reference Des. 1 1 0R/0603 R416 2 2 1M/0402 Resistor Resistor R405, R406 R200, R505 2 1k5/0603 Resistor 4 3 2k2/0603 Resistor R306, R307, R420 5 3 4k7/0402 Resistor R302, R304, R506 6 1 4u7F/0805 Capacitor, ceramic 10% X7R 7 15 10k/0402 Resistor C412, C506 R204, R303, R309, R310, R400, R401, R408, R412, R414, R419, R422, R428, R429, R503, R507 8 2 10nF/0402 Capacitor 9 9 10uF/10V/0805 Capacitor ceramic 10 2 12MHZ/S/3.2X2.5 Crystal, NX3225GD, NDK 11 6 15pF/0402 Capacitor, ceramic 10% NP0 12 1 32.768kHz Crystal, NX3215SA, NDK 13 12 33R/0402 Resistor 14 5 74LVC1G66DCK IC, Single Analog Switch 15 35 100nF/0402 Capacitor U301, U303, U304, U305, U306 C200, C201, C202, C205, C206, C209, C210, C300, C301, C302, C303, C304, C305, C306, C307, C309, C310, C311, C318, C319, C320, C321, C322, C400, C401, C413, C416, C502, C504, C505, C507, C508, C509, C511, C512 16 2 100uF/T/10V/C Capacitor, bipolar C411, C414 17 1 219-02 SW300 18 3 C406, C415 C308, C323, C324, C325, C326, C405, C407, C510 Q302, Q500 C312, C315, C316, C317, C500, C501 Q301 R202, R203, R402, R403, R404, R421, R423, R424, R425, R426, R501, R502 1 270k/0402 Dual DIP-Switch, 0.1" SMD Resistor 19 2 510R/0603 Resistor R313, R500 20 3 680R/0603 Resistor R301, R407, R504 21 3 BAS3010A-03W Diode, SOD323, Infineon V400, V408, V501 22 2 BAT54-02V Diode, SC79, Infineon V404, V405 23 1 BAV70 Diode, SOT23-3, Infineon V406 24 1 BC858C Transistor, SOT23-3, Infineon Q404 25 1 BK-885 Battery Holder, 12mm Coin Cell X402 26 4 BLM18PG600 Ferrite Bead, 0603, Murata L201, L300, L301, L500 27 2 ESD8V0L2B-03L Diode, TSLP-3-1, Infineon V201, V500 28 3 FIDUCIAL FIDUCIAL ADJ_1, ADJ_2, ADJ_3 29 3 HSEC8_MATING-CARD 30 1 IFX1763_PADNOP Connector, 80-pin Edgecard, Samtec X200, X201, X202 Voltage Regulator, 3.3V LDO, Infineon U401 31 1 LED-GE/D/0603 LED, yellow Board User's Manual R415 V300 33 Revision 1.0, 2014-01-10 CPU_45A-V3 CPU Board XMC4500 General Purpose Production Data Table 12 BOM of CPU_45A-V3 Board Pos. Qty Value No. Device Reference Des. 32 4 LED-GN/D/0603 LED, green V401, V402, V403, V502 33 1 LED-RT/D/0603 LED, red V407 34 1 NC7WZ07P6X NC7WZ07_2P6X U501 35 1 POTI/10K/VERT 36 1 S2*10/1.27SO Potentiometer, K09K1130A8G, ALPS R300 Connector, FTSH-110-01-L-DVK-P, Samtec X400 37 1 N25Q032A13ESE40 IC, Serial SPI Flash, 32Mb U302 38 2 TMPS2-SMD Switch, tactile SW400, SW401 39 1 TPS2051BDBV U403 40 1 XE3K_DM2+CTX IC, Power Switch Connector, FTSH-105-01-LM-DVK, without pin 7, Samtec Connector, FLE-103-01-G-DV, Samtec 41 1 XMC4200_QFN48 IC, XMC4200, QFN48, Infineon U500 42 1 XMC4500_LQFP144 IC, XMC4500, LQFP144, Infineon U300 43 2 ZX62-AB-5PA Connector, Micro-USB, Hirose X203, X500 44 1 no ass. Pinheader, 4-pin, 0.1" TH X501 45 4 no ass. 1 no ass./0R/0603 1 no ass./4k7/0402 Pinheader, 1-pin, 0.1" TH Resistor Resistor TP404, TP405, TP406, TP407 46 47 48 2 no ass./10k/0402 Resistor R411, R413 1 no ass./10nF/0402 Resistor C503 2 no ass./33R/0402 Resistor R410, R508 51 1 no ass. Pinheader, 3-pin, 0.1" TH, Hitex PowerScale JP300 52 5 0R/0402 Solder Jumper (0 Ohm) SJ3, SJ4, SJ5, SJ6, SJ7 49 50 Board User's Manual 34 X401 R417 R427 Revision 1.0, 2014-01-10 w w w . i n f i n e o n . c o m Published by Infineon Technologies AG