AK4127VF

[AKD4127-A]
AKD4127-A
AK4127 Evaluation Board Rev.0
GENERAL DESCRIPTION
The AKD4127-A is an evaluation board for AK4127, the digital sample rate converter. The AKD4127-A
has the digital audio interface and can achieve the interface with digital audio system via opt-connector.
Ordering guide
AKD4127-A
---
AK4127 Evaluation Board
FUNCTION
• DIR/DIT with optical input/output
• 10pin Header for AKM AD/DA evaluation board
5V
Opt In
GND
AK4114
AK4114
Opt Out
Regulator
COAX
10pin
Header
COAX
AK4127
10pin
Header
DSP
Data
DSP
Data
Figure 1. AKD4127-A Block Diagram
* Circuit diagram and PCB layout are attached at the end of this manual.
[KM085601]
2006/11
-1-
[AKD4127-A]
Operation sequence
1) Set up the power supply lines.
[VCC]
(Red)
= +5V (for regulator)
[DGND]
(Black)
= 0V
Each supply line should be distributed from the power supply unit.
The regulator can be supplied 3.3V to all circuits.
2) Set up the evaluation mode, jumper pins. (See the followings.)
3) Power on.
The AK4127 should be reset once bringing SW1 (PDN) “L” upon power-up.
Evaluation mode
(1) Setting for Input port
(1) When using DIR function of AK4114 (U3)
When using PORT1 (DIR) or J1 (COAX), nothing should be connected to PORT2 (INPUT).
JP2
IBICK
JP3
SDTI
JP4
ILRCK
• SW3 setting (See Table 1)
Upper-side is “H” and lower-side is “L”.
The audio interface format of the AK4114 is fixed to 24bit, MSB justified. IDIF2-0 and PLL2-0 of SW3
should be used by default setting.
SW3 No.
1
2
3
4
5
6
7
Name
DITH
PLL2
PLL1
PLL0
IDIF0
IDIF1
IDIF2
ON (“H”)
Dither ON
OFF (“L”)
Dither OFF
PLL Mode Setting
Fixed to default
AK4127 Audio I/F Format Setting
Fixed to default
Default
L
H
L
H
L
H
L
Table 1. SW3 Setting
[KM085601]
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-2-
[AKD4127-A]
(2) All clocks are fed through the 10pin port
When using PORT2 (INPUT), nothing should be connected to J1 (COAX) and PORT1 (DIR).
JP2
IBICK
JP3
SDTI
JP4
ILRCK
• SW3 setting (See Table 2)
Upper-side is “H” and lower-side is “L”.
SW3 No.
1
2
3
4
5
6
7
Name
DITH
PLL2
PLL1
PLL0
IDIF0
IDIF1
IDIF2
ON (“H”)
Dither ON
OFF (“L”)
Dither OFF
PLL Mode Setting
Refer to Table 3
AK4127 Audio I/F Format Setting
Refer to Table 4
Default
L
H
L
H
L
H
L
Table 2. SW3 Setting
Mode
PLL2
PLL1
PLL0
ILRCK Freq
IBICK Freq
IMCLK
0
L
L
L
1
L
L
H
8k ∼ 96kHz
8k ∼ 216kHz
16k ∼ 216kHz
(Note 1)
Depending on
IDIF2-0
Not
needed.
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Master / Slave
Slave
IMCLK = DVSS
IBICK = Input
ILRCK = Input
Master
IMCLK = Input
IBICK = Output
ILRCK = Output
L
L
H
H
H
H
L
L
L
L
H
H
H
H
H
L
H
H
Reserved
L
L
32fsi (Note 3)
L
H
64fsi
Not
8k ∼ 216kHz
needed.
(Note 2)
H
L
128fsi
H
H
64fsi
L
L
128fs
8k ∼ 216kHz
L
H
256fs
8k ∼ 108kHz
H
L
512fs
8k ∼ 54kHz
H
H
128fs
8k ∼ 216kHz
64fs
L
L
192fs
8k ∼ 216kHz
L
H
384fs
8k ∼ 108kHz
H
L
768fs
8k ∼ 54kHz
H
H
192fs
8k ∼ 216kHz
Table 3. PLL Setting (Input PORT)
SMUTE
(Note 4)
Manual
Semi-Auto
Manual
Semi-Auto
Manual
Semi-Auto
Manual
Semi-Auto
Note 1. PLL lock rage is changed by the value of R and C connected FILT pin. Refer to “PLL Loop Filter” in the
datasheet. 470Ω, 0.22μF and 1nF are implemented on the evaluation board.
Note 2. The IBCIK must be continuous except when the clocks are changed.
Note 3. IBCIK = 32fsi is supported only 16bit LSB justified and I2S Compatible.
Note 4. Refer to “Soft Mute Operation” for Manual mode and Semi-Auto mode in the datasheet.
[KM085601]
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[AKD4127-A]
Mode
0
1
2
IDIF2
L
L
L
IDIF1
L
L
H
IDIF0
L
H
L
SDTI Format
16bit, LSB justified
20bit, LSB justified
24/20bit, MSB justified
3
L
H
H
24/16bit, I2S Compatible
4
5
6
7
H
H
H
H
L
L
H
H
L
H
L
H
24bit, LSB justified
24bit, MSB justified
24bit, I2S Compatible
ILRCK
IBICK
Input
Input
Output
Output
IBICK Freq
≥ 32fsi
≥ 40fsi
≥ 48fsi
≥ 48fsi or
32fsi
≥ 48fsi
64fs
64fs
Master / Slave
Slave
Master
Reserved
Table 4. Input Audio Interface Format (Input PORT)
(2) Setting for Output port
(1) When using DIT function of AK4114 (U4)
When using PORT4 (DIT) or J2 (TX), nothing should be connected to PORT3 (OUTPUT). When BICK and
LRCK frequencies are changed, the value of X’tal (X1) frequency should be changed.
JP6
OBICK
JP7
OLRCK
• SW4 setting (See Table 5)
Upper-side is “H” and lower-side is “L”.
The audio interface format of the AK4114 is fixed to 24bit, MSB justified. ODIF2-0, CMODE2-0 and
OBIT1-0 of SW3 should be used by default setting.
SW4 No.
1
2
3
4
5
6
7
Name
ODIF1
ODIF0
CMODE2
CMODE1
CMODE0
OBIT1
OBIT0
ON (“H”)
OFF (“L”)
AK4127 Output Audio I/F Format Setting
Fixed to default
AK4127 Mode Setting
Fixed to default
AK4127 Output bit Length Setting
Fixed to default
Table 5. SW4 Setting
[KM085601]
Default
H
L
H
L
L
H
H
2006/11
-4-
[AKD4127-A]
(2) All clocks are fed through the 10pin port
When using PORT3 (OUTPUT), nothing should be connected to J2 (TX) and PORT4 (DIT).
JP6
OBICK
JP7
OLRCK
• SW4 setting (See Table 6)
Upper-side is “H” and lower-side is “L”.
SW4 No.
1
2
3
4
5
6
7
Name
ODIF1
ODIF0
CMODE2
CMODE1
CMODE0
OBIT1
OBIT0
ON (“H”)
OFF (“L”)
AK4127 Output Audio I/F Format Setting
Refer to Table 7
AK4127 Mode Setting
Refer to Table 8
AK4127 Output bit Length Setting
Refer to Table 9
Table 6. SW4 Setting
Default
H
L
H
L
L
H
H
Mode
ODIF1
ODIF0
SDTO Format
0
L
L
LSB justified
1
L
H
(Reserved)
2
H
L
MSB justified
3
H
H
I2S Compatible
Table 7. Output Audio Interface Format 1 (Output PORT)
Mode
0
1
2
3
4
5
6
7
CMODE2
L
L
L
L
H
H
H
H
CMODE1 CMODE0
Master / Slave
OMCLK
L
L
Master
256fso
L
H
Master
384fso
H
L
Master
512fso
H
H
Master
768fso
L
L
Slave
Not used. Set to DVSS.
L
H
Master
128fso
H
L
Master
192fso
H
H
Master (Bypass) Not used. Set to DVSS.
Table 8. Master/Slave Control (Output PORT)
fso
8k ∼ 108kHz
8k ∼ 108kHz
8k ∼ 54kHz
8k ∼ 54kHz
8k ∼ 216kHz
8k ∼ 216kHz
8k ∼ 216kHz
8k ∼ 216kHz
Mode
OBIT1
OBIT0
SDTO Output
0
L
L
16bit
1
L
H
18bit
2
H
L
20bit
3
H
H
24bit
Table 9. Output Audio Interface Format 2 (Output PORT)
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[AKD4127-A]
Other jumper pins set up
1. JP1 (RX) : Select of RX input
COAX: COAX input.
RX:
Optical input. <Default>
2. JP5 (CKSO) : AK4114 BICK and LRCK setting
H: BICK: 2.048MHz ∼ 12.288MHz, LRCK: 32kHz ∼ 192kHz
L: BICK: 2.048MHz ∼ 6.144MHz, LRCK: 32kHz ∼ 96kHz <Default>
When BICK and LRCK frequencies are changed, the value of X’tal (X1) frequency should be changed.
3. JP8 (TX) : Select of TX output
BNC: BNC connector (J2) output.
OPT: Optical (PORT4) output. <Default>
The function of the toggle SW
Upper-side is “H” and lower-side is “L”.
[SW1] (PDN): Resets the AK4127 and the AK4114. Keep “H” during normal operation.
The AK4127 and the AK4114 should be resets once bringing “L” upon power-up.
[SW2] (SMUTE): Soft mute of AK4127
Indication for LED
[LED1] (UNLOCK): Monitor UNLOCK pin of the AK4127. LED turns on when unlock occurs.
[LED2] (ERF): Monitor INT0 pin of the AK4114 (U3). LED turns on when unlock or parity error occurs.
[KM085601]
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[AKD4127-A]
MEASUREMENT RESULTS
[Measurement condition]
• Measurement unit
• Power Supply
• Band width
• Temperature
: Audio Precision, System Two Cascade
: AVDD = DVDD = 3.3V
: 20Hz ∼ FSO/2
: Room
[Measurement Result]
SRC Characteristics
THD+N
(Input = 1kHz, 0dBFS)
FSO/FSI = 44.1kHz/48kHz
FSO/FSI = 48kHz/44.1kHz
FSO/FSI = 48kHz/192kHz
FSO/FSI = 192kHz/48kHz
Worst Case (FSO/FSI = 32kHz/176.4kHz)
Dynamic Range
(Input = 1kHz, −60dBFS)
FSO/FSI = 44.1kHz/48kHz
FSO/FSI = 48kHz/44.1kHz
FSO/FSI = 48kHz/192kHz
FSO/FSI = 192kHz/48kHz
Worst Case (FSO/FSI = 48kHz/32kHz)
Dynamic Range
(Input = 1kHz, −60dBFS, A-weighted)
FSO/FSI = 44.1kHz/48kHz
[KM085601]
SDTO Lcht
SDTO Rch
Unit
130.4
125.0
136.9
124.7
96.1
130.4
125.0
136.9
124.7
96.1
dB
dB
dB
dB
dB
137.3
137.3
137.3
135.6
135.7
137.3
137.3
137.3
135.6
135.7
dB
dB
dB
dB
dB
139.7
139.7
dB
2006/11
-7-
[AKD4127-A]
[Plot]
AK4127 FFT Plot (fsi=48[KHz], fso=44.1[KHz]) AVDD=DVDD=3.3[V], Input Level=0[dBFS], fin=1[KHz]
+0
-10
-20
-30
-40
-50
-60
-70
-80
d
B
F
S
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
-200
20
50
100
200
500
1k
2k
5k
10k
20k
Hz
Fig 6. FFT Plot (Input Level= 0[dBFS])
AK4127 FFT Plot (fsi=48[KHz], fso=44.1[KHz]) AVDD=DVDD=3.3[V], Input Level=-60[dBFS], fin=1[KHz]
+0
-10
-20
-30
-40
-50
-60
-70
-80
d
B
F
S
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
-200
20
50
100
200
500
1k
2k
5k
10k
20k
Hz
Fig 7. FFT Plot (Input Level= −60[dBFS])
[KM085601]
2006/11
-8-
[AKD4127-A]
AK4127 THD+N vs Input Level (fsi=48[KHz], fso=44.1[KHz]) AVDD=DVDD=3.3[V], fin=1[KHz]
-100
-105
-110
-115
-120
-125
-130
d
B
F
S
-135
-140
-145
-150
-155
-160
-165
-170
-175
-180
-140
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
+0
dBFS
Fig 1. THD+N vs. Input Level
AK4127 THD+N vs Input Frequency (fsi=48[KHz], fso=44.1[KHz]) AVDD=DVDD=3.3[V], Input Level=0[dBFS]
-80
-85
-90
-95
-100
-105
-110
d
B
F
S
-115
-120
-125
-130
-135
-140
-145
-150
-155
-160
20
50
100
200
500
1k
2k
5k
10k
20k
Hz
Fig 2. THD+N vs. Input Frequency (Input Level= 0[dBFS])
[KM085601]
2006/11
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[AKD4127-A]
AK4127 THD+N vs Input Frequency (fsi=48[KHz], fso=44.1[KHz]) AVDD=DVDD=3.3[V], Input Level=-60[dBFS]
-100
-105
-110
-115
-120
-125
-130
d
B
F
S
-135
-140
-145
-150
-155
-160
-165
-170
-175
-180
20
50
100
200
500
1k
2k
5k
10k
20k
Hz
Fig 3. THD+N vs. Input Frequency (Input Level= −60[dBFS])
AK4127 Linearity (fsi=48[KHz], fso=44.1[KHz]) AVDD=DVDD=3.3[V], fin=1[KHz]
+0
-10
-20
-30
-40
-50
-60
d
B
F
S
-70
-80
-90
-100
-110
-120
-130
-140
-150
-150
-140
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
+0
dBFS
Fig 4. Linearity
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[AKD4127-A]
AK4127
Frequency Response (fsi=48[KHz], fso=44.1[KHz]) AVDD=DVDD=3.3[V], Input Level=0[dBFS]
+1
+0.5
-0
-0.5
-1
-1.5
-2
-2.5
d
B
F
S
-3
-3.5
-4
-4.5
-5
-5.5
-6
-6.5
-7
-7.5
-8
2k
4k
6k
8k
10k
12k
14k
16k
18k
20k
22k
24k
Hz
Fig 5. Frequency Response
AK4127 Frequency Response (fsi=44.1[KHz] (Yellow) / 48[KHz] (Blue) / 96[KHz] (Red) / 192[KHz] (Green),
fso=44.1[KHz]) AVDD=DVDD=3.3[V], Input Level=0[dBFS]
+1
-0
fsi=44.1kHz
-1
fsi=192kHz
-2
fsi=96kHz
-3
fsi=48kHz
-4
d
B
F
S
-5
-6
-7
-8
-9
-10
-11
-12
2k
4k
6k
8k
10k
12k
14k
16k
18k
20k
22k
24k
Hz
Fig 9. Frequency Response
[KM085601]
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[AKD4127-A]
AK4127 Frequency Response (fsi=48[KHz] (Blue) / 96[KHz] (Red) / 192[KHz] (Green), fso=48[KHz])
AVDD=DVDD=3.3[V], Input Level=0[dBFS]
+1
-0
-1
fsi=192kHz
-2
fsi=96kHz
-3
fsi=48kHz
-4
d
B
F
S
-5
-6
-7
-8
-9
-10
-11
-12
2k
4k
6k
8k
10k
12k
14k
16k
18k
20k
22k
Hz
Fig 8. Frequency Response
[KM085601]
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[AKD4127-A]
Revision History
Date
Manual
Board
Reason
(YY/MM/DD) Revision Revision
06/09/26
KM085600
0
First Edition
06/11/15
KM085601
0
Contents
Add
Add Table Data, Plot Data
Measurement
Results
IMPORTANT NOTICE
These products and their specifications are subject to change without notice.
When you consider any use or application of these products, please make inquiries the sales office of Asahi Kasei
EMD Corporation (AKEMD) or authorized distributors as to current status of the products.
AKEMD assumes no liability for infringement of any patent, intellectual property, or other rights in the application
or use of any information contained herein.
Any export of these products, or devices or systems containing them, may require an export license or other official
approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange,
or strategic materials.
AKEMD products are neither intended nor authorized for use as critical componentsNote1) in any safety, life support,
or other hazard related device or systemNote2), and AKEMD assumes no responsibility for such use, except for the
use approved with the express written consent by Representative Director of AKEMD. As used here:
Note1) A critical component is one whose failure to function or perform may reasonably be expected to result,
whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and
which must therefore meet very high standards of performance and reliability.
Note2) A hazard related device or system is one designed or intended for life support or maintenance of safety
or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or
perform may reasonably be expected to result in loss of life or in significant injury or damage to person or
property.
It is the responsibility of the buyer or distributor of AKEMD products, who distributes, disposes of, or otherwise
places the product with a third party, to notify such third party in advance of the above content and conditions, and
the buyer or distributor agrees to assume any and all responsibility and liability for and hold AKEMD harmless
from any and all claims arising from the use of said product in the absence of such notification.
[KM085601]
2006/11
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A
B
C
D
E
E
1
D1
HSU119
R1
10k
E
1
1
H
3
L
C1
0.1u
SW1
ATE1D-2M3
2
3
U1A
74HC14
4
PDN
REG
U1B
74HC14
OUT
2
PDN
U2
C5
1n
C7
0.22u
REG
FILT
AVDD
30
R2
470
C8
0.1u
2
AVSS
DVSS
29
3
PDN
DVDD
28
4
SMUTE
OMCLK
27
2
1
R3
10k
1
3
SMUTE
C11
0.1u
6
9
U1C
74HC14
8
U1D
74HC14
C6
0.1u
+ C9
10u
D
OMCLK
R5
51
5
DITHER
OLRCK
26
OLRCK
R6
51
2
SW2
ATE1D-2M3
+
R4
51
5
H
C3 C4
0.1u 47u
C10
0.1u
D
L
For 74HC14 x 1
REG
IN
C2
0.1u
1
D2
HSU119
VCC
T1
TA48M33F
GND
2
REG
6
PLL2
OBICK
25
R7
51
OBICK
R8
51
ILRCK
7
ILRCK
SDTO
24
8
IBICK
ODIF1
23
9
SDTI
ODIF0
22
10
IDIF0
CMODE2
21
11
IDIF1
CMODE1
20
12
IDIF2
CMODE0
19
SDTO
R9
51
IBICK
C
C
R10
51
SDTI
REG
DITH
PLL2
PLL1
PLL0
IDIF0
IDIF1
IDIF2
B
RP1
M8-1-473
1
2
3
4
5
6
7
REG
R11
51
SW3
DSS107
13
14
13
12
11
10
9
8
INPUT
PLL0
IMCLK
18
14
PLL1
OBIT1
17
15
UNLOCK
OBIT0
16
SW4
DSS107
IMCLK
1
2
3
4
5
6
7
14
13
12
11
10
9
8
ODIF1
ODIF0
CMODE2
CMODE1
CMODE0
OBIT1
OBIT0
B
OUTPUT
11
7
6
5
4
3
2
1
RP2
M8-1-473
AK4127
7
6
5
4
3
2
1
10
U1E
74HC14
47K
LED1
SML-210JT
REG
1
R12
1k
47K
2
UNLOCK
A
A
Title
-14-
Size
A3
Date:
A
B
C
D
AKD4127-A
Document Number
Rev
AK4127
Monday, August 28, 2006
Sheet
E
0
1
of
3
A
RX(COAX)
B
J1
BNC-R-PC
C
D
E
C12
0.1u
R13
75
E
E
DIF2 DIF1 DIF0
PORT1
TORX141
VCC
3
GND
OUT
2
1
C13
0.1u
COAX JP1 HIF3G-50P-2.54DSA (3x1)
RX
R14
470
H
OCKS1
C14
10u
OPT
1
2
Setting
24bit, MSB justified
OCKS0
H
H
CM1
CM0
L
L
Setting
128fs, 192kHz
Setting
PLL=ON, RX Mode
2
D
37
INT1
AVDD
R
38
R16
1k
39
40
VCOM
41
AVSS
42
RX0
43
NC
44
RX1
46
45
TEST1
NC
RX2
47
48
RX3
IPS0
ERF
LED2
SML-210JT
R15
18k
C16
0.47u
+
C
1
L
C15
0.1u
D
U3
L
+
RX(OPT)
REG
L1
47u
U1F
74HC14
INT0
36
NC
OCKS0
35
3
DIF0
OCKS1
34
4
TEST2
CM1
33
5
DIF1
CM0
32
13
12
C
R17
100
IMCLK
6
7
AK4114
NC
PDN
DIF2
XTI
31
30
PDN
R18
100
PORT2
A1-10PA-2.54DSA
IBICK
R19
100
8
IPS1
XTO
29
9
P/SN
DAUX
28
IMCLK
IBICK
ILRCK
SDTI
ILRCK
R20
100
1
2
3
4
5
10
9
8
7
6
INPUT
SDTI
B
10
XTL0
MCKO2
27
11
XTL1
BICK
26
12
VIN
SDTO
25
R21
220k
JP2 HIF3G-50P-2.54DSA (2x1)
IBICK
R22
220k
R23
220k
B
R24
220k
LRCK
24
MCKO1
23
22
DVSS
DVDD
21
VOUT
20
UOUT
19
BOUT
COUT
18
JP4 HIF3G-50P-2.54DSA (2x1)
ILRCK
C20
10u
+
A
C18
0.1u
A
+
C19
10u
17
TX1
16
TX0
15
DVSS
C17
0.1u
14
13
TVDD
JP3 HIF3G-50P-2.54DSA (2x1)
SDTI
Title
-15-
Size
A3
Date:
A
B
C
D
AKD4127-A
Document Number
Rev
INPUT
Monday, August 28, 2006
0
Sheet
E
2
of
3
A
B
C
D
E
REG
+
E
DIF2 DIF1 DIF0
C21
10u
H
C22
0.1u
IPS0
2
NC
37
INT1
R
AVDD
39
40
VCOM
41
42
AVSS
NC
RX0
43
44
RX1
46
45
TEST1
NC
RX2
47
48
RX3
1
38
C23
0.47u
+
U4
OCKS1
INT0
36
OCKS0
35
OCKS1
34
L
L
Setting
E
24bit, MSB justified
Setting
OCKS0
L
L
256fs, 96kHz
H
H
128fs, 192kHz
CM1
CM0
L
H
Setting
PLL=OFF, X'tal Mode
H
D
L
3
DIF0
4
TEST2
CM1
33
5
DIF1
CM0
32
D
JP5 HIF3G-50P-2.54DSA (3x1)
CKSO
R25
100
OMCLK
R26
100
PORT3
A1-10PA-2.54DSA
OBICK
R27
100
OMCLK
OBICK
OLRCK
SDTO
OLRCK
7
C
AK4114
NC
31
PDN
DIF2
30
XTI
R28
100
PDN
C24 5p
R29
220k
IPS1
XTO
29
9
P/SN
DAUX
28
10
XTL0
MCKO2
27
11
XTL1
BICK
26
12
VIN
SDTO
25
OUTPUT
R30
220k
R31
220k
R32
220k
C
2
X1 HC-49/U
11.2896MHz
8
10
9
8
7
6
SDTO
1
6
1
2
3
4
5
C25 5p
PORT4
TOTX141
TX(OPT)
IN
VCC
3
2
GND
1
LRCK
24
MCKO1
23
22
DVSS
DVDD
+
OPT
C31
0.1u
C27
0.1u
B
JP7 HIF3G-50P-2.54DSA (2x1)
OLRCK
C29
10u
+
C28
10u
21
20
VOUT
UOUT
19
COUT
18
BOUT
17
TX1
16
TX0
15
C26
0.1u
14
13
B
DVSS
TVDD
JP6 HIF3G-50P-2.54DSA (2x1)
OBICK
BNC
C30
0.1u
R33
240
JP8 HIF3G-50P-2.54DSA (3x1)
TX
T2
DA-02F
J2
BNC-R-PC
TX(BNC)
R34
150
1:1
A
A
Title
-16-
Size
A3
Date:
A
B
C
D
AKD4127-A
Document Number
Rev
OUTPUT
Monday, August 28, 2006
Sheet
E
0
3
of
3
-17-
-18-
-19-
-20-
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