AKM AKD4127

[AK4127]
AK4127
192kHz / 24Bit High Performance Asynchronous SRC
GENERAL DESCRIPTION
The AK4127 is a stereo digital sample rate converter (SRC). The input sample rate ranges from 8kHz to
216kHz. The output sample rate is from 8kHz to 216kHz. The system can take very simple configuration
because the AK4127 has an internal PLL and does not need any master clock at slave mode. The
AK4127 is suitable for the application interfacing to different sample rates such as high-end Car Audio
and DVD recorder.
FEATURES
1. SRC
2.
3.
4.
5.
• Asynchronous Sample Rate Converter
• Input Sample Rate Range (fsi): 8kHz ∼ 216kHz
• Output Sample Rate (fso): 8kHz ∼ 216kHz
• Input to Output Sample Rate Ratio: 1/6 to 6
• THD+N: −130dB
• Dynamic Range: 140dB (A-weighted)
• I/F format: MSB justified, LSB justified, I2S compatible and TDM
• PLL for Internal Operation Clock
• Clock for Master mode: 128/192/256/384/512/768fsi, 128/256/384/512/768fso
• SRC Bypass mode (Master/Slave)
• Soft Mute Function
Power Supply
• AVDD, DVDD: 3.0 ∼ 3.6V (typ. 3.3V)
Ta = −40 ∼ 85°C
Package: 30pin VSOP
AK4124/5 Pin-compatible
IDIF2 IDIF1 IDIF0
AVDD AVSS DVDD DVSS ODIF1 ODIF0
OBIT1
OBIT0
IBICK
ILRCK
SDTI
Serial
Audio
I/F
Serial
Audio
I/F
SRC
OLRCK
OBICK
SDTO
OMCLK
PDN
PLL2
PLL1
PLL0
SMUTE
PLL
UNLOCK
DITHER
IMCLK
CMODE2 CMODE1 CMODE0
MS0593-E-01
2007/07
-1-
[AK4127]
TABLE OF CONTENTS
GENERAL DESCRIPTION............................................................................................................................................... 1
FEATURES........................................................................................................................................................................ 1
■ Ordering Guide ........................................................................................................................................................... 3
Pin Layout ..................................................................................................................................................................... 3
■ Compatibility with AK4125........................................................................................................................................ 4
PIN/FUNCTION ................................................................................................................................................................ 5
■ Handling of Unused pins............................................................................................................................................. 6
ABSOLUTE MAXIMUM RATINGS ............................................................................................................................... 6
RECOMMENDED OPERATING CONDITIONS ............................................................................................................ 6
SRC CHARACTERISTICS ............................................................................................................................................... 7
FILTER CHARACTERISTICS ......................................................................................................................................... 8
DC CHARACTERISTICS ................................................................................................................................................. 9
SWITCHING CHARACTERISTICS ................................................................................................................................ 9
■ Timing Diagram ........................................................................................................................................................ 11
OPERATION OVERVIEW ............................................................................................................................................. 13
■ System Clock & Audio Interface Format for Input PORT........................................................................................ 13
■ System Clock & Audio Interface Format for Output PORT ..................................................................................... 15
■ Cascade TDM Mode ................................................................................................................................................. 18
■ Soft Mute Operation.................................................................................................................................................. 19
■ Dither ........................................................................................................................................................................ 20
■ System Reset ............................................................................................................................................................. 20
■ Internal Reset Function for Clock Change ................................................................................................................ 21
■ Sequence of Changing Clocks .................................................................................................................................. 21
■ UNLOCK pin ............................................................................................................................................................ 21
■ PLL Loop Filter......................................................................................................................................................... 22
SYSTEM DESIGN........................................................................................................................................................... 23
PACKAGE ....................................................................................................................................................................... 27
■ Material & Lead finish .............................................................................................................................................. 27
MARKING ....................................................................................................................................................................... 28
REVISION HISTORY ..................................................................................................................................................... 28
IMPORTANT NOTICE ................................................................................................................................................... 29
MS0593-E-01
2007/07
-2-
[AK4127]
■ Ordering Guide
AK4127VF
AKD4127
−40 ∼ +85°C
30pin VSOP (0.65mm pitch)
Evaluation Board for AK4127
■ Pin Layout
FILT
1
30
AVDD
AVSS
2
29
DVSS
PDN
3
28
DVDD
SMUTE
4
27
OMCLK
DITHER
5
26
OLRCK
PLL2
6
25
OBICK
ILRCK
7
24
SDTO
IBICK
8
23
ODIF1
SDTI
9
22
ODIF0
IDIF0
10
21
CMODE2
IDIF1
11
20
CMODE1
IDIF2
12
19
CMODE0
PLL0
13
18
IMCLK
PLL1
14
17
OBIT1
UNLOCK
15
16
OBIT0
Top View
MS0593-E-01
2007/07
-3-
[AK4127]
■ Compatibility with AK4125
Item
TDM Mode
Slave Mode at Bypass Mode
AK4125
-
OMCLK pin
OMCLK
OMCLK=192fso for Output PORT
(at Master Mode)
X
AK4127
X
X
Normal Mode: OMCLK
TDM Mode: TDMIN
(-: Not available, X: Available)
MS0593-E-01
2007/07
-4-
[AK4127]
PIN/FUNCTION
No.
Pin Name
I/O
Function
PLL Loop Filter Pin, Hi-Z when PDN pin = “L”.
Analog Ground Pin
Power-Down Mode Pin
“H”: Power up, “L”: Power down reset and initializes the control register.
Soft Mute Pin
“H” : Soft Mute, “L” : Normal Operation
Dither Enable Pin
“H” : Dither ON, “L” : Dither OFF
PLL Mode Select 2 Pin
Input Channel Clock Pin, Output “L” when PDN = “L” and master mode.
Audio Serial Data Clock Pin, Output “L” when PDN = “L” and master mode.
Audio Serial Data Input Pin
Audio Interface Format 0 Pin for Input PORT
Audio Interface Format 1 Pin for Input PORT
Audio Interface Format 2 Pin for Input PORT
PLL Mode Select 0 Pin
PLL Mode Select 1 Pin
Unlock Status Pin, Output “H” when PDN = “L”
Bit Length Select 0 Pin for Output Data
Bit Length Select 1 Pin for Output Data
Master Clock Input Pin for Input PORT
Clock Mode Select 0 Pin
Clock Mode Select 1 Pin
Clock Mode Select 2 Pin
Audio Interface Format 0 Pin for Output PORT
Audio Interface Format 1 Pin for Output PORT
Audio Serial Data Output Pin for Output PORT, Output “L” when PDN pin = “L”
Audio Serial Data Clock Pin for Output PORT
Output “L” when PDN = “L” and master mode.
Output Channel Clock Pin for Output PORT
Output “L” when PDN = “L” and master mode.
Master Clock/TDM Data Input Pin for Output PORT
OMCLK: Master Clock Input Pin (except for PLL2/1/0 pin = “L/H/H”)
TDMIN: TDM Data Input Pin (PLL2/1/0 pin = “L/H/H”)
Digital Power Supply Pin, 3.0 ∼ 3.6V
Digital Ground Pin
Analog Power Supply Pin, 3.0 ∼ 3.6V
1
2
FILT
AVSS
O
-
3
PDN
I
4
SMUTE
I
5
DITHER
I
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
PLL2
ILRCK
IBICK
SDTI
IDIF0
IDIF1
IDIF2
PLL0
PLL1
UNLOCK
OBIT0
OBIT1
IMCLK
CMODE0
CMODE1
CMODE2
ODIF0
ODIF1
SDTO
I
I/O
I/O
I
I
I
I
I
I
O
I
I
I
I
I
I
I
I
O
25
OBICK
I/O
26
OLRCK
I/O
27
OMCLK
I
28
29
30
DVDD
DVSS
AVDD
-
Note: All input pins must not be left floating.
MS0593-E-01
2007/07
-5-
[AK4127]
■ Handling of Unused pins
The unused digital I/O pins should be processed appropriately as below.
Classification
Analog
Digital
Pin Name
FILT
SMUTE, DITHER
IMCLK, OMCLK
UNLOCK
Setting
This pin should be open.
These pins should be connected to DVSS.
These pins should be connected to DVSS in slave mode.
This pin should be open.
ABSOLUTE MAXIMUM RATINGS
(AVSS, DVSS=0V; Note 1)
Parameter
Power Supplies:
Analog
Digital
|AVSS − DVSS| (Note 2)
Input Current, Any Pin Except Supplies
Digital Input Voltage (Note 3)
Ambient Temperature (Power applied)
Storage Temperature
Symbol
min
max
Units
AVDD
DVDD
ΔGND
IIN
VIND
Ta
Tstg
−0.3
−0.3
−0.3
−40
−65
4.6
4.6
0.3
±10
DVDD+0.3
85
150
V
V
V
mA
V
°C
°C
Note 1. All voltages with respect to ground.
Note 2. AVSS, BVSS and DVSS must be connected to the same ground.
Note 3. PND, SMUTE, DITHER, PLL2, ILRCK, IBICK, SDTI, IDIF0, IDIF1, IDIF2, PLL0, PLL1, OBIT0, OBIT1,
IMCLK, CMODE0, CMODE1, CMODE2, ODIF0, ODIF1, OBICK, OLRCK and OMCLK
WARNING: Operation at or beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
RECOMMENDED OPERATING CONDITIONS
(AVSS, DVSS=0V; Note 1)
Parameter
Symbol
min
typ
Power Supplies
Analog
AVDD
3.0
3.3
(Note 4)
Digital
DVDD
3.0
3.3
max
3.6
AVDD
Units
V
V
Note 4. The power up sequence between AVDD and DVDD is not important.
WARNING: AKEMD assumes no responsibility for the usage beyond the conditions in this datasheet.
MS0593-E-01
2007/07
-6-
[AK4127]
SRC CHARACTERISTICS
(Ta=25°C; AVDD=DVDD=3.3V; AVSS=DVSS=0V; data = 24bit; measurement bandwidth = 20Hz ~ FSO/2; unless
otherwise specified.)
Parameter
Symbol
min
typ
max
Units
SRC Characteristics:
Resolution
24
Bits
Input Sample Rate
FSI
8
216
kHz
Output Sample Rate
FSO
8
216
kHz
THD+N
(Input = 1kHz, 0dBFS, Note 5)
FSO/FSI = 44.1kHz/48kHz
−130
dB
FSO/FSI = 48kHz/44.1kHz
−124
dB
FSO/FSI = 48kHz/192kHz
−133
dB
FSO/FSI = 192kHz/48kHz
−124
dB
Worst Case (FSO/FSI = 32kHz/176.4kHz)
−91
dB
Dynamic Range (Input = 1kHz, −60dBFS, Note 5)
FSO/FSI = 44.1kHz/48kHz
136
dB
FSO/FSI = 48kHz/44.1kHz
136
dB
FSO/FSI = 48kHz/192kHz
136
dB
FSO/FSI = 192kHz/48kHz
132
dB
Worst Case (FSO/FSI = 48kHz/32kHz)
132
dB
Dynamic Range (Input = 1kHz, −60dBFS, A-weighted, Note 5)
FSO/FSI = 44.1kHz/48kHz
140
dB
Ratio between Input and Output Sample Rate
FSO/FSI
1/6
6
Note 5. Measured by Audio Precision System Two Cascade
MS0593-E-01
2007/07
-7-
[AK4127]
FILTER CHARACTERISTICS
(Ta=25°C; AVDD, DVDD=3.0 ∼ 3.6V)
Parameter
Digital Filter
Passband −0.01dB
0.985 ≤ FSO/FSI ≤ 6.000
0.905 ≤ FSO/FSI < 0.985
0.714 ≤ FSO/FSI < 0.905
0.656 ≤ FSO/FSI < 0.714
0.536 ≤ FSO/FSI < 0.656
0.492 ≤ FSO/FSI < 0.536
0.452 ≤ FSO/FSI < 0.492
0.357 ≤ FSO/FSI < 0.452
0.324 ≤ FSO/FSI < 0.357
0.246 ≤ FSO/FSI < 0.324
0.226 ≤ FSO/FSI < 0.246
0.1667 ≤ FSO/FSI < 0.226
Stopband
0.985 ≤ FSO/FSI ≤ 6.000
0.905 ≤ FSO/FSI < 0.985
0.714 ≤ FSO/FSI < 0.905
0.656 ≤ FSO/FSI < 0.714
0.536 ≤ FSO/FSI < 0.656
0.492 ≤ FSO/FSI < 0.536
0.452 ≤ FSO/FSI < 0.492
0.357 ≤ FSO/FSI < 0.452
0.324 ≤ FSO/FSI < 0.357
0.246 ≤ FSO/FSI < 0.324
0.226 ≤ FSO/FSI < 0.246
0.1667 ≤ FSO/FSI < 0.226
Passband Ripple
Stopband
0.985 ≤ FSO/FSI ≤ 6.000
Attenuation
0.905 ≤ FSO/FSI < 0.985
0.714 ≤ FSO/FSI < 0.905
0.656 ≤ FSO/FSI < 0.714
0.536 ≤ FSO/FSI < 0.656
0.492 ≤ FSO/FSI < 0.536
0.452 ≤ FSO/FSI < 0.492
0.357 ≤ FSO/FSI < 0.452
0.324 ≤ FSO/FSI < 0.357
0.246 ≤ FSO/FSI < 0.324
0.226 ≤ FSO/FSI < 0.246
0.1667 ≤ FSO/FSI < 0.226
Group Delay
(Note 6)
Symbol
min
PB
PB
PB
PB
PB
PB
PB
PB
PB
PB
PB
PB
SB
SB
SB
SB
SB
SB
SB
SB
SB
SB
SB
SB
PR
SA
SA
SA
SA
SA
SA
SA
SA
SA
SA
SA
SA
GD
0
0
0
0
0
0
0
0
0
0
0
0
0.5417FSI
0.5021FSI
0.3965FSI
0.3643FSI
0.2974FSI
0.2813FSI
0.2604FSI
0.2116FSI
0.1969FSI
0.1573FSI
0.1471FSI
0.1020FSI
typ
max
Units
0.4583FSI
0.4167FSI
0.3195FSI
0.2852FSI
0.2182FSI
0.2177FSI
0.1948FSI
0.1458FSI
0.1302FSI
0.0917FSI
0.0826FSI
0.0583FSI
kHz
kHz
kHz
kHz
kHz
kHz
kHz
kHz
kHz
kHz
kHz
kHz
kHz
kHz
kHz
kHz
kHz
kHz
kHz
kHz
kHz
kHz
kHz
kHz
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
1/fs
±0.01
121.2
121.4
115.3
116.9
114.6
100.2
103.3
102.0
103.6
104.0
103.3
73.2
-
56
-
Note 6. This delay is the a period from the rising edge of ILRCK, just after the data is input, to the rising edge of OLRCK,
just after the data is output, when there is no phase difference between ILRCK and OLRCK.
MS0593-E-01
2007/07
-8-
[AK4127]
DC CHARACTERISTICS
(Ta=25°C; AVDD, DVDD=3.0 ∼ 3.6V)
Parameter
High-Level Input Voltage
Low-Level Input Voltage
High-Level Output Voltage
(Iout=−400μA)
Low-Level Output Voltage
(Iout=400μA)
Input Leakage Current
Symbol
VIH
VIL
VOH
VOL
Iin
min
70%DVDD
DVDD−0.4
-
typ
-
Power Supplies
Power Supply Current
Normal operation (PDN pin = “H”)
FSI=FSO=48kHz at Slave Mode: AVDD=DVDD=3.3V
FSI=FSO=192kHz at Master Mode: AVDD=DVDD=3.3V
: AVDD=DVDD=3.6V
Power down (PDN pin = “L”) (Note 7)
AVDD+DVDD
max
30%DVDD
0.4
±10
Units
V
V
V
V
μA
100
mA
mA
mA
100
μA
15
65
10
Note 7. All digital input pins are held DVSS.
SWITCHING CHARACTERISTICS
(Ta=25°C; AVDD, DVDD=3.0 ∼ 3.6V; CL=20pF)
Parameter
Symbol
min
Master Clock Timing
Frequency
fCLK
1.024
Pulse Width Low
tCLKL
0.4/fCLK
Pulse Width High
tCLKH
0.4/fCLK
LRCK for Input data (ILRCK)
Frequency
fs
8
Duty Cycle
Slave Mode
Duty
48
Master Mode
Duty
LRCK for Output data (OLRCK)
Frequency
Duty Cycle
Slave Mode
Master Mode
fs
Duty
Duty
8
48
LRCK for TDM Mode (OLRCK)
Frequency
“H” time
“L” time
fs
tLRH
tLRL
8
1/256fs
1/256fs
tBCK
tBCK
tBCK
tBCKL
tBCKH
tLRB
tBLR
tSDH
tSDS
1/256fs
1/128fs
1/64fs
27
27
15
15
15
15
Audio Interface Timing
Input PORT (Slave mode)
IBICK Period
(8kHz ∼ 54kHz)
(54kHz ∼ 108kHz)
(108kHz ∼ 216kHz)
IBICK Pulse Width Low
Pulse Width High
ILRCK Edge to IBICK “↑”
(Note 8)
IBICK “↑” to ILRCK Edge
(Note 8)
SDTI Hold Time from IBICK “↑”
SDTI Setup Time to IBICK “↑”
MS0593-E-01
typ
50
50
50
50
max
Units
41.472
MHz
ns
ns
216
52
kHz
%
%
216
52
kHz
%
%
48
kHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2007/07
-9-
[AK4127]
Input PORT (Master mode)
IBICK Frequency
IBICK Duty
IBICK “↓” to ILRCK
SDTI Hold Time from IBICK “↑”
SDTI Setup Time to IBICK “↑”
Output PORT (Slave mode)
OBICK Period (8kHz ∼ 54kHz)
(54kHz ∼ 108kHz)
(108kHz ∼ 216kHz)
OBICK Pulse Width Low
Pulse Width High
OLRCK Edge to OBICK “↑”
(Note 8)
OBICK “↑” to OLRCK Edge
(Note 8)
OLRCK to SDTO (MSB) (Except I2S mode)
OBICK “↓” to SDTO
Output PORT (TDM slave mode)
OBICK Period
OBICK Pulse Width Low
Pulse Width High
OLRCK Edge to BICK “↑”
(Note 8)
OBICK “↑” to LRCK Edge
(Note 8)
OBICK “↓” to SDTO
TDMIN Hold Time
TDMIN Setup Time
Output PORT (Master mode)
OBICK Frequency
OBICK Duty
OBICK “↓” to OLRCK
OBICK “↓” to SDTO
fBCK
dBCK
tMBLR
tSDH
tSDS
64fs
50
−20
15
15
tBCK
tBCK
tBCK
tBCKL
tBCKH
tLRB
tBLR
tLRS
tBSD
1/256fs
1/128fs
1/64fs
27
27
20
20
tBCK
tBCKL
tBCKH
tLRB
tBLR
tBSD
tSDH
tSDS
81
32
32
20
20
fBCK
dBCK
tMBLR
tBSD
20
20
20
20
10
64fs
50
−20
−20
Reset Timing
PDN Pulse Width
(Note 9)
tPD
150
Note 8. BICK rising edge must not occur at the same time as LRCK edge.
Note 9. The AK4127 can be reset by bringing the PDN pin = “L”.
MS0593-E-01
20
20
20
Hz
%
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Hz
%
ns
ns
ns
2007/07
- 10 -
[AK4127]
■ Timing Diagram
1/fCLK
VIH
MCLK
VIL
tCLKH
tCLKL
1/fs
VIH
LRCK
VIL
tBCK
VIH
BICK
VIL
tBCKH
tBCKL
Clock Timing
VIH
LRCK
VIL
tBLR
tLRB
VIH
BICK
VIL
tBSD
tLRS
SDTO
50%DVDD
tSDS
tSDH
VIH
SDTI
VIL
Audio Interface Timing (Slave mode)
Note : BICK shows IBICK and OBICK, LRCK shows ILRCK and OLRCK.
MS0593-E-01
2007/07
- 11 -
[AK4127]
LRCK
50%DVDD
tMBLR
dBCK
BICK
50%DVDD
tBSD
SDTO
50%DVDD
tSDH
tSDS
VIH
SDTI
VIL
Audio Interface Timing (Master mode)
Note : BICK shows IBICK and OBICK, LRCK shows ILRCK and OLRCK.
tPD
PDN
VIL
Power Down & Reset Timing
MS0593-E-01
2007/07
- 12 -
[AK4127]
OPERATION OVERVIEW
■ System Clock & Audio Interface Format for Input PORT
The input port works in master mode or slave mode. An internal system clock is created by the internal PLL using ILRCK
(Mode 0 ∼ 3 of Table 2) or IBICK (Mode 4 ∼ 7 of Table 2) in slave mode. The MCLK is not needed in slave mode. And
an internal system clock is created by IMCLK (Mode 8 ∼ 15 of Table 2) in master mode. The PLL2-0 pins and IDIF2-0
pins select the master/slave and PLL mode. The PLL2-0 pins and IDIF2-0 pins should be controlled when the PDN pin =
“L”. When the PLL2-0 pin= “L/H/H”, setting the output port slave (CMODE2-0pin = “H/L/L” or “H/H/L”) enables the
TDM mode at the output port.
The IDIF2-0 pins select the audio interface format for the input port. The audio data is MSB first, 2’s compliment format.
The SDTI is latched on the rising edge of IBICK. Select the audio interface format when the PDN pin = “L”. When in
BYPASS mode, both IBICK and OBICK are fixed to 64fs.
Mode
0
1
2
3
4
5
6
7
Mode
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
IDIF2
L
L
L
L
H
H
H
H
IDIF1
L
L
H
H
L
L
H
H
Master / Slave
Slave
IMCLK = DVSS
IBICK = Input
ILRCK = Input
Master
IMCLK = Input
IBICK = Output
ILRCK = Output
IDIF0
SDTI Format
ILRCK IBICK
IBICK Freq
L
16bit, LSB justified
≥ 32fsi
H
20bit, LSB justified
≥ 40fsi
Input
Input
L
24/20bit, MSB justified
≥ 48fsi
2
H
24/16bit, I S Compatible
≥ 48fsi or 32fsi
L
24bit, LSB justified
≥ 48fsi
H
24bit, MSB justified
64fs
Output Output
L
24bit, I2S Compatible
64fs
H
Reserved
Table 1. Input Audio Interface Format (Input PORT)
PLL2
PLL1
PLL0
ILRCK Freq
L
L
L
L
L
L
H
H
L
H
L
H
8k ∼ 216kHz
16k ∼ 216kHz
(Note 10)
H
H
H
H
L
L
L
L
H
H
H
H
L
8k ∼ 96kHz
L
8k ∼ 216kHz
L
H
(Note 11)
H
L
H
H
8k ∼ 216kHz
L
L
8k ∼ 108kHz
L
H
8k ∼ 54kHz
H
L
8k ∼ 216kHz
H
H
8k ∼ 216kHz
L
L
8k ∼ 108kHz
L
H
8k ∼ 54kHz
H
L
8k ∼ 216kHz
H
H
Table 2. PLL Setting (Input PORT)
Master / Slave
IBICK Freq
IMCLK
Depending
on IDIF2-0
(Note 11)
Not
needed.
(Note 13)
32fsi
(Note 12)
64fsi
128fsi
64fsi
Not
needed.
(Note 13)
64fsi
128fsi
256fsi
512fsi
128fsi
192fsi
384fsi
768fsi
192fsi
Slave
Master
SMUTE
(Note 14)
Manual
Semi-Auto
Manual
Manual
Semi-Auto
Manual
Semi-Auto
Manual
Semi-Auto
Note 10. PLL lock rage is changed by the value of R and C connected FILT pin. Refer to “PLL Loop Filter”.
Note 11. The IBCIK must be continuous except when the clocks are changed.
Note 12. IBCIK = 32fsi is supported only 16bit LSB justified and I2S Compatible.
Note 13. Fixed to DVSS.
Note 14. Refer to “Soft Mute Operation” for Manual mode and Semi-Auto mode.
MS0593-E-01
2007/07
- 13 -
[AK4127]
ILRCK
0 1 2 3
9 10 11 12 13 14 15 0 1 2 3
9 10 11 12 13 14 15 0 1
IBICK(32fs)
SDTI(i)
15 14 13
7 6 5 4 3 2 1 0 15 14 13
0 1 2 3
17 18 19 20
7 6 5 4 3 2 1 0 15
31 0 1 2 3
17 18 19 20
31 0 1
IBICK(64fs)
SDTI(i)
Don't Care
15 14 13 12
1 0
Don't Care
15 14 13 12
2 1 0
15:MSB, 0:LSB
Lch Data
Rch Data
Figure 1. Mode 0 Timing
ILRCK
0 1 2
12 13
24
31 0 1 2
12 13
24
31 0 1
IBICK(64fs)
SDTI(i)
19
Don't Care
8
1 0
Don't Care
19
8
1 0
19:MSB, 0:LSB
Lch Data
Rch Data
Figure 2. Mode 1 Timing
ILRCK
0 1 2
20 21 22 23 24
31 0 1 2
20 21 22 23 24
31 0 1
IBICK(64fs)
SDTI(i)
23 22
4 3 2 1 0
Don't Care 23 22
4 3 2 1 0
Don't Care 23
23:MSB, 0:LSB
Lch Data
Rch Data
Figure 3. Mode 2,5 Timing (24bit MSB)
ILRCK
0 1 2 3
21 22 23 24 25
0 1 2
21 22 23 24 25
0 1
IBICK(64fs)
SDTI(i)
23 22
4 3 2 1 0
Don't Care 23 22
4 3 2 1 0
Don't Care
23:MSB, 0:LSB
Lch Data
Rch Data
2
Figure 4. Mode 3, 6 Timing (24bit I S)
MS0593-E-01
2007/07
- 14 -
[AK4127]
ILRCK
0 1 2
8 9
24
31 0 1 2
8 9
24
31 0 1
IBICK(64fs)
SDTI(i)
Don't Care
23
8
1 0
Don't Care
23
8
1 0
23:MSB, 0:LSB
Lch Data
Rch Data
Figure 5. Mode 4 Timing
■ System Clock & Audio Interface Format for Output PORT
The output port works in master mode or slave mode. The MCLK is not needed in slave mode. The CMODE2-0 pins
select the master/slave and bypass mode. The CMODE2-0 pins should be controlled when the PDN pin = “L”.
The ODIF1-0 pins and OBIT1-0 pins select the audio interface format for the output port. The audio data is MSB first, 2’s
compliment format. The SDTO is clocked out on the falling edge of OBICK. Select the audio interface format when the
PDN pin = “L”. When in BYPASS mode, both IBICK and OBICK are fixed to 64fs.
When the PLL2-0 pin= “L/H/H”, setting the output port slave (CMODE2-0pin = “H/L/L” or “H/H/L”) enables the TDM
mode at the output port. The OMCLK pin changes to TDMIN pin for TDM data input in TDM mode.
0
1
2
3
CMODE
2
L
L
L
L
CMODE
1
L
L
H
H
4
H
5
6
Mode
CMODE0
Master / Slave
OMCLK
fso
L
H
L
H
Master
Master
Master
Master
8k ∼ 108kHz
8k ∼ 108kHz
8k ∼ 54kHz
8k ∼ 54kHz
L
L
Slave
H
L
H
Master
H
H
L
Slave (Bypass)
256fso
384fso
512fso
768fso
Not used. Set to DVSS.
(Note 15)
128fso
Not used. Set to DVSS.
(Note 15)
Not used. Set to DVSS.
7
H
H
H
Master (Bypass)
Note 15. Changed to TDMIN pin when PLL2-0 pins = “L/H/H”.
8k ∼ 216kHz
8k ∼ 216kHz
8k ∼ 216kHz
8k ∼ 216kHz
Table 3. Master/Slave Control (Output PORT)
Mode ODIF1 ODIF0
SDTO Format
0
L
L
LSB justified
1
L
H
(Reserved)
2
H
L
MSB justified
3
H
H
I2S Compatible
Table 4. Output Audio Interface Format 1 (Output PORT)
MS0593-E-01
2007/07
- 15 -
[AK4127]
Mode
0
1
2
3
4
5
6
7
Master / Slave
OBIT
0
OBIT1
SDTO
OLRCK
OBICK Frequency
LSB
MSB justified,
justified
I2S
≥ 32fso
≥ 36fso
64fso
≥ 40fso
≥ 48fso
OBICK
L
L
16bit
L
H
18bit
Input
Input
H
L
20bit
H
H
24bit
L
L
16bit
L
H
18bit
Output
Output
H
L
20bit
H
H
24bit
Table 5. Output Audio Interface Format 2 (Output PORT)
Slave
CMODE2-0 =
“HLL” or “HHL”
Master
Except
CMODE2-0 =
“HLL” or “HHL”
64fso
OLRCK
0 1
8 9 10 11 12 13 14 15 16 17
20 21 22 23
29 30 31 0 1
8 9 10 11 12 13 14 15 16 17
20 21 22 23
29 30 31 0 1 2
OBICK(64fs)
15 14
11 10 9 8
2 1 0
15 14
11 10 9 8
2 1 0
17 16 15 14
11 10 9 8
2 1 0
17 16 15 14
11 10 9 8
2 1 0
19 18 17 16 15 14
11 10 9 8
2 1 0
19 18 17 16 15 14
11 10 9 8
2 1 0
11 10 9 8
2 1 0
23 22 21 20 19 18 17 16 15 14
11 10 9 8
2 1 0
SDTO(O)
15:MSB, 0:LSB
SDTO(O)
17:MSB, 0:LSB
SDTO(O)
19:MSB, 0:LSB
SDTO(O)
23 22 21 20 19 18 17 16 15 14
23:MSB, 0:LSB
Lch Data
Rch Data
Figure 6. Normal Mode LSB Timing
OLRCK
0 1 2 3 4
13 14 15 16 17 18 19 20 21 22 23 24
31 0 1 2 3 4
13 14 15 16 17 18 19 20 21 22 23 24
31 0 1 2
OBICK(64fs)
SDTO(O)
15 14 13 12
2 1 0
15 14 13 12
2 1 0
15 14
17 16 15 14
4 3 2 1 0
17 16
19 18 17 16
6 5 4 3 2 1 0
19 18
23 22 21 20
10 9 8 7 6 5 4 3 2 1 0
23 22
15:MSB, 0:LSB
SDTO(O)
17 16 15 14
4 3 2 1 0
17:MSB, 0:LSB
SDTO(O)
19 18 17 16
6 5 4 3 2 1 0
19:MSB, 0:LSB
SDTO(O)
23 22 21 20
10 9 8 7 6 5 4 3 2 1 0
23:MSB, 0:LSB
Lch Data
Rch Data
Figure 7. Normal Mode MSB Timing
OLRCK
0 1 2 3 4
14 15 16 17 18 19 20 21 22 23 24
0 1 2 3 4
14 15 16 17 18 19 20 21 22 23 24
31 0 1 2
OBICK(64fs)
SDTO(O)
15 14 13 12
2 1 0
15 14 13 12
2 1 0
15
17 16 15 14
4 3 2 1 0
17
19 18 17 16
6 5 4 3 2 1 0
19
23 22 21 20
10 9 8 7 6 5 4 3 2 1 0
23
15:MSB, 0:LSB
SDTO(O)
17 16 15 14
4 3 2 1 0
17:MSB, 0:LSB
SDTO(O)
19 18 17 16
6 5 4 3 2 1 0
19:MSB, 0:LSB
SDTO(O)
23 22 21 20
10 9 8 7 6 5 4 3 2 1 0
23:MSB, 0:LSB
Lch Data
Rch Data
2
Figure 8. Normal Mode I S Compatible Timing
MS0593-E-01
2007/07
- 16 -
[AK4127]
256 OBICK
OLRCK(I)
OBICK (I: 256fso)
TDMIN(I)
23 22
0
23 22
L2
SDTO(O)
23 22
0
23 22
R2
0
23 22
0
23 22
L3
0
23 22
0
23 22
R3
0
23 22
0
23 22
L4
0
L1
R1
L2
R2
32 BICK
32 BICK
32 BICK
32 BICK
23 22
0
23 22
R4
0
23 22
L3
0
23 22
R3
0
23 22
L4
0
23 22
R4
Figure 9. TDM mode MSB Timing
256 OBICK
OLRCK(I)
OBICK (I: 256fso)
TDMIN(I)
23
0
23
L2
SDTO(O)
23
0
23
R2
0
23
0
23
L3
0
23
0
R3
0
23
0
23
L4
0
L1
R1
L2
R2
32 BICK
32 BICK
32 BICK
32 BICK
23
0
23
23
R4
0
23
L3
0
R3
23
0
L4
23
0
23
R4
Figure 10. TDM mode I2S Compatible Timing
MS0593-E-01
2007/07
- 17 -
[AK4127]
■ Cascade TDM Mode
The AK4127 supports cascading connection of up to four devices (8channels) in a daisy chain configuration at TDM
mode. In this mode, the SDTO pin of device #N is connected to TDMIN pin of device #(N+1). The device can output up
to 8ch TDM data multiplexed with TDMIN data. Figure 11shows a connection example of a daisy chain.
AK4127 #1
OMCLK
256fs or 512fs
OLRCK
48kHz
OBICK
256fs
TDMIN
GND
SDTO
OMCLK
AK4127 #2
OLRCK
OBICK
TDMIN
(TDMIN of AK4127 #3)
SDTO
Figure 11. Cascade TDM Connection Diagram
256 BICK
OLRCK
OBICK(256fs)
#1 SDTO(o)
= #2 TDMIN(i)
#2 SDTO(o)
= #3 TDMIN(i)
#3 SDTO(o)
= #4 TDMIN(i)
#4 SDTO(o)
23 33
0
23 22
0
L #1
R #1
32 BICK
32 BICK
23 22
0
23 22
0
23 22
23 22
0
23 22
0
L #2
R #2
L #1
R #1
32 BICK
32 BICK
32 BICK
32 BICK
23 22
0
23 22
0
23 22
0
23 22
0
23 22
23 22
0
23 22
0
L #3
R #3
L #2
R #2
L #1
R #1
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
23 22
0
23 22
0
23 22
0
23 22
0
23 22
0
23 22
0
23 22
23 22
0
23 22
0
L #4
R #4
L #3
R #3
L #2
R #2
L #1
R #1
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
23 22
Figure 12. Cascade TDM Timing (4devices)
MS0593-E-01
2007/07
- 18 -
[AK4127]
■ Soft Mute Operation
1. Manual mode
Soft mute operation is performed in the digital domain of the SRC output. Soft mute can be controlled by the SMUTE pin.
When the SMUTE pin changes to “H”, the SRC output data is attenuated by −∞ within 1024 OLRCK cycles. When the
SMUTE pin changes to “L” the mute is cancelled and the output attenuation gradually changes to 0dB during 1024
OLRCK cycles. If the soft mute is cancelled before mute state after starting of the operation, the attenuation is
discontinued and returned to 0dB by the same cycles. The soft mute is effective for changing the signal source.
SM UTE
1024/fso
(1)
0dB
(2)
A ttenuation
-∞
SDTO
Figure 13. Soft Mute Function (Manual Mode)
(1) The output data is attenuated by −∞ during 1024 OLRCK cycles (1024/fso).
(2) If the soft mute is cancelled before attenuating to −∞ after starting the operation, the attenuation is discontinued and
returned to 0dB by the same number of clock cycles.
2. Semi-Auto mode
The soft mute is cancelled automatically by the setting of PLL2-0 pins (Table 2), after the AK4127 detects the rising edge
(PDN pin = “L” → “H”) and the mute is continued during [email protected]=44.1kHz. After PDN pin = “L” → “H”
and when SMUTE pin is “H”, the mute is not cancelled.
P D N pin
“L”
D on’t care
S M U TE pin
0dB
A ttenuation
“L”
(1)
4410/fso
-∞
S D TO
Figure 14. Soft Mute Function (Semi-Auto Mode)
(1) The output data is returned to 0dB during 1024 OLRCK cycles (1024/fso).
MS0593-E-01
2007/07
- 19 -
[AK4127]
■ Dither
The AK4127 has a dither circuit. The dither circuit adds the dither to the LSB of the output data, which is the value of the
OBIT1-0 pins, by DITHER pin = “H” regardless of the SRC mode or the SRC bypass mode.
■ System Reset
Bringing the PDN pin = “L” sets the AK4127 power-down mode and initializes the digital filter. The AK4127 should be
reset once by bringing the PDN pin = “L” when power-up. When the PDN pin = “L”, the SDTO output is “L”. The SDTO
valid time is 100ms. Until the output data becomes valid, the SDTO pin outputs “L”.
Case 1
External clocks
(Input port)
Don’t care
Input Clocks 1
Input Clocks 2
Don’t care
SDTI
Don’t care
Input Data 1
Input Data 2
Don’t care
External clocks
(Output port)
Don’t care
Output Clocks 1
Output Clocks 2
Don’t care
PDN
< 100ms
< 100ms
(Internal state) Power-down
SDTO
Normal
operation
PLL lock &
fs detection
“0” data
PD
Normal data
PLL lock &
fs detection
“0” data
Normal
operation
Power-down
Normal data
“0” data
UNLOCK
Figure 15. System Reset
Case 2
External clocks
(Input port)
(No Clock)
SDTI
External clocks
(Output port)
Input Clocks
Don’t care
(Don’t care)
Input Data
Don’t care
(Don’t care)
Output Clocks
Don’t care
PDN
< 100ms
(Internal state) Power-down
SDTO
PLL Unlock
“0” data
PLL lock &
fs detection
Normal
operation
Power-down
Normal data
“0” data
UNLOCK
Figure 16. System Reset 2
MS0593-E-01
2007/07
- 20 -
[AK4127]
■ Internal Reset Function for Clock Change
The AK4127 is reset automatically when the output clock is stopped. If the output clock is started again, normal data is
output within 100ms.
■ Sequence of Changing Clocks
The change sequence of the clock supplied to AK4127 is shown in Figure 17.
External clocks
(Input port
or Output port)
Clocks 1
Don’t care
Clocks 2
PDN pin
< 100ms
(Internal state) Normal operation Power-down PLL lock &
fs detection
SDTO
Normal data
SMUTE (Note2,
recommended)
Att.Level
Note1
Normal operation
Normal data
1024/fso
1024/fso
0dB
-∞dB
Figure 17. Sequence of changing clocks
Note 1. The data on SDTO may cause a clicking noise. To prevent this, set “0” to the SDTI from GD before the PDN
pin changes to “L”. It makes the data on SDTO remain as “0”.
Note 2. SMUTE can also be used to remove the unknown data.
■ UNLOCK pin
The UNLOCK pin outputs “L” when the internal PLL is locked. When the internal PLL is unlocked, the UNLOCK pin
outputs “H” and the SDTO = “0”. When the PDN pin = “L”, the UNLOCK pin outputs “H”.
MS0593-E-01
2007/07
- 21 -
[AK4127]
■ PLL Loop Filter
The C1 and R should be connected in series and attached between the FILT pin and AVSS in parallel with C2. Please be
careful the noise onto the FILT pin. When using IBICK, the value of external element is not dependent on the IBICK
input frequency.
AK4127
FILT
R
C2
C1
AVSS
Figure 18. PLL Loop Filter
[Input PORT in slave mode]
1. When using ILRCK
PLL2
L
PLL1
L
L
L
L
H
L
H
PLL0
L
ILRCK
R [Ω]
8k ∼ 96kHz
1.8k ± 5%
8k ∼ 216kHz
1k ± 5%
H
16k ∼ 216kHz
1.5k ± 5%
8k ∼ 216kHz
1k ± 5%
L
16k ∼ 216kHz
1.5k ± 5%
8k ∼ 216kHz
1k ± 5%
H
16k ∼ 216kHz
1.5k ± 5%
Table 6. PLL Loop Filter (ILRCK Mode)
C1 [μF]
0.68 ± 30%
1.0 ± 30%
0.68 ± 30%
1.0 ± 30%
0.68 ± 30%
1.0 ± 30%
0.68 ± 30%
C2 [nF]
0.68 ± 30%
2.2 ± 30%
0.68 ± 30%
2.2 ± 30%
0.68 ± 30%
2.2 ± 30%
0.68 ± 30%
- Note. Smaller value can be selected for the capacitors (C1, C2) in case of ILRCK range from 16kHz to 216kHz..
2. When using IBICK
PLL2
H
PLL1
*
PLL0
ILRCK
R [Ω]
C1 [μF]
*
8k ∼ 216kHz
470 ± 5%
0.22 ± 30%
Table 7. PLL Loop Filter (IBICK Mode, *: Don’t care)
C2 [nF]
1.0 ± 30%
Note. The IBCIK must be continuous except when the clocks are changed.
Note. IBCIK = 32fsi is supported only 16bit LSB justified and I2S Compatible.
[Input PORT in master mode]
1. When IMCLK is 256fs, 384fs, 512fs or 768fs, any external parts shown in Figure 18 are not required.
2. When IMCLK is 128fs or 192fs, the external parts shown in Table 7 are required.
MS0593-E-01
2007/07
- 22 -
[AK4127]
SYSTEM DESIGN
Figure 19 and Figure 20 show the system connection diagrams. The evaluation board demonstrates application circuits, the
optimum layout, power supply arrangements and measurement results.
• Input PORT: Slave Mode, IBICK lock mode (64fsi), 24bit MSB justified
• Output PORT: Slave mode, 24bit MSB justified
• Dither = OFF
470 1.0n
10μ
1 FILT
AVDD 30
2 AVSS
DVSS 29
3 PDN
DVDD 28
0.22μ
Reset
4 SMUTE
OMCLK 27
5 DITHER
OLRCK 26
64fsi
DSP, uP
7 ILRCK
AK4127
Supply
3.0 ~ 3.6V
0.1μ
OBICK 25
6 PLL2
fsi
0.1μ
fso
64fso
DSP
SDTO 24
8 IBICK
ODIF1 23
9 SDTI
ODIF0 22
10 IDIF0
CMODE2 21
11 IDIF1
CMODE1 20
12 IDIF2
CMODE0 19
13 PLL0
IMCLK 18
14 PLL1
OBIT1 17
15 UNLOCK
OBIT0 16
Note:
- AVSS and DVSS of the AK4127 must be distributed separately from the ground of external digital
devices (MPU, DSP etc.).
- All digital input pins must not be left floating.
Figure 19. Typical Connection Diagram (Slave mode)
MS0593-E-01
2007/07
- 23 -
[AK4127]
• Input PORT: Slave Mode, IBICK lock mode (64fsi), 24bit MSB justified
• Output PORT: Master mode, 24bit MSB justified
• Dither = OFF
470 1.0n
10μ
1 FILT
AVDD 30
2 AVSS
DVSS 29
3 PDN
DVDD 28
0.22μ
Reset
4 SMUTE
OMCLK 27
5 DITHER
OLRCK 26
64fsi
7 ILRCK
0.1μ
OBICK 25
6 PLL2
fsi
0.1μ
AK4127
Supply
3.0 ~ 3.6V
128fso
fso
64fso
DSP
SDTO 24
8 IBICK
ODIF1 23
9 SDTI
ODIF0 22
10 IDIF0
CMODE2 21
11 IDIF1
CMODE1 20
12 IDIF2
CMODE0 19
13 PLL0
IMCLK 18
14 PLL1
OBIT1 17
15 UNLOCK
OBIT0 16
DSP, uP
Note:
- AVSS and DVSS of the AK4127 must be distributed separately from the ground of external digital
devices (MPU, DSP etc.).
- All digital input pins must not be left floating.
Figure 20. Typical Connection Diagram (Master mode)
1. Grounding and Power Supply Decoupling
The AK4127 requires careful attention to power supply and grounding arrangements. Alternatively if AVDD and DVDD
are supplied separately, the power up sequence is not important. Decoupling capacitors should be as near to the AK4127 as
possible, with the small value ceramic capacitor being the nearest.
MS0593-E-01
2007/07
- 24 -
[AK4127]
2. Jitter Tolerance
Figure 21shows the jitter tolerance to ILRCK and IBICK. The jitter quantity is defined by the jitter frequency and the jitter
amplitude shown in Figure 21. When the jitter amplitude is 0.01Uipp or less, the AK4127 operates normally regardless of
the jitter frequency.
AK4127 Jitter Tolerance
10.00
Amplitude [UIpp]
1.00
(3)
0.10
(2)
0.01
(1)
0.00
1
10
100
1000
10000
Jitter Frequency [Hz]
(1) Normal operation
(2) There is a possibility that the distortion degrades. (It may degrade up to about −50dB.)
(3) There is a possibility that the output data is lost.
Note:
- When PLL2-0 = “L/*/*” (*: Don’t care), the jitter amplitude is for ILRCK and 1UI (Unit Interval) is one cycle of
ILRCK. When FSI = 48kHz, 1UI is 1/48kHz = 20.8μs.
- When PLL2-0 = “H/*/*” (*: Don’t care), the jitter amplitude is for IBICK and 1UI (Unit Interval) is one cycle of
IBICK. When FSI = 48kHz, 1UI is 1/(64 x 48kHz) = 326ns.
Figure 21. Jitter Tolerance
Tracking to the Input Sampling Frequency
When the ILRCK is generated by an external PLL, it may take time to settle after changing the input sampling frequency
because the response of an external PLL to the frequency change is slow. The AK4127 operates normally up to 23%/sec
speed but outputs incorrect data at the speed of the frequency change over 23%/sec.
MS0593-E-01
2007/07
- 25 -
[AK4127]
3. Digital Filter Response Example
Table 8shows the examples of digital filter response performed by the AK4127.
Ratio
FSO/FSI [kHz]
4.000
1.000
0.919
0.725
0.667
0.544
0.500
0.500
0.459
0.363
0.333
0.250
0.250
0.230
0.167
0.181
0.167
0.181
192/48.0
48.0/48.0
44.1/48.0
32.0/44.1
32.0/48.0
48.0/88.2
48.0/96.0
44.1/88.2
44.1/96.0
32.0/88.2
32.0/96.0
48.0/192.0
44.1/176.4
44.1/192.0
32.0/192.0
32.0/176.4
8/48.0
8/44.1
Stopband
Attenuation [dB]
22.000
26.000
−121.2
22.000
26.000
−121.2
20.000
24.100
−121.4
14.088
17.487
−115.3
13.688
17.488
−116.9
19.250
26.232
−114.6
20.900
27.000
−100.2
19.202
24.806
−100.2
18.700
25.000
−103.3
12.863
18.665
−102.0
12.500
18.900
−103.6
17.600
30.200
−104.0
16.170
27.746
−104.0
15.860
28.240
−103.3
11.200
19.600
−73.2
10.278
17.987
−73.2
2.800
4.900
−73.2
2.5695
4.4968
−73.2
Table 8. Digital Filter Example
Passband [kHz]
Stopband [kHz]
MS0593-E-01
Gain [dB]
−0.01@ 20k
−0.01@ 20k
−0.01@ 20k
−0.01@ 14.5k
−0.19@ 14.5k
−0.03@ 20k
−0.01@ 20k
−0.08@ 20k
−0.23@ 20k
−0.75@ 14.5k
−1.07@ 14.5k
−0.18@ 20k
−1.34@ 20k
−1.40@ 20k
−2.97@ 14.5k
−7.88@ 14.5k
−2.97@ 3.625k
−7.88@ 3.625k
2007/07
- 26 -
[AK4127]
PACKAGE
30pin VSOP (Unit: mm)
1.5MAX
*9.7±0.1
0.3
30
16
15
1
0.22±0.1
7.6±0.2
5.6±0.1
A
0.15 +0.10
-0.05
0.65
0.12 M
0.45±0.2
+0.10
0.08
0.10 -0.05
1.2±0.10
Detail A
NOTE: Dimension "*" does not include mold flash.
■ Material & Lead finish
Package molding compound:
Lead frame material:
Lead frame surface treatment:
Epoxy
Cu
Solder (Pb free) plate
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[AK4127]
MARKING
AKM
AK4127VF
XXXBYYYYC
XXXBYYYYC
Date code identifier
XXXB: Lot number (X: Digit number, B: Alpha character)
YYYYC: Assembly date (Y: Digit number, C: Alpha character)
REVISION HISTORY
Date (YY/MM/DD)
07/02/07
Revision
00
07/07/26
01
Reason
First edition
Description
Change
Page
Contents
19
Figure 13 and Figure 14 were changed.
21
■ Internal Rest Function for Clock Change
■ Sequence of Changing Clocks
■ UNLOCK pin
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[AK4127]
IMPORTANT NOTICE
z These products and their specifications are subject to change without notice.
When you consider any use or application of these products, please make inquiries the sales office of Asahi Kasei
EMD Corporation (AKEMD) or authorized distributors as to current status of the products.
z AKEMD assumes no liability for infringement of any patent, intellectual property, or other rights in the application or
use of any information contained herein.
z Any export of these products, or devices or systems containing them, may require an export license or other official
approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or
strategic materials.
z AKEMD products are neither intended nor authorized for use as critical componentsNote1) in any safety, life support, or
other hazard related device or systemNote2), and AKEMD assumes no responsibility for such use, except for the use
approved with the express written consent by Representative Director of AKEMD. As used here:
Note1) A critical component is one whose failure to function or perform may reasonably be expected to result,
whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and
which must therefore meet very high standards of performance and reliability.
Note2) A hazard related device or system is one designed or intended for life support or maintenance of safety or
for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform
may reasonably be expected to result in loss of life or in significant injury or damage to person or property.
z It is the responsibility of the buyer or distributor of AKEMD products, who distributes, disposes of, or otherwise places
the product with a third party, to notify such third party in advance of the above content and conditions, and the buyer
or distributor agrees to assume any and all responsibility and liability for and hold AKEMD harmless from any and all
claims arising from the use of said product in the absence of such notification.
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2007/07
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