INTERSIL EL5211A

EL5211A
®
Data Sheet
June 15, 2005
60MHz Rail-to-Rail Input-Output Op Amp
Features
The EL5211A is a low power, high voltage, rail-to-rail inputoutput amplifier containing two amplifiers. Operating on
supplies ranging from 5V to 15V, while consuming only
2.5mA per amplifier, the EL5211A has a bandwidth of
60MHz (-3dB) and provides common-mode input ability
beyond the supply rails, as well as rail-to-rail output
capability. This enables the EL5211A to offer maximum
dynamic range at any supply voltage.
• 60MHz -3dB bandwidth
The EL5211A also features fast slewing and settling times,
as well as a high output drive capability of 65mA (sink and
source). These features make the EL5211A ideal for high
speed filtering and signal conditioning application. Other
applications include battery-powered, portable devices and
anywhere low power consumption is important.
• Rail-to-rail output swing
The EL5211A is available in the 8-pin HMSOP package,
features a standard operational amplifier pinout, and is
specified for operation over a temperature range of -40°C to
+85°C.
• TFT-LCD panels
• Supply voltage = 4.5V to 16.5V
• Low supply current (per amplifier) = 2.5mA
• High slew rate = 75V/µs
• Unity-gain stable
• Beyond the rails input capability
• ±110mA output short current
• Pb-free plus anneal available (RoHS compliant)
Applications
• VCOM amplifiers
• Drivers for A-to-D converters
• Data acquisition
Ordering Information
PART NUMBER
(See Note)
FN6143.0
• Video processing
PACKAGE
(Pb-Free)
TAPE &
REEL
PKG. DWG. #
EL5211AIYEZ
8-Pin HMSOP
-
MDP0050
• Active filters
EL5211AIYEZ-T7
8-Pin HMSOP
7”
MDP0050
• Test equipment
EL5211AIYEZ-T13
8-Pin HMSOP
13”
MDP0050
• Battery-powered applications
NOTE: Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100%
matte tin plate termination finish, which are RoHS compliant and
compatible with both SnPb and Pb-free soldering operations. Intersil
Pb-free products are MSL classified at Pb-free peak reflow
temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.
• Audio processing
• Portable equipment
Pinout
EL5211A
(8-PIN HMSOP)
TOP VIEW
VOUTA 1
VINA- 2
VINA+ 3
VS- 4
1
8 VS+
7 VOUTB
+
+
6 VINB5 VINB+
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2005. All Rights Reserved.
All other trademarks mentioned are the property of their respective owners.
EL5211A
Absolute Maximum Ratings (TA = 25°C)
Supply Voltage between VS+ and VS- . . . . . . . . . . . . . . . . . . . .+18V
Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . VS- - 0.5V, VS +0.5V
Maximum Continuous Output Current . . . . . . . . . . . . . . . . . . . 65mA
Maximum Die Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . +125°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Ambient Operating Temperature . . . . . . . . . . . . . . . .-40°C to +85°C
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Curves
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typ values are for information purposes only. Unless otherwise noted, all tests are
at the specified temperature and are pulsed tests, therefore: TJ = TC = TA
Electrical Specifications
PARAMETER
VS+ = +5V, VS- = -5V, RL = 1kΩ to 0V, TA = 25°C, unless otherwise specified
DESCRIPTION
CONDITIONS
MIN
TYP
MAX
UNIT
3
15
mV
INPUT CHARACTERISTICS
VOS
Input Offset Voltage
TCVOS
Average Offset Voltage Drift (Note 1)
IB
Input Bias Current
RIN
Input Impedance
1
GΩ
CIN
Input Capacitance
2
pF
CMIR
Common-Mode Input Range
CMRR
Common-Mode Rejection Ratio
for VIN from -5.5V to 5.5V
50
70
dB
AVOL
Open-Loop Gain
-4.5V ≤ VOUT ≤ 4.5V
60
70
dB
VCM = 0V
7
VCM = 0V
2
-5.5
µV/°C
60
+5.5
nA
V
OUTPUT CHARACTERISTICS
VOL
Output Swing Low
IL = -5mA
VOH
Output Swing High
IL = 5mA
ISC
IOUT
-4.9
4.8
-4.8
V
4.9
V
Short-Circuit Current
±125
mA
Output Current
±65
mA
80
dB
POWER SUPPLY PERFORMANCE
PSRR
Power Supply Rejection Ratio
VS is moved from ±2.25V to ±7.75V
IS
Supply Current
No load
5
60
7.5
mA
DYNAMIC PERFORMANCE
SR
Slew Rate (Note 2)
-4.0V ≤ VOUT ≤ 4.0V, 20% to 80%
75
V/µs
tS
Settling to +0.1% (AV = +1)
(AV = +1), VO = 2V step
80
ns
BW
-3dB Bandwidth
60
MHz
GBWP
Gain-Bandwidth Product
32
MHz
PM
Phase Margin
50
°
CS
Channel Separation
f = 5MHz
110
dB
dG
Differential Gain (Note 3)
RF = RG = 1kΩ and VOUT = 1.4V
0.17
%
dP
Differential Phase (Note 3)
RF = RG = 1kΩ and VOUT = 1.4V
0.24
°
NOTES:
1. Measured over operating temperature range.
2. Slew rate is measured on rising and falling edges.
3. NTSC signal generator used.
2
FN6143.0
June 15, 2005
EL5211A
Electrical Specifications
PARAMETER
VS+ = +5V, VS- = 0V, RL = 1kΩ to 2.5V, TA = 25°C, unless otherwise specified
DESCRIPTION
CONDITION
MIN
TYP
MAX
UNIT
3
15
mV
INPUT CHARACTERISTICS
VOS
Input Offset Voltage
TCVOS
Average Offset Voltage Drift (Note 4)
IB
Input Bias Current
RIN
Input Impedance
1
GΩ
CIN
Input Capacitance
2
pF
CMIR
Common-Mode Input Range
CMRR
Common-Mode Rejection Ratio
for VIN from -0.5V to 5.5V
45
66
dB
AVOL
Open-Loop Gain
0.5V ≤ VOUT ≤ 4.5V
60
70
dB
VCM = 2.5V
7
VCM = 2.5V
2
-0.5
µV/°C
60
+5.5
nA
V
OUTPUT CHARACTERISTICS
VOL
Output Swing Low
IL = -5mA
VOH
Output Swing High
IL = 5mA
ISC
IOUT
100
4.8
200
mV
4.9
V
Short-Circuit Current
±125
mA
Output Current
±65
mA
80
dB
POWER SUPPLY PERFORMANCE
PSRR
Power Supply Rejection Ratio
VS is moved from 4.5V to 15.5V
IS
Supply Current
No load
5
60
7.5
mA
DYNAMIC PERFORMANCE
SR
Slew Rate (Note 5)
1V ≤ VOUT ≤ 4V, 20% to 80%
75
V/µs
tS
Settling to +0.1% (AV = +1)
(AV = +1), VO = 2V step
80
ns
BW
-3dB Bandwidth
60
MHz
GBWP
Gain-Bandwidth Product
32
MHz
PM
Phase Margin
50
°
CS
Channel Separation
f = 5MHz
110
dB
dG
Differential Gain (Note 6)
RF = RG = 1kΩ and VOUT = 1.4V
0.17
%
dP
Differential Phase (Note 6)
RF = RG = 1kΩ and VOUT = 1.4V
0.24
°
NOTES:
4. Measured over operating temperature range.
5. Slew rate is measured on rising and falling edges.
6. NTSC signal generator used.
Electrical Specifications
PARAMETER
VS+ = +15V, VS- = 0V, RL = 1kΩ to 7.5V, TA = 25°C, unless otherwise specified
DESCRIPTION
CONDITION
MIN
TYP
MAX
UNIT
3
15
mV
INPUT CHARACTERISTICS
VOS
Input Offset Voltage
TCVOS
Average Offset Voltage Drift (Note 7)
IB
Input Bias Current
RIN
Input Impedance
1
GΩ
CIN
Input Capacitance
2
pF
CMIR
Common-Mode Input Range
3
VCM = 7.5V
7
VCM = 7.5V
2
-0.5
µV/°C
60
+15.5
nA
V
FN6143.0
June 15, 2005
EL5211A
Electrical Specifications
PARAMETER
VS+ = +15V, VS- = 0V, RL = 1kΩ to 7.5V, TA = 25°C, unless otherwise specified (Continued)
DESCRIPTION
CONDITION
MIN
TYP
MAX
UNIT
CMRR
Common-Mode Rejection Ratio
for VIN from -0.5V to 15.5V
53
72
dB
AVOL
Open-Loop Gain
0.5V ≤ VOUT ≤ 14.5V
60
70
dB
OUTPUT CHARACTERISTICS
VOL
Output Swing Low
IL = -5mA
VOH
Output Swing High
IL = 5mA
ISC
IOUT
100
14.8
200
mV
14.9
V
Short-Circuit Current
±125
mA
Output Current
±65
mA
80
dB
POWER SUPPLY PERFORMANCE
PSRR
Power Supply Rejection Ratio
VS is moved from 4.5V to 15.5V
IS
Supply Current
No load
5
60
7.5
mA
DYNAMIC PERFORMANCE
SR
Slew Rate (Note 8)
1V ≤ VOUT ≤ 14V, 20% to 80%
75
V/µs
tS
Settling to +0.1% (AV = +1)
(AV = +1), VO = 2V step
80
ns
BW
-3dB Bandwidth
60
MHz
GBWP
Gain-Bandwidth Product
32
MHz
PM
Phase Margin
50
°
CS
Channel Separation
f = 5MHz
110
dB
dG
Differential Gain (Note 9)
RF = RG = 1kΩ and VOUT = 1.4V
0.16
%
dP
Differential Phase (Note 9)
RF = RG = 1kΩ and VOUT = 1.4V
0.22
°
NOTES:
7. Measured over operating temperature range
8. Slew rate is measured on rising and falling edges
9. NTSC signal generator used
Typical Performance Curves
TYPICAL
PRODUCTION
DISTRIBUTION
300
200
100
25
VS=±5V
TYPICAL
PRODUCTION
DISTRIBUTION
20
15
10
5
FIGURE 1. INPUT OFFSET VOLTAGE DISTRIBUTION
4
21
19
17
15
13
11
9
7
5
12
8
10
6
4
2
-0
-2
-4
-6
-8
-10
-12
INPUT OFFSET VOLTAGE (mV)
3
0
0
1
400
VS=±5V
TA=25°C
QUANTITY (AMPLIFIERS)
QUANTITY (AMPLIFIERS)
500
INPUT OFFSET VOLTAGE DRIFT, TCVOS (µV/°C)
FIGURE 2. INPUT OFFSET VOLTAGE DRIFT
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June 15, 2005
EL5211A
Typical Performance Curves (Continued)
0.008
INPUT BIAS CURRENT (µA)
INPUT OFFSET VOLTAGE (mV)
2
1.5
1
0.5
0
-0.5
-50
-10
30
70
110
VS=±5V
0.004
0
-0.004
-0.008
-0.012
-50
150
-10
TEMPERATURE (°C)
4.92
4.90
4.88
-10
30
70
110
-4.85
150
VS=±5V
IOUT=5mA
-4.87
-4.89
-4.91
-4.93
-4.95
-50
150
-10
TEMPERATURE (°C)
30
70
110
150
TEMPERATURE (°C)
FIGURE 5. OUTPUT HIGH VOLTAGE vs TEMPERATURE
FIGURE 6. OUTPUT LOW VOLTAGE vs TEMPERATURE
78
75
VS=±5V
RL=1kΩ
VS=±5V
77
SLEW RATE (V/µs)
OPEN-LOOP GAIN (dB)
110
FIGURE 4. INPUT BIAS CURRENT vs TEMPERATURE
OUTPUT LOW VOLTAGE (V)
OUTPUT HIGH VOLTAGE (V)
VS=±5V
IOUT=5mA
4.94
4.86
-50
70
TEMPERATURE (°C)
FIGURE 3. INPUT OFFSET VOLTAGE vs TEMPERATURE
4.96
30
70
65
76
75
74
73
60
-50
-10
30
70
110
150
TEMPERATURE (°C)
FIGURE 7. OPEN-LOOP GAIN vs TEMPERATURE
5
72
-50
-10
30
70
110
150
TEMPERATURE (°C)
FIGURE 8. SLEW RATE vs TEMPERATURE
FN6143.0
June 15, 2005
EL5211A
Typical Performance Curves (Continued)
2.7
TA=25°C
2.7
SUPPLY CURRENT (mA)
2.5
2.3
2.1
1.9
1.7
1.5
4
8
12
16
VS=±5V
2.65
2.6
2.55
2.5
2.45
2.4
-50
20
-10
FIGURE 9. SUPPLY CURRENT PER AMPLIFIER vs SUPPLY
VOLTAGE
110
150
FIGURE 10. SUPPLY CURRENT PER AMPLIFIER vs
TEMPERATURE
0
0.3
DIFFERENTIAL PHASE (°)
-0.02
-0.04
-0.06
-0.08
-0.1
-0.12
-0.14 V =±5V
S
-0.16 AV=2
RL=1kΩ
-0.18
0
0.25
0.2
0.15
0.1
0.05
0
100
200
0
100
IRE
FIGURE 12. DIFFERENTIAL PHASE
-30
GAIN (dB)
GAIN
2nd HD
-70
-90
4
6
8
10
VOP-P (V)
FIGURE 13. HARMONIC DISTORTION vs VOP-P
6
40
20
130
PHASE
70
10
0
3rd HD
2
190
60
-60
0
250
80
VS=±5V
AV=2
-40 R =1kΩ
L
FREQ=1MHz
-50
-80
200
IRE
FIGURE 11. DIFFERENTIAL GAIN
DISTORTION (dB)
70
TEMPERATURE (°C)
SUPPLY VOLTAGE (V)
DIFFERENTIAL GAIN (%)
30
-20
1K
PHASE (°)
SUPPLY CURRENT (mA)
2.9
10K
100K
1M
10M
-50
100M
FREQUENCY (Hz)
FIGURE 14. OPEN LOOP GAIN AND PHASE
FN6143.0
June 15, 2005
EL5211A
MAGNITUDE (NORMALIZED) (dB)
5
3
VS=±5V
AV=1
CLOAD=0pF
MAGNITUDE (NORMALIZED) (dB)
Typical Performance Curves (Continued)
1kΩ
1
-1
560Ω
-3
150Ω
-5
100K
1M
100pF
15
1000pF
47pF
10pF
5
-5
-15
VS=±5V
AV=1
RL=1kΩ
-25
100K
100M
10M
25
1M
FREQUENCY (Hz)
FIGURE 16. FREQUENCY RESPONSE FOR VARIOUS CL
MAXIMUM OUTPUT SWING (VP-P)
OUTPUT IMPEDANCE (Ω)
400
350
300
250
200
150
100
50
100K
1M
100M
FREQUENCY (Hz)
FIGURE 15. FREQUENCY RESPONSE FOR VARIOUS RL
0
10K
10M
10M
100M
12
10
8
6
4
VS=±5V
2 AV=1
RL=1kΩ
DISTORTION <1%
0
10K
100K
FREQUENCY (Hz)
1M
10M
100M
FREQUENCY (kHz)
FIGURE 17. CLOSED LOOP OUTPUT IMPEDANCE
FIGURE 18. MAXIMUM OUTPUT SWING vs FREQUENCY
-15
-80
PSRR+
-35
-45
-40
-20
-55
-65
1K
PSRR-
-60
PSRR (dB)
CMRR (dB)
-25
VS=±5V
TA=25°C
10K
100K
1M
FREQUENCY (Hz)
FIGURE 19. CMRR
7
10M
100M
0
100
1K
10K
100K
1M
10M
FREQUENCY (Hz)
FIGURE 20. PSRR
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June 15, 2005
EL5211A
Typical Performance Curves (Continued)
-60
DUAL MEASURED CH A TO B
QUAD MEASURED CH A TO D OR B TO C
-80 OTHER COMBINATIONS YIELD
IMPROVED REJECTION
100
XTALK (dB)
VOLTAGE NOISE (nV/√Hz)
1K
10
-100
-120
VS=±5V
RL=1kΩ
AV=1
VIN=110mVRMS
-140
1
100
1K
10K
100K
1M
10M
-160
1K
100M
10K
100K
FREQUENCY (Hz)
10M 30M
FREQUENCY (Hz)
FIGURE 21. INPUT VOLTAGE NOISE SPECTRAL DENSITY
FIGURE 22. CHANNEL SEPARATION
5
100
VS=±5V
4 A =1
V
3 RL=1kΩ
VS=±5V
AV=1
80 RL=1kΩ
VIN=±50mV
TA=25°C
60
STEP SIZE (V)
OVERSHOOT (%)
1M
40
0.1%
2
1
0
-1
-2
0.1%
-3
20
-4
0
10
100
1K
LOAD CAPACITANCE (pF)
FIGURE 23. SMALL-SIGNAL OVERSHOOT vs LOAD
CAPACITANCE
-5
55
65
75
85
95
105
SETTLING TIME (ns)
FIGURE 24. SETTLING TIME vs STEP SIZE
VS=±5V
TA=25°C
AV=1
RL=1kΩ
VS=±5V
TA=25°C
AV=1
RL=1kΩ
100mV STEP
1V STEP
50ns/DIV
FIGURE 25. LARGE SIGNAL TRANSIENT RESPONSE
8
50ns/DIV
FIGURE 26. SMALL SIGNAL TRANSIENT RESPONSE
FN6143.0
June 15, 2005
EL5211A
Pin Descriptions
PIN NUMBER
PIN NAME
1
VOUTA
FUNCTION
EQUIVALENT CIRCUIT
Amplifier A output
VS+
VS-
GND
CIRCUIT 1
2
VINA-
Amplifier A inverting input
VS+
VS-
CIRCUIT 2
3
VINA+
Amplifier A non-inverting input
(Reference Circuit 2)
4
VS-
5
VINB+
Amplifier B non-inverting input
(Reference Circuit 2)
6
VINB-
Amplifier B inverting input
(Reference Circuit 2)
7
VOUTB
Amplifier B output
(Reference Circuit 1)
8
VS+
Negative power supply
Positive power supply
Product Description
The EL5211A voltage feedback amplifier is fabricated using
a high voltage CMOS process. It exhibits rail-to-rail input and
output capability, is unity gain stable, and has low power
consumption (2.5mA per amplifier). These features make
the EL5211A ideal for a wide range of general-purpose
applications. Connected in voltage follower mode and driving
a load of 1kΩ, the EL5211A has a -3dB bandwidth of 60MHz
while maintaining a 75V/µs slew rate. The EL5211A is a dual
amplifier.
range even closer to the supply rails. Figure 27 shows the
input and output waveforms for the device in the unity-gain
configuration. Operation is from ±5V supply with a 1kΩ load
connected to GND. The input is a 10VP-P sinusoid. The
output voltage is approximately 9.8VP-P.
5V
10µs
INPUT
Applications Information
The EL5211A is specified with a single nominal supply
voltage from 5V to 15V or a split supply with its total range
from 5V to 15V. Correct operation is guaranteed for a supply
range of 4.5V to 16.5V. Most EL5211A specifications are
stable over both the full supply range and operating
temperatures of -40°C to +85°C. Parameter variations with
operating voltage and/or temperature are shown in the
typical performance curves.
The input common-mode voltage range of the EL5211A
extends 500mV beyond the supply rails. The output swings
of the EL5211A typically extend to within 100mV of positive
and negative supply rails with load currents of 5mA.
Decreasing load currents will extend the output voltage
9
5V
VS=±5V
TA=25°C
AV=1
VIN=10VP-P
OUTPUT
Operating Voltage, Input, and Output
FIGURE 27. OPERATION WITH RAIL-TO-RAIL INPUT AND
OUTPUT
Short Circuit Current Limit
The EL5211A will limit the short circuit current to ±110mA if
the output is directly shorted to the positive or the negative
supply. If an output is shorted indefinitely, the power
dissipation could easily increase such that the device may
be damaged. Maximum reliability is maintained if the output
FN6143.0
June 15, 2005
EL5211A
continuous current never exceeds ±65mA. This limit is set by
the design of the internal metal interconnects.
Output Phase Reversal
The EL5211A is immune to phase reversal as long as the
input voltage is limited from VS- -0.5V to VS+ +0.5V. Figure
28 shows a photo of the output of the device with the input
voltage driven beyond the supply rails. Although the device's
output will not change phase, the input's overvoltage should
be avoided. If an input voltage exceeds supply voltage by
more than 0.6V, electrostatic protection diodes placed in the
input stage of the device begin to conduct and overvoltage
damage could occur.
when sourcing, and:
P DMAX = Σi [ V S × I SMAX + ( V OUT i – V S - ) × I LOAD i ]
when sinking,
where:
• i = 1 to 2 for dual and 1 to 4 for quad
• VS = Total supply voltage
• ISMAX = Maximum supply current per amplifier
• VOUTi = Maximum output voltage of the application
• ILOADi = Load current
1V
10µs
VS=±2.5V
TA=25°C
AV=1
VIN=6VP-P
1V
If we set the two PDMAX equations equal to each other, we
can solve for RLOADi to avoid device overheat. Figures 29
and 30 provide a convenient way to see if the device will
overheat. The maximum safe power dissipation can be
found graphically, based on the package type and the
ambient temperature. By using the previous equation, it is a
simple matter to see if PDMAX exceeds the device's power
derating curves. To ensure proper operation, it is important
to observe the recommended derating curves shown in
Figures 29 and 30.
FIGURE 28. OPERATION WITH BEYOND-THE-RAILS INPUT
With the high-output drive capability of the EL5211A
amplifier, it is possible to exceed the 125°C 'absolutemaximum junction temperature' under certain load current
conditions. Therefore, it is important to calculate the
maximum junction temperature for the application to
determine if load conditions need to be modified for the
amplifier to remain in the safe operating area.
POWER DISSIPATION (W)
Power Dissipation
0.6
486mW
0.5
0.4
θ
JA
=
0.3
HM
SO
P8
20
6°
C/
W
0.2
0.1
0
The maximum power dissipation allowed in a package is
determined according to:
T JMAX – T AMAX
P DMAX = --------------------------------------------Θ JA
JEDEC JESD51-3 LOW EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD
0
25
50
75 85
100
125
AMBIENT TEMPERATURE (°C)
FIGURE 29. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
where:
• TAMAX = Maximum ambient temperature
• ΘJA = Thermal resistance of the package
• PDMAX = Maximum power dissipation in the package
The maximum power dissipation actually produced by an IC
is the total quiescent supply current times the total power
supply voltage, plus the power in the IC due to the loads, or:
P DMAX = Σi [ V S × I SMAX + ( V S + – V OUT i ) × I LOAD i ]
POWER DISSIPATION (W)
1
• TJMAX = Maximum junction temperature
JEDEC JESD51-7 HIGH EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD
870mW
0.9
0.8
0.7
θ
JA
0.6
0.5
HM
S
=1 OP
8
15
°C
/W
0.4
0.3
0.2
0.1
0
0
25
50
75 85
100
125
AMBIENT TEMPERATURE (°C)
FIGURE 30. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
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EL5211A
Unused Amplifiers
It is recommended that any unused amplifiers in a dual and
a quad package be configured as a unity gain follower. The
inverting input should be directly connected to the output
and the non-inverting input tied to the ground plane.
Power Supply Bypassing and Printed Circuit
Board Layout
The EL5211A can provide gain at high frequency. As with
any high-frequency device, good printed circuit board layout
is necessary for optimum performance. Ground plane
construction is highly recommended, lead lengths should be
as short as possible and the power supply pins must be well
bypassed to reduce the risk of oscillation. For normal single
supply operation, where the VS- pin is connected to ground,
a 0.1µF ceramic capacitor should be placed from VS+ to pin
to VS- pin. A 4.7µF tantalum capacitor should then be
connected in parallel, placed in the region of the amplifier.
One 4.7µF capacitor may be used for multiple devices. This
same capacitor combination should be placed at each
supply pin to ground if split supplies are to be used.
Package Outline Drawing
NOTE: The package drawing shown here may not be the latest version. To check the latest revision, please refer to the Intersil website at
http://www.intersil.com/design/packages/index.asp
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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