INTERSIL ISL97536

ISL97536
®
Data Sheet
October 5, 2006
Monolithic 1A Step-Down Regulator with
Low Quiescent Current
The ISL97536 is a synchronous, integrated FET 1A
step-down regulator with internal compensation. It operates
with an input voltage range from 2.5V to 6V, which
accommodates supplies of 3.3V, 5V, or a Li-Ion battery
source. The output can be externally set from 0.8V to VIN
with a resistive divider.
The ISL97536 features PWM control with a 1.4MHz typical
switching frequency. The typical no load quiescent current is
only 500µA. Additional features include a 100ms Power-OnReset output, <1µA shutdown current, short-circuit
protection, and over-temperature protection.
FN6279.0
Features
• Less than 0.15in2 footprint for the complete 1A converter
• Components on one side of PCB
• Max height 1.1mm MSOP10
• 100ms Power-On-Reset output (POR)
• Internally-compensated voltage mode controller
• Up to 95% efficiency
• <1µA shutdown current
• 500µA quiescent current
• Hiccup mode overcurrent and over-temperature protection
The ISL97536 is available in the 10 Ld MSOP package,
making the entire converter occupy less than 0.15in2 of PCB
area with components on one side only. The 10 Ld MSOP
package is specified for operation over the full -40°C to
+85°C temperature range.
• Pb-free plus anneal available (RoHS compliant)
Ordering Information
• Cellular phones
PART
NUMBER
ISL97536IUZ
(Note)
PART
MARKING
7536Z
ISL97536IUZ-TK 7536Z
(Note)
ISL97536IUZ-T
(Note)
TAPE &
REEL
7536Z
-
PACKAGE
PKG.
DWG. #
10 Ld MSOP MDP0043
(Pb-free)
13”
10 Ld MSOP MDP0043
(1k pcs) (Pb-free)
Applications
• PDA and pocket PC computers
• Bar code readers
• Portable test equipment
• Li-Ion battery powered devices
• Small form factor (SFP) modules
Pinout and Typical Application Diagram
ISL97536
(10 LD MSOP)
TOP VIEW
13”
10 Ld MSOP MDP0043
(2.5k pcs) (Pb-free)
NOTE: Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100%
matte tin plate termination finish, which are RoHS compliant and
compatible with both SnPb and Pb-free soldering operations. Intersil
Pb-free products are MSL classified at Pb-free peak reflow
temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.
C1
10µF
VO ([email protected])
VS (2.5V-6V)
C2
10µF
L1
1.8µH
R3
100Ω
C3
0.1µF
1 SGND
FB 10
2 PGND
VO 9
3 LX
POR 8
R2*
100kΩ
R1*
124kΩ
C4
470pF
POR
4 VIN
EN 7
EN
5 VDD
RSI 6
RSI
R6
100kΩ
R4
100kΩ
R5
100kΩ
* VO = 0.8V * (1 + R1/R2)
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2006. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
ISL97536
Absolute Maximum Ratings (TA = +25°C)
Thermal Information
VIN, VDD, PG to SGND . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6.5V
LX to PGND . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to (VIN + +0.3V)
SYNC, EN, VO, FB to SGND . . . . . . . . . . . . . -0.3V to (VIN + +0.3V)
PGND to SGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +0.3V
Continuous Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1A
Thermal Resistance (Typical, Note 1)
θJA (°C/W)
MSOP10 Package . . . . . . . . . . . . . . . . . . . . . . . . . .
130
Operating Ambient Temperature . . . . . . . . . . . . . . . .-40°C to +85°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +125°C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typ values are for information purposes only. Unless otherwise noted, all tests are
at the specified temperature and are pulsed tests, therefore: TJ = TC = TA
Electrical Specifications
PARAMETER
VDD = VIN = VEN = 3.3V, C1 = C2 = 10µF, L = 1.8µH, VO = 1.8V (as shown in Typical Application Diagram),
TA = -40°C to +85°C unless otherwise specified.
DESCRIPTION
CONDITIONS
MIN
TYP
MAX
UNIT
790
800
810
mV
250
nA
2.5
6
V
DC CHARACTERISTICS
VFB
Feedback Input Voltage
IFB
Feedback Input Current
VIN, VDD
Input Voltage
VIN,OFF
Minimum Voltage for Shutdown
VIN falling, TA = +25°C only
2
2.2
V
VIN,ON
Maximum Voltage for Start-up
VIN rising, TA = +25°C only
2.2
2.4
V
IDD
Supply Current
VIN = VDD = 5V
400
500
µA
EN = 0, VIN = VDD = 5V
0.1
3
µA
PMOS FET Resistance
VDD = 5V, TA = +25°C
70
mΩ
RDS(ON)-NMOS NMOS FET Resistance
VDD = 5V, TA = +25°C
45
mΩ
1.5
A
RDS(ON)-PMOS
ILMAX
Current Limit
TOT,OFF
Over-temperature Threshold
T rising
145
°C
TOT,ON
Over-temperature Hysteresis
T falling
130
°C
IEN, IRSI
EN, RSI Current
VEN, VRSI = 0V and 3.3V
VEN1, VRSI1
EN, RSI Rising Threshold
VDD = 3.3V
VEN2, VRSI2
EN, RSI Falling Threshold
VDD = 3.3V
VPOR
Minimum VFB for POR, WRT Targeted
VFB Value
VFB rising
POR Voltage Drop
ISINK = 3.3mA
VOLPOR
VFB falling
-1
1
µA
2.4
V
0.8
V
95
86
%
%
35
70
mV
1.4
1.6
MHz
25
50
ns
AC CHARACTERISTICS
FPWM
PWM Switching Frequency
tRSI
Minimum RSI Pulse Width
tSS
Soft-Start Time
tPOR
Power On Reset Delay Time
2
1.25
Guaranteed by design
650
80
100
µs
120
ms
FN6279.0
October 5, 2006
ISL97536
Pin Descriptions
PIN NUMBER
PIN NAME
PIN FUNCTION
1
SGND
Negative supply for the controller stage
2
PGND
Negative supply for the power stage
3
LX
Inductor drive pin; high current digital output with average voltage equal to the regulator output voltage
4
VIN
Positive supply for the power stage
5
VDD
Power supply for the controller stage
6
RSI
Resets POR timer
7
EN
Enable
8
POR
9
VO
Output voltage sense
10
FB
Voltage feedback input; connected to an external resistor divider between VO and SGND for variable
output
Power on reset open drain output
Block Diagram
100Ω
0.1µF
VDD
INDUCTOR SHORT
VO
+
CURRENT
SENSE
10pF
C4 124k
470pF
FB
5M
+
PWM
COMPENSATION
100k
CLOCK
RAMP
GENERATOR
EN
EN
SOFTSTART
10µF
5V +
–
BANDGAP
REFERENCE
+
PWM
COMPARATOR
PFM
ON-TIME
CONTROL
+
PWM
COMPARATOR
UNDERVOLTAGE
LOCKOUT
TEMPERATURE
SENSE
SGND
VIN
P-DRIVER
LX
CONTROL
LOGIC
1.8V
0 TO 1A
10µF
N-DRIVER
+
SYNCHRONOUS
RECTIFIER
1.8µH
PGND
100k
POR
POR
POR
RSI
3
FN6279.0
October 5, 2006
ISL97536
Performance Curves and Waveforms
All waveforms are taken at VIN = 3.3V, VO = 1.8V, IO = 600mA with component values shown on page 1 at room ambient temperature, unless
otherwise noted.
100
100
90
90
80
70
VO = 3.3V
60
EFFECIENCY (%)
EFFECIENCY (%)
80
VO = 2.5V
50
VO = 1.8V
40
VO = 1.2V
30
70
30
20
10
200
400
600
800
VO = 1.2V
40
10
0
VO = 1.8V
50
20
0
VO = 2.5V
60
0
1000
0
200
400
IO (mA)
400.2
600.2
800.2
1000.2
VO = 3.3V
VO = 1.8V
-0.4
VO = 2.5V
-0.6
VO = 1.2V
-1
-1.2
200
400
-0.2
800
1000
1200
-0.4
VO = 1.8V
-0.6
-0.8
VO = 1.2V
-1
-1.2
IO (mA)
FIGURE 3. LOAD REGULATION vs IO AT 5V VIN
2
3
4
5
FIGURE 4. LOAD REGULATION vs IO AT 3.3V VIN
6
12
-0.05
10
-0.1
8
-0.15
IS (mA)
LINE REGULATION (%)
600
VO = 2.5V
IO (mA)
-0.2
VO = 1.2V
-0.25
-0.3
1000
0
-0.2
-0.8
0
1200.2
LOAD REGULATION (%)
LOAD REGULATION (%)
200.2
800
FIGURE 2. EFFICIENCY vs IO AT 3.3V
FIGURE 1. EFFICIENCY vs IO AT 5V VIN
0.2
0
600
IO (mA)
6
4
2
VO = 1.8V
0
-0.35
2.5
VIN (V)
FIGURE 5. LINE REGULATION vs VIN
4
3
3.5
4
4.5
5
VS (V)
FIGURE 6. NO LOAD QUIESCENT CURRENT
FN6279.0
October 5, 2006
ISL97536
Performance Curves and Waveforms
(Continued)
All waveforms are taken at VIN = 3.3V, VO = 1.8V, IO = 600mA with component values shown on page 1 at room ambient temperature, unless
otherwise noted.
LX
(2V/DIV)
VOUT
IL
(0.5A/DIV)
VIN
∆VO
(10mV/DIV)
IIN
0.5µs/DIV
FIGURE 8. PWM STEADY-STATE OPERATION (IO = 600mA)
FIGURE 7. START-UP AT IO = 600mA
SYNC
(2V/DIV)
SYNC
(2V/DIV)
LX
(2V/DIV)
IL
(0.5A/DIV)
LX
(2V/DIV)
IL
(0.5A/DIV)
20ns/DIV
0.2µs/DIV
FIGURE 9. EXTERNAL SYNCHRONIZATION TO 2MHz
FIGURE 10. EXTERNAL SYNCHRONIZATION TO 12MHz
IO
(200mA/DIV)
IO
(200mA/DIV)
∆VO
(100mV/DIV)
∆VO
(100mV/DIV)
100µs/DIV
FIGURE 11. LOAD TRANSIENT RESPONSE (22mA TO 600mA)
5
50µs/DIV
FIGURE 12. LOAD TRANSIENT RESPONSE
(30mA TO 600mA)
FN6279.0
October 5, 2006
ISL97536
Performance Curves and Waveforms
(Continued)
All waveforms are taken at VIN = 3.3V, VO = 1.8V, IO = 600mA with component values shown on page 1 at room ambient temperature, unless
otherwise noted.
1
100
12MHz
1.4MHz
0.6
5MHz
60
VO CHANGES (%)
EFFICIENCY (%)
80
12MHz
40
5MHz
0
-0.2
20
0
1.4MHz
0.2
-0.6
0
200
400
600
800
1K
1.2K
0
200
400
600
800
1K
1.2K
IO (mA)
IO (mA)
FIGURE 13. EFFICIENCY vs IO
FIGURE 14. LOAD REGULATION
PG
0.5
VO CHANGES (%)
0.3
12MHz
0.1
IL
1.4MHz
-0.1
-0.5
VO
5MHz
-0.3
0
200
400
600
800
1K
1.2K
VIN (V)
FIGURE 15. LINE REGULATION @ 500mA
FIGURE 16. OVERCURRENT SHUTDOWN
PG
IL
VO
FIGURE 17. OVERCURRENT HICCUP MODE
6
FN6279.0
October 5, 2006
ISL97536
Applications Information
Product Description
The ISL97536 is a synchronous, integrated FET 1A
step-down regulator which operates from an input of 2.5V to
6V. The output voltage is user-adjustable with a pair of
external resistors.
The internally-compensated controller makes it possible to
use only two ceramic capacitors and one inductor to form a
complete, very small footprint 1A DC:DC converter.
PWM Operation
In PWM switching mode, the P-channel MOSFET and
N-channel MOSFET always operate complementary. When
the P-channel MOSFET is on and the N-channel MOSFET
off, the inductor current increases linearly. The input energy
is transferred to the output and also stored in the inductor.
When the P-channel MOSFET is off and the N-channel
MOSFET on, the inductor current decreases linearly, and
energy is transferred from the inductor to the output. Hence,
the average current through the inductor is the output
current. Since the inductor and the output capacitor act as a
low pass filter, the duty cycle ratio is approximately equal to
VO divided by VIN.
The output LC filter has a second order effect. To maintain
the stability of the converter, the overall controller must be
compensated. This is done with the fixed internally
compensated error amplifier and the PWM compensator.
Because the compensations are fixed, the values of input
and output capacitors are 10µF to 40µF ceramic and
inductor is 1.5µH to 2.2µH.
Start-Up and Shutdown
When the EN pin is tied to VIN, and VIN reaches
approximately 2.4V, the regulator begins to switch. The
inductor current limit is gradually increased to ensure proper
soft-start operation.
When the EN pin is connected to a logic low, the ISL97536 is
in the shutdown mode. All the control circuitry and both
MOSFETs are off, and VOUT falls to zero. In this mode, the
total input current is less than 1µA.
When the EN reaches logic HI, the regulator repeats the
start-up procedure, including the soft-start function.
Current Limit and Short-Circuit Protection
The current limit is set at about 1.5A for the PMOS. When a
short-circuit occurs in the load, the preset current limit
restricts the amount of current available to the output, which
causes the output voltage to drop as load demand
increases. When the output voltage drops 30mV below the
reference voltage, the converter will shutdown for a period of
time, approximated by Equation 1, and then restart. If the
overcurrent condition still exists, it will repeat the shutdownwait-restart event. This is called a “hiccup” event. The
7
average power dissipation is reduced, thereby reducing the
likelihood of damage current and thermal conditions in the IC.
700µ ⋅ V IN
tHICCUP ≈ ⎛ --------------------------- + 216µ⎞
⎝
⎠
3
(EQ. 1)
Thermal Shutdown
Once the junction reaches about 145°C, the regulator shuts
down. Both the P-channel and the N-channel MOSFETs turn
off. The output voltage will drop to zero. With the output
MOSFETs turned off, the regulator will cool down. Once the
junction temperature drops to about 130°C, the regulator will
perform a normal restart.
Thermal Performance
The ISL97536 is available in a fused-lead MSOP10.
Compared with regular MSOP10 package, the fused-lead
package provides lower thermal resistance. The θJA is
+100°C/W on a 4-layer board and +125°C/W on 2-layer
board. Maximizing the copper area around the pins will
further improve the thermal performance.
RSI/POR Function
When powering up, the open-collector Power-On-Reset
output holds low for about 100ms after VO reaches the
preset voltage. When the active-HI reset signal RSI is
issued, POR goes to low immediately and holds for the
same period of time after RSI comes back to LOW. The
output voltage is unaffected. (Please refer to the timing
diagram). When the function is not used, connect RSI to
ground and leave open the pull-up resister R4 at POR pin.
The POR output also serves as a 100ms delayed Power
Good signal when the pull-up resister R4 is installed. The
RSI pin needs to be directly (or indirectly through a resister
R6) connected to Ground for this to function properly.
VO
MIN
25ns
RSI
100ms
100ms
POR
FIGURE 18. RSI AND POR TIMING DIAGRAM
Output Voltage Selection
Users can set the output voltage of the variable version with
a resister divider, which can be chosen based on the
following formula:
R ⎞
⎛
V O = 0.8 × ⎜ 1 + ------2-⎟
R 1⎠
⎝
(EQ. 2)
FN6279.0
October 5, 2006
ISL97536
Component Selection
Because of the fixed internal compensation, the component
choice is relatively narrow. For a regulator with fixed output
voltage, only two capacitors and one inductor are required.
Capacitors must be chosen in the range of 10µF to 40µF,
multilayer ceramic capacitors with X5R or X7R rating for
both the input and output capacitors, and inductors in the
range of 1.5µH to 2.2µH.
The RMS current present at the input capacitor is decided by
the following formula:
V O × ( V IN – V O )
I INRMS = ----------------------------------------------- × I O
V IN
(EQ. 3)
This is about half of the output current IO for all the VO. This
input capacitor must be able to handle this current.
1
f Z = ---------------------2πR 2 C 4
(EQ. 5)
Over a normal range of R2 (~10-100k), C4 will range from
~470-4700pF. The pole frequency cannot be set once the
zero frequency is chosen as it is dictated by the ratio of R1
and R2, which is solely determined by the desired output set
point. The equation below shows the pole frequency
relationship:
1
f P = --------------------------------------2π ( R 1 R 2 )C 4
(EQ. 6)
Layout Considerations
The layout is very important for the converter to function
properly. The following PC layout guidelines should be
followed:
The inductor peak-to-peak ripple current is given as:
( V IN – V O ) × V O
∆I IL = ------------------------------------------L × V IN × f S
lead at a frequency of ~2.5kHz. The zero will always appear
at lower frequency than the pole and follow the equation
below:
(EQ. 4)
1. Separate the Power Ground ( ) and Signal Ground
( ); connect them only at one point right at the pins
L is the inductance
fS the switching frequency (nominally 1.4MHz)
The inductor must be able to handle IO for the RMS load
current, and to assure that the inductor is reliable, it must
handle the 2A surge current that can occur during a current
limit condition.
In addition to decoupling capacitors and inductor value, it is
important to properly size the phase-lead capacitor C4
(Refer to the Typical Application Diagram). The phase-lead
capacitor creates additional phase margin in the control loop
by generating a zero and a pole in the transfer function. As a
general rule of thumb, C4 should be sized to start the phase-
8
2. Place the input capacitor as close to VIN and PGND pins
as possible
3. Make the following PC traces as small as possible:
- from LX pin to L
- from CO to PGND
4. If used, connect the trace from the FB pin to R1 and R2
as close as possible
5. Maximize the copper area around the PGND pin
6. Place several via holes under the chip to additional
ground plane to improve heat dissipation
The demo board is a good example of layout based on this
outline. Please refer to the ISL97536 Application Brief.
FN6279.0
October 5, 2006
ISL97536
Mini SO Package Family (MSOP)
0.25 M C A B
D
MINI SO PACKAGE FAMILY
(N/2)+1
N
E
MDP0043
A
E1
PIN #1
I.D.
1
B
(N/2)
e
H
C
SEATING
PLANE
SYMBOL
MSOP8
MSOP10
TOLERANCE
NOTES
A
1.10
1.10
Max.
-
A1
0.10
0.10
±0.05
-
A2
0.86
0.86
±0.09
-
b
0.33
0.23
+0.07/-0.08
-
c
0.18
0.18
±0.05
-
D
3.00
3.00
±0.10
1, 3
E
4.90
4.90
±0.15
-
E1
3.00
3.00
±0.10
2, 3
e
0.65
0.50
Basic
-
L
0.55
0.55
±0.15
-
L1
0.95
0.95
Basic
-
N
8
10
Reference
Rev. C 6/99
0.10 C
N LEADS
0.08 M C A B
b
NOTES:
1. Plastic or metal protrusions of 0.15mm maximum per side are not
included.
2. Plastic interlead protrusions of 0.25mm maximum per side are
not included.
L1
3. Dimensions “D” and “E1” are measured at Datum Plane “H”.
A
4. Dimensioning and tolerancing per ASME Y14.5M-1994.
c
SEE DETAIL "X"
A2
GAUGE
PLANE
L
A1
0.25
3° ±3°
DETAIL X
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from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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9
FN6279.0
October 5, 2006