A8733 Datasheet

A8733
Mobile Phone Xenon Photoflash Capacitor Charger
With IGBT Driver
Discontinued Product
This device is no longer in production. The device should not be
purchased for new design applications. Samples are no longer available.
Date of status change: December 10, 2012
Recommended Substitutions:
For existing customer transition, and for new customers or new applications, contact Allegro Sales.
NOTE: For detailed information on purchasing options, contact your
local Allegro field applications engineer or sales representative.
Allegro MicroSystems, Inc. reserves the right to make, from time to time, revisions to the anticipated product life cycle plan
for a product to accommodate changes in production capabilities, alternative product availabilities, or market demand. The
information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no responsibility for its use; nor for any infringements of patents or other rights of third parties which may result from its use.
A8733
Mobile Phone Xenon Photoflash Capacitor Charger
With IGBT Driver
Features and Benefits
Description
▪ Low quiescent current draw (0.01 μA in shutdown mode)
▪ Primary-side output voltage sensing; no resistor divider
required
▪ User-adjustable current limit from 0.6 to 1.8 A
▪ 1.1 V logic (VHI(min)) compatibility
▪ Integrated IGBT driver
▪ System enable input
▪ Optimized for mobile phone, 1-cell Li+ battery applications
▪ Zero-voltage switching for lower loss
▪ >75% efficiency
▪ Regulation feature to maintain the output voltage
▪ Charge complete indication
▪ Integrated 40 V DMOS switch
The Allegro® A8733 Xenon photoflash charger IC is designed
to meet the needs of ultra-low power, small form factor cameras,
particularly camera-phones.
The charge time is adjustable by setting the charge current
limit from 0.6 to 1.8 A maximum. By using primary-side
voltage sensing, the need for a secondary-side resistive voltage
divider is eliminated. This has the additional benefit of reducing
leakage currents on the secondary side of the transformer. To
extend battery life, the A8733 features very low supply current
draw—typically 0.01 μA in shutdown mode.
The A8733 has a system enable pin to prevent accidental
activation of CHARGE or TRIGGER signals The charge and
trigger voltage logic thresholds are set at 1.1 VHI (min) to support
applications implementing low voltage control logic.
The A8733 is available in a 10-contact 3 mm × 3 mm DFN
package with a 0.75 nominal overall package height, and an
exposed pad for enhanced thermal performance.
Applications
▪ Mobile phone flash
▪ Digital and film camera flash
Package: 10-contact DFN with exposed
thermal pad (package EJ)
Approximate Scale 1:1
Typical Applications
1 : 10
C2
Battery Input +
2.3 to 5.5 V
1 : 10
D1
C1
C2
COUT
VIN
COUT
RSET
SW
ISET
Control
Block
CREG
10 MF
ISW sense
RREG
10 MΩ
RSET
100 kΩ
DONE
Block
VPULLUP
100 kΩ
DONE
DONE
ENABLE
VIN
VIN
IGBT Driver
TRIGGER
IGBT Driver
IGBT Gate
TRIGGER
IGBT Gate
GATE
GND
Application 1. Maintaining output voltage by predicting the
output voltage droop (REG pin connected to primary -side
RC network).
A8733-DS, Rev. 1
R2
38.3 kΩ
ISW sense
REG
CHARGE
DONE
ENABLE
R1
10 MΩ
Control
VPULLUP
REG
CHARGE
19F
330 V
VOUT Detect
SW
ISET
D1
C1
VIN
19F
330 V
VOUT Detect
Battery Input +
2.3 to 5.5 V
GATE
GND
Application 2. Maintaining output target voltage by directly
monitoring the output voltage (REG pin connected to a
secondary-side resistor divider).
Mobile Phone Xenon Photoflash Capacitor Charger
With IGBT Driver
A8733
Selection Guide
Part Number
A8733EEJTR-T
Package
Packing
10-contact DFN
Tape and reel, 1500 pieces per reel
*Contact Allegro for additional ordering information.
Absolute Maximum Ratings
Characteristic
Symbol
Notes
Rating
Units
–0.3 to 40
V
–0.3 to 6.0
V
–0.6 to VIN + 0.3 V
V
–0.3 to VIN + 0.3 V
V
DC voltage.
SW Pin
VSW
VIN Pin
VIN
ENABLE, CHARGE, TRIGGER,
¯N̄¯Ē¯ Pins
D̄¯Ō
(VSW is self-clamped by internal active clamp
and is allowed to exceed 40 V during flyback
spike durations. Maximum repetitive energy
during flyback spike: 0.5 μJ at frequency
≤ 400 kHz.)
Care should be taken to limit the current when
–0.6 V is applied to these pins.
Remaining Pins
Operating Ambient Temperature
Maximum Junction
Storage Temperature
TA
–40 to 85
ºC
TJ(max)
Range E
150
ºC
Tstg
–55 to 150
ºC
Thermal Characteristics
Characteristic
Package Thermal Resistance
Symbol
RθJA
Value
Units
On 2-layer PCB with 0.88 in.2 area of 2 oz. copper each side,
based on JEDEC standard
Test Conditions*
65
ºC/W
On 4-layer PCB based on JEDEC standard
45
ºC/W
*Additional thermal information available on Allegro website.
Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
2
Mobile Phone Xenon Photoflash Capacitor Charger
With IGBT Driver
A8733
Functional Block Diagram
VIN
SW
VSW – VIN
DCM
Detector
ISET
toff(max)
ISET Buffer
Control Logic
DMOS
18 μs
VDSref
HmL
Triggered Timer
OCP
S
Q
R
Q
ton(max)
18 μs
REG
0.96 V
Enable
S
Q
R
Q
DONE
1.2 V
CHARGE
VIN
IGBT Driver
RSOURCE
GATE
ENABLE
RSINK
TRIGGER
GND
Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
3
Mobile Phone Xenon Photoflash Capacitor Charger
With IGBT Driver
A8733
Pin-out Diagram
ISET
1
GATE
2
10 REG
PAD
9
DONE
VIN
3
8
TRIGGER
GND
4
7
SW
CHARGE
5
6
ENABLE
(Contacts-Down View)
Terminal List Table
Number
Name
Function
1
ISET
Sets the maximum switch current; connect an external resistor to GND to
set the desired peak current
2
GATE
IGBT gate drive (sink and source)
3
VIN
Input voltage; connect to a 2.3 to 5.5 V battery supply; use same battery
supply connected to transformer.
4
GND
5
CHARGE
Pull high to initiate charging
Ground connection
6
ENABLE
System enable input; when ENABLE = low, both CHARGE and
TRIGGER are disabled
7
SW
Drain connection of internal power MOSFET switch; connect to
transformer primary winding
8
TRIGGER
9
¯N̄¯Ē¯
D̄¯Ō
10
REG
Output voltage regulation pin; connect to external resistor and capacitor
to regulate output voltage (see Output Regulation section for details)
–
PAD
Exposed pad for enhanced thermal dissipation; connect to ground plane
IGBT input trigger
Pulls low when output reaches target value and CHARGE pin is high;
goes high during charging or whenever CHARGE pin is low
Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
4
Mobile Phone Xenon Photoflash Capacitor Charger
With IGBT Driver
A8733
ELECTRICAL CHARACTERISTICS valid at VIN = 3.6 V, ENABLE = VIN, RSET = 26.7 kΩ, ISWlim = 1.2 A, and TA=25°C, except
tions guaranteed from −40°C to 85°C unless otherwise noted
Characteristics
Symbol
VIN Voltage Range
Test Conditions
VIN
UVLO Enable Threshold
UVLO Hysteresis
VIN Supply Current
VINUV
VINUVhys
IIN
VIN rising
Shutdown (ENABLE = low, CHARGE = low, and
TRIGGER = low)
Standby current (ENABLE = high, CHARGE = high,
¯N̄¯Ē¯ = low)
D̄¯Ō
Charging (ENABLE = high and CHARGE = high)
indicates specifica-
Min.
Typ.
Max.
2.3
–
5.5
Unit
V
–
–
2.05
150
2.2
–
V
mV
–
0.01
0.5
μA
–
0.7
–
mA
–
2
–
mA
1.62
–
–
–
–
–
1.8
0.6
28
1.2
1000
0.25
1.98
–
–
–
–
–
A
A
kA/A
V
Ω
Ω
–
–
2
μA
–
–
0.5
μA
Current Limits
Switch Current Limit1
SW / ISET Current Ratio
ISET Pin Voltage While Charging
ISET Pin Internal Resistance
Switch On-Resistance
ISWlimMAX
ISWlimMIN
ISW/ISET
VSET
RSET(INT)
RSWDS(on)
RSET = 18 kΩ
RSET = 55 kΩ
CHARGE = high
CHARGE = high
VIN = 3.6 V, ID = 1.2 A
VSW = VIN(max)
Switch Leakage Current2
ENABLE Input Current
ENABLE Logic Input2
ISWlk
IENABLE
VENABLE
ENABLE Pull-Down Resistor Value
CHARGE Input Current
ICHARGE
CHARGE Logic Input2
VCHARGE
RCHPD
tCH
toffMAX
tonMAX
¯N̄¯Ē¯ Output Leakage Current2
D̄¯Ō
IDONElk
¯N̄¯Ē¯ Output Low
D̄¯Ō
Output Comparator Trip Voltage2
–
36
–
μA
High, over input supply range
1.1
–
–
V
Low, over input supply range
–
–
0.4
V
VCHARGE = VIN
–
–
100
36
–
–
kΩ
μA
V
RENPD
CHARGE Pull-Down Resistor Value
CHARGE ON/OFF Delay
Maximum Switch-Off Timeout
Maximum Switch-On Timeout
Voltage2
Combined VIN and SW leakage current at TA=25°C
VIN= 5.5 V in Shutdown
VENABLE = VIN
VDONEL
VOUTTRIP
High, over input supply range
1.1
–
–
Low, over input supply range
–
–
0.4
V
–
–
–
–
100
20
18
18
–
–
–
–
kΩ
us
μs
μs
–
–
1
μA
mV
Time between CHARGE = 1 and charging enabled
¯N̄¯Ē¯ pin
32 μA into D̄¯Ō
–
–
100
Measured as VSW – VIN
31
31.5
32
V
–
–
200
20
400
–
mV
V/μs
Output Comparator Overdrive
dV/dt Threshold of ZVS Comparator
Regulation
VOUTOV
dV/dt
Pulse width = 200 ns (90% to 90%)
Measured at SW pin
REG Voltage When Charging Completes
VREG(H)
¯N̄¯Ē¯ → low transition
CHARGE = high, at D̄¯Ō
1.15
1.2
1.25
V
REG Voltage Threshold for Regulation
VREG(L)
¯N̄¯Ē
¯ = low
CHARGE = high, at D̄¯Ō
–
0.96
–
V
¯N̄¯Ē
¯ = high, VSW – VIN = 30
CHARGE = high, at D̄¯Ō
V, VREG = 1.0 V
–
50
–
μA
REG Output Current Drive Capability
IREG
Continued on the next page…
Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
5
Mobile Phone Xenon Photoflash Capacitor Charger
With IGBT Driver
A8733
ELECTRICAL CHARACTERISTICS (continued) valid at VIN = 3.6 V, ENABLE = VIN, RSET = 26.7 kΩ, ISWlim = 1.2 A,
and TA=25°C, unless otherwise noted
Characteristics
IGBT Driver
Symbol
TRIGGER Logic Input2
Test Conditions
Min.
Typ.
Max.
Unit
V
VTRIG(H)
Input = logic high, over input supply range
1.1
–
–
VTRIG(L)
Input = logic low, over input supply range
–
–
0.4
V
100
10
30
110
140
125
360
–
–
–
–
–
–
–
kΩ
Ω
Ω
ns
ns
ns
ns
TRIGGER Pull-Down Resistor
RTRIGPD
–
GATE Resistance to VIN
RSrcDS(on) VIN = 3.6 V, VGATE =1.8 V, VTRIGGER = Logic high
–
–
GATE Resistance to GND
RSnkDS(on) VIN = 3.6 V, VGATE = 1.8 V, VTRIGGER = Logic low
Propagation Delay (Rising)
tDr
–
Propagation Delay (Falling)
tDf
–
Measurement taken at pin, CL= 6500 pF,
VIN = 3.6 V
Output Rise Time
tr
–
Output Fall Time
tf
–
1Current limit guaranteed by design and correlation to static test. Refer to application section for peak current in actual circuits.
2Specifications over the range T = –40°C to 85°C; guaranteed by design and characterization.
A
IGBT Drive Timing Definition
TRIGGER
50%
tDr
50%
tr
tDf
90%
GATE
10%
tf
90%
10%
Operation Timing Diagram
VIN
ENABLE
CHARGE
SW
VOUT
DONE
A
B
C
D
E
TRIGGER
GATE
Trigger ‘A’ arrives during charging process. GATE is enabled.
Trigger ‘B’ arrives during regulation mode while not refreshing. GATE is enabled.
Charging resumes once DONE pins goes high.
Trigger ‘C’ arrives during regulation mode while refreshing. GATE is enabled.
Trigger ‘D’ arrives when ENABLE is high but CHARGE pin is low. GATE is enabled.
Trigger ‘E’ arrives when ENABLE is low. GATE is disabled.
Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
6
Mobile Phone Xenon Photoflash Capacitor Charger
With IGBT Driver
A8733
Performance Characteristics
Charging Time at Various Peak Current Levels
Common Parameters
Symbol
Parameter Units/Division
C1
VOUT
50 V
C2
VBAT
1V
C3
IIN
100 mA
t
time
200 ms
Conditions Parameter
Value
VBAT
3.6 V
COUT
20 μF
Conditions
Parameter
RSET
ISWlim
Value
26.7 kΩ
≈1.2 A
VOUT
VBAT
C1
C2
IIN
C1
C2
C3
C3
t
VOUT
C1
VBAT
Conditions
Parameter
RSET
ISWlim
Value
33.2 kΩ
≈1.0 A
C2
IIN
C1
C2
C3
C3
t
VOUT
C1
VBAT
Conditions
Parameter
RSET
ISWlim
Value
39 kΩ
≈0.9 A
C2
IIN
C1
C2
C3
C3
t
Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
7
Mobile Phone Xenon Photoflash Capacitor Charger
With IGBT Driver
A8733
Efficiency versus Battery Voltage
Charge Time versus Battery Voltage
Transformer Lp= 8 μH, N = 10.2; COUT= 20 μF / 330 V UCC; TA=25°
Transformer Lp= 8 μH, N = 10.2; COUT= 20 μF / 330 V UCC; TA=25°
71
3.5
2.0
45
≈ 0.8
67
39
≈ 0.9
66
33.2
≈ 1.0
65
26.7
≈ 1.2
69
68
1.5
1.0
0.5
64
62
RSET
(kΩ)
55
IP
(A)
≈ 0.65
61
45
≈ 0.8
60
39
≈ 0.9
59
33.2
≈ 1.0
58
26.7
≈ 1.2
63
57
56
55
0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
2.0
6.0
2.5
3.0
3.5
VBAT (V)
COUT= 20 μF. For larger or smaller capacitances, charging time
scales proportionally.
4.0
VBAT (V)
4.5
5.0
5.5
6.0
Special low-profile transformer with relatively low inductance
(Lp= 8 μH) and high winding resistance (Rp = 0.37 Ω). Higher efficiency can be achieved by using transformers with higher Lp, which reduces
switching frequency and therefore switching loses, and lower resistance,
which reduces conduction losses.
Average Input Current versus Battery Voltage
XFM Lp= 8 μH, N = 10.2, COUT= 20 μF 330 V UCC, TA=25°
0.55
0.50
0.45
0.40
IIN (A)
Time (s)
2.5
IP
(A)
≈ 0.65
Efficiency (%)
3.0
70
RSET
(kΩ)
55
0.35
0.30
RSET
(kΩ)
26.7
IP
(A)
≈ 1.2
33.2
≈ 1.0
39
≈ 0.9
45
≈ 0.8
55
≈ 0.65
0.25
0.20
0.15
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
VBAT (V)
An increase in ISWlim with respect to VBAT actually keeps the average input current
roughly constant throughout the battery voltage range. Normally, if ISWlim is kept
constant, the average current will drop as VBAT goes higher.
Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
8
A8733
Mobile Phone Xenon Photoflash Capacitor Charger
With IGBT Driver
Application Information
General Operation Overview
The charging operation is started by a low-to-high
signal on the ENABLE pin, provided that VIN is above
the VUVLO level. It is strongly recommended to keep
the ENABLE pin at logic low during power-up.
• When ENABLE input is low, the device will be completely shut down and will not respond to any input
at CHARGE or TRIGGER pin.
• When ENABLE is high and CHARGE is low, the
device will remain in low-power standby mode.
However, the IGBT gate driver will now respond to
TRIGGER input signal.
• When ENABLE is high and CHARGE is high, the
device will start switching to charge-up the output
capacitor. Charging will stop after the output target
voltage is reached.
Pulling either the CHARGE pin or the ENABLE pin
low during a charging process stops the charging
immediatey.
¯ open-drain indicator is pulled low when
The D̄¯¯ Ō¯¯N̄¯Ē
CHARGE is high and target output voltage is reached.
The primary peak current is set by RSET connected
across ISET. When a charging cycle is initiated, the
transformer primary side current, IPrimary, ramps up
linearly at a rate determined by the combined effect of
the battery voltage, VBAT, and the primary side inductance, LPrimary. When IPrimary reaches the current limit,
ISWLIM, the internal MOSFET is turned off immediately, allowing the energy to be pushed into the photoflash capacitor, COUT, from the secondary winding.
The secondary side current drops linearly as COUT
charges. The switching cycle starts again, either after
the transformer flux is reset, or after a predetermined
time period, toffMAX (18 μs), whichever occurs first.
The A8733 senses output voltage indirectly on the
primary side. This eliminates need for high voltage
feedback resistors required for secondary sensing.
Flyback converter stops switching when output voltage reaches:
VOUT = K × N - VD ,
(1)
where K = 31.5 typically, N is the transformer turns
ratio, and VD is the forward drop of the output diode
(approximately 1 to 2 V).
Output Voltage Regulation
The A8733 can also be used to regulate output voltage
within a predetermined window. In this mode, connect a capacitor, CREG, and resistor, RREG, from the
REG pin to GND (refer to the figure Application 1).
When CHARGE is held high, the voltage monitoring
circuit of the A8733 is always active, irrespective of
the REG pin voltage level.
Voltage Regulation Using Predicitive Droop The A8733
uses a technique called Predictive Droop for regulating the output capacitor voltage after the completion
of a charging cycle. When the target output voltage
is reached, the converter stops charging and output
capacitor voltage droops due to leakage current. An
external resistor and capacitor connected from the
REG pin to ground will provide an RC discharge time
constant. This time constant can be selected to mirror
the droop rate of the output capacitor. When voltage at
the REG pin drops to 80% of the reference value, the
converter starts charging again and brings the output
capacitor back to target voltage again.
The time required for an RREG-CREG network to discharge from V0 to VT is given by:
T = RREG × CREG × ln (V0 / VT) .
(2)
For example, if CREG = 10 μF, RREG = 10 MΩ and
V0 / VT = 1.25, then T = 22 seconds. Assuming that the
RC-discharge characteristic of the output capacitor
Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
9
A8733
Mobile Phone Xenon Photoflash Capacitor Charger
With IGBT Driver
matches that at the REG pin, we can predict that the
output voltage has drooped 20%, and therefore it is
time to recharge the output capacitor.
By implementing a Predictive Droop technique, no
additional leakage paths are introduced on the secondary side, which helps to keep power losses to a minimum. By intentionally making the RC discharge time
constant of the REG pin shorter than that of the output
capacitor, we can regulate the output voltage to a window tighter than the default 20% hysteresis.
Voltage Regulation Using Direct Sensing If
direct
sensing from the secondary side is desired, connect
the REG pin to a resistor divider network across the
output capacitor to enable output regulation. In this
case, the charging cut-off is still controlled by primary
side sensing (charging stops when reflected voltage
across transformer primary winding reaches 31.5 V),
but the regulation threshold is controlled by the secondary side sensing. When the CHARGE pin is high,
and the sensed output voltage falls below the lower
VREG threshold, the flyback converter charges the output capacitor again until the primary side sensing stops
further charging. This cycle repeats till the CHARGE
pin is pulled low.
The benefit of this method is that a lower output voltage can be selected independently, simply by changing the resistor divider ratio. For example, given
R1=10 MΩ, R2= 33.2 kΩ, and VREG(L)= 0.96 V, then:
VOUT(Low) = VREG(L) × ( R1/ R2 + 1) = 290 V . (3)
Selection of Switching Current Limit
The A8733 features continuously adjustable peak
switching current between 0.6 and 1.8 A. This is done
by selecting the value of an external resistor RSET,
connected from the ISET pin to GND, which determines the ISET bias current, and therefore the switching current limit, ISWlim.
To the first order approximation, ISWlim is related to
ISET and RSET according to the following equations:
ISWlim = ISET × K = VSET / RSET × K ,
(4)
where K = 28000 when battery voltage is 3.6 V.
In real applications, the actual switching current
limit is affected by input battery voltage, and also the
transformer primary inductance, Lp. If necessary, the
following expressions can be used to determine ISWlim
more accurately:
ISET = VSET / (RSET + RSET(INT) – K × RGND(INT) ), (5)
where:
RSET(INT) is the internal resistance of the ISET pin
(1 kΩ typical),
RGND(INT) is the internal resistance of the bonding
wire for the GND pin (27 mΩ typical), and
K = (K′ + VIN × K″), with K′ = 24350 and
K″ ≈ 1040 at TA = 25°C. Then,
ISWlim = ISET × K + VBAT / LP × tD ,
(6)
where tD is the delay in SW turn-off (0.1 μs typical).
10
Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
Mobile Phone Xenon Photoflash Capacitor Charger
With IGBT Driver
A8733
when the battery voltage drops below 2.5 V, the signal
at BL (battery-low) goes high. The resistor RBL, connecting BL to the ISET pin, then injects 10 μA into
RSET. This effectively reduces ISET current to 26 μA
(for ISWLIM = 0.73 A). A disadvantage of the above
method is that the 10 μA current is always flowing
whenever the BL signal goes high.
Figure 2 can be used to determine the relationship
between RSET and ISWlim at various battery voltages.
Smart Current Limit (Optional)
With the help of some simple external logic, the user
can change the charging current according to the battery voltage. For example, assume that ISET is normally 36 μA (for ISWlim = 1.0 A). Referring to figure 3,
1.9
1.8
1.7
VIN
(V)
IPEAK (A)
1.6
1.5
5.5
1.4
3.6
1.3
2.3
1.2
1.1
1.0
0.9
0.8
0.7
0.6
15
20
25
30
35
40
45
50
55
60
65
70
RISET (kΩ)
Figure 2. Peak Current versus ISET resistance at various input voltages.
TA ≈ 22°C, transformer LP = 8.2 μH.
BL
RBL
ISET
RSET
Figure 3. Smart Current Limit reference circuit
11
Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
A8733
Mobile Phone Xenon Photoflash Capacitor Charger
With IGBT Driver
Timer Mode and Fast Charging Mode
The A8733 achieves fast charging times and high efficiency by operating in discontinuous conduction mode
(DCM) through most of the charging process The
relationship of Timer Mode and Fast Charging Mode
is shown in figure 4.
The IC operates in Timer Mode when beginning to
charge a completely discharged photoflash capacitor, usually when the output voltage, VOUT, is less
than approximately 15 to 20 V. Timer Mode is a fixed
period, 18 μs, off-time control. One advantage of
having Timer Mode is that it limits the initial battery
current surge and thus acts as a “soft-start.” A timeexpanded view of a Timer Mode interval is shown in
figure 5.
As soon as a sufficient voltage has built up at the
output capacitor, the IC enters Fast-Charging Mode.
In this mode, the next switching cycle starts after the
secondary side current has stopped flowing, and the
switch voltage has dropped to a minimum value. A
proprietary circuit is used to allow minimum-voltage
switching, even if the SW pin voltage does not drop to
VOUT
Timer Mode
Fast Charging Mode
VBAT
IIN
Figure 4. Timer Mode and Fast Charging Mode. t =200 ms/div,
VOUT =50 V/div, VBAT =1 V/div., IIN =100 mA/div., VBAT =3.6 V,
COUT =20 μF/330 V, RSET=46 kΩ (ISWlim≈0.75 A).
VSW
VBAT
VOUT
ISW
Figure 5. Timer Mode expanded view. VOUT ≤ 14 V, t = 2 μs / div.,
VBAT = 3.6 V, RSET = 33.2 kΩ.
12
Allegro MicroSystems, Inc.
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www.allegromicro.com
Mobile Phone Xenon Photoflash Capacitor Charger
With IGBT Driver
A8733
0 V. This enables Fast-Charging Mode to start earlier
than previously possible, thereby reducing the overall
charging time. Minimum-voltage switching is shown
in figure 6.
During Fast-Charging Mode, when VOUT is high
enough (over 50 V), true zero-voltage switching
(ZVS) is achieved. This further improves efficiency
as well as reduces switching noise. A ZVS interval is
shown in figure 7.
Minimum Voltage
Switching
VSW
VBAT
Transformer Selection
VOUT
1. The transformer turns ratio, N, determines the output voltage:
N = NS / NP ,
VOUT = 31.5 × N – Vd ,
(7)
(8)
where 31.5 is the typical value of VOUTTRIP , and Vd is
the forward drop of the output diode.
ISW
Figure 6. Minimum voltage switching. VOUT ≥ 15 V; t =1 μs/div.,
VBAT = 3.6 V, RSET = 33.2 kΩ.
2. The primary inductance, LP , determines the on-time
of the switch:
ton = (–LP / R ) × ln (1 – ISWlim × R /VIN) ,
(9)
where R is the total resistance in the primary current
path (including RSWDS(on) and the DC resistance of the
transformer).
VOUT
VSW
If VIN is much larger than ISWlim × R, then ton can be
approximated by:
ton = ISWlim × LP /VIN .
(10)
3. The secondary inductance, LS, determines the offtime of the switch. Given:
LS / LP = N × N , then
toff = (ISWlim / N) × LS /VOUT
(11)
= (ISWlim × LP × N) /VOUT .
(12)
The minimum pulse width for toff determines what
is the minimum LP required for the transformer. For
VSW
VBAT
VBAT
ISW
VOUT
Zero Voltage
Switching
ISW
Figure 7. Zero voltage switching. VOUT = 120 V. t = 0.2 μs/div.,
VBAT = 3.6 V, RSET = 33.2 kΩ.
13
Allegro MicroSystems, Inc.
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Mobile Phone Xenon Photoflash Capacitor Charger
With IGBT Driver
A8733
example, if ISWlim = 0.7 A, N = 10, and VOUT = 315 V,
then LP must be at least 9 μH in order to keep toff at
200 ns or longer. These relationships are illustrated in
figure 8.
In general, choosing a transformer with a larger LP
results in higher efficiency (because a larger LP means
lower switch frequency and hence lower switching
loss). But transformers with a larger LP also require
more windings and larger magnetic cores. Therefore, a
trade-off must be made between transformer size and
efficiency.
SW node does not exceed the absolute maximum specification on the SW pin (refer to the Absolute Maximum Ratings table). An achievable minimum leakage
inductance for this application, however, is usually
compromised by an increase in parasitic capacitance.
Furthermore, the transformer secondary capacitance
should be minimized. Any secondary capacitance is
multiplied by N2 when reflected to the primary, leading to high initial current swings when the switch turns
on, and to reduced efficiency.
Component Selection
Ceramic capacitors with X5R or X7R dielectrics
are recommended for the input capacitor, CIN. During initial timer mode the device operates with
18 μs off-time. The resonant period caused by the
input filter inductor and capacitor should be at least
2 times greater or smaller than the 18 μs timer period,
to reduce input ripple current during this period.
Selection of the flyback transformer should be based
on the peak current, according to the following table:
IPeak Range
LP
(A)
Supplier
Part Number
(μH)
0.6 to 1.2
TDK
LDT565630T-003
10.5
0.9 to 1.6
TDK
LDT565630T-001
6
0.6 to 1.6
Tokyo Coil
T-16-024A
12.8
0.6 to 1.8
Tokyo Coil
T-15-154M
14.2
Leakage Inductance and Secondary Capacitance
The transformer design should minimize the leakage
inductance to ensure the turn-off voltage spike at the
ton
Input Capacitor Selection
The resonant period is given by:
TRES = 2 π (LIN × CIN)1/2 .
(13)
It is recommended to use at least 4.7 μF / 6.3 V to
decouple the battery input, VBAT , at the primary
of the transformer. Decouple the VIN pin using
toff
VSW
ISW
Vr
tf
VIN
VIN
ISW
VSW
tneg
Figure 8. Pulse width relationship definitions.
14
Allegro MicroSystems, Inc.
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www.allegromicro.com
A8733
Mobile Phone Xenon Photoflash Capacitor Charger
With IGBT Driver
0.1 μF / 6.3 V bypass capacitor. This configuration is
illustrated in figure 9.
power switch loop (transformer primary side) and the
rectifier loop (secondary side).
Output Diode Selection
• Use short, thick traces for connections to the transformer primary and the SW pin.
¯ signal trace and other
• It is important that the D̄¯¯ Ō¯¯N̄¯Ē
signal traces be routed away from the transformer
and other switching traces, in order to minimize
noise pickup.
• High voltage isolation rules must be followed carefully to avoid breakdown failure of the circuit board.
• Avoid ground plane underneath transformer secondary and diode to minimize parasitic capacitance.
• For low threshold logic (< 1.2 V), add 1 nF capacitors
across the CHARGE and TRIGGER pins to GND to
avoid malfunction due to noise.
Refer to the figures on the following page for a recommended layout.
Choose the rectifying diodes, D1, to have small parasitic capacitance (short reverse recovery time) while
satisfying the reverse voltage and forward current
requirements. The peak reverse voltage of the diode,
VRDPeak , occurs when the internal MOSFET switch is
closed. It can be calculated as:
(14)
VRDPeak = VOUT + N × VBAT .
The peak current of the rectifying diode, IDPeak , is
calculated as:
(15)
IDPeak = IPrimary_Peak / N .
Layout Guidelines
Key to a good layout for the photoflash capacitor charger circuit is to keep the parasitics minimized on the
LIN
+
VBAT
CIN
A8733
Figure 9. Typical input selection with input inductance.
Inductance, LIN , may ba an input filter inductor or inductance due
to long wires in the test setup.
15
Allegro MicroSystems, Inc.
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Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
Mobile Phone Xenon Photoflash Capacitor Charger
With IGBT Driver
A8733
Application 1
D1
XEN+
T1
R5
COUT
Trigger
T2
C6
U1
RPULLUP
C1
XEN–
VIN
DONE
SW
A8733
GATE
ENABLE
TRIGGER
Q1
R3
CHARGE
ISET
C2
GND
R4
REG
RREG
RSET
CREG
Component Table for Application Circuits on Page 1
Component
Rating
Part Number
JMK212BJ475K
Taiyo Yuden
EPH-331E--800A030S
Chemi-Con
C1, Input Capacitor
4.7 μF, ±10%, 6.3 V, X5R ceramic capacitor (0805)
C2, Bypass capacitor
0.1 μF, ±10%, 6.3 V X7R ceramic capacitor (0603)
COUT, Photoflash Capacitor
80 μF / 330 V
D1, Output Diode
RSET
Source
800 V
FV02R80
Origin
2 × 250 V, 225 mA, 5 pF
BAV23S
Philips Semiconductor,
Fairchild Semiconductor
36 kΩ, 1%
RPULLUP
100 kΩ
CREG (application 1 only)
10 μF / 6.3 V
RREG (application 1 only)
10 MΩ
R1 (application 2 only)
10 MΩ, high voltage
R2 (application 2 only)
38.3 kΩ (0603)
T1, Transformer
Refer to Component Selection section
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115 Northeast Cutoff, Box 15036
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www.allegromicro.com
Mobile Phone Xenon Photoflash Capacitor Charger
With IGBT Driver
A8733
Package EJ, 3 mm x 3 mm 10-Contact DFN
with Exposed Thermal Pad
0.30
3.00 ±0.15
0.85
0.50
10
10
3.00 ±0.15
1.64
3.10
A
1
2
1
11X
D
SEATING
PLANE
0.08 C
+0.05
0.25 –0.07
C
C
2.38
PCB Layout Reference View
0.75 ±0.05
0.50
1
For Reference Only
(reference JEDEC MO-229WEED)
Dimensions in millimeters
Exact case and lead configuration at supplier discretion within limits shown
2
0.40 ±0.10
1.64
B
10
2.38
A Terminal #1 mark area
B Exposed thermal pad (reference only, terminal #1
identifier appearance at supplier discretion)
C Reference land pattern layout (reference
IPC7351 SON50P300X300X80-11WEED3M);
All pads a minimum of 0.20 mm from all adjacent pads; adjust as
necessary to meet application process requirements and PCB layout
tolerances; when mounting on a multilayer PCB, thermal vias at the
exposed thermal pad land can improve thermal dissipation (reference
EIA/JEDEC Standard JESD51-5)
17
Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
Mobile Phone Xenon Photoflash Capacitor Charger
With IGBT Driver
A8733
Revision History
Revision
Revision Date
Rev. 1
April 19, 2012
Description of Revision
Miscellaneous format changes
Copyright ©2008-2012, Allegro MicroSystems, Inc.
Allegro MicroSystems, Inc. reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the
information being relied upon is current.
Allegro’s products are not to be used in life support devices or systems, if a failure of an Allegro product can reasonably be expected to cause the
failure of that life support device or system, or to affect the safety or effectiveness of that device or system.
The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no responsibility for its use;
nor for any infringement of patents or other rights of third parties which may result from its use.
For the latest version of this document, visit our website:
www.allegromicro.com
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