A8738 Datasheet

A8738
Fixed Gate Drive Xenon Photoflash Charger
Discontinued Product
This device is no longer in production. The device should not be
purchased for new design applications. Samples are no longer available.
Date of status change: December 10, 2012
Recommended Substitutions:
For existing customer transition, and for new customers or new applications, contact Allegro Sales.
NOTE: For detailed information on purchasing options, contact your
local Allegro field applications engineer or sales representative.
Allegro MicroSystems, Inc. reserves the right to make, from time to time, revisions to the anticipated product life cycle plan
for a product to accommodate changes in production capabilities, alternative product availabilities, or market demand. The
information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no responsibility for its use; nor for any infringements of patents or other rights of third parties which may result from its use.
A8738
Fixed Gate Drive Xenon Photoflash Charger
Features and Benefits
Description
▪ Low quiescent current draw (0.5 μA max in shutdown mode)
▪ Primary-side output voltage sensing; no resistive divider
required
▪ User-adjustable current limit from 0.4 to 0.9 A
▪ 1.1 V logic (VIH(min)) compatibility
▪ Integrated constant voltage IGBT driver with separate sink
and source
▪ Optimized for mobile phone, 1-cell Li+ battery applications
▪ Zero-voltage switching for lower loss
▪ >75% efficiency
▪ Charge Complete indication
▪ Independent charge/trigger control
▪ Integrated 40 V DMOS switch
The Allegro® A8738 Xenon photoflash charger IC is designed
to meet the needs of ultra-low power, small form factor cameras,
particularly camera-phones.
This device integrates a fixed regulator to precisely control the
IGBT flash current across a wide range of battery voltages,
providing a 3 V, gate drive. The IGBT driver also has separate
source and sink connections, for flexibility in controlling IGBT
rise and fall times.
▪ Mobile phone flash
▪ Digital and film camera flash
The charge current time is adjustable by setting the charge
current limit from 0.4 to 0.9 A maximum. By using primary-side
voltage sensing, the a secondary-side resistive voltage divider is
eliminated. This has the additional benefit of reducing leakage
currents on the secondary side of the transformer. To extend
battery life, the A8738 features very low supply current draw,
typically 0.5 μA maximum in shutdown mode.
Package: 10-contact TDFN with exposed
thermal pad (suffix EJ)
The charge and trigger voltage logic thresholds are set at 1.1 V
(VIH(min)) to support applications implementing low voltage
control logic.
Applications
The device is available in a 10-contact, 3 mm × 3 mm TDFN
package with exposed pad for enhanced thermal performance.
It is lead (Pb) free, with 100% matte-tin leadframe plating.
Approximate size
Typical Application
Battery Input +
2.3 to 5.5 V
C1
CIN
VIN
ISET
RISET
C2
1 μF
6.3 V
COUT
19 μF
350 V
SW
VIN
A8738
100 kΩ
CHARGE
DONE
VBIAS
TRIGGER
IGBTSRC
GND
R1
IGBTSINK
Figure 1. Typical application circuit
A8737-DS, Rev. 1
D1
1:10
R2
GATE
To IGBT Gate
A8738
Fixed Gate Drive Xenon Photoflash Charger
Selection Guide
Part Number
IGBT Drive Voltage
VIGBT(V)
A8738EEJTR-T
3
Packing
1500 pieces per 7-in. reel
Package
10-contact TDFN
Absolute Maximum Ratings
Characteristic
Symbol
Notes
Rating
Units
SW Pin
VSW
DC voltage (VSW is self-clamped by an internal
active clamp and is allowed to exceed 40 V during flyback spike durations. Maximum repetitive
energy during flyback spike: 0.5 μJ at frequency
= 400 kHz.)
–0.3 to 40
V
VIN Pin
VIN
–0.3 to 6.0
V
Logic and Input Pins
VI
–0.6 to VIN + 0.3
V
–0.3 to 6.0
V
VBIAS Pin
VBIAS
IGBTSRC and IGBTSINK Pins
VIGBT
Operating Ambient Temperature
TA
Maximum Junction Temperature
Storage Temperature
Care should be taken to limit the current when
–0.6 V is applied to these pins.
–0.3 to VBIAS + 0.3
V
–40 to 85
ºC
TJ(max)
150
ºC
Tstg
–55 to 150
ºC
Value
Units
45
ºC/W
65
ºC/W
Range E
Thermal Characteristics
Characteristic
Symbol
Test Conditions*
On 4-layer PCB, based on JEDEC standard
Package Thermal Resistance
RθJA
in.2
On 2-layer PCB with 0.88
2-oz. copper each
side, based on JEDEC standard
*Additional thermal information available on the Allegro website
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115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
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2
A8738
Fixed Gate Drive Xenon Photoflash Charger
Functional Block Diagram
VIN
SW
VSW – VIN
DCM
Detector
ISET
toff(max)
ISET Buffer
VDSref
Control Logic
DMOS
13 μs
HmL
Triggered Timer
OCP
S
Q
R
Q
ton(max)
13 μs
Enable
S
Q
R
Q
DONE
CHARGE
Internal
Regulator
VBIAS
VBIAS
IGBT Driver
TRIGGER
IGBTSRC
IGBTSINK
GND
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A8738
Fixed Gate Drive Xenon Photoflash Charger
Pin-out Diagram
VBIAS
1
IGBTSRC
2
IGBTSINK
3
VIN
GND
10 ISET
9
TRIGGER
8
DONE
4
7
CHARGE
5
6
SW
PAD
(Top View)
Terminal List Table
Name
Number
Function
CHARGE
7
Pull high to initiate charging; pull low to enter low-power standby mode.
¯N̄¯Ē¯
D̄¯Ō
8
Pulls low when output reaches target value and CHARGE pin is high;
goes high during charging or whenever CHARGE pin is low. Connect an
external pull-up resistor to VIN.
GND
5
Ground connection.
IGBTSINK
3
IGBT driver gate drive sink output.
IGBTSRC
2
IGBT driver gate drive source output.
ISET
10
Set the maximum switch current. Connect an external resistor to GND
to program the desired peak switch current.
PAD
–
Exposed pad for enhanced thermal dissipation. Connect to GND plane.
SW
6
Drain connection of internal power MOSFET switch; connect to
transformer primary winding.
TRIGGER
9
IGBT input trigger.
VIN
4
Input voltage; connect to a 2.3 to 5.5 V input supply. Decouple this pin
with 0.1 μF capacitor.
VBIAS
1
Output of internal 3 V regulated supply. Connect a 1 μF/ 6.3 V capacitor
from this pin to GND.
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A8738
Fixed Gate Drive Xenon Photoflash Charger
ELECTRICAL CHARACTERISTICS Valid at VIN = 3.6 V, TA = 25°C except
indicates specifications guaranteed from −40°C to
85°C ambient unless otherwise specified
Characteristics
VIN Voltage Range1
UVLO Enable Threshold
UVLO Hysteresis
VIN Supply Current
Symbol
Test Conditions
VIN
VUVLO
VIN rising
VUVLOhys
IIN
Min
Typ
Max
Unit
2.3
–
5.5
V
–
2.05
2.2
V
mV
–
150
–
Shutdown, CHARGE = TRIGGER = 0
–
0.01
0.5
μA
Charging completed (regulating VBIAS)
–
0.8
–
mA
During charging (CHARGE = VIN)
–
2.8
–
mA
Current Limit
Switch Current Limit2
SW/ISET Ratio
ISET Charging Pin Voltage
ISET Pin Internal Resistance
ISWLIMmax
RSET = 37.4 kΩ
0.8
0.9
1.0
A
ISWLIMmin
RSET = 85 kΩ
–
0.4
–
A
ISW/ISET
RSET = 37.4 kΩ; CHARGE = 1
–
28
–
kA/A
VSET
RSET = 37.4 kΩ; CHARGE = 1,
ISW = 0 A (SW disconnected)
–
1.2
–
V
RSET(INT)
–
1000
–
Ω
Switch Resistance
RDS(on)
–
0.25
–
Ω
VSW = VIN(max)
–
–
2
μA
Switch Leakage Current1
ISWLEAK
Combined VIN and SW leakage current at TA = 25°C,
VIN = 5.5 V in Shutdown
–
–
0.5
μA
TRIGGER/CHARGE Input Current
IINPUT
–
36
–
μA
Logic Input High1
VIH
CHARGE and TRIGGER pins; High over full VIN range
1.1
–
–
V
Logic Input Low1
VIL
CHARGE and TRIGGER pins; Low over full VIN range
–
–
0.4
V
TRIGGER/CHARGE Pull-down
CHARGE On/Off Delay
VCHARGE = VTRIGGER = VIN
RPULLDOWN Internal pull-down resistor
tCH
Time between CHARGE = 1 and charging enabled
–
100
–
KΩ
–
20
–
μs
Switch Off Timeout
tOFFMAX
–
13
–
μs
Switch On Timeout
tONMIN
–
13
–
μs
¯N̄¯Ē¯ Output Leakage Current
D̄¯Ō
IDONElk
¯N̄¯Ē¯ Output Low Voltage
D̄¯Ō
VDONEL
Output Comparator Trip Voltage1
Output Comparator Overdrive
dV/dt Threshold for ZVS Comparator
VOUTTRIP
VOUTOV
dV/dt
–
–
1
μA
¯N̄¯Ē¯ pin
32 μA into D̄¯Ō
–
–
100
mV
Measured as VSW – VIN
31
31.5
32
V
140 ns pulse width (90% to 90%)
–
200
400
mV
Measured at SW pin
–
20
–
V/μs
–
3
–
V
–
5
–
Ω
IGBT Driver
IGBT Drive Voltage
IGBT Source Resistance
VIGBT
RSOURCE
VBIAS = 3 V, IGBTSINK = 1.5 V
IGBT Sink Resistance
RSINK
IGBTSINK = 1.5 V
–
6
–
Ω
IGBT Sink Pull-Down Resistor
RGsink
Internal pull-down resistor on IGBTSINK
–
500
–
kΩ
Continued on the next page…
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A8738
Fixed Gate Drive Xenon Photoflash Charger
ELECTRICAL CHARACTERISTICS (continued) Valid at VIN = 3.6 V, TA = 25°C except
indicates specifications guaranteed
from −40°C to 85°C ambient unless otherwise specified
Characteristics
Symbol
Test Conditions
IGBTSRC and IGBTSINK tied together, measurement
taken at pin; RGATE = 12 Ω, CL = 6500 pF
Min
Typ
Max
Unit
–
30
–
ns
TRIGGER Propagation Delay, Rising
tDr
TRIGGER Propagation Delay, Falling
tDf
–
30
–
ns
Output Rise Time
tr
–
70
–
ns
Output Fall Time
tf
–
70
–
ns
1Specifications
over the range TA = –40°C to 85°C guaranteed by design and characterization.
2Current limit guaranteed by design and correlation to static test. Refer to Applications Information section for peak current in actual circuits.
TRIGGER
50%
tdr
IGBTSRC and
IGBTSINK
(connected together)
50%
tr
tdf
90%
10%
tf
90%
10%
Figure 2. IGBT Drive Timing Definition
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A8738
Fixed Gate Drive Xenon Photoflash Charger
Characteristic Performance
Test conditions: LP = 6.5 μH, N = 10.2, COUT = 21 μF, VOUT = 330 V
Charge Time vs. Battery Voltage
Time
(s)
Average Input Current vs. Battery voltage
7
400
6
350
5
300
Iin
250
(mA)
Rset = 36 kΩ
4
Rset = 51 kΩ
Rset = 60 kΩ
3
Rset = 36 kΩ
Rset = 51 kΩ
Rset = 60 kΩ
200
2
150
1
100
0
50
2
2.5
3
3.5
4
4.5
5
5.5
6
2
2.5
3
3.5
VBAT (V)
4
4.5
5
5.5
6
VBAT (V)
Final Output Voltage vs. Switch Off-Time
Final Output Voltage vs. Battery Voltage
335
331.8
334
331.6
333
331.4
332
331.2
Vin=2.5 V
331
Vout
(V)
Vin=3.7 V
Vout 330
(V)
Vin=5.5 V
Rset = 60 kΩ
328
330.6
327
330.4
326
330.2
325
120
140
160
180
200
220
240
330
260
2
2.5
3
Toff (ns)
3.5
4
4.5
5
5.5
6
VBAT (V)
Efficiency vs. Battery Voltage
70.00
65.00
60.00
Efficiency (%)
100
Rset = 51 kΩ
330.8
329
80
Rset = 36 kΩ
331
Rset = 36 kΩ
55.00
Rset = 51 kΩ
Rset = 60 kΩ
50.00
45.00
40.00
2
2.5
3
3.5
4
4.5
5
5.5
6
VBAT (V)
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A8738
Fixed Gate Drive Xenon Photoflash Charger
Characteristic Performance
Charging Time at Various RISET Values
Common Conditions
Common Parameters
Symbol
Parameter
Units/Division
Parameter
Value
3.6 V
C1
VOUT
50 V
VBAT
C2
VBAT
1V
COUT
21 μF
LPRI
8 μH
RSET= 61 kΩ, CH4: IIN = 100 mA/div, Time = 1s/div
RSET = 49 kΩ, CH4: IIN 200 mA/div, Time = 0.5 s/div
RSET = 36 kΩ, CH4: IIN = 200 mA/div, Time = 0.5 s/div
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A8738
Fixed Gate Drive Xenon Photoflash Charger
Complete CBIAS Charge Cycle versus Time
See Charge Pump Operation section for timing diagram details
VIN = 3.6 V, COUT = 21 μF, CBIAS = 1 μF, Trigger pulse width = 50 ms,
C1: Charge = 2 V/div, C2: VBIAS = 2 V/div, C3: VOUT = 50 V/div,
C4: VGATE = 2 V/div, Time = 500 ms/div
VBIAS Charging versus VIN
VIN = 2.3 V.
CBIAS = 1 μF, Charge Time = 8 ms, C1: , Charge = 2 V/div,
C2: VBIAS = 2 V/div, C3: VOUT = 50 V/div, Time = 10 ms/div
VIN = 3.6.
CBIAS = 1 μF, Charge Time = 6 ms, C1: Charge = 2 V/div,
C2: VBIAS = 2 V/div, C3: VOUT = 50 V/div, Time = 10 ms/div
VBIAS charges to required 3 V level in 8 ms, at 2.3 V input, and in 6 ms at 3.6 V input. This is much faster than VOUT charging.
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A8738
Fixed Gate Drive Xenon Photoflash Charger
Typical VBIAS versus VBAT
3.2
VBIAS (V)
3.0
2.8
2.6
2.0
2.5
3.0
3.5
VBAT (V)
4.0
4.5
5.0
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A8738
Fixed Gate Drive Xenon Photoflash Charger
Functional Description
General Operation Overview
The charging operation is started by a low-to-high signal on the
CHARGE pin, provided that VIN is above the VUVLO level. It is
strongly recommended to keep the CHARGE pin at logic low
during power-up. After VIN exceeds the UVLO level, a lowto-high transition on the CHARGE pin is required to start the
charging.
¯ open-drain indicator is pulled low when CHARGE is
The D̄¯¯ Ō¯¯N̄¯Ē
high and target output voltage is reached. The primary peak current is set by RSET connected across ISET. When a charging cycle
is initiated, the transformer primary side current, IPrimary, ramps
up linearly at a rate determined by the combined effect of the
battery voltage, VBAT, and the primary side inductance, LPrimary.
When IPrimary reaches the current limit, ISWLIM, the internal MOSFET is turned off immediately, allowing the energy to be pushed
into the photoflash capacitor, COUT, from the secondary winding. The secondary side current drops linearly as COUT charges.
The switching cycle starts again, either after the transformer flux
is reset, or after a predetermined time period, tOFF(max) (13 μs),
whichever occurs first.
The A8738 senses output voltage indirectly on the primary side.
This eliminates the requirement for high voltage feedback resistors required for secondary sensing. Flyback converter stops
switching when output voltage reaches:
VOUT = K × N - Vd ,
where:
K = 31.5 typically,
Vd is the forward drop of the output diode (around 2 V), and
N is transformer turns ratio.
Toggling the CHARGE pin reinitiates charging operation.
Switch On-Time and Off-Time Control
The A8738 implements an adaptive on-time/off-time control. Ontime duration, ton , is equal to ton = ISWlim × LP / VBAT. Off-time
duration, toff , depends on the operating conditions during switch
off-time. The A8738 applies two charging modes, Fast Charging
mode and Timer mode, according to those conditions.
Timer Mode and Fast Charging Mode
The A8738 achieves fast charging times and high efficiency by
operating in discontinuous conduction mode (DCM) through
most of the charging process The relationship of Timer mode and
Fast Charging mode is shown in figure 3.
The IC operates in Timer mode when beginning to charge a completely discharged photoflash capacitor, usually when the output
voltage, VOUT, is less than approximately 15 to 20 V. Timer mode
is a fixed period, 13 μs, off-time control. One advantage of having Timer mode is that it limits the initial battery current surge
VOUT
Timer Mode
Fast Charging Mode
VBAT
IIN
Figure 3. Timer mode and Fast Charging mode: t = 200 ms/div;
VOUT = 50 V/div; VBAT = 1 V/div.; IIN = 100 mA/div., VBAT = 3.6 V;
COUT = 20 μF / 330 V; and ISWlim ≈ 0.75 A.
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A8738
Fixed Gate Drive Xenon Photoflash Charger
and thus acts as a “soft-start.” A time-expanded view of a Timer
mode interval is shown in figure 4.
As soon as a sufficient voltage has built-up at the output capacitor, the IC enters Fast-Charging mode. In this mode, the next
switching cycle starts after the secondary side current has stopped
flowing, and the switch voltage has dropped to a minimum value.
A proprietary circuit is used to allow minimum-voltage switching, even if the SW pin voltage does not drop to 0 V. This enables
Fast-Charging mode to start earlier, thereby reducing the overall
charging time. Minimum-voltage switching is shown in figure 5.
During Fast-Charging mode, when VOUT is high enough (over
50 V), true zero-voltage switching (ZVS) is achieved. This
further improves efficiency as well as reduces switching noise. A
ZVS interval is shown in figure 6.
Switch Current Setting
ISET = VSET / (RSET + RSET(INT) – K × RGND(INT) ) ,
(4)
where:
RSET(INT) is the internal resistance of the ISET pin (1 kΩ typical),
RGND(INT) is the internal resistance of the bonding wire for the
GND pin (27 mΩ typical), and
K = (K′ + VIN × K″), with K′ = 24350 and K″ ≈ 1040 at
TA = 25°C.
Then,
ISWlim = ISET × K + VBAT / LPrimary × tD ,
where tD is the delay in SW turn-off (0.1 μs typical).
The chart in figure 7 can be used to determine the relationship
between RSET and ISWlim at various battery voltages.
The A8738 features continuously adjustable peak switching current between 0.4 and 0.9 A. This is done by selecting the value of
an external resistor, RSET, connected from the ISET pin to GND,
which determines the ISET bias current, and therefore the switching current limit, ISWlim.
To the first order approximation, ISWlim is related to ISET and
RSET according to the following equations:
ISWlim = ISET × K = VSET / RSET × K ,
VSW
VBAT
(3)
where K = 28000 when battery voltage is 3.6 V.
In real applications, the actual switching current limit is affected
by input battery voltage, and also the transformer primary inductance, LPrimary. If necessary, the following expressions can be
used to determine ISWlim more accurately:
VOUT
ISW
Figure 5. Minimum-voltage switching: VOUT ≥ 15 V; t =1 μs/div;
VBAT = 3.6 V.
VOUT
VSW
VSW
VSW
VBAT
VBAT
VOUT
ISW
Figure 4. Expanded view of Timer mode: VOUT ≤ 14 V; t = 2 μs/div;
VBAT = 3.6 V.
VBAT
ISW
VOUT
ISW
Figure 6. True zero-voltage switching (ZVS): VOUT = 120 V; t =0.2 μs/div;
VBAT =3.6 V.
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A8738
Fixed Gate Drive Xenon Photoflash Charger
Smart Current Limit (Optional)
With the help of some simple external logic, charging current
can be varied according to the battery voltage. For example, let’s
say ISET current is normally 33 μA (for ILIM = 0.9 A). When the
battery voltage drops below 2.5 V, a BL (battery-low) signal from
external controller goes high. A resistor connecting from BL to
ISET pin then injects 15 μA into RSET. This effectively reduces
ISET current to 18 μA (for ILIM = 0.5 A) (see figure 8).
BL
RBL
ISET
RSET
Charge Pump Operation
The A8738 integrates a regulated 2× charge pump to regulate
gate voltage across a wide range of supply voltages. It can regulate output voltage to 3 V over the entire range of VIN. The charge
pump is enabled as long as the CHARGE pin is high. Figure 9
shows a timing diagram for output capacitor charging and VBIAS.
Figure 8. Smart current limiting option
Peak Current Limit versus ISET Resistance
VIN = VBAT, XFM Lp = 8 μH, TA=25°C
1.3
1.2
1.1
VIN = 5.5 V
VIN = 4.5 V
ISWlim (A)
1.0
VIN = 3.6 V
VIN = 3.0 V
0.9
VIN = 2.3 V
0.8
0.7
0.6
0.5
0.4
35
40
45
50
55
60
65
70
75
80
85
90
RSET (kΩ)
Figure 7. Determination of value for current limiting
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A8738
Fixed Gate Drive Xenon Photoflash Charger
In figure 9, at time A, the output capacitor is completely discharged and the CHARGE pin is pulled high. The flyback
converter charges the output capacitor to the target output level at
¯ pin goes low, indicating Charge Complete.
time C, and the D̄¯¯ Ō¯¯N̄¯Ē
The charge pump output voltage reaches 3 V during time interval
A–B. The charge pump stops regulating voltage after time D, as
the CHARGE pin is pulled low.
Voltage across CBIAS (C2) may drop after this time due to leakage. The voltage drop is:
ΔVBIAS = 0.2 μA × time / CBIAS ,
where 0.2 μA is the internal leakage current via the VBIAS pin.
To minimize VBIAS voltage droop, apply the TRIGGER pulse
within a few milliseconds (<100 ms) after the CHARGE pin is
pulled low.
A short pre-flash trigger pulse is applied at time E. The typical
IGBT gate charge is 40 nC. This charge is supplied by CBIAS ,
and VBIAS drops by 40 nC / CBIAS . The main trigger pulse is
applied at time G. Voltage VBIAS drops further in this period.
IGBT gate voltage drops due to charge transfer to the IGBT gate.
The IGBT trigger pulse can be applied at any time, as shown at
time instance I.
Figure 9. Timing diagram for output capacitor charging and charge pump
output (Not to Scale)
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A8738
Fixed Gate Drive Xenon Photoflash Charger
Applications Information
toff = (ISWlim / N) × LS /VOUT
Transformer Design
1. The transformer turns ratio, N, determines the output voltage:
= (ISWlim × LP × N) /VOUT .
N = NS / NP
The minimum pulse width for toff determines what is the
minimum LPrimary required for the transformer. For example, if
ISWlim = 0.7 A, N = 10, and VOUT = 315 V, then LPrimary must be
VOUT = 31.5 × N – Vd ,
where 31.5 is the typical value of VOUTTRIP , and Vd is the forward drop of the output diode.
at least 6.3 μH in order to keep toff at 140 ns or longer. These
relationships are illustrated in figure 10.
2. The primary inductance, LP , determines the on-time of the
switch:
In general, choosing a transformer with a larger LPrimary results in
higher efficiency (because a larger LPrimary corresponds to a lower
switch frequency and hence lower switching loss). But transformers with a larger LPrimary also require more windings and larger
magnetic cores. Therefore, a trade-off must be made between
transformer size and efficiency.
ton = (–LP / R ) × ln (1 – ISWlim × R /VIN) ,
where R is the total resistance in the primary current path (including RSWDS(on) and the DC resistance of the transformer).
If VIN is much larger than ISWlim × R, then ton can be approximated by:
ton = ISWlim × LP /VIN .
Leakage Inductance and Secondary Capacitance
The transformer design should minimize the leakage inductance to ensure the turn-off voltage spike at the SW node does
not exceed the absolute maximum specification on the SW pin
(refer to the Absolute Maximum Ratings table). An achievable
minimum leakage inductance for this application, however, is
3. The secondary inductance, LS, determines the off-time of the
switch. Given:
LS / LP = N × N , then
ton
toff
VSW
ISW
Vr
tf
VIN
VIN
VSW
ISW
tneg
Figure 10. Transformer Selection Relationships
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A8738
Fixed Gate Drive Xenon Photoflash Charger
usually compromised by an increase in parasitic capacitance.
Furthermore, the transformer secondary capacitance should be
minimized. Any secondary capacitance is multiplied by N2 when
reflected to the primary, leading to high initial current swings
when the switch turns on, and to reduced efficiency.
Input Capacitor Selection
Ceramic capacitors with X5R or X7R dielectrics are recommended for the input capacitor, CIN. During initial timer mode
the device operates with 13 μs off time. Resonant period caused
by input filter inductor and capacitor should be at least 2 times
greater or smaller than the 13 μs timer period, to reduce input
ripple current during this period. The typical input LC filter is
shown in figure 11.
The resonant period is given by:
Tres = 2
Figure 12. Input current waveforms with Li+ battery connected
by 5-in. wire and decoupled by 4.7 μF capacitor. CH1: VOUT =
100 V/div, CH2: VBAT = 2 V/div, CH4: IIN(av) = 500 mA/div, Time =
200 ms/div, COUT = 21 μF, RISET = 36 kΩ
(L × CIN)1/2 .
Effect of input filter components is shown in figures 12, 13, and
14. It is recommended to use at least 4.7 μF / 6.3 V to decouple
the battery input, VBAT , at the primary of the transformer.
Decouple VIN pin using 0.1 μF / 6.3 V bypass capacitor.
Output Diode Selection
Choose the rectifying diode(s), D1, to have small parasitic capacitance (short reverse recovery time) while satisfying the reverse
voltage and forward current requirements. The peak reverse
voltage of the diode, VDPeak , occurs when the internal MOSFET
switch is closed. It can be calculated as:
VDPeak = VOUT + N × VBAT .
The peak current of the rectifying diode, IDPeak, is calculated as:
Figure 13. Input current waveforms with Li+ battery connected
through 10 μH inductor and 4.7 μF capacitor. CH1: VOUT =
100 V/div, CH2: VBAT = 2 V/div, CH4: IIN(av) = 500 mA/div, Time =
200 ms/div, COUT = 21 μF, RISET = 36 kΩ
I DPeak = IPrimary_Peak / N .
LIN
+
VBAT
CIN
A8738
Figure 11. Typical input section with input inductance
(inductance, LIN, may be an input filter inductor or
inductance due to long wires in test setup)
Figure 14. Input current waveforms with Li+ battery connected
through 10 μH inductor and 10 μF capacitor. CH1: VOUT = 100 V/div,
CH2: VBAT = 2 V/div, CH4: IIN(av) = 200 mA/div, Time = 200 ms/div,
COUT = 21 μF, RISET = 36 kΩ
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16
A8738
Fixed Gate Drive Xenon Photoflash Charger
Bias Capacitor Selection
Select bias capacitor sufficiently large to hold the voltage during
Charging done and trigger applied. Also this capacitor provides
charge to IGBT gate capacitance during every flash period. It is
recommended to use a 1 μF / 6.3 V capacitor for this application.
If the voltage droop is more than requirement, increase capacitor
accordingly. The MLCC (multi-layer ceramic capacitor) specify
capacitance at zero-bias voltage. When a DC bias is applied, the
capacitance may be reduced by as much as 70%. For example,
when a ceramic capacitor rated as 0.47 μF / 6.3 V biased at
5 VDC could have capacitance equal to 0.15 μF. A larger package (such as a 0603) is preferred over a smaller one (such as a
0402), because the capacitance derating is worse for capacitors
with smaller package and lower operating voltage. See the table
Recommended Components for more information.
Layout Guidelines
Key to a good layout for the photoflash capacitor charger circuit
is to keep the parasitics minimized on the power switch loop
(transformer primary side) and the rectifier loop (secondary side).
Use short, thick traces for connections to the transformer primary
¯ signal trace and other
and SW pin. It is important that the D̄¯¯ Ō¯¯N̄¯Ē
signal traces be routed away from the transformer and other
switching traces, in order to minimize noise pickup. In addition,
high voltage isolation rules must be followed carefully to avoid
breakdown failure of the circuit board.
Avoid ground plane underneath transformer secondary and diode
to minimize parasitic capacitance.
For low threshold logic (<1.2 V) add 1 nF capacitors across the
CHARGE and TRIGGER pins to GND to avoid malfunction due
to noise.
Connect EJ package PAD, or CG package GND pins to ground
pad for better thermal performance. Use ground planes on both
the top and bottom layers below the IC, and connect through
multiple thermal vias. Refer to the figures on the next page for
recommended layout.
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A8738
Fixed Gate Drive Xenon Photoflash Charger
Recommended layout:
Schematic
Top side
Bottom side
Top components
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A8738
Fixed Gate Drive Xenon Photoflash Charger
Recommended Components
Component
Rating
Part Number
Source
C1
0.1 uF, 6.3 V, X5R ceramic capacitor
C2, Bias Capacitor
1 μF, ±10%, 6.3 V, X7R ceramic capacitor (0603)
GRM188R60J105
Murata
CIN, Input Capacitor
4.7 μF, ±10%, 6.3 V, X5R ceramic capacitor (0805)
JMK212BJ475K
Taiyo Yuden
COUT , Photoflash Capacitor
80 μF / 330 V
EPH-331E--800A030S
Chemi-Con
D1, Output Diode
2 x 250 V, 225 mA, 5 pF
BAV23S
Philips Semiconductor,
Fairchild Semiconductor
Lprimary = 8 μH, N = 9.9, 5 mm x 5 mm x 2.2 mm
C5-KT2.2L
Mitsumi Electric Co.
Lprimary = 6.6 μH, N = 10.2, 5 mm x 5 mm x 2 mm
T-19-243
Tokyo Coil Electric
Rset
36 kΩ, 1%
R1
23 Ω, 0603
R2
30 Ω 0603
T1, Transformer
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A8738
Fixed Gate Drive Xenon Photoflash Charger
Package EJ 10-Contact TDFN
with Exposed Thermal Pad
0.30
3.00 ±0.15
0.85
0.50
10
10
3.00 ±0.15
1.65
3.10
A
1
2
1
11X
D
SEATING
PLANE
0.08 C
+0.05
0.25 –0.07
C
C
2.38
PCB Layout Reference View
0.75 ±0.05
0.50
1
For Reference Only
(reference JEDEC MO-229WEED)
Dimensions in millimeters
Exact case and lead configuration at supplier discretion within limits shown
2
0.40 ±0.10
1.65
B
10
2.38
A Terminal #1 mark area
B Exposed thermal pad (reference only, terminal #1
identifier appearance at supplier discretion)
C Reference land pattern layout (reference
IPC7351 SON50P300X300X80-11WEED3M);
All pads a minimum of 0.20 mm from all adjacent pads; adjust as
necessary to meet application process requirements and PCB layout
tolerances; when mounting on a multilayer PCB, thermal vias at the
exposed thermal pad land can improve thermal dissipation (reference
EIA/JEDEC Standard JESD51-5)
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Worcester, Massachusetts 01615-0036 U.S.A.
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A8738
Fixed Gate Drive Xenon Photoflash Charger
Revision History
Revision
Revision Date
Rev. 1
April 19, 2012
Description of Revision
A8738 only, miscellaneous format changes
Copyright ©2008-2012, Allegro MicroSystems, Inc.
Allegro MicroSystems, Inc. reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the
information being relied upon is current.
Allegro’s products are not to be used in life support devices or systems, if a failure of an Allegro product can reasonably be expected to cause the
failure of that life support device or system, or to affect the safety or effectiveness of that device or system.
The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no responsibility for its use;
nor for any infringement of patents or other rights of third parties which may result from its use.
For the latest version of this document, visit our website:
www.allegromicro.com
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