HIP4011 Three Phase Brushless DC Motor Controller April 1994 Features Description • 3A DC, 5A Peak Output Current The HIP4011 motor driver is intended for three phase Brushless motor control at continuous output currents up to 3A. It • 16V Max. Rated Supply Voltage accepts inputs from buffered Hall effect sensors and drives [ /Title (HIP4011) three motor windings, regulating the current through an • Built-in “Free-Wheeling” Diodes /Subject (Three Phase Brushless DC Motor Controller) external current sensing resistor, according to an analog •/Author Output () dv/dt Limited to Reduce EMI control input. Output “freewheeling” diodes are built in and output dv/dt is limited to decrease the generated EMI. •/Keywords External Dynamic Brake Control Switch With () Thermal and current limiting are used to protect the device Undervoltage Sense /Creator () from locked rotor conditions. A brake control input forces all •/DOCINFO Thermal and Current Limiting Protects Against outputs to ground simultaneously to provide dynamic pdfmark Locked Rotor Conditions braking, and an internal voltage sensor does the same when the supply drops below a predetermined switch point. Power •[ /PageMode Provides Analog Current Sense and Reference Inputs /UseOutlines down braking energy is stored in an external capacitor. /DOCVIEW pdfmark • Decode Logic with Illegal Code Rejection Applications Ordering Information • Drive Spindle Motor Controller PART NUMBER • 3 Phase Brushless DC Motor Controller • Brushless DC Motor Driver for 12V Battery Powered Appliances TEMPERATURE RANGE PACKAGE -40oC to +85oC HIP4011IS 15 Pin Plastic SIP Surface Mount • Phased Driver for 12V DC Applications • Logic Controlled Driver for Solenoids, Relays and Lamps Pinout OUTPUT TRUTH TABLE HIP4011 (SIP) TOP VIEW PGND PIN (TAB) MUST BE ELECTRICALLY CONNECTED 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 FORCE BRAKE INPUT* SENSOR INPUTS SGND SPD SV+ ISEN OUTA BCAP PV+ OUTB ISEN FBRK OUTC PV+ SENC SENB SENA = SIGNAL GROUND = SPEED CONTROL = SIGNAL V+ = ISENSE = OUTPUT A = BRAKING CAPACITOR = POWER V+ = OUTPUT B = ISENSE = FORCED BRAKE = OUTPUT C = POWER V+ = SENSE INPUT C = SENSE INPUT B = SENSE INPUT A OUTPUTS A B C FBRK A B C 0 0 0 0 OFF OFF OFF 1 0 0 0 1 OFF 0 0 1 0 0 0 1 OFF 1 1 0 0 OFF 1 0 0 0 1 0 OFF 0 1 1 0 1 0 1 0 OFF 0 1 1 0 0 OFF 1 1 1 1 0 OFF OFF OFF X X X 1 0 0 0 * Undervoltage and Force Brake logic truth table entries are identical. “X” = Don’t Care CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 407-727-9207 | Copyright © Intersil Corporation 1999 6-11 File Number 2939.3 Specifications HIP4011 Absolute Maximum Ratings Thermal Information Supply Voltage, SV+ or PV+. . . . . . . . . . . . . . . . . . . . . . -1V to +16V Referred to SGND or PGND (Note 1) Output Current, Continuous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3A Output Current, Peak (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . 5A Substrate (PGND) Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1A Logic Input Current . . . . . . . . . . . . . . . . . . . . . . . . . -20mA to +20mA (Clamped to SV+ and SGND) Thermal Resistance θJA θJC 15 Lead SIP Power Package. . . . . . . . . . 45oC/W 3oC/W Power Dissipation (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25W Junction Temperature Range, Operating . . . . . . . . . . . . . . . +150oC Storage Temperature Range. . . . . . . . . . . . . . . . . . -55oC to +150oC Power Dissipation Up to +125oC without heat sink . . . . . . . . . . . . . . . . . . . . . 0.56W Above +125oC without Heat Sink . . Derate Linearly at 22mW/ oC Up to +125oC with Infinite Heat Sink . . . . . . . . . . . . . . . . . 8.33W Above +125oC with Infinite Heat Sink . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Derate Linearly at 333mW/oC Lead Temperature (During Soldering) At a Distance 1/16 inch ±1/32 inch (1.59mm ±0.79mm) from Case for 10s Max. . . . . . . . . . . . . . . . . . . . . . . . . . +265oC NOTES: 1. PV+ and SV+ are to be tied together, as are PGND and SGND. 2. Operating above the continuous current rating causes a decrease in operating life. 3. Derate power dissipation above case temperature of +75oC at 0.33 Watts/oC. CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Electrical Specifications TA = +25oC and SV+ = PV+ = 10.4V to 13.2V, Unless Otherwise Specified PARAMETERS TEST CONDITION MIN TYP MAX UNITS SUPPLY (SV+) CURRENT No Drive Outputs Off - - 10 mA With Drive Outputs On - - 15 mA -0.5 - -1.5 mA 50 - 150 µA LOGIC INPUT CURRENT Sensor Inputs SENA, SENB & SENC = 0V to 3V Brake Input FBRK = 0.8V to 2.4V LOGIC INPUT THRESHOLDS Sensor Inputs Logic “0” Input Voltage - - 1.8 V Sensor Inputs Logic “1” Input Voltage 3 - - V Brake Input Logic “0” Input Voltage - - 0.8 V Brake Input Logic “1” Input Voltage 2.4 - - V Bias Current - - 700 nA Offset Voltage - - 3 mV Input Range (Linear) 0 - 1 V Input Impedance 1 - - MΩ AMPLIFIER INPUT (SPD) System Bandwidth (Note 1) - 35 - kHz Current Limit Rsense = 0.20Ω - 5 - A Threshold - 155 - oC Hysteresis - 40 - oC THERMAL LIMIT OUTPUT DRIVERS On Saturation (See Note 5) IOUT = 3A, VPMOS + VNMOS - - 2.2 V On Saturation (See Note 5) IOUT = 0.6A, VPMOS + VNMOS - - 0.44 V Off Leakage PV+ > VOUT > PGND or ISEN - - 1 mA Slew Rate (See Note 2) - 0.5 - V/µS 6-12 HIP4011 TA = +25oC and SV+ = PV+ = 10.4V to 13.2V, Unless Otherwise Specified (Continued) Electrical Specifications PARAMETERS TEST CONDITION MIN TYP MAX UNITS - - 1.5 V FREEWHEEL DIODES Forward Drop IOUT = 1A INTERNAL BRAKE DRIVER Undervoltage Trip Point, PV+ (See Note 3) 2.7 - 3.3 V Hysteresis (See Note 4) 40 - 60 % On Saturation Each NMOS, IOUT = 3A - - 0.4 V SV+ = PV+ = 3V to 12V, BCAP = 10V - - 5 µA BRAKE CAPACITOR (BCAP) Discharge Leakage NOTES: 1. The system bandwidth is fixed by an internal RC network around the amplifier. 2. Internal limiting of turn on and turn off drive is used to limit output dv/dt. 3. The braking action starts at the given trip point with a falling supply voltage. 4. Hysteresis causes the brake to be removed at a higher trip point with a rising supply voltage. 5. This value includes the combined voltage drops of one upper plus one lower switch at the indicated current. Functional Block Diagram BCAP SIGNAL V+ 13 V+ 1mA 10 V+ 4 PV+ 9 PV+ SENA 1 11 MOTOR φB V+ DECODE LOGIC WITH ILLEGAL CODE REJECTION 1mA SENB 2 HALL SENSOR B OUTB 8 OUTC V+ ISEN (CURRENT LIMITING REF) + 38.5K C1 100pF HALL SENSOR C BREAK BEFORE MAKE THERMAL SENSING R1 100µA 14 12 VCL 3 6 ISEN CURRENT LIMITING SENC FBRK MOTOR φC 5 1mA IREF POWER V+ MOTOR φA OUTA HALL SENSOR A FORCE BRAKE BRAKE CAP. VBS (BRAKE (SENSE REF) 39K R2 39K 15 SIGNAL SGND GND 6-13 7 1K 1K CURRENT SENSE RESISTOR PGND TAB SUBSTRATE GND HIP4011 All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. 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