Package Outline Drawing (POD)

Plastic Packages for Integrated Circuits
Package Outline Drawing
W4x5.20A
20 BALL WAFER LEVEL CHIP SCALE PACKAGE (WLCSP)
Rev 2, 6/16
1.200
X
1.595 ±0.02
Y
0.400
5
0.400
20X 0.270 ±0.03
4
3
2.335 ±0.02
1.600
2
1
0.367
(4X)
0.10
A
PIN 1 (A1 CORNER)
TOP VIEW
B
C
D
0.197
0.200
BOTTOM VIEW
Z
0.05 Z
PACKAGE
OUTLINE
0.225
3
SEATING PLANE
0.300 ±0.025
0.400
0.275
0.270 ±0.03
0.10
0.05
ZXY
Z
0.200 ±0.03
TYPICAL RECOMMENDED LAND PATTERN
0.555 MAX
SIDE VIEW
NOTES:
1. Dimensions and tolerance per ASME Y 14.5M - 1994.
2. Dimension is measured at the maximum bump diameter
parallel to primary datum Z .
3. Primary datum Z and seating plane are defined by the spherical
crowns of the bump.
4. Bump position designation per JESD 95-1, SPP-010.
5. There shall be a minimum clearance of 0.10mm between
the edge of the bump and the body edge.
1