Plastic Packages for Integrated Circuits Package Outline Drawing W4x5.20B 20 BALL WAFER LEVEL CHIP SCALE PACKAGE (WLCSP) Rev 2, 9/12 1.200 X 1.82±0.03 PIN 1 (A1 CORNER) Y 0.400 A 0.400 B 20x 0.265 ± 0.03 C 2.15±0.03 1.600 D E (2X) 0.10 4 3 2 1 0.200 TOP VIEW BOTTOM VIEW Z 0.05 Z SEATING PLANE 3 PACKAGE OUTLINE 0.225 0.305 ± 0.025 0.400 0.265±0.035 0.275 0.15 0.05 ZXY Z 0.200±0.03 0.500±0.045 TYPICAL RECOMMENDED LAND PATTERN SIDE VIEW NOTES: 1. Dimensions and tolerance per ASME Y 14.5M - 1994. 2. Dimension is measured at the maximum bump diameter parallel to primary datum Z. 3. Primary datum Z and seating plane are defined by the spherical crowns of the bump. 4. Bump position designation per JESD 95-1, SPP-010. 5. There shall be a minimum clearance of 0.10mm between the edge of the bump and the body edge. 1