Package Outline Drawing (POD)

Plastic Packages for Integrated Circuits
Package Outline Drawing
W4x6.24
4X6 ARRAY 24 BALL WAFER LEVEL CHIP SCALE PACKAGE (WLCSP)
Rev 1, 9/10
1.60± 0.02
24X 0.270 ± 0.03
1.20
PIN A1
F
E
D
2.40± 0.02
2.00
C
B
0.40
A
1
TOP VIEW
2
3
4
BOTTOM VIEW
0.305 ± 0.025
0.55 mm MAX
Z SEATING PLANE
0.19 ± 0.03
0.27 ± 0.03
0.05 Z
Ø0.10 M Z X Y
Ø0.05 M Z
SIDE VIEW
0.275
PACKAGE
OUTLINE
NOTES:
1. All dimensions are in millimeters.
2. Dimension and tolerance per ASMEY 14.5M-1994,
and JESD 95-1 SPP-010.
3. NSMD refers to Non-solder Mask Defined pad design per
Intersil Tech Brief TB451 located at:
http://www.intersil.com/data/tb/tb451.pdf.
0.225
0.40
3
NSMD
TYPICAL RECOMMENDED LAND PATTERN
1