Package Outline Drawing (POD)

Plastic Packages for Integrated Circuits
Package Outline Drawing
W4x5.20J
20 BALL WAFER LEVEL CHIP SCALE PACKAGE (WLCSP 0.4mm Pitch) 
Rev 1, 1/15
X
Y
0.400
1.64 ± 0.030
E
D
20x 0.265 ±0.035
2.18 ±0.030
C
B
A
(4X)
0.10
PIN 1
(A1 CORNER)
TOP VIEW
0.290
1
2
3
4
0.200
0.220
BOTTOM VIEW
Z
0.240
0.05 Z
PACKAGE OUTLINE
SEATING PLANE
3
0.400
0.290
2
0.265 ±0.035 x20
0.10
0.05
Z X Y
Z
4
0.200 ±0.030
6 NSMD
0.500 ±0.050
RECOMMENDED LAND PATTERN
SIDE VIEW
NOTES:
1. Dimensions and tolerance per ASMEY 14.5 - 1994.
2. Dimension is measured at the maximum bump diameter parallel to primary datum Z.
3. Primary datum Z and seating plane are defined by the spherical crowns of the bump.
4. Bump position designation per JESD 95-1, SPP-010.
5. All dimensions are in millimeters.
6. NSMD refers to non-solder mask defined pad design per Intersil Techbrief TB451.
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