Package Outline Drawing (POD)

Plastic Packages for Integrated Circuits
Package Outline Drawing
W5x5.25
5X5 ARRAY 25 BALL WAFER LEVEL CHIP SCALE PACKAGE (WLCSP)
Rev 1, 2/13
2.000
2.600 ±0.030
X
25X 0.320 ± 0.030
Y
E
D
2.600 ±0.030
C
B
0.500
A
0.10
(4X)
0.300
1
PIN 1 (A1 CORNER)
2
3
4
5
0.500
TOP VIEW
0.300
BOTTOM VIEW
PACKAGE OUTLINE
0.330
0.280
0.540±0.040mm
0.500
0.240 ± 0.030
0.320 ± 0.030 X25
0.10
0.05
3 NSMD
ZXY
Z
TYPICAL RECOMMENDED LAND PATTERN
Z SEATING
PLANE
0.05 Z
SIDE VIEW
NOTES:
1. All dimensions are in millimeters.
2. Dimension and tolerance per ASMEY 14.5M-1994,
and JESD 95-1 SPP-010.
3. NSMD refers to Non-solder Mask Defined pad design per
Intersil Tech Brief TB451 located at:
http://www.intersil.com/data/tb/tb451.pdf
1