751AP

MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOIC−14
CASE 751AP
ISSUE B
14
1
SCALE 1:1
DATE 18 MAY 2015
0.10 C D
NOTES 4&5
45 5 CHAMFER
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION.
H
ALLOWABLE PROTRUSION SHALL BE 0.004 mm IN EXCESS OF
MAXIMUM MATERIAL CONDITION.
4. DIMENSION D DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS
OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS
SHALL NOT EXCEED 0.006 mm PER SIDE. DIMENSION E1 DOES
NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD
FLASH OR PROTRUSION SHALL NOT EXCEED 0.010 mm PER SIDE.
5. THE PACKAGE TOP MAY BE SMALLER THAN THE PACKAGE BOT­
TOM. DIMENSIONS D AND E1 ARE DETERMINED AT THE OUTER­
SEATING
L
MOST EXTREMES OF THE PLASTIC BODY AT DATUM H.
C PLANE
6. DIMENSIONS A AND B ARE TO BE DETERMINED AT DATUM H.
DETAIL A
7. DIMENSIONS b AND c APPLY TO THE FLAT SECTION OF THE LEAD
BETWEEN 0.10 TO 0.25 FROM THE LEAD TIP.
8. A1 IS DEFINED AS THE VERTICAL DISTANCE FROM THE SEATING
PLANE TO THE LOWEST POINT ON THE PACKAGE BODY.
h
D
NOTE 6
D
A
14
2X
8
0.10 C D
E
E1
NOTES 4&5
L2
0.20 C D
2X
1
7
B
14X b
NOTE 6
0.25
TOP VIEW
M
C A-B D
NOTES 3&7
DETAIL A
A2
NOTE 7
0.10 C
A
e
A1
C
SIDE VIEW
NOTE 8
DIM
A
A1
A2
b
c
D
E
E1
e
h
L
L2
c
END VIEW
SEATING
PLANE
RECOMMENDED
SOLDERING FOOTPRINT*
MILLIMETERS
MIN
MAX
--1.75
0.10
0.25
1.25
--0.31
0.51
0.10
0.25
8.65 BSC
6.00 BSC
3.90 BSC
1.27 BSC
0.25
0.41
0.40
1.27
0.25 BSC
GENERIC
MARKING DIAGRAM*
14X
0.76
14
XXXXXXXXXG
AWLYWW
14X
1.52
1
7.00
XXXXX
A
WL
Y
WW
G
1
1.27
PITCH
DIMENSIONS: MILLIMETERS
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
DOCUMENT NUMBER:
STATUS:
98AON30871E
ON SEMICONDUCTOR STANDARD
REFERENCE:
© Semiconductor Components Industries, LLC, 2002
October, DESCRIPTION:
2002 − Rev. 0
SOIC−14
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
http://onsemi.com
1
Electronic versions are uncontrolled except when
accessed directly from the Document Repository. Printed
versions are uncontrolled except when stamped
“CONTROLLED COPY” in red.
Case Outline Number:
PAGE 1 OFXXX
2
DOCUMENT NUMBER:
98AON30871E
PAGE 2 OF 2
ISSUE
REVISION
DATE
O
RELEASED FOR PRODUCTION FROM POD #6000209 TO ON SEMICONDUCTOR.
REQ. BY B. BERGMAN.
19 JUN 2008
A
CHANGED FROM A MULTI−PIN CASE OUTLINE DESCRIPTION TO A SOIC−14
CASE OUTLINE DESCRIPTION. REQ. BY B. BERGMAN.
29 AUG 2008
B
REDREW DRAWING TO JEDEC STANDARDS AND ADDED SOLDER FOOTPRINT.
REQ. BY F. KOLANKO.
18 MAY 2015
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
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intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
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© Semiconductor Components Industries, LLC, 2015
May, 2015 − Rev. B
Case Outline Number:
751AP
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