AN1779: Configuring Current Sharing on the ZL6105 and ZL8101

Application Note 1779
Author: Barry Kates
Configuring Current Sharing on the ZL6105 and ZL8101
Introduction
TABLE 2. COMPLETE ISHARE_CONFIG FIELD
This application note describes the features and setup
procedure for the ZL6105 and ZL8101 digital DC controllers
configured in current sharing groups. These products employ
an inter-device communication Bus called the Digital-DC bus
(DDC Bus). The DDC Bus enables Intersil Zilker Labs IC’s to
exchange critical real-time telemetry to any device connected
to the Bus. The DDC Bus enables advanced power
management, fault management, sequencing, and many
other features.
Overview
A current sharing group is comprised of 2 or more parallel
converters operating at the same frequency, but interleaved in
such a way to multiply the input and output ripple frequency by
the number of paralleled phases. Paralleling converters in this
manner has the added benefits of reducing the input filter
stress, distributing the converter thermal load, reducing
volume and weight and many other advantages. Figure 1 is a
typical example of a 2-phase current sharing group. Multiple
current sharing groups and power rails can communicate and
connect to the same DDC Bus.
DDC Bus
Zilker Labs (Digital-DC) products utilize a unique dedicated
serial bus (DDC bus) to synchronize and communicate
real-time events to other Zilker Labs devices connected to the
bus. A 5-bit address is assigned to each DDC Bus controller
based on the 5 LSB’s of its SMBus address and comprises the
Rail DDC ID#. This Rail DDC ID# is used to specify which
controllers on the same DDC Bus listen and respond to Fault
Spreading and Sequencing.
The Rail DDC ID# is automatically assigned as the IShare Rail
ID in the ISHARE_CONFIG command. However, the IShare Rail
ID number must be common to each controller in the current
sharing group and not used to define any other output rail.
Table 1 below serves as an example for the current sharing
group in Figure 1. In this example the IShare Rail ID has been
arbitrarily assigned a value of 5.
BINARY
5 LSBs
RAIL
DDC ID
0x21
00100001
00001
1
0x22
00100010
00010
2
ISHARE
RAIL ID
5
Table 2 illustrates the complete structure of the
ISHARE_CONFIG field.
A maximum of 7 devices or phases is allowed in a sharing
group. Please ensure that the DDC signal integrity is
maintained by adjusting the pull-up resistor value when using
a large device count.
December 23, 2013
AN1779.1
1
BITS
PURPOSE
15:8
VALUE
DESCRIPTION
Sets the current share rail’s
DDC ID for each controller
within a current share rail.
0 to 31
IShare Rail ID
(0x00 to 0x1F Each controller in the sharing
group must have the same
IShare Rail ID
7:5
Number of
Devices
0 to 7
Number of devices in current
share rail -1
4:2
Device Position
0 to 7
Position of device within
current share rail
1
Reserved
0
Device is not a member of a
current share rail
0
0
Current Share
Control
Device is not a member of a
current share rail
1
Device is a member of a
current share rail
During DDC events, all devices will receive transmissions,
however, only those devices configured to respond will do so.
DDC devices can also transmit events if the configuration
requires inter device communication. Some examples include
fault spreading, sequencing, phase add/drop, broadcast
margin, broadcast enable, and auto compensation.
Vpull-up
DDC
SDA
SCL
ZL6105
0x21
VCC
PH_1
GH
SW
DDC
SDA
SCL
SY NC
Rout
Cout
GL
SEN+
SEN-
ZL6105
0x22
VCC
SY NC
GH
SW
DDC
SDA
SCL
TABLE 1. CONFIGURING ISHARE RAIL ID#
PMBUS
ADDRESS
ISHARE_CONFIG
PH_2
GL
SEN+
SEN-
FIGURE 1. TYPICAL CURRENT SHARING APPLICATION
Active Droop Current Sharing
Zilker Labs current sharing devices use a patented form of
digitally controlled active droop, resulting in the highest degree
of phase current balancing. The specific droop is configured
based on the application and is set to the same value for each
group member.
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
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Application Note 1779
Total Load Current = 114.5A / 3 = 38.16A
1.10
1.05
1.00
0.95
Ref
Mem_1
Mem_2
38.16A / Ph
0.90
0.85
0.80
Figure 2 is an example of a current sharing application whose
loadlines were all configured to 1mΩ. Due to differences in layout
and component variances the actual member loadlines contain
slope differences; they are exaggerated in this example.
Each phase carries 38.16A
Group Loadline is equal to configured
loadline = 1 mOhm
0.65
0.60
0.55
5
10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90 95 100 105 110 115 Iout
FIGURE 3. MEMBER(S) REFERENCE VOLTAGE IS TRIMMED UNTIL
ALL DEVICE CURRENTS EQUALIZE
The Current sharing equilibrium is shown in Figure 4 with a
singular loadline being plotted that represents the actual static
V-I characteristic for the sharing group. Since each group
member in this example is configured to 1mΩ, the slope of the
sharing group is equal to 1mΩ.
Actual Current Share Loadline = 1 mOhm
Vout
Current Sharing Algorithm
1.20
1.15
Total Load Current = 114.5A / 3 = 38.16A
1.10
1.05
Unbalanced Phase Currents
Vout
1.15
0.70
The controller with the lowest SMBus address in the current
sharing group is designated as the Reference Device. The
Reference Device continuously broadcasts its inductor current
over the DDC bus, while each Member device receives the
transmission and trims its output voltage up or down until all
group members supply the same current to the load. The process
of broadcasting the Reference’s load current and trimming each
Member’s output voltage to achieve current balance continues
unless a fault occurs or the Reference Phase is dropped.
1.00
1.20
1.10
1.20
0.75
Reference Device
1.15
Balanced Phase Currents
Vout
The droop function is implemented in both hardware (fast and
local) and firmware (slow over DDC Bus). During turn-on/off a
combination of droop and a unique ramping algorithm results in
near perfect current sharing. The specific value of droop typically
ranges between 0.15mΩ and 1mΩ. Each controller in the sharing
group is assigned the same droop value. The droop value
represents the output loadline. If phases are added or dropped
the rail loadline remains constant. Droop is configured with the
VOUT_DROOP command, units are in mV’s.
Rail Loadline
0.95
Total Load Current = 27.5A + 35A + 52A = 114.5A
38.16A / Ph
0.90
0.85
1.05
0.80
1.00
0.75
0.95
27.5A
0.90
0.85
0.80
35A
Ref
52A
Mem_1
Mem_2
Programmed Loadline = 1 mOhm/Ph.
Actual Loadlines = ;
Master = 1.0 mOhm
Slave_1 = 1.5 mOhm
Slave_2 = 2.0 mOhm
0.75
0.70
0.65
0.60
0.55
5
10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90 95 100 105 110 115 Iout
FIGURE 2. UNBALANCED PHASE CURRENTS DUE TO SLOPE ERROR
The imbalance results in each phase contributing an unequal
portion of the load current. Each controller will respond to the
imbalance with its local hardware droop function and the output
voltage will trim down proportionally to constrain the phase
current.
After the rail has reached the configured target voltage the DDC
Bus will begin to dynamically equalize the phase currents. The
Reference Phase controller with the lowest PMBus address
periodically broadcasts its current. Each Member Phase(s)
reference voltage is trimmed up or down until all devices in the
group carry an equal portion of the load current. The current
sharing algorithm uses the PMBus Trim command so the Trim
command must not be configured by the designer when using
current sharing. This effect is shown in Figure 3. Notice in this case
the Reference-Phase initially sourced the majority of the load
current. Each Member Controller’s reference voltage was trimmed
in the positive direction until all phase’s are sourcing equal
current to the load.
2
0.70
Each phase carries 38.16A
Group Loadline is equal to configured
loadline = 1 mOhm
0.65
0.60
0.55
5
10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90 95 100 105 110 115 Iout
FIGURE 4. CURRENT SHARING PHASE BALANCE IS ACHIEVED
Phase Add/Drop
When Zilker Labs Digital-DC power conversion devices are
configured in a current sharing group, individual group members
are capable of (dynamically) dropping and adding back to the
group. Group members are typically dropped or added to improve
efficiency or to process a fault.
Group members can be added or dropped on the fly by using a
separate power management host controller invoking the Phase
Control command, actively driving the Phase Enable pin PH_EN,
or by using the GUI. Adding and dropping phases may cause a
slight output voltage perturbation.
If a phase was dropped due to a fault, the standing phase(s)
continue to operate. They will autonomously redistribute their
phase relationship and maintain the configured load line. This
family of controllers don’t provide a protocol to fault the entire
sharing group. Each controller must detect the fault and then
respond as configured.
AN1779.1
December 23, 2013
Application Note 1779
Dropped Phase/SYNC CLOCK
Vpull-up
If the dropped group member was supplying the SYNC clock, it
will continue to do so even though it has become inactive. If the
device supplying the SYNC clock dropped from the group and is
no longer capable of supplying the clock, the remaining
members will detect the absence of SYNC and respond according
to their fault spreading configuration. If a host or power system
manager is monitoring the group, then SALRT will assert, and the
PMBus can be read and will respond with the appropriate fault
management alarm as described in the PMBus™ Power System
Management Protocol Specification – Part II.
ZL6105
0x20
Inactive
DDC
SDA
SCL
DDC
SDA
SCL
ZL6105
0x21
REF.
DDC
SDA
SCL
VCC
PH_3
GL
SEN+
SEN-
FIGURE 6. 3-PHASE CONVERTER AFTER REFERENCE PHASE IS
DROPPED
Phase Add
GL
SEN+
SEN-
VCC
PH_3
GL
SEN+
SEN-
FIGURE 5. 3-PHASE CONVERTER SHOWING REFERENCE, MEMBER,
AND POSITION NUMBER
Figure 5 shows an example of a functional 3-phase current
sharing group prior to asserting a Phase Control command to
drop the Reference Phase (0x20).
Figure 6 illustrates the new 2-phase configuration after the
reference phase (0x20) is dropped. Address 0x21 is now the new
designated reference. Address 0x20 continues supplying the
SYNC clock even though it has been dropped.
The timing diagram is shown in Figure 7. After the reference
phase is dropped the remaining two phases are redistributed and
the phase displacement changes from 120° to 180°.
3
The phase that was previously dropped may be added back into
the group as determined by the power management host or the
Phase Control command. When the command is given to add the
phase, the event is coordinated with the active member devices
over the DDC Bus, and the previously inactive device is
seamlessly added back into the group. In this example, position 1
was made active and resumed the role of reference device, see
Figure 5. The phase offset of each member was automatically
redistributed from 180° to 120° as shown in the top section of
Figure 7.
SYNC
CLK
REF
PH_1
0x20
MEM_1
PH_2
0x21
0x22
PH_2
0x21
VCC
GH
SW
SY NC
IN
Cout Rout
SEN+
SEN-
ZL6105
0x22
MEM_2
DDC
SDA
SCL
DDC
SDA
SCL
SYNC
IN
GH
SW
SY NC
IN
ZL6105
0x22
MEM_1
GL
ZL6105
0x21
MEM_1
DDC
SDA
SCL
SEN+
SEN-
MEM_2
PH_3
o
o
0
REF
PH_1
MEM_1
PH_2
0x22
o
0
o
120
240
0x22
o
360
o
o
480
600
o
720
o
o
840
960
0x21
0x22
SY NC
OUT
GL
SYNC
IN
0x20
DDC
SDA
SCL
PH_2
GH
SW
PH_1
GH
SW
VCC
GH
SW
0x21
DDC
SDA
SCL
SEN+
SEN-
VCC
REF.
Cout Rout
GL
SYNC
OUT
The phase position is defined by the angular offset relative to the
rising edge of the SYNC clock and will autonomously redistribute
based on the number of standing phases.
ZL6105
0x20
PH_1
GH
SW
If the dropped phase was the group reference, a new reference
will be reassigned based on the lowest SMBus address of the
remaining operational members. However, if the dropped
reference was supplying the SYNC clock it will continue to do so.
Vpull-up
VCC
o
180
o
360
o
540
o
720
o
900
FIGURE 7. 3-PHASE CONVERTER TIMING DIAGRAM BEFORE AND
AFTER PHASE_1 (REFERENCE PHASE) IS DROPPED
AN1779.1
December 23, 2013
Application Note 1779
NLR Threshold Scaling
Vpull-up
When multiple devices are configured in a current sharing group,
the effective output ripple is divided by the number of active
members. When all members of the group are operating, the
NLR (Non Linear Response) thresholds can be set to a small
value just above the minimum ripple amplitude. When a group
member is dropped, the ripple amplitude will increase.
Nall
Nactive
PH_1
GH
SW
DDC
SDA
SCL
DDC
SDA
SCL
SYNC
OUT
SEN+
SEN-
SYNC
VCC
PH_2
GH
SW
DDC
SDA
SCL
SYNC
IN
Where:
GL
SEN+
SEN-
ZL6105
0x22
MEM_2
Vt_part is the NLR inner threshold setting used with some group
members deactivated
VCC
PH_3
GH
SW
Vt_all is the NLR inner threshold setting configured for the group
with all members operating
DDC
SDA
SCL
Nall is the total number of members in the group
SYNC
IN
Nactive is the number of members active in the group (that is,
the number of members not faulted or intentionally deactivated)
Rail_1
GL
SEN+
SEN-
ZL6105
0x23
Rail_2
Nall and Nactive are determined automatically from the group
configuration parameters. No additional programming or
configuration is required.
Cout Rout
GL
ZL6105
0x21
MEM_1
(EQ. 1)
Since the available thresholds are quantized to multiples of 0.5%
of the configured output voltage, the next higher available
threshold is used if the result of the above formula is fractional.
For additional information about NLR, please reference AN2032
“NLR Configuration DDC Products”.
VCC
REF.
In order to avoid spurious NLR activity, the Digital-DC features
automatically adjust the NLR thresholds according to the ratio of
active group members to total members of the group
(see Equation 1).
Vt _ part = Vt _ all *
ZL6105
0x20
VCC
Cout Rout
GH
SW
DDC
SDA
SCL
SYNC
IN
GL
Rail_2
SEN+
SEN-
FIGURE 8. EXAMPLE OF SHARING GROUP AND AUXILIARY OUTPUT
RAIL WITH A COMMON SYNC CLOCK
Phase Offset
SYNC Clock
To configure a current sharing group, a common SYNC clock
must be provided to each group member. This SYNC clock can be
provided by any Zilker Labs Digital DC device, or the SYNC can be
provided by an external source that satisfies the electrical
specifications of the SYNC pin. Note: the switching frequency of
each ZL Controller must be configured to the same value.
Once the SYNC source has been designated, the SYNC pins of all
group members and any other Zilker Labs device requiring
synchronization and interleaving must be connected together as
shown in Figure 8. Note that any of the devices whose SYNC pins
are physically connected together can be configured to output
the SYNC clock. The SYNC output can be configured as push-pull
or open-drain. All other devices connected to the SYNC source
must be configured as SYNC inputs. If the SYNC source becomes
disabled while the current sharing rail is enabled, each sharing
device will reconfigure to use its internal clock. During the
transition small output voltage perturbations might occur. SALRT
will assert and the loss of SYNC status register will set. If the
output voltage perturbation does not cause a UV fault the current
sharing rail will continue to operate. The loss of intra-controller
synchronization will cause a small modulated envelope.
4
The current sharing group in Figure 8 will autonomously
distribute each member’s phase with respect to the SYNC clock.
Since the sharing group contains 3 members, each member will
be ideally offset in phase by 120°. The actual phase offset is
represented by a 4 bit binary number resulting in 16 possible
offset values in 22.5° steps. The real phase displacement will be
rounded to the closest 22.5° increment. All possible phase
displacements are shown in Figure 9.
For the 3-phase example shown in Figure 8. the actual sharing
group phase offset will be rounded as shown in Table 3.
TABLE 3. IDEAL vs ACTUAL PHASE OFFSET
PHASE POSITION
IDEAL OFFSET
ACTUAL OFFSET
1
0°
0°
2
120°
112.5°
3
240°
247.5°
AN1779.1
December 23, 2013
Application Note 1779
Although Rail_2 is connected to the same SYNC clock, it will not
be autonomously offset in phase with respect to the current
sharing group. Rail_2 will assume an offset of 67.5 degrees from
the rising edge of the sync clock based on the configured PMBus
address 0x23. Rail_2 can be offset in phase to one of the 16
possible offset values by using the INTERLEAVE command.
Vpull-up
ZL6105
0x20
VCC
Sharing Group_1
PH_1
GH
SW
DDC
SDA
SCL
DDC
SDA
SCL
SY NC
OUT
SEN+
SEN-
VCC
PH_2
GH
SW
SY NC
IN
GL
SEN+
SEN-
ZL6105
0x22
VCC
Sharing Group_2
PH_1
GH
SW
DDC
SDA
SCL
SY NC
IN
After the ISHARE_CONFIG command is configured, each sharing
group will autonomously phase spread within the group, but not
between the 2 groups. The resulting timing waveform is shown in
Figure 11.
SY NC
IN
Rail_2
VCC
PH_2
GH
SW
Current sharing groups are autonomously offset in phase with
respect to each group member, however, when there are multiple
sharing groups connected to the same SYNC clock the 2 groups
will not autonomously offset from each other. Consider the 2
current sharing groups shown in Figure 10. This configuration
consists of 2 output rails with each rail containing a 2-phase
sharing group and a common SYNC clock.
Cout
SEN+
SEN-
FIGURE 9. PHASE OFFSET RESOLUTION WHEEL
DDC
SDA
SCL
Rout
GL
ZL6105
0x23
INTERLEAVE Command
Cout
GL
ZL6105
0x21
DDC
SDA
SCL
Rout
GL
SEN+
SEN-
FIGURE 10. EXAMPLE OF 2x2-PHASE CURRENT SHARING GROUPS
USING THE SAME SYNC CLOCK
SYNC
CLK
0x20
Rail_1
0x21
Rail_1
0x22
Rail_2
0x23
Rail_2
o
0
o
90
o
180
o
270
o
360
o
450
o
540
o
630
o
720
o
810
o
900
o
990
FIGURE 11. TIMING DIAGRAM FOR A 2 RAILx2-PHASE CURRENT
SHARING EXAMPLE
5
AN1779.1
December 23, 2013
Application Note 1779
Ramp Synchronization
Notice that the positional phase equivalents in each sharing
group are not offset from each other.
If desired, Sharing Group_2 can be offset in phase from Group_1
by using the INTERLEAVE command field in the GUI or creating
an equivalent interleave command line in a configuration file.
The simplest way to achieve equal phase offset for the 4 devices
in Figure 10 is to offset Sharing Group_2 by 90°. This is easily
done in the GUI by declaring 2 Devices in Sharing Group_2 and
assigning the Position in Interleave Group as 4. The INTERLEAVE
command would be placed in each config file for Sharing
Group_2 with a value of 0x0024.
During turn-on and turn-off, the voltage ramps of each phase are
synchronized to start at the same time. This ensures that
inter-phase circulating currents are minimized.
Each current sharing device contains a separate digital controller
that executes firmware. The individual controller firmware
requires synchronization prior to ramp events to ensure that
intra-phase circulating currents are minimized.
This is accomplished by forcing the reference phase to wait at
least two additional firmware cycles during ramping events by
configuring it to have additional Time On and Time Off Delay
relative to the other group members.
When the sharing group receives a hardware or PMBus enable,
the member devices initialize their registers and freeze the state
of their firmware, once the reference phase completes its extra
timing delay it transmits a DDC Ramp Flag and all members of
the group produce a sequenced PWM and begin their soft-start
routine.
SYNC
CLK
PH_1
FIGURE 12. INTERLEAVE CONFIGURATION TO OFFSET SHARING
GROUP_2 BY 90°
PH_2
Referencing Figure 9, the value 4 represents an offset of 90°.
The same entries are made for both devices in Sharing
Group_2’s configuration files.
PH_3
o
0
The interleave value for Sharing Group_1 is simply
INTERLEAVE = 0000, so the INTERLEAVE command is not used in
the configuration files for Sharing Group_1. The Interleave
function for Sharing Group 1 is handled by the ISHARE_CONFIG
command.
The timing diagram shown in Figure 13 illustrates that each
Phase in Sharing Group_2 is now equally offset from Sharing
Group_1.
o
120
o
240
o
360
o
480
o
600
o
720
o
840
o
960
FIGURE 14. START-UP SYNCHRONIZATION
Ensure that the Time On Delay and Time Off Delay parameters
for the reference phase are at least 10ms greater than the delay
parameters of each member device as shown in Figure 15.
Alternate Ramp Control
Alternate Ramp Control is not supported.
SYNC
CLK
0x20
Rail_1
0x21
Rail_1
0x22
Rail_2
0x23
Rail_2
o
0
o
90
o
180
o
270
o
360
o
450
o
540
o
630
o
720
o
810
o
900
o
990
FIGURE 13. 2x2-PHASE CURRENT SHARING GROUPS NOW EQUALLY
OFFSET USING INTERLEAVE COMMAND
6
AN1779.1
December 23, 2013
Application Note 1779
FIGURE 15. SETTING THE REFERENCE TIME ON/OFF DELAYS 10ms GREATER THAN MEMBER DELAYS
Minimum Duty Cycle
Current sharing groups can be comprised of 2 to 7 phases
(controllers). Each phase contains its own digital PID controller.
The Minimum Duty Cycle parameter is required when configuring
current sharing, enabling a minimum duty cycle ensures that
each controller produces an identical initial pulse which helps
balance intra-phase currents during ramps. Configure the
minimum duty cycle to be slightly above the value specified in
the driver data sheet.
.
TABLE 4. BROADCAST MARGIN/ENABLE SETUP
ZL Controller Address
Rail #
Assigned
Broadcast Group
ON_OFF_CONFIG
MISC_CONFIG
Broadcast Margin/Enable
0x20
0x21
0x22
0x24
0x25
0x26
1
2
3
4
4
4
2
2
2
2
2
2
PMBus Enable
PMBus Enable
PMBus Enable
PMBus Enable
PMBus Enable
PMBus Enable
Enable
Enable
Enable
Enable
Enable
Enable
The Min Duty Cycle command is located in the USER_CONFIG
field on the PMBus Advanced section of the GUI. The ZL8101
contains extra Minimum Duty Cycle options to enable the use of
DrMos devices. Reference the ZL8101 data sheet for additional
information.
Broadcast Enable/Margin
Broadcast Margin/Enable allows all controllers in a pre-defined
group to respond to a single PMBus margin or enable command.
The commands can be sent to any SMBus address in the group
and all group members will respond relative to their
configuration.
PMBus enable and margining commands can be configured with
current sharing groups just like single phase converters. The
broadcast group can be comprised of current sharing and Single
Phase devices. An example is shown in Figure 17.
This configuration contains 3 Single Phase converters (Rails_1-3)
and a 3-phase current sharing group (Rail_4). Table 4 shows the
DDC_CONFIG and ON_OFF_CONFIG requirements to Enable
Broadcast PMBus commands.
To configure a broadcast group, assign each group member the
same Broadcast Group Number. The Broadcast Group Number is
Part of the DDC_CONFIG command. The ON_OFF_CONFIG
parameter has to be set to PMBus Enable.
7
FIGURE 16. SETTING BROADCAST ENABLE AND MARGIN IN THE
MISC_CONFIG FIELD
Broadcast Checklist
1. ON_OFF_CONFIG set to PMBus Enable
2. MISC_CONFIG enable broadcast
3. DDC_CONFIG assign Broadcast Group number
After the broadcast group is configured, every member in the
group will respond to a PMBus margin or enable command.
AN1779.1
December 23, 2013
Application Note 1779
Vpull-up
ZL6105
0x20
VCC
REF.
Rail DDC ID = 0
Broadcast Group = 2
Rail_1
GH
SW
DDC
SDA
SCL
DDC
SDA
SCL
SYNC
SY NC
OUT
VCC
Rail DDC ID = 1
Broadcast Group = 2
Rail_2
GH
SW
DDC
SDA
SCL
SY NC
IN
SEN+
SEN-
VCC
Rail DDC ID = 2
Broadcast Group = 2
GH
SW
DDC
SDA
SCL
SY NC
IN
Rail_3
GL
SEN+
SEN-
SEN+
SEN-
VCC
PH_2
GH
SW
SY NC
IN
GL
SEN+
SEN-
ZL6105
0x26
MEM_3
GH
SW
DDC
SDA
SCL
SY NC
IN
Rail DDC ID = 5
Broadcast Group = 2
PH_1
Rail_4
Rail_4
GL
ZL6105
0x25
MEM_2
DDC
SDA
SCL
GL
ZL6105
0x22
MEM_2
GH
SW
SY NC
IN
SEN+
SEN-
VCC
REF.
DDC
SDA
SCL
GL
ZL6105
0x21
MEM_1
ZL6105
0x24
VCC
PH_3
GL
SEN+
SEN-
FIGURE 17. 4-RAIL POWER SUPPLY WITH PMBUS BROADCAST MARGIN AND ENABLE
Configuring Current Sharing
Consider the 3-phase current sharing group shown in Figure 18.
Ensure that each Zilker Labs device in the group is connected to
the same DDC and SMBus. The device with the lowest SMBus
address is the designated Reference Phase. The Reference
phase is used to provide the load current information to each
member device by periodically broadcasting its load current over
the DDC Bus. Each member device will trim its reference up or
down until the member currents equal the reference current. If
the Reference Device is dropped or faults the device with the
next lowest PMBus address becomes the new Reference Device.
Rail DDC ID#/ISHARE Rail ID
The Rail DDC ID# is automatically assigned by each controllers
firmware and cannot be changed. The Rail DDC ID# is used to
configure Fault Spreading and Sequencing for single phase rails.
The ISHARE Rail ID is used to configure Fault Spreading and
Sequencing for current sharing groups.
The Rail DDC ID is set by the 5 LSB’s of the SMBus address.
Table 16 (Appendix) maps the Rail DDC ID with the SMBus
address. Care must be taken to ensure that duplicate Rail DDC
ID’s are not created by choosing SMBus address’s whose 5 LSB’s
are identical.
8
The Rail DDC ID# is not used for current sharing, the ISHARE Rail
ID number is used instead, however, versions of the GUI lower
than version 4.0 will automatically copy the Rail DDC ID# into the
ISHARE Rail ID dialog box, this results in each current sharing
controller with a unique ISHARE Rail ID. In order for current
sharing to function the ISHARE Rail ID must be the same value
for each controller in the sharing group. The ISHARE Rail ID tells
the member devices to listen and respond to the load current and
DDC events emanating from the reference controller.
The ISHARE Rail ID is part of the ISHARE_CONFIG command.
Damage to the controller may result if the current sharing rail is
enabled without a common ISHARE Rail ID. The ISHARE_CONFIG
command is outlined in Table 2 on page 1.
DDC_CONFIG
The DDC config Field is not used as part of the current sharing
algorithm. However, if the current sharing group is part of a
broadcast group the Broadcast Group number is assigned in the
DDC_CONFIG command.
Table 5 on page 9 shows the format of the DDC_CONFIG
command, The Rail DDC ID# field is used to identify the ZL
Controller for single phase sequencing and fault spreading. The
Rail DDC ID # is described on Page 1 and Table 16 on page 23
AN1779.1
December 23, 2013
Application Note 1779
TABLE 5.
TABLE 6. ISHARE_CONFIG COMMAND CONFIGURATION FOR
3-PHASE CURRENT SHARE EXAMPLE
DDC_CONFIG
Bits
Purpose
Value
Description
15:13
Reserved
0
12:8
Broadcast Group
0 to 31
7:6
Reserved
0
Reserved
5
DDC TX Inhibit
1
DDC Tranmisson Inhibited
0
DDC Transmission Enabled
4:0
Rail DDC ID#
Vpull-up
0 to 31
ZL6105
0x20
VCC
REF.
DDC
SDA
SCL
GH
SW
DDC
SDA
SCL
SYNC
IN
Number of
Devices
Device Position
0x20
0x21
0x22
5
5
5
3
3
3
1
2
3
Phase
Displacem
ent Degrees
0
120
240
Current
Share Control
ISHARE_CONFIG
Hex
Enabled
Enabled
Enabled
0x541
0x545
0x549
USER_CONFIG
The following parameters related to current sharing is located in
the USER_CONFIG field and must be set to properly configure
current sharing.
Min Duty Cycle
The minimum allowable duty cycle must be set to Enable, to
ensure that each phase starts the turn-on ramp with the same
pulse width, without missing pulses. The Min Duty Cycle function
is equal to:
(EQ. 2)
VCC
PH_2
TSW = Switching Frequency Period
TABLE 7.
GL
MIN DUTY CYCLE N OPTIONS
SEN+
SEN-
VCC
PH_3
GH
SW
SYNC
IN
ISHARE Rail ID = 5
Broadcast Group = 2
PH_1
Rail_1
ISHARE
Rail
ID
TSW
inDutyCycle = N × -----------256
ZL6105
0x22
MEM_3
DDC
SDA
SCL
DDC ID
SEN+
SEN-
GH
SW
SYNC
IN
Group number
GL
ZL6105
0x21
MEM_2
DDC
SDA
SCL
Reserved
SMBus
Address
GL
SEN+
SEN-
FIGURE 18. 3-PHASE CURRENT SHARING EXAMPLE
ISHARE_CONFIG
The ISHARE_CONFIG field contains 4 fields:
1. ISHARE Rail ID
Assigns the Rail Number for the Current Sharing Group.
Must be the same for every controller in a current sharing
group. The IShare Rail ID must be configured manually in the
configuration file for each sharing group member. Pin-strap
current sharing is not supported. The IShare Rail ID is also
used to configure Fault Spreading and Sequencing for current
sharing groups.
2. Number of Devices
number of devices or phases in current sharing group, this
entry is used to calculate phase offset relative to the rising
edge of the SYNC Clock.
3. Device Position
This entry is used to calculate phase offset relative to the
rising edge of the SYNC Clock.
4. Current Share Control
Enables current sharing, for this example the specific entries
for each address is shown in Table 6.
9
DEVICE
N
ZL6105
1-4
ZL8101
0, 2, 4, 6, 8, 10, 12, 14
The Min Duty Cycle function is also used to ensure that PWM
pulses below the minimum are not presented to an external
driver or DrMos device. The Minimum Duty Cycle value should be
set equal to or slightly above the driver requirement.
SYNC Time-out Enable
The SYNC Time-out Enable function is used to configure the state
of the SYNC output when the controller is disabled. If the
controller is supplying the SYNC signal in a current sharing group,
SYNC Time-out must be set to SYNC always On. This will ensure
that the SYNC source is ready prior to rail enable. Always on also
ensures that if the SYNC source is dropped from the current
sharing group that the SYNC clock will remain present to the
standing group members.
The Reference Controller is typically used to provide the SYNC
Clock. However any device internal or external to the sharing
group can provide the SYNC Clock.
SYNC Input Mode/SYNC Pin Configuration
The SYNC Input Mode is used along with the SYNC Pin Configure
parameter to specify whether the device will output the SYNC
clock or use the SYNC clock as an input.
SYNC Clock Source Mode (device is outputting Sync): Set SYNC
Input Mode to Pinstrap Input and set SYNC Pin Configure to
Output Int. Signal. The controller will now operate as a clock
source.
AN1779.1
December 23, 2013
Application Note 1779
SYNC Clock Input Mode (device is using an external Sync):
Configure SYNC Input Mode to External Sync now the controller
will use the SYNC signal present on its Sync Pin.
Configure the SYNC Output Mode command in the MFR_CONFIG
field to be Push-Pull or Open Drain to satisfy your system design
requirements. Reference the device data sheet for additional
information.
Standby Mode
Standby Mode is used to select whether the controller is in Low
Power mode or Monitor Mode. Low Power Mode is not available
with current sharing groups. All current sharing controllers must
me configured as monitor mode.
Standby mode must be set to Monitor Enabled for both
Reference and Member Devices. Setting this parameter to
monitor mode ensures that the firmware is initialized prior to
enabling the output rail.
The other entries in the USER_CONFIG field do not affect current
sharing groups, and should be configured to meet the designer’s
system requirements. For additional information about these
parameters please reference.
Lowside FET Mode
The Lowside FET Mode is used to configure the state of the
lowside FET when the Rail or controller is disabled. The default
mode is Off when Disabled. This means that the lowside gate is
held low (FET off) when the controller is disabled. The FET on
mode is used to mimic an active crowbar during an over-voltage
condition, or to discharge a pre-bias leakage.
The USER_CONFIG GUI entries for this example are shown in
Figure 19, illustrating the configuration for the Reference device.
Figure 20 illustrates the configuration for Member device(s).
FIGURE 20. USER_CONFIG FIELD (MEMBER)
MFR_CONFIG
The following parameters related to current sharing is located in
the MFR_CONFIG field and must be set to properly configure
current sharing.
I Sense Delay
The I Sense Delay parameter is used to configure the time that
current samples are ignored after FET switch transitions. The
delay parameter is configured to be greater than the worst case
switch node ring out time. Ensure that the same blanking value is
used for the Reference and Member device(s).
I Sense Control
I Sense Control is used to configure the current sensing method.
Various modes of current sensing are available depending on
duty cycle and switching frequency. Current sensing options are
shown below in Table 8. A lumped or distributed resistor can be
substituted for rDS(ON) and DCR sensing. Ensure that the same
I Sense Control is used for the Reference and Member device(s).
TABLE 8. CURRENT SENSING METHOD SELECTION
CURRENT SENSE CONTROL
USAGE
Ground referenced, down-slope
(rDS(ON))
Low duty cycle and low FSW
Not supported on the ZL8101
VOUT referenced, down-slope
(Inductor DCR Sensing)
Low duty cycle and high FSW
VOUT referenced, up-slope (Inductor
DCR sensing)
High duty cycle
FIGURE 19. USER_CONFIG FIELD (REFERENCE)
Reference AN2026 “PowerNavigator™ Users Manual” and
AN2033 “Zilker Labs PMBus Command Set for DDC Products” for
additional information.
10
AN1779.1
December 23, 2013
Application Note 1779
NLR During Ramp
TABLE 9. TEMPO_CONFIG
Determines if NLR is active during ramps or waits until
Power-Good is asserted. This should always be set to Wait for PG
for both Reference and Member device(s) when configuring
current sharing groups.
FIELD
PURPOSE
VALUE
7
Selects the
temperature
sensor source for
tempco
correction
0
Selects the internal
temperature sensor
1
Selects the XTEMP pin
for temperature
measurements
Sets Tempco
correction in
units of
100ppm/°C
TC
RSEN(EXT)
Alternate Ramp Control
Set to disable for Reference and Member device(s). Alternate
Ramp control is not supported for the controllers referenced in
this document.
6:0
SYNC Output Mode
DESCRIPTION
RSEN(INT)
Configures the SYNC pin as Open Drain or Push-Pull. SYNC
Output Mode is typically set to Push-Pull for the SYNC clock
source and Open Drain for devices that receive the SYNC clock as
an input.
Equation 3 can be used to fine tune the temperature correction
for internal and external sense elements.
The MFR_CONFIG GUI entries are shown below. The comments
refer to current sharing groups. Reference AN2026
“PowerNavigator™ Users Manual” for additional information.
RSEN ( INT ) = IOUT _ CAL _ OFFSET × (1 + TC × 10 −4 × (T − 25))
RSEN ( EXT ) = IOUT _ CAL _ GAIN × (1 + TC × 10 −4 × (T − 25))
(EQ. 3)
Where:
IOUT_CAL_GAIN = the impedance of the current sense element
at +25°C
IOUT_CAL_OFFSET = offset added to IOUT readings, this offset is
used to compensate for current measurement error due to
blanking.
RSEN(EXT) = DCR inductor resistance
RSEN(INT) = Internal silicon temp diode
rDS(ON) = Low-side FET channel resistance
T = Temperature measured by sensing device
TC = Temperature correction factor
The hex values in Table 10 can be used to accurately compensate
most designs if the measurement element is tightly (thermally)
coupled to the sense element.
TABLE 10. TYPICAL TEMPCO_CONFIG VALUES BY ZL PART NUMBER
FIGURE 21. MFR_CONFIG FIELD
TEMPCO_CONFIG
The TEMPCO_CONFIG command is used to configure the
temperature correction factor and temperature measurement
source (internal or external) when performing temperature
coefficient correction for the current sensing element.
TEMPCO_CONFIG values are applied as a negative correction to a
positive temperature coefficient. The TEMPCO_CONFIG
command is defined in Table 9. The TEMPCO_CONFIG parameter
must be configured to the same value for the Reference and
Member(s).
ZL DEVICE
EXTERNAL TEMP
DIODE
INTERNAL SILICON
DIODE
ZL6105
A8
2C
ZL8101
A8
2C
AUTOCOMP_CONFIG
The ZL6105 and ZL8101 have an auto compensation feature
that measures the characteristics of the power train and
calculates the proper compensator PID coefficients. Auto
compensation is configured using the FC0 and FC1 pins, GUI, or
config files, reference the specific product data sheets for
additional information.
When configuring current sharing groups to use autocomp, every
device in the sharing group must have the same
AUTOCOMP_CONFIG value.
11
AN1779.1
December 23, 2013
Application Note 1779
When the Auto Compensation algorithm is enabled, the
configured soft-start values (Rise/Fall times) are used to
calculate the loop gain that's used during the turn-on/turn-off
ramps to ensure current sharing while ramping. If the rise/fall
time is set too large the gain term cannot be optimized to ensure
current balance during ramping. To ensure current balance
constrain current sharing groups to rise/fall times between 5ms
and 20ms.
While ramping, the loop bandwidth is intentionally set to a very
low value so transient compliance will be very poor. The designer
should limit dynamic loading while ramping. Even if autocomp is
disabled and the sharing group employs a user defined
compensator, transient response will be poor during ramps.
Once the ramp has completed, the autocomp algorithm will
begin and a new optimized compensator solution will be found
and the compensator solution will transmit over the DDC Bus
such that each controller has the same PID compensator values.
If Autocomp is disabled the controllers will switch to the
configured compensator by using the PID Taps defined in the
configuration files.
If Auto Comp is enabled, VIN must be stable before the autocomp
algorithm begins, as shown in Equation 4.
ΔVin
100%
-------------------- % ≤ --------------------------------------Vin NOM
256 × Vout
1 + ----------------------------Vin NOM
(EQ. 4)
AUTO_COMP_CONFIG
The AUTO_COMP_CONFIG command is used to configure auto
compensation.
AUTO COMP ENABLE
Used to enable/disable autocomp and determine how often the
rail runs the autocomp algorithm. The choices are:
before the ramp is finished. If PG Assert is set to “IMM After AC”,
PG will be asserted immediately after the first Auto Comp cycle
completes and the configured POWER_GOOD_DELAY parameter
will be ignored. Since the Autocomp algorithm typically takes
between 50ms and 200ms to complete the option “IMM After AC”
is suggested.
AUTO COMP GAIN
The Auto Comp Gain control scales the Auto Comp results to
allow a trade-off between transient response and steady-state
duty cycle jitter. A setting of 100% will provide the fastest
transient response while a setting of 10% will produce the lowest
jitter. The optimal gain value will need to be determined
empirically based on the system requirements.
PMBus Basic Commands
VOUT_COMMAND
Set each current sharing phase to the same output voltage value.
The VOUT_COMMAND can be stated in each configuration file, or
VOUT_COMMAND can be defined by pinstrap. If using pinstraps
to configure the current sharing rail voltage, don’t use the
VOUT_COMMAND statement in the configuration files.
VOUT_TRIM
Typically set to 0 (default value) for each current sharing phase.
The reference phase will always retain a zero value. Member
phases will adjust the trim value until all phases carry equal load
current. If an offset voltage is desirable to overcome the effects
of droop use the VOUT_CAL_OFFSET command to add an offset.
See “(VOUT_CAL_OFFSET)”. The VOUT_TRIM command is not
available when current sharing.
VOUT_CAL_OFFSET
• Autocomp once, will run autocomp algorithm each time the
rail is enabled
The VOUT_CAL_OFFSET command is used to apply an offset
voltage that can compensate for the load-line droop. While
positive and negative offset values are valid, a positive offset
value is typically used with a magnitude of Equation 5.
• Autocomp every second will initiate a new autocomp algorithm
each 1 second
VOUT _ CAL _ OFFSET = 0.5 × I MAX × RDROOP
• Autocomp every minute will initiate a new autocomp algorithm
every minute.
If the VOUT_CAL_OFFSET command is used, ensure that each
group member is assigned the same VOUT_CAL_OFFSET value.
It is recommended that current sharing groups use only the
Autocomp Once option.
VOUT_DROOP
AUTO COMP STORE
controls whether or not the autocomp result is stored in ram. If
autocomp store is enabled, the autocomp result found on the
first ramp will be used on all subsequent ramps, as long as input
power to the controller is present. If input power is cycled, the
result will be lost. Autocomp Store disabled will run a new
autocomp algorithm the first time the rail is enabled.
POWER-GOOD ASSERT
If the PG Assert parameter is set to “Use PG Delay”, PG will be
asserted according to the POWER_GOOD_DELAY command,
after which Auto Comp will begin. When Auto Comp is enabled,
the user must not program a Power-Good Delay that will expire
12
(EQ. 5)
Droop resistance is used as part of the current sharing algorithm.
The recommended droop or loadline resistance for current
sharing groups is between 0.15mΩ and 1.0mΩ. Each group
member is assigned the same droop value.
MAX_DUTY
The maximum duty cycle must be constrained as the switching
frequency increases. Configure the MAX_DUTY cycle to a
maximum value for each group member per Equation 6, round
the result down to the closest integer value. Table 11 lists
MAX_DUTY values for a few common switching frequencies.
δ max(%) = [1 − (150ns × Fsw)] ×100
(EQ. 6)
AN1779.1
December 23, 2013
Application Note 1779
TABLE 11. MAX_DUTY VALUES FOR COMMON SWITCHING FREQUENCIES
FSW
(kHz)
MAX DUTY
(%)
200
97
400
94
600
91
800
88
1000
85
1400
80
FIGURE 22. RECOMMENDED DEADTIME CONFIGURATION
TON_DELAY, TOFF_DELAY
Voltage Tracking
Time On Delay and Time Off Delay parameters for the reference
phase must be set at least 10ms greater than the delay
parameters of each member device, reference Figure 15.
The ZL8101 integrates a lossless tracking scheme that allows its
output to track a voltage that is applied to the VTRK pin with no
extra components required. The VTRK pin is an analog input that,
when tracking mode is enabled, configures the voltage applied to
the VTRK pin to act as a reference for the member device’s
output regulation.
The ZL6105 and ZL8101 offer two modes of tracking: coincident
and ratiometric. Figures 23 and 24 illustrate the output voltages
for the two tracking modes.
1. Coincident. This mode configures the controller to ramp its
output voltage at the same rate as the voltage applied to the
VTRK pin. Two options are available for this mode;
- Track at 100% VOUT limited. Member rail tracks the
reference rail and stops when the member reaches its
configured target voltage. Figure 23A and 23B.
- Track at 100% VTRK limited. Member rail tracks the
reference at the instantaneous voltage value applied to the
VTRK pin. Figure 23C.
To configure the deadtimes for current sharing use the
DEADTIME_CONFIG command. The DEADTIME _CONFIG
command structure is shown Table 12.
TABLE 12.
DEADTIME_CONFIG
BITS
15
PURPOSE
VALUE
Sets high to low deadtime
mode
DESCRIPTION
0
Adaptive H-to-L control
1
Freeze H-to-L deadtime
14:8 Sets H-to-L deadtime
H
H X 2ns (signed)
7
Sets L-to-H deadtime
mode
0
Adaptive L-to-H control
1
Freeze L-to-H deadtime
6:0
Sets H-to-L deadtime
L
H X 2ns (signed)
Coincident Tracking
Track @ 100% Vout Limited
Vref > Vmem VRef
Ton Dly
0
Vmem
Toff Dly
Vref=1.5V
Vmem=0.75V
EN
A.
Track @ 100% Vout Limited
Vref = Vmem VRef
Vmem
Toff Dly
Ton Dly
0
There are 2 other commands associated with deadtimes,
DEADTIME_MAX and DEADTIME. When the deadtimes are set to
Freeze mode these commands are not needed, simply omit them
from the configuration file.
~~
When current sharing several other algorithms are also running
I.E. local droop, rail droop, voltage regulation, and current
balance algorithms. In order to avoid the possibility of these
algorithms interacting with each other, the adaptive deadtime
algorithm must be disabled while current sharing, set deadtimes
to Freeze and then configure fixed deadtimes to optimize the
selected drive train.
Voltage tracking for current sharing groups is the same for single
rail designs with the exception that a configuration file or PMBus
operation is required. Pin-strapped current share tracking is not
supported.
~
The ZL6105 and ZL8101 controllers utilize a closed loop
algorithm to optimize the dead-time applied between the gate
drive signals for the top and bottom FETs. When enabled the
algorithm continuously adjusts the deadtimes until the duty cycle
reaches a minimum.
Vref=1.5V
Vmem=1.5V
EN
B.
Track @ 100% Vtrk Limited
Vref = Vmem VRef
Ton Dly
0
~
ADAPTIVE DEADTIME
Vmem
Toff Dly
Vref=1.5V
Vmem=1.5V
EN
C.
FIGURE 23. COINCIDENT TRACKING
13
AN1779.1
December 23, 2013
Application Note 1779
2. Ratiometric. This mode configures the controller to ramp its
output voltage as a percentage of the voltage applied to the
VTRK pin. The default setting is 50%, but an external resistor
maybe used to configure a different tracking ratio.
- Track at 50% VOUT limited. Member rail tracks the
reference rail and stops when the member reaches 50% of
the reference’s target voltage
- Track at 50% VTRK limited. Member rail tracks the
reference at the instantaneous voltage value applied to the
VTRK pin until the member rail reaches 50% of the
reference rail voltage, or if the member is configured to
less than 50% of the reference the member will achieve its
configured target
Vpull-up
ZL6105
0x20
DDC
SDA
SCL
ENABLE
DDC
SDA
SCL
~~
Ton Dly
DDC
SDA
SCL
Vmem
DDC
SDA
SCL
~~
Ton Dly
0
SY NC
IN
Vmem
Toff Dly
Vref=1.5V
Vmem=0.75V
EN
Cout
SEN+
SEN-
Rail_2
VCC
PH_2
GH
SW
ENABLE
Track @ 50% Vtrk Limited
Vref = 1.5V
VRef
Vmem = 0.75V
Rout
GL
VTRK
EN
A.
Tracking Member
PH_1
GH
SW
ZL6105
0x23
Vref=1.5V
Vmem=0.75V
Rail_1
VCC
VTRK
SY NC
IN
Toff Dly
GL
ZL6105
0x22
Ratiometric Tracking
Cout
SEN+
SEN-
ENABLE
0
Rout
Lout
VOUT_REFERENCE
.
Track @ 50% Vout Limited
Vref = 1.5V
VRef
Vmem = 0.75V
Tracking Reference
GH
SW
ENABLE
SY NC
OUT
VCC
GL
SEN+
SEN-
FIGURE 25. CURRENT SHARING GROUP TRACKING A SINGLE RAIL
Configuring Tracking with Current Sharing
B.
FIGURE 24. RATIOMETRIC TRACKING
Vpull-up
ZL6105
0x20
Tracking with Autocomp
The ZL6105 and ZL8101 uses a unique ramping algorithm that
results in near perfect tracking while ramping. This is
accomplished by deriving different compensator coefficients for
ramping than those used for steady-state operation. The ramp
compensation is derived from the configured rise/fall time, VIN,
and VOUT. While ramping the loop bandwidth is intentionally set
to a very low value so to ensure that inter-phase current balance
is maintained. Since the loop bandwidth is low response to
transients will be limited. The user should limit dynamic loading
while ramping. Once the ramp has completed the autocomp
algorithm will begin and a new optimized compensator solution
will be found. If Autocomp is disabled the controllers will switch
to the configured compensator by using the PID Taps defined in
the configuration files. If Autocomp is enabled the tracking
member Rise/Fall times might need to be adjusted slightly until
the desired tracking accuracy is achieved. For the best possible
tracking accuracy disable autocomp and manually assign PID
coefficients in the configuration file. Even though Autocomp is
disabled current sharing groups will still us a calculated ramping
compensator that ensures current balance.
Current Sharing and Tracking
When the ZL6105 and ZL8101 is configured in a current sharing
group and voltage tracking is desired, the VTRK pin of each
sharing group member must be tied together, and connected to
the reference rails output voltage. Figures 25 and 26 show
tracking connections for current sharing groups. Two current
sharing groups can also be configured to track each other.
14
DDC
SDA
SCL
ENABLE
DDC
SDA
SCL
ENABLE
SY NC
OUT
ENABLE
SY NC
IN
Tracking Reference
Sharing Group
PH_1
GH
SW
Rout
Cout
GL
SEN+
SEN-
ZL6105
0x21
DDC
SDA
SCL
VCC
Rail_1
VCC
PH_2
GH
SW
GL
SEN+
SEN-
VOUT_REFERENCE
ZL6105
0x22
VTRK
DDC
SDA
SCL
ENABLE
SY NC
IN
GH
SW
VCC
Tracking Member
Lout
Rout
Cout
GL
SEN+
SEN-
Rail_2
FIGURE 26. SINGLE RAIL TRACKING A CURRENT SHARING GROUP
In a tracking group, the rail output with highest voltage is defined
as the reference device. The device(s) that track the reference is
called member device(s). The reference device will control the
ramp delay and ramp rate of all tracking devices and is not
placed in the tracking mode. The reference device is configured
to the highest output voltage for the group and all other device(s)
AN1779.1
December 23, 2013
Application Note 1779
output voltages are meant to track and never exceed the
reference device output voltage. The reference device must be
configured to have a minimum Time-On Delay as shown in
Equation 7.
(EQ. 7)
t OnDly ( REF ) ≥ t OnDly ( MEM ) + t OnRise ( REF ) + 5ms
The member device(s) must be configured to have a minimum
Time-Off Delay as shown in Equation 8.
(EQ. 8)
t OffDly ( MEM ) ≥ t OffDly ( REF ) + t OffFall ( REF ) + 5ms
When the Tracking Reference is comprised of a current sharing
group the delay time must me added to the standing current
sharing tOnDly . Using Figure 26 as an example the non-Tracking
timing configuration is shown below in Table 13.
TABLE 13. NON-TRACKING DELAY TIMING FOR FIGURE 26
RAIL #
VOUT tON_DLY tON_RISE tOFF_DLY tOFF_FALL
(v)
(ms)
(ms)
(ms)
(ms)
MODE
Rail_1
1.5
Tracking Reference
5
5
5
5
Tracking
Disabled
Rail_2
0.75
Sharing Reference
Tracking Member
15
5
5
5
Tracking
Disabled
Rail_2
0.75
Sharing Member
Tracking Member
15
5
15
5
Tracking
Disabled
Compensation
The ZL6105 and ZL8101 Digital DC/DC PWM Controllers include
an auto compensation algorithm. The auto compensation
function can be used to find a compensator each time the
current sharing rail is enabled or the algorithm can be used to
find a suitable compensator which can be inserted in each
configuration file.
Autocomp every second and autocomp every minute should not
be selected with current sharing groups.
The Zilker Labs CompZL program can be used to obtain PID taps
that ensure stability and result in moderate to optimal transient
response.
Filter Design
The design of the output filter is based on the system
requirements for ripple, noise, transient response, and
phase-count.
After the filter design is complete, consider any one of the
phases for the compensation analysis and divide the total
capacitance by the number of phases. The resultant filter
consists of the phase output inductor and the equivalent phase
capacitance. Consider the 3-Phase example shown in Figure 27.
This schematic is drawn symmetrically with identical phase
filters; consider any one of the phases plus any common output
capacitance divided by the number of phases, in this case 3.
To obtain the tracking timing we get the following
t OnDly ( Ref ) = 15ms + 5ms + 5ms = 25ms
L1
L_esr_1
0.33uH 0.4m Cout10 Cout11 Cout12
(EQ. 9)
t OffDly ( Mem ) = 5ms + 5ms + 5ms + 15ms = 30ms
(EQ. 10)
ZL6105
ZL8101
Phase_1
The Tracking Timing is shown below in Table 14.
TABLE 14. TRACKING TIMING FOR FIGURE 26
RAIL #
VOUT tON_DLY tON_RISE tOFF_DLY tOFF_FALL
(v)
(ms)
(ms)
(ms)
(ms)
Rail_1
1.5
Tracking Reference
25
5
Rail_2
0.75
Sharing Reference
Tracking Member
15
5
Rail_2
0.75
Sharing Member
Tracking Member
5
5
30
Tracking
Disabled
5
Track at
100% VOUT
or V TRAK
Limited
5
Track at
100% VOUT
or V TRAK
Limited
All of the ENABLE pins must be connected together and driven by
a single logic source. If PMBus ENABLE is going to be used
ensure that the tracking and sharing devices are configured to be
in the same Broadcast Group with the DDC_CONFIG command.
Ensure that Broadcast Enable is active for each controller in the
tracking and sharing group, Broadcast Enable is part of the
MISC_CONFIG command.
C11
5X
100uF
C12
470uF
esr10
3.5m/3
esr11
2.5m/5
esr12
8m
esl10
3X
1nH
esl11
5X
1nH
esl12
6nH
20%
L2
L_esr_2
0.33uH 0.4m Cout20 Cout21 Cout22
MODE
5
C10
3X
47uF
ZL6105
ZL8101
Phase_2
C20
3X
47uF
C21
5X
100uF
esr20
3.5m/3
esr21
2.5m/5
esl20
3X
1nH
esl21
5X
1nH
VOUT
C22
470uF
esr22
8m
esl22
6nH
20%
GND
L3
0.33uH
ZL6105
ZL8101
Phase_3
L_esr_3
0.4m Cout30 Cout31 Cout32
C30
3X
47uF
esr30
3.5m/3
esl30
3X
1nH
C31
5X
100uF
esr31
2.5m/5
esl31
5X
1nH
C32
470uF
esr32
8m
esl32
6nH
20%
FIGURE 27. 3-PHASE CURRENT SHARING EXAMPLE
15
AN1779.1
December 23, 2013
Application Note 1779
The resultant 3-Phase compensation model reduces to the
configuration shown in Figure 28.
L_n
0.33uH
ZL6105
ZL8101
Phase_N
L_n_esr
0.4m
1V
C_n0
3X
47uF
C_n1
5X
100uF
esl_n1
5X
1nH
(EQ. 15)
POUT = VOUT ∗ I OUT
(EQ. 16)
C_n2
470uF
esr_n0 esr_n1 esr_n2
3.5m/3 2.5m/5
8m
esl_n0
3X
1nH
2
PLOUT = I LOUT
∗ RDCR
Iout
25A
esr_n2
6nH
20%
GND
2
I LOUT = I OUT
+
⎡ ⎛ VOUT ⎞
⎟×VOUT
⎢ ⎜⎜ 1−
V IN ⎟⎠
⎢⎝
⎢
LOUT × FSW
⎢
⎢⎣
⎤
⎥
⎥
⎥
⎥
⎥⎦
2
(EQ. 17)
12
Where:
FIGURE 28. CURRENT SHARING COMPENSATION MODEL (USING
COMPZL TO CALCULATE TAPS)
RDCR’ = Total resistive conversion loss minus CompZL calculated
losses
PIN = Total input power
Using CompAZL to Calculate Taps
PHI_Cond = High-side FET Conduction loss
In order to calculate accurate taps for the sharing group, all of
the conversion losses need to be identified and entered into the
CompZL power stage model. These losses include inductor AC
loss, routing loss, and FET switching loss.
PLO_Cond = Low-side FET Conduction loss
It is particularly important to identify and estimate these losses
with low impedance (hi Q) output filters. These previously
unaccounted losses in the CompZL program increase the filter
damping and usually enable the use of real zeros in the
compensator.
Real zeros can be strategically placed above and below the filter
resonant frequency and result in increased midband frequency
gain. Please reference AN2035 for additional information on
using CompZL.
Equations 11 through 17 can be used to estimate the conversion
losses that are not included in CompZL, including these losses in
the analysis increases circuit damping and the effectiveness of
using real zeros. Once the analysis is complete, simply substitute
the calculated value RDCR’ into the CompZL model for DCR.
’ is calculated by subtracting the losses known by CompZL
RDCR
from the total circuit losses. The total losses are known by
measuring, calculating, or estimating the conversion efficiency at
the operating point of interest. Once the efficiency is known,
these equations (Equations 11 through 17) can be used to obtain
the losses not considered in the CompZL program at the
operating point of interest.
'
DCR
R
=
PIN − PHI _ Cond − PLO _ Cond − PLOUT − POUT
2
I OUT
IOUT2 = Output current
RDS_LO = Low-Side FET rDS(ON)
RDS_HI = High-Side FET rDS(ON)
η = Converter efficiency
VIN = Converter input voltage
VOUT = Converter output voltage
IQC = Controller quiescent current
IOUT = Converter output current
ILOUT = Output inductor RMS current
Compensation Example
The 3-Phase converter shown in Figure 28 has the following
component values:
VOUT = 1.0V
VIN = 12V
IOUT = 25A/Phase
FSW = 615kHz/Phase
COUT_n0 = 3 X 47µF, 3.5mΩ, 1nH
(EQ. 11)
COUT_n1 = 5 X 100µF, 2.5mΩ, 6nH
COUT_n2 = 470µF, 8mΩ, 6nH
⎛P
⎞
PIN = ⎜⎜ OUT −V IN∗I QC ⎟⎟
⎝ η
⎠
(EQ. 12)
LOUT = 0.33µH
DCR = 0.4mΩ
2
PHI _ Cond = I OUT
∗ RDS _ HI ∗
VOUT
VIN
⎛ V
2
∗ RDS _ LO ∗ ⎜⎜1 − OUT
PLO _ Cond = I OUT
VIN
⎝
(
PLOUT = Output inductor DCR loss
)
16
(EQ. 13)
RDS_HI = 4mΩ
RDS_LO = 2mΩ
⎞
⎟⎟
⎠
ç = 85%
(EQ. 14)
IQC = 35mA
AN1779.1
December 23, 2013
Application Note 1779
The individual power losses are calculated in Equations 18
through 23. The losses already accounted for in CompZL are then
subtracted from the input power.
This new adjusted value yields a more accurate compensation
model and increases the filter dampening. As a result, the possibility
of using real zeros increases with low impedance output filters.
⎛ 1V ∗ 25 A
⎞
− 12V * 35mA ⎟ = 28.99W
PIN = ⎜
0
.
84
⎝
⎠
(EQ. 18)
Suggested Guidelines
1V
= 0.208W
12V
(EQ. 19)
PHI _ COND = 252 A ∗ 4mΩ ∗
1V ⎞
⎛
PLO _ COND = 25 2 A ∗ 2mΩ ∗ ⎜1 −
⎟ = 1.15W
⎝ 12V ⎠
(EQ. 20)
2
⎡ ⎛ 1V ⎞
⎤
⎢ ⎜1 − 12V ⎟ ∗1V ⎥
⎠
⎢ ⎝
⎥
0
.
33
uH
615
KHz⎥
∗
⎢
⎢
⎥⎦
I LOUT = 252 A + ⎣
= 25.03A
12
(EQ. 21)
PLOUT = 25.032 A * 0.4mΩ = 0.25W
(EQ. 22)
POUT = 1V * 25 A = 25W
(EQ. 23)
'
RDCR
=
29.34W − 0.204W − 1.145W − 0.25W − 25W
= 3.82 mΩ
25 2 A
(EQ. 24)
The adjusted value of R’DCR is 3.82mΩ. Type this value into the
CompZL location for the inductor DCR. This adjusted value now
contains all of the frequency dependent losses at the operating
point of interest, these losses were previously unaccounted for in
the CompZL model.
17
To ensure that the digital PID controller constrains internal noise
and minimizes PWM jitter, the low frequency gain Gc should be
constrained to 30dB if possible. Q should be initially set between
0.1 to 0.4. The compensator should be set to Overdamped (real
zeros). If the Q of the output filter is extremely low, (very small
parasitic resistance) an overdamped compensator will not be
possible. In that case switch to the underdamped mode.
The compensator natural frequency Fn is adjusted below the
calculated output filter natural frequency (see Equation 25), by
moving the zeros until the phase margin, gain margin, and
crossover criteria is met.
The compensation results are shown in Figure 29. the
compensator is set to overdamped (real zeros). The gain term
was set to initially 25dB, and Q was set to 0.35.
Fn =
1
2 * π * Lout * Cout
Fn =
1
= 8.31kHz
2 * π * 0.33uH *1111uF
(EQ. 25)
While moving each zero in turn, observe the actual phase and
gain margin values and ensure that the phase and gain margin
goals are met.
Notice how the gain levels off at approximately 2.5kHz. This is
due to the careful placement of the zeros and results in a
flattened midband gain characteristic with improved damping
and transient response.
Once the PID coefficients have been calculated, enter the same
values for each phase in their respective configuration files.
AN1779.1
December 23, 2013
Application Note 1779
FIGURE 29. USING COMPZL IN THE MANUAL MODE
Configuration Files
Once the hardware design is completed and verified, a
configuration file is created for each sharing group controller. The
configuration file is composed by using a text editor such as
Microsoft Notepad. Other editors can be used as long as the
filename has a .txt extension. The configuration file data can
utilize both decimal and hexadecimal data. Hexadecimal data is
always preceded by 0x. Comments can be added to the
configuration file if preceded with a # sign.
Consider the 3-phase sharing group shown in Figure 30. The
operating requirements are shown in Table 15.
Configuration files were composed for each phase and are
shown in Figure 31. Reference AN2031 “Writing Configuration
Files for Zilker” for additional information on composing
configuration files.
2.5V - 5.0V
VCC
DEV_1
0x20
REF.
POS_1
Rail_1
ISHARE Rail ID = 5
Rout
Cout
PH_1
DDC
SDA
SCL
SYNC
SYNC_Out
VCC
DEV_2
0x21
MEM_1
POS_2
PH_2
SYNC_In
VCC
DEV_3
0x22
MEM_2
POS_3
PH_3
SYNC_In
FIGURE 30. 3-PHASE SHARING GROUP EXAMPLE
18
AN1779.1
December 23, 2013
Application Note 1779
TABLE 15. 3-PHASE SHARING GROUP REQUIREMENTS
DEVICE
(PHASE)
PH_1Ref
ADDRESS (HEX)
Rail DDC ID
ISHARE Rail ID
SYNC
VIN
(V)
VOUT
(A)
IOUT
(A)
FSW (kHz)
0x20
0
5
Source
12
1.0V
25
615
PH_2Mem_1
0x21
1
5
Input
12
1.0V
25
615
PH_2Mem_2
0x22
2
5
Input
12
1.0V
25
615
Configuration File Checklist
Use the following checklist as a guideline when creating
configuration files for current sharing rails.
1. Follow memory restore guidelines
• RESTORE_FACTORY
• STORE_USER_ALL
• STORE_DEFAULT_ALL
• RESTORE_DEFAULT_ALL
• STORE_DEFAULT_ALL
• RESTORE_DEFAULT_ALL
2. Assign the same VOUT_DROOP value to all ZL devices in the
current sharing group with a value typically between 0.15Ω
and 1.0Ω.
3. Ensure that the Time On Delay and Time Off Delay
parameters for the reference phase are at least 10ms greater
than the delay parameters of each member device.
4. Ensure that each controller in the sharing group has equally
configured Time On/Off, Rise/Fall times. Assign the same
fault responses for each device.
5. Designate and configure the SYNC source for the group, if the
source is one of the group devices all other device(s) in the
group are configured as SYNC inputs.
6. Assign the same ISHARE Rail ID to each device in the group
using ISHARE_CONFIG.
19
7. Configure the High to Low and Low to High deadtimes to
Freeze using the DEADTIME_CONFIG command.
8. Ensure that each phase of the sharing group has been
calibrated for measuring current by using the IOUT_CAL_GAIN
and IOUT_CAL_OFFSET commands
9. Each sharing group controller has the same configured
switching frequency
10. Each sharing group controller has the same current limit
configuration.
11. Each sharing group controller has the same fault response
configuration.Assign a unique phase position to each group
device using ISHARE_CONFIG.
12. Configure Standby Mode to Monitor Enabled for each group
member.
13. Set the TEMPCO_CONFIG value for each group member to the
same value.
14. Assign the maximum duty cycle to each group device per
Equation 6.
15. Configure the Min Duty Cycle command to Enabled.
16. Configure SYNC Time-out EN to SYNC always On.
17. Diode Emulation, Adaptive Frequency Compensation is not
supported with current sharing and must be disabled.
AN1779.1
December 23, 2013
Application Note 1779
FIGURE 31. CONFIGURATION FILE FOR 3-PHASE CURRENT SHARING GROUP (REF_PHASE)
20
AN1779.1
December 23, 2013
Application Note 1779
FIGURE 32. CONFIGURATION FILE FOR 3-PHASE CURRENT SHARING GROUP (MEM_1)
21
AN1779.1
December 23, 2013
Application Note 1779
FIGURE 33. CONFIGURATION FILE FOR 3-PHASE CURRENT SHARING GROUP (MEM_2)
22
AN1779.1
December 23, 2013
Application Note 1779
Appendix
TABLE 17. ISHARE_CONFIG
TABLE 16. DDC RAIL ID# vs SMBus ADDRESS
PMBus Address
0x20
0x21
0x22
0x23
0x24
0x25
0x26
0x27
0x28
0x29
0x2A
0x2B
0x2C
0x2D
0x2E
0x2F
0x30
0x31
0x32
0x33
0x34
0x35
0x36
0x37
0x38
0x39
0x3A
0x3B
0x3C
0x3D
0x3E
0x3F
Binary
00100000
00100001
00100010
00100011
00100100
00100101
00100110
00100111
00101000
00101001
00101010
00101011
00101100
00101101
00101110
00101111
00110000
00110001
00110010
00110011
00110100
00110101
00110110
00110111
00111000
00111001
00111010
00111011
00111100
00111101
00111110
00111111
5 LSB's
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
10010
10011
10100
10101
10110
10111
11000
11001
11010
11011
11100
11101
11110
11111
Rail DDC ID
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
BITS PURPOSE VALUE
15:8
IShare
Rail ID
0
7:5
Number of
Devices
1
4:2
Device
Position
1
1
Reserved
0
0
Current
Share
Control
0
DESCRIPTION
Sets the current share rail’s DDC ID for each device
within a current share rail. Set to the same DDC ID
as in DDC_CONFIG. This DDC ID is used for
sequencing and fault spreading when used in a
current share rail.
Number of devices in current share rail -1
Position of device within current share rail
Reserved.
0 = Device is not a member of a current share rail
1 = Device is a member of a current share rail
Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is
cautioned to verify that the Application Note or Technical Brief is current before proceeding.
For information regarding Intersil Corporation and its products, see www.intersil.com
23
AN1779.1
December 23, 2013
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